AWfaw/ai-hdlcoder-dataset · Datasets at Hugging Face

repo_name stringlengths 6 79	path stringlengths 5 236	copies stringclasses 54 values	size stringlengths 1 8	content stringlengths 0 1.04M ⌀	license stringclasses 15 values
nickg/nvc	test/jit/proc1.vhd	1	1066	package proc1_pack0 is procedure add_n (x : inout integer; n : in integer); end package; package body proc1_pack0 is procedure add_n (x : inout integer; n : in integer) is begin if x = 10 then wait for 1 ns; else x := x + n; end if; end procedure; end package body; ------------------------------------------------------------------------------- package proc1_pack1 is procedure add1 (x : inout integer); end package; use work.proc1_pack0.all; package body proc1_pack1 is procedure add1 (x : inout integer) is begin add_n(x, 1); end procedure; end package body; ------------------------------------------------------------------------------- package proc1_pack2 is function add2 (x : integer) return integer; end package; use work.proc1_pack1.all; package body proc1_pack2 is function add2 (x : integer) return integer is variable r : integer := x; begin add1(r); add1(r); return r; end function; end package body;	gpl-3.0
nickg/nvc	test/regress/comp1.vhd	5	707	entity comp1_bot is port ( x : in integer; y : out integer ); end entity; architecture rtl of comp1_bot is begin y <= x + 1; end architecture; ------------------------------------------------------------------------------- entity comp1 is end entity; architecture rtl of comp1 is signal a, b : integer; component comp1_bot is port ( x : in integer; y : out integer ); end component; begin c1: component comp1_bot port map ( 1, a ); c2: comp1_bot port map ( 2, b ); process is begin wait for 1 ns; assert a = 2; assert b = 3; wait; end process; end architecture;	gpl-3.0
nickg/nvc	test/regress/bounds18.vhd	1	609	entity bounds18 is end entity; architecture test of bounds18 is function func(x : bit_vector(1 to 5)) return bit is begin return x(1) and x(5); end function; procedure proc(n : positive) is variable v : bit_vector(1 to n); begin assert func(v) = '0'; end procedure; begin process is variable v : bit_vector(1 to 4); begin --assert func(v) = '0'; -- Caught during analysis proc(5); -- OK proc(3); -- Failure here wait; end process; end architecture;	gpl-3.0
Darkin47/Zynq-TX-UTT	Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_register_s2mm.vhd	3	174357	-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_register_s2mm.vhd -- -- Description: This entity encompasses the channel register set. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_9; use axi_dma_v7_1_9.axi_dma_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_register_s2mm is generic( C_NUM_REGISTERS : integer := 11 ; C_INCLUDE_SG : integer := 1 ; C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ; C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ; C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ; C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ; C_MICRO_DMA : integer range 0 to 1 := 0 ; C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0 --C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034 ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- AXI Interface Control -- axi2ip_wrce : in std_logic_vector -- (C_NUM_REGISTERS-1 downto 0) ; -- axi2ip_wrdata : in std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- -- -- DMASR Control -- stop_dma : in std_logic ; -- halted_clr : in std_logic ; -- halted_set : in std_logic ; -- idle_set : in std_logic ; -- idle_clr : in std_logic ; -- ioc_irq_set : in std_logic ; -- dly_irq_set : in std_logic ; -- irqdelay_status : in std_logic_vector(7 downto 0) ; -- irqthresh_status : in std_logic_vector(7 downto 0) ; -- irqthresh_wren : out std_logic ; -- irqdelay_wren : out std_logic ; -- dlyirq_dsble : out std_logic ; -- CR605888 -- -- Error Control -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- ftch_interr_set : in std_logic ; -- ftch_slverr_set : in std_logic ; -- ftch_decerr_set : in std_logic ; -- ftch_error_addr : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_interr_set : in std_logic ; -- updt_slverr_set : in std_logic ; -- updt_decerr_set : in std_logic ; -- updt_error_addr : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- error_in : in std_logic ; -- error_out : out std_logic ; -- introut : out std_logic ; -- soft_reset_in : in std_logic ; -- soft_reset_clr : in std_logic ; -- -- -- CURDESC Update -- update_curdesc : in std_logic ; -- tdest_in : in std_logic_vector (5 downto 0) ; new_curdesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- -- TAILDESC Update -- tailpntr_updated : out std_logic ; -- -- -- Channel Register Out -- sg_ctl : out std_logic_vector (7 downto 0) ; dmacr : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- dmasr : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc1_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc1_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc1_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc1_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc2_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc2_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc2_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc2_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc3_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc3_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc3_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc3_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc4_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc4_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc4_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc4_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc5_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc5_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc5_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc5_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc6_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc6_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc6_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc6_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc7_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc7_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc7_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc7_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc8_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc8_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc8_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc8_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc9_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc9_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc9_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc9_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc10_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc10_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc10_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc10_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc11_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc11_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc11_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc11_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc12_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc12_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc12_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc12_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc13_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc13_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc13_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc13_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc14_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc14_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc14_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc14_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc15_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc15_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc15_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc15_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- buffer_address : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0); -- buffer_length : out std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- buffer_length_wren : out std_logic ; -- bytes_received : in std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- bytes_received_wren : in std_logic -- ); -- end axi_dma_register_s2mm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_register_s2mm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- constant SGCTL_INDEX : integer := 0; constant DMACR_INDEX : integer := 1; -- DMACR Register index constant DMASR_INDEX : integer := 2; -- DMASR Register index constant CURDESC_LSB_INDEX : integer := 3; -- CURDESC LSB Reg index constant CURDESC_MSB_INDEX : integer := 4; -- CURDESC MSB Reg index constant TAILDESC_LSB_INDEX : integer := 5; -- TAILDESC LSB Reg index constant TAILDESC_MSB_INDEX : integer := 6; -- TAILDESC MSB Reg index constant CURDESC1_LSB_INDEX : integer := 17; -- CURDESC LSB Reg index constant CURDESC1_MSB_INDEX : integer := 18; -- CURDESC MSB Reg index constant TAILDESC1_LSB_INDEX : integer := 19; -- TAILDESC LSB Reg index constant TAILDESC1_MSB_INDEX : integer := 20; -- TAILDESC MSB Reg index constant CURDESC2_LSB_INDEX : integer := 25; -- CURDESC LSB Reg index constant CURDESC2_MSB_INDEX : integer := 26; -- CURDESC MSB Reg index constant TAILDESC2_LSB_INDEX : integer := 27; -- TAILDESC LSB Reg index constant TAILDESC2_MSB_INDEX : integer := 28; -- TAILDESC MSB Reg index constant CURDESC3_LSB_INDEX : integer := 33; -- CURDESC LSB Reg index constant CURDESC3_MSB_INDEX : integer := 34; -- CURDESC MSB Reg index constant TAILDESC3_LSB_INDEX : integer := 35; -- TAILDESC LSB Reg index constant TAILDESC3_MSB_INDEX : integer := 36; -- TAILDESC MSB Reg index constant CURDESC4_LSB_INDEX : integer := 41; -- CURDESC LSB Reg index constant CURDESC4_MSB_INDEX : integer := 42; -- CURDESC MSB Reg index constant TAILDESC4_LSB_INDEX : integer := 43; -- TAILDESC LSB Reg index constant TAILDESC4_MSB_INDEX : integer := 44; -- TAILDESC MSB Reg index constant CURDESC5_LSB_INDEX : integer := 49; -- CURDESC LSB Reg index constant CURDESC5_MSB_INDEX : integer := 50; -- CURDESC MSB Reg index constant TAILDESC5_LSB_INDEX : integer := 51; -- TAILDESC LSB Reg index constant TAILDESC5_MSB_INDEX : integer := 52; -- TAILDESC MSB Reg index constant CURDESC6_LSB_INDEX : integer := 57; -- CURDESC LSB Reg index constant CURDESC6_MSB_INDEX : integer := 58; -- CURDESC MSB Reg index constant TAILDESC6_LSB_INDEX : integer := 59; -- TAILDESC LSB Reg index constant TAILDESC6_MSB_INDEX : integer := 60; -- TAILDESC MSB Reg index constant CURDESC7_LSB_INDEX : integer := 65; -- CURDESC LSB Reg index constant CURDESC7_MSB_INDEX : integer := 66; -- CURDESC MSB Reg index constant TAILDESC7_LSB_INDEX : integer := 67; -- TAILDESC LSB Reg index constant TAILDESC7_MSB_INDEX : integer := 68; -- TAILDESC MSB Reg index constant CURDESC8_LSB_INDEX : integer := 73; -- CURDESC LSB Reg index constant CURDESC8_MSB_INDEX : integer := 74; -- CURDESC MSB Reg index constant TAILDESC8_LSB_INDEX : integer := 75; -- TAILDESC LSB Reg index constant TAILDESC8_MSB_INDEX : integer := 76; -- TAILDESC MSB Reg index constant CURDESC9_LSB_INDEX : integer := 81; -- CURDESC LSB Reg index constant CURDESC9_MSB_INDEX : integer := 82; -- CURDESC MSB Reg index constant TAILDESC9_LSB_INDEX : integer := 83; -- TAILDESC LSB Reg index constant TAILDESC9_MSB_INDEX : integer := 84; -- TAILDESC MSB Reg index constant CURDESC10_LSB_INDEX : integer := 89; -- CURDESC LSB Reg index constant CURDESC10_MSB_INDEX : integer := 90; -- CURDESC MSB Reg index constant TAILDESC10_LSB_INDEX : integer := 91; -- TAILDESC LSB Reg index constant TAILDESC10_MSB_INDEX : integer := 92; -- TAILDESC MSB Reg index constant CURDESC11_LSB_INDEX : integer := 97; -- CURDESC LSB Reg index constant CURDESC11_MSB_INDEX : integer := 98; -- CURDESC MSB Reg index constant TAILDESC11_LSB_INDEX : integer := 99; -- TAILDESC LSB Reg index constant TAILDESC11_MSB_INDEX : integer := 100; -- TAILDESC MSB Reg index constant CURDESC12_LSB_INDEX : integer := 105; -- CURDESC LSB Reg index constant CURDESC12_MSB_INDEX : integer := 106; -- CURDESC MSB Reg index constant TAILDESC12_LSB_INDEX : integer := 107; -- TAILDESC LSB Reg index constant TAILDESC12_MSB_INDEX : integer := 108; -- TAILDESC MSB Reg index constant CURDESC13_LSB_INDEX : integer := 113; -- CURDESC LSB Reg index constant CURDESC13_MSB_INDEX : integer := 114; -- CURDESC MSB Reg index constant TAILDESC13_LSB_INDEX : integer := 115; -- TAILDESC LSB Reg index constant TAILDESC13_MSB_INDEX : integer := 116; -- TAILDESC MSB Reg index constant CURDESC14_LSB_INDEX : integer := 121; -- CURDESC LSB Reg index constant CURDESC14_MSB_INDEX : integer := 122; -- CURDESC MSB Reg index constant TAILDESC14_LSB_INDEX : integer := 123; -- TAILDESC LSB Reg index constant TAILDESC14_MSB_INDEX : integer := 124; -- TAILDESC MSB Reg index constant CURDESC15_LSB_INDEX : integer := 129; -- CURDESC LSB Reg index constant CURDESC15_MSB_INDEX : integer := 130; -- CURDESC MSB Reg index constant TAILDESC15_LSB_INDEX : integer := 131; -- TAILDESC LSB Reg index constant TAILDESC15_MSB_INDEX : integer := 132; -- TAILDESC MSB Reg index -- CR603034 moved s2mm back to offset 6 --constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA) --constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA) -- -- --constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA) -- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx -- SA_ADDRESS_INDEX, -- Source Address Index -- DA_ADDRESS_INDEX); -- Destination Address Index constant BUFF_ADDRESS_INDEX : integer := 7; constant BUFF_ADDRESS_MSB_INDEX : integer := 8; constant BUFF_LENGTH_INDEX : integer := 11; -- Buffer Length Reg constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0'); constant DMA_CONFIG : std_logic_vector(0 downto 0) := std_logic_vector(to_unsigned(C_INCLUDE_SG,1)); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal dmacr_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal dmasr_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0'); signal curdesc_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0'); signal taildesc_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal buffer_address_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal buffer_address_64_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal buffer_length_i : std_logic_vector (C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal curdesc1_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc1_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc1_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc1_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc2_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc2_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc2_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc2_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc3_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc3_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc3_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc3_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc4_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc4_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc4_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc4_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc5_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc5_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc5_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc5_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc6_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc6_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc6_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc6_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc7_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc7_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc7_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc7_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc8_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc8_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc8_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc8_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc9_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc9_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc9_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc9_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc10_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc10_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc10_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc10_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc11_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc11_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc11_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc11_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc12_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc12_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc12_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc12_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc13_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc13_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc13_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc13_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc14_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc14_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc14_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc14_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc15_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc15_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc15_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc15_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal update_curdesc1 : std_logic := '0'; signal update_curdesc2 : std_logic := '0'; signal update_curdesc3 : std_logic := '0'; signal update_curdesc4 : std_logic := '0'; signal update_curdesc5 : std_logic := '0'; signal update_curdesc6 : std_logic := '0'; signal update_curdesc7 : std_logic := '0'; signal update_curdesc8 : std_logic := '0'; signal update_curdesc9 : std_logic := '0'; signal update_curdesc10 : std_logic := '0'; signal update_curdesc11 : std_logic := '0'; signal update_curdesc12 : std_logic := '0'; signal update_curdesc13 : std_logic := '0'; signal update_curdesc14 : std_logic := '0'; signal update_curdesc15 : std_logic := '0'; signal dest0 : std_logic := '0'; signal dest1 : std_logic := '0'; signal dest2 : std_logic := '0'; signal dest3 : std_logic := '0'; signal dest4 : std_logic := '0'; signal dest5 : std_logic := '0'; signal dest6 : std_logic := '0'; signal dest7 : std_logic := '0'; signal dest8 : std_logic := '0'; signal dest9 : std_logic := '0'; signal dest10 : std_logic := '0'; signal dest11 : std_logic := '0'; signal dest12 : std_logic := '0'; signal dest13 : std_logic := '0'; signal dest14 : std_logic := '0'; signal dest15 : std_logic := '0'; -- DMASR Signals signal halted : std_logic := '0'; signal idle : std_logic := '0'; signal cmplt : std_logic := '0'; signal error : std_logic := '0'; signal dma_interr : std_logic := '0'; signal dma_slverr : std_logic := '0'; signal dma_decerr : std_logic := '0'; signal sg_interr : std_logic := '0'; signal sg_slverr : std_logic := '0'; signal sg_decerr : std_logic := '0'; signal ioc_irq : std_logic := '0'; signal dly_irq : std_logic := '0'; signal error_d1 : std_logic := '0'; signal error_re : std_logic := '0'; signal err_irq : std_logic := '0'; signal sg_ftch_error : std_logic := '0'; signal sg_updt_error : std_logic := '0'; signal error_pointer_set : std_logic := '0'; signal error_pointer_set1 : std_logic := '0'; signal error_pointer_set2 : std_logic := '0'; signal error_pointer_set3 : std_logic := '0'; signal error_pointer_set4 : std_logic := '0'; signal error_pointer_set5 : std_logic := '0'; signal error_pointer_set6 : std_logic := '0'; signal error_pointer_set7 : std_logic := '0'; signal error_pointer_set8 : std_logic := '0'; signal error_pointer_set9 : std_logic := '0'; signal error_pointer_set10 : std_logic := '0'; signal error_pointer_set11 : std_logic := '0'; signal error_pointer_set12 : std_logic := '0'; signal error_pointer_set13 : std_logic := '0'; signal error_pointer_set14 : std_logic := '0'; signal error_pointer_set15 : std_logic := '0'; -- interrupt coalescing support signals signal different_delay : std_logic := '0'; signal different_thresh : std_logic := '0'; signal threshold_is_zero : std_logic := '0'; -- soft reset support signals signal soft_reset_i : std_logic := '0'; signal run_stop_clr : std_logic := '0'; signal tail_update_lsb : std_logic := '0'; signal tail_update_msb : std_logic := '0'; signal sg_cache_info : std_logic_vector (7 downto 0); signal halt_free : std_logic := '0'; signal tmp11 : std_logic := '0'; signal sig_cur_updated : std_logic := '0'; signal tailpntr_updated_d1 : std_logic; signal tailpntr_updated_d2 : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin GEN_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate begin halt_free <= '1'; end generate GEN_MULTI_CH; GEN_NOMULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate begin halt_free <= dmasr_i(DMASR_HALTED_BIT); end generate GEN_NOMULTI_CH; GEN_DESC_UPDATE_FOR_SG : if C_NUM_S2MM_CHANNELS = 1 generate begin update_curdesc1 <= '0'; update_curdesc2 <= '0'; update_curdesc3 <= '0'; update_curdesc4 <= '0'; update_curdesc5 <= '0'; update_curdesc6 <= '0'; update_curdesc7 <= '0'; update_curdesc8 <= '0'; update_curdesc9 <= '0'; update_curdesc10 <= '0'; update_curdesc11 <= '0'; update_curdesc12 <= '0'; update_curdesc13 <= '0'; update_curdesc14 <= '0'; update_curdesc15 <= '0'; end generate GEN_DESC_UPDATE_FOR_SG; dest0 <= '1' when tdest_in (4 downto 0) = "00000" else '0'; dest1 <= '1' when tdest_in (4 downto 0) = "00001" else '0'; dest2 <= '1' when tdest_in (4 downto 0) = "00010" else '0'; dest3 <= '1' when tdest_in (4 downto 0) = "00011" else '0'; dest4 <= '1' when tdest_in (4 downto 0) = "00100" else '0'; dest5 <= '1' when tdest_in (4 downto 0) = "00101" else '0'; dest6 <= '1' when tdest_in (4 downto 0) = "00110" else '0'; dest7 <= '1' when tdest_in (4 downto 0) = "00111" else '0'; dest8 <= '1' when tdest_in (4 downto 0) = "01000" else '0'; dest9 <= '1' when tdest_in (4 downto 0) = "01001" else '0'; dest10 <= '1' when tdest_in (4 downto 0) = "01010" else '0'; dest11 <= '1' when tdest_in (4 downto 0) = "01011" else '0'; dest12 <= '1' when tdest_in (4 downto 0) = "01100" else '0'; dest13 <= '1' when tdest_in (4 downto 0) = "01101" else '0'; dest14 <= '1' when tdest_in (4 downto 0) = "01110" else '0'; dest15 <= '1' when tdest_in (4 downto 0) = "01111" else '0'; GEN_DESC_UPDATE_FOR_SG_CH : if C_NUM_S2MM_CHANNELS > 1 generate update_curdesc1 <= update_curdesc when tdest_in (4 downto 0) = "00001" else '0'; update_curdesc2 <= update_curdesc when tdest_in (4 downto 0) = "00010" else '0'; update_curdesc3 <= update_curdesc when tdest_in (4 downto 0) = "00011" else '0'; update_curdesc4 <= update_curdesc when tdest_in (4 downto 0) = "00100" else '0'; update_curdesc5 <= update_curdesc when tdest_in (4 downto 0) = "00101" else '0'; update_curdesc6 <= update_curdesc when tdest_in (4 downto 0) = "00110" else '0'; update_curdesc7 <= update_curdesc when tdest_in (4 downto 0) = "00111" else '0'; update_curdesc8 <= update_curdesc when tdest_in (4 downto 0) = "01000" else '0'; update_curdesc9 <= update_curdesc when tdest_in (4 downto 0) = "01001" else '0'; update_curdesc10 <= update_curdesc when tdest_in (4 downto 0) = "01010" else '0'; update_curdesc11 <= update_curdesc when tdest_in (4 downto 0) = "01011" else '0'; update_curdesc12 <= update_curdesc when tdest_in (4 downto 0) = "01100" else '0'; update_curdesc13 <= update_curdesc when tdest_in (4 downto 0) = "01101" else '0'; update_curdesc14 <= update_curdesc when tdest_in (4 downto 0) = "01110" else '0'; update_curdesc15 <= update_curdesc when tdest_in (4 downto 0) = "01111" else '0'; end generate GEN_DESC_UPDATE_FOR_SG_CH; GEN_DA_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate begin buffer_address <= buffer_address_64_i & buffer_address_i ; end generate GEN_DA_ADDR_EQL64; GEN_DA_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin buffer_address <= buffer_address_i ; end generate GEN_DA_ADDR_EQL32; dmacr <= dmacr_i ; dmasr <= dmasr_i ; curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ; curdesc_msb <= curdesc_msb_i ; taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ; taildesc_msb <= taildesc_msb_i ; buffer_length <= buffer_length_i ; curdesc1_lsb <= curdesc1_lsb_i ; curdesc1_msb <= curdesc1_msb_i ; taildesc1_lsb <= taildesc1_lsb_i ; taildesc1_msb <= taildesc1_msb_i ; curdesc2_lsb <= curdesc2_lsb_i ; curdesc2_msb <= curdesc2_msb_i ; taildesc2_lsb <= taildesc2_lsb_i ; taildesc2_msb <= taildesc2_msb_i ; curdesc3_lsb <= curdesc3_lsb_i ; curdesc3_msb <= curdesc3_msb_i ; taildesc3_lsb <= taildesc3_lsb_i ; taildesc3_msb <= taildesc3_msb_i ; curdesc4_lsb <= curdesc4_lsb_i ; curdesc4_msb <= curdesc4_msb_i ; taildesc4_lsb <= taildesc4_lsb_i ; taildesc4_msb <= taildesc4_msb_i ; curdesc5_lsb <= curdesc5_lsb_i ; curdesc5_msb <= curdesc5_msb_i ; taildesc5_lsb <= taildesc5_lsb_i ; taildesc5_msb <= taildesc5_msb_i ; curdesc6_lsb <= curdesc6_lsb_i ; curdesc6_msb <= curdesc6_msb_i ; taildesc6_lsb <= taildesc6_lsb_i ; taildesc6_msb <= taildesc6_msb_i ; curdesc7_lsb <= curdesc7_lsb_i ; curdesc7_msb <= curdesc7_msb_i ; taildesc7_lsb <= taildesc7_lsb_i ; taildesc7_msb <= taildesc7_msb_i ; curdesc8_lsb <= curdesc8_lsb_i ; curdesc8_msb <= curdesc8_msb_i ; taildesc8_lsb <= taildesc8_lsb_i ; taildesc8_msb <= taildesc8_msb_i ; curdesc9_lsb <= curdesc9_lsb_i ; curdesc9_msb <= curdesc9_msb_i ; taildesc9_lsb <= taildesc9_lsb_i ; taildesc9_msb <= taildesc9_msb_i ; curdesc10_lsb <= curdesc10_lsb_i ; curdesc10_msb <= curdesc10_msb_i ; taildesc10_lsb <= taildesc10_lsb_i ; taildesc10_msb <= taildesc10_msb_i ; curdesc11_lsb <= curdesc11_lsb_i ; curdesc11_msb <= curdesc11_msb_i ; taildesc11_lsb <= taildesc11_lsb_i ; taildesc11_msb <= taildesc11_msb_i ; curdesc12_lsb <= curdesc12_lsb_i ; curdesc12_msb <= curdesc12_msb_i ; taildesc12_lsb <= taildesc12_lsb_i ; taildesc12_msb <= taildesc12_msb_i ; curdesc13_lsb <= curdesc13_lsb_i ; curdesc13_msb <= curdesc13_msb_i ; taildesc13_lsb <= taildesc13_lsb_i ; taildesc13_msb <= taildesc13_msb_i ; curdesc14_lsb <= curdesc14_lsb_i ; curdesc14_msb <= curdesc14_msb_i ; taildesc14_lsb <= taildesc14_lsb_i ; taildesc14_msb <= taildesc14_msb_i ; curdesc15_lsb <= curdesc15_lsb_i ; curdesc15_msb <= curdesc15_msb_i ; taildesc15_lsb <= taildesc15_lsb_i ; taildesc15_msb <= taildesc15_msb_i ; --------------------------------------------------------------------------- -- DMA Control Register --------------------------------------------------------------------------- -- DMACR - Interrupt Delay Value ------------------------------------------------------------------------------- DMACR_DELAY : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0'); elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT); end if; end if; end process DMACR_DELAY; -- If written delay is different than previous value then assert write enable different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) /= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) else '0'; -- delay value different, drive write of delay value to interrupt controller NEW_DELAY_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then irqdelay_wren <= '0'; -- If AXI Lite write to DMACR and delay different than current -- setting then update delay value elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then irqdelay_wren <= '1'; else irqdelay_wren <= '0'; end if; end if; end process NEW_DELAY_WRITE; ------------------------------------------------------------------------------- -- DMACR - Interrupt Threshold Value ------------------------------------------------------------------------------- threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD else '0'; DMACR_THRESH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD; -- On AXI Lite write elsif(axi2ip_wrce(DMACR_INDEX) = '1')then -- If value is 0 then set threshold to 1 if(threshold_is_zero='1')then dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD; -- else set threshold to axi lite wrdata value else dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT); end if; end if; end if; end process DMACR_THRESH; -- If written threshold is different than previous value then assert write enable different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) /= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) else '0'; -- new treshold written therefore drive write of threshold out NEW_THRESH_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then irqthresh_wren <= '0'; -- If AXI Lite write to DMACR and threshold different than current -- setting then update threshold value elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then irqthresh_wren <= '1'; else irqthresh_wren <= '0'; end if; end if; end process NEW_THRESH_WRITE; ------------------------------------------------------------------------------- -- DMACR - Remainder of DMA Control Register, Key Hole write bit (3) ------------------------------------------------------------------------------- DMACR_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 downto DMACR_RESERVED5_BIT) <= (others => '0'); elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15 downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT) -- bit 14 & axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 13 & axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 12 & axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bits 11 downto 3 & ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT); end if; end if; end process DMACR_REGISTER; DMACR_REGISTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then dmacr_i(DMACR_KH_BIT) <= '0'; dmacr_i(CYCLIC_BIT) <= '0'; elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT); dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT); end if; end if; end process DMACR_REGISTER1; ------------------------------------------------------------------------------- -- DMACR - Reset Bit ------------------------------------------------------------------------------- DMACR_RESET : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(soft_reset_clr = '1')then dmacr_i(DMACR_RESET_BIT) <= '0'; -- If soft reset set in other channel then set -- reset bit here too elsif(soft_reset_in = '1')then dmacr_i(DMACR_RESET_BIT) <= '1'; -- If DMACR Write then pass axi lite write bus to DMARC reset bit elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT); end if; end if; end process DMACR_RESET; soft_reset_i <= dmacr_i(DMACR_RESET_BIT); ------------------------------------------------------------------------------- -- Tail Pointer Enable fixed at 1 for this release of axi dma ------------------------------------------------------------------------------- dmacr_i(DMACR_TAILPEN_BIT) <= '1'; ------------------------------------------------------------------------------- -- DMACR - Run/Stop Bit ------------------------------------------------------------------------------- run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error or error_in = '1' -- S2MM Error or stop_dma = '1' -- Stop due to error or soft_reset_i = '1' -- MM2S Soft Reset or soft_reset_in = '1' -- S2MM Soft Reset else '0'; DMACR_RUNSTOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_RS_BIT) <= '0'; -- Clear on sg error (i.e. error) or other channel -- error (i.e. error_in) or dma error or soft reset elsif(run_stop_clr = '1')then dmacr_i(DMACR_RS_BIT) <= '0'; elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT); end if; end if; end process DMACR_RUNSTOP; --------------------------------------------------------------------------- -- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA -- channel is halted. --------------------------------------------------------------------------- DMASR_HALTED : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or halted_set = '1')then halted <= '1'; elsif(halted_clr = '1')then halted <= '0'; end if; end if; end process DMASR_HALTED; --------------------------------------------------------------------------- -- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA -- channel is IDLE waiting at tail pointer. Update of Tail Pointer -- will cause engine to resume. Note: Halted channels return to a -- reset condition. --------------------------------------------------------------------------- DMASR_IDLE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or idle_clr = '1' or halted_set = '1')then idle <= '0'; elsif(idle_set = '1')then idle <= '1'; end if; end if; end process DMASR_IDLE; --------------------------------------------------------------------------- -- DMA Status Error bit (BIT 3) -- Note: any error will cause entire engine to halt --------------------------------------------------------------------------- error <= dma_interr or dma_slverr or dma_decerr or sg_interr or sg_slverr or sg_decerr; -- Scatter Gather Error --sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set; -- SG Update Errors or DMA errors assert flag on descriptor update -- Used to latch current descriptor pointer --sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set -- or dma_interr or dma_slverr or dma_decerr; -- Map out to halt opposing channel error_out <= error; SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_ftch_error <= '0'; sg_updt_error <= '0'; else sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set; sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set or dma_interr or dma_slverr or dma_decerr; end if; end if; end process SG_FTCH_ERROR_PROC; --------------------------------------------------------------------------- -- DMA Status DMA Internal Error bit (BIT 4) --------------------------------------------------------------------------- DMASR_DMAINTERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_interr <= '0'; elsif(dma_interr_set = '1' )then dma_interr <= '1'; end if; end if; end process DMASR_DMAINTERR; --------------------------------------------------------------------------- -- DMA Status DMA Slave Error bit (BIT 5) --------------------------------------------------------------------------- DMASR_DMASLVERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_slverr <= '0'; elsif(dma_slverr_set = '1' )then dma_slverr <= '1'; end if; end if; end process DMASR_DMASLVERR; --------------------------------------------------------------------------- -- DMA Status DMA Decode Error bit (BIT 6) --------------------------------------------------------------------------- DMASR_DMADECERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_decerr <= '0'; elsif(dma_decerr_set = '1' )then dma_decerr <= '1'; end if; end if; end process DMASR_DMADECERR; --------------------------------------------------------------------------- -- DMA Status SG Internal Error bit (BIT 8) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGINTERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_interr <= '0'; elsif(ftch_interr_set = '1' or updt_interr_set = '1')then sg_interr <= '1'; end if; end if; end process DMASR_SGINTERR; --------------------------------------------------------------------------- -- DMA Status SG Slave Error bit (BIT 9) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGSLVERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_slverr <= '0'; elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then sg_slverr <= '1'; end if; end if; end process DMASR_SGSLVERR; --------------------------------------------------------------------------- -- DMA Status SG Decode Error bit (BIT 10) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGDECERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_decerr <= '0'; elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then sg_decerr <= '1'; end if; end if; end process DMASR_SGDECERR; --------------------------------------------------------------------------- -- DMA Status IOC Interrupt status bit (BIT 11) --------------------------------------------------------------------------- DMASR_IOCIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then ioc_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT))) or ioc_irq_set; elsif(ioc_irq_set = '1')then ioc_irq <= '1'; end if; end if; end process DMASR_IOCIRQ; --------------------------------------------------------------------------- -- DMA Status Delay Interrupt status bit (BIT 12) --------------------------------------------------------------------------- DMASR_DLYIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dly_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT))) or dly_irq_set; elsif(dly_irq_set = '1')then dly_irq <= '1'; end if; end if; end process DMASR_DLYIRQ; -- CR605888 Disable delay timer if halted or on delay irq set --dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348 dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348 or dmasr_i(DMASR_DLYIRQ_BIT); --------------------------------------------------------------------------- -- DMA Status Error Interrupt status bit (BIT 12) --------------------------------------------------------------------------- -- Delay error setting for generation of error strobe GEN_ERROR_RE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then error_d1 <= '0'; else error_d1 <= error; end if; end if; end process GEN_ERROR_RE; -- Generate rising edge pulse on error error_re <= error and not error_d1; DMASR_ERRIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then err_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT))) or error_re; elsif(error_re = '1')then err_irq <= '1'; end if; end if; end process DMASR_ERRIRQ; --------------------------------------------------------------------------- -- DMA Interrupt OUT --------------------------------------------------------------------------- REG_INTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then introut <= '0'; else introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT)) or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT)) or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT)); end if; end if; end process; --------------------------------------------------------------------------- -- DMA Status Register --------------------------------------------------------------------------- dmasr_i <= irqdelay_status -- Bits 31 downto 24 & irqthresh_status -- Bits 23 downto 16 & '0' -- Bit 15 & err_irq -- Bit 14 & dly_irq -- Bit 13 & ioc_irq -- Bit 12 & '0' -- Bit 11 & sg_decerr -- Bit 10 & sg_slverr -- Bit 9 & sg_interr -- Bit 8 & '0' -- Bit 7 & dma_decerr -- Bit 6 & dma_slverr -- Bit 5 & dma_interr -- Bit 4 & DMA_CONFIG -- Bit 3 & '0' -- Bit 2 & idle -- Bit 1 & halted; -- Bit 0 -- Generate current descriptor and tail descriptor register for Scatter Gather Mode GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate begin GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate begin MM2S_SGCTL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_cache_info <= "00000011"; --(others => '0'); elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0); else sg_cache_info <= sg_cache_info; end if; end if; end process MM2S_SGCTL; sg_ctl <= sg_cache_info; end generate GEN_SG_CTL_REG; GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate begin sg_ctl <= "00000011"; --(others => '0'); end generate GEN_SG_NO_CTL_REG; -- Signals not used for Scatter Gather Mode, only simple mode buffer_address_i <= (others => '0'); buffer_length_i <= (others => '0'); buffer_length_wren <= '0'; --------------------------------------------------------------------------- -- Current Descriptor LSB Register --------------------------------------------------------------------------- CURDESC_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc_lsb_i <= (others => '0'); error_pointer_set <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6); error_pointer_set <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest0 = '1')then -- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6); error_pointer_set <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and halt_free = '1')then curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT); -- & ZERO_VALUE(CURDESC_RESERVED_BIT5 -- downto CURDESC_RESERVED_BIT0); error_pointer_set <= '0'; end if; end if; end if; end process CURDESC_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT); -- & ZERO_VALUE(TAILDESC_RESERVED_BIT5 -- downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC_LSB_REGISTER; GEN_DESC1_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate CURDESC1_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc1_lsb_i <= (others => '0'); error_pointer_set1 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set1 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then curdesc1_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set1 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest1 = '1')then -- curdesc1_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set1 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then curdesc1_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set1 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC1_LSB_INDEX) = '1' and halt_free = '1')then curdesc1_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set1 <= '0'; end if; end if; end if; end process CURDESC1_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC1_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc1_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC1_LSB_INDEX) = '1')then taildesc1_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC1_LSB_REGISTER; end generate GEN_DESC1_REG_FOR_SG; GEN_DESC2_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate CURDESC2_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc2_lsb_i <= (others => '0'); error_pointer_set2 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set2 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then curdesc2_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set2 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest2 = '1')then -- curdesc2_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set2 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then curdesc2_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set2 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC2_LSB_INDEX) = '1' and halt_free = '1')then curdesc2_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set2 <= '0'; end if; end if; end if; end process CURDESC2_LSB_REGISTER; TAILDESC2_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc2_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC2_LSB_INDEX) = '1')then taildesc2_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC2_LSB_REGISTER; end generate GEN_DESC2_REG_FOR_SG; GEN_DESC3_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate CURDESC3_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc3_lsb_i <= (others => '0'); error_pointer_set3 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set3 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then curdesc3_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set3 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest3 = '1')then -- curdesc3_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set3 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then curdesc3_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set3 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC3_LSB_INDEX) = '1' and halt_free = '1')then curdesc3_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set3 <= '0'; end if; end if; end if; end process CURDESC3_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC3_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc3_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC3_LSB_INDEX) = '1')then taildesc3_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC3_LSB_REGISTER; end generate GEN_DESC3_REG_FOR_SG; GEN_DESC4_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate CURDESC4_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc4_lsb_i <= (others => '0'); error_pointer_set4 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set4 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then curdesc4_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set4 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest4 = '1')then -- curdesc4_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set4 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then curdesc4_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set4 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC4_LSB_INDEX) = '1' and halt_free = '1')then curdesc4_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set4 <= '0'; end if; end if; end if; end process CURDESC4_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC4_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc4_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC4_LSB_INDEX) = '1')then taildesc4_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC4_LSB_REGISTER; end generate GEN_DESC4_REG_FOR_SG; GEN_DESC5_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate CURDESC5_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc5_lsb_i <= (others => '0'); error_pointer_set5 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set5 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then curdesc5_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set5 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest5 = '1')then -- curdesc5_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set5 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then curdesc5_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set5 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC5_LSB_INDEX) = '1' and halt_free = '1')then curdesc5_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set5 <= '0'; end if; end if; end if; end process CURDESC5_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC5_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc5_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC5_LSB_INDEX) = '1')then taildesc5_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC5_LSB_REGISTER; end generate GEN_DESC5_REG_FOR_SG; GEN_DESC6_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate CURDESC6_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc6_lsb_i <= (others => '0'); error_pointer_set6 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set6 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then curdesc6_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set6 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest6 = '1')then -- curdesc6_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set6 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then curdesc6_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set6 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC6_LSB_INDEX) = '1' and halt_free = '1')then curdesc6_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set6 <= '0'; end if; end if; end if; end process CURDESC6_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC6_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc6_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC6_LSB_INDEX) = '1')then taildesc6_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC6_LSB_REGISTER; end generate GEN_DESC6_REG_FOR_SG; GEN_DESC7_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate CURDESC7_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc7_lsb_i <= (others => '0'); error_pointer_set7 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set7 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then curdesc7_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set7 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest7 = '1')then -- curdesc7_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set7 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then curdesc7_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set7 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC7_LSB_INDEX) = '1' and halt_free = '1')then curdesc7_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set7 <= '0'; end if; end if; end if; end process CURDESC7_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC7_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc7_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC7_LSB_INDEX) = '1')then taildesc7_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC7_LSB_REGISTER; end generate GEN_DESC7_REG_FOR_SG; GEN_DESC8_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate CURDESC8_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc8_lsb_i <= (others => '0'); error_pointer_set8 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set8 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then curdesc8_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set8 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest8 = '1')then -- curdesc8_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set8 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then curdesc8_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set8 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC8_LSB_INDEX) = '1' and halt_free = '1')then curdesc8_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set8 <= '0'; end if; end if; end if; end process CURDESC8_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC8_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc8_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC8_LSB_INDEX) = '1')then taildesc8_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC8_LSB_REGISTER; end generate GEN_DESC8_REG_FOR_SG; GEN_DESC9_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate CURDESC9_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc9_lsb_i <= (others => '0'); error_pointer_set9 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set9 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then curdesc9_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set9 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest9 = '1')then -- curdesc9_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set9 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then curdesc9_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set9 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC9_LSB_INDEX) = '1' and halt_free = '1')then curdesc9_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set9 <= '0'; end if; end if; end if; end process CURDESC9_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC9_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc9_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC9_LSB_INDEX) = '1')then taildesc9_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC9_LSB_REGISTER; end generate GEN_DESC9_REG_FOR_SG; GEN_DESC10_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate CURDESC10_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc10_lsb_i <= (others => '0'); error_pointer_set10 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set10 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then curdesc10_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set10 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest10 = '1')then -- curdesc10_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set10 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then curdesc10_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set10 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC10_LSB_INDEX) = '1' and halt_free = '1')then curdesc10_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set10 <= '0'; end if; end if; end if; end process CURDESC10_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC10_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc10_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC10_LSB_INDEX) = '1')then taildesc10_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC10_LSB_REGISTER; end generate GEN_DESC10_REG_FOR_SG; GEN_DESC11_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate CURDESC11_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc11_lsb_i <= (others => '0'); error_pointer_set11 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set11 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then curdesc11_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set11 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest11 = '1')then -- curdesc11_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set11 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then curdesc11_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set11 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC11_LSB_INDEX) = '1' and halt_free = '1')then curdesc11_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set11 <= '0'; end if; end if; end if; end process CURDESC11_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC11_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc11_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC11_LSB_INDEX) = '1')then taildesc11_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC11_LSB_REGISTER; end generate GEN_DESC11_REG_FOR_SG; GEN_DESC12_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate CURDESC12_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc12_lsb_i <= (others => '0'); error_pointer_set12 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set12 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then curdesc12_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set12 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest12 = '1')then -- curdesc12_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set12 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then curdesc12_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set12 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC12_LSB_INDEX) = '1' and halt_free = '1')then curdesc12_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set12 <= '0'; end if; end if; end if; end process CURDESC12_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC12_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc12_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC12_LSB_INDEX) = '1')then taildesc12_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC12_LSB_REGISTER; end generate GEN_DESC12_REG_FOR_SG; GEN_DESC13_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate CURDESC13_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc13_lsb_i <= (others => '0'); error_pointer_set13 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set13 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then curdesc13_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set13 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest13 = '1')then -- curdesc13_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set13 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then curdesc13_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set13 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC13_LSB_INDEX) = '1' and halt_free = '1')then curdesc13_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set13 <= '0'; end if; end if; end if; end process CURDESC13_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC13_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc13_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC13_LSB_INDEX) = '1')then taildesc13_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC13_LSB_REGISTER; end generate GEN_DESC13_REG_FOR_SG; GEN_DESC14_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate CURDESC14_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc14_lsb_i <= (others => '0'); error_pointer_set14 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set14 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then curdesc14_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set14 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest14 = '1')then -- curdesc14_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set14 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then curdesc14_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set14 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC14_LSB_INDEX) = '1' and halt_free = '1')then curdesc14_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set14 <= '0'; end if; end if; end if; end process CURDESC14_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC14_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc14_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC14_LSB_INDEX) = '1')then taildesc14_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC14_LSB_REGISTER; end generate GEN_DESC14_REG_FOR_SG; GEN_DESC15_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate CURDESC15_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc15_lsb_i <= (others => '0'); error_pointer_set15 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set15 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then curdesc15_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set15 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest15 = '1')then -- curdesc15_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set15 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then curdesc15_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set15 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC15_LSB_INDEX) = '1' and halt_free = '1')then curdesc15_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set15 <= '0'; end if; end if; end if; end process CURDESC15_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC15_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc15_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC15_LSB_INDEX) = '1')then taildesc15_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC15_LSB_REGISTER; end generate GEN_DESC15_REG_FOR_SG; --------------------------------------------------------------------------- -- Current Descriptor MSB Register --------------------------------------------------------------------------- -- Scatter Gather Interface configured for 64-Bit SG Addresses GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin CURDESC_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc_msb_i <= (others => '0'); elsif(error_pointer_set = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then curdesc_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error elsif(sg_updt_error = '1' and dest0 = '1')then curdesc_msb_i <= updt_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then curdesc_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and halt_free = '1')then curdesc_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then taildesc_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC_MSB_REGISTER; GEN_DESC1_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate CURDESC1_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc1_msb_i <= (others => '0'); elsif(error_pointer_set1 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then curdesc1_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest1 = '1')then -- curdesc1_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then curdesc1_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC1_MSB_INDEX) = '1' and halt_free = '1')then curdesc1_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC1_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC1_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc1_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC1_MSB_INDEX) = '1')then taildesc1_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC1_MSB_REGISTER; end generate GEN_DESC1_MSB_FOR_SG; GEN_DESC2_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate CURDESC2_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc2_msb_i <= (others => '0'); elsif(error_pointer_set2 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then curdesc2_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest2 = '1')then -- curdesc2_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then curdesc2_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC2_MSB_INDEX) = '1' and halt_free = '1')then curdesc2_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC2_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC2_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc2_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC2_MSB_INDEX) = '1')then taildesc2_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC2_MSB_REGISTER; end generate GEN_DESC2_MSB_FOR_SG; GEN_DESC3_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate CURDESC3_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc3_msb_i <= (others => '0'); elsif(error_pointer_set3 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then curdesc3_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest3 = '1')then -- curdesc3_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then curdesc3_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC3_MSB_INDEX) = '1' and halt_free = '1')then curdesc3_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC3_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC3_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc3_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC3_MSB_INDEX) = '1')then taildesc3_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC3_MSB_REGISTER; end generate GEN_DESC3_MSB_FOR_SG; GEN_DESC4_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate CURDESC4_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc4_msb_i <= (others => '0'); elsif(error_pointer_set4 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then curdesc4_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest4 = '1')then -- curdesc4_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then curdesc4_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC4_MSB_INDEX) = '1' and halt_free = '1')then curdesc4_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC4_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC4_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc4_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC4_MSB_INDEX) = '1')then taildesc4_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC4_MSB_REGISTER; end generate GEN_DESC4_MSB_FOR_SG; GEN_DESC5_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate CURDESC5_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc5_msb_i <= (others => '0'); elsif(error_pointer_set5 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then curdesc5_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest5 = '1')then -- curdesc5_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then curdesc5_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC5_MSB_INDEX) = '1' and halt_free = '1')then curdesc5_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC5_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC5_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc5_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC5_MSB_INDEX) = '1')then taildesc5_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC5_MSB_REGISTER; end generate GEN_DESC5_MSB_FOR_SG; GEN_DESC6_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate CURDESC6_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc6_msb_i <= (others => '0'); elsif(error_pointer_set6 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then curdesc6_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest6 = '1')then -- curdesc6_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then curdesc6_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC6_MSB_INDEX) = '1' and halt_free = '1')then curdesc6_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC6_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC6_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc6_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC6_MSB_INDEX) = '1')then taildesc6_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC6_MSB_REGISTER; end generate GEN_DESC6_MSB_FOR_SG; GEN_DESC7_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate CURDESC7_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc7_msb_i <= (others => '0'); elsif(error_pointer_set7 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then curdesc7_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest7 = '1')then -- curdesc7_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then curdesc7_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC7_MSB_INDEX) = '1' and halt_free = '1')then curdesc7_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC7_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC7_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc7_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC7_MSB_INDEX) = '1')then taildesc7_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC7_MSB_REGISTER; end generate GEN_DESC7_MSB_FOR_SG; GEN_DESC8_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate CURDESC8_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc8_msb_i <= (others => '0'); elsif(error_pointer_set8 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then curdesc8_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest8 = '1')then -- curdesc8_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then curdesc8_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC8_MSB_INDEX) = '1' and halt_free = '1')then curdesc8_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC8_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC8_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc8_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC8_MSB_INDEX) = '1')then taildesc8_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC8_MSB_REGISTER; end generate GEN_DESC8_MSB_FOR_SG; GEN_DESC9_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate CURDESC9_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc9_msb_i <= (others => '0'); elsif(error_pointer_set9 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then curdesc9_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest9 = '1')then -- curdesc9_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then curdesc9_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC9_MSB_INDEX) = '1' and halt_free = '1')then curdesc9_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC9_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC9_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc9_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC9_MSB_INDEX) = '1')then taildesc9_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC9_MSB_REGISTER; end generate GEN_DESC9_MSB_FOR_SG; GEN_DESC10_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate CURDESC10_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc10_msb_i <= (others => '0'); elsif(error_pointer_set10 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then curdesc10_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest10 = '1')then -- curdesc10_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then curdesc10_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC10_MSB_INDEX) = '1' and halt_free = '1')then curdesc10_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC10_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC10_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc10_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC10_MSB_INDEX) = '1')then taildesc10_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC10_MSB_REGISTER; end generate GEN_DESC10_MSB_FOR_SG; GEN_DESC11_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate CURDESC11_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc11_msb_i <= (others => '0'); elsif(error_pointer_set11 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then curdesc11_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest11 = '1')then -- curdesc11_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then curdesc11_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC11_MSB_INDEX) = '1' and halt_free = '1')then curdesc11_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC11_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC11_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc11_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC11_MSB_INDEX) = '1')then taildesc11_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC11_MSB_REGISTER; end generate GEN_DESC11_MSB_FOR_SG; GEN_DESC12_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate CURDESC12_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc12_msb_i <= (others => '0'); elsif(error_pointer_set12 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then curdesc12_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest12 = '1')then -- curdesc12_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then curdesc12_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC12_MSB_INDEX) = '1' and halt_free = '1')then curdesc12_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC12_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC12_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc12_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC12_MSB_INDEX) = '1')then taildesc12_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC12_MSB_REGISTER; end generate GEN_DESC12_MSB_FOR_SG; GEN_DESC13_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate CURDESC13_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc13_msb_i <= (others => '0'); elsif(error_pointer_set13 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then curdesc13_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest13 = '1')then -- curdesc13_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then curdesc13_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC13_MSB_INDEX) = '1' and halt_free = '1')then curdesc13_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC13_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC13_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc13_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC13_MSB_INDEX) = '1')then taildesc13_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC13_MSB_REGISTER; end generate GEN_DESC13_MSB_FOR_SG; GEN_DESC14_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate CURDESC14_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc14_msb_i <= (others => '0'); elsif(error_pointer_set14 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then curdesc14_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest14 = '1')then -- curdesc14_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then curdesc14_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC14_MSB_INDEX) = '1' and halt_free = '1')then curdesc14_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC14_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC14_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc14_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC14_MSB_INDEX) = '1')then taildesc14_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC14_MSB_REGISTER; end generate GEN_DESC14_MSB_FOR_SG; GEN_DESC15_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate CURDESC15_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc15_msb_i <= (others => '0'); elsif(error_pointer_set15 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then curdesc15_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest15 = '1')then -- curdesc15_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then curdesc15_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC15_MSB_INDEX) = '1' and halt_free = '1')then curdesc15_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC15_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC15_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc15_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC15_MSB_INDEX) = '1')then taildesc15_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC15_MSB_REGISTER; end generate GEN_DESC15_MSB_FOR_SG; end generate GEN_SG_ADDR_EQL64; -- Scatter Gather Interface configured for 32-Bit SG Addresses GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin curdesc_msb_i <= (others => '0'); taildesc_msb_i <= (others => '0'); -- Extending this to the extra registers curdesc1_msb_i <= (others => '0'); taildesc1_msb_i <= (others => '0'); curdesc2_msb_i <= (others => '0'); taildesc2_msb_i <= (others => '0'); curdesc3_msb_i <= (others => '0'); taildesc3_msb_i <= (others => '0'); curdesc4_msb_i <= (others => '0'); taildesc4_msb_i <= (others => '0'); curdesc5_msb_i <= (others => '0'); taildesc5_msb_i <= (others => '0'); curdesc6_msb_i <= (others => '0'); taildesc6_msb_i <= (others => '0'); curdesc7_msb_i <= (others => '0'); taildesc7_msb_i <= (others => '0'); curdesc8_msb_i <= (others => '0'); taildesc8_msb_i <= (others => '0'); curdesc9_msb_i <= (others => '0'); taildesc9_msb_i <= (others => '0'); curdesc10_msb_i <= (others => '0'); taildesc10_msb_i <= (others => '0'); curdesc11_msb_i <= (others => '0'); taildesc11_msb_i <= (others => '0'); curdesc12_msb_i <= (others => '0'); taildesc12_msb_i <= (others => '0'); curdesc13_msb_i <= (others => '0'); taildesc13_msb_i <= (others => '0'); curdesc14_msb_i <= (others => '0'); taildesc14_msb_i <= (others => '0'); curdesc15_msb_i <= (others => '0'); taildesc15_msb_i <= (others => '0'); end generate GEN_SG_ADDR_EQL32; -- Scatter Gather Interface configured for 32-Bit SG Addresses GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin -- Added dest so that BD can be dynamically updated GENERATE_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0) or (axi2ip_wrce(TAILDESC1_LSB_INDEX) and dest1) or (axi2ip_wrce(TAILDESC2_LSB_INDEX) and dest2) or (axi2ip_wrce(TAILDESC3_LSB_INDEX) and dest3) or (axi2ip_wrce(TAILDESC4_LSB_INDEX) and dest4) or (axi2ip_wrce(TAILDESC5_LSB_INDEX) and dest5) or (axi2ip_wrce(TAILDESC6_LSB_INDEX) and dest6) or (axi2ip_wrce(TAILDESC7_LSB_INDEX) and dest7) or (axi2ip_wrce(TAILDESC8_LSB_INDEX) and dest8) or (axi2ip_wrce(TAILDESC9_LSB_INDEX) and dest9) or (axi2ip_wrce(TAILDESC10_LSB_INDEX) and dest10) or (axi2ip_wrce(TAILDESC11_LSB_INDEX) and dest11) or (axi2ip_wrce(TAILDESC12_LSB_INDEX) and dest12) or (axi2ip_wrce(TAILDESC13_LSB_INDEX) and dest13) or (axi2ip_wrce(TAILDESC14_LSB_INDEX) and dest14) or (axi2ip_wrce(TAILDESC15_LSB_INDEX) and dest15); end generate GENERATE_MULTI_CH; GENERATE_NO_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0); end generate GENERATE_NO_MULTI_CH; TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then tailpntr_updated_d1 <= '0'; elsif (tail_update_lsb = '1' and tdest_in(5) = '0')then tailpntr_updated_d1 <= '1'; else tailpntr_updated_d1 <= '0'; end if; end if; end process TAILPNTR_UPDT_PROCESS; TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tailpntr_updated_d2 <= '0'; else tailpntr_updated_d2 <= tailpntr_updated_d1; end if; end if; end process TAILPNTR_UPDT_PROCESS_DEL; tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2); end generate GEN_TAILUPDATE_EQL32; -- Scatter Gather Interface configured for 64-Bit SG Addresses GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin -- Added dest so that BD can be dynamically updated GENERATE_NO_MULTI_CH1 : if C_ENABLE_MULTI_CHANNEL = 1 generate tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0) or (axi2ip_wrce(TAILDESC1_MSB_INDEX) and dest1) or (axi2ip_wrce(TAILDESC2_MSB_INDEX) and dest2) or (axi2ip_wrce(TAILDESC3_MSB_INDEX) and dest3) or (axi2ip_wrce(TAILDESC4_MSB_INDEX) and dest4) or (axi2ip_wrce(TAILDESC5_MSB_INDEX) and dest5) or (axi2ip_wrce(TAILDESC6_MSB_INDEX) and dest6) or (axi2ip_wrce(TAILDESC7_MSB_INDEX) and dest7) or (axi2ip_wrce(TAILDESC8_MSB_INDEX) and dest8) or (axi2ip_wrce(TAILDESC9_MSB_INDEX) and dest9) or (axi2ip_wrce(TAILDESC10_MSB_INDEX) and dest10) or (axi2ip_wrce(TAILDESC11_MSB_INDEX) and dest11) or (axi2ip_wrce(TAILDESC12_MSB_INDEX) and dest12) or (axi2ip_wrce(TAILDESC13_MSB_INDEX) and dest13) or (axi2ip_wrce(TAILDESC14_MSB_INDEX) and dest14) or (axi2ip_wrce(TAILDESC15_MSB_INDEX) and dest15); end generate GENERATE_NO_MULTI_CH1; GENERATE_NO_MULTI_CH2 : if C_ENABLE_MULTI_CHANNEL = 0 generate tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0); end generate GENERATE_NO_MULTI_CH2; TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then tailpntr_updated_d1 <= '0'; elsif (tail_update_msb = '1' and tdest_in(5) = '0')then tailpntr_updated_d1 <= '1'; else tailpntr_updated_d1 <= '0'; end if; end if; end process TAILPNTR_UPDT_PROCESS; TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tailpntr_updated_d2 <= '0'; else tailpntr_updated_d2 <= tailpntr_updated_d1; end if; end if; end process TAILPNTR_UPDT_PROCESS_DEL; tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2); end generate GEN_TAILUPDATE_EQL64; end generate GEN_DESC_REG_FOR_SG; -- Generate Buffer Address and Length Register for Simple DMA Mode GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate begin -- Signals not used for simple dma mode, only for sg mode curdesc_lsb_i <= (others => '0'); curdesc_msb_i <= (others => '0'); taildesc_lsb_i <= (others => '0'); taildesc_msb_i <= (others => '0'); -- Extending this to new registers curdesc1_msb_i <= (others => '0'); taildesc1_msb_i <= (others => '0'); curdesc2_msb_i <= (others => '0'); taildesc2_msb_i <= (others => '0'); curdesc3_msb_i <= (others => '0'); taildesc3_msb_i <= (others => '0'); curdesc4_msb_i <= (others => '0'); taildesc4_msb_i <= (others => '0'); curdesc5_msb_i <= (others => '0'); taildesc5_msb_i <= (others => '0'); curdesc6_msb_i <= (others => '0'); taildesc6_msb_i <= (others => '0'); curdesc7_msb_i <= (others => '0'); taildesc7_msb_i <= (others => '0'); curdesc8_msb_i <= (others => '0'); taildesc8_msb_i <= (others => '0'); curdesc9_msb_i <= (others => '0'); taildesc9_msb_i <= (others => '0'); curdesc10_msb_i <= (others => '0'); taildesc10_msb_i <= (others => '0'); curdesc11_msb_i <= (others => '0'); taildesc11_msb_i <= (others => '0'); curdesc12_msb_i <= (others => '0'); taildesc12_msb_i <= (others => '0'); curdesc13_msb_i <= (others => '0'); taildesc13_msb_i <= (others => '0'); curdesc14_msb_i <= (others => '0'); taildesc14_msb_i <= (others => '0'); curdesc15_msb_i <= (others => '0'); taildesc15_msb_i <= (others => '0'); curdesc1_lsb_i <= (others => '0'); taildesc1_lsb_i <= (others => '0'); curdesc2_lsb_i <= (others => '0'); taildesc2_lsb_i <= (others => '0'); curdesc3_lsb_i <= (others => '0'); taildesc3_lsb_i <= (others => '0'); curdesc4_lsb_i <= (others => '0'); taildesc4_lsb_i <= (others => '0'); curdesc5_lsb_i <= (others => '0'); taildesc5_lsb_i <= (others => '0'); curdesc6_lsb_i <= (others => '0'); taildesc6_lsb_i <= (others => '0'); curdesc7_lsb_i <= (others => '0'); taildesc7_lsb_i <= (others => '0'); curdesc8_lsb_i <= (others => '0'); taildesc8_lsb_i <= (others => '0'); curdesc9_lsb_i <= (others => '0'); taildesc9_lsb_i <= (others => '0'); curdesc10_lsb_i <= (others => '0'); taildesc10_lsb_i <= (others => '0'); curdesc11_lsb_i <= (others => '0'); taildesc11_lsb_i <= (others => '0'); curdesc12_lsb_i <= (others => '0'); taildesc12_lsb_i <= (others => '0'); curdesc13_lsb_i <= (others => '0'); taildesc13_lsb_i <= (others => '0'); curdesc14_lsb_i <= (others => '0'); taildesc14_lsb_i <= (others => '0'); curdesc15_lsb_i <= (others => '0'); taildesc15_lsb_i <= (others => '0'); tailpntr_updated <= '0'; error_pointer_set <= '0'; -- Buffer Address register. Used for Source Address (SA) if MM2S -- and used for Destination Address (DA) if S2MM BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_address_i <= (others => '0'); elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then buffer_address_i <= axi2ip_wrdata; end if; end if; end process BUFFER_ADDR_REGISTER; GEN_BUF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate begin BUFFER_ADDR_REGISTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_address_64_i <= (others => '0'); elsif(axi2ip_wrce(BUFF_ADDRESS_MSB_INDEX) = '1')then buffer_address_64_i <= axi2ip_wrdata; end if; end if; end process BUFFER_ADDR_REGISTER1; end generate GEN_BUF_ADDR_EQL64; -- Buffer Length register. Used for number of bytes to transfer if MM2S -- and used for size of receive buffer is S2MM BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_length_i <= (others => '0'); -- Update with actual bytes received (Only for S2MM channel) elsif(bytes_received_wren = '1' and C_MICRO_DMA = 0)then buffer_length_i <= bytes_received; elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0); end if; end if; end process BUFFER_LNGTH_REGISTER; -- Buffer Length Write Enable control. Assertion of wren will -- begin a transfer if channel is Idle. BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_length_wren <= '0'; -- Non-zero length value written elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1' and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then buffer_length_wren <= '1'; else buffer_length_wren <= '0'; end if; end if; end process BUFFER_LNGTH_WRITE; end generate GEN_REG_FOR_SMPL; end implementation;	gpl-3.0
nickg/nvc	test/bounds/bounds2.vhd	1	3770	entity bounds2 is end entity; architecture test of bounds2 is begin asssignment_delays: block signal b1,b2,b3,b4,b5,b6,b7 : boolean; begin b1 <= true; -- OK b2 <= true after 10 ns; -- OK b3 <= true after 0 ns; -- OK b4 <= true after -1 ns; -- Error process begin b5 <= true; -- OK b5 <= true after 0 ns; -- OK b5 <= true after 1 fs; -- OK b5 <= true after -1 fs; -- Error wait; end process; b6 <= true after -10 ns when now = 5 ns else false; b7 <= true when now = 1 ns else false after -10 ns; end block; rejection_limits: block signal b1,b2,b3 : boolean; begin b1 <= reject 10 ns inertial true after 10 ns; -- OK b2 <= reject -10 ns inertial true; -- Error b3 <= reject 10 ns inertial true after 5 ns; -- Error end block; process begin wait for -10 ns; -- Error wait; end process; default_values: block type r is range 0 to 1; constant ok1 : integer range 0 to 1 := 1; -- OK constant ok2 : character range 'a' to 'z' := 'b'; -- OK constant ok3 : real range 0.0 to 1.0 := 0.0; -- OK constant ok4 : time range 10 ns to 20 ns := 10 ns; -- OK constant ok5 : r := 0; -- OK signal s : integer range 0 to 9 := 20; -- Error constant c1 : character range 'a' to 'z' := 'Z'; -- Error shared variable v : real range 0.0 to 5.0 := 10.0; -- Error constant t : time range 10 ns to 10 us := 0 fs; -- Error constant c2 : r := 10; -- Error subtype subint is integer range 1 to 10; procedure test(a : subint := 30) is begin end procedure; function test(a : character range 'a' to 'b' := 'c') return integer is begin return 1; end function; component comp is generic ( g2 : integer range 10 downto 0 := 20 ); port ( p2 : in integer range 0 to 1 := 2 ); end component; begin process is variable v2 : real range 0.0 to 5.0 := 5.1; -- Error begin end process; end block; ascending_time: block signal s : integer; signal del : time; begin process begin s <= 0 after 10 ns, 1 after 11 ns; -- OK s <= 0, 1 after 1 ns; -- OK s <= 10 after del; -- OK s <= 10 after del, 20 after del + 1 ns; -- OK s <= 0, 1; -- Error s <= 0 after 1 ns, 1; -- Error s <= 0 after 2 ns, 1 after 1 ns; -- Error s <= 0 after 1 ns, 1 after del, 2; -- Error s <= 1 after del, 2; -- Error wait; end process; end block; textio1: block is function unit_string (unit : time) return string is begin if unit = fs then -- OK return " fs"; elsif unit = ps then return " ps"; elsif unit = ns then return " ns"; else report "invalid unit " & time'image(unit); end if; end function; begin end block; end architecture;	gpl-3.0
nickg/nvc	test/regress/implicit3.vhd	5	675	entity sub is port ( x : in integer; y : out boolean ); end entity; architecture test of sub is begin y <= x'delayed(5 ns) > x; end architecture; ------------------------------------------------------------------------------- entity implicit3 is end entity; architecture test of implicit3 is signal x : integer := 0; signal y : boolean; begin sub_i: entity work.sub port map (x, y); process is begin x <= 1; wait for 1 ns; assert not y; wait for 5 ns; assert not y; x <= -1; wait for 5 ns; assert y; wait; end process; end architecture;	gpl-3.0
nickg/nvc	test/regress/func21.vhd	1	489	entity func21 is end entity; architecture test of func21 is type rec is record x, y : integer; end record; function func (r : rec) return integer is begin return r.x + r.y; end function; begin p1: process is variable a, b : integer; begin assert func(r.x => 1, r.y => 2) = 3; a := 4; b := 5; wait for 1 ns; assert func(r.x => a, r.y => b) = 9; wait; end process; end architecture;	gpl-3.0
Darkin47/Zynq-TX-UTT	Vivado_HLS/image_histogram/solution1/sim/vhdl/AESL_sim_pkg.vhd	2	8773	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2016.1 -- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== -- synthesis translate_off library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; use std.textio.all; --library work; --use work.AESL_components.all; package AESL_sim_components is -- simulation routines procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER); procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING); procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR; variable RHS : in STRING); procedure esl_assign_l (signal LHS : out STD_LOGIC; variable RHS : in STRING); procedure esl_compare_l (signal LHS: in STD_LOGIC; variable RHS: in STRING; variable dontcare: in BOOLEAN; variable isok: out BOOLEAN); procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR; variable RHS: in STRING; variable dontcare: in BOOLEAN; variable isok: out BOOLEAN); function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING; function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING; function esl_conv_lv (str : string; base : integer; len : integer) return STD_LOGIC_VECTOR; end package; package body AESL_sim_components is --simulation routines procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is variable whitespace : CHARACTER; variable i : INTEGER; variable ok: BOOLEAN; variable buff: STRING(1 to token'length); begin ok := false; i := 1; loop_main: while not endfile(textfile) loop if textline = null or textline'length = 0 then readline(textfile, textline); end if; loop_remove_whitespace: while textline'length > 0 loop if textline(textline'left) = ' ' or textline(textline'left) = HT or textline(textline'left) = CR or textline(textline'left) = LF then read(textline, whitespace); else exit loop_remove_whitespace; end if; end loop; loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop if textline(textline'left) = ' ' or textline(textline'left) = HT or textline(textline'left) = CR or textline(textline'left) = LF then exit loop_aesl_read_token; else read(textline, buff(i)); i := i + 1; end if; ok := true; end loop; if ok = true then exit loop_main; end if; end loop; buff(i) := ' '; token := buff; token_len:= i-1; end procedure esl_read_token; procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING) is variable i : INTEGER; begin esl_read_token (textfile, textline, token, i); end procedure esl_read_token; procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR; variable RHS : in STRING) is variable i : INTEGER; variable bitwidth : INTEGER; begin bitwidth := LHS'length; for i in 1 to bitwidth loop if RHS(i) = '1' then LHS(bitwidth - i) <= '1'; elsif RHS(i) = '0' then LHS(bitwidth - i) <= '0'; else LHS(bitwidth - i) <= 'X'; end if; end loop; end procedure; procedure esl_assign_l (signal LHS : out STD_LOGIC; variable RHS : in STRING) is begin if RHS(1) = '1' then LHS <= '1'; elsif RHS(1) = '0' then LHS <= '0'; else LHS <= 'X'; end if; end procedure; procedure esl_compare_l (signal LHS: in STD_LOGIC; variable RHS: in STRING; variable dontcare: in BOOLEAN; variable isok: out BOOLEAN) is begin if dontcare then isok := true; elsif RHS(1) = '1' then if LHS = '1' then isok := true; else isok := false; end if; elsif RHS(1) = '0' then if LHS = '0' then isok := true; else isok := false; end if; else isok := true; end if; end procedure; procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR; variable RHS: in STRING; variable dontcare: in BOOLEAN; variable isok: out BOOLEAN) is variable i : INTEGER; variable bitwidth : INTEGER; begin bitwidth := LHS'length; if dontcare then isok := true; else isok := true; loop_compare: for i in 1 to bitwidth loop if RHS(i) = '1' then if LHS(bitwidth - i) /= '1' then isok := false; exit loop_compare; end if; elsif RHS(i) = '0' then if LHS(bitwidth - i) /= '0' then isok := false; exit loop_compare; end if; end if; end loop; end if; end procedure; function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING is variable ret : STRING (1 to lv'length); variable i: INTEGER; begin for i in 1 to lv'length loop if lv(lv'length - i) = '1' then ret(i) := '1'; elsif lv(lv'length - i) = '0' then ret(i) := '0'; else ret(i) := 'X'; end if; end loop; return ret; end function; function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is constant LEN : integer := (lv'length + 3)/4; variable ret : STRING (1 to LEN); variable i, tmp: INTEGER; variable normal_lv : STD_LOGIC_VECTOR(LEN * 4 - 1 downto 0); variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0); begin normal_lv := (others => '0'); normal_lv(lv'length - 1 downto 0) := lv; for i in 0 to LEN - 1 loop tmp_lv := normal_lv(LEN * 4 - 1 - i * 4 downto LEN * 4 - 4 - i * 4); case tmp_lv is when "0000" => ret(i + 1) := '0'; when "0001" => ret(i + 1) := '1'; when "0010" => ret(i + 1) := '2'; when "0011" => ret(i + 1) := '3'; when "0100" => ret(i + 1) := '4'; when "0101" => ret(i + 1) := '5'; when "0110" => ret(i + 1) := '6'; when "0111" => ret(i + 1) := '7'; when "1000" => ret(i + 1) := '8'; when "1001" => ret(i + 1) := '9'; when "1010" => ret(i + 1) := 'a'; when "1011" => ret(i + 1) := 'b'; when "1100" => ret(i + 1) := 'c'; when "1101" => ret(i + 1) := 'd'; when "1110" => ret(i + 1) := 'e'; when "1111" => ret(i + 1) := 'f'; when others => ret(i + 1) := '0'; end case; end loop; return ret; end function; function esl_conv_lv (str : STRING; base : integer; len : integer) return STD_LOGIC_VECTOR is variable ret : STD_LOGIC_VECTOR(len - 1 downto 0); variable val : integer := 0; variable pos : boolean := true; variable i : integer; begin loop_main: for i in 1 to str'length loop if str(i) = ' ' or str(i) = HT or str(i) = CR or str(i) = LF then exit loop_main; elsif str(i) = '-' then pos := false; else case base is when 10 => if '0' <= str(i) and str(i) <= '9' then val := val10 + character'pos(str(i)) - character'pos('0'); else val := val10; end if; when others => val := 0; end case; end if; end loop; if pos = false then val := val * (-1); end if; ret := conv_std_logic_vector(val, len); return ret; end function; end package body; -- synthesis translate_on -- XSIP watermark, do not delete 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689	gpl-3.0
makestuff/comm-fpga	ss/vhdl/sync-recv/tb_unit/sync_recv_tb.vhdl	1	3670	-- -- Copyright (C) 2009-2012 Chris McClelland -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Lesser General Public License for more details. -- -- You should have received a copy of the GNU Lesser General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; entity sync_recv_tb is end entity; architecture behavioural of sync_recv_tb is signal sysClk : std_logic; -- main system clock signal dispClk : std_logic; -- display version of sysClk, which leads it by 4ns -- Serial in signal serClk : std_logic; signal serData : std_logic; -- Parallel out signal recvData : std_logic_vector(7 downto 0); signal recvValid : std_logic; -- Detect rising serClk edges signal serClk_prev : std_logic; signal serClkFE : std_logic; begin -- Instantiate sync_recv module for testing uut: entity work.sync_recv port map( clk_in => sysClk, -- Serial in serClkFE_in => serClkFE, serData_in => serData, -- Parallel out recvData_out => recvData, recvValid_out => recvValid ); -- Infer registers process(sysClk) begin if ( rising_edge(sysClk) ) then serClk_prev <= serClk; end if; end process; -- Detect rising edges on serClk serClkFE <= '1' when serClk = '0' and serClk_prev = '1' else '0'; -- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time -- for signals in GTKWave. process begin sysClk <= '0'; dispClk <= '1'; wait for 10 ns; dispClk <= '0'; wait for 10 ns; loop dispClk <= '1'; wait for 4 ns; sysClk <= '1'; wait for 6 ns; dispClk <= '0'; wait for 4 ns; sysClk <= '0'; wait for 6 ns; end loop; end process; -- Drive serClk process begin serClk <= '0'; loop wait until rising_edge(sysClk); wait until rising_edge(sysClk); wait until rising_edge(sysClk); wait until rising_edge(sysClk); serClk <= not(serClk); end loop; end process; -- Drive the sync serial signals process procedure sendByte(constant b : in std_logic_vector(7 downto 0)) is begin serData <= '0'; -- start bit wait until rising_edge(serClk); serData <= b(0); -- bit 0 wait until rising_edge(serClk); serData <= b(1); -- bit 1 wait until rising_edge(serClk); serData <= b(2); -- bit 2 wait until rising_edge(serClk); serData <= b(3); -- bit 3 wait until rising_edge(serClk); serData <= b(4); -- bit 4 wait until rising_edge(serClk); serData <= b(5); -- bit 5 wait until rising_edge(serClk); serData <= b(6); -- bit 6 wait until rising_edge(serClk); serData <= b(7); -- bit 7 wait until rising_edge(serClk); serData <= '1'; -- stop bit wait until rising_edge(serClk); end procedure; procedure pause(constant n : in integer) is variable i : integer; begin for i in 1 to n loop wait until rising_edge(serClk); end loop; end procedure; begin serData <= '1'; pause(4); sendByte(x"55"); sendByte(x"5B"); sendByte(x"5A"); serData <= 'Z'; -- tri-state data line after final send (AVR disables sender) wait; end process; end architecture;	gpl-3.0
nickg/nvc	test/regress/link3.vhd	1	2986	-- From OSVVM -- use std.textio.all ; package NamePkg is type NamePType is protected procedure Set (NameIn : String) ; impure function Get (DefaultName : string := "") return string ; impure function GetOpt return string ; impure function IsSet return boolean ; procedure Clear ; -- clear name procedure Deallocate ; -- effectively alias to clear name end protected NamePType ; end package NamePkg ; package body NamePkg is type NamePType is protected body variable NamePtr : line ; ------------------------------------------------------------ procedure Set (NameIn : String) is ------------------------------------------------------------ begin deallocate(NamePtr) ; NamePtr := new string'(NameIn) ; end procedure Set ; ------------------------------------------------------------ impure function Get (DefaultName : string := "") return string is ------------------------------------------------------------ begin if NamePtr = NULL then return DefaultName ; else return NamePtr.all ; end if ; end function Get ; ------------------------------------------------------------ impure function GetOpt return string is ------------------------------------------------------------ begin if NamePtr = NULL then return NUL & "" ; else return NamePtr.all ; end if ; end function GetOpt ; ------------------------------------------------------------ impure function IsSet return boolean is ------------------------------------------------------------ begin return NamePtr /= NULL ; end function IsSet ; ------------------------------------------------------------ procedure Clear is -- clear name ------------------------------------------------------------ begin deallocate(NamePtr) ; end procedure Clear ; ------------------------------------------------------------ procedure Deallocate is -- clear name ------------------------------------------------------------ begin Clear ; end procedure Deallocate ; end protected body NamePType ; end package body NamePkg ; ------------------------------------------------------------------------------- use work.namepkg.all; package other_pkg is type otherptype is protected procedure do_clear; end protected; end package; package body other_pkg is type otherptype is protected body variable n : nameptype; procedure do_clear is begin n.clear; end procedure; end protected body; end package body; ------------------------------------------------------------------------------- entity link3 is end entity; use work.other_pkg.all; architecture test of link3 is shared variable p : otherptype; begin p1: process is begin p.do_clear; wait; end process; end architecture;	gpl-3.0
Darkin47/Zynq-TX-UTT	Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_indet_btt.vhd	3	60736	------------------------------------------------------------------------------- -- axi_datamover_indet_btt.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_indet_btt.vhd -- -- Description: -- This file implements the DataMover S2MM Indeterminate BTT support module. -- This Module keeps track of the incoming data stream and generates a transfer -- descriptor for each AXI MMap Burst worth of data loaded in the Data FIFO. -- This information is stored in a separate FIFO that the Predictive Transfer -- Calculator fetches sequentially as it is generating commands for the AXI MMap -- bus. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library lib_pkg_v1_0_2; Use lib_pkg_v1_0_2.lib_pkg.clog2; library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_sfifo_autord; use axi_datamover_v5_1_10.axi_datamover_skid_buf; Use axi_datamover_v5_1_10.axi_datamover_stbs_set; Use axi_datamover_v5_1_10.axi_datamover_stbs_set_nodre; ------------------------------------------------------------------------------- entity axi_datamover_indet_btt is generic ( C_SF_FIFO_DEPTH : integer range 128 to 8192 := 128; -- Sets the depth of the Data FIFO C_IBTT_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8; -- Sets the width of the sf2pcc_xfer_bytes port C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2; -- Sets the bit width of the starting address offset port -- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH) C_MAX_BURST_LEN : Integer range 2 to 256 := 16; -- Indicates what is set as the allowed max burst length for AXI4 -- transfers C_MMAP_DWIDTH : Integer range 32 to 1024 := 32; -- Indicates the width of the AXI4 MMap data path C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Indicates the width of the stream data path C_ENABLE_SKID_BUF : string := "11111"; C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_ENABLE_DRE : Integer range 0 to 1 := 0; C_FAMILY : String := "virtex7" -- Specifies the target FPGA Family ); port ( -- Clock input -------------------------------------------- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ----------------------------------------------------------- -- Write Data Controller I/O ---------------------------------------------------------- -- ibtt2wdc_stbs_asserted : Out std_logic_vector(7 downto 0); -- -- Indicates the number of asserted WSTRB bits for the -- -- associated output stream data beat -- -- ibtt2wdc_eop : Out std_logic; -- -- Write End of Packet flag output to Write Data Controller -- -- ibtt2wdc_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); -- -- Write DATA output to Write Data Controller -- -- ibtt2wdc_tstrb : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); -- -- Write DATA output to Write Data Controller -- -- ibtt2wdc_tlast : Out std_logic; -- -- Write LAST output to Write Data Controller -- -- ibtt2wdc_tvalid : Out std_logic; -- -- Write VALID output to Write Data Controller -- -- wdc2ibtt_tready : In std_logic; -- -- Write READY input from Write Data Controller -- --------------------------------------------------------------------------------------- -- DRE Stream In ---------------------------------------------------------------------- -- dre2ibtt_tvalid : In std_logic; -- -- DRE Stream VALID Output -- -- ibtt2dre_tready : Out Std_logic; -- -- DRE Stream READY input -- -- dre2ibtt_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- DRE Stream DATA input -- -- dre2ibtt_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- DRE Stream STRB input -- -- dre2ibtt_tlast : In std_logic; -- -- DRE Xfer LAST input -- -- dre2ibtt_eop : In std_logic; -- -- DRE Stream end of Stream packet flag -- -------------------------------------------------------------------------------------- -- Starting Address Offset Input ------------------------------------------------- -- dre2ibtt_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); -- -- Used by Packing logic to set the initial data slice position for the -- -- packing operation. Packing is only needed if the MMap and Stream Data -- -- widths do not match. This input is sampled on the first valid DRE Stream In -- -- input databeat of a packet. -- -- -- ----------------------------------------------------------------------------------- -- Store and Forward Command Calculator Interface --------------------------------------- -- sf2pcc_xfer_valid : Out std_logic; -- -- Indicates that at least 1 xfer descriptor entry is in in the XFER_DESCR_FIFO -- -- pcc2sf_xfer_ready : in std_logic; -- -- Indicates that a full burst of data has been loaded into the data FIFO -- -- -- sf2pcc_cmd_cmplt : Out std_logic; -- -- Indicates that this is the final xfer for an associated command loaded -- -- into the Realigner by the IBTTCC interface -- -- -- sf2pcc_packet_eop : Out std_logic; -- -- Indicates the end of a Stream Packet corresponds to the pending -- -- xfer data described by this xfer descriptor -- -- sf2pcc_xfer_bytes : Out std_logic_vector(C_IBTT_XFER_BYTES_WIDTH-1 downto 0) -- -- This byte count is used by the IBTTCC for setting up the spawned child -- -- commands. The IBTTCC must use this count to generate the appropriate -- -- LEN value to put out on the AXI4 Write Addr Channel and the WSTRB on the AXI4 -- -- Write Data Channel. -- ----------------------------------------------------------------------------------------- ); end entity axi_datamover_indet_btt; architecture implementation of axi_datamover_indet_btt is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Functions ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_cntr_width -- -- Function Description: -- This function calculates the needed counter bit width from the -- number of count sates needed (input). -- ------------------------------------------------------------------- function funct_get_cntr_width (num_cnt_values : integer) return integer is Variable temp_cnt_width : Integer := 0; begin if (num_cnt_values <= 2) then temp_cnt_width := 1; elsif (num_cnt_values <= 4) then temp_cnt_width := 2; elsif (num_cnt_values <= 8) then temp_cnt_width := 3; elsif (num_cnt_values <= 16) then temp_cnt_width := 4; elsif (num_cnt_values <= 32) then temp_cnt_width := 5; elsif (num_cnt_values <= 64) then temp_cnt_width := 6; elsif (num_cnt_values <= 128) then temp_cnt_width := 7; else temp_cnt_width := 8; end if; Return (temp_cnt_width); end function funct_get_cntr_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 4 and 32. THis is used for sizing the SRL based XD FIFO. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 4) then temp_pwr2 := 4; elsif (input_value <= 8) then temp_pwr2 := 8; elsif (input_value <= 16) then temp_pwr2 := 16; else temp_pwr2 := 32; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- -- Constants Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant BITS_PER_BYTE : integer := 8; Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH; Constant STRM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/BITS_PER_BYTE; Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/BITS_PER_BYTE; Constant STRM_STRBS_ASSERTED_WIDTH : integer := clog2(STRM_WSTB_WIDTH)+1; -- Constant DATA_FIFO_DFACTOR : integer := 4; -- set buffer to 4 times the Max allowed Burst Length -- Constant DATA_FIFO_DEPTH : integer := C_MAX_BURST_LENDATA_FIFO_DFACTOR; Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH; Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+MMAP_WSTB_WIDTHC_ENABLE_S2MM_TKEEP+2; -- Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+STRB_CNTR_WIDTH+2; Constant DATA_FIFO_CNT_WIDTH : integer := clog2(DATA_FIFO_DEPTH)+1; Constant BURST_CNTR_WIDTH : integer := clog2(C_MAX_BURST_LEN); Constant MAX_BURST_DBEATS : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(C_MAX_BURST_LEN-1, BURST_CNTR_WIDTH); Constant DBC_ONE : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, BURST_CNTR_WIDTH); Constant BYTE_CNTR_WIDTH : integer := C_IBTT_XFER_BYTES_WIDTH; Constant BYTES_PER_MMAP_DBEAT : integer := C_MMAP_DWIDTH/BITS_PER_BYTE; Constant BYTES_PER_STRM_DBEAT : integer := C_STREAM_DWIDTH/BITS_PER_BYTE; --Constant MAX_BYTE_CNT : integer := C_MAX_BURST_LENBYTES_PER_DBEAT; --Constant NUM_STRB_BITS : integer := BYTES_PER_DBEAT; Constant BCNTR_ONE : Unsigned(BYTE_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, BYTE_CNTR_WIDTH); --Constant XD_FIFO_DEPTH : integer := 16; Constant XD_FIFO_DEPTH : integer := funct_rnd2pwr_of_2(DATA_FIFO_DEPTH/C_MAX_BURST_LEN); Constant XD_FIFO_CNT_WIDTH : integer := clog2(XD_FIFO_DEPTH)+1; Constant XD_FIFO_WIDTH : integer := BYTE_CNTR_WIDTH+2; Constant MMAP_STBS_ASSERTED_WIDTH : integer := 8; Constant SKIDBUF2WDC_DWIDTH : integer := C_MMAP_DWIDTH + MMAP_STBS_ASSERTED_WIDTH; Constant SKIDBUF2WDC_STRB_WIDTH : integer := SKIDBUF2WDC_DWIDTH/BITS_PER_BYTE; --Constant NUM_ZEROS_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH; Constant STRB_CNTR_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH; -- Signals signal sig_wdc2ibtt_tready : std_logic := '0'; signal sig_ibtt2wdc_tvalid : std_logic := '0'; signal sig_ibtt2wdc_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tstrb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tlast : std_logic := '0'; signal sig_ibtt2wdc_eop : std_logic := '0'; signal sig_push_data_fifo : std_logic := '0'; signal sig_pop_data_fifo : std_logic := '0'; signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_data_fifo_dvalid : std_logic := '0'; signal sig_data_fifo_full : std_logic := '0'; signal sig_data_fifo_rd_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0'); signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0'); signal sig_push_xd_fifo : std_logic := '0'; signal sig_pop_xd_fifo : std_logic := '0'; signal sig_xd_fifo_data_in : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_xd_fifo_data_out : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_xd_fifo_dvalid : std_logic := '0'; signal sig_xd_fifo_full : std_logic := '0'; signal sig_tmp : std_logic := '0'; signal sig_strm_in_ready : std_logic := '0'; signal sig_good_strm_dbeat : std_logic := '0'; signal sig_good_tlast_dbeat : std_logic := '0'; signal sig_dre2ibtt_tlast_reg : std_logic := '0'; signal sig_dre2ibtt_eop_reg : std_logic := '0'; signal sig_burst_dbeat_cntr : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_incr_dbeat_cntr : std_logic := '0'; signal sig_clr_dbeat_cntr : std_logic := '0'; signal sig_clr_dbc_reg : std_logic := '0'; signal sig_dbc_max : std_logic := '0'; signal sig_pcc2ibtt_xfer_ready : std_logic := '0'; signal sig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_ld_byte_cntr : std_logic := '0'; signal sig_incr_byte_cntr : std_logic := '0'; signal sig_clr_byte_cntr : std_logic := '0'; signal sig_fifo_tstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); signal sig_num_ls_zeros : integer range 0 to STRM_WSTB_WIDTH := 0; signal sig_ls_assert_found : std_logic := '0'; signal sig_num_ms_zeros : integer range 0 to STRM_WSTB_WIDTH := 0; signal sig_ms_assert_found : std_logic := '0'; -- signal sig_num_zeros : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0'); -- signal sig_num_ones : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0'); signal sig_stbs2sfcc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0'); signal sig_stbs2wdc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0'); signal sig_skidbuf_in_tready : std_logic := '0'; signal sig_skidbuf_in_tvalid : std_logic := '0'; signal sig_skidbuf_in_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0'); signal sig_skidbuf_in_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_skidbuf_in_tlast : std_logic := '0'; signal sig_skidbuf_in_eop : std_logic := '0'; signal sig_skidbuf_out_tready : std_logic := '0'; signal sig_skidbuf_out_tvalid : std_logic := '0'; signal sig_skidbuf_out_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0'); signal sig_skidbuf_out_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_skidbuf_out_tlast : std_logic := '0'; signal sig_skidbuf_out_eop : std_logic := '0'; signal sig_enable_dbcntr : std_logic := '0'; signal sig_good_fifo_write : std_logic := '0'; begin --(architecture implementation) -- Write Data Controller I/O sig_wdc2ibtt_tready <= wdc2ibtt_tready ; ibtt2wdc_tvalid <= sig_ibtt2wdc_tvalid ; ibtt2wdc_tdata <= sig_ibtt2wdc_tdata ; ibtt2wdc_tstrb <= sig_ibtt2wdc_tstrb ; ibtt2wdc_tlast <= sig_ibtt2wdc_tlast ; ibtt2wdc_eop <= sig_ibtt2wdc_eop ; ibtt2wdc_stbs_asserted <= sig_ibtt2wdc_stbs_asserted; -- PCC I/O sf2pcc_xfer_valid <= sig_xd_fifo_dvalid; sig_pcc2ibtt_xfer_ready <= pcc2sf_xfer_ready; sf2pcc_packet_eop <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH+1); sf2pcc_cmd_cmplt <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH); sf2pcc_xfer_bytes <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH-1 downto 0); -- DRE Stream In ibtt2dre_tready <= sig_strm_in_ready; -- sig_strm_in_ready <= not(sig_xd_fifo_full) and -- not(sig_data_fifo_full); sig_good_strm_dbeat <= dre2ibtt_tvalid and sig_strm_in_ready; sig_good_tlast_dbeat <= sig_good_strm_dbeat and dre2ibtt_tlast; -- Burst Packet Counter Logic ------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_DBC_STUFF -- -- Process Description: -- Just a register for data beat counter signals. -- ------------------------------------------------------------- REG_DBC_STUFF : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_dre2ibtt_tlast_reg <= '0'; sig_dre2ibtt_eop_reg <= '0'; sig_clr_dbc_reg <= '0'; else sig_dre2ibtt_tlast_reg <= dre2ibtt_tlast; sig_dre2ibtt_eop_reg <= dre2ibtt_eop; sig_clr_dbc_reg <= sig_clr_dbeat_cntr; end if; end if; end process REG_DBC_STUFF; -- sig_clr_dbc_reg <= sig_clr_dbeat_cntr; -- Increment the dataBeat counter on a data fifo wide -- load condition. If packer logic is enabled, this will -- only occur when a full fifo data width has been collected -- from the Stream input. sig_incr_dbeat_cntr <= sig_good_strm_dbeat and sig_enable_dbcntr; -- Check to see if a max burst len of databeats have been -- loaded into the FIFO sig_dbc_max <= '1' when (sig_burst_dbeat_cntr = MAX_BURST_DBEATS) Else '0'; -- Start the counter over at a max burst len boundary or at -- the end of the packet. sig_clr_dbeat_cntr <= '1' when (sig_dbc_max = '1' and sig_good_strm_dbeat = '1' and sig_enable_dbcntr = '1') or (sig_good_tlast_dbeat = '1' and sig_enable_dbcntr = '1') Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DBC_CMTR -- -- Process Description: -- The Databeat Counter keeps track of how many databeats have -- been loaded into the Data FIFO. When a max burst worth of -- databeats have been loaded (or a TLAST encountered), the -- XD FIFO can be loaded with a transfer data set to be sent -- to the IBTTCC. -- ------------------------------------------------------------- IMP_DBC_CMTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_clr_dbeat_cntr = '1') then sig_burst_dbeat_cntr <= (others => '0'); elsif (sig_incr_dbeat_cntr = '1') then sig_burst_dbeat_cntr <= sig_burst_dbeat_cntr + DBC_ONE; else null; -- hold current value end if; end if; end process IMP_DBC_CMTR; ----- Byte Counter Logic ----------------------------------------------- sig_clr_byte_cntr <= sig_clr_dbc_reg and not(sig_good_strm_dbeat); sig_ld_byte_cntr <= sig_clr_dbc_reg and sig_good_strm_dbeat; sig_incr_byte_cntr <= sig_good_strm_dbeat; sig_byte_cntr_incr_value <= RESIZE(UNSIGNED(sig_stbs2sfcc_asserted), BYTE_CNTR_WIDTH); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_BYTE_CMTR -- -- Process Description: -- Keeps a running byte count per burst packet loaded into the -- xfer FIFO. It is based on the strobes set on the incoming -- Stream dbeat. -- ------------------------------------------------------------- IMP_BYTE_CMTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_clr_byte_cntr = '1') then sig_byte_cntr <= (others => '0'); elsif (sig_ld_byte_cntr = '1') then sig_byte_cntr <= sig_byte_cntr_incr_value; elsif (sig_incr_byte_cntr = '1') then sig_byte_cntr <= sig_byte_cntr + sig_byte_cntr_incr_value; else null; -- hold current value end if; end if; end process IMP_BYTE_CMTR; ------------------------------------------------------------ -- Instance: I_IBTTCC_STBS_SET -- -- Description: -- Instance of the asserted strobe counter for the IBTTCC -- interface. -- ------------------------------------------------------------ SAME_WIDTH_NO_DRE : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate begin I_IBTTCC_STBS_SET : entity axi_datamover_v5_1_10.axi_datamover_stbs_set_nodre generic map ( C_STROBE_WIDTH => STRM_WSTB_WIDTH ) port map ( tstrb_in => dre2ibtt_tstrb, num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv ); end generate SAME_WIDTH_NO_DRE; DIFF_WIDTH_OR_DRE : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate begin I_IBTTCC_STBS_SET : entity axi_datamover_v5_1_10.axi_datamover_stbs_set generic map ( C_STROBE_WIDTH => STRM_WSTB_WIDTH ) port map ( tstrb_in => dre2ibtt_tstrb, num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv ); end generate DIFF_WIDTH_OR_DRE; ----- Xfer Descriptor FIFO Logic ----------------------------------------------- sig_push_xd_fifo <= sig_clr_dbc_reg ; sig_pop_xd_fifo <= sig_pcc2ibtt_xfer_ready and sig_xd_fifo_dvalid ; sig_xd_fifo_data_in <= sig_dre2ibtt_eop_reg & -- (TLAST for the input Stream) sig_dre2ibtt_tlast_reg & -- (TLAST for the IBTTCC command) std_logic_vector(sig_byte_cntr); -- Number of bytes in this xfer ------------------------------------------------------------ -- Instance: I_XD_FIFO -- -- Description: -- Implement the Transfer Desciptor (XD) FIFO. This FIFO holds -- the individual child command xfer descriptors used by the -- IBTTCC to generate the commands sent to the Address Cntlr and -- the Data Cntlr. -- ------------------------------------------------------------ I_XD_FIFO : entity axi_datamover_v5_1_10.axi_datamover_sfifo_autord generic map ( C_DWIDTH => XD_FIFO_WIDTH , C_DEPTH => XD_FIFO_DEPTH , C_DATA_CNT_WIDTH => XD_FIFO_CNT_WIDTH , C_NEED_ALMOST_EMPTY => 0 , C_NEED_ALMOST_FULL => 1 , C_USE_BLKMEM => 0 , C_FAMILY => C_FAMILY ) port map ( -- Inputs SFIFO_Sinit => mmap_reset , SFIFO_Clk => primary_aclk , SFIFO_Wr_en => sig_push_xd_fifo , SFIFO_Din => sig_xd_fifo_data_in , SFIFO_Rd_en => sig_pop_xd_fifo , SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW , -- Outputs SFIFO_DValid => sig_xd_fifo_dvalid , SFIFO_Dout => sig_xd_fifo_data_out , SFIFO_Full => sig_xd_fifo_full , SFIFO_Empty => open , SFIFO_Almost_full => sig_tmp , SFIFO_Almost_empty => open , SFIFO_Rd_count => open , SFIFO_Rd_count_minus1 => open , SFIFO_Wr_count => open , SFIFO_Rd_ack => open ); ---------------------------------------------------------------- -- Packing Logic ------------------------------------------ ---------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: OMIT_PACKING -- -- If Generate Description: -- Omits any packing logic in the Store and Forward module. -- The Stream and MMap data widths are the same. -- ------------------------------------------------------------ OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate begin -- The data beat counter is always enabled when the packer -- is omitted. sig_enable_dbcntr <= '1'; sig_good_fifo_write <= sig_good_strm_dbeat; sig_strm_in_ready <= not(sig_xd_fifo_full) and not(sig_data_fifo_full) and not (sig_tmp); GEN_S2MM_TKEEP_ENABLE5 : if C_ENABLE_S2MM_TKEEP = 1 generate begin -- Concatonate the Stream inputs into the single FIFO data -- word input value sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker dre2ibtt_tlast & -- Tlast marker dre2ibtt_tstrb & -- TSTRB Value dre2ibtt_tdata; -- data value end generate GEN_S2MM_TKEEP_ENABLE5; GEN_S2MM_TKEEP_DISABLE5 : if C_ENABLE_S2MM_TKEEP = 0 generate begin -- Concatonate the Stream inputs into the single FIFO data -- word input value sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker dre2ibtt_tlast & -- Tlast marker --dre2ibtt_tstrb & -- TSTRB Value dre2ibtt_tdata; -- data value end generate GEN_S2MM_TKEEP_DISABLE5; end generate OMIT_PACKING; ------------------------------------------------------------ -- If Generate -- -- Label: INCLUDE_PACKING -- -- If Generate Description: -- Includes packing logic in the IBTT Store and Forward -- module. The MMap Data bus is wider than the Stream width. -- ------------------------------------------------------------ INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate Constant TLAST_WIDTH : integer := 1; -- bit Constant EOP_WIDTH : integer := 1; -- bit Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH; Constant STRB_SLICE_WIDTH : integer := STRM_WSTB_WIDTH; Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH + EOP_WIDTH; Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO); Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, OFFSET_CNTR_WIDTH); Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH); -- Types ----------------------------------------------------------------------------- type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of std_logic_vector(DATA_SLICE_WIDTH-1 downto 0); type lsig_strb_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of std_logic_vector(STRB_SLICE_WIDTH-1 downto 0); type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0); -- local signals signal lsig_data_slice_reg : lsig_data_slice_type; signal lsig_strb_slice_reg : lsig_strb_slice_type; signal lsig_flag_slice_reg : lsig_flag_slice_type; signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0'); signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0'); signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0'); signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0'); signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0'); signal lsig_ld_offset : std_logic := '0'; signal lsig_incr_offset : std_logic := '0'; signal lsig_offset_cntr_eq_max : std_logic := '0'; signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0'); signal lsig_combined_strb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); signal lsig_tlast_or : std_logic := '0'; signal lsig_eop_or : std_logic := '0'; signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0'); signal lsig_partial_eop_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0'); signal lsig_packer_full : std_logic := '0'; signal lsig_packer_empty : std_logic := '0'; signal lsig_set_packer_full : std_logic := '0'; signal lsig_good_push2fifo : std_logic := '0'; signal lsig_first_dbeat : std_logic := '0'; begin -- Generate the stream ready sig_strm_in_ready <= not(sig_xd_fifo_full) and not(sig_tmp) and (not(lsig_packer_full) or lsig_good_push2fifo) ; -- Enable the Data Beat counter when the packer is -- going full sig_enable_dbcntr <= lsig_set_packer_full; -- Assign the flag indicating that a fifo write is going -- to occur at the next rising clock edge. sig_good_fifo_write <= lsig_good_push2fifo; GEN_S2MM_TKEEP_ENABLE6 : if C_ENABLE_S2MM_TKEEP = 1 generate begin -- Format the composite FIFO input data word sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit lsig_tlast_or & lsig_combined_strb & lsig_combined_data ; -- LS Bits end generate GEN_S2MM_TKEEP_ENABLE6; GEN_S2MM_TKEEP_DISABLE6 : if C_ENABLE_S2MM_TKEEP = 0 generate begin -- Format the composite FIFO input data word sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit lsig_tlast_or & --lsig_combined_strb & lsig_combined_data ; -- LS Bits end generate GEN_S2MM_TKEEP_DISABLE6; -- Generate a flag indicating a write to the DataFIFO -- is going to complete lsig_good_push2fifo <= lsig_packer_full and not(sig_data_fifo_full); -- Generate the control that loads the starting address -- offset for the next input packet lsig_ld_offset <= lsig_first_dbeat and sig_good_strm_dbeat; -- Generate the control for incrementing the offset counter lsig_incr_offset <= sig_good_strm_dbeat; -- Generate a flag indicating the packer input register -- array is full or has loaded the last data beat of -- the input paket lsig_set_packer_full <= sig_good_strm_dbeat and (dre2ibtt_tlast or lsig_offset_cntr_eq_max); -- Check to see if the offset counter has reached its max -- value lsig_offset_cntr_eq_max <= '1' --when (lsig_0ffset_cntr = OFFSET_CNT_MAX) when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX) Else '0'; -- Mux between the input start offset and the offset counter -- output to use for the packer slice load control. lsig_0ffset_to_to_use <= UNSIGNED(dre2ibtt_strt_addr_offset) when (lsig_first_dbeat = '1') Else lsig_0ffset_cntr; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_OFFSET_LD_MARKER -- -- Process Description: -- Implements the flop indicating the first databeat of -- an input data packet. -- ------------------------------------------------------------- IMP_OFFSET_LD_MARKER : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_first_dbeat <= '1'; elsif (sig_good_strm_dbeat = '1' and dre2ibtt_tlast = '0') then lsig_first_dbeat <= '0'; Elsif (sig_good_strm_dbeat = '1' and dre2ibtt_tlast = '1') Then lsig_first_dbeat <= '1'; else null; -- Hold Current State end if; end if; end process IMP_OFFSET_LD_MARKER; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_OFFSET_CNTR -- -- Process Description: -- Implements the address offset counter that is used to -- steer the data loads into the packer register slices. -- Note that the counter has to be loaded with the starting -- offset plus one to sync up with the data input. ------------------------------------------------------------- IMP_OFFSET_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_0ffset_cntr <= (others => '0'); Elsif (lsig_ld_offset = '1') Then lsig_0ffset_cntr <= UNSIGNED(dre2ibtt_strt_addr_offset) + OFFSET_CNT_ONE; elsif (lsig_incr_offset = '1') then lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE; else null; -- Hold Current State end if; end if; end process IMP_OFFSET_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PACK_REG_FULL -- -- Process Description: -- Implements the Packer Register full/empty flags -- ------------------------------------------------------------- IMP_PACK_REG_FULL : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_packer_full <= '0'; lsig_packer_empty <= '1'; Elsif (lsig_set_packer_full = '1' and lsig_packer_full = '0') Then lsig_packer_full <= '1'; lsig_packer_empty <= '0'; elsif (lsig_set_packer_full = '0' and lsig_good_push2fifo = '1') then lsig_packer_full <= '0'; lsig_packer_empty <= '1'; else null; -- Hold Current State end if; end if; end process IMP_PACK_REG_FULL; ------------------------------------------------------------ -- For Generate -- -- Label: DO_REG_SLICES -- -- For Generate Description: -- -- Implements the Packng Register Slices -- -- ------------------------------------------------------------ DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate begin -- generate the register load enable for each slice segment based -- on the address offset count value lsig_segment_ld(slice_index) <= '1' when (sig_good_strm_dbeat = '1' and TO_INTEGER(lsig_0ffset_to_to_use) = slice_index) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DATA_SLICE -- -- Process Description: -- Implement a data register slice abd Strobe register slice -- for the packer (upsizer). -- ------------------------------------------------------------- IMP_DATA_SLICE : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_data_slice_reg(slice_index) <= (others => '0'); lsig_strb_slice_reg(slice_index) <= (others => '0'); elsif (lsig_segment_ld(slice_index) = '1') then lsig_data_slice_reg(slice_index) <= dre2ibtt_tdata; lsig_strb_slice_reg(slice_index) <= dre2ibtt_tstrb; -- optional clear of slice reg elsif (lsig_segment_ld(slice_index) = '0' and lsig_good_push2fifo = '1') then lsig_data_slice_reg(slice_index) <= (others => '0'); lsig_strb_slice_reg(slice_index) <= (others => '0'); else null; -- Hold Current State end if; end if; end process IMP_DATA_SLICE; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FLAG_SLICE -- -- Process Description: -- Implement a flag register slice for the packer. -- ------------------------------------------------------------- IMP_FLAG_SLICE : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_flag_slice_reg(slice_index) <= (others => '0'); elsif (lsig_segment_ld(slice_index) = '1') then lsig_flag_slice_reg(slice_index) <= dre2ibtt_tlast & -- bit 1 dre2ibtt_eop; -- bit 0 elsif (lsig_segment_ld(slice_index) = '0' and lsig_good_push2fifo = '1') then lsig_flag_slice_reg(slice_index) <= (others => '0'); else null; -- Hold Current State end if; end if; end process IMP_FLAG_SLICE; end generate DO_REG_SLICES; -- Do the OR functions of the Flags ------------------------------------- lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ; lsig_eop_or <= lsig_partial_eop_or(MMAP2STRM_WIDTH_RATO-1); lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1); lsig_partial_eop_or(0) <= lsig_flag_slice_reg(0)(0); ------------------------------------------------------------ -- For Generate -- -- Label: DO_FLAG_OR -- -- For Generate Description: -- Implement the OR of the TLAST and EOP Error flags. -- -- -- ------------------------------------------------------------ DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate begin lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or --lsig_partial_tlast_or(slice_index); lsig_flag_slice_reg(slice_index)(1); lsig_partial_eop_or(slice_index) <= lsig_partial_eop_or(slice_index-1) or --lsig_partial_eop_or(slice_index); lsig_flag_slice_reg(slice_index)(0); end generate DO_FLAG_OR; ------------------------------------------------------------ -- For Generate -- -- Label: DO_DATA_COMBINER -- -- For Generate Description: -- Combines the Data Slice register and Strobe slice register -- outputs into a single data and single strobe vector used for -- input data to the Data FIFO. -- -- ------------------------------------------------------------ DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate begin lsig_combined_data((slice_indexDATA_SLICE_WIDTH)-1 downto (slice_index-1)DATA_SLICE_WIDTH) <= lsig_data_slice_reg(slice_index-1); lsig_combined_strb((slice_indexSTRB_SLICE_WIDTH)-1 downto (slice_index-1)*STRB_SLICE_WIDTH) <= lsig_strb_slice_reg(slice_index-1); end generate DO_DATA_COMBINER; end generate INCLUDE_PACKING; -- Data FIFO Logic ------------------------------------------ --sig_push_data_fifo <= sig_good_strm_dbeat; sig_push_data_fifo <= sig_good_fifo_write; sig_pop_data_fifo <= sig_skidbuf_in_tready and sig_data_fifo_dvalid; -- -- Concatonate the Stream inputs into the single FIFO data in value -- sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker -- dre2ibtt_tlast & -- dre2ibtt_tstrb & -- dre2ibtt_tdata; ------------------------------------------------------------ -- Instance: I_DATA_FIFO -- -- Description: -- Implements the Store and Forward data FIFO -- ------------------------------------------------------------ I_DATA_FIFO : entity axi_datamover_v5_1_10.axi_datamover_sfifo_autord generic map ( C_DWIDTH => DATA_FIFO_WIDTH , C_DEPTH => DATA_FIFO_DEPTH , C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH , C_NEED_ALMOST_EMPTY => 0 , C_NEED_ALMOST_FULL => 0 , C_USE_BLKMEM => 1 , C_FAMILY => C_FAMILY ) port map ( -- Inputs SFIFO_Sinit => mmap_reset , SFIFO_Clk => primary_aclk , SFIFO_Wr_en => sig_push_data_fifo , SFIFO_Din => sig_data_fifo_data_in , SFIFO_Rd_en => sig_pop_data_fifo , SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW , -- Outputs SFIFO_DValid => sig_data_fifo_dvalid , SFIFO_Dout => sig_data_fifo_data_out , SFIFO_Full => sig_data_fifo_full , SFIFO_Empty => open , SFIFO_Almost_full => open , SFIFO_Almost_empty => open , SFIFO_Rd_count => sig_data_fifo_rd_cnt , SFIFO_Rd_count_minus1 => open , SFIFO_Wr_count => sig_data_fifo_wr_cnt , SFIFO_Rd_ack => open ); ------------------------------------------------------------------------- ---------------- Asserted TSTRB calculation logic --------------------- ------------------------------------------------------------------------- GEN_S2MM_TKEEP_ENABLE7 : if C_ENABLE_S2MM_TKEEP = 1 generate begin -- Rip the write strobe value from the FIFO output data sig_fifo_tstrb_out <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto C_MMAP_DWIDTH); end generate GEN_S2MM_TKEEP_ENABLE7; GEN_S2MM_TKEEP_DISBALE7 : if C_ENABLE_S2MM_TKEEP = 0 generate begin sig_fifo_tstrb_out <= (others => '1'); end generate GEN_S2MM_TKEEP_DISBALE7; ------------------------------------------------------------ -- Instance: I_WDC_STBS_SET -- -- Description: -- Instance of the asserted strobe counter for the WDC -- interface. -- ------------------------------------------------------------ SAME_WIDTH_NO_DRE_WDC : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate begin I_WDC_STBS_SET : entity axi_datamover_v5_1_10.axi_datamover_stbs_set_nodre generic map ( C_STROBE_WIDTH => MMAP_WSTB_WIDTH ) port map ( tstrb_in => sig_fifo_tstrb_out, num_stbs_asserted => sig_stbs2wdc_asserted ); end generate SAME_WIDTH_NO_DRE_WDC; DIFF_WIDTH_OR_DRE_WDC : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate begin I_WDC_STBS_SET : entity axi_datamover_v5_1_10.axi_datamover_stbs_set generic map ( C_STROBE_WIDTH => MMAP_WSTB_WIDTH ) port map ( tstrb_in => sig_fifo_tstrb_out, num_stbs_asserted => sig_stbs2wdc_asserted ); end generate DIFF_WIDTH_OR_DRE_WDC; ------------------------------------------------------------------------- ------- Isolation Skid Buffer Logic (needed for Fmax timing) ----------- ------------------------------------------------------------------------- -- Skid Buffer output assignments ----------- sig_skidbuf_out_tready <= sig_wdc2ibtt_tready; sig_ibtt2wdc_tvalid <= sig_skidbuf_out_tvalid; sig_ibtt2wdc_tdata <= sig_skidbuf_out_tdata(C_MMAP_DWIDTH-1 downto 0) ; sig_ibtt2wdc_tstrb <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH-1 downto 0) ; sig_ibtt2wdc_tlast <= sig_skidbuf_out_tlast ; -- Rip the EOP marker from the MS bit of the skid output strobes sig_ibtt2wdc_eop <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH) ; -- Rip the upper 8 bits of the skid output data for the strobes asserted value sig_ibtt2wdc_stbs_asserted <= sig_skidbuf_out_tdata(SKIDBUF2WDC_DWIDTH-1 downto C_MMAP_DWIDTH); -- Skid Buffer input assignments ----------- sig_skidbuf_in_tvalid <= sig_data_fifo_dvalid; sig_skidbuf_in_eop <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-1); sig_skidbuf_in_tlast <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-2); -- Steal the extra input strobe bit and use it for the EOP marker ---- sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop & ---- sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto ---- C_MMAP_DWIDTH); ---- sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop & sig_fifo_tstrb_out; -- Insert the Strobes Asserted count in the extra (MS) data byte -- for the skid buffer sig_skidbuf_in_tdata <= sig_stbs2wdc_asserted & sig_data_fifo_data_out(C_MMAP_DWIDTH-1 downto 0); ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '1' generate begin ------------------------------------------------------------ -- Instance: I_INDET_BTT_SKID_BUF -- -- Description: -- Instance for the Store and Forward isolation Skid Buffer -- which is required to achieve Fmax timing. Note that this -- skid buffer is 1 byte wider than the stream data width to -- allow for the asserted strobes count to be passed through -- it. The EOP marker is inserted in the extra strobe slot. -- ------------------------------------------------------------ I_INDET_BTT_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => SKIDBUF2WDC_DWIDTH ) port map ( -- System Ports aclk => primary_aclk , arst => mmap_reset , -- Shutdown control (assert for 1 clk pulse) skid_stop => LOGIC_LOW , -- Slave Side (Stream Data Input) s_valid => sig_skidbuf_in_tvalid , s_ready => sig_skidbuf_in_tready , s_data => sig_skidbuf_in_tdata , s_strb => sig_skidbuf_in_tstrb , s_last => sig_skidbuf_in_tlast , -- Master Side (Stream Data Output m_valid => sig_skidbuf_out_tvalid , m_ready => sig_skidbuf_out_tready , m_data => sig_skidbuf_out_tdata , m_strb => sig_skidbuf_out_tstrb , m_last => sig_skidbuf_out_tlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '0' generate begin sig_skidbuf_out_tvalid <= sig_skidbuf_in_tvalid; sig_skidbuf_in_tready <= sig_skidbuf_out_tready ; sig_skidbuf_out_tdata <= sig_skidbuf_in_tdata ; sig_skidbuf_out_tstrb <= sig_skidbuf_in_tstrb ; sig_skidbuf_out_tlast <= sig_skidbuf_in_tlast ; end generate DISABLE_AXIS_SKID; end implementation;	gpl-3.0
nickg/nvc	test/regress/elab32.vhd	1	358	entity sub is port ( x : in bit_vector ); end entity; architecture test of sub is begin end architecture; ------------------------------------------------------------------------------- entity elab32 is end entity; architecture test of elab32 is signal b : bit; begin uut: entity work.sub port map ( x(0) => b ); end architecture;	gpl-3.0
Darkin47/Zynq-TX-UTT	Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_sg_v4_1/hdl/src/vhdl/axi_sg_pkg.vhd	13	6615	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_sg_pkg.vhd -- Description: This package contains various constants and functions for -- AXI SG Engine. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package axi_sg_pkg is ------------------------------------------------------------------------------- -- Function declarations ------------------------------------------------------------------------------- -- Convert boolean to a std_logic function bo2int (value : boolean) return integer; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- AXI Response Values constant OKAY_RESP : std_logic_vector(1 downto 0) := "00"; constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01"; constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10"; constant DECERR_RESP : std_logic_vector(1 downto 0) := "11"; -- Misc Constants constant CMD_BASE_WIDTH : integer := 40; constant SG_BTT_WIDTH : integer := 7; constant SG_ADDR_LSB : integer := 6; -- Interrupt Coalescing constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0'); constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001"; constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0'); -- Constants Used in Desc Updates constant DESC_STS_TYPE : std_logic := '1'; constant DESC_DATA_TYPE : std_logic := '0'; -- DataMover Command / Status Constants constant DATAMOVER_STS_CMDDONE_BIT : integer := 7; constant DATAMOVER_STS_SLVERR_BIT : integer := 6; constant DATAMOVER_STS_DECERR_BIT : integer := 5; constant DATAMOVER_STS_INTERR_BIT : integer := 4; constant DATAMOVER_STS_TAGMSB_BIT : integer := 3; constant DATAMOVER_STS_TAGLSB_BIT : integer := 0; constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0; constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22; constant DATAMOVER_CMD_TYPE_BIT : integer := 23; constant DATAMOVER_CMD_DSALSB_BIT : integer := 24; constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29; constant DATAMOVER_CMD_EOF_BIT : integer := 30; constant DATAMOVER_CMD_DRR_BIT : integer := 31; constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32; -- Note: Bit offset require adding ADDR WIDTH to get to actual bit index constant DATAMOVER_CMD_ADDRMSB_BOFST : integer := 31; constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32; constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35; constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36; constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39; -- Descriptor field bits constant DESC_STS_INTERR_BIT : integer := 28; constant DESC_STS_SLVERR_BIT : integer := 29; constant DESC_STS_DECERR_BIT : integer := 30; constant DESC_STS_CMPLTD_BIT : integer := 31; -- IOC Bit on descriptor update -- Stored in LSB of TAG field then catinated on status word from primary -- datamover (i.e. DESCTYPE & IOC & STATUS & Bytes Transferred). constant DESC_IOC_TAG_BIT : integer := 32; end axi_sg_pkg; ------------------------------------------------------------------------------- -- PACKAGE BODY ------------------------------------------------------------------------------- package body axi_sg_pkg is ------------------------------------------------------------------------------- -- Boolean to Integer ------------------------------------------------------------------------------- function bo2int ( value : boolean) return integer is variable value_int : integer; begin if(value)then value_int := 1; else value_int := 0; end if; return value_int; end function bo2int; end package body axi_sg_pkg;	gpl-3.0
nickg/nvc	test/regress/issue29.vhd	5	769	entity sub is generic ( width : integer ); port ( x : in bit_vector(width - 1 downto 0); y : in bit_vector; z : out bit_vector(width - 1 downto 0) ); end entity; architecture test of sub is begin z <= x and y after 1 us; end architecture; ------------------------------------------------------------------------------- entity issue29 is end entity; architecture rtl of issue29 is signal z : bit_vector(7 downto 0); begin sub_i: entity work.sub generic map ( width => 8 ) port map ( x => X"ab", y => X"cd", z => z ); process is begin wait for 2 us; assert z = "10001001"; wait; end process; end architecture;	gpl-3.0
nickg/nvc	lib/std.08/textio.vhd	1	6827	------------------------------------------------------------------------------- -- Copyright (C) 2012-2021 Nick Gasson -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- TEXTIO package as defined by IEEE 1076-2008 ------------------------------------------------------------------------------- package textio is type line is access string; type text is file of string; type side is (RIGHT, LEFT); subtype width is natural; function justify (value : string; justified : side := right; field : width := 0) return string; file input : text open READ_MODE is "STD_INPUT"; file output : text open WRITE_MODE is "STD_OUTPUT"; procedure readline (file f: text; l: inout line); procedure read (l : inout line; value : out bit; good : out boolean ); procedure read (l : inout line; value : out bit ); procedure read (l : inout line; value : out bit_vector; good : out boolean ); procedure read (l : inout line; value : out bit_vector ); procedure read (l : inout line; value : out boolean; good : out boolean ); procedure read (l : inout line; value : out boolean ); procedure read (l : inout line; value : out character; good : out boolean ); procedure read (l : inout line; value : out character ); procedure read (l : inout line; value : out integer; good : out boolean ); procedure read (l : inout line; value : out integer ); procedure read (l : inout line; value : out real; good : out boolean ); procedure read (l : inout line; value : out real ); procedure read (l : inout line; value : out string; good : out boolean ); procedure read (l : inout line; value : out string ); procedure read (l : inout line; value : out time; good : out boolean ); procedure read (l : inout line; value : out time ); procedure sread (l : inout line; value : out string; strlen : out natural); alias string_read is sread [line, string, natural]; alias bread is read [line, bit_vector, boolean]; alias bread is read [line, bit_vector]; alias binary_read is read [line, bit_vector, boolean]; alias binary_read is read [line, bit_vector]; procedure oread (l : inout line; value : out bit_vector; good : out boolean); procedure oread (l : inout line; value : out bit_vector); alias octal_read is oread [line, bit_vector, boolean]; alias octal_read is oread [line, bit_vector]; procedure hread (l : inout line; value : out bit_vector; good : out boolean); procedure hread (l : inout line; value : out bit_vector); alias hex_read is hread [line, bit_vector, boolean]; alias hex_read is hread [line, bit_vector]; procedure writeline (file f : text; l : inout line); procedure tee (file f : text; l : inout line); procedure write (l : inout line; value : in bit; justified : in side := right; field : in width := 0 ); procedure write (l : inout line; value : in bit_vector; justified : in side := right; field : in width := 0 ); procedure write (l : inout line; value : in boolean; justified : in side := right; field : in width := 0 ); procedure write (l : inout line; value : in character; justified : in side := right; field : in width := 0 ); procedure write (l : inout line; value : in integer; justified : in side := right; field : in width := 0 ); procedure write (l : inout line; value : in real; justified : in side:= right; field : in width := 0; digits : in natural:= 0 ); procedure write (l : inout line; value : in real; format : in string ); procedure write (l : inout line; value : in string; justified : in side := right; field : in width := 0 ); procedure write (l : inout line; value : in time; justified : in side := right; field : in width := 0; unit : in time := ns ); alias swrite is write [line, string, side, width]; alias string_write is write [line, string, side, width]; alias bwrite is write [line, bit_vector, side, width]; alias binary_write is write [line, bit_vector, side, width]; procedure owrite (l : inout line; value : in bit_vector; justified : in side := right; field : in width := 0); alias octal_write is owrite [line, bit_vector, side, width]; procedure hwrite (l : inout line; value : in bit_vector; justified : in side := right; field : in width := 0); alias hex_write is hwrite [line, bit_vector, side, width]; end package;	gpl-3.0
nickg/nvc	test/regress/ieee1.vhd	5	688	library ieee; use ieee.std_logic_1164.all; entity ieee1 is end entity; architecture test of ieee1 is begin process is variable a, b, c : std_logic_vector(3 downto 0); variable d : std_logic_vector(5 downto 0); begin a := ( '0', '1', '0', '0' ); b := ( '1', '0', '1', '0' ); assert_a: assert ((a(3) or b(3)) = '1') report "a"; c := (a or b); assert c(3) = '1' report "c(3)"; assert c(0) = '0' report "c(0)"; assert_b: assert c = ( '1', '1', '1', '0' ) report "b"; d(4 downto 1) := (a or b); assert d = ( 'U', '1', '1', '1', '0', 'U' ); wait; end process; end architecture;	gpl-3.0
nickg/nvc	test/regress/textio7.vhd	1	1237	-- -- Test READ for real types -- entity textio7 is end entity; use std.textio.all; architecture test of textio7 is procedure check(value, expect : real) is variable l : line; begin assert abs(value - expect) < 0.0001 report "value=" & real'image(value) & " expect=" & real'image(expect) severity failure; write(l, value); writeline(output, l); deallocate(l); end procedure; begin main: process is variable r : real; variable l : line; begin l := new string'("1.23"); read(l, r); check(r, 1.23); deallocate(l); l := new string'("+4"); read(l, r); check(r, 4.0); deallocate(l); l := new string'("-0.001"); read(l, r); check(r, -0.001); deallocate(l); l := new string'("1.23e2"); read(l, r); check(r, 123.0); deallocate(l); l := new string'("1.994500e+03"); read(l, r); check(r, 1994.5); deallocate(l); l := new string'(" 1.994500e+03"); read(l, r); check(r, 1994.5); deallocate(l); wait; end process; end architecture;	gpl-3.0
nickg/nvc	test/jit/ieeewarn.vhd	1	485	package ieeewarn is constant enabled : boolean; end package; library nvc; use nvc.sim_pkg.all; package body ieeewarn is constant enabled : boolean := ieee_warnings; -- Should not be folded end package body; ------------------------------------------------------------------------------- entity ieeewarn_e is end entity; use work.ieeewarn; architecture a of ieeewarn_e is constant e : boolean := ieeewarn.enabled; -- Also shouldn't be folded begin end architecture;	gpl-3.0
Darkin47/Zynq-TX-UTT	Vivado_HLS/image_contrast_adj/solution1/impl/vhdl/project.srcs/sources_1/ip/doHistStretch_ap_fmul_2_max_dsp_32/xbip_bram18k_v3_0_2/hdl/xbip_bram18k_v3_0_vh_rfs.vhd	9	96728	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block obXXhxRlTaHjCpJV4uPTkRwgR3GpcvDfot0y8VTPyFxY1NMmmd9nxF2yYzxY4op4aE47wJsPh3ch Ifk4Z8Oulg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hmzRe/Qr+6nIcxuhkGdjIkYxpmHpO2VQJwayWf2lxaeB8TRqxhanf79tJphTIT7qZJNlaejd5WBb CQ1aMumla5wg4w9VFCJ3RfIX218tcMJOolbR14I3sidO+tsZwyzxKpPgnD/kd4T877IMOTrRvnIx 6PdsYAvnCf3xQFi7I2w= `protect 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Darkin47/Zynq-TX-UTT	Vivado_HLS/image_contrast_adj/solution1/impl/ip/tmp.srcs/sources_1/ip/doHistStretch_ap_fmul_2_max_dsp_32/xbip_bram18k_v3_0_2/hdl/xbip_bram18k_v3_0_vh_rfs.vhd	9	96728	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block obXXhxRlTaHjCpJV4uPTkRwgR3GpcvDfot0y8VTPyFxY1NMmmd9nxF2yYzxY4op4aE47wJsPh3ch Ifk4Z8Oulg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hmzRe/Qr+6nIcxuhkGdjIkYxpmHpO2VQJwayWf2lxaeB8TRqxhanf79tJphTIT7qZJNlaejd5WBb CQ1aMumla5wg4w9VFCJ3RfIX218tcMJOolbR14I3sidO+tsZwyzxKpPgnD/kd4T877IMOTrRvnIx 6PdsYAvnCf3xQFi7I2w= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block x0fTehxzghnOkOVVaF5ZPRso1LEjaAT4Ij9Za1bH3Oj/tMEqkw6sMVwuBHCx+9OVt2006A4ekCrO o6bGNZkP9ZTi3rPDQxJqDp8sg5+LnJfN79zDXHa15RdmKwVkjgf3nwhk4ny+EFYVb0Y54aV8MR9O zAXbiBIex84Cf/eo0y4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Ic1yv1cEiezEPDPgDJrMxh9C2VwWquV93tLinJarxYj+AmqpzKzI5K1H2OQZe7dbFN/MWnbwXkU3 VZ4HTFO2LNY6CAQ7agHefFUAhNGwX0QRTr7VGuTBYmzhsAHdeMqszybd5GeRvJKr6TK24gNATQrN nT2+HjrdVmQVjknT/su1Hfhm/cYUP3DwaHb/YUh3OhjGRMtE/ZGv2ChKMu2k7R9vmk5m/gNYJ2nE 08anLKgzUjVJXgO49+Y0G/wzgXuirkniHC7vyzJoNICrYz2RxJ622p1143uKw66xJyQQhrd2qIBT Jl/KhVnIuyuaJXAkrqwFPiigy+IHyR/snmCbug== `protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block LFux42eTG7g9Qxp237PDkKB2zzr08ZwHBtwQiK5Ci6HPYEcDQC5ARtEmy5K+FX4t3iGvCUCf7B7w WkQZxeuQq5Pu6G1UdqUYoZkYnIGvv/FBS58O80A7wz1hDYmIuCFtceYj9Pc2fMtYY1GsiMPo8DHK SwPJ/nBgoPhAul+T5S2sYyEyPKDBAHo2NS+ueZipFxaUmHpYSWv2JHPg5npmpprgScJtWI7t52dF UBV3yLc4chOAUHmW60pHDB60diNc3yRD3AWRAYuPmEcz797OhGqtq/0Gf/sQq2aaRuUjcjmv7RjV F0UQ0AGzw4qc2pK/6BN6qq92U2093f2LWTUUxA== `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mLsPIi/Ovuty+EZo5FSaXGTuskBHoX/S7M5BlV63QV6xgpHFSsvDZ9Xz7MoE307jvEG7GvmYbswJ 7MgGzFiYjlGDXcPhjku9wDs+Lmtnt1wDk3JEvFz7Qw/y4xrtBAKwKEzSCJWoN1fsuG/a1bHGMBW9 QIANQXT/XtWTLwK/eGYczVjN8LvuNEgutpT0ch7ABudM0jLaNAh74dH36yQSfhAmYUPLYgwDG1YG +aO/K3xh2vVQGtq+ZMzL4D6TG82lwyl33sG5zqpY5BEVhRG0s6EN4POou3ixu/Cj3dzQaQQh4MGA wnkI7caqlqGiTD7K0fMqU6D6LxVakb07jRj56Q== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", 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nickg/nvc	test/lower/access1.vhd	2	433	entity access1 is end entity; architecture test of access1 is type list; type list_ptr is access list; type list is record link : list_ptr; value : integer; end record; procedure list_add(l : inout list_ptr; v : integer) is variable n : list_ptr; begin n := new list; n.link := l; n.value := v; l := n; end procedure; begin end architecture;	gpl-3.0
Darkin47/Zynq-TX-UTT	Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/doHistStretch_fdiv_32ns_32ns_32_16.vhd	5	3100	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2016.1 -- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity doHistStretch_fdiv_32ns_32ns_32_16 is generic ( ID : integer := 2; NUM_STAGE : integer := 16; din0_WIDTH : integer := 32; din1_WIDTH : integer := 32; dout_WIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); din1 : in std_logic_vector(din1_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of doHistStretch_fdiv_32ns_32ns_32_16 is --------------------- Component --------------------- component doHistStretch_ap_fdiv_14_no_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); s_axis_b_tvalid : in std_logic; s_axis_b_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(31 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal b_tvalid : std_logic; signal b_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(31 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- doHistStretch_ap_fdiv_14_no_dsp_32_u : component doHistStretch_ap_fdiv_14_no_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, s_axis_b_tvalid => b_tvalid, s_axis_b_tdata => b_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; b_tvalid <= '1'; b_tdata <= din1_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; din1_buf1 <= din1; end if; end if; end process; end architecture;	gpl-3.0
nickg/nvc	test/jit/record2.vhd	1	804	package pack3 is type int_vector is array (natural range <>) of integer; type rec is record x : integer; y : integer; a : int_vector(1 to 3); z : integer; end record; constant r : rec; end package; package body pack3 is constant r : rec := (1, 2, (3, 4, 5), 6); end package body; ------------------------------------------------------------------------------- package pack4 is function sum_fields return integer; end package; use work.pack3.all; package body pack4 is function sum_fields return integer is variable sum : integer := r.x + r.y + r.z; begin --for i in r.a'range loop for i in 1 to 3 loop sum := sum + r.a(i); end loop; return sum; end function; end package body;	gpl-3.0
nickg/nvc	test/regress/issue352.vhd	1	1177	library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; -- use ieee.numeric_std.all; -- use ieee.std_logic_unsigned.all; entity issue352 is end entity; architecture arch of issue352 is signal FixRealKCM_F400_uid2_Rtemp : std_logic_vector(4 downto 0) := "11111"; signal R :std_logic_vector(5 downto 0); function check_dims(x : unsigned) return unsigned is alias ax : unsigned(1 to x'length) is x; variable s : string(1 to x'length); begin assert x'low >= unsigned'low; assert x'high <= unsigned'high; for i in 1 to x'length loop s(i) := std_logic'image(ax(i))(2); end loop; report s; return x; end function; begin -- R <= "000000" - (FixRealKCM_F400_uid2_Rtemp(4) & FixRealKCM_F400_uid2_Rtemp(4 downto 0)); R <= std_logic_vector(unsigned'(unsigned'("00000") - check_dims(unsigned (FixRealKCM_F400_uid2_Rtemp(4) & FixRealKCM_F400_uid2_Rtemp(4 downto 0))))); process is begin wait for 1 ns; assert R = "000001"; assert FixRealKCM_F400_uid2_Rtemp'last_event = time'high; wait; end process; end architecture;	gpl-3.0
nickg/nvc	test/regress/wait18.vhd	1	580	entity wait18 is end entity; library ieee; use ieee.std_logic_1164.all; architecture test of wait18 is signal clk, d, q : std_logic := '0'; begin process (clk) is begin if rising_edge(clk) then q <= d; end if; end process; process is begin clk <= '1' after 10 ns; d <= '1'; wait for 11 ns; assert q = '1'; wait; end process; postponed process (clk) is begin if rising_edge(clk) then assert q = '1'; end if; end process; end architecture;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_gpio_v2_0/58435b11/hdl/src/vhdl/axi_gpio.vhd	5	33293	------------------------------------------------------------------------------- -- AXI_GPIO - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_gpio.vhd -- Version: v2.0 -- Description: General Purpose I/O for AXI Interface -- ------------------------------------------------------------------------------- -- Structure: -- axi_gpio.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- gpio_core.vhd ------------------------------------------------------------------------------- -- Author: KSB -- History: -- ~~~~~~~~~~~~~~ -- KSB 07/28/09 -- ^^^^^^^^^^^^^^ -- First version of axi_gpio. Based on xps_gpio 2.00a -- -- KSB 05/20/10 -- ^^^^^^^^^^^^^^ -- Updated for holes in address range -- ~~~~~~~~~~~~~~ -- VB 09/23/10 -- ^^^^^^^^^^^^^^ -- Updated for axi_lite_ipfi_v1_01_a -- ~~~~~~~~~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; use std.textio.all; ------------------------------------------------------------------------------- -- AXI common package of the proc common library is used for different -- function declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- axi_gpio_v2_0 library is used for axi4 component declarations ------------------------------------------------------------------------------- library axi_lite_ipif_v3_0; use axi_lite_ipif_v3_0.ipif_pkg.calc_num_ce; use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE; use axi_lite_ipif_v3_0.ipif_pkg.SLV64_ARRAY_TYPE; ------------------------------------------------------------------------------- -- axi_gpio_v2_0 library is used for interrupt controller component -- declarations ------------------------------------------------------------------------------- library interrupt_control_v3_1; ------------------------------------------------------------------------------- -- axi_gpio_v2_0 library is used for axi_gpio component declarations ------------------------------------------------------------------------------- library axi_gpio_v2_0; ------------------------------------------------------------------------------- -- Defination of Generics : -- ------------------------------------------------------------------------------- -- AXI generics -- C_BASEADDR -- Base address of the core -- C_HIGHADDR -- Permits alias of address space -- by making greater than xFFF -- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits) -- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits) -- C_FAMILY -- XILINX FPGA family -- C_INSTANCE -- Instance name ot the core in the EDK system -- C_GPIO_WIDTH -- GPIO Data Bus width. -- C_ALL_INPUTS -- Inputs Only. -- C_INTERRUPT_PRESENT -- GPIO Interrupt. -- C_IS_BIDIR -- Selects gpio_io_i as input. -- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. -- C_TRI_DEFAULT -- GPIO_TRI Register reset value. -- C_IS_DUAL -- Dual Channel GPIO. -- C_ALL_INPUTS_2 -- Channel2 Inputs only. -- C_IS_BIDIR_2 -- Selects gpio2_io_i as input. -- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. -- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Defination of Ports -- ------------------------------------------------------------------------------- -- AXI signals -- s_axi_awaddr -- AXI Write address -- s_axi_awvalid -- Write address valid -- s_axi_awready -- Write address ready -- s_axi_wdata -- Write data -- s_axi_wstrb -- Write strobes -- s_axi_wvalid -- Write valid -- s_axi_wready -- Write ready -- s_axi_bresp -- Write response -- s_axi_bvalid -- Write response valid -- s_axi_bready -- Response ready -- s_axi_araddr -- Read address -- s_axi_arvalid -- Read address valid -- s_axi_arready -- Read address ready -- s_axi_rdata -- Read data -- s_axi_rresp -- Read response -- s_axi_rvalid -- Read valid -- s_axi_rready -- Read ready -- GPIO Signals -- gpio_io_i -- Channel 1 General purpose I/O in port -- gpio_io_o -- Channel 1 General purpose I/O out port -- gpio_io_t -- Channel 1 General purpose I/O -- TRI-STATE control port -- gpio2_io_i -- Channel 2 General purpose I/O in port -- gpio2_io_o -- Channel 2 General purpose I/O out port -- gpio2_io_t -- Channel 2 General purpose I/O -- TRI-STATE control port -- System Signals -- s_axi_aclk -- AXI Clock -- s_axi_aresetn -- AXI Reset -- ip2intc_irpt -- AXI GPIO Interrupt ------------------------------------------------------------------------------- entity axi_gpio is generic ( -- -- System Parameter C_FAMILY : string := "virtex7"; -- -- AXI Parameters C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9; C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32; -- -- GPIO Parameter C_GPIO_WIDTH : integer range 1 to 32 := 32; C_GPIO2_WIDTH : integer range 1 to 32 := 32; C_ALL_INPUTS : integer range 0 to 1 := 0; C_ALL_INPUTS_2 : integer range 0 to 1 := 0; C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 C_INTERRUPT_PRESENT : integer range 0 to 1 := 0; C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF"; C_IS_DUAL : integer range 0 to 1 := 0; C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF" ); port ( -- AXI interface Signals -------------------------------------------------- s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; -- Interrupt--------------------------------------------------------------- ip2intc_irpt : out std_logic; -- GPIO Signals------------------------------------------------------------ gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0) ); ------------------------------------------------------------------------------- -- fan-out attributes for XST ------------------------------------------------------------------------------- attribute MAX_FANOUT : string; attribute MAX_FANOUT of s_axi_aclk : signal is "10000"; attribute MAX_FANOUT of s_axi_aresetn : signal is "10000"; ------------------------------------------------------------------------------- -- Attributes for MPD file ------------------------------------------------------------------------------- attribute IP_GROUP : string ; attribute IP_GROUP of axi_gpio : entity is "LOGICORE"; attribute SIGIS : string ; attribute SIGIS of s_axi_aclk : signal is "Clk"; attribute SIGIS of s_axi_aresetn : signal is "Rst"; attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH"; end entity axi_gpio; ------------------------------------------------------------------------------- -- Architecture Section ------------------------------------------------------------------------------- architecture imp of axi_gpio is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ------------------------------------------------------------------------------- -- constant added for webtalk information ------------------------------------------------------------------------------- --function chr(sl: std_logic) return character is -- variable c: character; -- begin -- case sl is -- when '0' => c:= '0'; -- when '1' => c:= '1'; -- when 'Z' => c:= 'Z'; -- when 'U' => c:= 'U'; -- when 'X' => c:= 'X'; -- when 'W' => c:= 'W'; -- when 'L' => c:= 'L'; -- when 'H' => c:= 'H'; -- when '-' => c:= '-'; -- end case; -- return c; -- end chr; -- --function str(slv: std_logic_vector) return string is -- variable result : string (1 to slv'length); -- variable r : integer; -- begin -- r := 1; -- for i in slv'range loop -- result(r) := chr(slv(i)); -- r := r + 1; -- end loop; -- return result; -- end str; type bo2na_type is array (boolean) of natural; -- boolean to --natural conversion constant bo2na : bo2na_type := (false => 0, true => 1); ------------------------------------------------------------------------------- -- Function Declarations ------------------------------------------------------------------------------- type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean; ---------------------------------------------------------------------------- -- This function returns the number of elements that are true in -- a boolean array. ---------------------------------------------------------------------------- function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is variable n : natural := 0; begin for i in ba'range loop n := n + bo2na(ba(i)); end loop; return n; end; ---------------------------------------------------------------------------- -- This function returns a num_ce integer array that is constructed by -- taking only those elements of superset num_ce integer array -- that will be defined by the current case. -- The superset num_ce array is given by parameter num_ce_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE; num_ce_by_ard : INTEGER_ARRAY_TYPE ) return INTEGER_ARRAY_TYPE is variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := num_ce_by_ard(j); i := i+1; j := j+1; end loop; return res; end; ---------------------------------------------------------------------------- -- This function returns a addr_range array that is constructed by -- taking only those elements of superset addr_range array -- that will be defined by the current case. -- The superset addr_range array is given by parameter addr_range_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE; addr_range_by_ard : SLV64_ARRAY_TYPE ) return SLV64_ARRAY_TYPE is variable res : SLV64_ARRAY_TYPE(0 to 2num_set(defined_ards)-1); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := addr_range_by_ard(2j); res(i+1) := addr_range_by_ard((2j)+1); i := i+2; j := j+1; end loop; return res; end; function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE ) return std_logic_vector is variable res : std_logic_vector(0 to 31); begin res := (others => '0'); if defined_ards(defined_ards'right) then res(0 to 3) := "1111"; res(12) := '1'; res(13) := '1'; res(15) := '1'; else res(0 to 3) := "1111"; end if; return res; end; ---------------------------------------------------------------------------- -- This function returns the maximum width amongst the two GPIO Channels -- and if there is only one channel, it returns just the width of that -- channel. ---------------------------------------------------------------------------- function max_width( dual_channel : INTEGER; channel1_width : INTEGER; channel2_width : INTEGER ) return INTEGER is begin if (dual_channel = 0) then return channel1_width; else if (channel1_width > channel2_width) then return channel1_width; else return channel2_width; end if; end if; end; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant INTR_TYPE : integer := 5; constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100"; constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF"; constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F"; constant MAX_GPIO_WIDTH : integer := max_width (C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH); constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := qual_ard_addr_range_array( (true,C_INTERRUPT_PRESENT=1), (ZERO_ADDR_PAD & X"00000000", ZERO_ADDR_PAD & GPIO_HIGHADDR, ZERO_ADDR_PAD & INTR_BASEADDR, ZERO_ADDR_PAD & INTR_HIGHADDR ) ); constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := qual_ard_num_ce_array( (true,C_INTERRUPT_PRESENT=1), (4,16) ); constant ARD_CE_VALID : std_logic_vector(0 to 31) := qual_ard_ce_valid( (true,C_INTERRUPT_PRESENT=1) ); constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1)) := (others => 5); constant C_USE_WSTRB : integer := 0; constant C_DPHASE_TIMEOUT : integer := 8; ------------------------------------------------------------------------------- -- Signal and Type Declarations ------------------------------------------------------------------------------- signal ip2bus_intrevent : std_logic_vector(0 to 1); signal GPIO_xferAck_i : std_logic; signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); -- IPIC Used Signals signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1); signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_rnw : std_logic; signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na (C_INTERRUPT_PRESENT=1)); signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15); signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15); signal intr_wr_ce_or_reduce : std_logic; signal intr_rd_ce_or_reduce : std_logic; signal ip2Bus_RdAck_intr_reg_hole : std_logic; signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic; signal ip2Bus_WrAck_intr_reg_hole : std_logic; signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic; signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1); signal bus2ip_clk : std_logic; signal bus2ip_reset : std_logic; signal bus2ip_resetn : std_logic; signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal intr2bus_wrack : std_logic; signal intr2bus_rdack : std_logic; signal intr2bus_error : std_logic; signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_wrack_i : std_logic; signal ip2bus_wrack_i_D1 : std_logic; signal ip2bus_rdack_i : std_logic; signal ip2bus_rdack_i_D1 : std_logic; signal ip2bus_error_i : std_logic; signal IP2INTC_Irpt_i : std_logic; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- begin -- architecture IMP AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, C_FAMILY => C_FAMILY ) port map ( S_AXI_ACLK => s_axi_aclk, S_AXI_ARESETN => s_axi_aresetn, S_AXI_AWADDR => s_axi_awaddr, S_AXI_AWVALID => s_axi_awvalid, S_AXI_AWREADY => s_axi_awready, S_AXI_WDATA => s_axi_wdata, S_AXI_WSTRB => s_axi_wstrb, S_AXI_WVALID => s_axi_wvalid, S_AXI_WREADY => s_axi_wready, S_AXI_BRESP => s_axi_bresp, S_AXI_BVALID => s_axi_bvalid, S_AXI_BREADY => s_axi_bready, S_AXI_ARADDR => s_axi_araddr, S_AXI_ARVALID => s_axi_arvalid, S_AXI_ARREADY => s_axi_arready, S_AXI_RDATA => s_axi_rdata, S_AXI_RRESP => s_axi_rresp, S_AXI_RVALID => s_axi_rvalid, S_AXI_RREADY => s_axi_rready, -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, Bus2IP_Resetn => bus2ip_resetn, IP2Bus_Data => ip2bus_data_i_D1, IP2Bus_WrAck => ip2bus_wrack_i_D1, IP2Bus_RdAck => ip2bus_rdack_i_D1, --IP2Bus_WrAck => ip2bus_wrack_i, --IP2Bus_RdAck => ip2bus_rdack_i, IP2Bus_Error => ip2bus_error_i, Bus2IP_Addr => bus2ip_addr, Bus2IP_Data => bus2ip_data, Bus2IP_RNW => bus2ip_rnw, Bus2IP_BE => bus2ip_be, Bus2IP_CS => bus2ip_cs, Bus2IP_RdCE => bus2ip_rdce, Bus2IP_WrCE => bus2ip_wrce ); ip2bus_data_i <= intr2bus_data or ip2bus_data; ip2bus_wrack_i <= intr2bus_wrack or (GPIO_xferAck_i and not(bus2ip_rnw)) or ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range ip2bus_rdack_i <= intr2bus_rdack or (GPIO_xferAck_i and bus2ip_rnw) or ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2bus_wrack_i_D1 <= '0'; ip2bus_rdack_i_D1 <= '0'; ip2bus_data_i_D1 <= (others => '0'); else ip2bus_wrack_i_D1 <= ip2bus_wrack_i; ip2bus_rdack_i_D1 <= ip2bus_rdack_i; ip2bus_data_i_D1 <= ip2bus_data_i; end if; end if; end process I_WRACK_RDACK_DELAYS; ip2bus_error_i <= intr2bus_error; ---------------------- --REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of -- the core. ---------------------- REG_RESET_FROM_IPIF: process (s_axi_aclk) is begin if(s_axi_aclk'event and s_axi_aclk = '1') then bus2ip_reset <= not(bus2ip_resetn); end if; end process REG_RESET_FROM_IPIF; --------------------------------------------------------------------------- -- Interrupts --------------------------------------------------------------------------- INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate constant NUM_IPIF_IRPT_SRC : natural := 1; constant NUM_CE : integer := 16; signal errack_reserved : std_logic_vector(0 to 1); signal ipif_lvl_interrupts : std_logic_vector(0 to NUM_IPIF_IRPT_SRC-1); begin ipif_lvl_interrupts <= (others => '0'); errack_reserved <= (others => '0'); --- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0' & bus2ip_rdce(14) & "00000"; Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0' & bus2ip_wrce(14) & "00000"; intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or Bus2IP_RdCE(13) or or_reduce(Bus2IP_RdCE(15 to 19)); intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or bus2ip_wrce(13) or or_reduce(bus2ip_wrce(15 to 19)); I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_RdAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole_d1 <= '0'; else ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce; ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and (not ip2Bus_RdAck_intr_reg_hole_d1); end if; end if; end process I_READ_ACK_INTR_HOLES; I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_WrAck_intr_reg_hole_d1 <= '0'; else ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce; ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and (not ip2Bus_WrAck_intr_reg_hole_d1); end if; end if; end process I_WRITE_ACK_INTR_HOLES; INTERRUPT_CONTROL_I : entity interrupt_control_v3_1.interrupt_control generic map ( C_NUM_CE => NUM_CE, C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC, C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, C_INCLUDE_DEV_PENCODER => false, C_INCLUDE_DEV_ISC => false, C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH ) port map ( -- Inputs From the IPIF Bus Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Reset => bus2ip_reset, Bus2IP_Data => bus2ip_data, Bus2IP_BE => bus2ip_be, Interrupt_RdCE => Intrpt_bus2ip_rdce, Interrupt_WrCE => Intrpt_bus2ip_wrce, -- Interrupt inputs from the IPIF sources that will -- get registered in this design IPIF_Reg_Interrupts => errack_reserved, -- Level Interrupt inputs from the IPIF sources IPIF_Lvl_Interrupts => ipif_lvl_interrupts, -- Inputs from the IP Interface IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range), -- Final Device Interrupt Output Intr2Bus_DevIntr => IP2INTC_Irpt_i, -- Status Reply Outputs to the Bus Intr2Bus_DBus => intr2bus_data, Intr2Bus_WrAck => intr2bus_wrack, Intr2Bus_RdAck => intr2bus_rdack, Intr2Bus_Error => intr2bus_error, Intr2Bus_Retry => open, Intr2Bus_ToutSup => open ); -- registering interrupt I_INTR_DELAY: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2intc_irpt <= '0'; else ip2intc_irpt <= IP2INTC_Irpt_i; end if; end if; end process I_INTR_DELAY; end generate INTR_CTRLR_GEN; ----------------------------------------------------------------------- -- Assigning the intr2bus signal to zero's when interrupt is not -- present ----------------------------------------------------------------------- REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate intr2bus_data <= (others => '0'); ip2intc_irpt <= '0'; intr2bus_error <= '0'; intr2bus_rdack <= '0'; intr2bus_wrack <= '0'; ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole <= '0'; end generate REMOVE_INTERRUPT; gpio_core_1 : entity axi_gpio_v2_0.gpio_core generic map ( C_DW => C_S_AXI_DATA_WIDTH, C_AW => C_S_AXI_ADDR_WIDTH, C_GPIO_WIDTH => C_GPIO_WIDTH, C_GPIO2_WIDTH => C_GPIO2_WIDTH, C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH, C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT, C_DOUT_DEFAULT => C_DOUT_DEFAULT, C_TRI_DEFAULT => C_TRI_DEFAULT, C_IS_DUAL => C_IS_DUAL, C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2, C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2, C_FAMILY => C_FAMILY ) port map ( Clk => Bus2IP_Clk, Rst => bus2ip_reset, ABus_Reg => Bus2IP_Addr, BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1), DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1), RNW_Reg => Bus2IP_RNW, GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1), GPIO_xferAck => GPIO_xferAck_i, GPIO_Select => bus2ip_cs(0), GPIO_intr => ip2bus_intrevent(0), GPIO2_intr => ip2bus_intrevent(1), GPIO_IO_I => gpio_io_i, GPIO_IO_O => gpio_io_o, GPIO_IO_T => gpio_io_t, GPIO2_IO_I => gpio2_io_i, GPIO2_IO_O => gpio2_io_o, GPIO2_IO_T => gpio2_io_t ); Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1' and bus2ip_addr (5) = '0'else Bus2IP2_Data_i; BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate Bus2IP1_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH); end generate BUS_CONV_ch1; BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate Bus2IP2_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH); end generate BUS_CONV_ch2; end architecture imp;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/lib_fifo_v1_0/ca55fafe/hdl/src/vhdl/async_fifo_fg.vhd	11	123226	-- async_fifo_fg.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- ********************************************************************* -- ------------------------------------------------------------------------------- -- Filename: async_fifo_fg.vhd -- -- Description: -- This HDL file adapts the legacy CoreGen Async FIFO interface to the new -- FIFO Generator async FIFO interface. This wrapper facilitates the "on -- the fly" call of FIFO Generator during design implementation. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- async_fifo_fg.vhd -- \| -- \|-- fifo_generator_v4_3 -- \| -- \|-- fifo_generator_v9_3 -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- Revision: $Revision: 1.5.2.68 $ -- Date: $1/15/2008$ -- -- History: -- DET 1/15/2008 Initial Version -- -- DET 7/30/2008 for EDK 11.1 -- ~~~~~~ -- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator -- feature of specifing 2N depth of FIFO, Legacy CoreGen Async FIFOs -- only allowed (2N)-1 depth specification. Parameter is defalted to -- the legacy CoreGen method so current users are not impacted. -- - Incorporated calculation and assignment corrections for the Read and -- Write Pointer Widths. -- - Upgraded to FIFO Generator Version 4.3. -- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO -- Generator instance. -- ^^^^^^ -- -- MSH and DET 3/2/2009 For Lava SP2 -- ~~~~~~ -- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6 -- devices. -- - IfGen used so that legacy FPGA families still use Fifo Generator -- version 4.3. -- ^^^^^^ -- -- DET 2/9/2010 for EDK 12.1 -- ~~~~~~ -- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3. -- ^^^^^^ -- -- DET 3/10/2010 For EDK 12.x -- ~~~~~~ -- -- Per CR553307 -- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1. -- ^^^^^^ -- -- DET 6/18/2010 EDK_MS2 -- ~~~~~~ -- -- Per IR565916 -- - Added derivative part type checks for S6 or V6. -- ^^^^^^ -- -- DET 8/30/2010 EDK_MS4 -- ~~~~~~ -- -- Per CR573867 -- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2. -- - Added all of the AXI parameters and ports. They are not used -- in this application. -- - Updated method for derivative part support using new family -- aliasing function in family_support.vhd. -- - Incorporated an implementation to deal with unsupported FPGA -- parts passed in on the C_FAMILY parameter. -- ^^^^^^ -- -- DET 10/4/2010 EDK 13.1 -- ~~~~~~ -- - Updated the FIFO Generator version from V7.2 to 7.3. -- ^^^^^^ -- -- DET 12/8/2010 EDK 13.1 -- ~~~~~~ -- -- Per CR586109 -- - Updated the FIFO Generator version from V7.3 to 8.1. -- ^^^^^^ -- -- DET 3/2/2011 EDK 13.2 -- ~~~~~~ -- -- Per CR595473 -- - Update to use fifo_generator_v8_2 -- ^^^^^^ -- -- -- RBODDU 08/18/2011 EDK 13.3 -- ~~~~~~ -- - Update to use fifo_generator_v8_3 -- ^^^^^^ -- -- RBODDU 06/07/2012 EDK 14.2 -- ~~~~~~ -- - Update to use fifo_generator_v9_1 -- ^^^^^^ -- RBODDU 06/11/2012 EDK 14.4 -- ~~~~~~ -- - Update to use fifo_generator_v9_2 -- ^^^^^^ -- RBODDU 07/12/2012 EDK 14.5 -- ~~~~~~ -- - Update to use fifo_generator_v9_3 -- ^^^^^^ -- RBODDU 07/12/2012 EDK 14.5 -- ~~~~~~ -- - Update to use fifo_generator_v12_0 -- - Added sleep, wr_rst_busy, and rd_rst_busy signals -- - Changed FULL_FLAGS_RST_VAL to '1' -- ^^^^^^ -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library fifo_generator_v12_0; use fifo_generator_v12_0.all; --library lib_fifo_v1_0; --use lib_fifo_v1_0.lib_fifo_pkg.all; --use lib_fifo_v1_0.family_support.all; -- synopsys translate_off --library XilinxCoreLib; --use XilinxCoreLib.all; -- synopsys translate_on ------------------------------------------------------------------------------- entity async_fifo_fg is generic ( C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2N depth C_FAMILY : String := "virtex5"; -- new for FIFO Gen C_DATA_WIDTH : integer := 16; C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG C_FIFO_DEPTH : integer := 15; C_HAS_ALMOST_EMPTY : integer := 1 ; C_HAS_ALMOST_FULL : integer := 1 ; C_HAS_RD_ACK : integer := 0 ; C_HAS_RD_COUNT : integer := 1 ; C_HAS_RD_ERR : integer := 0 ; C_HAS_WR_ACK : integer := 0 ; C_HAS_WR_COUNT : integer := 1 ; C_HAS_WR_ERR : integer := 0 ; C_RD_ACK_LOW : integer := 0 ; C_RD_COUNT_WIDTH : integer := 3 ; C_RD_ERR_LOW : integer := 0 ; C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0 C_PRELOAD_REGS : integer := 0 ; C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1 C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM C_WR_ACK_LOW : integer := 0 ; C_WR_COUNT_WIDTH : integer := 3 ; C_WR_ERR_LOW : integer := 0 ; C_SYNCHRONIZER_STAGE : integer := 2 -- valid values are 0 to 8 ); port ( Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); Wr_en : in std_logic := '1'; Wr_clk : in std_logic := '1'; Rd_en : in std_logic := '0'; Rd_clk : in std_logic := '1'; Ainit : in std_logic := '1'; Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0); Full : out std_logic; Empty : out std_logic; Almost_full : out std_logic; Almost_empty : out std_logic; Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0); Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0); Rd_ack : out std_logic; Rd_err : out std_logic; Wr_ack : out std_logic; Wr_err : out std_logic ); end entity async_fifo_fg; architecture implementation of async_fifo_fg is -- Function delarations ------------------------------------------------------------------- -- Function -- -- Function Name: GetMemType -- -- Function Description: -- Generates the required integer value for the FG instance assignment -- of the C_MEMORY_TYPE parameter. Derived from -- the input memory type parameter C_USE_BLOCKMEM. -- -- FIFO Generator values -- 0 = Any -- 1 = BRAM -- 2 = Distributed Memory -- 3 = Shift Registers -- ------------------------------------------------------------------- function GetMemType (inputmemtype : integer) return integer is Variable memtype : Integer := 0; begin If (inputmemtype = 0) Then -- distributed Memory memtype := 2; else memtype := 1; -- BRAM End if; return(memtype); end function GetMemType; function log2(x : natural) return integer is variable i : integer := 0; variable val: integer := 1; begin if x = 0 then return 0; else for j in 0 to 29 loop -- for loop for XST if val >= x then null; else i := i+1; val := val2; end if; end loop; -- Fix per CR520627 XST was ignoring this anyway and printing a -- Warning in SRP file. This will get rid of the warning and not -- impact simulation. -- synthesis translate_off assert val >= x report "Function log2 received argument larger" & " than its capability of 2^30. " severity failure; -- synthesis translate_on return i; end if; end function log2; -- Constant Declarations ---------------------------------------------- -- C_FAMILY is directly passed. No need to have family_support function Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd -- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily")); -- Proc_common supports all families Constant FAMILY_IS_SUPPORTED : boolean := true; --not(FAMILY_NOT_SUPPORTED); -- Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or -- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or -- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and -- FAMILY_IS_SUPPORTED; -- Changing this to true Constant FAM_IS_NOT_S3_V4_V5 : boolean := true; -- Get the integer value for a Block memory type fifo generator call Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM); -- Set the required integer value for the FG instance assignment -- of the C_IMPLEMENTATION_TYPE parameter. Derived from -- the input memory type parameter C_MEMORY_TYPE. -- -- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO) -- 1 = Common Clock Shift Register (Synchronous FIFO) -- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO) -- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls -- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls -- Constant FG_IMP_TYPE : integer := 2; --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal PROG_FULL : std_logic; signal PROG_EMPTY : std_logic; signal SBITERR : std_logic; signal DBITERR : std_logic; signal WR_RST_BUSY : std_logic; signal RD_RST_BUSY : std_logic; signal S_AXI_AWREADY : std_logic; signal S_AXI_WREADY : std_logic; signal S_AXI_BID : std_logic_vector(3 DOWNTO 0); signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_BUSER : std_logic_vector(0 downto 0); signal S_AXI_BVALID : std_logic; -- AXI Full/Lite Master Write Channel (Read side) signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0); signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWUSER : std_logic_vector(0 downto 0); signal M_AXI_AWVALID : std_logic; signal M_AXI_WID : std_logic_vector(3 DOWNTO 0); signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0); signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0); signal M_AXI_WLAST : std_logic; signal M_AXI_WUSER : std_logic_vector(0 downto 0); signal M_AXI_WVALID : std_logic; signal M_AXI_BREADY : std_logic; -- AXI Full/Lite Slave Read Channel (Write side) signal S_AXI_ARREADY : std_logic; signal S_AXI_RID : std_logic_vector(3 DOWNTO 0); signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0); signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_RLAST : std_logic; signal S_AXI_RUSER : std_logic_vector(0 downto 0); signal S_AXI_RVALID : std_logic; -- AXI Full/Lite Master Read Channel (Read side) signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0); signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARUSER : std_logic_vector(0 downto 0); signal M_AXI_ARVALID : std_logic; signal M_AXI_RREADY : std_logic; -- AXI Streaming Slave Signals (Write side) signal S_AXIS_TREADY : std_logic; -- AXI Streaming Master Signals (Read side) signal M_AXIS_TVALID : std_logic; signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0); signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TLAST : std_logic; signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0); signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_SBITERR : std_logic; signal AXI_AW_DBITERR : std_logic; signal AXI_AW_OVERFLOW : std_logic; signal AXI_AW_UNDERFLOW : std_logic; signal AXI_AW_PROG_FULL : STD_LOGIC; signal AXI_AW_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Data Channel Signals signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_SBITERR : std_logic; signal AXI_W_DBITERR : std_logic; signal AXI_W_OVERFLOW : std_logic; signal AXI_W_UNDERFLOW : std_logic; signal AXI_W_PROG_FULL : STD_LOGIC; signal AXI_W_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Response Channel Signals signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_SBITERR : std_logic; signal AXI_B_DBITERR : std_logic; signal AXI_B_OVERFLOW : std_logic; signal AXI_B_UNDERFLOW : std_logic; signal AXI_B_PROG_FULL : STD_LOGIC; signal AXI_B_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Address Channel Signals signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_SBITERR : std_logic; signal AXI_AR_DBITERR : std_logic; signal AXI_AR_OVERFLOW : std_logic; signal AXI_AR_UNDERFLOW : std_logic; signal AXI_AR_PROG_FULL : STD_LOGIC; signal AXI_AR_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Data Channel Signals signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_SBITERR : std_logic; signal AXI_R_DBITERR : std_logic; signal AXI_R_OVERFLOW : std_logic; signal AXI_R_UNDERFLOW : std_logic; signal AXI_R_PROG_FULL : STD_LOGIC; signal AXI_R_PROG_EMPTY : STD_LOGIC; -- AXI Streaming FIFO Related Signals signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_SBITERR : std_logic; signal AXIS_DBITERR : std_logic; signal AXIS_OVERFLOW : std_logic; signal AXIS_UNDERFLOW : std_logic; signal AXIS_PROG_FULL : STD_LOGIC; signal AXIS_PROG_EMPTY : STD_LOGIC; begin --(architecture implementation) ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_FAMILY -- -- If Generate Description: -- This IfGen is implemented if an unsupported FPGA family -- is passed in on the C_FAMILY parameter, -- ------------------------------------------------------------ -- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate -- begin -- synthesis translate_off ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_ASSERTION -- -- Process Description: -- Generate a simulation error assertion for an unsupported -- FPGA family string passed in on the C_FAMILY parameter. -- ------------------------------------------------------------- -- DO_ASSERTION : process -- begin -- Wait until second rising wr clock edge to issue assertion -- Wait until Wr_clk = '1'; -- wait until Wr_clk = '0'; -- Wait until Wr_clk = '1'; -- Report an error in simulation environment -- assert FALSE report "****** UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!" -- severity ERROR; -- Wait; -- halt this process -- end process DO_ASSERTION; -- synthesis translate_on -- Tie outputs to logic low or logic high as required -- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Full <= '0' ; -- : out std_logic; -- Empty <= '1' ; -- : out std_logic; -- Almost_full <= '0' ; -- : out std_logic; -- Almost_empty <= '0' ; -- : out std_logic; -- Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0); -- Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0); -- Rd_ack <= '0' ; -- : out std_logic; -- Rd_err <= '1' ; -- : out std_logic; -- Wr_ack <= '0' ; -- : out std_logic; -- Wr_err <= '1' ; -- : out std_logic -- end generate GEN_NO_FAMILY; ------------------------------------------------------------ -- If Generate -- -- Label: LEGACY_COREGEN_DEPTH -- -- If Generate Description: -- This IfGen implements the FIFO Generator call where -- the User specified depth and count widths follow the -- legacy CoreGen Async FIFO requirements of depth being -- (2N)-1 and the count widths set to reflect the (2N)-1 -- FIFO depth. -- -- Special Note: -- The legacy CoreGen Async FIFOs would only support fifo depths of (2n)-1 -- and the Dcount widths were 1 less than if a full 2n depth were supported. -- Thus legacy IP will be calling this wrapper with the (2n)-1 FIFo depths -- specified and the Dcount widths smaller by 1 bit. -- This wrapper file has to account for this since the new FIFO Generator -- does not follow this convention for Async FIFOs and expects depths to -- be specified in full 2n values. -- ------------------------------------------------------------ LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and FAMILY_IS_SUPPORTED) generate -- IfGen Constant Declarations ------------- -- See Special Note above for reasoning behind -- this adjustment of the requested FIFO depth and data count -- widths. Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1; Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH; Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH; -- The programable thresholds are not used so this is housekeeping. Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3; Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4; -- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core -- must be in the range of 4 thru 22. The setting is dependant upon the -- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs -- previous to development of fifo generator do not support separate read and -- write fifo widths (and depths dependant upon the widths) both of the pointer value -- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for -- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it -- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 - -- Asynchronous FIFO v6.1) Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH); Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH); -- Constant zeros for programmable threshold inputs signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- IfGen Signal Declarations -------------- Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0); Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0); --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0); begin -- Rip the LS bits of the write data count and assign to Write Count -- output port Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0); -- Rip the LS bits of the read data count and assign to Read Count -- output port Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0); ------------------------------------------------------------ -- If Generate -- -- Label: V6_S6_AND_LATER -- -- If Generate Description: -- This IFGen Implements the FIFO using fifo_generator_v9_3 -- for FPGA Families that are Virtex-6, Spartan-6, and later. -- ------------------------------------------------------------ V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate begin ------------------------------------------------------------------------------- -- Instantiate the generalized FIFO Generator instance -- -- NOTE: -- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!! -- This is a Coregen FIFO Generator Call module for -- legacy BRAM implementations of an Async FIFo. -- ------------------------------------------------------------------------------- I_ASYNC_FIFO_BRAM : entity fifo_generator_v12_0.fifo_generator_v12_0 generic map( C_COMMON_CLOCK => 0, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => C_DATA_WIDTH, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => C_DATA_WIDTH, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_FAMILY => FAMILY_TO_USE, C_FULL_FLAGS_RST_VAL => 1, C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY, C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 0, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => C_HAS_WR_ERR, C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_HAS_UNDERFLOW => C_HAS_RD_ERR, C_HAS_VALID => C_HAS_RD_ACK, C_HAS_WR_ACK => C_HAS_WR_ACK, C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => FG_IMP_TYPE, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => FG_MEM_TYPE, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => C_WR_ERR_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129 C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129 C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL, C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH, C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH, C_UNDERFLOW_LOW => C_RD_ERR_LOW, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129 C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH, C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE, -- AXI Interface related parameters start here C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0; C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0; C_HAS_SLAVE_CE => 0, -- : integer := 0; C_HAS_MASTER_CE => 0, -- : integer := 0; C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0; C_USE_COMMON_OVERFLOW => 0, -- : integer := 0; C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0; C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH => 4 , -- : integer := 0; C_AXI_ADDR_WIDTH => 32, -- : integer := 0; C_AXI_DATA_WIDTH => 64, -- : integer := 0; C_AXI_LEN_WIDTH => 8, -- : integer := 8; C_AXI_LOCK_WIDTH => 2, -- : integer := 2; C_HAS_AXI_ID => 0, -- : integer := 0; C_HAS_AXI_AWUSER => 0 , -- : integer := 0; C_HAS_AXI_WUSER => 0 , -- : integer := 0; C_HAS_AXI_BUSER => 0 , -- : integer := 0; C_HAS_AXI_ARUSER => 0 , -- : integer := 0; C_HAS_AXI_RUSER => 0 , -- : integer := 0; C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0; C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0; C_AXI_WUSER_WIDTH => 1 , -- : integer := 0; C_AXI_BUSER_WIDTH => 1 , -- : integer := 0; C_AXI_RUSER_WIDTH => 1 , -- : integer := 0; -- AXI Streaming C_HAS_AXIS_TDATA => 0 , -- : integer := 0; C_HAS_AXIS_TID => 0 , -- : integer := 0; C_HAS_AXIS_TDEST => 0 , -- : integer := 0; C_HAS_AXIS_TUSER => 0 , -- : integer := 0; C_HAS_AXIS_TREADY => 1 , -- : integer := 0; C_HAS_AXIS_TLAST => 0 , -- : integer := 0; C_HAS_AXIS_TSTRB => 0 , -- : integer := 0; C_HAS_AXIS_TKEEP => 0 , -- : integer := 0; C_AXIS_TDATA_WIDTH => 64, -- : integer := 1; C_AXIS_TID_WIDTH => 8 , -- : integer := 1; C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1; C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1; C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1; C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Data FIFO C_APPLICATION_TYPE_WACH => 0, -- : integer := 0; C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0; C_APPLICATION_TYPE_RACH => 0, -- : integer := 0; C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH => 0, -- : integer := 0; C_USE_ECC_WDCH => 0, -- : integer := 0; C_USE_ECC_WRCH => 0, -- : integer := 0; C_USE_ECC_RACH => 0, -- : integer := 0; C_USE_ECC_RDCH => 0, -- : integer := 0; C_USE_ECC_AXIS => 0, -- : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH => 32, -- : integer := 1; C_DIN_WIDTH_WDCH => 64, -- : integer := 1; C_DIN_WIDTH_WRCH => 2 , -- : integer := 1; C_DIN_WIDTH_RACH => 32, -- : integer := 1; C_DIN_WIDTH_RDCH => 64, -- : integer := 1; C_DIN_WIDTH_AXIS => 1 , -- : integer := 1; C_WR_DEPTH_WACH => 16 , -- : integer := 16; C_WR_DEPTH_WDCH => 1024, -- : integer := 16; C_WR_DEPTH_WRCH => 16 , -- : integer := 16; C_WR_DEPTH_RACH => 16 , -- : integer := 16; C_WR_DEPTH_RDCH => 1024, -- : integer := 16; C_WR_DEPTH_AXIS => 1024, -- : integer := 16; C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4; C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0; C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0; C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0; C_REG_SLICE_MODE_WACH => 0, -- : integer := 0; C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0; C_REG_SLICE_MODE_RACH => 0, -- : integer := 0; C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0 ) port map ( backup => '0', backup_marker => '0', clk => '0', rst => Ainit, srst => '0', wr_clk => Wr_clk, wr_rst => Ainit, rd_clk => Rd_clk, rd_rst => Ainit, din => Din, wr_en => Wr_en, rd_en => Rd_en, prog_empty_thresh => PROG_RDTHRESH_ZEROS, prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, prog_full_thresh => PROG_WRTHRESH_ZEROS, prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, int_clk => '0', injectdbiterr => '0', -- new FG 5.1/5.2 injectsbiterr => '0', -- new FG 5.1/5.2 sleep => '0', dout => Dout, full => Full, almost_full => Almost_full, wr_ack => Wr_ack, overflow => Wr_err, empty => Empty, almost_empty => Almost_empty, valid => Rd_ack, underflow => Rd_err, data_count => DATA_COUNT, rd_data_count => sig_full_fifo_rdcnt, wr_data_count => sig_full_fifo_wrcnt, prog_full => PROG_FULL, prog_empty => PROG_EMPTY, sbiterr => SBITERR, dbiterr => DBITERR, wr_rst_busy => WR_RST_BUSY, rd_rst_busy => RD_RST_BUSY, -- AXI Global Signal m_aclk => '0', -- : IN std_logic := '0'; s_aclk => '0', -- : IN std_logic := '0'; s_aresetn => '0', -- : IN std_logic := '0'; m_aclk_en => '0', -- : IN std_logic := '0'; s_aclk_en => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Slave Write Channel (write side) s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awvalid => '0', -- : IN std_logic := '0'; s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic; s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wlast => '0', -- : IN std_logic := '0'; s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wvalid => '0', -- : IN std_logic := '0'; s_axi_wready => S_AXI_WREADY, -- : OUT std_logic; s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0); s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic; s_axi_bready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Write Channel (Read side) m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0); m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic; m_axi_awready => '0', -- : IN std_logic := '0'; m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0); m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic; m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0); m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic; m_axi_wready => '0', -- : IN std_logic := '0'; m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bvalid => '0', -- : IN std_logic := '0'; m_axi_bready => M_AXI_BREADY, -- : OUT std_logic; -- AXI Full/Lite Slave Read Channel (Write side) s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arvalid => '0', -- : IN std_logic := '0'; s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic; s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic; s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0); s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic; s_axi_rready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Read Channel (Read side) m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0); m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic; m_axi_arready => '0', -- : IN std_logic := '0'; m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rlast => '0', -- : IN std_logic := '0'; m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rvalid => '0', -- : IN std_logic := '0'; m_axi_rready => M_AXI_RREADY, -- : OUT std_logic; -- AXI Streaming Slave Signals (Write side) s_axis_tvalid => '0', -- : IN std_logic := '0'; s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic; s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tlast => '0', -- : IN std_logic := '0'; s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- AXI Streaming Master Signals (Read side) m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic; m_axis_tready => '0', -- : IN std_logic := '0'; m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0); m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0); m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0); m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic; m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0); m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0); m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals axi_aw_injectsbiterr => '0', -- : IN std_logic := '0'; axi_aw_injectdbiterr => '0', -- : IN std_logic := '0'; axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic; axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic; axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic; axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic; axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Data Channel Signals axi_w_injectsbiterr => '0', -- : IN std_logic := '0'; axi_w_injectdbiterr => '0', -- : IN std_logic := '0'; axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic; axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic; axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic; axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic; axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Response Channel Signals axi_b_injectsbiterr => '0', -- : IN std_logic := '0'; axi_b_injectdbiterr => '0', -- : IN std_logic := '0'; axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic; axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic; axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic; axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic; axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Address Channel Signals axi_ar_injectsbiterr => '0', -- : IN std_logic := '0'; axi_ar_injectdbiterr => '0', -- : IN std_logic := '0'; axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic; axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic; axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic; axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic; axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Data Channel Signals axi_r_injectsbiterr => '0', -- : IN std_logic := '0'; axi_r_injectdbiterr => '0', -- : IN std_logic := '0'; axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic; axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic; axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic; axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic; axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Streaming FIFO Related Signals axis_injectsbiterr => '0', -- : IN std_logic := '0'; axis_injectdbiterr => '0', -- : IN std_logic := '0'; axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic; axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic; axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic; axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0'; axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1'; ); end generate V6_S6_AND_LATER; end generate LEGACY_COREGEN_DEPTH; ------------------------------------------------------------ -- If Generate -- -- Label: USE_2N_DEPTH -- -- If Generate Description: -- This IfGen implements the FIFO Generator call where -- the User may specify depth and count widths of 2N -- for Async FIFOs The associated count widths are set to -- reflect the 2**N FIFO depth. -- ------------------------------------------------------------ USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and FAMILY_IS_SUPPORTED) generate -- The programable thresholds are not used so this is housekeeping. Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3; Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4; Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH); Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH); -- Constant zeros for programmable threshold inputs signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- Signals Declarations Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0); Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0); --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0); begin -- Rip the LS bits of the write data count and assign to Write Count -- output port Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0); -- Rip the LS bits of the read data count and assign to Read Count -- output port Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0); ------------------------------------------------------------ -- If Generate -- -- Label: V6_S6_AND_LATER -- -- If Generate Description: -- This IFGen Implements the FIFO using fifo_generator_v9_3 -- for FPGA Families that are Virtex-6, Spartan-6, and later. -- ------------------------------------------------------------ V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate begin ------------------------------------------------------------------------------- -- Instantiate the generalized FIFO Generator instance -- -- NOTE: -- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!! -- This is a Coregen FIFO Generator Call module for -- legacy BRAM implementations of an Async FIFo. -- ------------------------------------------------------------------------------- I_ASYNC_FIFO_BRAM : entity fifo_generator_v12_0.fifo_generator_v12_0 generic map( C_COMMON_CLOCK => 0, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => C_DATA_WIDTH, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => C_DATA_WIDTH, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_FAMILY => FAMILY_TO_USE, C_FULL_FLAGS_RST_VAL => 1, C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY, C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 0, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => C_HAS_WR_ERR, C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_HAS_UNDERFLOW => C_HAS_RD_ERR, C_HAS_VALID => C_HAS_RD_ACK, C_HAS_WR_ACK => C_HAS_WR_ACK, C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => FG_IMP_TYPE, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => FG_MEM_TYPE, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => C_WR_ERR_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129 C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129 C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL, C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH, C_RD_DEPTH => C_FIFO_DEPTH, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => RD_PNTR_WIDTH, C_UNDERFLOW_LOW => C_RD_ERR_LOW, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129 C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH, C_WR_DEPTH => C_FIFO_DEPTH, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => WR_PNTR_WIDTH, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, -- AXI Interface related parameters start here C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0; C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0; C_HAS_SLAVE_CE => 0, -- : integer := 0; C_HAS_MASTER_CE => 0, -- : integer := 0; C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0; C_USE_COMMON_OVERFLOW => 0, -- : integer := 0; C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0; C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH => 4 , -- : integer := 0; C_AXI_ADDR_WIDTH => 32, -- : integer := 0; C_AXI_DATA_WIDTH => 64, -- : integer := 0; C_HAS_AXI_AWUSER => 0 , -- : integer := 0; C_HAS_AXI_WUSER => 0 , -- : integer := 0; C_HAS_AXI_BUSER => 0 , -- : integer := 0; C_HAS_AXI_ARUSER => 0 , -- : integer := 0; C_HAS_AXI_RUSER => 0 , -- : integer := 0; C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0; C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0; C_AXI_WUSER_WIDTH => 1 , -- : integer := 0; C_AXI_BUSER_WIDTH => 1 , -- : integer := 0; C_AXI_RUSER_WIDTH => 1 , -- : integer := 0; -- AXI Streaming C_HAS_AXIS_TDATA => 0 , -- : integer := 0; C_HAS_AXIS_TID => 0 , -- : integer := 0; C_HAS_AXIS_TDEST => 0 , -- : integer := 0; C_HAS_AXIS_TUSER => 0 , -- : integer := 0; C_HAS_AXIS_TREADY => 1 , -- : integer := 0; C_HAS_AXIS_TLAST => 0 , -- : integer := 0; C_HAS_AXIS_TSTRB => 0 , -- : integer := 0; C_HAS_AXIS_TKEEP => 0 , -- : integer := 0; C_AXIS_TDATA_WIDTH => 64, -- : integer := 1; C_AXIS_TID_WIDTH => 8 , -- : integer := 1; C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1; C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1; C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1; C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Data FIFO C_APPLICATION_TYPE_WACH => 0, -- : integer := 0; C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0; C_APPLICATION_TYPE_RACH => 0, -- : integer := 0; C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH => 0, -- : integer := 0; C_USE_ECC_WDCH => 0, -- : integer := 0; C_USE_ECC_WRCH => 0, -- : integer := 0; C_USE_ECC_RACH => 0, -- : integer := 0; C_USE_ECC_RDCH => 0, -- : integer := 0; C_USE_ECC_AXIS => 0, -- : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH => 32, -- : integer := 1; C_DIN_WIDTH_WDCH => 64, -- : integer := 1; C_DIN_WIDTH_WRCH => 2 , -- : integer := 1; C_DIN_WIDTH_RACH => 32, -- : integer := 1; C_DIN_WIDTH_RDCH => 64, -- : integer := 1; C_DIN_WIDTH_AXIS => 1 , -- : integer := 1; C_WR_DEPTH_WACH => 16 , -- : integer := 16; C_WR_DEPTH_WDCH => 1024, -- : integer := 16; C_WR_DEPTH_WRCH => 16 , -- : integer := 16; C_WR_DEPTH_RACH => 16 , -- : integer := 16; C_WR_DEPTH_RDCH => 1024, -- : integer := 16; C_WR_DEPTH_AXIS => 1024, -- : integer := 16; C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4; C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0; C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0; C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0; C_REG_SLICE_MODE_WACH => 0, -- : integer := 0; C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0; C_REG_SLICE_MODE_RACH => 0, -- : integer := 0; C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0 ) port map ( backup => '0', -- : IN std_logic := '0'; backup_marker => '0', -- : IN std_logic := '0'; clk => '0', -- : IN std_logic := '0'; rst => Ainit, -- : IN std_logic := '0'; srst => '0', -- : IN std_logic := '0'; wr_clk => Wr_clk, -- : IN std_logic := '0'; wr_rst => Ainit, -- : IN std_logic := '0'; rd_clk => Rd_clk, -- : IN std_logic := '0'; rd_rst => Ainit, -- : IN std_logic := '0'; din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); wr_en => Wr_en, -- : IN std_logic := '0'; rd_en => Rd_en, -- : IN std_logic := '0'; prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); int_clk => '0', -- : IN std_logic := '0'; injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0'; injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0'; sleep => '0', -- : IN std_logic := '0'; dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); full => Full, -- : OUT std_logic; almost_full => Almost_full, -- : OUT std_logic; wr_ack => Wr_ack, -- : OUT std_logic; overflow => Rd_err, -- : OUT std_logic; empty => Empty, -- : OUT std_logic; almost_empty => Almost_empty, -- : OUT std_logic; valid => Rd_ack, -- : OUT std_logic; underflow => Wr_err, -- : OUT std_logic; data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0); rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0); wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0); prog_full => PROG_FULL, -- : OUT std_logic; prog_empty => PROG_EMPTY, -- : OUT std_logic; sbiterr => SBITERR, -- : OUT std_logic; dbiterr => DBITERR, -- : OUT std_logic wr_rst_busy => WR_RST_BUSY, rd_rst_busy => RD_RST_BUSY, -- AXI Global Signal m_aclk => '0', -- : IN std_logic := '0'; s_aclk => '0', -- : IN std_logic := '0'; s_aresetn => '0', -- : IN std_logic := '0'; m_aclk_en => '0', -- : IN std_logic := '0'; s_aclk_en => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Slave Write Channel (write side) s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awvalid => '0', -- : IN std_logic := '0'; s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic; s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wlast => '0', -- : IN std_logic := '0'; s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wvalid => '0', -- : IN std_logic := '0'; s_axi_wready => S_AXI_WREADY, -- : OUT std_logic; s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0); s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic; s_axi_bready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Write Channel (Read side) m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0); m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic; m_axi_awready => '0', -- : IN std_logic := '0'; m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0); m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic; m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0); m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic; m_axi_wready => '0', -- : IN std_logic := '0'; m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bvalid => '0', -- : IN std_logic := '0'; m_axi_bready => M_AXI_BREADY, -- : OUT std_logic; -- AXI Full/Lite Slave Read Channel (Write side) s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arvalid => '0', -- : IN std_logic := '0'; s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic; s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic; s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0); s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic; s_axi_rready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Read Channel (Read side) m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0); m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic; m_axi_arready => '0', -- : IN std_logic := '0'; m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rlast => '0', -- : IN std_logic := '0'; m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rvalid => '0', -- : IN std_logic := '0'; m_axi_rready => M_AXI_RREADY, -- : OUT std_logic; -- AXI Streaming Slave Signals (Write side) s_axis_tvalid => '0', -- : IN std_logic := '0'; s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic; s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tlast => '0', -- : IN std_logic := '0'; s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- AXI Streaming Master Signals (Read side) m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic; m_axis_tready => '0', -- : IN std_logic := '0'; m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0); m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0); m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0); m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic; m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0); m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0); m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals axi_aw_injectsbiterr => '0', -- : IN std_logic := '0'; axi_aw_injectdbiterr => '0', -- : IN std_logic := '0'; axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic; axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic; axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic; axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic; axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Data Channel Signals axi_w_injectsbiterr => '0', -- : IN std_logic := '0'; axi_w_injectdbiterr => '0', -- : IN std_logic := '0'; axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic; axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic; axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic; axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic; axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Response Channel Signals axi_b_injectsbiterr => '0', -- : IN std_logic := '0'; axi_b_injectdbiterr => '0', -- : IN std_logic := '0'; axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic; axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic; axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic; axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic; axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Address Channel Signals axi_ar_injectsbiterr => '0', -- : IN std_logic := '0'; axi_ar_injectdbiterr => '0', -- : IN std_logic := '0'; axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic; axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic; axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic; axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic; axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Data Channel Signals axi_r_injectsbiterr => '0', -- : IN std_logic := '0'; axi_r_injectdbiterr => '0', -- : IN std_logic := '0'; axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic; axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic; axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic; axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic; axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Streaming FIFO Related Signals axis_injectsbiterr => '0', -- : IN std_logic := '0'; axis_injectdbiterr => '0', -- : IN std_logic := '0'; axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic; axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic; axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic; axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0'; axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1'; ); end generate V6_S6_AND_LATER; end generate USE_2N_DEPTH; ----------------------------------------------------------------------- end implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/syn/vhdl/FIFO_image_filter_img_1_data_stream_1_V.vhd	4	4629	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_img_1_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_img_1_data_stream_1_V_shiftReg; architecture rtl of FIFO_image_filter_img_1_data_stream_1_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_img_1_data_stream_1_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_img_1_data_stream_1_V is component FIFO_image_filter_img_1_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_img_1_data_stream_1_V_shiftReg : FIFO_image_filter_img_1_data_stream_1_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_skid2mm_buf.vhd	5	17065	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_sg_skid2mm_buf.vhd -- -- Description: -- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode. -- -- This Module also provides Write Data Bus Mirroring and WSTRB -- Demuxing to match a narrow Stream to a wider MMap Write -- Channel. By doing this in the skid buffer, the resource -- utilization of the skid buffer can be minimized by only -- having to buffer/mux the Stream data width, not the MMap -- Data width. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_wr_demux; ------------------------------------------------------------------------------- entity axi_sg_skid2mm_buf is generic ( C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ; -- Width of the MMap Write Data bus (in bits) C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ; -- Width of the Stream Data bus (in bits) C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5 -- Width of the LS address bus needed to Demux the WSTRB ); port ( -- Clock and Reset Inputs ------------------------------------------- -- ACLK : In std_logic ; -- ARST : In std_logic ; -- --------------------------------------------------------------------- -- Slave Side (Wr Data Controller Input Side) ----------------------- -- S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); -- S_VALID : In std_logic ; -- S_READY : Out std_logic ; -- S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); -- S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); -- S_LAST : In std_logic ; -- --------------------------------------------------------------------- -- Master Side (MMap Write Data Output Side) ------------------------ M_VALID : Out std_logic ; -- M_READY : In std_logic ; -- M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); -- M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); -- M_LAST : Out std_logic -- --------------------------------------------------------------------- ); end entity axi_sg_skid2mm_buf; architecture implementation of axi_sg_skid2mm_buf is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH; Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH; -- Signals decalrations ------------------------- Signal sig_reset_reg : std_logic := '0'; signal sig_spcl_s_ready_set : std_logic := '0'; signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_skid_reg : std_logic := '0'; signal sig_skid_reg_en : std_logic := '0'; signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_skid_mux_out : std_logic := '0'; signal sig_skid_mux_sel : std_logic := '0'; signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_reg_out : std_logic := '0'; signal sig_data_reg_out_en : std_logic := '0'; signal sig_m_valid_out : std_logic := '0'; signal sig_m_valid_dup : std_logic := '0'; signal sig_m_valid_comb : std_logic := '0'; signal sig_s_ready_out : std_logic := '0'; signal sig_s_ready_dup : std_logic := '0'; signal sig_s_ready_comb : std_logic := '0'; signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); -- Register duplication attribute assignments to control fanout -- on handshake output signals Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no"; begin --(architecture implementation) M_VALID <= sig_m_valid_out; S_READY <= sig_s_ready_out; M_STRB <= sig_strb_reg_out; M_LAST <= sig_last_reg_out; M_DATA <= sig_mirror_data_out; -- Assign the special S_READY FLOP set signal sig_spcl_s_ready_set <= sig_reset_reg; -- Generate the ouput register load enable control sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup); -- Generate the skid inpit register load enable control sig_skid_reg_en <= sig_s_ready_dup; -- Generate the skid mux select control sig_skid_mux_sel <= not(sig_s_ready_dup); -- Skid Mux sig_data_skid_mux_out <= sig_data_skid_reg When (sig_skid_mux_sel = '1') Else S_DATA; sig_strb_skid_mux_out <= sig_strb_skid_reg When (sig_skid_mux_sel = '1') --Else S_STRB; Else sig_wstrb_demux_out; sig_last_skid_mux_out <= sig_last_skid_reg When (sig_skid_mux_sel = '1') Else S_LAST; -- m_valid combinational logic sig_m_valid_comb <= S_VALID or (sig_m_valid_dup and (not(sig_s_ready_dup) or not(M_READY))); -- s_ready combinational logic sig_s_ready_comb <= M_READY or (sig_s_ready_dup and (not(sig_m_valid_dup) or not(S_VALID))); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_THE_RST -- -- Process Description: -- Register input reset -- ------------------------------------------------------------- REG_THE_RST : process (ACLK) begin if (ACLK'event and ACLK = '1') then sig_reset_reg <= ARST; end if; end process REG_THE_RST; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: S_READY_FLOP -- -- Process Description: -- Registers S_READY handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- S_READY_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_s_ready_out <= '0'; sig_s_ready_dup <= '0'; Elsif (sig_spcl_s_ready_set = '1') Then sig_s_ready_out <= '1'; sig_s_ready_dup <= '1'; else sig_s_ready_out <= sig_s_ready_comb; sig_s_ready_dup <= sig_s_ready_comb; end if; end if; end process S_READY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: M_VALID_FLOP -- -- Process Description: -- Registers M_VALID handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- M_VALID_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1' or sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA sig_m_valid_out <= '0'; sig_m_valid_dup <= '0'; else sig_m_valid_out <= sig_m_valid_comb; sig_m_valid_dup <= sig_m_valid_comb; end if; end if; end process M_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_DATA_REG -- -- Process Description: -- This process implements the Skid register for the -- Skid Buffer Data signals. -- ------------------------------------------------------------- SKID_DATA_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (sig_skid_reg_en = '1') then sig_data_skid_reg <= S_DATA; else null; -- hold current state end if; end if; end process SKID_DATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_CNTL_REG -- -- Process Description: -- This process implements the Output registers for the -- Skid Buffer Control signals -- ------------------------------------------------------------- SKID_CNTL_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_strb_skid_reg <= (others => '0'); sig_last_skid_reg <= '0'; elsif (sig_skid_reg_en = '1') then sig_strb_skid_reg <= sig_wstrb_demux_out; sig_last_skid_reg <= S_LAST; else null; -- hold current state end if; end if; end process SKID_CNTL_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_DATA_REG -- -- Process Description: -- This process implements the Output register for the -- Data signals. -- ------------------------------------------------------------- OUTPUT_DATA_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (sig_data_reg_out_en = '1') then sig_data_reg_out <= sig_data_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_DATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_CNTL_REG -- -- Process Description: -- This process implements the Output registers for the -- control signals. -- ------------------------------------------------------------- OUTPUT_CNTL_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_strb_reg_out <= (others => '0'); sig_last_reg_out <= '0'; elsif (sig_data_reg_out_en = '1') then sig_strb_reg_out <= sig_strb_skid_mux_out; sig_last_reg_out <= sig_last_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_CNTL_REG; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_WR_DATA_MIRROR -- -- Process Description: -- Implement the Write Data Mirror structure -- -- Note that it is required that the Stream Width be less than -- or equal to the MMap WData width. -- ------------------------------------------------------------- DO_WR_DATA_MIRROR : process (sig_data_reg_out) begin for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop sig_mirror_data_out(((C_SDATA_WIDTHslice_index)+C_SDATA_WIDTH)-1 downto C_SDATA_WIDTHslice_index) <= sig_data_reg_out; end loop; end process DO_WR_DATA_MIRROR; ------------------------------------------------------------ -- Instance: I_WSTRB_DEMUX -- -- Description: -- Instance for the Write Strobe DeMux. -- ------------------------------------------------------------ I_WSTRB_DEMUX : entity axi_sg_v4_1.axi_sg_wr_demux generic map ( C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH , C_MMAP_DWIDTH => C_MDATA_WIDTH , C_STREAM_DWIDTH => C_SDATA_WIDTH ) port map ( wstrb_in => S_STRB , demux_wstrb_out => sig_wstrb_demux_out , debeat_saddr_lsb => S_ADDR_LSB ); end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_mm2s_basic_wrap.vhd	5	44186	------------------------------------------------------------------------------- -- axi_datamover_mm2s_basic_wrap.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mm2s_basic_wrap.vhd -- -- Description: -- This file implements the DataMover MM2S Basic Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- axi_datamover Library Modules library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_reset; use axi_datamover_v5_1.axi_datamover_cmd_status; use axi_datamover_v5_1.axi_datamover_scc; use axi_datamover_v5_1.axi_datamover_addr_cntl; use axi_datamover_v5_1.axi_datamover_rddata_cntl; use axi_datamover_v5_1.axi_datamover_rd_status_cntl; use axi_datamover_v5_1.axi_datamover_skid_buf; ------------------------------------------------------------------------------- entity axi_datamover_mm2s_basic_wrap is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 2; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Basic MM2S functionality C_MM2S_ARID : Integer range 0 to 255 := 8; -- Specifies the constant value to output on -- the ARID output port C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 64 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_MICRO_DMA : integer range 0 to 1 := 0; C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock and Reset inputs ----------------------- mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- -------------------------------------------------------------- -- MM2S Halt request input control --------------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- -------------------------------------------------------------- -- Error discrete output ------------------------------------- mm2s_err : Out std_logic; -- -- Composite Error indication -- -------------------------------------------------------------- -- Optional MM2S Command and Status Clock and Reset ---------- -- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 -- mm2s_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- -------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) ------------------------------------------------- mm2s_cmd_wvalid : in std_logic; -- mm2s_cmd_wready : out std_logic; -- mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); -- ---------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ----------------- mm2s_sts_wvalid : out std_logic; -- mm2s_sts_wready : in std_logic; -- mm2s_sts_wdata : out std_logic_vector(7 downto 0); -- mm2s_sts_wstrb : out std_logic_vector(0 downto 0); -- mm2s_sts_wlast : out std_logic; -- ------------------------------------------------------------- -- Address Posting contols ---------------------------------- mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- ------------------------------------------------------------- -- MM2S AXI Address Channel I/O -------------------------------------- mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel USER output -- -- mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ------- -- addr2axi_alock : out std_logic_vector(2 downto 0); -- -- addr2axi_acache : out std_logic_vector(4 downto 0); -- -- addr2axi_aqos : out std_logic_vector(3 downto 0); -- -- addr2axi_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------- -- MM2S AXI MMap Read Data Channel I/O ------------------------------------------ mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); -- mm2s_rresp : In std_logic_vector(1 downto 0); -- mm2s_rlast : In std_logic; -- mm2s_rvalid : In std_logic; -- mm2s_rready : Out std_logic; -- ---------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ----------------------------------------------- mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); -- mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); -- mm2s_strm_wlast : Out std_logic; -- mm2s_strm_wvalid : Out std_logic; -- mm2s_strm_wready : In std_logic; -- -------------------------------------------------------------------------------------- -- Testing Support I/O -------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) -- ------------------------------------------------------------------- ); end entity axi_datamover_mm2s_basic_wrap; architecture implementation of axi_datamover_mm2s_basic_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_rdmux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Read data mux select control. -- ------------------------------------------------------------------- function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 5 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when others => -- 256 bits num_addr_bits_needed := 5; end case; Return (num_addr_bits_needed); end function func_calc_rdmux_sel_bits; -- Constant Declarations ---------------------------------------- Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant INCLUDE_MM2S : integer range 0 to 2 := 2; Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID; Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH; Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH; Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH; Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH; Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32); Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1; Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := C_MM2S_STSCMD_FIFO_DEPTH; Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC; Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0; Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2; Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16; Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH; Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH; Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH); Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); -- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0; -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0); signal sig_mm2s_cache_data : std_logic_vector(7 downto 0); signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_cmplt : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2rsc_calc_error : std_logic := '0'; signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2rsc_calc_err : std_logic := '0'; signal sig_data2rsc_okay : std_logic := '0'; signal sig_data2rsc_decerr : std_logic := '0'; signal sig_data2rsc_slverr : std_logic := '0'; signal sig_data2rsc_cmd_cmplt : std_logic := '0'; signal sig_rsc2data_ready : std_logic := '0'; signal sig_data2rsc_valid : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_data2skid_wvalid : std_logic := '0'; signal sig_data2skid_wready : std_logic := '0'; signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_data2skid_wlast : std_logic := '0'; signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2rsc_status_ready : std_logic := '0'; signal sig_rsc2stat_status_valid : std_logic := '0'; signal sig_rsc2mstr_halt_pipe : std_logic := '0'; signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal mm2s_arcache_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug Support ------------------------------------------ mm2s_dbg_data <= sig_dbg_data_mux_out; -- Note that only the mm2s_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (mm2s_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2rsc_status_ready; sig_dbg_data_1(7) <= sig_rsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake -- Spare bits in debug1 sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off mm2s_arcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register mm2s_aruser <= "0000";--sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters -- sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96); sig_mm2s_cache_data <= mm2s_cmd_wdata(79 downto 72); end generate GEN_CACHE2; -- Cache signal tie-off -- Internal error output discrete ------------------------------ mm2s_err <= sig_calc2dm_calc_err; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ) port map ( primary_aclk => mm2s_aclk , primary_aresetn => mm2s_aresetn , secondary_awclk => mm2s_cmdsts_awclk , secondary_aresetn => mm2s_cmdsts_aresetn , halt_req => mm2s_halt , halt_cmplt => mm2s_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => LOGIC_HIGH , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO , C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_STS_WIDTH => MM2S_STS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , secondary_awclk => mm2s_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => mm2s_cmd_wvalid , cmd_wready => mm2s_cmd_wready , cmd_wdata => sig_mm2s_cmd_wdata , cache_data => sig_mm2s_cache_data , sts_wvalid => mm2s_sts_wvalid , sts_wready => mm2s_sts_wready , sts_wdata => mm2s_sts_wdata , sts_wstrb => mm2s_sts_wstrb , sts_wlast => mm2s_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_rsc2stat_status , stat2mstr_status_ready => sig_stat2rsc_status_ready , mst2stst_status_valid => sig_rsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_RD_STATUS_CNTLR -- -- Description: -- Read Status Controller Block -- ------------------------------------------------------------ I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl generic map ( C_STS_WIDTH => MM2S_STS_WIDTH , C_TAG_WIDTH => C_TAG_WIDTH ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , calc2rsc_calc_error => sig_calc2dm_calc_err , addr2rsc_calc_error => sig_addr2rsc_calc_error , addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty , data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_error => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2stat_status => sig_rsc2stat_status , stat2rsc_status_ready => sig_stat2rsc_status_ready , rsc2stat_status_valid => sig_rsc2stat_status_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ------------------------------------------------------------ -- Instance: I_MSTR_SCC -- -- Description: -- Simple Command Calculator Block -- ------------------------------------------------------------ I_MSTR_SCC : entity axi_datamover_v5_1.axi_datamover_scc generic map ( C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_MAX_BURST_LEN => C_MM2S_BURST_SIZE , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_MICRO_DMA => C_MICRO_DMA , C_TAG_WIDTH => C_TAG_WIDTH ) port map ( -- Clock input primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_sof => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , calc_error => sig_calc2dm_calc_err ); ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl generic map ( -- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA , --C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH , C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_ADDR_ID => MM2S_ARID_VALUE , C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH , C_TAG_WIDTH => C_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => mm2s_arid , addr2axi_aaddr => mm2s_araddr , addr2axi_alen => mm2s_arlen , addr2axi_asize => mm2s_arsize , addr2axi_aburst => mm2s_arburst , addr2axi_aprot => mm2s_arprot , addr2axi_avalid => mm2s_arvalid , addr2axi_acache => open , addr2axi_auser => open , axi2addr_aready => mm2s_arready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => mm2s_allow_addr_req , addr_req_posted => mm2s_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => LOGIC_LOW , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2rsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_RD_DATA_CNTL -- -- Description: -- Read Data Controller Block -- ------------------------------------------------------------ I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl generic map ( C_INCLUDE_DRE => INCLUDE_MM2S_DRE , C_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => MM2S_MDATA_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_TAG_WIDTH => C_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset ----------------------------------- primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , -- Soft Shutdown Interface ----------------------------- rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , -- External Address Pipelining Contol support mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt , -- AXI Read Data Channel I/O ------------------------------- mm2s_rdata => mm2s_rdata , mm2s_rresp => mm2s_rresp , mm2s_rlast => mm2s_rlast , mm2s_rvalid => mm2s_rvalid , mm2s_rready => mm2s_rready , -- MM2S DRE Control ----------------------------------- mm2s_dre_new_align => open , mm2s_dre_use_autodest => open , mm2s_dre_src_align => open , mm2s_dre_dest_align => open , mm2s_dre_flush => open , -- AXI Master Stream ----------------------------------- mm2s_strm_wvalid => sig_data2skid_wvalid , mm2s_strm_wready => sig_data2skid_wready , mm2s_strm_wdata => sig_data2skid_wdata , mm2s_strm_wstrb => sig_data2skid_wstrb , mm2s_strm_wlast => sig_data2skid_wlast , -- MM2S Store and Forward Supplimental Control ----------- mm2s_data2sf_cmd_cmplt => open , -- Command Calculator Interface -------------------------- mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => LOGIC_LOW , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => DRE_ALIGN_ZEROS , mstr2data_dre_dest_align => DRE_ALIGN_ZEROS , -- Address Controller Interface -------------------------- addr2data_addr_posted => sig_addr2data_addr_posted , -- Data Controller Halted Status data2all_dcntlr_halted => sig_data2all_dcntlr_halted, -- Output Stream Skid Buffer Halt control data2skid_halt => sig_data2skid_halt , -- Read Status Controller Interface -------------------------- data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_err => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate begin ------------------------------------------------------------ -- Instance: I_MM2S_SKID_BUF -- -- Description: -- Instance for the MM2S Skid Buffer which provides for -- registerd Master Stream outputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => MM2S_SDATA_WIDTH ) port map ( -- System Ports aclk => mm2s_aclk , arst => sig_stream_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => sig_data2skid_wvalid , s_ready => sig_data2skid_wready , s_data => sig_data2skid_wdata , s_strb => sig_data2skid_wstrb , s_last => sig_data2skid_wlast , -- Master Side (Stream Data Output m_valid => mm2s_strm_wvalid , m_ready => mm2s_strm_wready , m_data => mm2s_strm_wdata , m_strb => mm2s_strm_wstrb , m_last => mm2s_strm_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate begin mm2s_strm_wvalid <= sig_data2skid_wvalid; sig_data2skid_wready <= mm2s_strm_wready; mm2s_strm_wdata <= sig_data2skid_wdata; mm2s_strm_wstrb <= sig_data2skid_wstrb; mm2s_strm_wlast <= sig_data2skid_wlast; end generate DISABLE_AXIS_SKID; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_mask_cols_V.vhd	2	4556	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_mask_cols_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_mask_cols_V_shiftReg; architecture rtl of FIFO_image_filter_mask_cols_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_mask_cols_V is generic ( MEM_STYLE : string := "shiftreg"; DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_mask_cols_V is component FIFO_image_filter_mask_cols_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_mask_cols_V_shiftReg : FIFO_image_filter_mask_cols_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/correct_one_bit_64.vhd	7	8400	------------------------------------------------------------------------------- -- correct_one_bit_64.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------ -- Filename: correct_one_bit_64.vhd -- -- Description: Identifies single bit to correct in 64-bit word of -- data read from memory as indicated by the syndrome input -- vector. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- \| -- \|-- full_axi.vhd -- \| -- sng_port_arb.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- wr_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- \| -- rd_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- \|-- axi_lite.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all; entity Correct_One_Bit_64 is generic ( C_USE_LUT6 : boolean := true; Correct_Value : std_logic_vector(0 to 7)); port ( DIn : in std_logic; Syndrome : in std_logic_vector(0 to 7); DCorr : out std_logic); end entity Correct_One_Bit_64; architecture IMP of Correct_One_Bit_64 is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; ----------------------------------------------------------------------------- -- Find which bit that has a '1' -- There is always one bit which has a '1' ----------------------------------------------------------------------------- function find_one (Syn : std_logic_vector(0 to 7)) return natural is begin -- function find_one for I in 0 to 7 loop if (Syn(I) = '1') then return I; end if; end loop; -- I return 0; -- Should never reach this statement end function find_one; constant di_index : natural := find_one(Correct_Value); signal corr_sel : std_logic; signal corr_c : std_logic; signal lut_compare : std_logic_vector(0 to 6); signal lut_corr_val : std_logic_vector(0 to 6); begin -- architecture IMP Remove_DI_Index : process (Syndrome) is begin -- process Remove_DI_Index if (di_index = 0) then lut_compare <= Syndrome(1 to 7); lut_corr_val <= Correct_Value(1 to 7); elsif (di_index = 6) then lut_compare <= Syndrome(0 to 6); lut_corr_val <= Correct_Value(0 to 6); else lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 7); lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 7); end if; end process Remove_DI_Index; corr_sel <= '0' when lut_compare = lut_corr_val else '1'; Corr_MUXCY : MUXCY_L port map ( DI => Syndrome(di_index), CI => '0', S => corr_sel, LO => corr_c); Corr_XORCY : XORCY port map ( LI => DIn, CI => corr_c, O => DCorr); end architecture IMP;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_rd_status_cntl.vhd	18	19292	------------------------------------------------------------------------------- -- axi_datamover_rd_status_cntl.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_rd_status_cntl.vhd -- -- Description: -- This file implements the DataMover Master Read Status Controller. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_datamover_rd_status_cntl is generic ( C_STS_WIDTH : Integer := 8; -- sets the width of the Status ports C_TAG_WIDTH : Integer range 1 to 8 := 4 -- Sets the width of the Tag field in the Status reply ); port ( -- Clock and Reset input -------------------------------------- -- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- --------------------------------------------------------------- -- Command Calculator Status Interface --------------------------- -- calc2rsc_calc_error : in std_logic ; -- -- Indication from the Command Calculator that a calculation -- -- error has occured. -- ------------------------------------------------------------------- -- Address Controller Status Interface ---------------------------- -- addr2rsc_calc_error : In std_logic ; -- -- Indication from the Data Channel Controller FIFO that it -- -- is empty (no commands pending) -- -- addr2rsc_fifo_empty : In std_logic ; -- -- Indication from the Address Controller FIFO that it -- -- is empty (no commands pending) -- ------------------------------------------------------------------- -- Data Controller Status Interface --------------------------------------------- -- data2rsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The command tag -- -- data2rsc_calc_error : In std_logic ; -- -- Indication from the Data Channel Controller FIFO that it -- -- is empty (no commands pending) -- -- data2rsc_okay : In std_logic ; -- -- Indication that the AXI Read transfer completed with OK status -- -- data2rsc_decerr : In std_logic ; -- -- Indication that the AXI Read transfer completed with decode error status -- -- data2rsc_slverr : In std_logic ; -- -- Indication that the AXI Read transfer completed with slave error status -- -- data2rsc_cmd_cmplt : In std_logic ; -- -- Indication by the Data Channel Controller that the -- -- corresponding status is the last status for a parent command -- -- pulled from the command FIFO -- -- rsc2data_ready : Out std_logic; -- -- Handshake bit from the Read Status Controller Module indicating -- -- that the it is ready to accept a new Read status transfer -- -- data2rsc_valid : in std_logic ; -- -- Handshake bit output to the Read Status Controller Module -- -- indicating that the Data Controller has valid tag and status -- -- indicators to transfer -- ---------------------------------------------------------------------------------- -- Command/Status Module Interface ---------------------------------------------- -- rsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); -- -- Read Status value collected during a Read Data transfer -- -- Output to the Command/Status Module -- -- stat2rsc_status_ready : In std_logic; -- -- Input from the Command/Status Module indicating that the -- -- Status Reg/FIFO is ready to accept a transfer -- -- rsc2stat_status_valid : Out std_logic ; -- -- Control Signal to the Status Reg/FIFO indicating a new status -- -- output value is valid and ready for transfer -- --------------------------------------------------------------------------------- -- Address and Data Controller Pipe halt ---------------------------------- -- rsc2mstr_halt_pipe : Out std_logic -- -- Indication to Halt the Data and Address Command pipeline due -- -- to the Status FIFO going full or an internal error being logged -- --------------------------------------------------------------------------- ); end entity axi_datamover_rd_status_cntl; architecture implementation of axi_datamover_rd_status_cntl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Constant Declarations -------------------------------------------- Constant OKAY : std_logic_vector(1 downto 0) := "00"; Constant EXOKAY : std_logic_vector(1 downto 0) := "01"; Constant SLVERR : std_logic_vector(1 downto 0) := "10"; Constant DECERR : std_logic_vector(1 downto 0) := "11"; Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000"; Constant TAG_WIDTH : integer := C_TAG_WIDTH; Constant STAT_REG_TAG_WIDTH : integer := 4; -- Signal Declarations -------------------------------------------- signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_rsc2status_valid : std_logic := '0'; signal sig_rsc2data_ready : std_logic := '0'; signal sig_rd_sts_okay_reg : std_logic := '0'; signal sig_rd_sts_interr_reg : std_logic := '0'; signal sig_rd_sts_decerr_reg : std_logic := '0'; signal sig_rd_sts_slverr_reg : std_logic := '0'; signal sig_rd_sts_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_pop_rd_sts_reg : std_logic := '0'; signal sig_push_rd_sts_reg : std_logic := '0'; Signal sig_rd_sts_push_ok : std_logic := '0'; signal sig_rd_sts_reg_empty : std_logic := '0'; signal sig_rd_sts_reg_full : std_logic := '0'; begin --(architecture implementation) -- Assign the status write output control rsc2stat_status_valid <= sig_rsc2status_valid ; sig_rsc2status_valid <= sig_rd_sts_reg_full; -- Formulate the status outout value (assumes an 8-bit status width) rsc2stat_status <= sig_rd_sts_okay_reg & sig_rd_sts_slverr_reg & sig_rd_sts_decerr_reg & sig_rd_sts_interr_reg & sig_tag2status; -- Detect that a push of a new status word is completing sig_rd_sts_push_ok <= sig_rsc2status_valid and stat2rsc_status_ready; -- Signal a halt to the execution pipe if new status -- is valid but the Status FIFO is not accepting it rsc2mstr_halt_pipe <= sig_rsc2status_valid and (not(stat2rsc_status_ready) ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_TAG_LE_STAT -- -- If Generate Description: -- Populates the TAG bits into the availble Status bits when -- the TAG width is less than or equal to the available number -- of bits in the Status word. -- ------------------------------------------------------------ GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate -- local signals signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0'); begin sig_tag2status <= lsig_temp_tag_small; ------------------------------------------------------------- -- Combinational Process -- -- Label: POPULATE_SMALL_TAG -- -- Process Description: -- -- ------------------------------------------------------------- POPULATE_SMALL_TAG : process (sig_rd_sts_tag_reg) begin -- Set default value lsig_temp_tag_small <= (others => '0'); -- Now overload actual TAG bits lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_rd_sts_tag_reg; end process POPULATE_SMALL_TAG; end generate GEN_TAG_LE_STAT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_TAG_GT_STAT -- -- If Generate Description: -- Populates the TAG bits into the availble Status bits when -- the TAG width is greater than the available number of -- bits in the Status word. The upper bits of the TAG are -- clipped off (discarded). -- ------------------------------------------------------------ GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate -- local signals signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0); begin sig_tag2status <= lsig_temp_tag_big; ------------------------------------------------------------- -- Combinational Process -- -- Label: POPULATE_BIG_TAG -- -- Process Description: -- -- ------------------------------------------------------------- POPULATE_SMALL_TAG : process (sig_rd_sts_tag_reg) begin -- Set default value lsig_temp_tag_big <= (others => '0'); -- Now overload actual TAG bits lsig_temp_tag_big <= sig_rd_sts_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0); end process POPULATE_SMALL_TAG; end generate GEN_TAG_GT_STAT; ------- Read Status Collection Logic -------------------------------- rsc2data_ready <= sig_rsc2data_ready ; sig_rsc2data_ready <= sig_rd_sts_reg_empty; sig_push_rd_sts_reg <= data2rsc_valid and sig_rsc2data_ready; sig_pop_rd_sts_reg <= sig_rd_sts_push_ok; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: RD_STATUS_FIFO_REG -- -- Process Description: -- Implement Read status FIFO register. -- This register holds the Read status from the Data Controller -- until it is transfered to the Status FIFO. -- ------------------------------------------------------------- RD_STATUS_FIFO_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_pop_rd_sts_reg = '1') then sig_rd_sts_tag_reg <= (others => '0'); sig_rd_sts_interr_reg <= '0'; sig_rd_sts_decerr_reg <= '0'; sig_rd_sts_slverr_reg <= '0'; sig_rd_sts_okay_reg <= '1'; -- set back to default of "OKAY" sig_rd_sts_reg_full <= '0'; sig_rd_sts_reg_empty <= '1'; Elsif (sig_push_rd_sts_reg = '1') Then sig_rd_sts_tag_reg <= data2rsc_tag; sig_rd_sts_interr_reg <= data2rsc_calc_error or sig_rd_sts_interr_reg; sig_rd_sts_decerr_reg <= data2rsc_decerr or sig_rd_sts_decerr_reg; sig_rd_sts_slverr_reg <= data2rsc_slverr or sig_rd_sts_slverr_reg; sig_rd_sts_okay_reg <= data2rsc_okay and not(data2rsc_decerr or sig_rd_sts_decerr_reg or data2rsc_slverr or sig_rd_sts_slverr_reg or data2rsc_calc_error or sig_rd_sts_interr_reg ); sig_rd_sts_reg_full <= data2rsc_cmd_cmplt or data2rsc_calc_error; sig_rd_sts_reg_empty <= not(data2rsc_cmd_cmplt or data2rsc_calc_error); else null; -- hold current state end if; end if; end process RD_STATUS_FIFO_REG; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_cdma_v4_1/25515467/hdl/src/vhdl/axi_cdma_pulse_gen.vhd	1	15300	------------------------------------------------------------------------------- -- axi_cdma_pulse_gen.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_cdma_pulse_gen.vhd -- -- Description: -- This file is the design for a parameterizable pulse width generator. -- The input Sig_In is either Positive Edge or Negative detected -- which triggers a pulse generator. Allowed pulse widths are 1 to -- 64 input clock periods. -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library lib_cdc_v1_0; library axi_cdma_v4_1; use axi_cdma_v4_1.axi_cdma_pkg.all; ------------------------------------------------------------------------------ entity axi_cdma_pulse_gen is generic ( C_INCLUDE_SYNCHRO : Integer range 0 to 1 := 0; -- 0 = Do not include synchronizer registers -- 1 = Include synchronizer registers C_POS_EDGE_TRIG : Integer range 0 to 1 := 1; -- 0 = Negative Edge Triggered Pulse -- 1 = Positive Edge Triggered Pulse C_PULSE_WIDTH_CLKS : integer range 1 to 64 := 4 -- Desired Output Pulse width (in Clk_In periods) ); port ( -- Input synchronization clock Clk_In : In std_logic; -- Module reset (active high) Rst_In : In std_logic; -- Input trigger signal Sig_in : In std_logic; -- Output pulse Pulse_Out : Out std_logic ); end entity axi_cdma_pulse_gen; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_cdma_pulse_gen is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ATTRIBUTE async_reg : STRING; ------------------------------------------------------------------------------- -- Functions Declarations ------------------------------------------------------------------------------- -- none ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- Constant ADJUSTED_CLKs : integer := C_PULSE_WIDTH_CLKS+1; ------------------------------------------------------------------------------- -- Internal Signal Declaration ------------------------------------------------------------------------------- -- System module reset interconnect signals signal sig_pulse_out : std_logic; signal sig_to_edge_detect_reg : std_logic; signal sig_pulse_trigger : std_logic; signal sig_shift_reg : std_logic_vector(0 to ADJUSTED_CLKs-1); -- Addition of synchronizer front-end signal sig_synchro_reg1_cdc_tig : std_logic; signal sig_synchro_reg2 : std_logic; signal sig_to_edge_detect : std_logic; -- ATTRIBUTE async_reg OF sig_synchro_reg1_cdc_tig : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF sig_synchro_reg2 : SIGNAL IS "true"; ------------------------------------------------------------------------------- begin -- architecture body -- Output Port assignments Pulse_Out <= sig_pulse_out ; ------------------------------------------------------------ -- If Generate -- -- Label: OMIT_SYNCHRO_REGS -- -- If Generate Description: -- This IfGen omits the implementation of a double register -- synchronizer on the input signal. -- ------------------------------------------------------------ OMIT_SYNCHRO_REGS : if (C_INCLUDE_SYNCHRO = 0) generate begin sig_to_edge_detect <= Sig_In; end generate OMIT_SYNCHRO_REGS; ------------------------------------------------------------ -- If Generate -- -- Label: INCLUDE_SYNCHRO_REGS -- -- If Generate Description: -- This IfGen includes the implementation of a double -- register synchronizer on the input signal. -- ------------------------------------------------------------ INCLUDE_SYNCHRO_REGS : if (C_INCLUDE_SYNCHRO = 1) generate begin sig_to_edge_detect <= sig_synchro_reg2; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_SYNCHRO_REGS -- -- Process Description: -- -- ------------------------------------------------------------- DO_SYNCHRO_REGS : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => Sig_In, prmry_vect_in => (others => '0'), scndry_aclk => Clk_In, scndry_resetn => '0', scndry_out => sig_synchro_reg2, scndry_vect_out => open ); -- DO_SYNCHRO_REGS : process (Clk_In) -- begin -- if (Clk_In'event and Clk_In = '1') then -- if (Rst_In = '1') then -- sig_synchro_reg1_cdc_tig <= '0'; -- sig_synchro_reg2 <= '0'; -- else -- sig_synchro_reg1_cdc_tig <= Sig_In; -- sig_synchro_reg2 <= sig_synchro_reg1_cdc_tig; -- end if; -- end if; -- end process DO_SYNCHRO_REGS; end generate INCLUDE_SYNCHRO_REGS; ------------------------------------------------------------ -- If Generate -- -- Label: POSITIVE_EDGE_TRIGGER -- -- If Generate Description: -- Generate Pulse trigger from Positive edge detection on -- the input signal -- -- ------------------------------------------------------------ POSITIVE_EDGE_TRIGGER : if (C_POS_EDGE_TRIG = 1) generate begin -- Do positive edge detection on input signal, This becomes -- the trigger for generating the output pulse. sig_pulse_trigger <= sig_to_edge_detect and not(sig_to_edge_detect_reg); end generate POSITIVE_EDGE_TRIGGER; ------------------------------------------------------------ -- If Generate -- -- Label: NEGATIVE_EDGE_TRIGGER -- -- If Generate Description: -- Generate Pulse trigger from negative edge detection on -- the input signal -- -- ------------------------------------------------------------ NEGATIVE_EDGE_TRIGGER : if (C_POS_EDGE_TRIG = 0) generate begin -- Do negative edge detection on input signal, This becomes -- the trigger for generating the output pulse. sig_pulse_trigger <= not(sig_to_edge_detect) and sig_to_edge_detect_reg; end generate NEGATIVE_EDGE_TRIGGER; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SIG_IN -- -- Process Description: -- This process registers the input signal for use in the -- edge detection logic. -- ------------------------------------------------------------- REG_SIG_IN : process (Clk_In) begin if (Clk_In'event and Clk_In = '1') then if (Rst_In = '1') then sig_to_edge_detect_reg <= '0'; else sig_to_edge_detect_reg <= sig_to_edge_detect; end if; end if; end process REG_SIG_IN; ------------------------------------------------------------ -- If Generate -- -- Label: DO_SINGLE_CLK_PULSE -- -- If Generate Description: -- -- Handles single clock pulse width case -- ------------------------------------------------------------ DO_SINGLE_CLK_PULSE : if (C_PULSE_WIDTH_CLKS = 1) generate begin sig_shift_reg <= (others => '0'); -- house keeping ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SINGLE_PULSE -- -- Process Description: -- This process registers a single pulse case. -- ------------------------------------------------------------- REG_SINGLE_PULSE : process (Clk_In) begin if (Clk_In'event and Clk_In = '1') then if (Rst_In = '1') then sig_pulse_out <= '0'; else sig_pulse_out <= sig_pulse_trigger; end if; end if; end process REG_SINGLE_PULSE; end generate DO_SINGLE_CLK_PULSE; ------------------------------------------------------------ -- If Generate -- -- Label: DO_MULTI_CLK_PULSE -- -- If Generate Description: -- -- Handles Multi clock pulse width case -- ------------------------------------------------------------ DO_MULTI_CLK_PULSE : if (C_PULSE_WIDTH_CLKS >= 2) generate begin ----------------------------------------------------------------------------- -- Implement the Shift register logic ----------------------------------------------------------------------------- -- The output pulse is ripped from the final stage of the shift register sig_pulse_out <= sig_shift_reg(ADJUSTED_CLKs-1); -- Tie the shift register input stage to 0 sig_shift_reg(0) <= '0'; ------------------------------------------------------------ -- For Generate -- -- Label: DO_SHIF_REG -- -- For Generate Description: -- This For Gen implements a parameterizable shift -- register for the pulse generator. The trigger presets -- all of the register segments and then zeros are shifted -- into the pipe until all stages are cleared. The resulting -- pulse out is equal to the number of stages in the shift -- register. -- -- -- ------------------------------------------------------------ DO_SHIF_REG : for reg_index in 1 to ADJUSTED_CLKs-1 generate begin ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_SHIFT_REG_SEGMENT -- -- Process Description: -- This process implements a single register segment of -- of the pulse generator shift register. -- ------------------------------------------------------------- DO_SHIFT_REG_SEGMENT : process (Clk_In) begin if (Clk_In'event and Clk_In = '1') then if (Rst_In = '1') then -- Clear the reg sig_shift_reg(reg_index) <= '0'; elsif (sig_pulse_trigger = '1') then -- preset the reg sig_shift_reg(reg_index) <= '1'; else -- shift stuff through sig_shift_reg(reg_index) <= sig_shift_reg(reg_index-1); end if; end if; end process DO_SHIFT_REG_SEGMENT; end generate DO_SHIF_REG; ----------------------------------------------------------------------------- -- End of Shift register logic ----------------------------------------------------------------------------- end generate DO_MULTI_CLK_PULSE; end architecture implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/axi_bram_ctrl.vhd	4	43388	------------------------------------------------------------------------------- -- axi_bram_ctrl.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: axi_bram_ctrl_wrapper.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller IP core. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v4_0) -- \| -- \|--axi_bram_ctrl_top.vhd -- \| -- \|-- full_axi.vhd -- \| -- sng_port_arb.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- wr_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- ecc_gen.vhd -- \| -- \| -- rd_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- ecc_gen.vhd -- \| -- \|-- axi_lite.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- ecc_gen.vhd -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; library work; use work.axi_bram_ctrl_top; use work.axi_bram_ctrl_funcs.all; --use work.coregen_comp_defs.all; library blk_mem_gen_v8_2; use blk_mem_gen_v8_2.all; ------------------------------------------------------------------------------ entity axi_bram_ctrl is generic ( C_BRAM_INST_MODE : string := "EXTERNAL"; -- external ; internal --determines whether the bmg is external or internal to axi bram ctrl wrapper C_MEMORY_DEPTH : integer := 4096; --Memory depth specified by the user C_BRAM_ADDR_WIDTH : integer := 12; -- Width of AXI address bus (in bits) C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH : INTEGER := 4; -- AXI ID vector width C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1; -- Support for narrow burst operations C_SINGLE_PORT_BRAM : INTEGER := 0; -- Enable single port usage of BRAM C_FAMILY : string := "virtex7"; -- Specify the target architecture type -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_TYPE : integer := 1; C_FAULT_INJECT : integer := 0; -- Enable fault injection registers -- (default = disabled) C_ECC_ONOFF_RESET_VALUE : integer := 1 -- By default, ECC checking is on -- (can disable ECC @ reset by setting this to 0) ); port ( -- AXI Interface Signals -- AXI Clock and Reset s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; ecc_interrupt : out std_logic := '0'; ecc_ue : out std_logic := '0'; -- axi write address channel Signals (AW) s_axi_awid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awlen : in std_logic_vector(7 downto 0); s_axi_awsize : in std_logic_vector(2 downto 0); s_axi_awburst : in std_logic_vector(1 downto 0); s_axi_awlock : in std_logic; s_axi_awcache : in std_logic_vector(3 downto 0); s_axi_awprot : in std_logic_vector(2 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; -- axi write data channel Signals (W) s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wstrb : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0); s_axi_wlast : in std_logic; s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; -- axi write data response Channel Signals (B) s_axi_bid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; -- axi read address channel Signals (AR) s_axi_arid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_arlen : in std_logic_vector(7 downto 0); s_axi_arsize : in std_logic_vector(2 downto 0); s_axi_arburst : in std_logic_vector(1 downto 0); s_axi_arlock : in std_logic; s_axi_arcache : in std_logic_vector(3 downto 0); s_axi_arprot : in std_logic_vector(2 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; -- axi read data channel Signals (R) s_axi_rid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rlast : out std_logic; s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; -- axi-lite ecc register Interface Signals -- axi-lite clock and Reset -- note: axi-lite control IF and AXI IF share the same clock. -- s_axi_ctrl_aclk : in std_logic; -- s_axi_ctrl_aresetn : in std_logic; -- axi-lite write address Channel Signals (AW) s_axi_ctrl_awvalid : in std_logic; s_axi_ctrl_awready : out std_logic; s_axi_ctrl_awaddr : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- axi-lite write data Channel Signals (W) s_axi_ctrl_wdata : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); s_axi_ctrl_wvalid : in std_logic; s_axi_ctrl_wready : out std_logic; -- axi-lite write data Response Channel Signals (B) s_axi_ctrl_bresp : out std_logic_vector(1 downto 0); s_axi_ctrl_bvalid : out std_logic; s_axi_ctrl_bready : in std_logic; -- axi-lite read address Channel Signals (AR) s_axi_ctrl_araddr : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); s_axi_ctrl_arvalid : in std_logic; s_axi_ctrl_arready : out std_logic; -- axi-lite read data Channel Signals (R) s_axi_ctrl_rdata : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); s_axi_ctrl_rresp : out std_logic_vector(1 downto 0); s_axi_ctrl_rvalid : out std_logic; s_axi_ctrl_rready : in std_logic; -- bram interface signals (Port A) bram_rst_a : out std_logic; bram_clk_a : out std_logic; bram_en_a : out std_logic; bram_we_a : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); bram_addr_a : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); bram_wrdata_a : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); bram_rddata_a : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); -- bram interface signals (Port B) bram_rst_b : out std_logic; bram_clk_b : out std_logic; bram_en_b : out std_logic; bram_we_b : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); bram_addr_b : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); bram_wrdata_b : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); bram_rddata_b : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) ); end entity axi_bram_ctrl; ------------------------------------------------------------------------------- architecture implementation of axi_bram_ctrl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------ -- FUNCTION: if_then_else -- This function is used to implement an IF..THEN when such a statement is not -- allowed. ------------------------------------------------------------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS VARIABLE retval : INTEGER := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; --------------------------------------------------------------------------- -- FUNCTION : log2roundup --------------------------------------------------------------------------- FUNCTION log2roundup (data_value : integer) RETURN integer IS VARIABLE width : integer := 0; VARIABLE cnt : integer := 1; CONSTANT lower_limit : integer := 1; CONSTANT upper_limit : integer := 8; BEGIN IF (data_value <= 1) THEN width := 0; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt 2; END LOOP; END IF; RETURN width; END log2roundup; ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- -- Only instantiate logic based on C_S_AXI_PROTOCOL. -- Determine external ECC width. -- Use function defined in axi_bram_ctrl_funcs package. -- Set internal parameters for ECC register enabling when C_ECC = 1 -- Catastrophic error indicated with ECC_UE & Interrupt flags. -- Counter only sized when C_ECC = 1. -- Selects CE counter width/threshold to assert ECC_Interrupt -- Hard coded at 8-bits to capture and count up to 256 correctable errors. -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code constant GND : std_logic := '0'; constant VCC : std_logic := '1'; constant ZERO1 : std_logic_vector(0 downto 0) := (others => '0'); constant ZERO2 : std_logic_vector(1 downto 0) := (others => '0'); constant ZERO3 : std_logic_vector(2 downto 0) := (others => '0'); constant ZERO4 : std_logic_vector(3 downto 0) := (others => '0'); constant ZERO8 : std_logic_vector(7 downto 0) := (others => '0'); constant WSTRB_ZERO : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); constant ZERO16 : std_logic_vector(15 downto 0) := (others => '0'); constant ZERO32 : std_logic_vector(31 downto 0) := (others => '0'); constant ZERO64 : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); CONSTANT MEM_TYPE : INTEGER := if_then_else((C_SINGLE_PORT_BRAM=1),0,2); CONSTANT BWE_B : INTEGER := if_then_else((C_SINGLE_PORT_BRAM=1),0,1); CONSTANT BMG_ADDR_WIDTH : INTEGER := log2roundup(C_MEMORY_DEPTH) + log2roundup(C_S_AXI_DATA_WIDTH/8) ; ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal clka_bram_clka_i : std_logic := '0'; signal rsta_bram_rsta_i : std_logic := '0'; signal ena_bram_ena_i : std_logic := '0'; signal REGCEA : std_logic := '0'; signal wea_bram_wea_i : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal addra_bram_addra_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal dina_bram_dina_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal douta_bram_douta_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); signal clkb_bram_clkb_i : std_logic := '0'; signal rstb_bram_rstb_i : std_logic := '0'; signal enb_bram_enb_i : std_logic := '0'; signal REGCEB : std_logic := '0'; signal web_bram_web_i : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal addrb_bram_addrb_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal dinb_bram_dinb_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal doutb_bram_doutb_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); ----------------------------------------------------------------------- -- Architecture Body ----------------------------------------------------------------------- begin gint_inst: IF (C_BRAM_INST_MODE = "INTERNAL" ) GENERATE constant c_addrb_width : INTEGER := log2roundup(C_MEMORY_DEPTH); constant C_WEA_WIDTH_I : INTEGER := (C_S_AXI_DATA_WIDTH/8 + C_ECC(1+(C_S_AXI_DATA_WIDTH/128))) ; constant C_WRITE_WIDTH_A_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))) ; constant C_READ_WIDTH_A_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))); constant C_ADDRA_WIDTH_I : INTEGER := log2roundup(C_MEMORY_DEPTH); constant C_WEB_WIDTH_I : INTEGER := (C_S_AXI_DATA_WIDTH/8 + C_ECC(1+(C_S_AXI_DATA_WIDTH/128))); constant C_WRITE_WIDTH_B_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))); constant C_READ_WIDTH_B_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))); signal s_axi_rdaddrecc_bmg_int : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0); signal s_axi_dbiterr_bmg_int : STD_LOGIC; signal s_axi_sbiterr_bmg_int : STD_LOGIC; signal s_axi_rvalid_bmg_int : STD_LOGIC; signal s_axi_rlast_bmg_int : STD_LOGIC; signal s_axi_rresp_bmg_int : STD_LOGIC_VECTOR(1 DOWNTO 0); signal s_axi_rdata_bmg_int : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); signal s_axi_rid_bmg_int : STD_LOGIC_VECTOR(3 DOWNTO 0); signal s_axi_arready_bmg_int : STD_LOGIC; signal s_axi_bvalid_bmg_int : STD_LOGIC; signal s_axi_bresp_bmg_int : STD_LOGIC_VECTOR(1 DOWNTO 0); signal s_axi_bid_bmg_int : STD_LOGIC_VECTOR(3 DOWNTO 0); signal s_axi_wready_bmg_int : STD_LOGIC; signal s_axi_awready_bmg_int : STD_LOGIC; signal rdaddrecc_bmg_int : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0); signal dbiterr_bmg_int : STD_LOGIC; signal sbiterr_bmg_int : STD_LOGIC; begin bmgv81_inst : entity blk_mem_gen_v8_2.blk_mem_gen_v8_2 GENERIC MAP( ---------------------------------------------------------------------------- -- Generic Declarations ---------------------------------------------------------------------------- --Device Family & Elaboration Directory Parameters: C_FAMILY => C_FAMILY, C_XDEVICEFAMILY => C_FAMILY, ---- C_ELABORATION_DIR => "NULL" , C_INTERFACE_TYPE => 0 , --General Memory Parameters: ----- C_ENABLE_32BIT_ADDRESS => 0 , C_MEM_TYPE => MEM_TYPE , C_BYTE_SIZE => 8 , C_ALGORITHM => 1 , C_PRIM_TYPE => 1 , --Memory Initialization Parameters: C_LOAD_INIT_FILE => 0 , C_INIT_FILE_NAME => "no_coe_file_loaded" , C_USE_DEFAULT_DATA => 0 , C_DEFAULT_DATA => "NULL" , --Port A Parameters: --Reset Parameters: C_HAS_RSTA => 0 , --Enable Parameters: C_HAS_ENA => 1 , C_HAS_REGCEA => 0 , --Byte Write Enable Parameters: C_USE_BYTE_WEA => 1 , C_WEA_WIDTH => C_WEA_WIDTH_I, --(C_S_AXI_DATA_WIDTH/8 + C_ECC(1+(C_S_AXI_DATA_WIDTH/128))) , --Write Mode: C_WRITE_MODE_A => "WRITE_FIRST" , --Data-Addr Width Parameters: C_WRITE_WIDTH_A => C_WRITE_WIDTH_A_I,--(C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))) , C_READ_WIDTH_A => C_READ_WIDTH_A_I,--(C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))) , C_WRITE_DEPTH_A => C_MEMORY_DEPTH , C_READ_DEPTH_A => C_MEMORY_DEPTH , C_ADDRA_WIDTH => C_ADDRA_WIDTH_I,--log2roundup(C_MEMORY_DEPTH) , --Port B Parameters: --Reset Parameters: C_HAS_RSTB => 0 , --Enable Parameters: C_HAS_ENB => 1 , C_HAS_REGCEB => 0 , --Byte Write Enable Parameters: C_USE_BYTE_WEB => BWE_B , C_WEB_WIDTH => C_WEB_WIDTH_I,--(C_S_AXI_DATA_WIDTH/8 + C_ECC(1+(C_S_AXI_DATA_WIDTH/128))) , --Write Mode: C_WRITE_MODE_B => "WRITE_FIRST" , --Data-Addr Width Parameters: C_WRITE_WIDTH_B => C_WRITE_WIDTH_B_I,--(C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))) , C_READ_WIDTH_B => C_READ_WIDTH_B_I,--(C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))) , C_WRITE_DEPTH_B => C_MEMORY_DEPTH , C_READ_DEPTH_B => C_MEMORY_DEPTH , C_ADDRB_WIDTH => C_ADDRB_WIDTH,--log2roundup(C_MEMORY_DEPTH) , --Output Registers/ Pipelining Parameters: C_HAS_MEM_OUTPUT_REGS_A => 0 , C_HAS_MEM_OUTPUT_REGS_B => 0 , C_HAS_MUX_OUTPUT_REGS_A => 0 , C_HAS_MUX_OUTPUT_REGS_B => 0 , C_MUX_PIPELINE_STAGES => 0 , --Input/Output Registers for SoftECC : C_HAS_SOFTECC_INPUT_REGS_A => 0 , C_HAS_SOFTECC_OUTPUT_REGS_B=> 0 , --ECC Parameters C_USE_ECC => 0 , C_USE_SOFTECC => 0 , C_HAS_INJECTERR => 0 , C_EN_ECC_PIPE => 0, C_EN_SLEEP_PIN => 0, --Simulation Model Parameters: C_SIM_COLLISION_CHECK => "NONE" , C_COMMON_CLK => 1 , C_DISABLE_WARN_BHV_COLL => 1 , C_DISABLE_WARN_BHV_RANGE => 1 ) PORT MAP( ---------------------------------------------------------------------------- -- Input and Output Declarations ---------------------------------------------------------------------------- -- Native BMG Input and Output Port Declarations --Port A: clka => clka_bram_clka_i , rsta => rsta_bram_rsta_i , ena => ena_bram_ena_i , regcea => GND , wea => wea_bram_wea_i , addra => addra_bram_addra_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) , --addra => addra_bram_addra_i(C_S_AXI_ADDR_WIDTH-1 downto (C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) , dina => dina_bram_dina_i , douta => douta_bram_douta_i , --port b: clkb => clkb_bram_clkb_i , rstb => rstb_bram_rstb_i , enb => enb_bram_enb_i , regceb => GND , web => web_bram_web_i , addrb => addrb_bram_addrb_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) , --addrb => addrb_bram_addrb_i(C_S_AXI_ADDR_WIDTH-1 downto (C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) , dinb => dinb_bram_dinb_i , doutb => doutb_bram_doutb_i , --ecc: injectsbiterr => GND , injectdbiterr => GND , sbiterr => sbiterr_bmg_int, dbiterr => dbiterr_bmg_int, rdaddrecc => rdaddrecc_bmg_int, eccpipece => GND, sleep => GND, -- axi bmg input and output Port Declarations -- axi global signals s_aclk => GND , s_aresetn => GND , -- axi full/lite slave write (write side) s_axi_awid => ZERO4 , s_axi_awaddr => ZERO32 , s_axi_awlen => ZERO8 , s_axi_awsize => ZERO3 , s_axi_awburst => ZERO2 , s_axi_awvalid => GND , s_axi_awready => s_axi_awready_bmg_int, s_axi_wdata => ZERO64 , s_axi_wstrb => WSTRB_ZERO, s_axi_wlast => GND , s_axi_wvalid => GND , s_axi_wready => s_axi_wready_bmg_int, s_axi_bid => s_axi_bid_bmg_int, s_axi_bresp => s_axi_bresp_bmg_int, s_axi_bvalid => s_axi_bvalid_bmg_int, s_axi_bready => GND , -- axi full/lite slave read (Write side) s_axi_arid => ZERO4, s_axi_araddr => "00000000000000000000000000000000", s_axi_arlen => "00000000", s_axi_arsize => "000", s_axi_arburst => "00", s_axi_arvalid => '0', s_axi_arready => s_axi_arready_bmg_int, s_axi_rid => s_axi_rid_bmg_int, s_axi_rdata => s_axi_rdata_bmg_int, s_axi_rresp => s_axi_rresp_bmg_int, s_axi_rlast => s_axi_rlast_bmg_int, s_axi_rvalid => s_axi_rvalid_bmg_int, s_axi_rready => GND , -- axi full/lite sideband Signals s_axi_injectsbiterr => GND , s_axi_injectdbiterr => GND , s_axi_sbiterr => s_axi_sbiterr_bmg_int, s_axi_dbiterr => s_axi_dbiterr_bmg_int, s_axi_rdaddrecc => s_axi_rdaddrecc_bmg_int ); abcv4_0_int_inst : entity work.axi_bram_ctrl_top generic map( -- AXI Parameters C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , -- AXI ID vector width C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST , -- Support for narrow burst operations C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , -- Enable single port usage of BRAM -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC => C_ECC , -- Enables or disables ECC functionality C_ECC_TYPE => C_ECC_TYPE , C_FAULT_INJECT => C_FAULT_INJECT , -- Enable fault injection registers -- (default = disabled) C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE -- By default, ECC checking is on -- (can disable ECC @ reset by setting this to 0) ) port map( -- AXI Interface Signals -- AXI Clock and Reset S_AXI_ACLK => S_AXI_ACLK , S_AXI_ARESETN => S_AXI_ARESETN , ECC_Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , -- AXI Write Address Channel Signals (AW) S_AXI_AWID => S_AXI_AWID , S_AXI_AWADDR => S_AXI_AWADDR , S_AXI_AWLEN => S_AXI_AWLEN , S_AXI_AWSIZE => S_AXI_AWSIZE , S_AXI_AWBURST => S_AXI_AWBURST , S_AXI_AWLOCK => S_AXI_AWLOCK , S_AXI_AWCACHE => S_AXI_AWCACHE , S_AXI_AWPROT => S_AXI_AWPROT , S_AXI_AWVALID => S_AXI_AWVALID , S_AXI_AWREADY => S_AXI_AWREADY , -- AXI Write Data Channel Signals (W) S_AXI_WDATA => S_AXI_WDATA , S_AXI_WSTRB => S_AXI_WSTRB , S_AXI_WLAST => S_AXI_WLAST , S_AXI_WVALID => S_AXI_WVALID , S_AXI_WREADY => S_AXI_WREADY , -- AXI Write Data Response Channel Signals (B) S_AXI_BID => S_AXI_BID , S_AXI_BRESP => S_AXI_BRESP , S_AXI_BVALID => S_AXI_BVALID , S_AXI_BREADY => S_AXI_BREADY , -- AXI Read Address Channel Signals (AR) S_AXI_ARID => S_AXI_ARID , S_AXI_ARADDR => S_AXI_ARADDR , S_AXI_ARLEN => S_AXI_ARLEN , S_AXI_ARSIZE => S_AXI_ARSIZE , S_AXI_ARBURST => S_AXI_ARBURST , S_AXI_ARLOCK => S_AXI_ARLOCK , S_AXI_ARCACHE => S_AXI_ARCACHE , S_AXI_ARPROT => S_AXI_ARPROT , S_AXI_ARVALID => S_AXI_ARVALID , S_AXI_ARREADY => S_AXI_ARREADY , -- AXI Read Data Channel Signals (R) S_AXI_RID => S_AXI_RID , S_AXI_RDATA => S_AXI_RDATA , S_AXI_RRESP => S_AXI_RRESP , S_AXI_RLAST => S_AXI_RLAST , S_AXI_RVALID => S_AXI_RVALID , S_AXI_RREADY => S_AXI_RREADY , -- AXI-Lite ECC Register Interface Signals -- AXI-Lite Write Address Channel Signals (AW) S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID , S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY , S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR , -- AXI-Lite Write Data Channel Signals (W) S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA , S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID , S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY , -- AXI-Lite Write Data Response Channel Signals (B) S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP , S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID , S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY , -- AXI-Lite Read Address Channel Signals (AR) S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR , S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID , S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY , -- AXI-Lite Read Data Channel Signals (R) S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA , S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP , S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID , S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY , -- BRAM Interface Signals (Port A) BRAM_Rst_A => rsta_bram_rsta_i , BRAM_Clk_A => clka_bram_clka_i , BRAM_En_A => ena_bram_ena_i , BRAM_WE_A => wea_bram_wea_i , BRAM_Addr_A => addra_bram_addra_i, BRAM_WrData_A => dina_bram_dina_i , BRAM_RdData_A => douta_bram_douta_i , -- BRAM Interface Signals (Port B) BRAM_Rst_B => rstb_bram_rstb_i , BRAM_Clk_B => clkb_bram_clkb_i , BRAM_En_B => enb_bram_enb_i , BRAM_WE_B => web_bram_web_i , BRAM_Addr_B => addrb_bram_addrb_i , BRAM_WrData_B => dinb_bram_dinb_i , BRAM_RdData_B => doutb_bram_doutb_i ); -- The following signals are driven 0's to remove the synthesis warnings bram_rst_a <= '0'; bram_clk_a <= '0'; bram_en_a <= '0'; bram_we_a <= (others => '0'); bram_addr_a <= (others => '0'); bram_wrdata_a <= (others => '0'); bram_rst_b <= '0'; bram_clk_b <= '0'; bram_en_b <= '0'; bram_we_b <= (others => '0'); bram_addr_b <= (others => '0'); bram_wrdata_b <= (others => '0'); END GENERATE gint_inst; -- End of internal bram instance gext_inst: IF (C_BRAM_INST_MODE = "EXTERNAL" ) GENERATE abcv4_0_ext_inst : entity work.axi_bram_ctrl_top generic map( -- AXI Parameters C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , -- AXI ID vector width C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST , -- Support for narrow burst operations C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , -- Enable single port usage of BRAM -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC => C_ECC , -- Enables or disables ECC functionality C_ECC_TYPE => C_ECC_TYPE , C_FAULT_INJECT => C_FAULT_INJECT , -- Enable fault injection registers -- (default = disabled) C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE -- By default, ECC checking is on -- (can disable ECC @ reset by setting this to 0) ) port map( -- AXI Interface Signals -- AXI Clock and Reset s_axi_aclk => s_axi_aclk , s_axi_aresetn => s_axi_aresetn , ecc_interrupt => ecc_interrupt , ecc_ue => ecc_ue , -- axi write address channel signals (aw) s_axi_awid => s_axi_awid , s_axi_awaddr => s_axi_awaddr , s_axi_awlen => s_axi_awlen , s_axi_awsize => s_axi_awsize , s_axi_awburst => s_axi_awburst , s_axi_awlock => s_axi_awlock , s_axi_awcache => s_axi_awcache , s_axi_awprot => s_axi_awprot , s_axi_awvalid => s_axi_awvalid , s_axi_awready => s_axi_awready , -- axi write data channel signals (w) s_axi_wdata => s_axi_wdata , s_axi_wstrb => s_axi_wstrb , s_axi_wlast => s_axi_wlast , s_axi_wvalid => s_axi_wvalid , s_axi_wready => s_axi_wready , -- axi write data response channel signals (b) s_axi_bid => s_axi_bid , s_axi_bresp => s_axi_bresp , s_axi_bvalid => s_axi_bvalid , s_axi_bready => s_axi_bready , -- axi read address channel signals (ar) s_axi_arid => s_axi_arid , s_axi_araddr => s_axi_araddr , s_axi_arlen => s_axi_arlen , s_axi_arsize => s_axi_arsize , s_axi_arburst => s_axi_arburst , s_axi_arlock => s_axi_arlock , s_axi_arcache => s_axi_arcache , s_axi_arprot => s_axi_arprot , s_axi_arvalid => s_axi_arvalid , s_axi_arready => s_axi_arready , -- axi read data channel signals (r) s_axi_rid => s_axi_rid , s_axi_rdata => s_axi_rdata , s_axi_rresp => s_axi_rresp , s_axi_rlast => s_axi_rlast , s_axi_rvalid => s_axi_rvalid , s_axi_rready => s_axi_rready , -- axi-lite ecc register interface signals -- axi-lite write address channel signals (aw) s_axi_ctrl_awvalid => s_axi_ctrl_awvalid , s_axi_ctrl_awready => s_axi_ctrl_awready , s_axi_ctrl_awaddr => s_axi_ctrl_awaddr , -- axi-lite write data channel signals (w) s_axi_ctrl_wdata => s_axi_ctrl_wdata , s_axi_ctrl_wvalid => s_axi_ctrl_wvalid , s_axi_ctrl_wready => s_axi_ctrl_wready , -- axi-lite write data response channel signals (b) s_axi_ctrl_bresp => s_axi_ctrl_bresp , s_axi_ctrl_bvalid => s_axi_ctrl_bvalid , s_axi_ctrl_bready => s_axi_ctrl_bready , -- axi-lite read address channel signals (ar) s_axi_ctrl_araddr => s_axi_ctrl_araddr , s_axi_ctrl_arvalid => s_axi_ctrl_arvalid , s_axi_ctrl_arready => s_axi_ctrl_arready , -- axi-lite read data channel signals (r) s_axi_ctrl_rdata => s_axi_ctrl_rdata , s_axi_ctrl_rresp => s_axi_ctrl_rresp , s_axi_ctrl_rvalid => s_axi_ctrl_rvalid , s_axi_ctrl_rready => s_axi_ctrl_rready , -- bram interface signals (port a) bram_rst_a => bram_rst_a , bram_clk_a => bram_clk_a , bram_en_a => bram_en_a , bram_we_a => bram_we_a , bram_addr_a => bram_addr_a , bram_wrdata_a => bram_wrdata_a , bram_rddata_a => bram_rddata_a , -- bram interface signals (port b) bram_rst_b => bram_rst_b , bram_clk_b => bram_clk_b , bram_en_b => bram_en_b , bram_we_b => bram_we_b , bram_addr_b => bram_addr_b , bram_wrdata_b => bram_wrdata_b , bram_rddata_b => bram_rddata_b ); END GENERATE gext_inst; -- End of internal bram instance end architecture implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_ftch_q_mngr.vhd	3	45519	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_sg_ftch_queue.vhd -- Description: This entity is the descriptor fetch queue interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_ftch_q_mngr is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Stream Data width C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch for channel 1 C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch for channel 1 C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1; -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1; -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check C_INCLUDE_CH1 : integer range 0 to 1 := 1; -- Include or Exclude channel 1 scatter gather engine -- 0 = Exclude Channel 1 SG Engine -- 1 = Include Channel 1 SG Engine C_INCLUDE_CH2 : integer range 0 to 1 := 1; -- Include or Exclude channel 2 scatter gather engine -- 0 = Exclude Channel 2 SG Engine -- 1 = Include Channel 2 SG Engine C_ENABLE_CDMA : integer range 0 to 1 := 0; C_FAMILY : string := "virtex7" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_mm2s_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- p_reset_n : in std_logic ; ch2_sg_idle : in std_logic ; -- -- Channel 1 Control -- ch1_desc_flush : in std_logic ; -- ch1_cyclic : in std_logic ; -- ch1_cntrl_strm_stop : in std_logic ; ch1_ftch_active : in std_logic ; -- ch1_nxtdesc_wren : out std_logic ; -- ch1_ftch_queue_empty : out std_logic ; -- ch1_ftch_queue_full : out std_logic ; -- ch1_ftch_pause : out std_logic ; -- -- -- Channel 2 Control -- ch2_desc_flush : in std_logic ; -- ch2_cyclic : in std_logic ; -- ch2_ftch_active : in std_logic ; -- ch2_nxtdesc_wren : out std_logic ; -- ch2_ftch_queue_empty : out std_logic ; -- ch2_ftch_queue_full : out std_logic ; -- ch2_ftch_pause : out std_logic ; -- nxtdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- -- DataMover Command -- ftch_cmnd_wr : in std_logic ; -- ftch_cmnd_data : in std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- ftch_stale_desc : out std_logic ; -- -- -- MM2S Stream In from DataMover -- m_axis_mm2s_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_mm2s_tkeep : in std_logic_vector -- ((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0); -- m_axis_mm2s_tlast : in std_logic ; -- m_axis_mm2s_tvalid : in std_logic ; -- m_axis_mm2s_tready : out std_logic ; -- -- -- -- Channel 1 AXI Fetch Stream Out -- m_axis_ch1_ftch_aclk : in std_logic ; m_axis_ch1_ftch_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); -- m_axis_ch1_ftch_tvalid : out std_logic ; -- m_axis_ch1_ftch_tready : in std_logic ; -- m_axis_ch1_ftch_tlast : out std_logic ; -- m_axis_ch1_ftch_tdata_new : out std_logic_vector -- (96+31C_ENABLE_CDMA downto 0); -- m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis_ch1_ftch_tvalid_new : out std_logic ; -- m_axis_ftch1_desc_available : out std_logic ; -- m_axis_ch2_ftch_tdata_new : out std_logic_vector -- (96+31C_ENABLE_CDMA downto 0); -- m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector -- (31 downto 0); -- m_axis_ch2_ftch_tvalid_new : out std_logic ; -- m_axis_ftch2_desc_available : out std_logic ; -- -- Channel 2 AXI Fetch Stream Out -- m_axis_ch2_ftch_aclk : in std_logic ; -- m_axis_ch2_ftch_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_ch2_ftch_tvalid : out std_logic ; -- m_axis_ch2_ftch_tready : in std_logic ; -- m_axis_ch2_ftch_tlast : out std_logic ; -- m_axis_mm2s_cntrl_tdata : out std_logic_vector -- (31 downto 0); -- m_axis_mm2s_cntrl_tkeep : out std_logic_vector -- (3 downto 0); -- m_axis_mm2s_cntrl_tvalid : out std_logic ; -- m_axis_mm2s_cntrl_tready : in std_logic := '0'; -- m_axis_mm2s_cntrl_tlast : out std_logic -- ); end axi_sg_ftch_q_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_ftch_q_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; attribute mark_debug : string; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Determine the maximum word count for use in setting the word counter width -- Set bit width on max num words to fetch constant FETCH_COUNT : integer := max2(C_SG_CH1_WORDS_TO_FETCH ,C_SG_CH2_WORDS_TO_FETCH); -- LOG2 to get width of counter constant WORDS2FETCH_BITWIDTH : integer := clog2(FETCH_COUNT); -- Zero value for counter constant WORD_ZERO : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0'); -- One value for counter constant WORD_ONE : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0) := std_logic_vector(to_unsigned(1,WORDS2FETCH_BITWIDTH)); -- Seven value for counter constant WORD_SEVEN : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0) := std_logic_vector(to_unsigned(7,WORDS2FETCH_BITWIDTH)); constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal m_axis_mm2s_tready_i : std_logic := '0'; signal ch1_ftch_tready : std_logic := '0'; signal ch2_ftch_tready : std_logic := '0'; -- Misc Signals signal writing_curdesc : std_logic := '0'; signal fetch_word_count : std_logic_vector (WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0'); signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0'); signal lsbnxtdesc_tready : std_logic := '0'; signal msbnxtdesc_tready : std_logic := '0'; signal nxtdesc_tready : std_logic := '0'; signal ch1_writing_curdesc : std_logic := '0'; signal ch2_writing_curdesc : std_logic := '0'; signal m_axis_ch2_ftch_tvalid_1 : std_logic := '0'; -- KAPIL signal ch_desc_flush : std_logic := '0'; signal m_axis_ch_ftch_tready : std_logic := '0'; signal ch_ftch_queue_empty : std_logic := '0'; signal ch_ftch_queue_full : std_logic := '0'; signal ch_ftch_pause : std_logic := '0'; signal ch_writing_curdesc : std_logic := '0'; signal ch_ftch_tready : std_logic := '0'; signal m_axis_ch_ftch_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal m_axis_ch_ftch_tvalid : std_logic := '0'; signal m_axis_ch_ftch_tlast : std_logic := '0'; signal data_concat : std_logic_vector (95 downto 0) := (others => '0'); signal data_concat_mcdma : std_logic_vector (63 downto 0) := (others => '0'); signal next_bd : std_logic_vector (31 downto 0) := (others => '0'); signal data_concat_valid, tvalid_new : std_logic; attribute mark_debug of data_concat_valid : signal is "true"; attribute mark_debug of tvalid_new : signal is "true"; signal data_concat_tlast, tlast_new : std_logic; attribute mark_debug of data_concat_tlast : signal is "true"; attribute mark_debug of tlast_new : signal is "true"; signal counter : std_logic_vector (C_SG_CH1_WORDS_TO_FETCH-1 downto 0); attribute mark_debug of counter : signal is "true"; signal sof_ftch_desc : std_logic; signal nxtdesc_int : std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- attribute mark_debug of nxtdesc_int : signal is "true"; signal cyclic_enable : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin cyclic_enable <= ch1_cyclic when ch1_ftch_active = '1' else ch2_cyclic; nxtdesc <= nxtdesc_int; TLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH = 13) generate -- TLAST is generated when 8th beat is received tlast_new <= counter (7) and m_axis_mm2s_tvalid; tvalid_new <= counter (7) and m_axis_mm2s_tvalid; SOF_CHECK : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tvalid = '1' and m_axis_mm2s_tlast = '1'))then sof_ftch_desc <= '0'; elsif(counter (6) = '1' and m_axis_mm2s_tready_i = '1' and m_axis_mm2s_tdata(27) = '1' )then sof_ftch_desc <= '1'; end if; end if; end process SOF_CHECK; end generate TLAST_GEN; NOTLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH /= 13) generate sof_ftch_desc <= '0'; CDMA : if C_ENABLE_CDMA = 1 generate -- For CDMA TLAST is generated when 7th beat is received -- because last one is not needed tlast_new <= counter (6) and m_axis_mm2s_tvalid; tvalid_new <=counter (6) and m_axis_mm2s_tvalid; end generate CDMA; NOCDMA : if C_ENABLE_CDMA = 0 generate -- For DMA tlast is generated with 8th beat tlast_new <= counter (7) and m_axis_mm2s_tvalid; tvalid_new <= counter (7) and m_axis_mm2s_tvalid; end generate NOCDMA; end generate NOTLAST_GEN; -- Following shift register keeps track of number of data beats -- of BD that is being read DATA_BEAT_REG : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1')) then counter (0) <= '1'; counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= (others => '0'); Elsif (m_axis_mm2s_tvalid = '1') then counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= counter (C_SG_CH1_WORDS_TO_FETCH-2 downto 0); counter (0) <= '0'; end if; end if; end process DATA_BEAT_REG; -- Registering the Buffer address from BD, 3rd beat -- Common for DMA, CDMA DATA_REG1 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (31 downto 0) <= (others => '0'); Elsif (counter (2) = '1') then data_concat (31 downto 0) <= m_axis_mm2s_tdata; end if; end if; end process DATA_REG1; DMA_REG2 : if C_ENABLE_CDMA = 0 generate begin -- For DMA, the 7th beat has the control information DATA_REG2 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (63 downto 32) <= (others => '0'); Elsif (counter (6) = '1') then data_concat (63 downto 32) <= m_axis_mm2s_tdata; end if; end if; end process DATA_REG2; end generate DMA_REG2; CDMA_REG2 : if C_ENABLE_CDMA = 1 generate begin -- For CDMA, the 5th beat has the DA information DATA_REG2 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (63 downto 32) <= (others => '0'); Elsif (counter (4) = '1') then data_concat (63 downto 32) <= m_axis_mm2s_tdata; end if; end if; end process DATA_REG2; end generate CDMA_REG2; NOFLOP_FOR_QUEUE : if C_SG_CH1_WORDS_TO_FETCH = 8 generate begin -- Last beat is directly concatenated and passed to FIFO -- Masking the CMPLT bit with cyclic_enable data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0); data_concat_valid <= tvalid_new; data_concat_tlast <= tlast_new; end generate NOFLOP_FOR_QUEUE; -- In absence of queuing option the last beat needs to be floped FLOP_FOR_NOQUEUE : if C_SG_CH1_WORDS_TO_FETCH = 13 generate begin NO_FETCH_Q : if C_SG_FTCH_DESC2QUEUE = 0 generate DATA_REG3 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (95 downto 64) <= (others => '0'); Elsif (counter (7) = '1') then data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0); end if; end if; end process DATA_REG3; end generate NO_FETCH_Q; FETCH_Q : if C_SG_FTCH_DESC2QUEUE /= 0 generate DATA_REG3 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (95) <= '0'; Elsif (counter (7) = '1') then data_concat (95) <= m_axis_mm2s_tdata (31) and (not cyclic_enable); end if; end if; end process DATA_REG3; data_concat (94 downto 64) <= (others => '0'); end generate FETCH_Q; DATA_CNTRL : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat_valid <= '0'; data_concat_tlast <= '0'; Else data_concat_valid <= tvalid_new; data_concat_tlast <= tlast_new; end if; end if; end process DATA_CNTRL; end generate FLOP_FOR_NOQUEUE; -- Since the McDMA BD has two more fields to be captured -- following procedures are needed NOMCDMA_FTECH : if C_ENABLE_MULTI_CHANNEL = 0 generate begin data_concat_mcdma <= (others => '0'); end generate NOMCDMA_FTECH; MCDMA_BD_FETCH : if C_ENABLE_MULTI_CHANNEL = 1 generate begin DATA_MCDMA_REG1 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat_mcdma (31 downto 0) <= (others => '0'); Elsif (counter (4) = '1') then data_concat_mcdma (31 downto 0) <= m_axis_mm2s_tdata; end if; end if; end process DATA_MCDMA_REG1; DATA_MCDMA_REG2 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat_mcdma (63 downto 32) <= (others => '0'); Elsif (counter (5) = '1') then data_concat_mcdma (63 downto 32) <= m_axis_mm2s_tdata; end if; end if; end process DATA_MCDMA_REG2; end generate MCDMA_BD_FETCH; --------------------------------------------------------------------------- -- For 32-bit SG addresses then drive zero on msb --------------------------------------------------------------------------- GEN_CURDESC_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin msb_curdesc <= (others => '0'); end generate GEN_CURDESC_32; --------------------------------------------------------------------------- -- For 64-bit SG addresses then capture upper order adder to msb --------------------------------------------------------------------------- GEN_CURDESC_64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin CAPTURE_CURADDR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then msb_curdesc <= (others => '0'); elsif(ftch_cmnd_wr = '1')then msb_curdesc <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto DATAMOVER_CMD_ADDRMSB_BOFST + DATAMOVER_CMD_ADDRLSB_BIT + 1); end if; end if; end process CAPTURE_CURADDR; end generate GEN_CURDESC_64; --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_LSB_NXTPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then nxtdesc_int(31 downto 0) <= (others => '0'); -- On valid and word count at 0 and channel active capture LSB next pointer elsif(m_axis_mm2s_tvalid = '1' and counter (0) = '1')then nxtdesc_int(31 downto 6) <= m_axis_mm2s_tdata (31 downto 6); -- BD addresses are always 16 word 32-bit aligned nxtdesc_int(5 downto 0) <= (others => '0'); end if; end if; end process REG_LSB_NXTPNTR; lsbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1' and counter (0) = '1' --etch_word_count = WORD_ZERO else '0'; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_NXTPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then nxtdesc_int(63 downto 32) <= (others => '0'); ch1_nxtdesc_wren <= '0'; ch2_nxtdesc_wren <= '0'; -- Capture upper pointer, drive ready to progress DataMover -- and also write nxtdesc out elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then nxtdesc_int(63 downto 32) <= m_axis_mm2s_tdata; ch1_nxtdesc_wren <= ch1_ftch_active; ch2_nxtdesc_wren <= ch2_ftch_active; -- Assert tready/wren for only 1 clock else ch1_nxtdesc_wren <= '0'; ch2_nxtdesc_wren <= '0'; end if; end if; end process REG_MSB_NXTPNTR; msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1' and counter (1) = '1' --fetch_word_count = WORD_ONE else '0'; end generate GEN_UPPER_MSB_NXTDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_NO_UPR_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_NXTPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then ch1_nxtdesc_wren <= '0'; ch2_nxtdesc_wren <= '0'; -- Throw away second word but drive ready to progress DataMover -- and also write nxtdesc out elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then --fetch_word_count = WORD_ONE)then ch1_nxtdesc_wren <= ch1_ftch_active; ch2_nxtdesc_wren <= ch2_ftch_active; -- Assert for only 1 clock else ch1_nxtdesc_wren <= '0'; ch2_nxtdesc_wren <= '0'; end if; end if; end process REG_MSB_NXTPNTR; msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1' and counter (1) = '1' --fetch_word_count = WORD_ONE else '0'; end generate GEN_NO_UPR_MSB_NXTDESC; -- Drive ready to DataMover for ether lsb or msb capture nxtdesc_tready <= msbnxtdesc_tready or lsbnxtdesc_tready; -- Generate logic for checking stale descriptor GEN_STALE_DESC_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 or C_SG_CH2_ENBL_STALE_ERROR = 1 generate begin --------------------------------------------------------------------------- -- Examine Completed BIT to determine if stale descriptor fetched --------------------------------------------------------------------------- CMPLTD_CHECK : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then ftch_stale_desc <= '0'; -- On valid and word count at 0 and channel active capture LSB next pointer elsif(m_axis_mm2s_tvalid = '1' and counter (7) = '1' --fetch_word_count = WORD_SEVEN and m_axis_mm2s_tready_i = '1' and m_axis_mm2s_tdata(DESC_STS_CMPLTD_BIT) = '1' )then ftch_stale_desc <= '1' and (not cyclic_enable); else ftch_stale_desc <= '0'; end if; end if; end process CMPLTD_CHECK; end generate GEN_STALE_DESC_CHECK; -- No needed logic for checking stale descriptor GEN_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 and C_SG_CH2_ENBL_STALE_ERROR = 0 generate begin ftch_stale_desc <= '0'; end generate GEN_NO_STALE_CHECK; --------------------------------------------------------------------------- -- SG Queueing therefore pass stream signals to -- FIFO --------------------------------------------------------------------------- GEN_QUEUE : if C_SG_FTCH_DESC2QUEUE /= 0 generate begin -- Instantiate the queue version FTCH_QUEUE_I : entity axi_sg_v4_1.axi_sg_ftch_queue generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH , C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE , C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH , C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC , C_ASYNC => C_ASYNC , C_FAMILY => C_FAMILY , C_SG2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH , C_INCLUDE_MM2S => C_INCLUDE_CH1, C_INCLUDE_S2MM => C_INCLUDE_CH2, C_ENABLE_CDMA => C_ENABLE_CDMA, C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_primary_aclk => m_axi_mm2s_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , p_reset_n => p_reset_n , ch2_sg_idle => '0' , -- Channel Control desc1_flush => ch1_desc_flush , desc2_flush => ch2_desc_flush , ch1_cntrl_strm_stop => ch1_cntrl_strm_stop , ftch1_active => ch1_ftch_active , ftch2_active => ch2_ftch_active , ftch1_queue_empty => ch1_ftch_queue_empty , ftch2_queue_empty => ch2_ftch_queue_empty , ftch1_queue_full => ch1_ftch_queue_full , ftch2_queue_full => ch2_ftch_queue_full , ftch1_pause => ch1_ftch_pause , ftch2_pause => ch2_ftch_pause , writing_nxtdesc_in => nxtdesc_tready , writing1_curdesc_out => ch1_writing_curdesc , writing2_curdesc_out => ch2_writing_curdesc , -- DataMover Command ftch_cmnd_wr => ftch_cmnd_wr , ftch_cmnd_data => ftch_cmnd_data , -- MM2S Stream In from DataMover m_axis_mm2s_tdata => m_axis_mm2s_tdata , m_axis_mm2s_tlast => m_axis_mm2s_tlast , m_axis_mm2s_tvalid => m_axis_mm2s_tvalid , sof_ftch_desc => sof_ftch_desc , next_bd => nxtdesc_int , data_concat => data_concat, data_concat_mcdma => data_concat_mcdma, data_concat_valid => data_concat_valid, data_concat_tlast => data_concat_tlast, m_axis1_mm2s_tready => ch1_ftch_tready , m_axis2_mm2s_tready => ch2_ftch_tready , -- Channel 1 AXI Fetch Stream Out m_axis_ftch_aclk => m_axi_sg_aclk, --m_axis_ch_ftch_aclk , m_axis_ftch1_tdata => m_axis_ch1_ftch_tdata , m_axis_ftch1_tvalid => m_axis_ch1_ftch_tvalid , m_axis_ftch1_tready => m_axis_ch1_ftch_tready , m_axis_ftch1_tlast => m_axis_ch1_ftch_tlast , m_axis_ftch1_tdata_new => m_axis_ch1_ftch_tdata_new , m_axis_ftch1_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new , m_axis_ftch1_tvalid_new => m_axis_ch1_ftch_tvalid_new , m_axis_ftch1_desc_available => m_axis_ftch1_desc_available , m_axis_ftch2_tdata_new => m_axis_ch2_ftch_tdata_new , m_axis_ftch2_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new , m_axis_ftch2_tvalid_new => m_axis_ch2_ftch_tvalid_new , m_axis_ftch2_desc_available => m_axis_ftch2_desc_available , m_axis_ftch2_tdata => m_axis_ch2_ftch_tdata , m_axis_ftch2_tvalid => m_axis_ch2_ftch_tvalid , m_axis_ftch2_tready => m_axis_ch2_ftch_tready , m_axis_ftch2_tlast => m_axis_ch2_ftch_tlast , m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata , m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep , m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid , m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready , m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ); m_axis_ch2_ftch_tdata_mcdma_nxt <= (others => '0'); end generate GEN_QUEUE; -- No SG Queueing therefore pass stream signals straight -- out channel port GEN_NO_QUEUE : if C_SG_FTCH_DESC2QUEUE = 0 generate begin -- Instantiate the No queue version NO_FTCH_QUEUE_I : entity axi_sg_v4_1.axi_sg_ftch_noqueue generic map ( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH, C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL, C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC , C_ASYNC => C_ASYNC , C_FAMILY => C_FAMILY , C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH , C_ENABLE_CH1 => C_INCLUDE_CH1 ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_primary_aclk => m_axi_mm2s_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , p_reset_n => p_reset_n , -- Channel Control desc_flush => ch1_desc_flush , ch1_cntrl_strm_stop => ch1_cntrl_strm_stop , ftch_active => ch1_ftch_active , ftch_queue_empty => ch1_ftch_queue_empty , ftch_queue_full => ch1_ftch_queue_full , desc2_flush => ch2_desc_flush , ftch2_active => ch2_ftch_active , ftch2_queue_empty => ch2_ftch_queue_empty , ftch2_queue_full => ch2_ftch_queue_full , writing_nxtdesc_in => nxtdesc_tready , writing_curdesc_out => ch1_writing_curdesc , writing2_curdesc_out => ch2_writing_curdesc , -- DataMover Command ftch_cmnd_wr => ftch_cmnd_wr , ftch_cmnd_data => ftch_cmnd_data , -- MM2S Stream In from DataMover m_axis_mm2s_tdata => m_axis_mm2s_tdata , m_axis_mm2s_tlast => m_axis_mm2s_tlast , m_axis_mm2s_tvalid => m_axis_mm2s_tvalid , m_axis_mm2s_tready => ch1_ftch_tready , m_axis2_mm2s_tready => ch2_ftch_tready , sof_ftch_desc => sof_ftch_desc , next_bd => nxtdesc_int , data_concat => data_concat, data_concat_mcdma => data_concat_mcdma, data_concat_valid => data_concat_valid, data_concat_tlast => data_concat_tlast, -- Channel 1 AXI Fetch Stream Out m_axis_ftch_tdata => m_axis_ch1_ftch_tdata , m_axis_ftch_tvalid => m_axis_ch1_ftch_tvalid , m_axis_ftch_tready => m_axis_ch1_ftch_tready , m_axis_ftch_tlast => m_axis_ch1_ftch_tlast , m_axis_ftch_tdata_new => m_axis_ch1_ftch_tdata_new , m_axis_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new , m_axis_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new , m_axis_ftch_desc_available => m_axis_ftch1_desc_available , m_axis2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new , m_axis2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new , m_axis2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt , m_axis2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new , m_axis2_ftch_desc_available => m_axis_ftch2_desc_available , m_axis2_ftch_tdata => m_axis_ch2_ftch_tdata , m_axis2_ftch_tvalid => m_axis_ch2_ftch_tvalid , m_axis2_ftch_tready => m_axis_ch2_ftch_tready , m_axis2_ftch_tlast => m_axis_ch2_ftch_tlast , m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata , m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep , m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid , m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready , m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ); ch1_ftch_pause <= '0'; ch2_ftch_pause <= '0'; end generate GEN_NO_QUEUE; ------------------------------------------------------------------------------- -- DataMover TREADY MUX ------------------------------------------------------------------------------- writing_curdesc <= ch1_writing_curdesc or ch2_writing_curdesc or ftch_cmnd_wr; TREADY_MUX : process(writing_curdesc, fetch_word_count, nxtdesc_tready, -- channel 1 signals ch1_ftch_active, ch1_desc_flush, ch1_ftch_tready, -- channel 2 signals ch2_ftch_active, ch2_desc_flush, counter(0), counter(1), ch2_ftch_tready) begin -- If commmanded to flush descriptor then assert ready -- to datamover until active de-asserts. this allows -- any commanded fetches to complete. if( (ch1_desc_flush = '1' and ch1_ftch_active = '1') or(ch2_desc_flush = '1' and ch2_ftch_active = '1'))then m_axis_mm2s_tready_i <= '1'; -- NOT ready if cmnd being written because -- curdesc gets written to queue elsif(writing_curdesc = '1')then m_axis_mm2s_tready_i <= '0'; -- First two words drive ready from internal logic elsif(counter(0) = '1' or counter(1)='1')then m_axis_mm2s_tready_i <= nxtdesc_tready; -- Remainder stream words drive ready from channel input else m_axis_mm2s_tready_i <= (ch1_ftch_active and ch1_ftch_tready) or (ch2_ftch_active and ch2_ftch_tready); end if; end process TREADY_MUX; m_axis_mm2s_tready <= m_axis_mm2s_tready_i; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_s2mm_omit_wrap.vhd	18	17501	------------------------------------------------------------------------------- -- axi_datamover_s2mm_omit_wrap.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_omit_wrap.vhd -- -- Description: -- This file implements the DataMover MM2S Omit Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_omit_wrap is generic ( C_INCLUDE_S2MM : Integer range 0 to 2 := 0; -- Specifies the type of S2MM function to include -- 0 = Omit S2MM functionality -- 1 = Full S2MM Functionality -- 2 = Lite S2MM functionality C_S2MM_AWID : Integer range 0 to 255 := 9; -- Specifies the constant value to output on -- the ARID output port C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the S2MM ID port C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the S2MM Master Stream Data -- Channel data bus C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit S2MM Status FIFO -- 1 = Include S2MM Status FIFO C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the S2MM Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the S2MM function -- 0 = Omit DRE -- 1 = Include DRE C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the S2MM function C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if Store and Forward is enabled C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1; -- This parameter specifies the depth of the S2MM internal -- address pipeline queues in the Write Address Controller -- and the Write Data Controller. Increasing this value will -- allow more Write Addresses to be issued to the AXI4 Write -- Address Channel before transmission of the associated -- write data on the Write Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- S2MM Primary Clock and reset inputs ----------------------- s2mm_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- S2MM Primary Reset input -- s2mm_aresetn : in std_logic; -- -- Reset used for the internal master logic -- -------------------------------------------------------------- -- S2MM Halt request input control --------------------------- s2mm_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- S2MM Halt Complete status flag -- s2mm_halt_cmplt : out std_logic; -- -- Active high soft shutdown complete status -- -------------------------------------------------------------- -- S2MM Error discrete output -------------------------------- s2mm_err : Out std_logic; -- -- Composite Error indication -- -------------------------------------------------------------- -- Optional S2MM Command/Status Clock and Reset Inputs ------- -- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 -- s2mm_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- s2mm_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- -------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) ----------------------------------------------------- s2mm_cmd_wvalid : in std_logic; -- s2mm_cmd_wready : out std_logic; -- s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); -- -------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) -------------------------------------------------------- s2mm_sts_wvalid : out std_logic; -- s2mm_sts_wready : in std_logic; -- s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT24)+8)-1 downto 0); -- s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); -- s2mm_sts_wlast : out std_logic; -- ---------------------------------------------------------------------------------------------------- -- Address posting controls ----------------------------------------- s2mm_allow_addr_req : in std_logic; -- s2mm_addr_req_posted : out std_logic; -- s2mm_wr_xfer_cmplt : out std_logic; -- s2mm_ld_nxt_len : out std_logic; -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- --------------------------------------------------------------------- -- S2MM AXI Address Channel I/O -------------------------------------- s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- s2mm_awlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- s2mm_awsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- s2mm_awburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- s2mm_awprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- s2mm_awuser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- s2mm_awready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ----------- -- s2mm__awlock : out std_logic_vector(2 downto 0); -- -- s2mm__awcache : out std_logic_vector(4 downto 0); -- -- s2mm__awqos : out std_logic_vector(3 downto 0); -- -- s2mm__awregion : out std_logic_vector(3 downto 0); -- ----------------------------------------------------------------------- -- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------- s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); -- s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); -- s2mm_wlast : Out std_logic; -- s2mm_wvalid : Out std_logic; -- s2mm_wready : In std_logic; -- --------------------------------------------------------------------------------------- -- S2MM AXI MMap Write response Channel I/O ------------------------------------------ s2mm_bresp : In std_logic_vector(1 downto 0); -- s2mm_bvalid : In std_logic; -- s2mm_bready : Out std_logic; -- --------------------------------------------------------------------------------------- -- S2MM AXI Master Stream Channel I/O ------------------------------------------------ s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); -- s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); -- s2mm_strm_wlast : In std_logic; -- s2mm_strm_wvalid : In std_logic; -- s2mm_strm_wready : Out std_logic; -- --------------------------------------------------------------------------------------- -- Testing Support I/O ----------------------------------------- s2mm_dbg_sel : in std_logic_vector( 3 downto 0); -- s2mm_dbg_data : out std_logic_vector(31 downto 0) -- ---------------------------------------------------------------- ); end entity axi_datamover_s2mm_omit_wrap; architecture implementation of axi_datamover_s2mm_omit_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; begin --(architecture implementation) -- Just tie off output ports s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type s2mm_addr_req_posted <= '0' ; s2mm_wr_xfer_cmplt <= '0' ; s2mm_ld_nxt_len <= '0' ; s2mm_wr_len <= (others => '0'); s2mm_halt_cmplt <= s2mm_halt ; s2mm_err <= '0' ; s2mm_cmd_wready <= '0' ; s2mm_sts_wvalid <= '0' ; s2mm_sts_wdata <= (others => '0'); s2mm_sts_wstrb <= (others => '0'); s2mm_sts_wlast <= '0' ; s2mm_awid <= (others => '0'); s2mm_awaddr <= (others => '0'); s2mm_awlen <= (others => '0'); s2mm_awsize <= (others => '0'); s2mm_awburst <= (others => '0'); s2mm_awprot <= (others => '0'); s2mm_awcache <= (others => '0'); s2mm_awuser <= (others => '0'); s2mm_awvalid <= '0' ; s2mm_wdata <= (others => '0'); s2mm_wstrb <= (others => '0'); s2mm_wlast <= '0' ; s2mm_wvalid <= '0' ; s2mm_bready <= '0' ; s2mm_strm_wready <= '0' ; -- Input ports are ignored end implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/FIFO_image_filter_p_src_cols_V_channel1.vhd	2	4636	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_p_src_cols_V_channel1_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_p_src_cols_V_channel1_shiftReg; architecture rtl of FIFO_image_filter_p_src_cols_V_channel1_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_p_src_cols_V_channel1 is generic ( MEM_STYLE : string := "shiftreg"; DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_p_src_cols_V_channel1 is component FIFO_image_filter_p_src_cols_V_channel1_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_p_src_cols_V_channel1_shiftReg : FIFO_image_filter_p_src_cols_V_channel1_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s06/AXI_STREAM_HLS_S06/HLS/simple_axi_stream_counter/solution1/impl/vhdl/axi_stream_counter.vhd	3	7508	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity axi_stream_counter is port ( ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; counter_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0); counter_TVALID : OUT STD_LOGIC; counter_TREADY : IN STD_LOGIC; ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of axi_stream_counter is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "axi_stream_counter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.440000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=34,HLS_SYN_LUT=34}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; signal ap_rst_n_inv : STD_LOGIC; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_bdd_19 : BOOLEAN; signal counterValue : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal counterValue_assign_fu_34_p2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_ioackin_counter_TREADY : STD_LOGIC; signal ap_reg_ioackin_counter_TREADY : STD_LOGIC := '0'; signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_bdd_60 : BOOLEAN; begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ioackin_counter_TREADY assign process. -- ap_reg_ioackin_counter_TREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ioackin_counter_TREADY <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then if (not(((ap_start = ap_const_logic_0) or (ap_const_logic_0 = ap_sig_ioackin_counter_TREADY)))) then ap_reg_ioackin_counter_TREADY <= ap_const_logic_0; elsif (ap_sig_bdd_60) then ap_reg_ioackin_counter_TREADY <= ap_const_logic_1; end if; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(((ap_start = ap_const_logic_0) or (ap_const_logic_0 = ap_sig_ioackin_counter_TREADY))))) then counterValue <= counterValue_assign_fu_34_p2; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_sig_ioackin_counter_TREADY) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => ap_NS_fsm <= ap_ST_st1_fsm_0; when others => ap_NS_fsm <= "X"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_ioackin_counter_TREADY) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(((ap_start = ap_const_logic_0) or (ap_const_logic_0 = ap_sig_ioackin_counter_TREADY))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_ioackin_counter_TREADY) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(((ap_start = ap_const_logic_0) or (ap_const_logic_0 = ap_sig_ioackin_counter_TREADY))))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_return <= ap_const_lv32_0; -- ap_rst_n_inv assign process. -- ap_rst_n_inv_assign_proc : process(ap_rst_n) begin ap_rst_n_inv <= not(ap_rst_n); end process; -- ap_sig_bdd_19 assign process. -- ap_sig_bdd_19_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_19 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; -- ap_sig_bdd_60 assign process. -- ap_sig_bdd_60_assign_proc : process(ap_start, counter_TREADY) begin ap_sig_bdd_60 <= (not((ap_start = ap_const_logic_0)) and (ap_const_logic_1 = counter_TREADY)); end process; -- ap_sig_cseq_ST_st1_fsm_0 assign process. -- ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_19) begin if (ap_sig_bdd_19) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; -- ap_sig_ioackin_counter_TREADY assign process. -- ap_sig_ioackin_counter_TREADY_assign_proc : process(counter_TREADY, ap_reg_ioackin_counter_TREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_counter_TREADY)) then ap_sig_ioackin_counter_TREADY <= counter_TREADY; else ap_sig_ioackin_counter_TREADY <= ap_const_logic_1; end if; end process; counterValue_assign_fu_34_p2 <= std_logic_vector(unsigned(counterValue) + unsigned(ap_const_lv32_1)); counter_TDATA <= std_logic_vector(unsigned(counterValue) + unsigned(ap_const_lv32_1)); -- counter_TVALID assign process. -- counter_TVALID_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_reg_ioackin_counter_TREADY) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (ap_const_logic_0 = ap_reg_ioackin_counter_TREADY))) then counter_TVALID <= ap_const_logic_1; else counter_TVALID <= ap_const_logic_0; end if; end process; end behav;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_ise/hw/xps_proj/pcores/logicvc_v3_00_a/doc/logicvc_comp.vhd	1	22930	package logicbricks is -- START COMPONENT component logicvc is generic ( -- Version generics C_IP_LICENSE_TYPE : integer := 0; -- IP encryption type: 0 = source, 1 = evaluation, 2 = release, 3 = university evaluation C_IP_MAJOR_REVISION : integer := 0; -- IP major revision: 0 - 31; vXX_yy_z C_IP_MINOR_REVISION : integer := 0; -- IP minor revision: 0 - 31; vxx_YY_z C_IP_PATCH_LEVEL : integer := 0; -- IP patch level: 0 - 25; vxx_yy_Z C_IP_LICENSE_CHECK : integer := 0; -- IP license check: 0 = no, 1 = yes C_IP_TIME_BEFORE_BREAK : integer := 0; -- IP time before break: 0 = infinite, 1 = 1h, 2 = 12h, 3 = 24h C_FAMILY : string := "spartan6"; -- Video memory generics C_VMEM_INTERFACE : integer := 0; -- Use PLB, XMB or AXI to access video memory: 0 - PLB, 1 - XMB, 2 - AXI C_VMEM_BASEADDR : std_logic_vector := x"FFFFFFFF"; C_VMEM_HIGHADDR : std_logic_vector := x"00000000"; C_MEM_BURST : integer := 4; -- Memory burst width; 4, 5 or 6. (4 means burst lasts 16 transfers), Used for XMB and AXI C_MEM_BYTE_SWAP : integer := 0; -- Memory access byte swap: 0 - Do not swap, 1 - Swap C_MEM_LITTLE_ENDIAN : integer := 1; -- Memory access endianness: 0 - Big endian, 1 - Little endian C_INCREASE_FIFO : integer := 1; -- FIFO size multiplication factor: 1=1x, 2=2x, 4=4x, 8=8x -- Master PLB generics C_MPLB_NUM_MASTERS : integer := 8; C_MPLB_AWIDTH : integer := 32; C_MPLB_DWIDTH : integer := 64; C_MPLB_PRIORITY : integer := 3; C_MPLB_SMALLEST_SLAVE : integer := 32; -- XMB generics C_XMB_DATA_BUS_WIDTH : integer := 64; -- XMB Memory interface data bus width -- Master AXI generics C_M_AXI_THREAD_ID_WIDTH : integer := 1; C_M_AXI_DATA_WIDTH : integer := 64; C_M_AXI_ADDR_WIDTH : integer := 32; -- Registers generics C_REGS_INTERFACE : integer := 0; -- Use OPB, PLB or AXI interface for registers: 0 - OPB, 1 - PLB, 2 - AXI C_READABLE_REGS : integer := 1; -- Are logiCVC registers readable?: 0 - no, 1 - yes C_REG_BYTE_SWAP : integer := 0; -- Registers access byte swap: 0 - Do not swap, 1 - Swap -- OPB generics C_REGS_BASEADDR : std_logic_vector := x"FFFFFFFF"; C_REGS_HIGHADDR : std_logic_vector := x"00000000"; C_OPB_AWIDTH : integer := 32; C_OPB_DWIDTH : integer := 32; -- Slave PLB generics C_SPLB_NUM_MASTERS : integer := 8; C_SPLB_MID_WIDTH : integer := 1; C_SPLB_AWIDTH : integer := 32; C_SPLB_DWIDTH : integer := 32; C_SPLB_NATIVE_DWIDTH : integer := 32; -- AXI4-Lite Slave generics C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_DATA_WIDTH : integer := 32; -- Output format C_PIXEL_DATA_WIDTH : integer := 24; -- Output data width: 12, 15, 16, 18 or 24 C_USE_VCLK2 : integer := 1; -- pix_clk rising edge will be in the middle of the DDR RGB data eye or synchronous if not used C_ROW_STRIDE : integer := 1024; -- Row stride in number of pixels C_XCOLOR : integer := 0; C_USE_SIZE_POSITION : integer := 0; -- Use layer size, position and offset functionality: 0 - no, 1 - yes C_DISPLAY_INTERFACE : integer := 0; -- Select output interface type: 0 - parallel only, 1 - ITU656, 2 - LVDS 4bit, 3 - camera link, 4 - LVDS 3bit, 5 - DVI C_DISPLAY_COLOR_SPACE : integer := 0; -- Select output interface color space: 0 - RGB, 1 - YCbCr 4:2:2, 2 - YCbCr 4:4:4 C_LVDS_DATA_WIDTH : integer := 4; -- 3 or 4 C_VCLK_PERIOD : integer := 25000; -- vclk clock period in ps -- Multilayer generics C_NUM_OF_LAYERS : positive := 3; -- Number of logiCVC layers: 1, 2, 3, 4 or 5 C_LAYER_0_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr C_LAYER_1_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr, 2 - Alpha C_LAYER_2_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr C_LAYER_3_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr, 2 - Alpha C_LAYER_4_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr C_LAYER_0_DATA_WIDTH : positive := 16; -- Layer 0 data width: 8, 16, 24 bit C_LAYER_1_DATA_WIDTH : positive := 16; -- Layer 1 data width: 8, 16, 24 bit C_LAYER_2_DATA_WIDTH : positive := 16; -- Layer 2 data width: 8, 16, 24 bit C_LAYER_3_DATA_WIDTH : positive := 16; -- Layer 3 data width: 8, 16, 24 bit C_LAYER_4_DATA_WIDTH : positive := 16; -- Layer 4 data width: 8, 16, 24 bit C_LAYER_0_ALPHA_MODE : integer := 0; -- Layer 0 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24 C_LAYER_1_ALPHA_MODE : integer := 0; -- Layer 1 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24 C_LAYER_2_ALPHA_MODE : integer := 0; -- Layer 2 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24 C_LAYER_3_ALPHA_MODE : integer := 0; -- Layer 3 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24 C_LAYER_4_ALPHA_MODE : integer := 0; -- Layer 4 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24 C_USE_BACKGROUND : integer := 0; -- configure last layer as background: 0 - no, 1 - yes C_USE_XTREME_DSP : integer := 2; -- enable or disable use of DSP resources: 0 - no, 1 - yes, 2 - auto C_USE_MULTIPLIER : integer := 2; -- control way in which multipliers in blender are implemented: 0 - lut, 1 - block, 2 - auto C_LAYER_0_OFFSET : natural := 0; -- address offset for layer 0 in 2k steps for 16bpp and 1k steps for 8bpp C_LAYER_1_OFFSET : natural := 2048; -- address offset for layer 1 in 2k steps for 16bpp and 1k steps for 8bpp C_LAYER_2_OFFSET : natural := 4096; -- address offset for layer 2 in 2k steps for 16bpp and 1k steps for 8bpp C_LAYER_3_OFFSET : natural := 6144; -- address offset for layer 3 in 2k steps for 16bpp and 1k steps for 8bpp C_LAYER_4_OFFSET : natural := 8192; -- address offset for layer 4 in 2k steps for 16bpp and 1k steps for 8bpp C_BUFFER_0_OFFSET : natural := 1024; -- address offset for layer 0 double buffer relative to LAYER_0_OFFSET C_BUFFER_1_OFFSET : natural := 1024; -- address offset for layer 1 double buffer relative to LAYER_1_OFFSET C_BUFFER_2_OFFSET : natural := 1024; -- address offset for layer 2 double buffer relative to LAYER_2_OFFSET C_BUFFER_3_OFFSET : natural := 1024; -- address offset for layer 3 double buffer relative to LAYER_3_OFFSET C_BUFFER_4_OFFSET : natural := 1024; -- address offset for layer 4 double buffer relative to LAYER_4_OFFSET -- Extern parallel input generics C_USE_E_PARALLEL_INPUT : integer := 0; -- Syncronize logiCVC to external parallel input and use data as one layer: 0 - no, 1 - yes C_USE_E_VCLK_BUFGMUX : integer := 1; -- Use BUFGMUX for switching video clock to e_vclk, else use vclk C_E_LAYER : integer := 0; -- External parallel input layer: 0, 1, 2, 3, 4 C_E_DATA_WIDTH : integer := 24 -- External parallel input data width: 8, 16, 24 bit ); port( rst : in std_logic; -- Global reset mclk : in std_logic; -- Memory clock vclk : in std_logic; -- Video clock vclk2 : in std_logic; -- Video clock x2 itu_clk_in : in std_logic; -- It has to be 27 MHz and synchronous to vclk lvds_clk : in std_logic; -- lvds clock is 3.5x video clock lvds_clkn : in std_logic; -- Inverted lvds_clk -- Xylon Memory Bus (XMB) mem_req : out std_logic; mem_wr : out std_logic; mem_ack : in std_logic := '0'; mem_addr : out std_logic_vector(31 downto 0); mem_data : out std_logic_vector(C_XMB_DATA_BUS_WIDTH - 1 downto 0); mem_data_be : out std_logic_vector(C_XMB_DATA_BUS_WIDTH / 8 - 1 downto 0); mem_wrack : in std_logic := '0'; mem_burst : out std_logic_vector(C_MEM_BURST - 1 downto 0); mem_data_valid : in std_logic := '0'; mem_data_in : in std_logic_vector(C_XMB_DATA_BUS_WIDTH - 1 downto 0) := (others => '0'); -- PLB -------------- -- Master mplb_rst : in std_logic; plb_maddrack : in std_logic; plb_mrearbitrate : in std_logic; plb_mssize : in std_logic_vector(0 to 1); plb_mbusy : in std_logic; plb_mrderr : in std_logic; plb_mwrerr : in std_logic; plb_mtimeout : in std_logic; plb_mirq : in std_logic; m_request : out std_logic; m_priority : out std_logic_vector(0 to 1); m_buslock : out std_logic; m_rnw : out std_logic; m_be : out std_logic_vector(0 to (C_MPLB_DWIDTH / 8) - 1); m_size : out std_logic_vector(0 to 3); m_type : out std_logic_vector(0 to 2); m_msize : out std_logic_vector(0 to 1); m_tattribute : out std_logic_vector(0 to 15); m_lockerr : out std_logic; m_abort : out std_logic; m_abus : out std_logic_vector(0 to (C_MPLB_AWIDTH - 1)); m_uabus : out std_logic_vector(0 to (C_MPLB_AWIDTH - 1)); plb_mwrdack : in std_logic; plb_mwrbterm : in std_logic; m_wrburst : out std_logic; m_wrdbus : out std_logic_vector(0 to (C_MPLB_DWIDTH - 1)); plb_mrddack : in std_logic; plb_mrdbterm : in std_logic; plb_mrdwdaddr : in std_logic_vector(0 to 3); plb_mrddbus : in std_logic_vector(0 to (C_MPLB_DWIDTH - 1)); m_rdburst : out std_logic; -- AXI -------------- -- Master M_AXI_ARESETN : in std_logic; M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0); M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0); M_AXI_AWLEN : out std_logic_vector(7 downto 0); M_AXI_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_AWBURST : out std_logic_vector(1 downto 0); M_AXI_AWLOCK : out std_logic_vector(1 downto 0); M_AXI_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_AWPROT : out std_logic_vector(2 downto 0); M_AXI_AWQOS : out std_logic_vector(3 downto 0); M_AXI_AWVALID : out std_logic; M_AXI_AWREADY : in std_logic; M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH - 1 downto 0); M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH / 8 - 1 downto 0); M_AXI_WLAST : out std_logic; M_AXI_WVALID : out std_logic; M_AXI_WREADY : in std_logic; M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0); M_AXI_BRESP : in std_logic_vector(1 downto 0); M_AXI_BVALID : in std_logic; M_AXI_BREADY : out std_logic; M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0); M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0); M_AXI_ARLEN : out std_logic_vector(7 downto 0); M_AXI_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_ARBURST : out std_logic_vector(1 downto 0); M_AXI_ARLOCK : out std_logic_vector(1 downto 0); M_AXI_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_ARPROT : out std_logic_vector(2 downto 0); M_AXI_ARQOS : out std_logic_vector(3 downto 0); M_AXI_ARVALID : out std_logic; M_AXI_ARREADY : in std_logic; M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0); M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH - 1 downto 0); M_AXI_RRESP : in std_logic_vector(1 downto 0); M_AXI_RLAST : in std_logic; M_AXI_RVALID : in std_logic; M_AXI_RREADY : out std_logic; ---------------------- -- OPB -------------- -- Slave OPB_Clk : in std_logic; OPB_Rst : in std_logic; OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH - 1); OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH / 8 - 1); OPB_RNW : in std_logic; OPB_select : in std_logic; OPB_seqAddr : in std_logic; OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH - 1); Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH - 1); Sl_errAck : out std_logic; Sl_retry : out std_logic; Sl_toutSup : out std_logic; Sl_xferAck : out std_logic; ---------------------- -- PLB -------------- -- Slave SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH - 1); PLB_UABus : in std_logic_vector(0 to C_SPLB_AWIDTH - 1); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH - 1); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH / 8 - 1); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_tattribute : in std_logic_vector(0 to 15); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH - 1); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH - 1); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1); Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1); Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1); Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1); ---------------------- -- AXI4-Lite -------- -- Slave S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH / 8) - 1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; ---------------------- -- Video Outputs -------------- pix_clk_i : in std_logic; -- Pixel clock pix_clk_o : out std_logic; -- Pixel clock pix_clk_t : out std_logic; -- Pixel clock pix_clk_n_i : in std_logic; -- Pixel clock inverted pix_clk_n_o : out std_logic; -- Pixel clock inverted pix_clk_n_t : out std_logic; -- Pixel clock inverted d_pix_i : in std_logic_vector(C_PIXEL_DATA_WIDTH - 1 downto 0); -- Pixel data bus d_pix_o : out std_logic_vector(C_PIXEL_DATA_WIDTH - 1 downto 0); -- Pixel data bus d_pix_t : out std_logic; -- Pixel data bus hsync_i : in std_logic; -- Hsync hsync_o : out std_logic; -- Hsync hsync_t : out std_logic; -- Hsync vsync_i : in std_logic; -- Vsync vsync_o : out std_logic; -- Vsync vsync_t : out std_logic; -- Vsync blank_i : in std_logic; -- Blank blank_o : out std_logic; -- Blank blank_t : out std_logic; -- Blank itu656_clk_o : out std_logic; -- ITU656 clock output itu656_data_o : out std_logic_vector(7 downto 0); -- ITU656 data output lvds_data_out_p : out std_logic_vector(C_LVDS_DATA_WIDTH - 1 downto 0); -- lvds data, positive lvds_data_out_n : out std_logic_vector(C_LVDS_DATA_WIDTH - 1 downto 0); -- lvds data, negative lvds_clk_out_p : out std_logic; -- lvds clk, positive lvds_clk_out_n : out std_logic; -- lvds clk, negative pllvclk_locked : in std_logic; -- PLL_BASE LOCKED (spartan6, LVDS clk gen) dvi_clk_p : out std_logic; -- DVI clock, positive dvi_clk_n : out std_logic; -- DVI clock, negative dvi_data_p : out std_logic_vector(2 downto 0); -- DVI data, positive dvi_data_n : out std_logic_vector(2 downto 0); -- DVI data, negative ---------------------- -- External parallel input -------------- e_vclk : in std_logic; -- External video clock e_vsync : in std_logic; -- External vsync e_hsync : in std_logic; -- External hsync e_blank : in std_logic; -- External blank e_data : in std_logic_vector(C_E_DATA_WIDTH - 1 downto 0); -- External data e_video_present : in std_logic; -- External video present flag ---------------------- -- Other -------------- e_curr_vbuff : in std_logic_vector(C_NUM_OF_LAYERS * 2 - 1 downto 0); -- Current external stream vbuffer e_next_vbuff : out std_logic_vector(C_NUM_OF_LAYERS * 2 - 1 downto 0); -- Next external stream vbuffer to write to e_sw_vbuff : in std_logic_vector(C_NUM_OF_LAYERS - 1 downto 0); -- Switch video buffers from external source e_sw_grant : out std_logic_vector(C_NUM_OF_LAYERS - 1 downto 0); -- Video buffers switch req granted vcdivsel : out std_logic_vector(1 downto 0); -- vclk div select bits vclksel : out std_logic_vector(2 downto 0); -- vclk select bits en_vdd : out std_logic; -- vdd enable en_blight : out std_logic; -- backlight enable v_en : out std_logic; -- Enable display control/data signals en_vee : out std_logic; -- vee enable interrupt : out std_logic -- logiCVC interrupt signal, level sensitive, high active ); end component; end logicbricks;	gpl-3.0
mistryalok/Zedboard	learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_bram_ctrl_1_0/sim/design_1_axi_bram_ctrl_1_0.vhd	1	15629	-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_bram_ctrl_v4_0; USE axi_bram_ctrl_v4_0.axi_bram_ctrl; ENTITY design_1_axi_bram_ctrl_1_0 IS PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC; s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC; s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; bram_rst_a : OUT STD_LOGIC; bram_clk_a : OUT STD_LOGIC; bram_en_a : OUT STD_LOGIC; bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ); END design_1_axi_bram_ctrl_1_0; ARCHITECTURE design_1_axi_bram_ctrl_1_0_arch OF design_1_axi_bram_ctrl_1_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_1_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_bram_ctrl IS GENERIC ( C_BRAM_INST_MODE : STRING; C_MEMORY_DEPTH : INTEGER; C_BRAM_ADDR_WIDTH : INTEGER; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER; C_S_AXI_ID_WIDTH : INTEGER; C_S_AXI_PROTOCOL : STRING; C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER; C_SINGLE_PORT_BRAM : INTEGER; C_FAMILY : STRING; C_S_AXI_CTRL_ADDR_WIDTH : INTEGER; C_S_AXI_CTRL_DATA_WIDTH : INTEGER; C_ECC : INTEGER; C_ECC_TYPE : INTEGER; C_FAULT_INJECT : INTEGER; C_ECC_ONOFF_RESET_VALUE : INTEGER ); PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; ecc_interrupt : OUT STD_LOGIC; ecc_ue : OUT STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC; s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC; s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_ctrl_awvalid : IN STD_LOGIC; s_axi_ctrl_awready : OUT STD_LOGIC; s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_wvalid : IN STD_LOGIC; s_axi_ctrl_wready : OUT STD_LOGIC; s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_ctrl_bvalid : OUT STD_LOGIC; s_axi_ctrl_bready : IN STD_LOGIC; s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_arvalid : IN STD_LOGIC; s_axi_ctrl_arready : OUT STD_LOGIC; s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_ctrl_rvalid : OUT STD_LOGIC; s_axi_ctrl_rready : IN STD_LOGIC; bram_rst_a : OUT STD_LOGIC; bram_clk_a : OUT STD_LOGIC; bram_en_a : OUT STD_LOGIC; bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rst_b : OUT STD_LOGIC; bram_clk_b : OUT STD_LOGIC; bram_en_b : OUT STD_LOGIC; bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT axi_bram_ctrl; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST"; ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; BEGIN U0 : axi_bram_ctrl GENERIC MAP ( C_BRAM_INST_MODE => "EXTERNAL", C_MEMORY_DEPTH => 2048, C_BRAM_ADDR_WIDTH => 11, C_S_AXI_ADDR_WIDTH => 13, C_S_AXI_DATA_WIDTH => 32, C_S_AXI_ID_WIDTH => 12, C_S_AXI_PROTOCOL => "AXI4", C_S_AXI_SUPPORTS_NARROW_BURST => 0, C_SINGLE_PORT_BRAM => 1, C_FAMILY => "zynq", C_S_AXI_CTRL_ADDR_WIDTH => 32, C_S_AXI_CTRL_DATA_WIDTH => 32, C_ECC => 0, C_ECC_TYPE => 0, C_FAULT_INJECT => 0, C_ECC_ONOFF_RESET_VALUE => 0 ) PORT MAP ( s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awid => s_axi_awid, s_axi_awaddr => s_axi_awaddr, s_axi_awlen => s_axi_awlen, s_axi_awsize => s_axi_awsize, s_axi_awburst => s_axi_awburst, s_axi_awlock => s_axi_awlock, s_axi_awcache => s_axi_awcache, s_axi_awprot => s_axi_awprot, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wstrb => s_axi_wstrb, s_axi_wlast => s_axi_wlast, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bid => s_axi_bid, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_arid => s_axi_arid, s_axi_araddr => s_axi_araddr, s_axi_arlen => s_axi_arlen, s_axi_arsize => s_axi_arsize, s_axi_arburst => s_axi_arburst, s_axi_arlock => s_axi_arlock, s_axi_arcache => s_axi_arcache, s_axi_arprot => s_axi_arprot, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rid => s_axi_rid, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rlast => s_axi_rlast, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, s_axi_ctrl_awvalid => '0', s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_wvalid => '0', s_axi_ctrl_bready => '0', s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_arvalid => '0', s_axi_ctrl_rready => '0', bram_rst_a => bram_rst_a, bram_clk_a => bram_clk_a, bram_en_a => bram_en_a, bram_we_a => bram_we_a, bram_addr_a => bram_addr_a, bram_wrdata_a => bram_wrdata_a, bram_rddata_a => bram_rddata_a, bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)) ); END design_1_axi_bram_ctrl_1_0_arch;	gpl-3.0
freecores/usb_fpga_1_11	examples/usb-fpga-1.2/intraffic/fpga/intraffic.vhd	42	1939	library ieee; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity intraffic is port( RESET : in std_logic; CONT : in std_logic; IFCLK : in std_logic; FD : out std_logic_vector(15 downto 0); SLOE : out std_logic; SLRD : out std_logic; SLWR : out std_logic; FIFOADR0 : out std_logic; FIFOADR1 : out std_logic; PKTEND : out std_logic; FLAGB : in std_logic ); end intraffic; architecture RTL of intraffic is ---------------------------- -- test pattern generator -- ---------------------------- -- 30 bit counter signal GEN_CNT : std_logic_vector(29 downto 0); signal INT_CNT : std_logic_vector(6 downto 0); signal FIFO_WORD : std_logic; begin SLOE <= '1'; SLRD <= '1'; FIFOADR0 <= '0'; FIFOADR1 <= '0'; PKTEND <= '1'; -- no data alignment dpIFCLK: process (IFCLK, RESET) begin -- reset if RESET = '1' then GEN_CNT <= ( others => '0' ); INT_CNT <= ( others => '0' ); FIFO_WORD <= '0'; SLWR <= '1'; -- IFCLK elsif IFCLK'event and IFCLK = '1' then if CONT = '1' or FLAGB = '1' then if FIFO_WORD = '0' then FD(14 downto 0) <= GEN_CNT(14 downto 0); else FD(14 downto 0) <= GEN_CNT(29 downto 15); end if; FD(15) <= FIFO_WORD; if FIFO_WORD = '1' then GEN_CNT <= GEN_CNT + '1'; if INT_CNT = conv_std_logic_vector(99,7) then INT_CNT <= ( others => '0' ); else INT_CNT <= INT_CNT + '1'; end if; end if; FIFO_WORD <= not FIFO_WORD; end if; if ( INT_CNT >= conv_std_logic_vector(90,7) ) and ( CONT = '0' ) then SLWR <= '1'; else SLWR <= '0'; end if; end if; end process dpIFCLK; end RTL;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_s2mm_mngr.vhd	3	50534	-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_mngr.vhd -- Description: This entity is the top level entity for the AXI DMA S2MM -- manager. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_s2mm_mngr is generic( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1; -- Depth of DataMover command FIFO C_DM_STATUS_WIDTH : integer range 8 to 32 := 8; -- Width of DataMover status word -- 8 for Determinate BTT Mode -- 32 for Indterminate BTT Mode ----------------------------------------------------------------------- -- Scatter Gather Parameters ----------------------------------------------------------------------- C_INCLUDE_SG : integer range 0 to 1 := 1; -- Include or Exclude the Scatter Gather Engine -- 0 = Exclude SG Engine - Enables Simple DMA Mode -- 1 = Include SG Engine - Enables Scatter Gather Mode C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1; -- Include or Exclude AXI Status and AXI Control Streams -- 0 = Exclude Status and Control Streams -- 1 = Include Status and Control Streams C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0; -- Include or Exclude Scatter Gather Descriptor Queuing -- 0 = Exclude SG Descriptor Queuing -- 1 = Include SG Descriptor Queuing C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Descriptor Buffer Length, Transferred Bytes, and Status Stream -- Rx Length Width. Indicates the least significant valid bits of -- descriptor buffer length, transferred bytes, or Rx Length value -- in the status word coincident with tlast. C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32; -- AXI Master Stream in for descriptor fetch C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33; -- 1 IOC bit + 32 Update Status Bits C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32; -- Slave AXI Status Stream Data Width ----------------------------------------------------------------------- -- Stream to Memory Map (S2MM) Parameters ----------------------------------------------------------------------- C_INCLUDE_S2MM : integer range 0 to 1 := 1; -- Include or exclude S2MM primary data path -- 0 = Exclude S2MM primary data path -- 1 = Include S2MM primary data path C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for S2MM Write Port C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1; C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_MICRO_DMA : integer range 0 to 1 := 0; C_FAMILY : string := "virtex5" -- Target FPGA Device Family ); port ( -- Secondary Clock and Reset m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Primary Clock and Reset -- axi_prmry_aclk : in std_logic ; -- p_reset_n : in std_logic ; -- -- soft_reset : in std_logic ; -- -- MM2S Control and Status -- s2mm_run_stop : in std_logic ; -- s2mm_keyhole : in std_logic ; s2mm_halted : in std_logic ; -- s2mm_ftch_idle : in std_logic ; -- s2mm_updt_idle : in std_logic ; -- s2mm_tailpntr_enble : in std_logic ; -- s2mm_ftch_err_early : in std_logic ; -- s2mm_ftch_stale_desc : in std_logic ; -- s2mm_halt : in std_logic ; -- s2mm_halt_cmplt : in std_logic ; -- s2mm_packet_eof_out : out std_logic ; s2mm_halted_clr : out std_logic ; -- s2mm_halted_set : out std_logic ; -- s2mm_idle_set : out std_logic ; -- s2mm_idle_clr : out std_logic ; -- s2mm_new_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- s2mm_new_curdesc_wren : out std_logic ; -- s2mm_stop : out std_logic ; -- s2mm_desc_flush : out std_logic ; -- s2mm_all_idle : out std_logic ; -- s2mm_error : out std_logic ; -- mm2s_error : in std_logic ; -- s2mm_desc_info_in : in std_logic_vector (13 downto 0) ; -- Simple DMA Mode Signals s2mm_da : in std_logic_vector -- (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- s2mm_length : in std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- s2mm_length_wren : in std_logic ; -- s2mm_smple_done : out std_logic ; -- s2mm_interr_set : out std_logic ; -- s2mm_slverr_set : out std_logic ; -- s2mm_decerr_set : out std_logic ; -- s2mm_bytes_rcvd : out std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- s2mm_bytes_rcvd_wren : out std_logic ; -- -- -- SG S2MM Descriptor Fetch AXI Stream In -- m_axis_s2mm_ftch_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); -- m_axis_s2mm_ftch_tvalid : in std_logic ; -- m_axis_s2mm_ftch_tready : out std_logic ; -- m_axis_s2mm_ftch_tlast : in std_logic ; -- m_axis_s2mm_ftch_tdata_new : in std_logic_vector -- (96 downto 0); -- m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector -- (63 downto 0); -- m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector -- (31 downto 0); -- m_axis_s2mm_ftch_tvalid_new : in std_logic ; -- m_axis_ftch2_desc_available : in std_logic; -- -- -- SG S2MM Descriptor Update AXI Stream Out -- s_axis_s2mm_updtptr_tdata : out std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis_s2mm_updtptr_tvalid : out std_logic ; -- s_axis_s2mm_updtptr_tready : in std_logic ; -- s_axis_s2mm_updtptr_tlast : out std_logic ; -- -- s_axis_s2mm_updtsts_tdata : out std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; -- s_axis_s2mm_updtsts_tvalid : out std_logic ; -- s_axis_s2mm_updtsts_tready : in std_logic ; -- s_axis_s2mm_updtsts_tlast : out std_logic ; -- -- -- User Command Interface Ports (AXI Stream) -- s_axis_s2mm_cmd_tvalid : out std_logic ; -- s_axis_s2mm_cmd_tready : in std_logic ; -- s_axis_s2mm_cmd_tdata : out std_logic_vector -- ((2C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0); -- -- -- User Status Interface Ports (AXI Stream) -- m_axis_s2mm_sts_tvalid : in std_logic ; -- m_axis_s2mm_sts_tready : out std_logic ; -- m_axis_s2mm_sts_tdata : in std_logic_vector -- (C_DM_STATUS_WIDTH - 1 downto 0) ; -- m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8-1) downto 0); -- s2mm_err : in std_logic ; -- updt_error : in std_logic ; -- ftch_error : in std_logic ; -- -- -- Stream to Memory Map Status Stream Interface -- s_axis_s2mm_sts_tdata : in std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- s_axis_s2mm_sts_tkeep : in std_logic_vector -- ((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); -- s_axis_s2mm_sts_tvalid : in std_logic ; -- s_axis_s2mm_sts_tready : out std_logic ; -- s_axis_s2mm_sts_tlast : in std_logic -- ); end axi_dma_s2mm_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; attribute mark_debug : string; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Primary DataMover Command signals signal s2mm_cmnd_wr : std_logic := '0'; signal s2mm_cmnd_data : std_logic_vector ((2C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0'); signal s2mm_cmnd_pending : std_logic := '0'; attribute mark_debug of s2mm_cmnd_wr : signal is "true"; attribute mark_debug of s2mm_cmnd_data : signal is "true"; -- Primary DataMover Status signals signal s2mm_done : std_logic := '0'; signal s2mm_stop_i : std_logic := '0'; signal s2mm_interr : std_logic := '0'; signal s2mm_slverr : std_logic := '0'; signal s2mm_decerr : std_logic := '0'; attribute mark_debug of s2mm_interr : signal is "true"; attribute mark_debug of s2mm_slverr : signal is "true"; attribute mark_debug of s2mm_decerr : signal is "true"; signal s2mm_tag : std_logic_vector(3 downto 0) := (others => '0'); signal s2mm_brcvd : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal dma_s2mm_error : std_logic := '0'; signal soft_reset_d1 : std_logic := '0'; signal soft_reset_d2 : std_logic := '0'; signal soft_reset_re : std_logic := '0'; signal s2mm_error_i : std_logic := '0'; signal sts_strm_stop : std_logic := '0'; signal s2mm_halted_set_i : std_logic := '0'; signal s2mm_sts_received_clr : std_logic := '0'; signal s2mm_sts_received : std_logic := '0'; signal s2mm_cmnd_idle : std_logic := '0'; signal s2mm_sts_idle : std_logic := '0'; signal s2mm_eof_set : std_logic := '0'; signal s2mm_packet_eof : std_logic := '0'; -- Scatter Gather Interface signals signal desc_fetch_req : std_logic := '0'; signal desc_fetch_done : std_logic := '0'; signal desc_update_req : std_logic := '0'; signal desc_update_done : std_logic := '0'; signal desc_available : std_logic := '0'; signal s2mm_desc_baddress : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_info : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_cmplt : std_logic := '0'; signal s2mm_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); -- S2MM Status Stream Signals signal s2mm_rxlength_valid : std_logic := '0'; signal s2mm_rxlength_clr : std_logic := '0'; signal s2mm_rxlength : std_logic_vector(C_SG_LENGTH_WIDTH - 1 downto 0) := (others => '0'); signal stsstrm_fifo_rden : std_logic := '0'; signal stsstrm_fifo_empty : std_logic := '0'; signal stsstrm_fifo_dout : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0'); signal s2mm_desc_flush_i : std_logic := '0'; signal updt_pending : std_logic := '0'; signal s2mm_cmnd_wr_1 : std_logic := '0'; signal s2mm_eof_micro, s2mm_sof_micro : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Include S2MM (Received) Channel ------------------------------------------------------------------------------- GEN_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 1 generate begin -- pass out to register module s2mm_halted_set <= s2mm_halted_set_i; ------------------------------------------------------------------------------- -- Graceful shut down logic ------------------------------------------------------------------------------- -- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error -- or SG Fetch error, or Stale Descriptor Error s2mm_error_i <= dma_s2mm_error -- Primary data mover reports error or updt_error -- SG Update engine reports error or ftch_error -- SG Fetch engine reports error or s2mm_ftch_err_early -- SG Fetch engine reports early error on S2MM or s2mm_ftch_stale_desc; -- SG Fetch stale descriptor error -- pass out to shut down mm2s s2mm_error <= s2mm_error_i; -- Clear run/stop and stop state machines due to errors or soft reset -- Error based on datamover error report or sg update error or sg fetch error -- SG update error and fetch error included because need to shut down, no way -- to update descriptors on sg update error and on fetch error descriptor -- data is corrupt therefor do not want to issue the xfer command to primary datamover --CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore -- need to stop all processes regardless of the source of the error. -- s2mm_stop_i <= s2mm_error -- Error -- or soft_reset; -- Soft Reset issued s2mm_stop_i <= s2mm_error_i -- Error on s2mm or mm2s_error -- Error on mm2s or soft_reset; -- Soft Reset issued -- Register signals out REG_OUT : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_stop <= '0'; s2mm_desc_flush_i <= '0'; else s2mm_stop <= s2mm_stop_i; -- Flush any fetch descriptors if error or if run stop cleared s2mm_desc_flush_i <= s2mm_stop_i or not s2mm_run_stop; end if; end if; end process REG_OUT; -- Generate DMA Controller For Scatter Gather Mode GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate begin -- Not used in Scatter Gather mode s2mm_smple_done <= '0'; s2mm_interr_set <= '0'; s2mm_slverr_set <= '0'; s2mm_decerr_set <= '0'; s2mm_bytes_rcvd <= (others => '0'); s2mm_bytes_rcvd_wren <= '0'; -- Flush descriptors s2mm_desc_flush <= s2mm_desc_flush_i; OLD_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate begin s2mm_cmnd_wr <= s2mm_cmnd_wr_1; end generate OLD_CMD_WR; NEW_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate begin s2mm_cmnd_wr <= m_axis_s2mm_ftch_tvalid_new; end generate NEW_CMD_WR; --------------------------------------------------------------------------- -- S2MM Primary DMA Controller State Machine --------------------------------------------------------------------------- I_S2MM_SM : entity axi_dma_v7_1.axi_dma_s2mm_sm generic map( C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH , C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE , C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM , C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH , C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL , C_MICRO_DMA => C_MICRO_DMA , C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , s2mm_stop => s2mm_stop_i , -- Channel 1 Control and Status s2mm_run_stop => s2mm_run_stop , s2mm_keyhole => s2mm_keyhole , s2mm_ftch_idle => s2mm_ftch_idle , s2mm_desc_flush => s2mm_desc_flush_i , s2mm_cmnd_idle => s2mm_cmnd_idle , s2mm_sts_idle => s2mm_sts_idle , s2mm_eof_set => s2mm_eof_set , s2mm_eof_micro => s2mm_eof_micro, s2mm_sof_micro => s2mm_sof_micro, -- S2MM Status Stream RX Length s2mm_rxlength_valid => s2mm_rxlength_valid , s2mm_rxlength_clr => s2mm_rxlength_clr , s2mm_rxlength => s2mm_rxlength , -- S2MM Descriptor Fetch Request (from s2mm_sm) desc_fetch_req => desc_fetch_req , desc_fetch_done => desc_fetch_done , desc_update_done => desc_update_done , updt_pending => updt_pending , desc_available => desc_available , -- DataMover Command s2mm_cmnd_wr => s2mm_cmnd_wr_1 , s2mm_cmnd_data => s2mm_cmnd_data , s2mm_cmnd_pending => s2mm_cmnd_pending , -- Descriptor Fields s2mm_desc_baddress => s2mm_desc_baddress , s2mm_desc_info => s2mm_desc_info , s2mm_desc_blength => s2mm_desc_blength, s2mm_desc_blength_v => s2mm_desc_blength_v, s2mm_desc_blength_s => s2mm_desc_blength_s ); --------------------------------------------------------------------------- -- S2MM Scatter Gather State Machine --------------------------------------------------------------------------- I_S2MM_SG_IF : entity axi_dma_v7_1.axi_dma_s2mm_sg_if generic map( ------------------------------------------------------------------- -- Scatter Gather Parameters ------------------------------------------------------------------- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM , C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE , C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH , C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH , C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH , C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH , C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH , C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS , C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL , C_MICRO_DMA => C_MICRO_DMA , C_FAMILY => C_FAMILY ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , s2mm_desc_info_in => s2mm_desc_info_in , -- SG S2MM Descriptor Fetch AXI Stream In m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata , m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid , m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready , m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast , m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new , m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new , m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt , m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new , m_axis_ftch2_desc_available => m_axis_ftch2_desc_available , -- SG S2MM Descriptor Update AXI Stream Out s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata , s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid , s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready , s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast , s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata , s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid , s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready , s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast , -- S2MM Descriptor Fetch Request (from s2mm_sm) desc_available => desc_available , desc_fetch_req => desc_fetch_req , desc_fetch_done => desc_fetch_done , updt_pending => updt_pending , -- S2MM Status Stream Interface stsstrm_fifo_rden => stsstrm_fifo_rden , stsstrm_fifo_empty => stsstrm_fifo_empty , stsstrm_fifo_dout => stsstrm_fifo_dout , -- Update command write interface from s2mm sm s2mm_cmnd_wr => s2mm_cmnd_wr , s2mm_cmnd_data => s2mm_cmnd_data ( ((1+C_ENABLE_MULTI_CHANNEL)* C_M_AXI_S2MM_ADDR_WIDTH+ CMD_BASE_WIDTH)-1 downto 0) , -- S2MM Descriptor Update Request (from s2mm_sm) desc_update_done => desc_update_done , s2mm_sts_received_clr => s2mm_sts_received_clr , s2mm_sts_received => s2mm_sts_received , s2mm_desc_cmplt => s2mm_desc_cmplt , s2mm_done => s2mm_done , s2mm_interr => s2mm_interr , s2mm_slverr => s2mm_slverr , s2mm_decerr => s2mm_decerr , s2mm_tag => s2mm_tag , s2mm_brcvd => s2mm_brcvd , s2mm_eof_set => s2mm_eof_set , s2mm_packet_eof => s2mm_packet_eof , s2mm_halt => s2mm_halt , s2mm_eof_micro => s2mm_eof_micro, s2mm_sof_micro => s2mm_sof_micro, -- S2MM Descriptor Field Output s2mm_new_curdesc => s2mm_new_curdesc , s2mm_new_curdesc_wren => s2mm_new_curdesc_wren , s2mm_desc_baddress => s2mm_desc_baddress , s2mm_desc_blength => s2mm_desc_blength , s2mm_desc_blength_v => s2mm_desc_blength_v , s2mm_desc_blength_s => s2mm_desc_blength_s , s2mm_desc_info => s2mm_desc_info , s2mm_desc_app0 => s2mm_desc_app0 , s2mm_desc_app1 => s2mm_desc_app1 , s2mm_desc_app2 => s2mm_desc_app2 , s2mm_desc_app3 => s2mm_desc_app3 , s2mm_desc_app4 => s2mm_desc_app4 ); end generate GEN_SCATTER_GATHER_MODE; s2mm_packet_eof_out <= s2mm_packet_eof; -- Generate DMA Controller for Simple DMA Mode GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate begin -- Scatter Gather signals not used in Simple DMA Mode s2mm_desc_flush <= '0'; m_axis_s2mm_ftch_tready <= '0'; s_axis_s2mm_updtptr_tdata <= (others => '0'); s_axis_s2mm_updtptr_tvalid <= '0'; s_axis_s2mm_updtptr_tlast <= '0'; s_axis_s2mm_updtsts_tdata <= (others => '0'); s_axis_s2mm_updtsts_tvalid <= '0'; s_axis_s2mm_updtsts_tlast <= '0'; desc_fetch_req <= '0'; desc_available <= '0'; desc_fetch_done <= '0'; desc_update_done <= '0'; s2mm_rxlength_clr <= '0'; stsstrm_fifo_rden <= '0'; s2mm_new_curdesc <= (others => '0'); s2mm_new_curdesc_wren <= '0'; s2mm_desc_baddress <= (others => '0'); s2mm_desc_info <= (others => '0'); s2mm_desc_blength <= (others => '0'); s2mm_desc_blength_v <= (others => '0'); s2mm_desc_blength_s <= (others => '0'); s2mm_desc_cmplt <= '0'; s2mm_desc_app0 <= (others => '0'); s2mm_desc_app1 <= (others => '0'); s2mm_desc_app2 <= (others => '0'); s2mm_desc_app3 <= (others => '0'); s2mm_desc_app4 <= (others => '0'); -- Simple DMA State Machine I_S2MM_SMPL_SM : entity axi_dma_v7_1.axi_dma_smple_sm generic map( C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_MICRO_DMA => C_MICRO_DMA , C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Channel 1 Control and Status run_stop => s2mm_run_stop , keyhole => s2mm_keyhole , stop => s2mm_stop_i , cmnd_idle => s2mm_cmnd_idle , sts_idle => s2mm_sts_idle , -- DataMover Status sts_received => s2mm_sts_received , sts_received_clr => s2mm_sts_received_clr , -- DataMover Command cmnd_wr => s2mm_cmnd_wr , cmnd_data => s2mm_cmnd_data , cmnd_pending => s2mm_cmnd_pending , -- Trasnfer Qualifiers xfer_length_wren => s2mm_length_wren , xfer_address => s2mm_da , xfer_length => s2mm_length ); -- Pass Done/Error Status out to DMASR s2mm_interr_set <= s2mm_interr; s2mm_slverr_set <= s2mm_slverr; s2mm_decerr_set <= s2mm_decerr; s2mm_bytes_rcvd <= s2mm_brcvd; s2mm_bytes_rcvd_wren <= s2mm_done; -- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR. -- Receive clear when not shutting down s2mm_smple_done <= s2mm_sts_received_clr when s2mm_stop_i = '0' -- Else halt set prior to halted being set else s2mm_halted_set_i when s2mm_halted = '0' else '0'; end generate GEN_SIMPLE_DMA_MODE; ------------------------------------------------------------------------------- -- S2MM DataMover Command / Status Interface ------------------------------------------------------------------------------- I_S2MM_CMDSTS : entity axi_dma_v7_1.axi_dma_s2mm_cmdsts_if generic map( C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_DM_STATUS_WIDTH => C_DM_STATUS_WIDTH , C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM , C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH , C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH , C_INCLUDE_SG => C_INCLUDE_SG , C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL , C_MICRO_DMA => C_MICRO_DMA , C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Update command write interface from s2mm sm s2mm_cmnd_wr => s2mm_cmnd_wr , s2mm_cmnd_data => s2mm_cmnd_data , s2mm_cmnd_pending => s2mm_cmnd_pending , s2mm_packet_eof => s2mm_packet_eof , -- EOF Detected s2mm_sts_received_clr => s2mm_sts_received_clr , s2mm_sts_received => s2mm_sts_received , s2mm_tailpntr_enble => s2mm_tailpntr_enble , s2mm_desc_cmplt => s2mm_desc_cmplt , -- User Command Interface Ports (AXI Stream) s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid , s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready , s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata , -- User Status Interface Ports (AXI Stream) m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid , m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready , m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata , m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep , -- S2MM Primary DataMover Status s2mm_brcvd => s2mm_brcvd , s2mm_err => s2mm_err , s2mm_done => s2mm_done , s2mm_error => dma_s2mm_error , s2mm_interr => s2mm_interr , s2mm_slverr => s2mm_slverr , s2mm_decerr => s2mm_decerr , s2mm_tag => s2mm_tag ); --------------------------------------------------------------------------- -- Halt / Idle Status Manager --------------------------------------------------------------------------- I_S2MM_STS_MNGR : entity axi_dma_v7_1.axi_dma_s2mm_sts_mngr generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- dma control and sg engine status signals s2mm_run_stop => s2mm_run_stop , s2mm_ftch_idle => s2mm_ftch_idle , s2mm_updt_idle => s2mm_updt_idle , s2mm_cmnd_idle => s2mm_cmnd_idle , s2mm_sts_idle => s2mm_sts_idle , -- stop and halt control/status s2mm_stop => s2mm_stop_i , s2mm_halt_cmplt => s2mm_halt_cmplt , -- system state and control s2mm_all_idle => s2mm_all_idle , s2mm_halted_clr => s2mm_halted_clr , s2mm_halted_set => s2mm_halted_set_i , s2mm_idle_set => s2mm_idle_set , s2mm_idle_clr => s2mm_idle_clr ); -- S2MM Status Stream Included GEN_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate begin -- Register soft reset to create rising edge pulse to use for shut down. -- soft_reset from DMACR does not clear until after all reset processes -- are done. This causes stop to assert too long causing issue with -- status stream skid buffer. REG_SFT_RST : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then soft_reset_d1 <= '0'; soft_reset_d2 <= '0'; else soft_reset_d1 <= soft_reset; soft_reset_d2 <= soft_reset_d1; end if; end if; end process REG_SFT_RST; -- Rising edge soft reset pulse soft_reset_re <= soft_reset_d1 and not soft_reset_d2; -- Status Stream module stop requires rising edge of soft reset to -- shut down due to DMACR.SoftReset does not deassert on internal hard reset -- It clears after therefore do not want to issue another stop to sts strm -- skid buffer. sts_strm_stop <= s2mm_error_i -- Error or soft_reset_re; -- Soft Reset issued I_S2MM_STS_STREAM : entity axi_dma_v7_1.axi_dma_s2mm_sts_strm generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH , C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH , C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH , C_FAMILY => C_FAMILY ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , axi_prmry_aclk => axi_prmry_aclk , p_reset_n => p_reset_n , s2mm_stop => sts_strm_stop , s2mm_rxlength_valid => s2mm_rxlength_valid , s2mm_rxlength_clr => s2mm_rxlength_clr , s2mm_rxlength => s2mm_rxlength , stsstrm_fifo_rden => stsstrm_fifo_rden , stsstrm_fifo_empty => stsstrm_fifo_empty , stsstrm_fifo_dout => stsstrm_fifo_dout , -- Stream to Memory Map Status Stream Interface , s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata , s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep , s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid , s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready , s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast ); end generate GEN_STS_STREAM; -- S2MM Status Stream Not Included GEN_NO_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate begin s2mm_rxlength_valid <= '0'; s2mm_rxlength <= (others => '0'); stsstrm_fifo_empty <= '1'; stsstrm_fifo_dout <= (others => '0'); s_axis_s2mm_sts_tready <= '0'; end generate GEN_NO_STS_STREAM; end generate GEN_S2MM_DMA_CONTROL; ------------------------------------------------------------------------------- -- Do Not Include S2MM Channel ------------------------------------------------------------------------------- GEN_NO_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 0 generate begin m_axis_s2mm_ftch_tready <= '0'; s_axis_s2mm_updtptr_tdata <= (others =>'0'); s_axis_s2mm_updtptr_tvalid <= '0'; s_axis_s2mm_updtptr_tlast <= '0'; s_axis_s2mm_updtsts_tdata <= (others =>'0'); s_axis_s2mm_updtsts_tvalid <= '0'; s_axis_s2mm_updtsts_tlast <= '0'; s2mm_new_curdesc <= (others =>'0'); s2mm_new_curdesc_wren <= '0'; s_axis_s2mm_cmd_tvalid <= '0'; s_axis_s2mm_cmd_tdata <= (others =>'0'); m_axis_s2mm_sts_tready <= '0'; s2mm_halted_clr <= '0'; s2mm_halted_set <= '0'; s2mm_idle_set <= '0'; s2mm_idle_clr <= '0'; s_axis_s2mm_sts_tready <= '0'; s2mm_stop <= '0'; s2mm_desc_flush <= '0'; s2mm_all_idle <= '1'; s2mm_error <= '0'; -- CR#570587 s2mm_packet_eof_out <= '0'; s2mm_smple_done <= '0'; s2mm_interr_set <= '0'; s2mm_slverr_set <= '0'; s2mm_decerr_set <= '0'; s2mm_bytes_rcvd <= (others => '0'); s2mm_bytes_rcvd_wren <= '0'; end generate GEN_NO_S2MM_DMA_CONTROL; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/full_axi.vhd	7	43438	------------------------------------------------------------------------------- -- full_axi.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: full_axi.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller when configured in a full AXI4 mode. -- The rd_chnl and wr_chnl modules are instantiated. -- The ECC AXI-Lite register module is instantiated, if enabled. -- When single port BRAM mode is selected, the arbitration logic -- is instantiated (and connected to each wr_chnl & rd_chnl). -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- \| -- \|-- full_axi.vhd -- \| -- sng_port_arb.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- wr_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- ecc_gen_hsiao.vhd -- \| -- \| -- rd_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- ecc_gen_hsiao.vhd -- \| -- \|-- axi_lite.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/15/2011 v1.03a -- ~~~~~~ -- Initial integration of Hsiao ECC algorithm. -- Add C_ECC_TYPE top level parameter and mappings on instantiated modules. -- ^^^^^^ -- JLJ 2/18/2011 v1.03a -- ~~~~~~ -- Update WE & BRAM data sizes based on 128-bit ECC configuration. -- Plus XST clean-up. -- ^^^^^^ -- JLJ 3/31/2011 v1.03a -- ~~~~~~ -- Add coverage tags. -- ^^^^^^ -- JLJ 4/11/2011 v1.03a -- ~~~~~~ -- Add signal, AW2Arb_BVALID_Cnt, between wr_chnl and sng_port_arb modules. -- ^^^^^^ -- JLJ 4/20/2011 v1.03a -- ~~~~~~ -- Add default values for Arb2AW_Active & Arb2AR_Active when dual port mode. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove usage of C_FAMILY. -- ^^^^^^ -- -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_bram_ctrl_funcs.all; use work.lite_ecc_reg; use work.sng_port_arb; use work.wr_chnl; use work.rd_chnl; ------------------------------------------------------------------------------ entity full_axi is generic ( -- AXI Parameters C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH : INTEGER := 4; -- AXI ID vector width C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1; -- Support for narrow burst operations C_SINGLE_PORT_BRAM : INTEGER := 0; -- Enable single port usage of BRAM -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_ECC_TYPE : integer := 0; -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Interface Signals -- AXI Clock and Reset S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; ECC_Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- AXI Write Address Channel Signals (AW) S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWLEN : in std_logic_vector(7 downto 0); S_AXI_AWSIZE : in std_logic_vector(2 downto 0); S_AXI_AWBURST : in std_logic_vector(1 downto 0); S_AXI_AWLOCK : in std_logic; S_AXI_AWCACHE : in std_logic_vector(3 downto 0); S_AXI_AWPROT : in std_logic_vector(2 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; -- AXI Write Data Channel Signals (W) S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0); S_AXI_WLAST : in std_logic; S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; -- AXI Write Data Response Channel Signals (B) S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; -- AXI Read Address Channel Signals (AR) S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARLEN : in std_logic_vector(7 downto 0); S_AXI_ARSIZE : in std_logic_vector(2 downto 0); S_AXI_ARBURST : in std_logic_vector(1 downto 0); S_AXI_ARLOCK : in std_logic; S_AXI_ARCACHE : in std_logic_vector(3 downto 0); S_AXI_ARPROT : in std_logic_vector(2 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; -- AXI Read Data Channel Signals (R) S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RLAST : out std_logic; S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- AXI-Lite ECC Register Interface Signals -- AXI-Lite Clock and Reset -- TBD -- S_AXI_CTRL_ACLK : in std_logic; -- S_AXI_CTRL_ARESETN : in std_logic; -- AXI-Lite Write Address Channel Signals (AW) S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic; -- BRAM Interface Signals (Port A) BRAM_En_A : out std_logic; BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); -- BRAM Interface Signals (Port B) BRAM_En_B : out std_logic; BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) ); end entity full_axi; ------------------------------------------------------------------------------- architecture implementation of full_axi is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH); -- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width -- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00" -- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000" -- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000" -- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000" constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- -- Internal AXI Signals signal S_AXI_AWREADY_i : std_logic := '0'; signal S_AXI_ARREADY_i : std_logic := '0'; -- Internal BRAM Signals signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal BRAM_En_A_i : std_logic := '0'; signal BRAM_En_B_i : std_logic := '0'; signal BRAM_WE_A_i : std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal BRAM_RdData_i : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); -- Internal ECC Signals signal Enable_ECC : std_logic := '0'; signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers signal Sl_CE : std_logic := '0'; -- Correctable Error Flag signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag signal Wr_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers --signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers --signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register signal Wr_Sl_CE : std_logic := '0'; -- Correctable Error Flag signal Wr_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag signal Rd_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers signal Rd_Sl_CE : std_logic := '0'; -- Correctable Error Flag signal Rd_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal FaultInjectECC : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width signal FaultInjectECC_i : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width signal Active_Wr : std_logic := '0'; signal BRAM_Addr_En : std_logic := '0'; signal Wr_BRAM_Addr_En : std_logic := '0'; signal Rd_BRAM_Addr_En : std_logic := '0'; -- Internal Arbitration Signals signal Arb2AW_Active : std_logic := '0'; signal AW2Arb_Busy : std_logic := '0'; signal AW2Arb_Active_Clr : std_logic := '0'; signal AW2Arb_BVALID_Cnt : std_logic_vector (2 downto 0) := (others => '0'); signal Arb2AR_Active : std_logic := '0'; signal AR2Arb_Active_Clr : std_logic := '0'; signal WrChnl_BRAM_Addr_Rst : std_logic := '0'; signal WrChnl_BRAM_Addr_Ld_En : std_logic := '0'; signal WrChnl_BRAM_Addr_Inc : std_logic := '0'; signal WrChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal RdChnl_BRAM_Addr_Ld_En : std_logic := '0'; signal RdChnl_BRAM_Addr_Inc : std_logic := '0'; signal RdChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- * BRAM Output Signals * --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: ADDR_SNG_PORT -- Purpose: OR the BRAM_Addr outputs from each wr_chnl & rd_chnl -- Only one write or read will be active at a time. -- Ensure that ecah channel address is driven to '0' when not in use. --------------------------------------------------------------------------- ADDR_SNG_PORT: if C_SINGLE_PORT_BRAM = 1 generate signal sng_bram_addr_rst : std_logic := '0'; signal sng_bram_addr_ld_en : std_logic := '0'; signal sng_bram_addr_ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal sng_bram_addr_inc : std_logic := '0'; begin -- BRAM_Addr_A <= BRAM_Addr_A_i or BRAM_Addr_B_i; -- BRAM_Addr_A <= BRAM_Addr_A_i when (Arb2AW_Active = '1') else BRAM_Addr_B_i; -- BRAM_Addr_A <= BRAM_Addr_A_i when (Active_Wr = '1') else BRAM_Addr_B_i; -- Insert mux on address counter control signals sng_bram_addr_rst <= WrChnl_BRAM_Addr_Rst; sng_bram_addr_ld_en <= WrChnl_BRAM_Addr_Ld_En or RdChnl_BRAM_Addr_Ld_En; sng_bram_addr_ld <= RdChnl_BRAM_Addr_Ld when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Ld; sng_bram_addr_inc <= RdChnl_BRAM_Addr_Inc when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Inc; I_ADDR_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (sng_bram_addr_rst = '1') then bram_addr_int <= (others => '0'); elsif (sng_bram_addr_ld_en = '1') then bram_addr_int <= sng_bram_addr_ld; elsif (sng_bram_addr_inc = '1') then bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12) <= bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12); bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <= std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1); end if; end if; end process I_ADDR_CNT; BRAM_Addr_B <= (others => '0'); BRAM_En_A <= BRAM_En_A_i or BRAM_En_B_i; -- BRAM_En_A <= BRAM_En_A_i when (Arb2AW_Active = '1') else BRAM_En_B_i; BRAM_En_B <= '0'; BRAM_RdData_i <= BRAM_RdData_A; -- Assign read data port A BRAM_WE_A <= BRAM_WE_A_i when (Arb2AW_Active = '1') else (others => '0'); -- v1.03a -- Early register on WrData and WSTRB in wr_chnl. (Previous value was always cleared). --------------------------------------------------------------------------- -- Generate: GEN_L_BRAM_ADDR -- Purpose: Generate zeros on lower order address bits adjustable -- based on BRAM data width. --------------------------------------------------------------------------- GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin BRAM_Addr_A (i) <= '0'; end generate GEN_L_BRAM_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_ADDR -- Purpose: Assign BRAM address output from address counter. --------------------------------------------------------------------------- GEN_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin BRAM_Addr_A (i) <= bram_addr_int (i); end generate GEN_BRAM_ADDR; end generate ADDR_SNG_PORT; --------------------------------------------------------------------------- -- Generate: ADDR_DUAL_PORT -- Purpose: Assign each BRAM address when in a dual port controller -- configuration. --------------------------------------------------------------------------- ADDR_DUAL_PORT: if C_SINGLE_PORT_BRAM = 0 generate begin BRAM_Addr_A <= BRAM_Addr_A_i; BRAM_Addr_B <= BRAM_Addr_B_i; BRAM_En_A <= BRAM_En_A_i; BRAM_En_B <= BRAM_En_B_i; BRAM_WE_A <= BRAM_WE_A_i; BRAM_RdData_i <= BRAM_RdData_B; -- Assign read data port B end generate ADDR_DUAL_PORT; BRAM_WrData_B <= (others => '0'); BRAM_WE_B <= (others => '0'); --------------------------------------------------------------------------- -- * AXI-Lite ECC Register Output Signals * --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NO_REGS -- Purpose: Generate default values if ECC registers are disabled (or when -- ECC is disabled). -- Include both AXI-Lite default signal values & internal -- core signal values. --------------------------------------------------------------------------- GEN_NO_REGS: if (C_ECC = 0) generate begin S_AXI_CTRL_AWREADY <= '0'; S_AXI_CTRL_WREADY <= '0'; S_AXI_CTRL_BRESP <= (others => '0'); S_AXI_CTRL_BVALID <= '0'; S_AXI_CTRL_ARREADY <= '0'; S_AXI_CTRL_RDATA <= (others => '0'); S_AXI_CTRL_RRESP <= (others => '0'); S_AXI_CTRL_RVALID <= '0'; -- No fault injection FaultInjectData <= (others => '0'); FaultInjectECC <= (others => '0'); -- Interrupt only enabled when ECC status/interrupt registers enabled ECC_Interrupt <= '0'; ECC_UE <= '0'; Enable_ECC <= '0'; end generate GEN_NO_REGS; --------------------------------------------------------------------------- -- Generate: GEN_REGS -- Purpose: Generate ECC register module when ECC is enabled and -- ECC registers are enabled. --------------------------------------------------------------------------- -- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate -- For future implementation. GEN_REGS: if (C_ECC = 1) generate begin --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- Description: This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. --------------------------------------------------------------------------- I_LITE_ECC_REG : entity work.lite_ecc_reg generic map ( C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width C_FAULT_INJECT => C_FAULT_INJECT , C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS , C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS , C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS , C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER , C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE , C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH ) port map ( S_AXI_AClk => S_AXI_AClk , -- AXI clock S_AXI_AResetn => S_AXI_AResetn , -- TBD -- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock -- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn , Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , -- Add AXI-Lite ECC Register Ports AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID , AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY , AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR , AXI_CTRL_WDATA => S_AXI_CTRL_WDATA , AXI_CTRL_WVALID => S_AXI_CTRL_WVALID , AXI_CTRL_WREADY => S_AXI_CTRL_WREADY , AXI_CTRL_BRESP => S_AXI_CTRL_BRESP , AXI_CTRL_BVALID => S_AXI_CTRL_BVALID , AXI_CTRL_BREADY => S_AXI_CTRL_BREADY , AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR , AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID , AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY , AXI_CTRL_RDATA => S_AXI_CTRL_RDATA , AXI_CTRL_RRESP => S_AXI_CTRL_RRESP , AXI_CTRL_RVALID => S_AXI_CTRL_RVALID , AXI_CTRL_RREADY => S_AXI_CTRL_RREADY , Enable_ECC => Enable_ECC , FaultInjectClr => FaultInjectClr , CE_Failing_We => CE_Failing_We , CE_CounterReg_Inc => CE_Failing_We , Sl_CE => Sl_CE , Sl_UE => Sl_UE , BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a BRAM_Addr_En => BRAM_Addr_En , Active_Wr => Active_Wr , -- BRAM_RdData_A => BRAM_RdData_A (C_S_AXI_DATA_WIDTH-1 downto 0) , -- BRAM_RdData_B => BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0) , FaultInjectData => FaultInjectData , FaultInjectECC => FaultInjectECC_i ); BRAM_Addr_En <= Wr_BRAM_Addr_En or Rd_BRAM_Addr_En; -- v1.03a -- Add coverage tags for Wr_CE_Failing_We. -- No testing on forcing errors with RMW and AXI write transfers. --coverage off CE_Failing_We <= Wr_CE_Failing_We or Rd_CE_Failing_We; Sl_CE <= Wr_Sl_CE or Rd_Sl_CE; Sl_UE <= Wr_Sl_UE or Rd_Sl_UE; --coverage on ------------------------------------------------------------------- -- Generate: GEN_32 -- Purpose: Add MSB '0' on ECC vector as only 7-bits wide in 32-bit. ------------------------------------------------------------------- GEN_32: if C_S_AXI_DATA_WIDTH = 32 generate begin FaultInjectECC <= '0' & FaultInjectECC_i; end generate GEN_32; ------------------------------------------------------------------- -- Generate: GEN_NON_32 -- Purpose: Data widths match at 8-bits for ECC on 64-bit data. -- And 9-bits for 128-bit data. ------------------------------------------------------------------- GEN_NON_32: if C_S_AXI_DATA_WIDTH /= 32 generate begin FaultInjectECC <= FaultInjectECC_i; end generate GEN_NON_32; end generate GEN_REGS; --------------------------------------------------------------------------- -- Generate: GEN_ARB -- Purpose: Generate arbitration module when AXI4 is configured in -- single port mode. --------------------------------------------------------------------------- GEN_ARB: if (C_SINGLE_PORT_BRAM = 1) generate begin --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- Description: This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. --------------------------------------------------------------------------- I_SNG_PORT : entity work.sng_port_arb generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ) port map ( S_AXI_AClk => S_AXI_AClk , -- AXI clock S_AXI_AResetn => S_AXI_AResetn , AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0), AXI_AWVALID => S_AXI_AWVALID , AXI_AWREADY => S_AXI_AWREADY , AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0), AXI_ARVALID => S_AXI_ARVALID , AXI_ARREADY => S_AXI_ARREADY , Arb2AW_Active => Arb2AW_Active , AW2Arb_Busy => AW2Arb_Busy , AW2Arb_Active_Clr => AW2Arb_Active_Clr , AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt , Arb2AR_Active => Arb2AR_Active , AR2Arb_Active_Clr => AR2Arb_Active_Clr ); end generate GEN_ARB; --------------------------------------------------------------------------- -- Generate: GEN_DUAL -- Purpose: Dual mode. AWREADY and ARREADY are generated from each -- wr_chnl and rd_chnl module. --------------------------------------------------------------------------- GEN_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate begin S_AXI_AWREADY <= S_AXI_AWREADY_i; S_AXI_ARREADY <= S_AXI_ARREADY_i; Arb2AW_Active <= '0'; Arb2AR_Active <= '0'; end generate GEN_DUAL; --------------------------------------------------------------------------- -- Instance: I_WR_CHNL -- -- Description: -- BRAM controller write channel logic. Controls AXI bus handshaking and -- data flow on the write address (AW), write data (W) and -- write response (B) channels. -- -- BRAM signals are marked as output from Wr Chnl for future implementation -- of merging Wr/Rd channel outputs to a single port of the BRAM module. -- --------------------------------------------------------------------------- I_WR_CHNL : entity work.wr_chnl generic map ( -- C_FAMILY => C_FAMILY , C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_ECC => C_ECC , C_ECC_WIDTH => C_ECC_WIDTH , C_ECC_TYPE => C_ECC_TYPE -- v1.03a ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , AXI_AWID => S_AXI_AWID , AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0), AXI_AWLEN => S_AXI_AWLEN , AXI_AWSIZE => S_AXI_AWSIZE , AXI_AWBURST => S_AXI_AWBURST , AXI_AWLOCK => S_AXI_AWLOCK , AXI_AWCACHE => S_AXI_AWCACHE , AXI_AWPROT => S_AXI_AWPROT , AXI_AWVALID => S_AXI_AWVALID , AXI_AWREADY => S_AXI_AWREADY_i , AXI_WDATA => S_AXI_WDATA , AXI_WSTRB => S_AXI_WSTRB , AXI_WLAST => S_AXI_WLAST , AXI_WVALID => S_AXI_WVALID , AXI_WREADY => S_AXI_WREADY , AXI_BID => S_AXI_BID , AXI_BRESP => S_AXI_BRESP , AXI_BVALID => S_AXI_BVALID , AXI_BREADY => S_AXI_BREADY , -- Arb Ports Arb2AW_Active => Arb2AW_Active , AW2Arb_Busy => AW2Arb_Busy , AW2Arb_Active_Clr => AW2Arb_Active_Clr , AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt , Sng_BRAM_Addr_Rst => WrChnl_BRAM_Addr_Rst , Sng_BRAM_Addr_Ld_En => WrChnl_BRAM_Addr_Ld_En , Sng_BRAM_Addr_Ld => WrChnl_BRAM_Addr_Ld , Sng_BRAM_Addr_Inc => WrChnl_BRAM_Addr_Inc , Sng_BRAM_Addr => bram_addr_int , -- ECC Ports Enable_ECC => Enable_ECC , BRAM_Addr_En => Wr_BRAM_Addr_En , FaultInjectClr => FaultInjectClr , CE_Failing_We => Wr_CE_Failing_We , Sl_CE => Wr_Sl_CE , Sl_UE => Wr_Sl_UE , Active_Wr => Active_Wr , FaultInjectData => FaultInjectData , FaultInjectECC => FaultInjectECC , BRAM_En => BRAM_En_A_i , -- BRAM_WE => BRAM_WE_A , -- 4/13 BRAM_WE => BRAM_WE_A_i , BRAM_WrData => BRAM_WrData_A , BRAM_RdData => BRAM_RdData_A , BRAM_Addr => BRAM_Addr_A_i ); --------------------------------------------------------------------------- -- Instance: I_RD_CHNL -- -- Description: -- BRAM controller read channel logic. Controls all handshaking and data -- flow on read address (AR) and read data (R) AXI channels. -- -- BRAM signals are marked as Rd Chnl signals for future implementation -- of merging Rd/Wr BRAM signals to a single BRAM port. -- --------------------------------------------------------------------------- I_RD_CHNL : entity work.rd_chnl generic map ( -- C_FAMILY => C_FAMILY , C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_ECC => C_ECC , C_ECC_WIDTH => C_ECC_WIDTH , C_ECC_TYPE => C_ECC_TYPE -- v1.03a ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , AXI_ARID => S_AXI_ARID , AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0), AXI_ARLEN => S_AXI_ARLEN , AXI_ARSIZE => S_AXI_ARSIZE , AXI_ARBURST => S_AXI_ARBURST , AXI_ARLOCK => S_AXI_ARLOCK , AXI_ARCACHE => S_AXI_ARCACHE , AXI_ARPROT => S_AXI_ARPROT , AXI_ARVALID => S_AXI_ARVALID , AXI_ARREADY => S_AXI_ARREADY_i , AXI_RID => S_AXI_RID , AXI_RDATA => S_AXI_RDATA , AXI_RRESP => S_AXI_RRESP , AXI_RLAST => S_AXI_RLAST , AXI_RVALID => S_AXI_RVALID , AXI_RREADY => S_AXI_RREADY , -- Arb Ports Arb2AR_Active => Arb2AR_Active , AR2Arb_Active_Clr => AR2Arb_Active_Clr , Sng_BRAM_Addr_Ld_En => RdChnl_BRAM_Addr_Ld_En , Sng_BRAM_Addr_Ld => RdChnl_BRAM_Addr_Ld , Sng_BRAM_Addr_Inc => RdChnl_BRAM_Addr_Inc , Sng_BRAM_Addr => bram_addr_int , -- ECC Ports Enable_ECC => Enable_ECC , BRAM_Addr_En => Rd_BRAM_Addr_En , CE_Failing_We => Rd_CE_Failing_We , Sl_CE => Rd_Sl_CE , Sl_UE => Rd_Sl_UE , BRAM_En => BRAM_En_B_i , BRAM_Addr => BRAM_Addr_B_i , BRAM_RdData => BRAM_RdData_i ); end architecture implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/impl/vhdl/image_filter_Mat2AXIvideo.vhd	2	23118	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity image_filter_Mat2AXIvideo is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_0_V_empty_n : IN STD_LOGIC; img_data_stream_0_V_read : OUT STD_LOGIC; img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_1_V_empty_n : IN STD_LOGIC; img_data_stream_1_V_read : OUT STD_LOGIC; img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_2_V_empty_n : IN STD_LOGIC; img_data_stream_2_V_read : OUT STD_LOGIC; OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0); OUTPUT_STREAM_TVALID : OUT STD_LOGIC; OUTPUT_STREAM_TREADY : IN STD_LOGIC; OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) ); end; architecture behav of image_filter_Mat2AXIvideo is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010"; constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100"; constant ap_ST_st5_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111"; constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000"; constant ap_const_lv13_1FFF : STD_LOGIC_VECTOR (12 downto 0) := "1111111111111"; constant ap_const_lv12_1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001"; constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111"; signal ap_done_reg : STD_LOGIC := '0'; signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_bdd_23 : BOOLEAN; signal p_3_reg_170 : STD_LOGIC_VECTOR (11 downto 0); signal ap_sig_bdd_60 : BOOLEAN; signal op2_assign_fu_186_p2 : STD_LOGIC_VECTOR (12 downto 0); signal op2_assign_reg_267 : STD_LOGIC_VECTOR (12 downto 0); signal exitcond3_fu_197_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC; signal ap_sig_bdd_74 : BOOLEAN; signal i_V_fu_202_p2 : STD_LOGIC_VECTOR (11 downto 0); signal i_V_reg_276 : STD_LOGIC_VECTOR (11 downto 0); signal exitcond4_fu_208_p2 : STD_LOGIC_VECTOR (0 downto 0); signal exitcond4_reg_281 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC; signal ap_sig_bdd_85 : BOOLEAN; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0'; signal ap_sig_bdd_99 : BOOLEAN; signal ap_sig_ioackin_OUTPUT_STREAM_TREADY : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal j_V_fu_213_p2 : STD_LOGIC_VECTOR (11 downto 0); signal axi_last_V_fu_223_p2 : STD_LOGIC_VECTOR (0 downto 0); signal axi_last_V_reg_290 : STD_LOGIC_VECTOR (0 downto 0); signal p_s_reg_159 : STD_LOGIC_VECTOR (11 downto 0); signal ap_sig_cseq_ST_st5_fsm_3 : STD_LOGIC; signal ap_sig_bdd_130 : BOOLEAN; signal tmp_user_V_fu_96 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ioackin_OUTPUT_STREAM_TREADY : STD_LOGIC := '0'; signal tmp_cast_fu_182_p1 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_cast_38_fu_219_p1 : STD_LOGIC_VECTOR (12 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0); begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_done_reg assign process. -- ap_done_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_done_reg <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_continue)) then ap_done_reg <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0)))) then ap_done_reg <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ioackin_OUTPUT_STREAM_TREADY assign process. -- ap_reg_ioackin_OUTPUT_STREAM_TREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0; else if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_99 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (ap_const_logic_1 = OUTPUT_STREAM_TREADY)))) then ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it0 assign process. -- ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0)))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_1; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0))))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; end if; end if; end if; end process; -- p_3_reg_170 assign process. -- p_3_reg_170_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then p_3_reg_170 <= j_V_fu_213_p2; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0))) then p_3_reg_170 <= ap_const_lv12_0; end if; end if; end process; -- p_s_reg_159 assign process. -- p_s_reg_159_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_3)) then p_s_reg_159 <= i_V_reg_276; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then p_s_reg_159 <= ap_const_lv12_0; end if; end if; end process; -- tmp_user_V_fu_96 assign process. -- tmp_user_V_fu_96_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then tmp_user_V_fu_96 <= ap_const_lv1_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then tmp_user_V_fu_96 <= ap_const_lv1_1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then axi_last_V_reg_290 <= axi_last_V_fu_223_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then exitcond4_reg_281 <= exitcond4_fu_208_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then i_V_reg_276 <= i_V_fu_202_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then op2_assign_reg_267 <= op2_assign_fu_186_p2; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_60, exitcond3_fu_197_p2, exitcond4_fu_208_p2, exitcond4_reg_281, ap_reg_ppiten_pp0_it0, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not(ap_sig_bdd_60)) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => if (not((exitcond3_fu_197_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st1_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; end if; when ap_ST_pp0_stg0_fsm_2 => if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0))))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0)))) then ap_NS_fsm <= ap_ST_st5_fsm_3; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; end if; when ap_ST_st5_fsm_3 => ap_NS_fsm <= ap_ST_st2_fsm_1; when others => ap_NS_fsm <= "XXXX"; end case; end process; OUTPUT_STREAM_TDATA <= (((ap_const_lv8_FF & img_data_stream_2_V_dout) & img_data_stream_1_V_dout) & img_data_stream_0_V_dout); OUTPUT_STREAM_TDEST <= ap_const_lv1_0; OUTPUT_STREAM_TID <= ap_const_lv1_0; OUTPUT_STREAM_TKEEP <= ap_const_lv4_F; OUTPUT_STREAM_TLAST <= axi_last_V_reg_290; OUTPUT_STREAM_TSTRB <= ap_const_lv4_0; OUTPUT_STREAM_TUSER <= tmp_user_V_fu_96; -- OUTPUT_STREAM_TVALID assign process. -- OUTPUT_STREAM_TVALID_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_reg_ppiten_pp0_it1, ap_reg_ioackin_OUTPUT_STREAM_TREADY) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_99 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (ap_const_logic_0 = ap_reg_ioackin_OUTPUT_STREAM_TREADY)))) then OUTPUT_STREAM_TVALID <= ap_const_logic_1; else OUTPUT_STREAM_TVALID <= ap_const_logic_0; end if; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_done_reg, exitcond3_fu_197_p2, ap_sig_cseq_ST_st2_fsm_1) begin if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(exitcond3_fu_197_p2, ap_sig_cseq_ST_st2_fsm_1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0)))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_sig_bdd_130 assign process. -- ap_sig_bdd_130_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_130 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; -- ap_sig_bdd_23 assign process. -- ap_sig_bdd_23_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_23 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; -- ap_sig_bdd_60 assign process. -- ap_sig_bdd_60_assign_proc : process(ap_start, ap_done_reg) begin ap_sig_bdd_60 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1)); end process; -- ap_sig_bdd_74 assign process. -- ap_sig_bdd_74_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_74 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; -- ap_sig_bdd_85 assign process. -- ap_sig_bdd_85_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_85 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; -- ap_sig_bdd_99 assign process. -- ap_sig_bdd_99_assign_proc : process(img_data_stream_0_V_empty_n, img_data_stream_1_V_empty_n, img_data_stream_2_V_empty_n, exitcond4_reg_281) begin ap_sig_bdd_99 <= (((img_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond4_reg_281 = ap_const_lv1_0)) or ((exitcond4_reg_281 = ap_const_lv1_0) and (img_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond4_reg_281 = ap_const_lv1_0) and (img_data_stream_2_V_empty_n = ap_const_logic_0))); end process; -- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. -- ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_85) begin if (ap_sig_bdd_85) then ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st1_fsm_0 assign process. -- ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_23) begin if (ap_sig_bdd_23) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st2_fsm_1 assign process. -- ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_74) begin if (ap_sig_bdd_74) then ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st5_fsm_3 assign process. -- ap_sig_cseq_ST_st5_fsm_3_assign_proc : process(ap_sig_bdd_130) begin if (ap_sig_bdd_130) then ap_sig_cseq_ST_st5_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_st5_fsm_3 <= ap_const_logic_0; end if; end process; -- ap_sig_ioackin_OUTPUT_STREAM_TREADY assign process. -- ap_sig_ioackin_OUTPUT_STREAM_TREADY_assign_proc : process(OUTPUT_STREAM_TREADY, ap_reg_ioackin_OUTPUT_STREAM_TREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_OUTPUT_STREAM_TREADY)) then ap_sig_ioackin_OUTPUT_STREAM_TREADY <= OUTPUT_STREAM_TREADY; else ap_sig_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1; end if; end process; axi_last_V_fu_223_p2 <= "1" when (tmp_cast_38_fu_219_p1 = op2_assign_reg_267) else "0"; exitcond3_fu_197_p2 <= "1" when (p_s_reg_159 = img_rows_V_read) else "0"; exitcond4_fu_208_p2 <= "1" when (p_3_reg_170 = img_cols_V_read) else "0"; i_V_fu_202_p2 <= std_logic_vector(unsigned(p_s_reg_159) + unsigned(ap_const_lv12_1)); -- img_data_stream_0_V_read assign process. -- img_data_stream_0_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then img_data_stream_0_V_read <= ap_const_logic_1; else img_data_stream_0_V_read <= ap_const_logic_0; end if; end process; -- img_data_stream_1_V_read assign process. -- img_data_stream_1_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then img_data_stream_1_V_read <= ap_const_logic_1; else img_data_stream_1_V_read <= ap_const_logic_0; end if; end process; -- img_data_stream_2_V_read assign process. -- img_data_stream_2_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then img_data_stream_2_V_read <= ap_const_logic_1; else img_data_stream_2_V_read <= ap_const_logic_0; end if; end process; j_V_fu_213_p2 <= std_logic_vector(unsigned(p_3_reg_170) + unsigned(ap_const_lv12_1)); op2_assign_fu_186_p2 <= std_logic_vector(unsigned(tmp_cast_fu_182_p1) + unsigned(ap_const_lv13_1FFF)); tmp_cast_38_fu_219_p1 <= std_logic_vector(resize(unsigned(p_3_reg_170),13)); tmp_cast_fu_182_p1 <= std_logic_vector(resize(unsigned(img_cols_V_read),13)); end behav;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/FIFO_image_filter_src0_rows_V.vhd	2	4556	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_src0_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_src0_rows_V_shiftReg; architecture rtl of FIFO_image_filter_src0_rows_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_src0_rows_V is generic ( MEM_STYLE : string := "shiftreg"; DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_src0_rows_V is component FIFO_image_filter_src0_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_src0_rows_V_shiftReg : FIFO_image_filter_src0_rows_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/demo/ipi_proj/srcs/ip/vsrc_sel_v1_0/vhdl/video_src_sel.vhd	6	8306	-- ************************************************************************* -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2010 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ************************************************************************* ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port: "_i" -- device pins: "_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC>" ------------------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Library UNISIM; use UNISIM.vcomponents.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_NUM_REG -- Number of software accessible registers -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Resetn -- Bus to IP reset -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity vsrc_sel is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_CHANNELS : integer := 1 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ -- User logic ports video_clk_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); video_clk_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); hsync_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); hsync_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); vsync_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); vsync_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); de_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); de_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); video_clk : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); hsync : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); vsync : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); de : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); video_sel : in std_logic ); attribute MAX_FANOUT : string; attribute SIGIS : string; -- attribute SIGIS of Bus2IP_Clk : signal is "CLK"; -- attribute SIGIS of Bus2IP_Resetn : signal is "RST"; end entity vsrc_sel; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of vsrc_sel is begin de <= de_1 when video_sel = '0' else de_2; hsync <= hsync_1 when video_sel = '0' else hsync_2; vsync <= vsync_1 when video_sel = '0' else vsync_2; VIDEO_SEL_GEN:for i in 0 to C_NUM_CHANNELS-1 generate begin BUFGMUX_INST : BUFGMUX generic map ( CLK_SEL_TYPE => "SYNC" -- Not supported. Must be "SYNC". ) port map ( O => video_clk(i), -- 1-bit output: Clock buffer output I0 => video_clk_1(i), -- 1-bit input: Clock buffer input (S=0) I1 => video_clk_2(i), -- 1-bit input: Clock buffer input (S=1) S => video_sel-- 1-bit input: Clock buffer select ); end generate VIDEO_SEL_GEN; end IMP;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_ftch_sm.vhd	4	47863	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_sg_ftch_sm.vhd -- Description: This entity manages fetching of descriptors. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.clog2; ------------------------------------------------------------------------------- entity axi_sg_ftch_sm is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_INCLUDE_CH1 : integer range 0 to 1 := 1; -- Include or Exclude channel 1 scatter gather engine -- 0 = Exclude Channel 1 SG Engine -- 1 = Include Channel 1 SG Engine C_INCLUDE_CH2 : integer range 0 to 1 := 1; -- Include or Exclude channel 2 scatter gather engine -- 0 = Exclude Channel 2 SG Engine -- 1 = Include Channel 2 SG Engine C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1; -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1 -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- updt_error : in std_logic ; -- -- -- Channel 1 Control and Status -- ch1_run_stop : in std_logic ; -- ch1_desc_flush : in std_logic ; -- ch1_updt_done : in std_logic ; -- ch1_sg_idle : in std_logic ; -- ch1_tailpntr_enabled : in std_logic ; -- ch1_ftch_queue_full : in std_logic ; -- ch1_ftch_queue_empty : in std_logic ; -- ch1_ftch_pause : in std_logic ; -- ch1_fetch_address : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch1_ftch_active : out std_logic ; -- ch1_ftch_idle : out std_logic ; -- ch1_ftch_interr_set : out std_logic ; -- ch1_ftch_slverr_set : out std_logic ; -- ch1_ftch_decerr_set : out std_logic ; -- ch1_ftch_err_early : out std_logic ; -- ch1_ftch_stale_desc : out std_logic ; -- -- -- Channel 2 Control and Status -- ch2_run_stop : in std_logic ; -- ch2_desc_flush : in std_logic ; -- ch2_updt_done : in std_logic ; -- ch2_sg_idle : in std_logic ; -- ch2_tailpntr_enabled : in std_logic ; -- ch2_ftch_queue_full : in std_logic ; -- ch2_ftch_queue_empty : in std_logic ; -- ch2_ftch_pause : in std_logic ; -- ch2_fetch_address : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch2_ftch_active : out std_logic ; -- ch2_ftch_idle : out std_logic ; -- ch2_ftch_interr_set : out std_logic ; -- ch2_ftch_slverr_set : out std_logic ; -- ch2_ftch_decerr_set : out std_logic ; -- ch2_ftch_err_early : out std_logic ; -- ch2_ftch_stale_desc : out std_logic ; -- -- -- DataMover Command -- ftch_cmnd_wr : out std_logic ; -- ftch_cmnd_data : out std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- DataMover Status -- ftch_done : in std_logic ; -- ftch_error : in std_logic ; -- ftch_interr : in std_logic ; -- ftch_slverr : in std_logic ; -- ftch_decerr : in std_logic ; -- ftch_stale_desc : in std_logic ; -- ftch_error_early : in std_logic ; -- ftch_error_addr : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) -- ); end axi_sg_ftch_sm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_ftch_sm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; attribute mark_debug : string; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- DataMover Command Type constant FETCH_CMD_TYPE : std_logic := '1'; -- DataMover Cmnd Reserved Bits constant FETCH_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0'); -- DataMover Cmnd Reserved Bits constant FETCH_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0'); -- DataMover Cmnd Bytes to Xfer for Channel 1 constant FETCH_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0) := std_logic_vector(to_unsigned( (C_SG_CH1_WORDS_TO_FETCH4),SG_BTT_WIDTH)); -- DataMover Cmnd Bytes to Xfer for Channel 2 constant FETCH_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0) := std_logic_vector(to_unsigned( (C_SG_CH2_WORDS_TO_FETCH4),SG_BTT_WIDTH)); -- DataMover Cmnd Reserved Bits constant FETCH_CMD_RSVD : std_logic_vector( DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH) := (others => '0'); -- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate -- Required width in bits for C_SG_FTCH_DESC2QUEUE --constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1); -- ---- Vector version of C_SG_FTCH_DESC2QUEUE --constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) -- := std_logic_vector(to_unsigned -- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH)); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- DataMover Commmand TAG signal fetch_tag : std_logic_vector(3 downto 0) := (others => '0'); type SG_FTCH_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, FETCH_STATUS, FETCH_ERROR ); signal ftch_cs : SG_FTCH_STATE_TYPE; signal ftch_ns : SG_FTCH_STATE_TYPE; -- State Machine Signals signal ch1_active_set : std_logic := '0'; signal ch2_active_set : std_logic := '0'; signal write_cmnd_cmb : std_logic := '0'; signal ch1_ftch_sm_idle : std_logic := '0'; signal ch2_ftch_sm_idle : std_logic := '0'; signal ch1_pause_fetch : std_logic := '0'; signal ch2_pause_fetch : std_logic := '0'; signal ch2_pause_fetch1 : std_logic := '0'; signal ch2_pause_fetch2 : std_logic := '0'; signal ch2_pause_fetch3 : std_logic := '0'; signal ch2_updt_done1 : std_logic := '0'; signal ch2_updt_done2 : std_logic := '0'; -- Misc Signals signal fetch_cmd_addr : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal ch1_active_i : std_logic := '0'; signal service_ch1 : std_logic := '0'; signal ch2_active_i : std_logic := '0'; signal service_ch2 : std_logic := '0'; attribute mark_debug of ch1_active_i : signal is "true"; attribute mark_debug of ch2_active_i : signal is "true"; signal fetch_cmd_btt : std_logic_vector (SG_BTT_WIDTH-1 downto 0) := (others => '0'); signal ch1_stale_descriptor : std_logic := '0'; signal ch2_stale_descriptor : std_logic := '0'; attribute mark_debug of ch1_stale_descriptor : signal is "true"; attribute mark_debug of ch2_stale_descriptor : signal is "true"; signal ch1_ftch_interr_set_i : std_logic := '0'; signal ch2_ftch_interr_set_i : std_logic := '0'; -- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate -- counts for keeping track of queue descriptors to prevent -- fifo fill --signal ch1_desc_ftched_count : std_logic_vector -- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0'); --signal ch2_desc_ftched_count : std_logic_vector -- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ch1_ftch_active <= ch1_active_i; ch2_ftch_active <= ch2_active_i; ------------------------------------------------------------------------------- -- Scatter Gather Fetch State Machine ------------------------------------------------------------------------------- SG_FTCH_MACHINE : process(ftch_cs, ch1_active_i, ch2_active_i, service_ch1, service_ch2, ftch_error, ftch_done) begin -- Default signal assignment ch1_active_set <= '0'; ch2_active_set <= '0'; write_cmnd_cmb <= '0'; ch1_ftch_sm_idle <= '0'; ch2_ftch_sm_idle <= '0'; ftch_ns <= ftch_cs; case ftch_cs is ------------------------------------------------------------------- when IDLE => ch1_ftch_sm_idle <= not service_ch1; ch2_ftch_sm_idle <= not service_ch2; -- sg error during fetch - shut down if(ftch_error = '1')then ftch_ns <= FETCH_ERROR; -- If channel 1 is running and not idle and queue is not full -- then fetch descriptor for channel 1 elsif(service_ch1 = '1')then ch1_active_set <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- If channel 2 is running and not idle and queue is not full -- then fetch descriptor for channel 2 elsif(service_ch2 = '1')then ch2_active_set <= '1'; ftch_ns <= FETCH_DESCRIPTOR; else ftch_ns <= IDLE; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => -- sg error during fetch - shut down if(ftch_error = '1')then ftch_ns <= FETCH_ERROR; else ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1; ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2; write_cmnd_cmb <= '1'; ftch_ns <= FETCH_STATUS; end if; ------------------------------------------------------------------- when FETCH_STATUS => ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1; ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2; -- sg error during fetch - shut down if(ftch_error = '1')then ftch_ns <= FETCH_ERROR; elsif(ftch_done = '1')then -- If just finished fethcing for channel 2 then... if(ch2_active_i = '1')then -- If ready, fetch descriptor for channel 1 if(service_ch1 = '1')then ch1_active_set <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- Else if channel 2 still ready then fetch -- another descriptor for channel 2 elsif(service_ch2 = '1')then ch1_ftch_sm_idle <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- Otherwise return to IDLE else ftch_ns <= IDLE; end if; -- If just finished fethcing for channel 1 then... elsif(ch1_active_i = '1')then -- If ready, fetch descriptor for channel 2 if(service_ch2 = '1')then ch2_active_set <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- Else if channel 1 still ready then fetch -- another descriptor for channel 1 elsif(service_ch1 = '1')then ch2_ftch_sm_idle <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- Otherwise return to IDLE else ftch_ns <= IDLE; end if; else ftch_ns <= IDLE; end if; else ftch_ns <= FETCH_STATUS; end if; ------------------------------------------------------------------- when FETCH_ERROR => ch1_ftch_sm_idle <= '1'; ch2_ftch_sm_idle <= '1'; ftch_ns <= FETCH_ERROR; ------------------------------------------------------------------- -- coverage off when others => ftch_ns <= IDLE; -- coverage on end case; end process SG_FTCH_MACHINE; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then ftch_cs <= IDLE; else ftch_cs <= ftch_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- Channel included therefore generate fetch logic ------------------------------------------------------------------------------- GEN_CH1_FETCH : if C_INCLUDE_CH1 = 1 generate begin ------------------------------------------------------------------------------- -- Active channel flag. Indicates which channel is active. -- 0 = channel active -- 1 = channel active ------------------------------------------------------------------------------- CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or ch2_active_set = '1')then ch1_active_i <= '0'; elsif(ch1_active_set = '1')then ch1_active_i <= '1'; end if; end if; end process CH1_ACTIVE_PROCESS; ------------------------------------------------------------------------------- -- Channel 1 IDLE process. Indicates channel 1 fetch process is IDLE -- This is 1 part of determining IDLE for a channel ------------------------------------------------------------------------------- CH1_IDLE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch1_ftch_idle <= '1'; -- SG Error therefore force IDLE -- CR564855 - fetch idle asserted too soon when update error occured. -- fetch idle does not need to be concerned with updt_error. This is -- because on going fetch is guarentteed to complete regardless of dma -- controller or sg update engine. --elsif(updt_error = '1' or ftch_error = '1' elsif(ftch_error = '1' or ch1_ftch_interr_set_i = '1')then ch1_ftch_idle <= '1'; -- When SG Fetch no longer idle then clear fetch idle elsif(ch1_sg_idle = '0')then ch1_ftch_idle <= '0'; -- If tail = cur and fetch queue is empty then elsif(ch1_sg_idle = '1' and ch1_ftch_queue_empty = '1' and ch1_ftch_sm_idle = '1')then ch1_ftch_idle <= '1'; end if; end if; end process CH1_IDLE_PROCESS; ------------------------------------------------------------------------------- -- For No Fetch Queue, generate pause logic to prevent partial descriptor from -- being fetched and then endless throttle on AXI read bus ------------------------------------------------------------------------------- GEN_CH1_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate begin REG_PAUSE_FETCH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- On descriptor update done clear pause if(m_axi_sg_aresetn = '0' or ch1_updt_done = '1')then ch1_pause_fetch <= '0'; -- If channel active and command written then pause elsif(ch1_active_i='1' and write_cmnd_cmb = '1')then ch1_pause_fetch <= '1'; end if; end if; end process REG_PAUSE_FETCH; end generate GEN_CH1_FETCH_PAUSE; -- Fetch queues so do not need to pause GEN_CH1_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate -- -- CR585958 -- -- Required width in bits for C_SG_FTCH_DESC2QUEUE -- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1); -- -- Vector version of C_SG_FTCH_DESC2QUEUE -- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) -- := std_logic_vector(to_unsigned -- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH)); -- signal desc_queued_incr : std_logic := '0'; -- signal desc_queued_decr : std_logic := '0'; -- -- -- CR585958 -- signal ch1_desc_ftched_count: std_logic_vector -- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0'); -- begin -- -- desc_queued_incr <= '1' when ch1_active_i = '1' -- and write_cmnd_cmb = '1' -- and ch1_ftch_descpulled = '0' -- else '0'; -- -- desc_queued_decr <= '1' when ch1_ftch_descpulled = '1' -- and not (ch1_active_i = '1' and write_cmnd_cmb = '1') -- else '0'; -- -- -- Keep track of descriptors queued version descriptors updated -- DESC_FETCHED_CNTR : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ch1_desc_ftched_count <= (others => '0'); -- elsif(desc_queued_incr = '1')then -- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) + 1); -- elsif(desc_queued_decr = '1')then -- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) - 1); -- end if; -- end if; -- end process DESC_FETCHED_CNTR; -- -- REG_PAUSE_FETCH : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ch1_pause_fetch <= '0'; -- elsif(ch1_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then -- ch1_pause_fetch <= '1'; -- else -- ch1_pause_fetch <= '0'; -- end if; -- end if; -- end process REG_PAUSE_FETCH; -- -- -- ch1_pause_fetch <= ch1_ftch_pause; end generate GEN_CH1_NO_FETCH_PAUSE; ------------------------------------------------------------------------------- -- Channel 1 ready to be serviced? ------------------------------------------------------------------------------- service_ch1 <= '1' when ch1_run_stop = '1' -- Channel running and ch1_sg_idle = '0' -- SG Engine running and ch1_ftch_queue_full = '0' -- Queue not full and updt_error = '0' -- No SG Update error and ch1_stale_descriptor = '0' -- No Stale Descriptors and ch1_desc_flush = '0' -- Not flushing desc and ch1_pause_fetch = '0' -- Not pausing else '0'; ------------------------------------------------------------------------------- -- Log Fetch Errors ------------------------------------------------------------------------------- INT_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch1_ftch_interr_set_i <= '0'; -- Channel active and datamover int error or fetch done and descriptor stale elsif((ch1_active_i = '1' and ftch_interr = '1') or ((ftch_done = '1' or ftch_error = '1') and ch1_stale_descriptor = '1'))then ch1_ftch_interr_set_i <= '1'; end if; end if; end process INT_ERROR_PROCESS; ch1_ftch_interr_set <= ch1_ftch_interr_set_i; SLV_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch1_ftch_slverr_set <= '0'; elsif(ch1_active_i = '1' and ftch_slverr = '1')then ch1_ftch_slverr_set <= '1'; end if; end if; end process SLV_ERROR_PROCESS; DEC_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch1_ftch_decerr_set <= '0'; elsif(ch1_active_i = '1' and ftch_decerr = '1')then ch1_ftch_decerr_set <= '1'; end if; end if; end process DEC_ERROR_PROCESS; -- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor -- from being used by dma controller ch1_ftch_err_early <= '1' when ftch_error_early = '1' and ch1_active_i = '1' else '0'; -- Enable stale descriptor check GEN_CH1_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 generate begin ----------------------------------------------------------------------- -- Stale Descriptor Error ----------------------------------------------------------------------- CH1_STALE_DESC : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset then clear flag if(m_axi_sg_aresetn = '0')then ch1_stale_descriptor <= '0'; elsif(ftch_stale_desc = '1' and ch1_active_i = '1' )then ch1_stale_descriptor <= '1'; end if; end if; end process CH1_STALE_DESC; end generate GEN_CH1_STALE_CHECK; -- Disable stale descriptor check GEN_CH1_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 generate begin ch1_stale_descriptor <= '0'; end generate GEN_CH1_NO_STALE_CHECK; -- Early detection of Stale Descriptor (valid only in tailpntr mode) used -- to prevent error'ed descriptor from being used. ch1_ftch_stale_desc <= ch1_stale_descriptor; end generate GEN_CH1_FETCH; ------------------------------------------------------------------------------- -- Channel excluded therefore do not generate fetch logic ------------------------------------------------------------------------------- GEN_NO_CH1_FETCH : if C_INCLUDE_CH1 = 0 generate begin service_ch1 <= '0'; ch1_active_i <= '0'; ch1_ftch_idle <= '0'; ch1_ftch_interr_set <= '0'; ch1_ftch_slverr_set <= '0'; ch1_ftch_decerr_set <= '0'; ch1_ftch_err_early <= '0'; ch1_ftch_stale_desc <= '0'; end generate GEN_NO_CH1_FETCH; ------------------------------------------------------------------------------- -- Channel included therefore generate fetch logic ------------------------------------------------------------------------------- GEN_CH2_FETCH : if C_INCLUDE_CH2 = 1 generate begin ------------------------------------------------------------------------------- -- Active channel flag. Indicates which channel is active. -- 0 = channel active -- 1 = channel active ------------------------------------------------------------------------------- CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or ch1_active_set = '1')then ch2_active_i <= '0'; elsif(ch2_active_set = '1')then ch2_active_i <= '1'; end if; end if; end process CH2_ACTIVE_PROCESS; ------------------------------------------------------------------------------- -- Channel 2 IDLE process. Indicates channel 2 fetch process is IDLE -- This is 1 part of determining IDLE for a channel ------------------------------------------------------------------------------- CH2_IDLE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch2_ftch_idle <= '1'; -- SG Error therefore force IDLE -- CR564855 - fetch idle asserted too soon when update error occured. -- fetch idle does not need to be concerned with updt_error. This is -- because on going fetch is guarentteed to complete regardless of dma -- controller or sg update engine. -- elsif(updt_error = '1' or ftch_error = '1' elsif(ftch_error = '1' or ch2_ftch_interr_set_i = '1')then ch2_ftch_idle <= '1'; -- When SG Fetch no longer idle then clear fetch idle elsif(ch2_sg_idle = '0')then ch2_ftch_idle <= '0'; -- If tail = cur and fetch queue is empty then elsif(ch2_sg_idle = '1' and ch2_ftch_queue_empty = '1' and ch2_ftch_sm_idle = '1')then ch2_ftch_idle <= '1'; end if; end if; end process CH2_IDLE_PROCESS; ------------------------------------------------------------------------------- -- For No Fetch Queue, generate pause logic to prevent partial descriptor from -- being fetched and then endless throttle on AXI read bus ------------------------------------------------------------------------------- GEN_CH2_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate begin REG_PAUSE_FETCH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- On descriptor update done clear pause if(m_axi_sg_aresetn = '0' or ch2_updt_done = '1')then ch2_pause_fetch <= '0'; -- If channel active and command written then pause elsif(ch2_active_i='1' and write_cmnd_cmb = '1')then ch2_pause_fetch <= '1'; end if; ch2_pause_fetch1 <= ch2_pause_fetch; ch2_pause_fetch2 <= ch2_pause_fetch1; ch2_pause_fetch3 <= ch2_pause_fetch2; end if; end process REG_PAUSE_FETCH; end generate GEN_CH2_FETCH_PAUSE; -- Fetch queues so do not need to pause GEN_CH2_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate -- -- CR585958 -- -- Required width in bits for C_SG_FTCH_DESC2QUEUE -- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1); -- -- Vector version of C_SG_FTCH_DESC2QUEUE -- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) -- := std_logic_vector(to_unsigned -- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH)); -- signal desc_queued_incr : std_logic := '0'; -- signal desc_queued_decr : std_logic := '0'; -- -- -- CR585958 -- signal ch2_desc_ftched_count: std_logic_vector -- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0'); -- -- begin -- -- desc_queued_incr <= '1' when ch2_active_i = '1' -- and write_cmnd_cmb = '1' -- and ch2_ftch_descpulled = '0' -- else '0'; -- -- desc_queued_decr <= '1' when ch2_ftch_descpulled = '1' -- and not (ch2_active_i = '1' and write_cmnd_cmb = '1') -- else '0'; -- -- -- Keep track of descriptors queued version descriptors updated -- DESC_FETCHED_CNTR : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ch2_desc_ftched_count <= (others => '0'); -- elsif(desc_queued_incr = '1')then -- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) + 1); -- elsif(desc_queued_decr = '1')then -- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) - 1); -- end if; -- end if; -- end process DESC_FETCHED_CNTR; -- -- REG_PAUSE_FETCH : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ch2_pause_fetch <= '0'; -- elsif(ch2_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then -- ch2_pause_fetch <= '1'; -- else -- ch2_pause_fetch <= '0'; -- end if; -- end if; -- end process REG_PAUSE_FETCH; -- ch2_pause_fetch <= ch2_ftch_pause; end generate GEN_CH2_NO_FETCH_PAUSE; ------------------------------------------------------------------------------- -- Channel 2 ready to be serviced? ------------------------------------------------------------------------------- MCDMA : if (C_ENABLE_MULTI_CHANNEL = 1) generate NOQUEUE : if (C_SG_FTCH_DESC2QUEUE = 0) generate service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running and ch2_sg_idle = '0' -- SG Engine running and ch2_ftch_queue_full = '0' -- Queue not full and updt_error = '0' -- No SG Update error and ch2_stale_descriptor = '0' -- No Stale Descriptors and ch2_desc_flush = '0' -- Not flushing desc and ch2_pause_fetch3 = '0' -- No fetch pause else '0'; end generate NOQUEUE; QUEUE : if (C_SG_FTCH_DESC2QUEUE /= 0) generate service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running and ch2_sg_idle = '0' -- SG Engine running and ch2_ftch_queue_full = '0' -- Queue not full and updt_error = '0' -- No SG Update error and ch2_stale_descriptor = '0' -- No Stale Descriptors and ch2_desc_flush = '0' -- Not flushing desc and ch2_pause_fetch = '0' -- No fetch pause else '0'; end generate QUEUE; end generate MCDMA; NO_MCDMA : if (C_ENABLE_MULTI_CHANNEL = 0) generate service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running and ch2_sg_idle = '0' -- SG Engine running and ch2_ftch_queue_full = '0' -- Queue not full and updt_error = '0' -- No SG Update error and ch2_stale_descriptor = '0' -- No Stale Descriptors and ch2_desc_flush = '0' -- Not flushing desc and ch2_pause_fetch = '0' -- No fetch pause else '0'; end generate NO_MCDMA; ------------------------------------------------------------------------------- -- Log Fetch Errors ------------------------------------------------------------------------------- INT_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch2_ftch_interr_set_i <= '0'; -- Channel active and datamover int error or fetch done and descriptor stale elsif((ch2_active_i = '1' and ftch_interr = '1') or ((ftch_done = '1' or ftch_error = '1') and ch2_stale_descriptor = '1'))then ch2_ftch_interr_set_i <= '1'; end if; end if; end process INT_ERROR_PROCESS; ch2_ftch_interr_set <= ch2_ftch_interr_set_i; SLV_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch2_ftch_slverr_set <= '0'; elsif(ch2_active_i = '1' and ftch_slverr = '1')then ch2_ftch_slverr_set <= '1'; end if; end if; end process SLV_ERROR_PROCESS; DEC_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch2_ftch_decerr_set <= '0'; elsif(ch2_active_i = '1' and ftch_decerr = '1')then ch2_ftch_decerr_set <= '1'; end if; end if; end process DEC_ERROR_PROCESS; -- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor -- from being used by dma controller ch2_ftch_err_early <= '1' when ftch_error_early = '1' and ch2_active_i = '1' else '0'; -- Enable stale descriptor check GEN_CH2_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 1 generate begin ----------------------------------------------------------------------- -- Stale Descriptor Error ----------------------------------------------------------------------- CH2_STALE_DESC : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset then clear flag if(m_axi_sg_aresetn = '0')then ch2_stale_descriptor <= '0'; elsif(ftch_stale_desc = '1' and ch2_active_i = '1' )then ch2_stale_descriptor <= '1'; end if; end if; end process CH2_STALE_DESC; end generate GEN_CH2_STALE_CHECK; -- Disable stale descriptor check GEN_CH2_NO_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 0 generate begin ch2_stale_descriptor <= '0'; end generate GEN_CH2_NO_STALE_CHECK; -- Early detection of Stale Descriptor (valid only in tailpntr mode) used -- to prevent error'ed descriptor from being used. ch2_ftch_stale_desc <= ch2_stale_descriptor; end generate GEN_CH2_FETCH; ------------------------------------------------------------------------------- -- Channel excluded therefore do not generate fetch logic ------------------------------------------------------------------------------- GEN_NO_CH2_FETCH : if C_INCLUDE_CH2 = 0 generate begin service_ch2 <= '0'; ch2_active_i <= '0'; ch2_ftch_idle <= '0'; ch2_ftch_interr_set <= '0'; ch2_ftch_slverr_set <= '0'; ch2_ftch_decerr_set <= '0'; ch2_ftch_err_early <= '0'; ch2_ftch_stale_desc <= '0'; end generate GEN_NO_CH2_FETCH; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- Assign fetch address fetch_cmd_addr <= ch1_fetch_address when ch1_active_i = '1' else ch2_fetch_address; -- Assign bytes to transfer (BTT) fetch_cmd_btt <= FETCH_CH1_CMD_BTT when ch1_active_i = '1' else FETCH_CH2_CMD_BTT; fetch_tag <= "0001" when ch1_active_i = '1' else "0000"; -- When command by sm, drive command to ftch_cmdsts_if --GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ftch_cmnd_wr <= '0'; -- ftch_cmnd_data <= (others => '0'); -- -- Fetch SM issued a command write -- elsif(write_cmnd_cmb = '1')then -- ftch_cmnd_wr <= '1'; -- ftch_cmnd_data <= FETCH_CMD_RSVD -- & fetch_tag -- & fetch_cmd_addr -- & FETCH_MSB_IGNORED -- & FETCH_CMD_TYPE -- & FETCH_LSB_IGNORED -- & fetch_cmd_btt; -- else -- ftch_cmnd_wr <= '0'; -- end if; -- end if; -- end process GEN_DATAMOVER_CMND; ftch_cmnd_wr <= write_cmnd_cmb; ftch_cmnd_data <= FETCH_CMD_RSVD & fetch_tag & fetch_cmd_addr & FETCH_MSB_IGNORED & FETCH_CMD_TYPE & FETCH_LSB_IGNORED & fetch_cmd_btt; ------------------------------------------------------------------------------- -- Capture and hold fetch address in case an error occurs ------------------------------------------------------------------------------- LOG_ERROR_ADDR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then ftch_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= (others => '0'); elsif(write_cmnd_cmb = '1')then ftch_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= fetch_cmd_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB); end if; end if; end process LOG_ERROR_ADDR; ftch_error_addr (5 downto 0) <= "000000"; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_s2mm_full_wrap.vhd	5	92755	------------------------------------------------------------------------------- -- axi_datamover_s2mm_full_wrap.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_full_wrap.vhd -- -- Description: -- This file implements the DataMover S2MM FULL Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all ; -- axi_datamover Library Modules library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_reset ; use axi_datamover_v5_1.axi_datamover_cmd_status ; use axi_datamover_v5_1.axi_datamover_pcc ; use axi_datamover_v5_1.axi_datamover_ibttcc ; use axi_datamover_v5_1.axi_datamover_indet_btt ; use axi_datamover_v5_1.axi_datamover_s2mm_realign ; use axi_datamover_v5_1.axi_datamover_addr_cntl ; use axi_datamover_v5_1.axi_datamover_wrdata_cntl ; use axi_datamover_v5_1.axi_datamover_wr_status_cntl; Use axi_datamover_v5_1.axi_datamover_skid2mm_buf ; Use axi_datamover_v5_1.axi_datamover_skid_buf ; Use axi_datamover_v5_1.axi_datamover_wr_sf ; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_full_wrap is generic ( C_INCLUDE_S2MM : Integer range 0 to 2 := 1; -- Specifies the type of S2MM function to include -- 0 = Omit S2MM functionality -- 1 = Full S2MM Functionality -- 2 = Lite S2MM functionality C_S2MM_AWID : Integer range 0 to 255 := 9; -- Specifies the constant value to output on -- the ARID output port C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the S2MM ID port C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the S2MM Master Stream Data -- Channel data bus C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit S2MM Status FIFO -- 1 = Include S2MM Status FIFO C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the S2MM Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the S2MM function -- 0 = Omit DRE -- 1 = Include DRE C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the S2MM function C_S2MM_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the S2MM Command Interface C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if support for indeterminate packet lengths -- are to be received on the input Stream interface -- 0 = Omit support (User MUST transfer the exact number of -- bytes on the Stream interface as specified in the BTT -- field of the Corresponding DataMover Command) -- 1 = Include support for indeterminate packet lengths -- This causes FIFOs to be added and "Store and Forward" -- behavior of the S2MM function C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the S2MM internal -- address pipeline queues in the Write Address Controller -- and the Write Data Controller. Increasing this value will -- allow more Write Addresses to be issued to the AXI4 Write -- Address Channel before transmission of the associated -- write data on the Write Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_INCLUDE_S2MM_GP_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- S2MM (Write) General Purpose Store and Forward function -- 0 = Omit GP Store and Forward -- 1 = Include GP Store and Forward C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- S2MM Primary Clock and Reset inputs ---------------------------- s2mm_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- ------------------------------------------------------------------- -- S2MM Primary Reset input --------------------------------------- s2mm_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------------- -- S2MM Halt request input control -------------------------------- s2mm_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- S2MM Halt Complete status flag -- s2mm_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------------- -- S2MM Error discrete output ------------------------------------- s2mm_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------------------------- -- Optional Command and Status Clock and Reset ------------------- -- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 -- -- s2mm_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- s2mm_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------------ -- User Command Interface Ports (AXI Stream) ----------------------------------------------------- s2mm_cmd_wvalid : in std_logic; -- s2mm_cmd_wready : out std_logic; -- s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); -- -------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) -------------------------------------------------------- s2mm_sts_wvalid : out std_logic; -- s2mm_sts_wready : in std_logic; -- s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT24)+8)-1 downto 0); -- s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT24)+8)/8)-1 downto 0); -- s2mm_sts_wlast : out std_logic; -- ---------------------------------------------------------------------------------------------------- -- Address posting controls --------------------------------------- s2mm_allow_addr_req : in std_logic; -- s2mm_addr_req_posted : out std_logic; -- s2mm_wr_xfer_cmplt : out std_logic; -- s2mm_ld_nxt_len : out std_logic; -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- ------------------------------------------------------------------- -- S2MM AXI Address Channel I/O -------------------------------------- s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- s2mm_awlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- s2mm_awsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- s2mm_awburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- s2mm_awprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- s2mm_awuser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- s2mm_awready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ----------- -- s2mm__awlock : out std_logic_vector(2 downto 0); -- -- s2mm__awcache : out std_logic_vector(4 downto 0); -- -- s2mm__awqos : out std_logic_vector(3 downto 0); -- -- s2mm__awregion : out std_logic_vector(3 downto 0); -- ----------------------------------------------------------------------- -- S2MM AXI MMap Write Data Channel I/O --------------------------------------------- s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); -- s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); -- s2mm_wlast : Out std_logic; -- s2mm_wvalid : Out std_logic; -- s2mm_wready : In std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI MMap Write response Channel I/O ----------------------------------------- s2mm_bresp : In std_logic_vector(1 downto 0); -- s2mm_bvalid : In std_logic; -- s2mm_bready : Out std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI Master Stream Channel I/O ----------------------------------------------- s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); -- s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); -- s2mm_strm_wlast : In std_logic; -- s2mm_strm_wvalid : In std_logic; -- s2mm_strm_wready : Out std_logic; -- -------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------ s2mm_dbg_sel : in std_logic_vector( 3 downto 0); -- s2mm_dbg_data : out std_logic_vector(31 downto 0) -- ----------------------------------------------------------------- ); end entity axi_datamover_s2mm_full_wrap; architecture implementation of axi_datamover_s2mm_full_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_wdemux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Write Strobe demux select control. -- ------------------------------------------------------------------- function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 7 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when 256 => num_addr_bits_needed := 5; when 512 => num_addr_bits_needed := 6; when others => -- 1024 bits num_addr_bits_needed := 7; end case; Return (num_addr_bits_needed); end function func_calc_wdemux_sel_bits; ------------------------------------------------------------------- -- Function -- -- Function Name: func_include_dre -- -- Function Description: -- This function desides if conditions are right for allowing DRE -- inclusion. -- ------------------------------------------------------------------- function func_include_dre (need_dre : integer; needed_data_width : integer) return integer is Variable include_dre : Integer := 0; begin if (need_dre = 1 and needed_data_width < 128 and needed_data_width > 8) Then include_dre := 1; Else include_dre := 0; End if; Return (include_dre); end function func_include_dre; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_align_width -- -- Function Description: -- This function calculates the needed DRE alignment port width\ -- based upon the inclusion of DRE and the needed bit width of the -- DRE. -- ------------------------------------------------------------------- function func_get_align_width (dre_included : integer; dre_data_width : integer) return integer is Variable align_port_width : Integer := 1; begin if (dre_included = 1) then If (dre_data_width = 64) Then align_port_width := 3; Elsif (dre_data_width = 32) Then align_port_width := 2; else -- 16 bit data width align_port_width := 1; End if; else align_port_width := 1; end if; Return (align_port_width); end function func_get_align_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_set_status_width -- -- Function Description: -- This function sets the width of the Status pipe depending on the -- Store and Forward inclusion or ommision. -- ------------------------------------------------------------------- function funct_set_status_width (store_forward_enabled : integer) return integer is Variable temp_status_bit_width : Integer := 8; begin If (store_forward_enabled = 1) Then temp_status_bit_width := 32; Else temp_status_bit_width := 8; End if; Return (temp_status_bit_width); end function funct_set_status_width; ------------------------------------------------------------------- -- Function -- -- Function Name: get_bits_needed -- -- Function Description: -- -- ------------------------------------------------------------------- function get_bits_needed (max_bytes : integer) return integer is Variable fvar_temp_bit_width : Integer := 1; begin if (max_bytes <= 1) then fvar_temp_bit_width := 1; elsif (max_bytes <= 3) then fvar_temp_bit_width := 2; elsif (max_bytes <= 7) then fvar_temp_bit_width := 3; elsif (max_bytes <= 15) then fvar_temp_bit_width := 4; elsif (max_bytes <= 31) then fvar_temp_bit_width := 5; elsif (max_bytes <= 63) then fvar_temp_bit_width := 6; elsif (max_bytes <= 127) then fvar_temp_bit_width := 7; elsif (max_bytes <= 255) then fvar_temp_bit_width := 8; elsif (max_bytes <= 511) then fvar_temp_bit_width := 9; elsif (max_bytes <= 1023) then fvar_temp_bit_width := 10; elsif (max_bytes <= 2047) then fvar_temp_bit_width := 11; elsif (max_bytes <= 4095) then fvar_temp_bit_width := 12; elsif (max_bytes <= 8191) then fvar_temp_bit_width := 13; else -- 8k - 16K fvar_temp_bit_width := 14; end if; Return (fvar_temp_bit_width); end function get_bits_needed; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 128 and 8192. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 128) then temp_pwr2 := 128; elsif (input_value <= 256) then temp_pwr2 := 256; elsif (input_value <= 512) then temp_pwr2 := 512; elsif (input_value <= 1024) then temp_pwr2 := 1024; elsif (input_value <= 2048) then temp_pwr2 := 2048; elsif (input_value <= 4096) then temp_pwr2 := 4096; else temp_pwr2 := 8192; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_need_realigner -- -- Function Description: -- Determines if the Realigner module needs to be included. -- ------------------------------------------------------------------- function funct_need_realigner (indet_btt_enabled : integer; dre_included : integer; gp_sf_included : integer) return integer is Variable temp_val : Integer := 0; begin If ((indet_btt_enabled = 1) or (dre_included = 1) or (gp_sf_included = 1)) Then temp_val := 1; else temp_val := 0; End if; Return (temp_val); end function funct_need_realigner; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_width -- -- Function Description: -- This function calculates the address offset width needed by -- the GP Store and Forward module with data packing. -- ------------------------------------------------------------------- function funct_get_sf_offset_width (mmap_dwidth : integer; stream_dwidth : integer) return integer is Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth; Variable fvar_temp_offset_width : Integer := 1; begin case FCONST_WIDTH_RATIO is when 1 => fvar_temp_offset_width := 1; when 2 => fvar_temp_offset_width := 1; when 4 => fvar_temp_offset_width := 2; when 8 => fvar_temp_offset_width := 3; when 16 => fvar_temp_offset_width := 4; when 32 => fvar_temp_offset_width := 5; when 64 => fvar_temp_offset_width := 6; when others => fvar_temp_offset_width := 7; end case; Return (fvar_temp_offset_width); end function funct_get_sf_offset_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stream_width2use -- -- Function Description: -- This function calculates the Stream width to use for S2MM -- modules downstream from the upsizing Store and Forward. If -- Store and forward is present, then the effective Stream width -- is the MMAP data width. If no Store and Forward then the Stream -- width is the input Stream width from the User. -- ------------------------------------------------------------------- function funct_get_stream_width2use (mmap_data_width : integer; stream_data_width : integer; sf_enabled : integer) return integer is Variable fvar_temp_width : Integer := 32; begin If (sf_enabled > 0) Then fvar_temp_width := mmap_data_width; Else fvar_temp_width := stream_data_width; End if; Return (fvar_temp_width); end function funct_get_stream_width2use; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_bytes_per_dbeat -- -- Function Description: -- This function calculates the number of bytes transfered per -- databeat on the MMap AXI4 Write Data Channel by the S2MM. The -- value is based on input parameterization of included functions -- in the S2MM block. -- ------------------------------------------------------------------- function funct_get_bytes_per_dbeat (ibtt_enabled : integer ; gpsf_enabled : integer ; stream_dwidth : integer ; mmap_dwidth : integer ) return integer is Variable fvar_temp_bytes_per_xfer : Integer := 4; begin If (ibtt_enabled > 0 or gpsf_enabled > 0) Then -- transfers will be upsized to mmap data width fvar_temp_bytes_per_xfer := mmap_dwidth/8; Else -- transfers will be in stream data widths (may be narrow transfers on mmap) fvar_temp_bytes_per_xfer := stream_dwidth/8; End if; Return (fvar_temp_bytes_per_xfer); end function funct_get_bytes_per_dbeat; -- Constant Declarations ---------------------------------------- Constant SF_ENABLED : integer := C_INCLUDE_S2MM_GP_SF + C_S2MM_SUPPORT_INDET_BTT; Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_S2MM_MDATA_WIDTH, C_S2MM_SDATA_WIDTH, SF_ENABLED); Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant IS_NOT_MM2S : integer range 0 to 1 := 0; Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID; Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH; Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH; Constant S2MM_MDATA_WIDTH : integer range 32 to 1024 := C_S2MM_MDATA_WIDTH; Constant S2MM_SDATA_WIDTH : integer range 8 to 1024 := C_S2MM_SDATA_WIDTH; Constant S2MM_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH; Constant S2MM_CMD_WIDTH : integer := (S2MM_TAG_WIDTH+S2MM_ADDR_WIDTH+32); Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := C_INCLUDE_S2MM_STSFIFO; Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH; Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC; Constant S2MM_BURST_SIZE : integer range 2 to 256 := C_S2MM_BURST_SIZE; Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH); Constant S2MM_BTT_USED : integer range 8 to 23 := C_S2MM_BTT_USED; Constant BITS_PER_BYTE : integer := 8; Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant S2MM_DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_SUPPORT_SCATTER : integer range 0 to 1 := 1; Constant ENABLE_INDET_BTT_SF : integer range 0 to 1 := C_S2MM_SUPPORT_INDET_BTT; Constant ENABLE_GP_SF : integer range 0 to 1 := C_INCLUDE_S2MM_GP_SF ; Constant BYTES_PER_MMAP_DBEAT : integer := funct_get_bytes_per_dbeat(ENABLE_INDET_BTT_SF , ENABLE_GP_SF , S2MM_SDATA_WIDTH , S2MM_MDATA_WIDTH); Constant MAX_BYTES_PER_BURST : integer := BYTES_PER_MMAP_DBEATS2MM_BURST_SIZE; Constant IBTT_XFER_BYTES_WIDTH : integer := get_bits_needed(MAX_BYTES_PER_BURST); Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going -- full thresholding -- in WSC Constant WSC_STATUS_WIDTH : integer range 8 to 32 := funct_set_status_width(ENABLE_INDET_BTT_SF); Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := S2MM_BTT_USED; Constant ADD_REALIGNER : integer := funct_need_realigner(ENABLE_INDET_BTT_SF , INCLUDE_S2MM_DRE , ENABLE_GP_SF); -- Calculates the minimum needed depth of the GP Store and Forward FIFO -- based on the S2MM pipeline depth and the max allowed Burst length Constant PIPEDEPTH_BURST_LEN_PROD : integer := (ADDR_CNTL_FIFO_DEPTH+2) * S2MM_BURST_SIZE; -- Assigns the depth of the optional GP Store and Forward FIFO to the nearest -- power of 2 Constant SF_FIFO_DEPTH : integer range 128 to 8192 := funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD); -- Calculate the width of the Store and Forward Starting Address Offset bus Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(S2MM_MDATA_WIDTH, S2MM_SDATA_WIDTH); -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0'); signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_last : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2addr_data_rdy : std_logic := '0'; signal sig_data2all_tlast_error : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2wsc_calc_error : std_logic := '0'; signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0'); signal sig_data2wsc_cmd_empty : std_logic := '0'; signal sig_data2wsc_calc_err : std_logic := '0'; signal sig_data2wsc_cmd_cmplt : std_logic := '0'; signal sig_data2wsc_last_err : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_wsc2stat_status : std_logic_vector(WSC_STATUS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2wsc_status_ready : std_logic := '0'; signal sig_wsc2stat_status_valid : std_logic := '0'; signal sig_wsc2mstr_halt_pipe : std_logic := '0'; signal sig_data2wsc_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wvalid : std_logic := '0'; signal sig_skid2data_wready : std_logic := '0'; signal sig_data2skid_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_data2skid_wlast : std_logic := '0'; signal sig_skid2axi_wvalid : std_logic := '0'; signal sig_axi2skid_wready : std_logic := '0'; signal sig_skid2axi_wdata : std_logic_vector(S2MM_MDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_skid2axi_wstrb : std_logic_vector((S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_skid2axi_wlast : std_logic := '0'; signal sig_data2wsc_sof : std_logic := '0'; signal sig_data2wsc_eof : std_logic := '0'; signal sig_data2wsc_valid : std_logic := '0'; signal sig_wsc2data_ready : std_logic := '0'; signal sig_data2wsc_eop : std_logic := '0'; signal sig_data2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_sf2pcc_xfer_valid : std_logic := '0'; signal sig_pcc2sf_xfer_ready : std_logic := '0'; signal sig_sf2pcc_cmd_cmplt : std_logic := '0'; signal sig_sf2pcc_packet_eop : std_logic := '0'; signal sig_sf2pcc_xfer_bytes : std_logic_vector(IBTT_XFER_BYTES_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tvalid : std_logic := '0'; signal sig_wdc2ibtt_tready : std_logic := '0'; signal sig_ibtt2wdc_tdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tlast : std_logic := '0'; signal sig_ibtt2wdc_eop : std_logic := '0'; signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0'); signal sig_dre2ibtt_tvalid : std_logic := '0'; signal sig_ibtt2dre_tready : std_logic := '0'; signal sig_dre2ibtt_tdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tlast : std_logic := '0'; signal sig_dre2ibtt_eop : std_logic := '0'; signal sig_dre2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2dre_cmd_valid : std_logic := '0'; signal sig_mstr2dre_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_src_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_dest_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_btt : std_logic_vector(S2MM_BTT_USED-1 downto 0) := (others => '0'); signal sig_mstr2dre_drr : std_logic := '0'; signal sig_mstr2dre_eof : std_logic := '0'; signal sig_mstr2dre_cmd_cmplt : std_logic := '0'; signal sig_mstr2dre_calc_error : std_logic := '0'; signal sig_realign2wdc_eop_error : std_logic := '0'; signal sig_dre2all_halted : std_logic := '0'; signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_wsc2rst_stop_cmplt : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal skid2dre_wvalid : std_logic := '0'; signal dre2skid_wready : std_logic := '0'; signal skid2dre_wdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal skid2dre_wstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal skid2dre_wlast : std_logic := '0'; signal sig_s2mm_allow_addr_req : std_logic := '0'; signal sig_ok_to_post_wr_addr : std_logic := '0'; signal sig_s2mm_addr_req_posted : std_logic := '0'; signal sig_s2mm_wr_xfer_cmplt : std_logic := '0'; signal sig_s2mm_ld_nxt_len : std_logic := '0'; signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_ibtt2wdc_error : std_logic := '0'; signal sig_sf_strt_addr_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal s2mm_awcache_int : std_logic_vector (3 downto 0); signal s2mm_awuser_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug/Test Port Assignments s2mm_dbg_data <= sig_dbg_data_mux_out; -- Note that only the s2mm_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (s2mm_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"CAFE1111" ; -- 32 bit Constant indicating S2MM FULL type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2wsc_status_ready; sig_dbg_data_1(7) <= sig_wsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error --sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADD_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen adds in the EOP status marker to the debug -- vector data when Indet BTT Store and Forward is enabled. -- ------------------------------------------------------------ GEN_ADD_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 1) generate begin sig_dbg_data_1(19) <= sig_wsc2stat_status(31) ; -- EOP Marker end generate GEN_ADD_DEBUG_EOP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen zeros the debug vector bit used for the EOP -- status marker when Indet BTT Store and Forward is not -- enabled. -- ------------------------------------------------------------ GEN_NO_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 0) generate begin sig_dbg_data_1(19) <= '0' ; -- EOP Marker end generate GEN_NO_DEBUG_EOP; ---- End of Debug/Test Support -------------------------------- -- Assign the Address posting control outputs s2mm_addr_req_posted <= sig_s2mm_addr_req_posted ; s2mm_wr_xfer_cmplt <= sig_s2mm_wr_xfer_cmplt ; s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len ; s2mm_wr_len <= sig_s2mm_wr_len ; -- Write Data Channel I/O s2mm_wvalid <= sig_skid2axi_wvalid; sig_axi2skid_wready <= s2mm_wready ; s2mm_wdata <= sig_skid2axi_wdata ; s2mm_wlast <= sig_skid2axi_wlast ; GEN_S2MM_TKEEP_ENABLE2 : if C_ENABLE_S2MM_TKEEP = 1 generate begin s2mm_wstrb <= sig_skid2axi_wstrb ; end generate GEN_S2MM_TKEEP_ENABLE2; GEN_S2MM_TKEEP_DISABLE2 : if C_ENABLE_S2MM_TKEEP = 0 generate begin s2mm_wstrb <= (others => '1'); end generate GEN_S2MM_TKEEP_DISABLE2; GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off s2mm_awcache <= s2mm_awcache_int; -- pre Interface-X guidelines for Masters s2mm_awuser <= s2mm_awuser_int; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= s2mm_cmd_wdata(79 downto 72); -- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE2; -- Internal error output discrete s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ) port map ( primary_aclk => s2mm_aclk , primary_aresetn => s2mm_aresetn , secondary_awclk => s2mm_cmdsts_awclk , secondary_aresetn => s2mm_cmdsts_aresetn , halt_req => s2mm_halt , halt_cmplt => s2mm_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => sig_wsc2rst_stop_cmplt , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO , C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , secondary_awclk => s2mm_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => s2mm_cmd_wvalid , cmd_wready => s2mm_cmd_wready , cmd_wdata => sig_s2mm_cmd_wdata , cache_data => sig_s2mm_cache_data , sts_wvalid => s2mm_sts_wvalid , sts_wready => s2mm_sts_wready , sts_wdata => s2mm_sts_wdata , sts_wstrb => s2mm_sts_wstrb , sts_wlast => s2mm_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_wsc2stat_status , stat2mstr_status_ready => sig_stat2wsc_status_ready , mst2stst_status_valid => sig_wsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_WR_STATUS_CNTLR -- -- Description: -- Write Status Controller Block -- ------------------------------------------------------------ I_WR_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_wr_status_cntl generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2wsc_stop_request => sig_rst2all_stop_request , wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt , addr2wsc_addr_posted => sig_addr2data_addr_posted , s2mm_bresp => s2mm_bresp , s2mm_bvalid => s2mm_bvalid , s2mm_bready => s2mm_bready , calc2wsc_calc_error => sig_calc2dm_calc_err , addr2wsc_calc_error => sig_addr2wsc_calc_error , addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_error => sig_data2wsc_calc_err , data2wsc_last_error => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , data2wsc_valid => sig_data2wsc_valid , wsc2data_ready => sig_wsc2data_ready , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2stat_status => sig_wsc2stat_status , stat2wsc_status_ready => sig_stat2wsc_status_ready , wsc2stat_status_valid => sig_wsc2stat_status_valid , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_PCC -- -- If Generate Description: -- Include the normal Predictive Command Calculator function, -- Store and Forward is not an included feature. -- -- ------------------------------------------------------------ GEN_INCLUDE_PCC : if (ENABLE_INDET_BTT_SF = 0) generate begin ------------------------------------------------------------ -- Instance: I_MSTR_PCC -- -- Description: -- Predictive Command Calculator Block -- ------------------------------------------------------------ I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc generic map ( C_IS_MM2S => IS_NOT_MM2S , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_SUPPORT_INDET_BTT => ENABLE_INDET_BTT_SF , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => open , mstr2data_dre_dest_align => open , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_PCC; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_IBTTCC -- -- If Generate Description: -- Include the Indeterminate BTT Command Calculator function, -- Store and Forward is enabled in the S2MM. -- -- ------------------------------------------------------------ GEN_INCLUDE_IBTTCC : if (ENABLE_INDET_BTT_SF = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_MSTR_SFCC -- -- Description: -- Instantiates the Store and Forward Command Calculator -- Block. -- ------------------------------------------------------------ I_S2MM_MSTR_IBTTCC : entity axi_datamover_v5_1.axi_datamover_ibttcc generic map ( C_SF_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_IBTTCC; ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate begin ------------------------------------------------------------ -- Instance: I_S2MM_STRM_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registerd Slave Stream inputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => s2mm_strm_wvalid , s_ready => s2mm_strm_wready , s_data => s2mm_strm_wdata , s_strb => s2mm_strm_wstrb , s_last => s2mm_strm_wlast , -- Master Side (Stream Data Output m_valid => skid2dre_wvalid , m_ready => dre2skid_wready , m_data => skid2dre_wdata , m_strb => skid2dre_wstrb , m_last => skid2dre_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate begin skid2dre_wvalid <= s2mm_strm_wvalid; s2mm_strm_wready <= dre2skid_wready; skid2dre_wdata <= s2mm_strm_wdata; skid2dre_wstrb <= s2mm_strm_wstrb; skid2dre_wlast <= s2mm_strm_wlast; end generate DISABLE_AXIS_SKID; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_REALIGNER -- -- If Generate Description: -- Omit the S2MM Realignment Engine -- -- ------------------------------------------------------------ GEN_NO_REALIGNER : if (ADD_REALIGNER = 0) generate begin -- Set to Always ready for DRE to PCC Command Interface sig_dre2mstr_cmd_ready <= LOGIC_HIGH; -- Without DRE and Scatter, the end of packet is the TLAST --sig_dre2ibtt_eop <= skid2dre_wlast ; sig_dre2ibtt_eop <= sig_dre2ibtt_tlast ; -- use skid buffered version -- Cant't detect undrrun/overrun here sig_realign2wdc_eop_error <= '0'; ENABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '1' generate begin ------------------------------------------------------------ -- Instance: I_NO_REALIGN_SKID_BUF -- -- Description: -- Instance for a Skid Buffer which provides for -- Fmax timing improvement between the Null Absorber and -- the Write Data controller when the Realigner is not -- present (no DRE and no Store and Forward case). -- ------------------------------------------------------------ I_NO_REALIGN_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => LOGIC_LOW , -- Slave Side (Null Absorber Input) s_valid => skid2dre_wvalid , s_ready => dre2skid_wready , s_data => skid2dre_wdata , s_strb => skid2dre_wstrb , s_last => skid2dre_wlast , -- Master Side (Stream Data Output to WData Cntlr) m_valid => sig_dre2ibtt_tvalid , m_ready => sig_ibtt2dre_tready , m_data => sig_dre2ibtt_tdata , m_strb => sig_dre2ibtt_tstrb , m_last => sig_dre2ibtt_tlast ); end generate ENABLE_NOREALIGNER_SKID; DISABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '0' generate begin sig_dre2ibtt_tvalid <= skid2dre_wvalid; dre2skid_wready <= sig_ibtt2dre_tready; sig_dre2ibtt_tdata <= skid2dre_wdata; sig_dre2ibtt_tstrb <= skid2dre_wstrb; sig_dre2ibtt_tlast <= skid2dre_wlast; end generate DISABLE_NOREALIGNER_SKID; end generate GEN_NO_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_REALIGNER -- -- If Generate Description: -- Include the S2MM realigner Module. It hosts the S2MM DRE -- and the Scatter Block. -- -- Note that the General Purpose Store and Forward Module -- needs the Scatter function to detect input overrun and -- underrun events on the AXI Stream input. Thus the Realigner -- is included whenever the GP Store and Forward is enabled. -- ------------------------------------------------------------ GEN_INCLUDE_REALIGNER : if (ADD_REALIGNER = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_REALIGNER -- -- Description: -- Instance for the S2MM Data Realignment Module. -- ------------------------------------------------------------ I_S2MM_REALIGNER : entity axi_datamover_v5_1.axi_datamover_s2mm_realign generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_INCLUDE_DRE => INCLUDE_S2MM_DRE , C_DRE_CNTL_FIFO_DEPTH => DRE_CNTL_FIFO_DEPTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SUPPORT_SCATTER => DRE_SUPPORT_SCATTER , C_BTT_USED => S2MM_BTT_USED , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , -- Write Data Controller or Store and Forward I/O ------- wdc2dre_wready => sig_ibtt2dre_tready , dre2wdc_wvalid => sig_dre2ibtt_tvalid , dre2wdc_wdata => sig_dre2ibtt_tdata , dre2wdc_wstrb => sig_dre2ibtt_tstrb , dre2wdc_wlast => sig_dre2ibtt_tlast , dre2wdc_eop => sig_dre2ibtt_eop , -- Starting offset output ------------------------------- dre2sf_strt_offset => sig_sf_strt_addr_offset , -- AXI Slave Stream In ----------------------------------- s2mm_strm_wready => dre2skid_wready , s2mm_strm_wvalid => skid2dre_wvalid , s2mm_strm_wdata => skid2dre_wdata , s2mm_strm_wstrb => skid2dre_wstrb , s2mm_strm_wlast => skid2dre_wlast , -- Command Calculator Interface -------------------------- dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset , -- Premature TLAST assertion error flag dre2all_tlast_error => sig_realign2wdc_eop_error , -- DRE Halted Status dre2all_halted => sig_dre2all_halted ); end generate GEN_INCLUDE_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT_SF -- -- If Generate Description: -- Include the Indeterminate BTT Logic with specialized -- Store and Forward function, This also requires the -- Scatter Engine in the Realigner module. -- -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT_SF : if (ENABLE_INDET_BTT_SF = 1) generate begin -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; ------------------------------------------------------------ -- Instance: I_INDET_BTT -- -- Description: -- Instance for the Indeterminate BTT with Store and Forward -- module. -- ------------------------------------------------------------ I_INDET_BTT : entity axi_datamover_v5_1.axi_datamover_indet_btt generic map ( C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_IBTT_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_ENABLE_DRE => INCLUDE_S2MM_DRE , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , ibtt2wdc_stbs_asserted => sig_ibtt2wdc_stbs_asserted, ibtt2wdc_eop => sig_ibtt2wdc_eop , ibtt2wdc_tdata => sig_ibtt2wdc_tdata , ibtt2wdc_tstrb => sig_ibtt2wdc_tstrb , ibtt2wdc_tlast => sig_ibtt2wdc_tlast , ibtt2wdc_tvalid => sig_ibtt2wdc_tvalid , wdc2ibtt_tready => sig_wdc2ibtt_tready , dre2ibtt_tvalid => sig_dre2ibtt_tvalid , ibtt2dre_tready => sig_ibtt2dre_tready , dre2ibtt_tdata => sig_dre2ibtt_tdata , dre2ibtt_tstrb => sig_dre2ibtt_tstrb , dre2ibtt_tlast => sig_dre2ibtt_tlast , dre2ibtt_eop => sig_dre2ibtt_eop , dre2ibtt_strt_addr_offset => sig_sf_strt_addr_offset , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes ); end generate GEN_ENABLE_INDET_BTT_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_SF -- -- If Generate Description: -- Bypasses any store and Forward functions. -- -- ------------------------------------------------------------ GEN_NO_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 0) generate begin -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; -- Housekeep unused signal in this case sig_ok_to_post_wr_addr <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; -- Just pass DRE signals through sig_ibtt2dre_tready <= sig_wdc2ibtt_tready ; sig_ibtt2wdc_tvalid <= sig_dre2ibtt_tvalid ; sig_ibtt2wdc_tdata <= sig_dre2ibtt_tdata ; sig_ibtt2wdc_tstrb <= sig_dre2ibtt_tstrb ; sig_ibtt2wdc_tlast <= sig_dre2ibtt_tlast ; sig_ibtt2wdc_eop <= sig_dre2ibtt_eop ; sig_ibtt2wdc_stbs_asserted <= (others => '0') ; -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; end generate GEN_NO_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_GP_SF -- -- If Generate Description: -- Include the General Purpose Store and Forward module. -- This If Generate can only be enabled when -- Indeterminate BTT mode is not enabled. The General Purpose -- Store and Forward is instantiated in place of the Indet -- BTT Store and Forward. -- ------------------------------------------------------------ GEN_INCLUDE_GP_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 1) generate begin -- Merge the external address posting control with the -- SF address posting control. sig_s2mm_allow_addr_req <= s2mm_allow_addr_req and sig_ok_to_post_wr_addr ; -- Zero these out since Indet BTT is not enabled, they -- are only used by the WDC in that mode sig_ibtt2wdc_stbs_asserted <= (others => '0') ; sig_ibtt2wdc_eop <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; ------------------------------------------------------------ -- Instance: I_S2MM_GP_SF -- -- Description: -- Instance for the S2MM (Write) General Purpose Store and -- Forward Module. This module can only be enabled when -- Indeterminate BTT mode is not enabled. It is connected -- in place of the IBTT Module when GP SF is enabled. -- ------------------------------------------------------------ I_S2MM_GP_SF : entity axi_datamover_v5_1.axi_datamover_wr_sf generic map ( C_WR_ADDR_PIPE_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset inputs ----------------------------- aclk => s2mm_aclk , reset => sig_mmap_rst , -- Slave Stream Input -------------------------------- sf2sin_tready => sig_ibtt2dre_tready , sin2sf_tvalid => sig_dre2ibtt_tvalid , sin2sf_tdata => sig_dre2ibtt_tdata , sin2sf_tkeep => sig_dre2ibtt_tstrb , sin2sf_tlast => sig_dre2ibtt_tlast , sin2sf_error => sig_realign2wdc_eop_error , -- Starting Address Offset Input --------------------- sin2sf_strt_addr_offset => sig_sf_strt_addr_offset , -- DataMover Write Side Address Pipelining Control Interface -------- ok_to_post_wr_addr => sig_ok_to_post_wr_addr , wr_addr_posted => sig_s2mm_addr_req_posted , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , wr_ld_nxt_len => sig_s2mm_ld_nxt_len , wr_len => sig_s2mm_wr_len , -- Write Side Stream Out to DataMover S2MM ------------- sout2sf_tready => sig_wdc2ibtt_tready , sf2sout_tvalid => sig_ibtt2wdc_tvalid , sf2sout_tdata => sig_ibtt2wdc_tdata , sf2sout_tkeep => sig_ibtt2wdc_tstrb , sf2sout_tlast => sig_ibtt2wdc_tlast , sf2sout_error => sig_ibtt2wdc_error ); end generate GEN_INCLUDE_GP_SF; ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl generic map ( C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_ADDR_ID => S2MM_AWID_VALUE , C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => s2mm_awid , addr2axi_aaddr => s2mm_awaddr , addr2axi_alen => s2mm_awlen , addr2axi_asize => s2mm_awsize , addr2axi_aburst => s2mm_awburst , addr2axi_aprot => s2mm_awprot , addr2axi_avalid => s2mm_awvalid , addr2axi_acache => s2mm_awcache_int , addr2axi_auser => s2mm_awuser_int , axi2addr_aready => s2mm_awready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , -- mstr2addr_cache_info => sig_cache2mstr_command , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => sig_s2mm_allow_addr_req , addr_req_posted => sig_s2mm_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2wsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_WR_DATA_CNTL -- -- Description: -- Write Data Controller Block -- ------------------------------------------------------------ I_WR_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_wrdata_cntl generic map ( C_REALIGNER_INCLUDED => ADD_REALIGNER , C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len , s2mm_wr_len => sig_s2mm_wr_len , data2skid_saddr_lsb => sig_data2skid_addr_lsb , data2skid_wdata => sig_data2skid_wdata , data2skid_wstrb => sig_data2skid_wstrb , data2skid_wlast => sig_data2skid_wlast , data2skid_wvalid => sig_data2skid_wvalid , skid2data_wready => sig_skid2data_wready , s2mm_strm_wvalid => sig_ibtt2wdc_tvalid , s2mm_strm_wready => sig_wdc2ibtt_tready , s2mm_strm_wdata => sig_ibtt2wdc_tdata , s2mm_strm_wstrb => sig_ibtt2wdc_tstrb , s2mm_strm_wlast => sig_ibtt2wdc_tlast , s2mm_strm_eop => sig_ibtt2wdc_eop , s2mm_stbs_asserted => sig_ibtt2wdc_stbs_asserted, realign2wdc_eop_error => sig_ibtt2wdc_error , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2all_tlast_error => sig_data2all_tlast_error , data2all_dcntlr_halted => sig_data2all_dcntlr_halted, data2skid_halt => sig_data2skid_halt , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_err => sig_data2wsc_calc_err , data2wsc_last_err => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , wsc2data_ready => sig_wsc2data_ready , data2wsc_valid => sig_data2wsc_valid , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); --ENABLE_AXIMMAP_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate --begin ------------------------------------------------------------ -- Instance: I_S2MM_MMAP_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registered outputs and supports bi-dir throttling. -- -- This Module also provides Write Data Bus Mirroring and WSTRB -- Demuxing to match a narrow Stream to a wider MMap Write -- Channel. By doing this in the skid buffer, the resource -- utilization of the skid buffer can be minimized by only -- having to buffer/mux the Stream data width, not the MMap -- Data width. -- ------------------------------------------------------------ I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid2mm_buf generic map ( C_MDATA_WIDTH => S2MM_MDATA_WIDTH , C_SDATA_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH ) port map ( -- System Ports ACLK => s2mm_aclk , ARST => sig_stream_rst , -- Slave Side (Wr Data Controller Input Side ) S_ADDR_LSB => sig_data2skid_addr_lsb, S_VALID => sig_data2skid_wvalid , S_READY => sig_skid2data_wready , S_Data => sig_data2skid_wdata , S_STRB => sig_data2skid_wstrb , S_Last => sig_data2skid_wlast , -- Master Side (MMap Write Data Output Side) M_VALID => sig_skid2axi_wvalid , M_READY => sig_axi2skid_wready , M_Data => sig_skid2axi_wdata , M_STRB => sig_skid2axi_wstrb , M_Last => sig_skid2axi_wlast ); --end generate ENABLE_AXIMMAP_SKID; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/FIFO_image_filter_img_0_data_stream_1_V.vhd	4	4629	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_img_0_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_img_0_data_stream_1_V_shiftReg; architecture rtl of FIFO_image_filter_img_0_data_stream_1_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_img_0_data_stream_1_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_img_0_data_stream_1_V is component FIFO_image_filter_img_0_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_img_0_data_stream_1_V_shiftReg : FIFO_image_filter_img_0_data_stream_1_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_skid_buf.vhd	12	16812	-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_skid_buf.vhd -- -- Description: -- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- entity axi_dma_skid_buf is generic ( C_WDATA_WIDTH : INTEGER range 8 to 256 := 32 -- Width of the Stream Data bus (in bits) ); port ( -- System Ports ACLK : In std_logic ; -- ARST : In std_logic ; -- -- -- Shutdown control (assert for 1 clk pulse) -- skid_stop : In std_logic ; -- -- Slave Side (Stream Data Input) -- S_VALID : In std_logic ; -- S_READY : Out std_logic ; -- S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); -- S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); -- S_Last : In std_logic ; -- -- -- Master Side (Stream Data Output -- M_VALID : Out std_logic ; -- M_READY : In std_logic ; -- M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); -- M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); -- M_Last : Out std_logic -- ); end entity axi_dma_skid_buf; architecture implementation of axi_dma_skid_buf is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Signals decalrations ------------------------- Signal sig_reset_reg : std_logic := '0'; signal sig_spcl_s_ready_set : std_logic := '0'; signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_skid_reg : std_logic := '0'; signal sig_skid_reg_en : std_logic := '0'; signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_skid_mux_out : std_logic := '0'; signal sig_skid_mux_sel : std_logic := '0'; signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_reg_out : std_logic := '0'; signal sig_data_reg_out_en : std_logic := '0'; signal sig_m_valid_out : std_logic := '0'; signal sig_m_valid_dup : std_logic := '0'; signal sig_m_valid_comb : std_logic := '0'; signal sig_s_ready_out : std_logic := '0'; signal sig_s_ready_dup : std_logic := '0'; signal sig_s_ready_comb : std_logic := '0'; signal sig_stop_request : std_logic := '0'; signal sig_stopped : std_logic := '0'; signal sig_sready_stop : std_logic := '0'; signal sig_sready_stop_reg : std_logic := '0'; signal sig_s_last_xfered : std_logic := '0'; signal sig_m_last_xfered : std_logic := '0'; signal sig_mvalid_stop_reg : std_logic := '0'; signal sig_mvalid_stop : std_logic := '0'; signal sig_slast_with_stop : std_logic := '0'; signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0'); -- Register duplication attribute assignments to control fanout -- on handshake output signals Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no"; begin --(architecture implementation) M_VALID <= sig_m_valid_out; S_READY <= sig_s_ready_out; M_STRB <= sig_strb_reg_out; M_Last <= sig_last_reg_out; M_Data <= sig_data_reg_out; -- Special shutdown logic version od Slast. -- A halt request forces a tlast through the skig buffer sig_slast_with_stop <= s_last or sig_stop_request; sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask; -- Assign the special S_READY FLOP set signal sig_spcl_s_ready_set <= sig_reset_reg; -- Generate the ouput register load enable control sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup); -- Generate the skid input register load enable control sig_skid_reg_en <= sig_s_ready_dup; -- Generate the skid mux select control sig_skid_mux_sel <= not(sig_s_ready_dup); -- Skid Mux sig_data_skid_mux_out <= sig_data_skid_reg When (sig_skid_mux_sel = '1') Else S_Data; sig_strb_skid_mux_out <= sig_strb_skid_reg When (sig_skid_mux_sel = '1') Else sig_sstrb_with_stop; sig_last_skid_mux_out <= sig_last_skid_reg When (sig_skid_mux_sel = '1') Else sig_slast_with_stop; -- m_valid combinational logic sig_m_valid_comb <= S_VALID or (sig_m_valid_dup and (not(sig_s_ready_dup) or not(M_READY))); -- s_ready combinational logic sig_s_ready_comb <= M_READY or (sig_s_ready_dup and (not(sig_m_valid_dup) or not(S_VALID))); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_THE_RST -- -- Process Description: -- Register input reset -- ------------------------------------------------------------- REG_THE_RST : process (ACLK) begin if (ACLK'event and ACLK = '1') then sig_reset_reg <= ARST; end if; end process REG_THE_RST; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: S_READY_FLOP -- -- Process Description: -- Registers S_READY handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- S_READY_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1' or sig_sready_stop = '1') then -- Special stop condition sig_s_ready_out <= '0'; sig_s_ready_dup <= '0'; Elsif (sig_spcl_s_ready_set = '1') Then sig_s_ready_out <= '1'; sig_s_ready_dup <= '1'; else sig_s_ready_out <= sig_s_ready_comb; sig_s_ready_dup <= sig_s_ready_comb; end if; end if; end process S_READY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: M_VALID_FLOP -- -- Process Description: -- Registers M_VALID handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- M_VALID_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1' or sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA sig_mvalid_stop = '1') then -- Special stop condition sig_m_valid_out <= '0'; sig_m_valid_dup <= '0'; else sig_m_valid_out <= sig_m_valid_comb; sig_m_valid_dup <= sig_m_valid_comb; end if; end if; end process M_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_REG -- -- Process Description: -- This process implements the output registers for the -- Skid Buffer Data signals -- ------------------------------------------------------------- SKID_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_data_skid_reg <= (others => '0'); sig_strb_skid_reg <= (others => '0'); sig_last_skid_reg <= '0'; elsif (sig_skid_reg_en = '1') then sig_data_skid_reg <= S_Data; sig_strb_skid_reg <= sig_sstrb_with_stop; sig_last_skid_reg <= sig_slast_with_stop; else null; -- hold current state end if; end if; end process SKID_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_REG -- -- Process Description: -- This process implements the output registers for the -- Skid Buffer Data signals -- ------------------------------------------------------------- OUTPUT_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1' or sig_mvalid_stop_reg = '1') then --sig_data_reg_out <= (others => '0'); -- CR585409 sig_strb_reg_out <= (others => '0'); sig_last_reg_out <= '0'; elsif (sig_data_reg_out_en = '1') then --sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409 sig_strb_reg_out <= sig_strb_skid_mux_out; sig_last_reg_out <= sig_last_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_REG; -- CR585409 - To lower reset fanout and improve FPGA fmax timing -- resets have been removed from AXI Stream data buses DATA_OUTPUT_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (sig_data_reg_out_en = '1') then sig_data_reg_out <= sig_data_skid_mux_out; else null; -- hold current state end if; end if; end process DATA_OUTPUT_REG; -------- Special Stop Logic -------------------------------------- sig_s_last_xfered <= sig_s_ready_dup and s_valid and sig_slast_with_stop; sig_sready_stop <= (sig_s_last_xfered and sig_stop_request) or sig_sready_stop_reg; sig_m_last_xfered <= sig_m_valid_dup and m_ready and sig_last_reg_out; sig_mvalid_stop <= (sig_m_last_xfered and sig_stop_request) or sig_mvalid_stop_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_STOP_REQ_FLOP -- -- Process Description: -- This process implements the Stop request flop. It is a -- sample and hold register that can only be cleared by reset. -- ------------------------------------------------------------- IMP_STOP_REQ_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_stop_request <= '0'; sig_sstrb_stop_mask <= (others => '0'); elsif (skid_stop = '1') then sig_stop_request <= '1'; sig_sstrb_stop_mask <= (others => '1'); else null; -- hold current state end if; end if; end process IMP_STOP_REQ_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CLR_SREADY_FLOP -- -- Process Description: -- This process implements the flag to clear the s_ready -- flop at a stop condition. -- ------------------------------------------------------------- IMP_CLR_SREADY_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_sready_stop_reg <= '0'; elsif (sig_s_last_xfered = '1' and sig_stop_request = '1') then sig_sready_stop_reg <= '1'; else null; -- hold current state end if; end if; end process IMP_CLR_SREADY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CLR_MREADY_FLOP -- -- Process Description: -- This process implements the flag to clear the m_ready -- flop at a stop condition. -- ------------------------------------------------------------- IMP_CLR_MVALID_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_mvalid_stop_reg <= '0'; elsif (sig_m_last_xfered = '1' and sig_stop_request = '1') then sig_mvalid_stop_reg <= '1'; else null; -- hold current state end if; end if; end process IMP_CLR_MVALID_FLOP; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/checkbit_handler.vhd	7	25695	------------------------------------------------------------------------------- -- checkbit_handler.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: checkbit_handler.vhd -- -- Description: Generates the ECC checkbits for the input vector of data bits. -- -- VHDL-Standard: VHDL'93/02 ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- \| -- \|-- full_axi.vhd -- \| -- sng_port_arb.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- wr_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- \| -- rd_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- \|-- axi_lite.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity checkbit_handler is generic ( C_ENCODE : boolean := true; C_USE_LUT6 : boolean := true ); port ( DataIn : in std_logic_vector(0 to 31); --- changed from 31 downto 0 to 0 to 31 to make it compatabile with LMB Controller's hamming code. CheckIn : in std_logic_vector(0 to 6); CheckOut : out std_logic_vector(0 to 6); Syndrome : out std_logic_vector(0 to 6); Syndrome_4 : out std_logic_vector (0 to 1); Syndrome_6 : out std_logic_vector (0 to 5); Syndrome_Chk : in std_logic_vector (0 to 6); Enable_ECC : in std_logic; UE_Q : in std_logic; CE_Q : in std_logic; UE : out std_logic; CE : out std_logic ); end entity checkbit_handler; library unisim; use unisim.vcomponents.all; architecture IMP of checkbit_handler is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; component XOR18 is generic ( C_USE_LUT6 : boolean); port ( InA : in std_logic_vector(0 to 17); res : out std_logic); end component XOR18; component Parity is generic ( C_USE_LUT6 : boolean; C_SIZE : integer); port ( InA : in std_logic_vector(0 to C_SIZE - 1); Res : out std_logic); end component Parity; signal data_chk0 : std_logic_vector(0 to 17); signal data_chk1 : std_logic_vector(0 to 17); signal data_chk2 : std_logic_vector(0 to 17); signal data_chk3 : std_logic_vector(0 to 14); signal data_chk4 : std_logic_vector(0 to 14); signal data_chk5 : std_logic_vector(0 to 5); begin -- architecture IMP data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) & DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) & DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30); data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) & DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) & DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31); data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31); data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25); data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25); data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31); -- Encode bits for writing data Encode_Bits : if (C_ENCODE) generate signal data_chk3_i : std_logic_vector(0 to 17); signal data_chk4_i : std_logic_vector(0 to 17); signal data_chk6 : std_logic_vector(0 to 17); begin ------------------------------------------------------------------------------------------------ -- Checkbit 0 built up using XOR18 ------------------------------------------------------------------------------------------------ XOR18_I0 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk0, -- [in std_logic_vector(0 to 17)] res => CheckOut(0)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 1 built up using XOR18 ------------------------------------------------------------------------------------------------ XOR18_I1 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk1, -- [in std_logic_vector(0 to 17)] res => CheckOut(1)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 2 built up using XOR18 ------------------------------------------------------------------------------------------------ XOR18_I2 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk2, -- [in std_logic_vector(0 to 17)] res => CheckOut(2)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 3 built up using XOR18 ------------------------------------------------------------------------------------------------ data_chk3_i <= data_chk3 & "000"; XOR18_I3 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk3_i, -- [in std_logic_vector(0 to 17)] res => CheckOut(3)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 4 built up using XOR18 ------------------------------------------------------------------------------------------------ data_chk4_i <= data_chk4 & "000"; XOR18_I4 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk4_i, -- [in std_logic_vector(0 to 17)] res => CheckOut(4)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 5 built up from 1 LUT6 ------------------------------------------------------------------------------------------------ Parity_chk5_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => CheckOut(5)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 6 built up from 3 LUT7 and 4 LUT6 ------------------------------------------------------------------------------------------------ data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) & DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29); XOR18_I6 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk6, -- [in std_logic_vector(0 to 17)] res => CheckOut(6)); -- [out std_logic] end generate Encode_Bits; -------------------------------------------------------------------------------------------------- -- Decode bits to get syndrome and UE/CE signals -------------------------------------------------------------------------------------------------- Decode_Bits : if (not C_ENCODE) generate signal syndrome_i : std_logic_vector(0 to 6) := (others => '0'); signal chk0_1 : std_logic_vector(0 to 3); signal chk1_1 : std_logic_vector(0 to 3); signal chk2_1 : std_logic_vector(0 to 3); signal data_chk3_i : std_logic_vector(0 to 15); signal chk3_1 : std_logic_vector(0 to 1); signal data_chk4_i : std_logic_vector(0 to 15); signal chk4_1 : std_logic_vector(0 to 1); signal data_chk5_i : std_logic_vector(0 to 6); signal data_chk6 : std_logic_vector(0 to 38); signal chk6_1 : std_logic_vector(0 to 5); signal syndrome_0_to_2 : std_logic_vector (0 to 2); signal syndrome_3_to_5 : std_logic_vector (3 to 5); signal syndrome_3_to_5_multi : std_logic; signal syndrome_3_to_5_zero : std_logic; signal ue_i_0 : std_logic; signal ue_i_1 : std_logic; begin ------------------------------------------------------------------------------------------------ -- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4 ------------------------------------------------------------------------------------------------ chk0_1(3) <= CheckIn(0); Parity_chk0_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(0)); -- [out std_logic] Parity_chk0_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(1)); -- [out std_logic] Parity_chk0_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(2)); -- [out std_logic] Parity_chk0_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4) port map ( InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(0)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4 ------------------------------------------------------------------------------------------------ chk1_1(3) <= CheckIn(1); Parity_chk1_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(0)); -- [out std_logic] Parity_chk1_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(1)); -- [out std_logic] Parity_chk1_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(2)); -- [out std_logic] Parity_chk1_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4) port map ( InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(1)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4 ------------------------------------------------------------------------------------------------ chk2_1(3) <= CheckIn(2); Parity_chk2_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(0)); -- [out std_logic] Parity_chk2_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(1)); -- [out std_logic] Parity_chk2_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(2)); -- [out std_logic] Parity_chk2_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4) port map ( InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(2)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2 ------------------------------------------------------------------------------------------------ data_chk3_i <= data_chk3 & CheckIn(3); Parity_chk3_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk3_1(0)); -- [out std_logic] Parity_chk3_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk3_1(1)); -- [out std_logic] -- For improved timing, remove Enable_ECC signal in this LUT level Parity_chk3_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2) port map ( InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(3)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2 ------------------------------------------------------------------------------------------------ data_chk4_i <= data_chk4 & CheckIn(4); Parity_chk4_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk4_1(0)); -- [out std_logic] Parity_chk4_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk4_1(1)); -- [out std_logic] -- Set bit 4 output with default. Real ECC XOR value will be determined post register -- stage. syndrome_i (4) <= '0'; -- For improved timing, move last LUT level XOR to next side of pipeline -- stage in read path. Syndrome_4 <= chk4_1; ------------------------------------------------------------------------------------------------ -- Syndrome bit 5 built up from 1 LUT7 ------------------------------------------------------------------------------------------------ data_chk5_i <= data_chk5 & CheckIn(5); Parity_chk5_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(5)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6 ------------------------------------------------------------------------------------------------ data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) & CheckIn(1) & CheckIn(0) & CheckIn(6); Parity_chk6_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(0)); -- [out std_logic] Parity_chk6_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(1)); -- [out std_logic] Parity_chk6_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(2)); -- [out std_logic] Parity_chk6_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(3)); -- [out std_logic] Parity_chk6_5 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(4)); -- [out std_logic] Parity_chk6_6 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(5)); -- [out std_logic] -- No internal use for MSB of syndrome (it is created after the -- register stage, outside of this block) syndrome_i(6) <= '0'; Syndrome <= syndrome_i; -- (N:0) <= (0:N) -- Bring out seperate output to do final XOR stage on Syndrome (6) after -- the pipeline stage. Syndrome_6 <= chk6_1 (0 to 5); --------------------------------------------------------------------------- -- With final syndrome registered outside this module for pipeline balancing -- Use registered syndrome to generate any error flags. -- Use input signal, Syndrome_Chk which is the registered Syndrome used to -- correct any single bit errors. syndrome_0_to_2 <= Syndrome_Chk(0) & Syndrome_Chk(1) & Syndrome_Chk(2); syndrome_3_to_5 <= Syndrome_Chk(3) & Syndrome_Chk(4) & Syndrome_Chk(5); syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0'; syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or syndrome_3_to_5 = "011" or syndrome_3_to_5 = "101") else '0'; -- Ensure that CE flag is only asserted for a single clock cycle (and does not keep -- registered output value) CE <= (Enable_ECC and Syndrome_Chk(6)) when (syndrome_3_to_5_multi = '0') else '0'; -- Similar edit from CE flag. Ensure that UE flags are only asserted for a single -- clock cycle. The flags are registered outside this module for detection in -- register module. ue_i_0 <= Enable_ECC when (syndrome_3_to_5_zero = '0') or (syndrome_0_to_2 /= "000") else '0'; ue_i_1 <= Enable_ECC and (syndrome_3_to_5_multi); Use_LUT6: if (C_USE_LUT6) generate begin UE_MUXF7 : MUXF7 port map ( I0 => ue_i_0, I1 => ue_i_1, S => Syndrome_Chk(6), O => UE); end generate Use_LUT6; Use_RTL: if (not C_USE_LUT6) generate begin UE <= ue_i_1 when Syndrome_Chk(6) = '1' else ue_i_0; end generate Use_RTL; end generate Decode_Bits; end architecture IMP;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/daf00b91/hdl/src/vhdl/axi_lite_ipif.vhd	16	14520	------------------------------------------------------------------- -- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------------- -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: axi_lite_ipif.vhd -- Version: v2.0 -- Description: This is the top level design file for the axi_lite_ipif -- function. It provides a standardized slave interface -- between the IP and the AXI. This version supports -- single read/write transfers only. It does not provide -- address pipelining or simultaneous read and write -- operations. ------------------------------------------------------------------------------- -- Structure: This section shows the hierarchical structure of axi_lite_ipif. -- -- --axi_lite_ipif.vhd -- --slave_attachment.vhd -- --address_decoder.vhd ------------------------------------------------------------------------------- -- Author: BSB -- -- History: -- -- BSB 05/20/10 -- First version -- ~~~~~~ -- - Created the first version v1.00.a -- ^^^^^^ -- ~~~~~~ -- SK 06/09/10 -- v1.01.a -- 1. updated to reduce the utilization -- Closed CR #574507 -- 2. Optimized the state machine code -- 3. Optimized the address decoder logic to generate the CE's with common logic -- 4. Address GAP decoding logic is removed and timeout counter is made active -- for all transactions. -- ^^^^^^ -- ~~~~~~ -- SK 12/16/12 -- v2.0 -- 1. up reved to major version for 2013.1 Vivado release. No logic updates. -- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format -- 3. updated the proc common version to proc_common_base_v5_0 -- 4. No Logic Updates -- ^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; --library proc_common_base_v5_0; --use proc_common_base_v5_0.ipif_pkg.all; library axi_lite_ipif_v3_0; use axi_lite_ipif_v3_0.ipif_pkg.all; ------------------------------------------------------------------------------- -- Definition of Generics ------------------------------------------------------------------------------- -- C_S_AXI_DATA_WIDTH -- AXI data bus width -- C_S_AXI_ADDR_WIDTH -- AXI address bus width -- C_S_AXI_MIN_SIZE -- Minimum address range of the IP -- C_USE_WSTRB -- Use write strobs or not -- C_DPHASE_TIMEOUT -- Data phase time out counter -- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range -- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range -- C_FAMILY -- Target FPGA family ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- -- S_AXI_ACLK -- AXI Clock -- S_AXI_ARESETN -- AXI Reset -- S_AXI_AWADDR -- AXI Write address -- S_AXI_AWVALID -- Write address valid -- S_AXI_AWREADY -- Write address ready -- S_AXI_WDATA -- Write data -- S_AXI_WSTRB -- Write strobes -- S_AXI_WVALID -- Write valid -- S_AXI_WREADY -- Write ready -- S_AXI_BRESP -- Write response -- S_AXI_BVALID -- Write response valid -- S_AXI_BREADY -- Response ready -- S_AXI_ARADDR -- Read address -- S_AXI_ARVALID -- Read address valid -- S_AXI_ARREADY -- Read address ready -- S_AXI_RDATA -- Read data -- S_AXI_RRESP -- Read response -- S_AXI_RVALID -- Read valid -- S_AXI_RREADY -- Read ready -- Bus2IP_Clk -- Synchronization clock provided to User IP -- Bus2IP_Reset -- Active high reset for use by the User IP -- Bus2IP_Addr -- Desired address of read or write operation -- Bus2IP_RNW -- Read or write indicator for the transaction -- Bus2IP_BE -- Byte enables for the data bus -- Bus2IP_CS -- Chip select for the transcations -- Bus2IP_RdCE -- Chip enables for the read -- Bus2IP_WrCE -- Chip enables for the write -- Bus2IP_Data -- Write data bus to the User IP -- IP2Bus_Data -- Input Read Data bus from the User IP -- IP2Bus_WrAck -- Active high Write Data qualifier from the IP -- IP2Bus_RdAck -- Active high Read Data qualifier from the IP -- IP2Bus_Error -- Error signal from the IP ------------------------------------------------------------------------------- entity axi_lite_ipif is generic ( C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; C_USE_WSTRB : integer := 0; C_DPHASE_TIMEOUT : integer range 0 to 512 := 8; C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used ( X"0000_0000_7000_0000", -- IP user0 base address X"0000_0000_7000_00FF", -- IP user0 high address X"0000_0000_7000_0100", -- IP user1 base address X"0000_0000_7000_01FF" -- IP user1 high address ); C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used ( 4, -- User0 CE Number 12 -- User1 CE Number ); C_FAMILY : string := "virtex6" ); port ( --System signals S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector ((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- Controls to the IP/IPIF modules Bus2IP_Clk : out std_logic; Bus2IP_Resetn : out std_logic; Bus2IP_Addr : out std_logic_vector ((C_S_AXI_ADDR_WIDTH-1) downto 0); Bus2IP_RNW : out std_logic; Bus2IP_BE : out std_logic_vector (((C_S_AXI_DATA_WIDTH/8)-1) downto 0); Bus2IP_CS : out std_logic_vector (((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0); Bus2IP_RdCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0); Bus2IP_WrCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0); Bus2IP_Data : out std_logic_vector ((C_S_AXI_DATA_WIDTH-1) downto 0); IP2Bus_Data : in std_logic_vector ((C_S_AXI_DATA_WIDTH-1) downto 0); IP2Bus_WrAck : in std_logic; IP2Bus_RdAck : in std_logic; IP2Bus_Error : in std_logic ); end axi_lite_ipif; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture imp of axi_lite_ipif is ---------------------------------------------------------------------------------- -- below attributes are added to reduce the synth warnings in Vivado tool attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ---------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Slave Attachment ------------------------------------------------------------------------------- I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0.slave_attachment generic map( C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH, C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, C_FAMILY => C_FAMILY ) port map( -- AXI signals S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_RREADY => S_AXI_RREADY, -- IPIC signals Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Resetn => Bus2IP_Resetn, Bus2IP_Addr => Bus2IP_Addr, Bus2IP_RNW => Bus2IP_RNW, Bus2IP_BE => Bus2IP_BE, Bus2IP_CS => Bus2IP_CS, Bus2IP_RdCE => Bus2IP_RdCE, Bus2IP_WrCE => Bus2IP_WrCE, Bus2IP_Data => Bus2IP_Data, IP2Bus_Data => IP2Bus_Data, IP2Bus_WrAck => IP2Bus_WrAck, IP2Bus_RdAck => IP2Bus_RdAck, IP2Bus_Error => IP2Bus_Error ); end imp;	gpl-3.0
mistryalok/Zedboard	learning/training/my/adder/hls/adder/solution1/syn/vhdl/adder_AXI_CTRL_s_axi.vhd	1	13809	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity adder_AXI_CTRL_s_axi is generic ( C_ADDR_WIDTH : INTEGER := 6; C_DATA_WIDTH : INTEGER := 32); port ( -- axi4 lite slave signals ACLK :in STD_LOGIC; ARESET :in STD_LOGIC; ACLK_EN :in STD_LOGIC; AWADDR :in STD_LOGIC_VECTOR(C_ADDR_WIDTH-1 downto 0); AWVALID :in STD_LOGIC; AWREADY :out STD_LOGIC; WDATA :in STD_LOGIC_VECTOR(C_DATA_WIDTH-1 downto 0); WSTRB :in STD_LOGIC_VECTOR(C_DATA_WIDTH/8-1 downto 0); WVALID :in STD_LOGIC; WREADY :out STD_LOGIC; BRESP :out STD_LOGIC_VECTOR(1 downto 0); BVALID :out STD_LOGIC; BREADY :in STD_LOGIC; ARADDR :in STD_LOGIC_VECTOR(C_ADDR_WIDTH-1 downto 0); ARVALID :in STD_LOGIC; ARREADY :out STD_LOGIC; RDATA :out STD_LOGIC_VECTOR(C_DATA_WIDTH-1 downto 0); RRESP :out STD_LOGIC_VECTOR(1 downto 0); RVALID :out STD_LOGIC; RREADY :in STD_LOGIC; interrupt :out STD_LOGIC; -- user signals ap_start :out STD_LOGIC; ap_done :in STD_LOGIC; ap_ready :in STD_LOGIC; ap_idle :in STD_LOGIC; a :out STD_LOGIC_VECTOR(31 downto 0); b :out STD_LOGIC_VECTOR(31 downto 0); c :in STD_LOGIC_VECTOR(31 downto 0); c_ap_vld :in STD_LOGIC); end entity adder_AXI_CTRL_s_axi; --------------------------Address Info------------------- -- 0x00 : Control signals -- bit 0 - ap_start (Read/Write/SC) -- bit 1 - ap_done (Read/COR) -- bit 2 - ap_idle (Read) -- bit 3 - ap_ready (Read) -- bit 7 - auto_restart (Read/Write) -- others - reserved -- 0x04 : Global Interrupt Enable Register -- bit 0 - Global Interrupt Enable (Read/Write) -- others - reserved -- 0x08 : IP Interrupt Enable Register (Read/Write) -- bit 0 - Channel 0 (ap_done) -- others - reserved -- 0x0c : IP Interrupt Status Register (Read/TOW) -- bit 0 - Channel 0 (ap_done) -- others - reserved -- 0x10 : Data signal of a -- bit 31~0 - a[31:0] (Read/Write) -- 0x14 : reserved -- 0x18 : Data signal of b -- bit 31~0 - b[31:0] (Read/Write) -- 0x1c : reserved -- 0x20 : Data signal of c -- bit 31~0 - c[31:0] (Read) -- 0x24 : Control signal of c -- bit 0 - c_ap_vld (Read/COR) -- others - reserved -- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) architecture behave of adder_AXI_CTRL_s_axi is constant ADDR_BITS : INTEGER := 6; constant ADDR_AP_CTRL : INTEGER :=16#00#; constant ADDR_GIE : INTEGER :=16#04#; constant ADDR_IER : INTEGER :=16#08#; constant ADDR_ISR : INTEGER :=16#0c#; constant ADDR_A_DATA_0 : INTEGER :=16#10#; constant ADDR_A_CTRL : INTEGER :=16#14#; constant ADDR_B_DATA_0 : INTEGER :=16#18#; constant ADDR_B_CTRL : INTEGER :=16#1c#; constant ADDR_C_DATA_0 : INTEGER :=16#20#; constant ADDR_C_CTRL : INTEGER :=16#24#; type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write FSM states signal wstate, wnext, rstate, rnext: states; -- Local signal signal waddr : UNSIGNED(ADDR_BITS-1 downto 0); signal wmask : UNSIGNED(31 downto 0); signal aw_hs : STD_LOGIC; signal w_hs : STD_LOGIC; signal rdata_data : UNSIGNED(31 downto 0); signal ar_hs : STD_LOGIC; signal raddr : UNSIGNED(ADDR_BITS-1 downto 0); signal AWREADY_t : STD_LOGIC; signal WREADY_t : STD_LOGIC; signal ARREADY_t : STD_LOGIC; signal RVALID_t : STD_LOGIC; -- internal registers signal int_ap_idle : STD_LOGIC; signal int_ap_ready : STD_LOGIC; signal int_ap_done : STD_LOGIC; signal int_ap_start : STD_LOGIC; signal int_auto_restart : STD_LOGIC; signal int_gie : STD_LOGIC; signal int_ier : STD_LOGIC; signal int_isr : STD_LOGIC; signal int_a : UNSIGNED(31 downto 0); signal int_b : UNSIGNED(31 downto 0); signal int_c : UNSIGNED(31 downto 0); signal int_c_ap_vld : STD_LOGIC; begin -- axi write AWREADY_t <= '1' when wstate = wridle else '0'; AWREADY <= AWREADY_t; WREADY_t <= '1' when wstate = wrdata else '0'; WREADY <= WREADY_t; BRESP <= "00"; -- OKAY BVALID <= '1' when wstate = wrresp else '0'; wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0)); aw_hs <= AWVALID and AWREADY_t; w_hs <= WVALID and WREADY_t; -- write FSM process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (ARESET = '1') then wstate <= wridle; else wstate <= wnext; end if; end if; end process; process (wstate, AWVALID, WVALID, BREADY) begin case (wstate) is when wridle => if (AWVALID = '1') then wnext <= wrdata; else wnext <= wridle; end if; when wrdata => if (WVALID = '1') then wnext <= wrresp; else wnext <= wrdata; end if; when wrresp => if (BREADY = '1') then wnext <= wridle; else wnext <= wrresp; end if; when others => wnext <= wridle; end case; end process; waddr_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (aw_hs = '1') then waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)); end if; end if; end process; -- axi read ARREADY_t <= '1' when (rstate = rdidle) else '0'; ARREADY <= ARREADY_t; RDATA <= STD_LOGIC_VECTOR(rdata_data); RRESP <= "00"; -- OKAY RVALID_t <= '1' when (rstate = rddata) else '0'; RVALID <= RVALID_t; ar_hs <= ARVALID and ARREADY_t; raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0)); -- read FSM process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (ARESET = '1') then rstate <= rdidle; else rstate <= rnext; end if; end if; end process; process (rstate, ARVALID, RREADY, RVALID_t) begin case (rstate) is when rdidle => if (ARVALID = '1') then rnext <= rddata; else rnext <= rdidle; end if; when rddata => if (RREADY = '1' and RVALID_t = '1') then rnext <= rdidle; else rnext <= rddata; end if; when others => rnext <= rdidle; end case; end process; rdata_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (ar_hs = '1') then case (TO_INTEGER(raddr)) is when ADDR_AP_CTRL => rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0'); when ADDR_GIE => rdata_data <= (1 => int_gie, others => '0'); when ADDR_IER => rdata_data <= (1 => int_ier, others => '0'); when ADDR_ISR => rdata_data <= (1 => int_isr, others => '0'); when ADDR_A_DATA_0 => rdata_data <= RESIZE(int_a(31 downto 0), 32); when ADDR_B_DATA_0 => rdata_data <= RESIZE(int_b(31 downto 0), 32); when ADDR_C_DATA_0 => rdata_data <= RESIZE(int_c(31 downto 0), 32); when ADDR_C_CTRL => rdata_data <= (0 => int_c_ap_vld, others => '0'); when others => rdata_data <= (others => '0'); end case; end if; end if; end process; -- internal registers interrupt <= int_gie and int_isr; ap_start <= int_ap_start; int_ap_idle <= ap_idle; int_ap_ready <= ap_ready; a <= STD_LOGIC_VECTOR(int_a); b <= STD_LOGIC_VECTOR(int_b); process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_start <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then int_ap_start <= '1'; elsif (ap_done = '1' and int_auto_restart = '1') then int_ap_start <= '1'; -- auto restart else int_ap_start <= '0'; -- self clear end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_done <= '0'; elsif (ACLK_EN = '1') then if (ap_done = '1') then int_ap_done <= '1'; elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then int_ap_done <= '0'; -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_auto_restart <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then int_auto_restart <= WDATA(7); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_gie <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then int_gie <= WDATA(0); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ier <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then int_ier <= WDATA(0); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr <= '0'; elsif (ACLK_EN = '1') then if (int_ier = '1' and ap_done = '1') then int_isr <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr <= int_isr xor WDATA(0); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_A_DATA_0) then int_a(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_a(31 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_B_DATA_0) then int_b(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_b(31 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_c <= (others => '0'); elsif (ACLK_EN = '1') then if (c_ap_vld = '1') then int_c <= UNSIGNED(c); -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_c_ap_vld <= '0'; elsif (ACLK_EN = '1') then if (c_ap_vld = '1') then int_c_ap_vld <= '1'; elsif (ar_hs = '1' and raddr = ADDR_C_CTRL) then int_c_ap_vld <= '0'; -- clear on read end if; end if; end if; end process; end architecture behave;	gpl-3.0
freecores/usb_fpga_1_11	examples/usb-fpga-2.01/2.01b/ucecho/fpga/ucecho.vhd	42	580	library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity ucecho is port( pc : in unsigned(7 downto 0); pb : out unsigned(7 downto 0); CLK : in std_logic ); end ucecho; architecture RTL of ucecho is --signal declaration signal pb_buf : unsigned(7 downto 0); begin dpUCECHO: process(CLK) begin if CLK' event and CLK = '1' then if ( pc >= 97 ) and ( pc <= 122) then pb_buf <= pc - 32; else pb_buf <= pc; end if; pb <= pb_buf; end if; end process dpUCECHO; end RTL;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_reset.vhd	6	26422	------------------------------------------------------------------------------- -- axi_datamover_reset.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_reset.vhd -- -- Description: -- This file implements the DataMover Reset module. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library lib_cdc_v1_0; ------------------------------------------------------------------------------- entity axi_datamover_reset is generic ( C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0 -- 0 = Use Synchronous Command/Statys User Interface -- 1 = Use Asynchronous Command/Statys User Interface ); port ( -- Primary Clock and Reset Inputs ----------------- -- primary_aclk : in std_logic; -- primary_aresetn : in std_logic; -- --------------------------------------------------- -- Async operation clock and reset from User ------ -- Used for Command/Status User interface -- -- synchronization when C_STSCMD_IS_ASYNC = 1 -- -- secondary_awclk : in std_logic; -- secondary_aresetn : in std_logic; -- --------------------------------------------------- -- Halt request input control ------------------------------- halt_req : in std_logic; -- -- Active high soft shutdown request (can be a pulse) -- -- -- Halt Complete status flag -- halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------- -- Soft Shutdown internal interface ------------------------------------------------ -- flush_stop_request : Out std_logic; -- -- Active high soft stop request to modules -- -- data_cntlr_stopped : in std_logic; -- -- Active high flag indicating the data controller is flushed and stopped -- -- addr_cntlr_stopped : in std_logic; -- -- Active high flag indicating the address controller is flushed and stopped -- -- aux1_stopped : in std_logic; -- -- Active high flag flush complete for auxillary 1 module -- -- Tie high if unused -- -- aux2_stopped : in std_logic; -- -- Active high flag flush complete for auxillary 2 module -- -- Tie high if unused -- ------------------------------------------------------------------------------------ -- HW Reset outputs to reset groups ------------------------------------- -- cmd_stat_rst_user : Out std_logic; -- -- The reset to the Command/Status Module User interface side -- -- cmd_stat_rst_int : Out std_logic; -- -- The reset to the Command/Status Module internal interface side -- -- mmap_rst : Out std_logic; -- -- The reset to the Memory Map interface side -- -- stream_rst : Out std_logic -- -- The reset to the Stream interface side -- -------------------------------------------------------------------------- ); end entity axi_datamover_reset; architecture implementation of axi_datamover_reset is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; constant MTBF_STAGES : integer := 4; -- ATTRIBUTE async_reg : STRING; -- Signals signal sig_cmd_stat_rst_user_n : std_logic := '0'; signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0'; signal sig_cmd_stat_rst_int_reg_n : std_logic := '0'; signal sig_mmap_rst_reg_n : std_logic := '0'; signal sig_stream_rst_reg_n : std_logic := '0'; signal sig_syncd_sec_rst : std_logic := '0'; -- soft shutdown support signal sig_internal_reset : std_logic := '0'; signal sig_s_h_halt_reg : std_logic := '0'; signal sig_halt_cmplt : std_logic := '0'; -- additional CDC synchronization signals signal sig_sec_neg_edge_plus_delay : std_logic := '0'; signal sig_secondary_aresetn_reg : std_logic := '0'; signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0'; signal sig_prim2sec_rst_reg2_n : std_logic := '0'; -- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg1_n_cdc_to : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg2_n : SIGNAL IS "true"; begin --(architecture implementation) -- Assign outputs cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n); cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or sig_syncd_sec_rst; mmap_rst <= not(sig_mmap_rst_reg_n) or sig_syncd_sec_rst; stream_rst <= not(sig_stream_rst_reg_n) or sig_syncd_sec_rst; -- Internal logic Implmentation ------------------------------------------------------------ -- If Generate -- -- Label: GEN_SYNC_CMDSTAT_RESET -- -- If Generate Description: -- This IfGen assigns the reset for the -- Synchronous Command/Status User interface case -- ------------------------------------------------------------ GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate begin sig_syncd_sec_rst <= '0'; sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from); end generate GEN_SYNC_CMDSTAT_RESET; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ASYNC_CMDSTAT_RESET -- -- If Generate Description: -- This IfGen assigns the reset for the -- Asynchronous Command/Status User interface case -- ------------------------------------------------------------ GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate -- ATTRIBUTE async_reg : STRING; signal sig_sec_reset_in_reg_n : std_logic := '0'; signal sig_secondary_aresetn_reg_tmp : std_logic := '0'; -- Secondary reset pulse stretcher signal sig_secondary_dly1 : std_logic := '0'; signal sig_secondary_dly2 : std_logic := '0'; signal sig_neg_edge_detect : std_logic := '0'; signal sig_sec2prim_reset : std_logic := '0'; signal sig_sec2prim_reset_reg_cdc_tig : std_logic := '0'; signal sig_sec2prim_reset_reg2 : std_logic := '0'; signal sig_sec2prim_rst_syncro1_cdc_tig : std_logic := '0'; signal sig_sec2prim_rst_syncro2 : std_logic := '0'; -- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg_cdc_tig : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg2 : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro1_cdc_tig : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro2 : SIGNAL IS "true"; begin -- Generate the reset in the primary clock domain. Use the longer -- of the pulse stretched reset or the actual reset. sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or sig_sec2prim_rst_syncro2; -- Check for falling edge of secondary_aresetn input sig_neg_edge_detect <= '1' when (sig_sec_reset_in_reg_n = '1' and secondary_aresetn = '0') else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PUSE_STRETCH_FLOPS -- -- Process Description: -- This process implements a 3 clock wide pulse whenever the -- secondary reset is asserted -- ------------------------------------------------------------- IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then If (sig_secondary_dly2 = '1') Then sig_secondary_dly1 <= '0' ; sig_secondary_dly2 <= '0' ; Elsif (sig_neg_edge_detect = '1') Then sig_secondary_dly1 <= '1'; else sig_secondary_dly2 <= sig_secondary_dly1 ; End if; end if; end process IMP_PUSE_STRETCH_FLOPS; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SYNC_NEG_EDGE -- -- Process Description: -- First (source clock) stage synchronizer for CDC of -- negative edge detection, -- ------------------------------------------------------------- SYNC_NEG_EDGE : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or sig_secondary_dly1 or sig_secondary_dly2; end if; end process SYNC_NEG_EDGE; -- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SEC2PRIM_RST_SYNCRO -- -- Process Description: -- This process registers the secondary reset input to -- the primary clock domain. -- ------------------------------------------------------------- SEC2PRIM_RST_SYNCRO : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => sig_sec_neg_edge_plus_delay, prmry_vect_in => (others => '0'), scndry_aclk => primary_aclk, scndry_resetn => '0', scndry_out => sig_sec2prim_reset_reg2, scndry_vect_out => open ); -- SEC2PRIM_RST_SYNCRO : process (primary_aclk) -- begin -- if (primary_aclk'event and primary_aclk = '1') then -- -- -- sig_sec2prim_reset_reg_cdc_tig <= sig_sec_neg_edge_plus_delay ; -- -- sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg_cdc_tig; -- -- end if; -- end process SEC2PRIM_RST_SYNCRO; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SEC_RST -- -- Process Description: -- First (source clock) stage synchronizer for CDC of -- secondary reset input, -- ------------------------------------------------------------- REG_SEC_RST : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_secondary_aresetn_reg <= secondary_aresetn; end if; end process REG_SEC_RST; -- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SEC2PRIM_RST_SYNCRO_2 -- -- Process Description: -- Second stage (destination) synchronizers for the secondary -- reset CDC to the primary clock. -- ------------------------------------------------------------- sig_secondary_aresetn_reg_tmp <= not(sig_secondary_aresetn_reg); SEC2PRIM_RST_SYNCRO_2 : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => sig_secondary_aresetn_reg_tmp, prmry_vect_in => (others => '0'), scndry_aclk => primary_aclk, scndry_resetn => '0', scndry_out => sig_sec2prim_rst_syncro2, scndry_vect_out => open ); -- SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk) -- begin -- if (primary_aclk'event and primary_aclk = '1') then -- -- -- -- CDC sig_sec2prim_rst_syncro1_cdc_tig <= not(secondary_aresetn); -- sig_sec2prim_rst_syncro1_cdc_tig <= not(sig_secondary_aresetn_reg); -- sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1_cdc_tig; -- -- -- end if; -- end process SEC2PRIM_RST_SYNCRO_2; -- Generate the Command and Status side reset sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and sig_prim2sec_rst_reg2_n; -- CDC sig_cmd_stat_rst_user_reg_n_cdc_from; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_RESET_ASYNC -- -- Process Description: -- This process registers the secondary reset input to -- generate the Command/Status User interface reset. -- ------------------------------------------------------------- REG_RESET_ASYNC : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_sec_reset_in_reg_n <= secondary_aresetn; end if; end process REG_RESET_ASYNC; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SYNC_PRIM2SEC_RST -- -- Process Description: -- Second (destination clock) stage synchronizers for CDC of -- primary reset input, -- ------------------------------------------------------------- SYNC_PRIM2SEC_RST : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => sig_cmd_stat_rst_user_reg_n_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => secondary_awclk, scndry_resetn => '0', scndry_out => sig_prim2sec_rst_reg2_n, scndry_vect_out => open ); -- SYNC_PRIM2SEC_RST : process (secondary_awclk) -- begin -- if (secondary_awclk'event and secondary_awclk = '1') then -- -- sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from; -- sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to; -- -- end if; -- end process SYNC_PRIM2SEC_RST; -- end generate GEN_ASYNC_CMDSTAT_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_CMDSTAT_PRIM_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Command/Status User interface reset. -- ------------------------------------------------------------- REG_CMDSTAT_PRIM_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn; end if; end process REG_CMDSTAT_PRIM_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_CMDSTAT_INT_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Command/Status internal interface reset. -- ------------------------------------------------------------- REG_CMDSTAT_INT_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_cmd_stat_rst_int_reg_n <= primary_aresetn; end if; end process REG_CMDSTAT_INT_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_MMAP_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Memory Map interface reset. -- ------------------------------------------------------------- REG_MMAP_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_mmap_rst_reg_n <= primary_aresetn; end if; end process REG_MMAP_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_STREAM_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Stream interface reset. -- ------------------------------------------------------------- REG_STREAM_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_stream_rst_reg_n <= primary_aresetn; end if; end process REG_STREAM_RESET; -- Soft Shutdown logic ------------------------------------------------------ sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or sig_syncd_sec_rst; flush_stop_request <= sig_s_h_halt_reg; halt_cmplt <= sig_halt_cmplt; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_HALT_REQ -- -- Process Description: -- Implements a sample and hold flop for the halt request -- input. Can only be cleared on a HW reset. -- ------------------------------------------------------------- REG_HALT_REQ : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_internal_reset = '1') then sig_s_h_halt_reg <= '0'; elsif (halt_req = '1') then sig_s_h_halt_reg <= '1'; else null; -- hold current state end if; end if; end process REG_HALT_REQ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_CMPLT -- -- Process Description: -- Implements a the flop for the halt complete status -- output. Can only be cleared on a HW reset. -- ------------------------------------------------------------- IMP_HALT_CMPLT : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_internal_reset = '1') then sig_halt_cmplt <= '0'; elsif (data_cntlr_stopped = '1' and addr_cntlr_stopped = '1' and aux1_stopped = '1' and aux2_stopped = '1') then sig_halt_cmplt <= '1'; else null; -- hold current state end if; end if; end process IMP_HALT_CMPLT; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/FIFO_image_filter_img_1_cols_V.vhd	4	4564	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_img_1_cols_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_img_1_cols_V_shiftReg; architecture rtl of FIFO_image_filter_img_1_cols_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_img_1_cols_V is generic ( MEM_STYLE : string := "shiftreg"; DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_img_1_cols_V is component FIFO_image_filter_img_1_cols_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_img_1_cols_V_shiftReg : FIFO_image_filter_img_1_cols_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_register_s2mm.vhd	2	178198	-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_register_s2mm.vhd -- -- Description: This entity encompasses the channel register set. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_register_s2mm is generic( C_NUM_REGISTERS : integer := 11 ; C_INCLUDE_SG : integer := 1 ; C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ; C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ; C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ; C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ; C_MICRO_DMA : integer range 0 to 1 := 0 ; C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0 --C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034 ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- AXI Interface Control -- axi2ip_wrce : in std_logic_vector -- (C_NUM_REGISTERS-1 downto 0) ; -- axi2ip_wrdata : in std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- -- -- DMASR Control -- stop_dma : in std_logic ; -- halted_clr : in std_logic ; -- halted_set : in std_logic ; -- idle_set : in std_logic ; -- idle_clr : in std_logic ; -- ioc_irq_set : in std_logic ; -- dly_irq_set : in std_logic ; -- irqdelay_status : in std_logic_vector(7 downto 0) ; -- irqthresh_status : in std_logic_vector(7 downto 0) ; -- irqthresh_wren : out std_logic ; -- irqdelay_wren : out std_logic ; -- dlyirq_dsble : out std_logic ; -- CR605888 -- -- Error Control -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- ftch_interr_set : in std_logic ; -- ftch_slverr_set : in std_logic ; -- ftch_decerr_set : in std_logic ; -- ftch_error_addr : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_interr_set : in std_logic ; -- updt_slverr_set : in std_logic ; -- updt_decerr_set : in std_logic ; -- updt_error_addr : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- error_in : in std_logic ; -- error_out : out std_logic ; -- introut : out std_logic ; -- soft_reset_in : in std_logic ; -- soft_reset_clr : in std_logic ; -- -- -- CURDESC Update -- update_curdesc : in std_logic ; -- tdest_in : in std_logic_vector (5 downto 0) ; new_curdesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- -- TAILDESC Update -- tailpntr_updated : out std_logic ; -- -- -- Channel Register Out -- sg_ctl : out std_logic_vector (7 downto 0) ; dmacr : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- dmasr : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc1_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc1_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc1_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc1_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc2_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc2_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc2_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc2_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc3_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc3_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc3_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc3_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc4_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc4_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc4_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc4_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc5_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc5_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc5_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc5_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc6_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc6_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc6_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc6_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc7_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc7_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc7_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc7_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc8_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc8_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc8_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc8_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc9_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc9_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc9_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc9_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc10_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc10_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc10_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc10_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc11_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc11_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc11_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc11_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc12_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc12_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc12_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc12_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc13_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc13_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc13_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc13_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc14_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc14_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc14_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc14_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc15_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc15_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc15_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc15_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- buffer_address : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- buffer_length : out std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- buffer_length_wren : out std_logic ; -- bytes_received : in std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- bytes_received_wren : in std_logic -- ); -- end axi_dma_register_s2mm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_register_s2mm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- constant SGCTL_INDEX : integer := 0; constant DMACR_INDEX : integer := 1; -- DMACR Register index constant DMASR_INDEX : integer := 2; -- DMASR Register index constant CURDESC_LSB_INDEX : integer := 3; -- CURDESC LSB Reg index constant CURDESC_MSB_INDEX : integer := 4; -- CURDESC MSB Reg index constant TAILDESC_LSB_INDEX : integer := 5; -- TAILDESC LSB Reg index constant TAILDESC_MSB_INDEX : integer := 6; -- TAILDESC MSB Reg index constant CURDESC1_LSB_INDEX : integer := 17; -- CURDESC LSB Reg index constant CURDESC1_MSB_INDEX : integer := 18; -- CURDESC MSB Reg index constant TAILDESC1_LSB_INDEX : integer := 19; -- TAILDESC LSB Reg index constant TAILDESC1_MSB_INDEX : integer := 20; -- TAILDESC MSB Reg index constant CURDESC2_LSB_INDEX : integer := 25; -- CURDESC LSB Reg index constant CURDESC2_MSB_INDEX : integer := 26; -- CURDESC MSB Reg index constant TAILDESC2_LSB_INDEX : integer := 27; -- TAILDESC LSB Reg index constant TAILDESC2_MSB_INDEX : integer := 28; -- TAILDESC MSB Reg index constant CURDESC3_LSB_INDEX : integer := 33; -- CURDESC LSB Reg index constant CURDESC3_MSB_INDEX : integer := 34; -- CURDESC MSB Reg index constant TAILDESC3_LSB_INDEX : integer := 35; -- TAILDESC LSB Reg index constant TAILDESC3_MSB_INDEX : integer := 36; -- TAILDESC MSB Reg index constant CURDESC4_LSB_INDEX : integer := 41; -- CURDESC LSB Reg index constant CURDESC4_MSB_INDEX : integer := 42; -- CURDESC MSB Reg index constant TAILDESC4_LSB_INDEX : integer := 43; -- TAILDESC LSB Reg index constant TAILDESC4_MSB_INDEX : integer := 44; -- TAILDESC MSB Reg index constant CURDESC5_LSB_INDEX : integer := 49; -- CURDESC LSB Reg index constant CURDESC5_MSB_INDEX : integer := 50; -- CURDESC MSB Reg index constant TAILDESC5_LSB_INDEX : integer := 51; -- TAILDESC LSB Reg index constant TAILDESC5_MSB_INDEX : integer := 52; -- TAILDESC MSB Reg index constant CURDESC6_LSB_INDEX : integer := 57; -- CURDESC LSB Reg index constant CURDESC6_MSB_INDEX : integer := 58; -- CURDESC MSB Reg index constant TAILDESC6_LSB_INDEX : integer := 59; -- TAILDESC LSB Reg index constant TAILDESC6_MSB_INDEX : integer := 60; -- TAILDESC MSB Reg index constant CURDESC7_LSB_INDEX : integer := 65; -- CURDESC LSB Reg index constant CURDESC7_MSB_INDEX : integer := 66; -- CURDESC MSB Reg index constant TAILDESC7_LSB_INDEX : integer := 67; -- TAILDESC LSB Reg index constant TAILDESC7_MSB_INDEX : integer := 68; -- TAILDESC MSB Reg index constant CURDESC8_LSB_INDEX : integer := 73; -- CURDESC LSB Reg index constant CURDESC8_MSB_INDEX : integer := 74; -- CURDESC MSB Reg index constant TAILDESC8_LSB_INDEX : integer := 75; -- TAILDESC LSB Reg index constant TAILDESC8_MSB_INDEX : integer := 76; -- TAILDESC MSB Reg index constant CURDESC9_LSB_INDEX : integer := 81; -- CURDESC LSB Reg index constant CURDESC9_MSB_INDEX : integer := 82; -- CURDESC MSB Reg index constant TAILDESC9_LSB_INDEX : integer := 83; -- TAILDESC LSB Reg index constant TAILDESC9_MSB_INDEX : integer := 84; -- TAILDESC MSB Reg index constant CURDESC10_LSB_INDEX : integer := 89; -- CURDESC LSB Reg index constant CURDESC10_MSB_INDEX : integer := 90; -- CURDESC MSB Reg index constant TAILDESC10_LSB_INDEX : integer := 91; -- TAILDESC LSB Reg index constant TAILDESC10_MSB_INDEX : integer := 92; -- TAILDESC MSB Reg index constant CURDESC11_LSB_INDEX : integer := 97; -- CURDESC LSB Reg index constant CURDESC11_MSB_INDEX : integer := 98; -- CURDESC MSB Reg index constant TAILDESC11_LSB_INDEX : integer := 99; -- TAILDESC LSB Reg index constant TAILDESC11_MSB_INDEX : integer := 100; -- TAILDESC MSB Reg index constant CURDESC12_LSB_INDEX : integer := 105; -- CURDESC LSB Reg index constant CURDESC12_MSB_INDEX : integer := 106; -- CURDESC MSB Reg index constant TAILDESC12_LSB_INDEX : integer := 107; -- TAILDESC LSB Reg index constant TAILDESC12_MSB_INDEX : integer := 108; -- TAILDESC MSB Reg index constant CURDESC13_LSB_INDEX : integer := 113; -- CURDESC LSB Reg index constant CURDESC13_MSB_INDEX : integer := 114; -- CURDESC MSB Reg index constant TAILDESC13_LSB_INDEX : integer := 115; -- TAILDESC LSB Reg index constant TAILDESC13_MSB_INDEX : integer := 116; -- TAILDESC MSB Reg index constant CURDESC14_LSB_INDEX : integer := 121; -- CURDESC LSB Reg index constant CURDESC14_MSB_INDEX : integer := 122; -- CURDESC MSB Reg index constant TAILDESC14_LSB_INDEX : integer := 123; -- TAILDESC LSB Reg index constant TAILDESC14_MSB_INDEX : integer := 124; -- TAILDESC MSB Reg index constant CURDESC15_LSB_INDEX : integer := 129; -- CURDESC LSB Reg index constant CURDESC15_MSB_INDEX : integer := 130; -- CURDESC MSB Reg index constant TAILDESC15_LSB_INDEX : integer := 131; -- TAILDESC LSB Reg index constant TAILDESC15_MSB_INDEX : integer := 132; -- TAILDESC MSB Reg index -- CR603034 moved s2mm back to offset 6 --constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA) --constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA) -- -- --constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA) -- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx -- SA_ADDRESS_INDEX, -- Source Address Index -- DA_ADDRESS_INDEX); -- Destination Address Index constant BUFF_ADDRESS_INDEX : integer := 7; constant BUFF_LENGTH_INDEX : integer := 11; -- Buffer Length Reg constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0'); constant DMA_CONFIG : std_logic_vector(0 downto 0) := std_logic_vector(to_unsigned(C_INCLUDE_SG,1)); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal dmacr_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal dmasr_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0'); signal curdesc_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0'); signal taildesc_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal buffer_address_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal buffer_length_i : std_logic_vector (C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal curdesc1_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc1_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc1_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc1_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc2_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc2_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc2_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc2_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc3_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc3_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc3_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc3_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc4_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc4_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc4_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc4_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc5_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc5_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc5_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc5_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc6_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc6_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc6_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc6_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc7_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc7_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc7_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc7_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc8_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc8_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc8_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc8_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc9_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc9_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc9_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc9_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc10_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc10_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc10_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc10_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc11_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc11_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc11_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc11_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc12_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc12_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc12_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc12_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc13_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc13_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc13_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc13_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc14_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc14_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc14_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc14_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc15_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc15_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc15_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc15_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal update_curdesc1 : std_logic := '0'; signal update_curdesc2 : std_logic := '0'; signal update_curdesc3 : std_logic := '0'; signal update_curdesc4 : std_logic := '0'; signal update_curdesc5 : std_logic := '0'; signal update_curdesc6 : std_logic := '0'; signal update_curdesc7 : std_logic := '0'; signal update_curdesc8 : std_logic := '0'; signal update_curdesc9 : std_logic := '0'; signal update_curdesc10 : std_logic := '0'; signal update_curdesc11 : std_logic := '0'; signal update_curdesc12 : std_logic := '0'; signal update_curdesc13 : std_logic := '0'; signal update_curdesc14 : std_logic := '0'; signal update_curdesc15 : std_logic := '0'; signal dest0 : std_logic := '0'; signal dest1 : std_logic := '0'; signal dest2 : std_logic := '0'; signal dest3 : std_logic := '0'; signal dest4 : std_logic := '0'; signal dest5 : std_logic := '0'; signal dest6 : std_logic := '0'; signal dest7 : std_logic := '0'; signal dest8 : std_logic := '0'; signal dest9 : std_logic := '0'; signal dest10 : std_logic := '0'; signal dest11 : std_logic := '0'; signal dest12 : std_logic := '0'; signal dest13 : std_logic := '0'; signal dest14 : std_logic := '0'; signal dest15 : std_logic := '0'; -- DMASR Signals signal halted : std_logic := '0'; signal idle : std_logic := '0'; signal cmplt : std_logic := '0'; signal error : std_logic := '0'; signal dma_interr : std_logic := '0'; signal dma_slverr : std_logic := '0'; signal dma_decerr : std_logic := '0'; signal sg_interr : std_logic := '0'; signal sg_slverr : std_logic := '0'; signal sg_decerr : std_logic := '0'; signal ioc_irq : std_logic := '0'; signal dly_irq : std_logic := '0'; signal error_d1 : std_logic := '0'; signal error_re : std_logic := '0'; signal err_irq : std_logic := '0'; signal sg_ftch_error : std_logic := '0'; signal sg_updt_error : std_logic := '0'; signal error_pointer_set : std_logic := '0'; signal error_pointer_set1 : std_logic := '0'; signal error_pointer_set2 : std_logic := '0'; signal error_pointer_set3 : std_logic := '0'; signal error_pointer_set4 : std_logic := '0'; signal error_pointer_set5 : std_logic := '0'; signal error_pointer_set6 : std_logic := '0'; signal error_pointer_set7 : std_logic := '0'; signal error_pointer_set8 : std_logic := '0'; signal error_pointer_set9 : std_logic := '0'; signal error_pointer_set10 : std_logic := '0'; signal error_pointer_set11 : std_logic := '0'; signal error_pointer_set12 : std_logic := '0'; signal error_pointer_set13 : std_logic := '0'; signal error_pointer_set14 : std_logic := '0'; signal error_pointer_set15 : std_logic := '0'; -- interrupt coalescing support signals signal different_delay : std_logic := '0'; signal different_thresh : std_logic := '0'; signal threshold_is_zero : std_logic := '0'; -- soft reset support signals signal soft_reset_i : std_logic := '0'; signal run_stop_clr : std_logic := '0'; signal tail_update_lsb : std_logic := '0'; signal tail_update_msb : std_logic := '0'; signal sg_cache_info : std_logic_vector (7 downto 0); signal halt_free : std_logic := '0'; signal tmp11 : std_logic := '0'; signal sig_cur_updated : std_logic := '0'; signal tailpntr_updated_d1 : std_logic; signal tailpntr_updated_d2 : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin GEN_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate begin halt_free <= '1'; end generate GEN_MULTI_CH; GEN_NOMULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate begin halt_free <= dmasr_i(DMASR_HALTED_BIT); end generate GEN_NOMULTI_CH; GEN_DESC_UPDATE_FOR_SG : if C_NUM_S2MM_CHANNELS = 1 generate begin update_curdesc1 <= '0'; update_curdesc2 <= '0'; update_curdesc3 <= '0'; update_curdesc4 <= '0'; update_curdesc5 <= '0'; update_curdesc6 <= '0'; update_curdesc7 <= '0'; update_curdesc8 <= '0'; update_curdesc9 <= '0'; update_curdesc10 <= '0'; update_curdesc11 <= '0'; update_curdesc12 <= '0'; update_curdesc13 <= '0'; update_curdesc14 <= '0'; update_curdesc15 <= '0'; end generate GEN_DESC_UPDATE_FOR_SG; dest0 <= '1' when tdest_in (4 downto 0) = "00000" else '0'; dest1 <= '1' when tdest_in (4 downto 0) = "00001" else '0'; dest2 <= '1' when tdest_in (4 downto 0) = "00010" else '0'; dest3 <= '1' when tdest_in (4 downto 0) = "00011" else '0'; dest4 <= '1' when tdest_in (4 downto 0) = "00100" else '0'; dest5 <= '1' when tdest_in (4 downto 0) = "00101" else '0'; dest6 <= '1' when tdest_in (4 downto 0) = "00110" else '0'; dest7 <= '1' when tdest_in (4 downto 0) = "00111" else '0'; dest8 <= '1' when tdest_in (4 downto 0) = "01000" else '0'; dest9 <= '1' when tdest_in (4 downto 0) = "01001" else '0'; dest10 <= '1' when tdest_in (4 downto 0) = "01010" else '0'; dest11 <= '1' when tdest_in (4 downto 0) = "01011" else '0'; dest12 <= '1' when tdest_in (4 downto 0) = "01100" else '0'; dest13 <= '1' when tdest_in (4 downto 0) = "01101" else '0'; dest14 <= '1' when tdest_in (4 downto 0) = "01110" else '0'; dest15 <= '1' when tdest_in (4 downto 0) = "01111" else '0'; GEN_DESC_UPDATE_FOR_SG_CH : if C_NUM_S2MM_CHANNELS > 1 generate update_curdesc1 <= update_curdesc when tdest_in (4 downto 0) = "00001" else '0'; update_curdesc2 <= update_curdesc when tdest_in (4 downto 0) = "00010" else '0'; update_curdesc3 <= update_curdesc when tdest_in (4 downto 0) = "00011" else '0'; update_curdesc4 <= update_curdesc when tdest_in (4 downto 0) = "00100" else '0'; update_curdesc5 <= update_curdesc when tdest_in (4 downto 0) = "00101" else '0'; update_curdesc6 <= update_curdesc when tdest_in (4 downto 0) = "00110" else '0'; update_curdesc7 <= update_curdesc when tdest_in (4 downto 0) = "00111" else '0'; update_curdesc8 <= update_curdesc when tdest_in (4 downto 0) = "01000" else '0'; update_curdesc9 <= update_curdesc when tdest_in (4 downto 0) = "01001" else '0'; update_curdesc10 <= update_curdesc when tdest_in (4 downto 0) = "01010" else '0'; update_curdesc11 <= update_curdesc when tdest_in (4 downto 0) = "01011" else '0'; update_curdesc12 <= update_curdesc when tdest_in (4 downto 0) = "01100" else '0'; update_curdesc13 <= update_curdesc when tdest_in (4 downto 0) = "01101" else '0'; update_curdesc14 <= update_curdesc when tdest_in (4 downto 0) = "01110" else '0'; update_curdesc15 <= update_curdesc when tdest_in (4 downto 0) = "01111" else '0'; end generate GEN_DESC_UPDATE_FOR_SG_CH; dmacr <= dmacr_i ; dmasr <= dmasr_i ; curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ; curdesc_msb <= curdesc_msb_i ; taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ; taildesc_msb <= taildesc_msb_i ; buffer_address <= buffer_address_i ; buffer_length <= buffer_length_i ; curdesc1_lsb <= curdesc1_lsb_i ; curdesc1_msb <= curdesc1_msb_i ; taildesc1_lsb <= taildesc1_lsb_i ; taildesc1_msb <= taildesc1_msb_i ; curdesc2_lsb <= curdesc2_lsb_i ; curdesc2_msb <= curdesc2_msb_i ; taildesc2_lsb <= taildesc2_lsb_i ; taildesc2_msb <= taildesc2_msb_i ; curdesc3_lsb <= curdesc3_lsb_i ; curdesc3_msb <= curdesc3_msb_i ; taildesc3_lsb <= taildesc3_lsb_i ; taildesc3_msb <= taildesc3_msb_i ; curdesc4_lsb <= curdesc4_lsb_i ; curdesc4_msb <= curdesc4_msb_i ; taildesc4_lsb <= taildesc4_lsb_i ; taildesc4_msb <= taildesc4_msb_i ; curdesc5_lsb <= curdesc5_lsb_i ; curdesc5_msb <= curdesc5_msb_i ; taildesc5_lsb <= taildesc5_lsb_i ; taildesc5_msb <= taildesc5_msb_i ; curdesc6_lsb <= curdesc6_lsb_i ; curdesc6_msb <= curdesc6_msb_i ; taildesc6_lsb <= taildesc6_lsb_i ; taildesc6_msb <= taildesc6_msb_i ; curdesc7_lsb <= curdesc7_lsb_i ; curdesc7_msb <= curdesc7_msb_i ; taildesc7_lsb <= taildesc7_lsb_i ; taildesc7_msb <= taildesc7_msb_i ; curdesc8_lsb <= curdesc8_lsb_i ; curdesc8_msb <= curdesc8_msb_i ; taildesc8_lsb <= taildesc8_lsb_i ; taildesc8_msb <= taildesc8_msb_i ; curdesc9_lsb <= curdesc9_lsb_i ; curdesc9_msb <= curdesc9_msb_i ; taildesc9_lsb <= taildesc9_lsb_i ; taildesc9_msb <= taildesc9_msb_i ; curdesc10_lsb <= curdesc10_lsb_i ; curdesc10_msb <= curdesc10_msb_i ; taildesc10_lsb <= taildesc10_lsb_i ; taildesc10_msb <= taildesc10_msb_i ; curdesc11_lsb <= curdesc11_lsb_i ; curdesc11_msb <= curdesc11_msb_i ; taildesc11_lsb <= taildesc11_lsb_i ; taildesc11_msb <= taildesc11_msb_i ; curdesc12_lsb <= curdesc12_lsb_i ; curdesc12_msb <= curdesc12_msb_i ; taildesc12_lsb <= taildesc12_lsb_i ; taildesc12_msb <= taildesc12_msb_i ; curdesc13_lsb <= curdesc13_lsb_i ; curdesc13_msb <= curdesc13_msb_i ; taildesc13_lsb <= taildesc13_lsb_i ; taildesc13_msb <= taildesc13_msb_i ; curdesc14_lsb <= curdesc14_lsb_i ; curdesc14_msb <= curdesc14_msb_i ; taildesc14_lsb <= taildesc14_lsb_i ; taildesc14_msb <= taildesc14_msb_i ; curdesc15_lsb <= curdesc15_lsb_i ; curdesc15_msb <= curdesc15_msb_i ; taildesc15_lsb <= taildesc15_lsb_i ; taildesc15_msb <= taildesc15_msb_i ; --------------------------------------------------------------------------- -- DMA Control Register --------------------------------------------------------------------------- -- DMACR - Interrupt Delay Value ------------------------------------------------------------------------------- DMACR_DELAY : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0'); elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT); end if; end if; end process DMACR_DELAY; -- If written delay is different than previous value then assert write enable different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) /= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) else '0'; -- delay value different, drive write of delay value to interrupt controller NEW_DELAY_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then irqdelay_wren <= '0'; -- If AXI Lite write to DMACR and delay different than current -- setting then update delay value elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then irqdelay_wren <= '1'; else irqdelay_wren <= '0'; end if; end if; end process NEW_DELAY_WRITE; ------------------------------------------------------------------------------- -- DMACR - Interrupt Threshold Value ------------------------------------------------------------------------------- threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD else '0'; DMACR_THRESH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD; -- On AXI Lite write elsif(axi2ip_wrce(DMACR_INDEX) = '1')then -- If value is 0 then set threshold to 1 if(threshold_is_zero='1')then dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD; -- else set threshold to axi lite wrdata value else dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT); end if; end if; end if; end process DMACR_THRESH; -- If written threshold is different than previous value then assert write enable different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) /= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) else '0'; -- new treshold written therefore drive write of threshold out NEW_THRESH_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then irqthresh_wren <= '0'; -- If AXI Lite write to DMACR and threshold different than current -- setting then update threshold value elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then irqthresh_wren <= '1'; else irqthresh_wren <= '0'; end if; end if; end process NEW_THRESH_WRITE; ------------------------------------------------------------------------------- -- DMACR - Remainder of DMA Control Register, Key Hole write bit (3) ------------------------------------------------------------------------------- DMACR_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 downto DMACR_RESERVED5_BIT) <= (others => '0'); elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15 downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT) -- bit 14 & axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 13 & axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 12 & axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bits 11 downto 3 & ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT); end if; end if; end process DMACR_REGISTER; DMACR_REGISTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then dmacr_i(DMACR_KH_BIT) <= '0'; dmacr_i(CYCLIC_BIT) <= '0'; elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT); dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT); end if; end if; end process DMACR_REGISTER1; ------------------------------------------------------------------------------- -- DMACR - Reset Bit ------------------------------------------------------------------------------- DMACR_RESET : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(soft_reset_clr = '1')then dmacr_i(DMACR_RESET_BIT) <= '0'; -- If soft reset set in other channel then set -- reset bit here too elsif(soft_reset_in = '1')then dmacr_i(DMACR_RESET_BIT) <= '1'; -- If DMACR Write then pass axi lite write bus to DMARC reset bit elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT); end if; end if; end process DMACR_RESET; soft_reset_i <= dmacr_i(DMACR_RESET_BIT); ------------------------------------------------------------------------------- -- Tail Pointer Enable fixed at 1 for this release of axi dma ------------------------------------------------------------------------------- dmacr_i(DMACR_TAILPEN_BIT) <= '1'; ------------------------------------------------------------------------------- -- DMACR - Run/Stop Bit ------------------------------------------------------------------------------- run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error or error_in = '1' -- S2MM Error or stop_dma = '1' -- Stop due to error or soft_reset_i = '1' -- MM2S Soft Reset or soft_reset_in = '1' -- S2MM Soft Reset else '0'; DMACR_RUNSTOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_RS_BIT) <= '0'; -- Clear on sg error (i.e. error) or other channel -- error (i.e. error_in) or dma error or soft reset elsif(run_stop_clr = '1')then dmacr_i(DMACR_RS_BIT) <= '0'; elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT); end if; end if; end process DMACR_RUNSTOP; --------------------------------------------------------------------------- -- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA -- channel is halted. --------------------------------------------------------------------------- DMASR_HALTED : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or halted_set = '1')then halted <= '1'; elsif(halted_clr = '1')then halted <= '0'; end if; end if; end process DMASR_HALTED; --------------------------------------------------------------------------- -- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA -- channel is IDLE waiting at tail pointer. Update of Tail Pointer -- will cause engine to resume. Note: Halted channels return to a -- reset condition. --------------------------------------------------------------------------- DMASR_IDLE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or idle_clr = '1' or halted_set = '1')then idle <= '0'; elsif(idle_set = '1')then idle <= '1'; end if; end if; end process DMASR_IDLE; --------------------------------------------------------------------------- -- DMA Status Error bit (BIT 3) -- Note: any error will cause entire engine to halt --------------------------------------------------------------------------- error <= dma_interr or dma_slverr or dma_decerr or sg_interr or sg_slverr or sg_decerr; -- Scatter Gather Error --sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set; -- SG Update Errors or DMA errors assert flag on descriptor update -- Used to latch current descriptor pointer --sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set -- or dma_interr or dma_slverr or dma_decerr; -- Map out to halt opposing channel error_out <= error; SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_ftch_error <= '0'; sg_updt_error <= '0'; else sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set; sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set or dma_interr or dma_slverr or dma_decerr; end if; end if; end process SG_FTCH_ERROR_PROC; --------------------------------------------------------------------------- -- DMA Status DMA Internal Error bit (BIT 4) --------------------------------------------------------------------------- DMASR_DMAINTERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_interr <= '0'; elsif(dma_interr_set = '1' )then dma_interr <= '1'; end if; end if; end process DMASR_DMAINTERR; --------------------------------------------------------------------------- -- DMA Status DMA Slave Error bit (BIT 5) --------------------------------------------------------------------------- DMASR_DMASLVERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_slverr <= '0'; elsif(dma_slverr_set = '1' )then dma_slverr <= '1'; end if; end if; end process DMASR_DMASLVERR; --------------------------------------------------------------------------- -- DMA Status DMA Decode Error bit (BIT 6) --------------------------------------------------------------------------- DMASR_DMADECERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_decerr <= '0'; elsif(dma_decerr_set = '1' )then dma_decerr <= '1'; end if; end if; end process DMASR_DMADECERR; --------------------------------------------------------------------------- -- DMA Status SG Internal Error bit (BIT 8) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGINTERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_interr <= '0'; elsif(ftch_interr_set = '1' or updt_interr_set = '1')then sg_interr <= '1'; end if; end if; end process DMASR_SGINTERR; --------------------------------------------------------------------------- -- DMA Status SG Slave Error bit (BIT 9) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGSLVERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_slverr <= '0'; elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then sg_slverr <= '1'; end if; end if; end process DMASR_SGSLVERR; --------------------------------------------------------------------------- -- DMA Status SG Decode Error bit (BIT 10) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGDECERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_decerr <= '0'; elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then sg_decerr <= '1'; end if; end if; end process DMASR_SGDECERR; --------------------------------------------------------------------------- -- DMA Status IOC Interrupt status bit (BIT 11) --------------------------------------------------------------------------- DMASR_IOCIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then ioc_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT))) or ioc_irq_set; elsif(ioc_irq_set = '1')then ioc_irq <= '1'; end if; end if; end process DMASR_IOCIRQ; --------------------------------------------------------------------------- -- DMA Status Delay Interrupt status bit (BIT 12) --------------------------------------------------------------------------- DMASR_DLYIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dly_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT))) or dly_irq_set; elsif(dly_irq_set = '1')then dly_irq <= '1'; end if; end if; end process DMASR_DLYIRQ; -- CR605888 Disable delay timer if halted or on delay irq set --dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348 dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348 or dmasr_i(DMASR_DLYIRQ_BIT); --------------------------------------------------------------------------- -- DMA Status Error Interrupt status bit (BIT 12) --------------------------------------------------------------------------- -- Delay error setting for generation of error strobe GEN_ERROR_RE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then error_d1 <= '0'; else error_d1 <= error; end if; end if; end process GEN_ERROR_RE; -- Generate rising edge pulse on error error_re <= error and not error_d1; DMASR_ERRIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then err_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT))) or error_re; elsif(error_re = '1')then err_irq <= '1'; end if; end if; end process DMASR_ERRIRQ; --------------------------------------------------------------------------- -- DMA Interrupt OUT --------------------------------------------------------------------------- REG_INTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then introut <= '0'; else introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT)) or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT)) or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT)); end if; end if; end process; --------------------------------------------------------------------------- -- DMA Status Register --------------------------------------------------------------------------- dmasr_i <= irqdelay_status -- Bits 31 downto 24 & irqthresh_status -- Bits 23 downto 16 & '0' -- Bit 15 & err_irq -- Bit 14 & dly_irq -- Bit 13 & ioc_irq -- Bit 12 & '0' -- Bit 11 & sg_decerr -- Bit 10 & sg_slverr -- Bit 9 & sg_interr -- Bit 8 & '0' -- Bit 7 & dma_decerr -- Bit 6 & dma_slverr -- Bit 5 & dma_interr -- Bit 4 & DMA_CONFIG -- Bit 3 & '0' -- Bit 2 & idle -- Bit 1 & halted; -- Bit 0 -- Generate current descriptor and tail descriptor register for Scatter Gather Mode GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate begin GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate begin MM2S_SGCTL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_cache_info <= "00000011"; --(others => '0'); elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0); else sg_cache_info <= sg_cache_info; end if; end if; end process MM2S_SGCTL; sg_ctl <= sg_cache_info; end generate GEN_SG_CTL_REG; GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate begin sg_ctl <= "00000011"; --(others => '0'); end generate GEN_SG_NO_CTL_REG; -- Signals not used for Scatter Gather Mode, only simple mode buffer_address_i <= (others => '0'); buffer_length_i <= (others => '0'); buffer_length_wren <= '0'; --------------------------------------------------------------------------- -- Current Descriptor LSB Register --------------------------------------------------------------------------- CURDESC_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc_lsb_i <= (others => '0'); error_pointer_set <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6); error_pointer_set <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest0 = '1')then -- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6); error_pointer_set <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and halt_free = '1')then curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT); -- & ZERO_VALUE(CURDESC_RESERVED_BIT5 -- downto CURDESC_RESERVED_BIT0); error_pointer_set <= '0'; end if; end if; end if; end process CURDESC_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT); -- & ZERO_VALUE(TAILDESC_RESERVED_BIT5 -- downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC_LSB_REGISTER; GEN_DESC1_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate CURDESC1_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc1_lsb_i <= (others => '0'); error_pointer_set1 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set1 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then curdesc1_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set1 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest1 = '1')then -- curdesc1_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set1 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then curdesc1_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set1 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC1_LSB_INDEX) = '1' and halt_free = '1')then curdesc1_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set1 <= '0'; end if; end if; end if; end process CURDESC1_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC1_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc1_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC1_LSB_INDEX) = '1')then taildesc1_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC1_LSB_REGISTER; end generate GEN_DESC1_REG_FOR_SG; GEN_DESC2_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate CURDESC2_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc2_lsb_i <= (others => '0'); error_pointer_set2 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set2 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then curdesc2_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set2 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest2 = '1')then -- curdesc2_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set2 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then curdesc2_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set2 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC2_LSB_INDEX) = '1' and halt_free = '1')then curdesc2_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set2 <= '0'; end if; end if; end if; end process CURDESC2_LSB_REGISTER; TAILDESC2_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc2_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC2_LSB_INDEX) = '1')then taildesc2_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC2_LSB_REGISTER; end generate GEN_DESC2_REG_FOR_SG; GEN_DESC3_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate CURDESC3_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc3_lsb_i <= (others => '0'); error_pointer_set3 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set3 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then curdesc3_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set3 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest3 = '1')then -- curdesc3_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set3 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then curdesc3_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set3 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC3_LSB_INDEX) = '1' and halt_free = '1')then curdesc3_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set3 <= '0'; end if; end if; end if; end process CURDESC3_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC3_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc3_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC3_LSB_INDEX) = '1')then taildesc3_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC3_LSB_REGISTER; end generate GEN_DESC3_REG_FOR_SG; GEN_DESC4_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate CURDESC4_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc4_lsb_i <= (others => '0'); error_pointer_set4 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set4 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then curdesc4_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set4 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest4 = '1')then -- curdesc4_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set4 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then curdesc4_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set4 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC4_LSB_INDEX) = '1' and halt_free = '1')then curdesc4_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set4 <= '0'; end if; end if; end if; end process CURDESC4_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC4_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc4_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC4_LSB_INDEX) = '1')then taildesc4_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC4_LSB_REGISTER; end generate GEN_DESC4_REG_FOR_SG; GEN_DESC5_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate CURDESC5_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc5_lsb_i <= (others => '0'); error_pointer_set5 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set5 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then curdesc5_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set5 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest5 = '1')then -- curdesc5_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set5 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then curdesc5_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set5 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC5_LSB_INDEX) = '1' and halt_free = '1')then curdesc5_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set5 <= '0'; end if; end if; end if; end process CURDESC5_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC5_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc5_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC5_LSB_INDEX) = '1')then taildesc5_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC5_LSB_REGISTER; end generate GEN_DESC5_REG_FOR_SG; GEN_DESC6_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate CURDESC6_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc6_lsb_i <= (others => '0'); error_pointer_set6 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set6 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then curdesc6_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set6 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest6 = '1')then -- curdesc6_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set6 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then curdesc6_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set6 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC6_LSB_INDEX) = '1' and halt_free = '1')then curdesc6_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set6 <= '0'; end if; end if; end if; end process CURDESC6_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC6_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc6_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC6_LSB_INDEX) = '1')then taildesc6_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC6_LSB_REGISTER; end generate GEN_DESC6_REG_FOR_SG; GEN_DESC7_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate CURDESC7_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc7_lsb_i <= (others => '0'); error_pointer_set7 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set7 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then curdesc7_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set7 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest7 = '1')then -- curdesc7_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set7 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then curdesc7_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set7 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC7_LSB_INDEX) = '1' and halt_free = '1')then curdesc7_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set7 <= '0'; end if; end if; end if; end process CURDESC7_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC7_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc7_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC7_LSB_INDEX) = '1')then taildesc7_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC7_LSB_REGISTER; end generate GEN_DESC7_REG_FOR_SG; GEN_DESC8_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate CURDESC8_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc8_lsb_i <= (others => '0'); error_pointer_set8 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set8 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then curdesc8_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set8 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest8 = '1')then -- curdesc8_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set8 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then curdesc8_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set8 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC8_LSB_INDEX) = '1' and halt_free = '1')then curdesc8_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set8 <= '0'; end if; end if; end if; end process CURDESC8_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC8_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc8_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC8_LSB_INDEX) = '1')then taildesc8_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC8_LSB_REGISTER; end generate GEN_DESC8_REG_FOR_SG; GEN_DESC9_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate CURDESC9_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc9_lsb_i <= (others => '0'); error_pointer_set9 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set9 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then curdesc9_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set9 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest9 = '1')then -- curdesc9_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set9 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then curdesc9_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set9 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC9_LSB_INDEX) = '1' and halt_free = '1')then curdesc9_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set9 <= '0'; end if; end if; end if; end process CURDESC9_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC9_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc9_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC9_LSB_INDEX) = '1')then taildesc9_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC9_LSB_REGISTER; end generate GEN_DESC9_REG_FOR_SG; GEN_DESC10_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate CURDESC10_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc10_lsb_i <= (others => '0'); error_pointer_set10 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set10 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then curdesc10_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set10 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest10 = '1')then -- curdesc10_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set10 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then curdesc10_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set10 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC10_LSB_INDEX) = '1' and halt_free = '1')then curdesc10_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set10 <= '0'; end if; end if; end if; end process CURDESC10_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC10_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc10_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC10_LSB_INDEX) = '1')then taildesc10_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC10_LSB_REGISTER; end generate GEN_DESC10_REG_FOR_SG; GEN_DESC11_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate CURDESC11_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc11_lsb_i <= (others => '0'); error_pointer_set11 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set11 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then curdesc11_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set11 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest11 = '1')then -- curdesc11_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set11 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then curdesc11_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set11 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC11_LSB_INDEX) = '1' and halt_free = '1')then curdesc11_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set11 <= '0'; end if; end if; end if; end process CURDESC11_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC11_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc11_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC11_LSB_INDEX) = '1')then taildesc11_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC11_LSB_REGISTER; end generate GEN_DESC11_REG_FOR_SG; GEN_DESC12_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate CURDESC12_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc12_lsb_i <= (others => '0'); error_pointer_set12 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set12 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then curdesc12_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set12 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest12 = '1')then -- curdesc12_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set12 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then curdesc12_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set12 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC12_LSB_INDEX) = '1' and halt_free = '1')then curdesc12_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set12 <= '0'; end if; end if; end if; end process CURDESC12_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC12_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc12_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC12_LSB_INDEX) = '1')then taildesc12_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC12_LSB_REGISTER; end generate GEN_DESC12_REG_FOR_SG; GEN_DESC13_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate CURDESC13_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc13_lsb_i <= (others => '0'); error_pointer_set13 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set13 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then curdesc13_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set13 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest13 = '1')then -- curdesc13_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set13 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then curdesc13_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set13 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC13_LSB_INDEX) = '1' and halt_free = '1')then curdesc13_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set13 <= '0'; end if; end if; end if; end process CURDESC13_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC13_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc13_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC13_LSB_INDEX) = '1')then taildesc13_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC13_LSB_REGISTER; end generate GEN_DESC13_REG_FOR_SG; GEN_DESC14_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate CURDESC14_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc14_lsb_i <= (others => '0'); error_pointer_set14 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set14 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then curdesc14_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set14 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest14 = '1')then -- curdesc14_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set14 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then curdesc14_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set14 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC14_LSB_INDEX) = '1' and halt_free = '1')then curdesc14_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set14 <= '0'; end if; end if; end if; end process CURDESC14_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC14_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc14_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC14_LSB_INDEX) = '1')then taildesc14_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC14_LSB_REGISTER; end generate GEN_DESC14_REG_FOR_SG; GEN_DESC15_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate CURDESC15_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc15_lsb_i <= (others => '0'); error_pointer_set15 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set15 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then curdesc15_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set15 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest15 = '1')then -- curdesc15_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set15 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then curdesc15_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set15 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC15_LSB_INDEX) = '1' and halt_free = '1')then curdesc15_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set15 <= '0'; end if; end if; end if; end process CURDESC15_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC15_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc15_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC15_LSB_INDEX) = '1')then taildesc15_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC15_LSB_REGISTER; end generate GEN_DESC15_REG_FOR_SG; --------------------------------------------------------------------------- -- Current Descriptor MSB Register --------------------------------------------------------------------------- -- Scatter Gather Interface configured for 64-Bit SG Addresses GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin CURDESC_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc_msb_i <= (others => '0'); elsif(error_pointer_set = '0')then -- Scatter Gather Fetch Error if(sg_ftch_error = '1' and dest0 = '1')then curdesc_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error elsif(sg_updt_error = '1' and dest0 = '1')then curdesc_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then curdesc_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and halt_free = '1')then curdesc_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then taildesc_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC_MSB_REGISTER; GEN_DESC1_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate CURDESC1_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc1_msb_i <= (others => '0'); elsif(error_pointer_set1 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then curdesc1_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest1 = '1')then -- curdesc1_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then curdesc1_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC1_MSB_INDEX) = '1' and halt_free = '1')then curdesc1_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC1_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC1_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc1_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC1_MSB_INDEX) = '1')then taildesc1_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC1_MSB_REGISTER; end generate GEN_DESC1_MSB_FOR_SG; GEN_DESC2_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate CURDESC2_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc2_msb_i <= (others => '0'); elsif(error_pointer_set2 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then curdesc2_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest2 = '1')then -- curdesc2_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then curdesc2_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC2_MSB_INDEX) = '1' and halt_free = '1')then curdesc2_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC2_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC2_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc2_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC2_MSB_INDEX) = '1')then taildesc2_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC2_MSB_REGISTER; end generate GEN_DESC2_MSB_FOR_SG; GEN_DESC3_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate CURDESC3_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc3_msb_i <= (others => '0'); elsif(error_pointer_set3 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then curdesc3_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest3 = '1')then -- curdesc3_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then curdesc3_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC3_MSB_INDEX) = '1' and halt_free = '1')then curdesc3_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC3_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC3_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc3_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC3_MSB_INDEX) = '1')then taildesc3_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC3_MSB_REGISTER; end generate GEN_DESC3_MSB_FOR_SG; GEN_DESC4_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate CURDESC4_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc4_msb_i <= (others => '0'); elsif(error_pointer_set4 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then curdesc4_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest4 = '1')then -- curdesc4_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then curdesc4_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC4_MSB_INDEX) = '1' and halt_free = '1')then curdesc4_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC4_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC4_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc4_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC4_MSB_INDEX) = '1')then taildesc4_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC4_MSB_REGISTER; end generate GEN_DESC4_MSB_FOR_SG; GEN_DESC5_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate CURDESC5_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc5_msb_i <= (others => '0'); elsif(error_pointer_set5 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then curdesc5_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest5 = '1')then -- curdesc5_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then curdesc5_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC5_MSB_INDEX) = '1' and halt_free = '1')then curdesc5_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC5_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC5_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc5_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC5_MSB_INDEX) = '1')then taildesc5_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC5_MSB_REGISTER; end generate GEN_DESC5_MSB_FOR_SG; GEN_DESC6_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate CURDESC6_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc6_msb_i <= (others => '0'); elsif(error_pointer_set6 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then curdesc6_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest6 = '1')then -- curdesc6_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then curdesc6_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC6_MSB_INDEX) = '1' and halt_free = '1')then curdesc6_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC6_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC6_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc6_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC6_MSB_INDEX) = '1')then taildesc6_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC6_MSB_REGISTER; end generate GEN_DESC6_MSB_FOR_SG; GEN_DESC7_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate CURDESC7_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc7_msb_i <= (others => '0'); elsif(error_pointer_set7 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then curdesc7_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest7 = '1')then -- curdesc7_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then curdesc7_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC7_MSB_INDEX) = '1' and halt_free = '1')then curdesc7_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC7_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC7_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc7_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC7_MSB_INDEX) = '1')then taildesc7_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC7_MSB_REGISTER; end generate GEN_DESC7_MSB_FOR_SG; GEN_DESC8_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate CURDESC8_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc8_msb_i <= (others => '0'); elsif(error_pointer_set8 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then curdesc8_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest8 = '1')then -- curdesc8_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then curdesc8_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC8_MSB_INDEX) = '1' and halt_free = '1')then curdesc8_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC8_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC8_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc8_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC8_MSB_INDEX) = '1')then taildesc8_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC8_MSB_REGISTER; end generate GEN_DESC8_MSB_FOR_SG; GEN_DESC9_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate CURDESC9_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc9_msb_i <= (others => '0'); elsif(error_pointer_set9 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then curdesc9_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest9 = '1')then -- curdesc9_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then curdesc9_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC9_MSB_INDEX) = '1' and halt_free = '1')then curdesc9_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC9_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC9_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc9_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC9_MSB_INDEX) = '1')then taildesc9_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC9_MSB_REGISTER; end generate GEN_DESC9_MSB_FOR_SG; GEN_DESC10_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate CURDESC10_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc10_msb_i <= (others => '0'); elsif(error_pointer_set10 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then curdesc10_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest10 = '1')then -- curdesc10_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then curdesc10_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC10_MSB_INDEX) = '1' and halt_free = '1')then curdesc10_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC10_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC10_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc10_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC10_MSB_INDEX) = '1')then taildesc10_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC10_MSB_REGISTER; end generate GEN_DESC10_MSB_FOR_SG; GEN_DESC11_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate CURDESC11_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc11_msb_i <= (others => '0'); elsif(error_pointer_set11 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then curdesc11_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest11 = '1')then -- curdesc11_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then curdesc11_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC11_MSB_INDEX) = '1' and halt_free = '1')then curdesc11_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC11_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC11_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc11_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC11_MSB_INDEX) = '1')then taildesc11_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC11_MSB_REGISTER; end generate GEN_DESC11_MSB_FOR_SG; GEN_DESC12_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate CURDESC12_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc12_msb_i <= (others => '0'); elsif(error_pointer_set12 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then curdesc12_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest12 = '1')then -- curdesc12_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then curdesc12_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC12_MSB_INDEX) = '1' and halt_free = '1')then curdesc12_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC12_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC12_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc12_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC12_MSB_INDEX) = '1')then taildesc12_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC12_MSB_REGISTER; end generate GEN_DESC12_MSB_FOR_SG; GEN_DESC13_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate CURDESC13_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc13_msb_i <= (others => '0'); elsif(error_pointer_set13 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then curdesc13_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest13 = '1')then -- curdesc13_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then curdesc13_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC13_MSB_INDEX) = '1' and halt_free = '1')then curdesc13_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC13_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC13_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc13_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC13_MSB_INDEX) = '1')then taildesc13_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC13_MSB_REGISTER; end generate GEN_DESC13_MSB_FOR_SG; GEN_DESC14_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate CURDESC14_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc14_msb_i <= (others => '0'); elsif(error_pointer_set14 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then curdesc14_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest14 = '1')then -- curdesc14_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then curdesc14_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC14_MSB_INDEX) = '1' and halt_free = '1')then curdesc14_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC14_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC14_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc14_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC14_MSB_INDEX) = '1')then taildesc14_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC14_MSB_REGISTER; end generate GEN_DESC14_MSB_FOR_SG; GEN_DESC15_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate CURDESC15_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc15_msb_i <= (others => '0'); elsif(error_pointer_set15 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then curdesc15_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest15 = '1')then -- curdesc15_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then curdesc15_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC15_MSB_INDEX) = '1' and halt_free = '1')then curdesc15_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC15_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC15_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc15_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC15_MSB_INDEX) = '1')then taildesc15_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC15_MSB_REGISTER; end generate GEN_DESC15_MSB_FOR_SG; end generate GEN_SG_ADDR_EQL64; -- Scatter Gather Interface configured for 32-Bit SG Addresses GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin curdesc_msb_i <= (others => '0'); taildesc_msb_i <= (others => '0'); -- Extending this to the extra registers curdesc1_msb_i <= (others => '0'); taildesc1_msb_i <= (others => '0'); curdesc2_msb_i <= (others => '0'); taildesc2_msb_i <= (others => '0'); curdesc3_msb_i <= (others => '0'); taildesc3_msb_i <= (others => '0'); curdesc4_msb_i <= (others => '0'); taildesc4_msb_i <= (others => '0'); curdesc5_msb_i <= (others => '0'); taildesc5_msb_i <= (others => '0'); curdesc6_msb_i <= (others => '0'); taildesc6_msb_i <= (others => '0'); curdesc7_msb_i <= (others => '0'); taildesc7_msb_i <= (others => '0'); curdesc8_msb_i <= (others => '0'); taildesc8_msb_i <= (others => '0'); curdesc9_msb_i <= (others => '0'); taildesc9_msb_i <= (others => '0'); curdesc10_msb_i <= (others => '0'); taildesc10_msb_i <= (others => '0'); curdesc11_msb_i <= (others => '0'); taildesc11_msb_i <= (others => '0'); curdesc12_msb_i <= (others => '0'); taildesc12_msb_i <= (others => '0'); curdesc13_msb_i <= (others => '0'); taildesc13_msb_i <= (others => '0'); curdesc14_msb_i <= (others => '0'); taildesc14_msb_i <= (others => '0'); curdesc15_msb_i <= (others => '0'); taildesc15_msb_i <= (others => '0'); end generate GEN_SG_ADDR_EQL32; -- Scatter Gather Interface configured for 32-Bit SG Addresses GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin -- Added dest so that BD can be dynamically updated GENERATE_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0) or (axi2ip_wrce(TAILDESC1_LSB_INDEX) and dest1) or (axi2ip_wrce(TAILDESC2_LSB_INDEX) and dest2) or (axi2ip_wrce(TAILDESC3_LSB_INDEX) and dest3) or (axi2ip_wrce(TAILDESC4_LSB_INDEX) and dest4) or (axi2ip_wrce(TAILDESC5_LSB_INDEX) and dest5) or (axi2ip_wrce(TAILDESC6_LSB_INDEX) and dest6) or (axi2ip_wrce(TAILDESC7_LSB_INDEX) and dest7) or (axi2ip_wrce(TAILDESC8_LSB_INDEX) and dest8) or (axi2ip_wrce(TAILDESC9_LSB_INDEX) and dest9) or (axi2ip_wrce(TAILDESC10_LSB_INDEX) and dest10) or (axi2ip_wrce(TAILDESC11_LSB_INDEX) and dest11) or (axi2ip_wrce(TAILDESC12_LSB_INDEX) and dest12) or (axi2ip_wrce(TAILDESC13_LSB_INDEX) and dest13) or (axi2ip_wrce(TAILDESC14_LSB_INDEX) and dest14) or (axi2ip_wrce(TAILDESC15_LSB_INDEX) and dest15); end generate GENERATE_MULTI_CH; GENERATE_NO_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0); end generate GENERATE_NO_MULTI_CH; TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then tailpntr_updated_d1 <= '0'; elsif (tail_update_lsb = '1' and tdest_in(5) = '0')then tailpntr_updated_d1 <= '1'; else tailpntr_updated_d1 <= '0'; end if; end if; end process TAILPNTR_UPDT_PROCESS; TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tailpntr_updated_d2 <= '0'; else tailpntr_updated_d2 <= tailpntr_updated_d1; end if; end if; end process TAILPNTR_UPDT_PROCESS_DEL; tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2); end generate GEN_TAILUPDATE_EQL32; -- Scatter Gather Interface configured for 64-Bit SG Addresses GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin -- Added dest so that BD can be dynamically updated tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0) or (axi2ip_wrce(TAILDESC1_MSB_INDEX) and dest1) or (axi2ip_wrce(TAILDESC2_MSB_INDEX) and dest2) or (axi2ip_wrce(TAILDESC3_MSB_INDEX) and dest3) or (axi2ip_wrce(TAILDESC4_MSB_INDEX) and dest4) or (axi2ip_wrce(TAILDESC5_MSB_INDEX) and dest5) or (axi2ip_wrce(TAILDESC6_MSB_INDEX) and dest6) or (axi2ip_wrce(TAILDESC7_MSB_INDEX) and dest7) or (axi2ip_wrce(TAILDESC8_MSB_INDEX) and dest8) or (axi2ip_wrce(TAILDESC9_MSB_INDEX) and dest9) or (axi2ip_wrce(TAILDESC10_MSB_INDEX) and dest10) or (axi2ip_wrce(TAILDESC11_MSB_INDEX) and dest11) or (axi2ip_wrce(TAILDESC12_MSB_INDEX) and dest12) or (axi2ip_wrce(TAILDESC13_MSB_INDEX) and dest13) or (axi2ip_wrce(TAILDESC14_MSB_INDEX) and dest14) or (axi2ip_wrce(TAILDESC15_MSB_INDEX) and dest15); -- tail_update_msb <= axi2ip_wrce(TAILDESC_MSB_INDEX) or -- axi2ip_wrce(TAILDESC1_MSB_INDEX) or -- axi2ip_wrce(TAILDESC2_MSB_INDEX) or -- axi2ip_wrce(TAILDESC3_MSB_INDEX) or -- axi2ip_wrce(TAILDESC4_MSB_INDEX) or -- axi2ip_wrce(TAILDESC5_MSB_INDEX) or -- axi2ip_wrce(TAILDESC6_MSB_INDEX) or -- axi2ip_wrce(TAILDESC7_MSB_INDEX) or -- axi2ip_wrce(TAILDESC8_MSB_INDEX) or -- axi2ip_wrce(TAILDESC9_MSB_INDEX) or -- axi2ip_wrce(TAILDESC10_MSB_INDEX) or -- axi2ip_wrce(TAILDESC11_MSB_INDEX) or -- axi2ip_wrce(TAILDESC12_MSB_INDEX) or -- axi2ip_wrce(TAILDESC13_MSB_INDEX) or -- axi2ip_wrce(TAILDESC14_MSB_INDEX) or -- axi2ip_wrce(TAILDESC15_MSB_INDEX); TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then tailpntr_updated_d1 <= '0'; elsif (tail_update_msb = '1' and tdest_in(5) = '0')then tailpntr_updated_d1 <= '1'; else tailpntr_updated_d1 <= '0'; end if; end if; end process TAILPNTR_UPDT_PROCESS; TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tailpntr_updated_d2 <= '0'; else tailpntr_updated_d2 <= tailpntr_updated_d1; end if; end if; end process TAILPNTR_UPDT_PROCESS_DEL; tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2); end generate GEN_TAILUPDATE_EQL64; end generate GEN_DESC_REG_FOR_SG; -- Generate Buffer Address and Length Register for Simple DMA Mode GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate begin -- Signals not used for simple dma mode, only for sg mode curdesc_lsb_i <= (others => '0'); curdesc_msb_i <= (others => '0'); taildesc_lsb_i <= (others => '0'); taildesc_msb_i <= (others => '0'); -- Extending this to new registers curdesc1_msb_i <= (others => '0'); taildesc1_msb_i <= (others => '0'); curdesc2_msb_i <= (others => '0'); taildesc2_msb_i <= (others => '0'); curdesc3_msb_i <= (others => '0'); taildesc3_msb_i <= (others => '0'); curdesc4_msb_i <= (others => '0'); taildesc4_msb_i <= (others => '0'); curdesc5_msb_i <= (others => '0'); taildesc5_msb_i <= (others => '0'); curdesc6_msb_i <= (others => '0'); taildesc6_msb_i <= (others => '0'); curdesc7_msb_i <= (others => '0'); taildesc7_msb_i <= (others => '0'); curdesc8_msb_i <= (others => '0'); taildesc8_msb_i <= (others => '0'); curdesc9_msb_i <= (others => '0'); taildesc9_msb_i <= (others => '0'); curdesc10_msb_i <= (others => '0'); taildesc10_msb_i <= (others => '0'); curdesc11_msb_i <= (others => '0'); taildesc11_msb_i <= (others => '0'); curdesc12_msb_i <= (others => '0'); taildesc12_msb_i <= (others => '0'); curdesc13_msb_i <= (others => '0'); taildesc13_msb_i <= (others => '0'); curdesc14_msb_i <= (others => '0'); taildesc14_msb_i <= (others => '0'); curdesc15_msb_i <= (others => '0'); taildesc15_msb_i <= (others => '0'); curdesc1_lsb_i <= (others => '0'); taildesc1_lsb_i <= (others => '0'); curdesc2_lsb_i <= (others => '0'); taildesc2_lsb_i <= (others => '0'); curdesc3_lsb_i <= (others => '0'); taildesc3_lsb_i <= (others => '0'); curdesc4_lsb_i <= (others => '0'); taildesc4_lsb_i <= (others => '0'); curdesc5_lsb_i <= (others => '0'); taildesc5_lsb_i <= (others => '0'); curdesc6_lsb_i <= (others => '0'); taildesc6_lsb_i <= (others => '0'); curdesc7_lsb_i <= (others => '0'); taildesc7_lsb_i <= (others => '0'); curdesc8_lsb_i <= (others => '0'); taildesc8_lsb_i <= (others => '0'); curdesc9_lsb_i <= (others => '0'); taildesc9_lsb_i <= (others => '0'); curdesc10_lsb_i <= (others => '0'); taildesc10_lsb_i <= (others => '0'); curdesc11_lsb_i <= (others => '0'); taildesc11_lsb_i <= (others => '0'); curdesc12_lsb_i <= (others => '0'); taildesc12_lsb_i <= (others => '0'); curdesc13_lsb_i <= (others => '0'); taildesc13_lsb_i <= (others => '0'); curdesc14_lsb_i <= (others => '0'); taildesc14_lsb_i <= (others => '0'); curdesc15_lsb_i <= (others => '0'); taildesc15_lsb_i <= (others => '0'); tailpntr_updated <= '0'; error_pointer_set <= '0'; -- Buffer Address register. Used for Source Address (SA) if MM2S -- and used for Destination Address (DA) if S2MM BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_address_i <= (others => '0'); elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then buffer_address_i <= axi2ip_wrdata; end if; end if; end process BUFFER_ADDR_REGISTER; -- Buffer Length register. Used for number of bytes to transfer if MM2S -- and used for size of receive buffer is S2MM BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_length_i <= (others => '0'); -- Update with actual bytes received (Only for S2MM channel) elsif(bytes_received_wren = '1' and C_MICRO_DMA = 0)then buffer_length_i <= bytes_received; elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0); end if; end if; end process BUFFER_LNGTH_REGISTER; -- Buffer Length Write Enable control. Assertion of wren will -- begin a transfer if channel is Idle. BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_length_wren <= '0'; -- Non-zero length value written elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1' and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then buffer_length_wren <= '1'; else buffer_length_wren <= '0'; end if; end if; end process BUFFER_LNGTH_WRITE; end generate GEN_REG_FOR_SMPL; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/FIFO_image_filter_dmask_rows_V.vhd	2	4564	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_dmask_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_dmask_rows_V_shiftReg; architecture rtl of FIFO_image_filter_dmask_rows_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_dmask_rows_V is generic ( MEM_STYLE : string := "shiftreg"; DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_dmask_rows_V is component FIFO_image_filter_dmask_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_dmask_rows_V_shiftReg : FIFO_image_filter_dmask_rows_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
mistryalok/Zedboard	learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/ecc_gen.vhd	8	7490	---------------------------------------------------------------------------------------------- -- -- Generated by X-HDL Verilog Translator - Version 4.0.0 Apr. 30, 2006 -- Wed Jun 17 2009 01:03:24 -- -- Input file : /home/samsonn/SandBox_LBranch_11.2/env/Databases/ip/src2/L/mig_v3_2/data/dlib/virtex6/ddr3_sdram/verilog/rtl/ecc/ecc_gen.v -- Component name : ecc_gen -- Author : -- Company : -- -- Description : -- -- ---------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; -- Generate the ecc code. Note that the synthesizer should -- generate this as a static logic. Code in this block should -- never run during simulation phase, or directly impact timing. -- -- The code generated is a single correct, double detect code. -- It is the classic Hamming code. Instead, the code is -- optimized for minimal/balanced tree depth and size. See -- Hsiao IBM Technial Journal 1970. -- -- The code is returned as a single bit vector, h_rows. This was -- the only way to "subroutinize" this with the restrictions of -- disallowed include files and that matrices cannot be passed -- in ports. -- -- Factorial and the combos functions are defined. Combos -- simply computes the number of combinations from the set -- size and elements at a time. -- -- The function next_combo computes the next combination in -- lexicographical order given the "current" combination. Its -- output is undefined if given the last combination in the -- lexicographical order. -- -- next_combo is insensitive to the number of elements in the -- combinations. -- -- An H transpose matrix is generated because that's the easiest -- way to do it. The H transpose matrix is generated by taking -- the one at a time combinations, then the 3 at a time, then -- the 5 at a time. The number combinations used is equal to -- the width of the code (CODE_WIDTH). The boundaries between -- the 1, 3 and 5 groups are hardcoded in the for loop. -- -- At the same time the h_rows vector is generated from the -- H transpose matrix. entity ecc_gen is generic ( CODE_WIDTH : integer := 72; ECC_WIDTH : integer := 8; DATA_WIDTH : integer := 64 ); port ( -- Outputs -- function next_combo -- Given a combination, return the next combo in lexicographical -- order. Scans from right to left. Assumes the first combination -- is k ones all of the way to the left. -- -- Upon entry, initialize seen0, trig1, and ones. "seen0" means -- that a zero has been observed while scanning from right to left. -- "trig1" means that a one have been observed _after_ seen0 is set. -- "ones" counts the number of ones observed while scanning the input. -- -- If trig1 is one, just copy the input bit to the output and increment -- to the next bit. Otherwise set the the output bit to zero, if the -- input is a one, increment ones. If the input bit is a one and seen0 -- is true, dump out the accumulated ones. Set seen0 to the complement -- of the input bit. Note that seen0 is not used subsequent to trig1 -- getting set. -- The stuff above leads to excessive XST execution times. For now, hardwire to 72/64 bit. h_rows : out std_logic_vector(CODE_WIDTH * ECC_WIDTH - 1 downto 0) ); end entity ecc_gen; architecture trans of ecc_gen is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of trans : architecture is "yes"; function factorial (ivar: integer) return integer is variable tmp : integer; begin if (ivar = 1) then return 1; else tmp := 1; for i in ivar downto 2 loop tmp := tmp * i; end loop; end if; return tmp; end function factorial; function combos ( n, k: integer) return integer is begin return factorial(n)/(factorial(k)factorial(n-k)); end function combos; function next_combo (i: std_logic_vector) return std_logic_vector is variable seen0: std_logic; variable trig1: std_logic; variable ones: std_logic_vector (ECC_WIDTH-1 downto 0); variable tmp: std_logic_vector (ECC_WIDTH-1 downto 0); variable tmp_index : integer; begin seen0 := '0'; trig1 := '0'; ones := (others => '0'); for index in ECC_WIDTH -1 downto 0 loop tmp_index := ECC_WIDTH -1 - index; if (trig1 = '1') then tmp(tmp_index) := i(tmp_index); else tmp(tmp_index) := '0'; ones := ones + i(tmp_index); if ((i(tmp_index) = '1') and (seen0 = '1')) then trig1 := '1'; for dump_index in tmp_index-1 downto 0 loop if (dump_index >= (tmp_index- conv_integer(ones)) ) then tmp(dump_index) := '1'; end if; end loop; end if; seen0 := not(i(tmp_index)); end if; end loop; return tmp; end function next_combo; constant COMBOS_3 : integer := combos(ECC_WIDTH, 3); constant COMBOS_5 : integer := combos(ECC_WIDTH, 5); type twoDarray is array (CODE_WIDTH -1 downto 0) of std_logic_vector (ECC_WIDTH-1 downto 0); signal ht_matrix : twoDarray; begin columns: for n in CODE_WIDTH - 1 downto 0 generate column0: if (n = 0) generate ht_matrix(n) <= "111" & conv_std_logic_vector(0,ECC_WIDTH-3); end generate; column_combos3: if ((n = COMBOS_3) and ( n < DATA_WIDTH) ) generate ht_matrix(n) <= "11111" & conv_std_logic_vector(0,ECC_WIDTH-5); end generate; column_combos5: if ((n = COMBOS_3 + COMBOS_5) and ( n < DATA_WIDTH) ) generate ht_matrix(n) <= "1111111" & conv_std_logic_vector(0,ECC_WIDTH-7); end generate; column_datawidth: if (n = DATA_WIDTH) generate ht_matrix(n) <= "1" & conv_std_logic_vector(0,ECC_WIDTH-1); end generate; column_gen: if ( (n /= 0 ) and ((n /= COMBOS_3) or (n > DATA_WIDTH)) and ((n /= COMBOS_3+COMBOS_5) or (n > DATA_WIDTH)) and (n /= DATA_WIDTH) ) generate ht_matrix(n) <= next_combo(ht_matrix(n-1)); end generate; out_assign: for s in ECC_WIDTH-1 downto 0 generate h_rows(sCODE_WIDTH+n) <= ht_matrix(n)(s); end generate; end generate; --h_row0 <= "100000000100100011101101001101001000110100100010000110100100010000100000"; --h_row1 <= "010000001010010011011010101010100100101010010001000101010010001000010000"; --h_row2 <= "001000001001001010110110010110010010011001001000100011001001000100001000"; --h_row3 <= "000100000111000101110001110001110001000111000100010000111000100010000100"; --h_row4 <= "000010000000111100001111110000001111000000111100001000000111100001000010"; --h_row5 <= "000001001111111100000000001111111111000000000011111000000000011111000001"; --h_row6 <= "000000101111111100000000000000000000111111111111111000000000000000111111"; --h_row7 <= "000000011111111100000000000000000000000000000000000111111111111111111111"; --h_rows <= (h_row7 & h_row6 & h_row5 & h_row4 & h_row3 & h_row2 & h_row1 & h_row0); end architecture trans;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_s2mm.vhd	3	17013	-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; library lib_fifo_v1_0; use lib_fifo_v1_0.async_fifo_fg; entity axi_dma_s2mm is generic ( C_FAMILY : string := "virtex7" ); port ( clk_in : in std_logic; sg_clk : in std_logic; resetn : in std_logic; reset_sg : in std_logic; s2mm_tvalid : in std_logic; s2mm_tlast : in std_logic; s2mm_tdest : in std_logic_vector (4 downto 0); s2mm_tuser : in std_logic_vector (3 downto 0); s2mm_tid : in std_logic_vector (4 downto 0); s2mm_tready : in std_logic; desc_available : in std_logic; -- s2mm_eof : in std_logic; s2mm_eof_det : in std_logic_vector (1 downto 0); ch2_update_active : in std_logic; tdest_out : out std_logic_vector (6 downto 0); -- to select desc same_tdest : out std_logic; -- to select desc -- to DM s2mm_desc_info : out std_logic_vector (13 downto 0); -- updt_cmpt : out std_logic; s2mm_tvalid_out : out std_logic; s2mm_tlast_out : out std_logic; s2mm_tready_out : out std_logic; s2mm_tdest_out : out std_logic_vector (4 downto 0) ); end entity axi_dma_s2mm; architecture implementation of axi_dma_s2mm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; signal first_data : std_logic; signal first_stream : std_logic; signal first_stream_del : std_logic; signal last_received : std_logic; signal first_received : std_logic; signal first_received1 : std_logic; signal open_window : std_logic; signal tdest_out_int : std_logic_vector (6 downto 0); signal fifo_wr : std_logic; signal last_update_over_int : std_logic; signal last_update_over_int1 : std_logic; signal last_update_over : std_logic; signal ch_updt_over_int : std_logic; signal ch_updt_over_int_cdc_from : std_logic; signal ch_updt_over_int_cdc_to : std_logic; signal ch_updt_over_int_cdc_to1 : std_logic; signal ch_updt_over_int_cdc_to2 : std_logic; -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; --ATTRIBUTE async_reg OF ch_updt_over_int_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF ch_updt_over_int_cdc_to1 : SIGNAL IS "true"; signal fifo_rd : std_logic; signal first_read : std_logic; signal first_rd_en : std_logic; signal fifo_rd_int : std_logic; signal first_read_int : std_logic; signal fifo_empty : std_logic; signal fifo_full : std_logic; signal s2mm_desc_info_int : std_logic_vector (13 downto 0); signal updt_cmpt : std_logic; signal tdest_capture : std_logic_vector (4 downto 0); signal noread : std_logic; signal same_tdest_b2b : std_logic; signal fifo_reset : std_logic; begin process (sg_clk) begin if (sg_clk'event and sg_clk = '1') then if (reset_sg = '0') then ch_updt_over_int_cdc_from <= '0'; else --if (sg_clk'event and sg_clk = '1') then ch_updt_over_int_cdc_from <= ch2_update_active; end if; end if; end process; process (clk_in) begin if (clk_in'event and clk_in = '1') then if (resetn = '0') then ch_updt_over_int_cdc_to <= '0'; ch_updt_over_int_cdc_to1 <= '0'; ch_updt_over_int_cdc_to2 <= '0'; else --if (clk_in'event and clk_in = '1') then ch_updt_over_int_cdc_to <= ch_updt_over_int_cdc_from; ch_updt_over_int_cdc_to1 <= ch_updt_over_int_cdc_to; ch_updt_over_int_cdc_to2 <= ch_updt_over_int_cdc_to1; end if; end if; end process; updt_cmpt <= (not ch_updt_over_int_cdc_to1) and ch_updt_over_int_cdc_to2; -- process (sg_clk) -- begin -- if (resetn = '0') then -- ch_updt_over_int <= '0'; -- elsif (sg_clk'event and sg_clk = '1') then -- ch_updt_over_int <= ch2_update_active; -- end if; -- end process; -- updt_cmpt <= (not ch2_update_active) and ch_updt_over_int; process (sg_clk) begin if (sg_clk'event and sg_clk = '1') then if (reset_sg = '0') then last_update_over_int <= '0'; last_update_over_int1 <= '0'; noread <= '0'; -- else --if (sg_clk'event and sg_clk = '1') then last_update_over_int1 <= last_update_over_int; elsif (s2mm_eof_det(1) = '1' and noread = '0') then last_update_over_int <= '1'; noread <= '1'; elsif (s2mm_eof_det(0) = '1') then noread <= '0'; last_update_over_int <= '0'; elsif (fifo_empty = '0') then -- (updt_cmpt = '1') then last_update_over_int <= '0'; else last_update_over_int <= last_update_over_int; end if; end if; -- end if; end process; last_update_over <= (not last_update_over_int) and last_update_over_int1; process (sg_clk) begin if (sg_clk'event and sg_clk = '1') then if (reset_sg = '0') then fifo_rd_int <= '0'; first_read <= '0'; -- else --if (sg_clk'event and sg_clk = '1') then elsif (last_update_over_int = '1' and fifo_rd_int = '0') then fifo_rd_int <= '1'; else fifo_rd_int <= '0'; end if; end if; end process; process (sg_clk) begin if (sg_clk'event and sg_clk = '1') then if (reset_sg = '0') then first_read_int <= '0'; else --if (sg_clk'event and sg_clk = '1') then first_read_int <= first_read; end if; end if; end process; first_rd_en <= first_read and (not first_read_int); fifo_rd <= last_update_over_int; --(fifo_rd_int or first_rd_en); -- process (clk_in) -- begin -- if (resetn = '0') then -- first_data <= '0'; -- first_stream_del <= '0'; -- elsif (clk_in'event and clk_in = '1') then -- if (s2mm_tvalid = '1' and first_data = '0' and s2mm_tready = '1') then -- no tlast -- first_data <= '1'; -- just after the system comes out of reset -- end if; -- first_stream_del <= first_stream; -- end if; -- end process; first_stream <= (s2mm_tvalid and (not first_data)); -- pulse when first stream comes after reset process (clk_in) begin if (clk_in'event and clk_in = '1') then if (resetn = '0') then first_received1 <= '0'; first_stream_del <= '0'; else --if (clk_in'event and clk_in = '1') then first_received1 <= first_received; --'0'; first_stream_del <= first_stream; end if; end if; end process; process (clk_in) begin if (clk_in'event and clk_in = '1') then if (resetn = '0') then last_received <= '0'; first_received <= '0'; tdest_capture <= (others => '0'); first_data <= '0'; -- else --if (clk_in'event and clk_in = '1') then elsif (s2mm_tvalid = '1' and first_data = '0' and s2mm_tready = '1') then -- first stream afetr reset s2mm_desc_info_int <= s2mm_tuser & s2mm_tid & s2mm_tdest; tdest_capture <= s2mm_tdest; -- latching tdest on first beat first_data <= '1'; -- just after the system comes out of reset elsif (s2mm_tlast = '1' and s2mm_tvalid = '1' and s2mm_tready = '1') then -- catch for last beat last_received <= '1'; first_received <= '0'; s2mm_desc_info_int <= s2mm_desc_info_int; elsif (last_received = '1' and s2mm_tvalid = '1' and s2mm_tready = '1') then -- catch for following first beat last_received <= '0'; first_received <= '1'; tdest_capture <= s2mm_tdest; -- latching tdest on first beat s2mm_desc_info_int <= s2mm_tuser & s2mm_tid & s2mm_tdest; else s2mm_desc_info_int <= s2mm_desc_info_int; last_received <= last_received; if (updt_cmpt = '1') then first_received <= '0'; else first_received <= first_received; -- hold the first received until update comes for previous tlast end if; end if; end if; end process; fifo_wr <= first_stream_del or (first_received and not (first_received1)); -- writing the tdest,tuser,tid into FIFO process (clk_in) begin if (clk_in'event and clk_in = '1') then if (resetn = '0') then tdest_out_int <= "0100000"; same_tdest_b2b <= '0'; -- else --if (clk_in'event and clk_in = '1') then elsif (first_received = '1' or first_stream = '1') then if (first_stream = '1') then -- when first stream is received, capture the tdest tdest_out_int (6) <= not tdest_out_int (6); -- signifies a new stream has come tdest_out_int (5 downto 0) <= '0' & s2mm_tdest; same_tdest_b2b <= '0'; -- elsif (updt_cmpt = '1' or (first_received = '1' and first_received1 = '0')) then -- when subsequent streams are received, pass the latched value of tdest -- elsif (first_received = '1' and first_received1 = '0') then -- when subsequent streams are received, pass the latched value of tdest -- Following change made to allow b2b same channel pkt elsif ((first_received = '1' and first_received1 = '0') and (tdest_out_int (4 downto 0) /= tdest_capture)) then -- when subsequent streams are received, pass the latched value of tdest tdest_out_int (6) <= not tdest_out_int (6); tdest_out_int (5 downto 0) <= '0' & tdest_capture; --s2mm_tdest; elsif (first_received = '1' and first_received1 = '0') then same_tdest_b2b <= not (same_tdest_b2b); end if; else tdest_out_int <= tdest_out_int; end if; end if; end process; tdest_out <= tdest_out_int; same_tdest <= same_tdest_b2b; process (clk_in) begin if (clk_in'event and clk_in = '1') then if (resetn = '0') then open_window <= '0'; -- else --if (clk_in'event and clk_in = '1') then elsif (desc_available = '1') then open_window <= '1'; elsif (s2mm_tlast = '1') then open_window <= '0'; else open_window <= open_window; end if; end if; end process; process (clk_in) begin if (clk_in'event and clk_in = '1') then if (resetn = '0') then s2mm_tvalid_out <= '0'; s2mm_tready_out <= '0'; s2mm_tlast_out <= '0'; s2mm_tdest_out <= "00000"; -- else --if (clk_in'event and clk_in = '1') then elsif (open_window = '1') then s2mm_tvalid_out <= s2mm_tvalid; s2mm_tready_out <= s2mm_tready; s2mm_tlast_out <= s2mm_tlast; s2mm_tdest_out <= s2mm_tdest; else s2mm_tready_out <= '0'; s2mm_tvalid_out <= '0'; s2mm_tlast_out <= '0'; s2mm_tdest_out <= "00000"; end if; end if; end process; fifo_reset <= not (resetn); -- s2mm_desc_info_int <= s2mm_tuser & s2mm_tid & s2mm_tdest; -- Following FIFO is used to store the Tuser, Tid and xCache info I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.async_fifo_fg generic map ( -- C_ALLOW_2N_DEPTH => 1, C_ALLOW_2N_DEPTH => 0, C_FAMILY => C_FAMILY, C_DATA_WIDTH => 14, C_ENABLE_RLOCS => 0, C_FIFO_DEPTH => 31, C_HAS_ALMOST_EMPTY => 1, C_HAS_ALMOST_FULL => 1, C_HAS_RD_ACK => 1, C_HAS_RD_COUNT => 1, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 0, C_HAS_WR_COUNT => 1, C_HAS_WR_ERR => 0, C_RD_ACK_LOW => 0, C_RD_COUNT_WIDTH => 5, C_RD_ERR_LOW => 0, C_USE_BLOCKMEM => 0, C_WR_ACK_LOW => 0, C_WR_COUNT_WIDTH => 5, C_WR_ERR_LOW => 0, C_SYNCHRONIZER_STAGE => C_FIFO_MTBF -- C_USE_EMBEDDED_REG => 1, -- 0 ; -- C_PRELOAD_REGS => 0, -- 0 ; -- C_PRELOAD_LATENCY => 1 -- 1 ; ) port Map ( Din => s2mm_desc_info_int, Wr_en => fifo_wr, Wr_clk => clk_in, Rd_en => fifo_rd, Rd_clk => sg_clk, Ainit => fifo_reset, Dout => s2mm_desc_info, Full => fifo_Full, Empty => fifo_empty, Almost_full => open, Almost_empty => open, Wr_count => open, Rd_count => open, Rd_ack => open, Rd_err => open, -- Not used by axi_dma Wr_ack => open, -- Not used by axi_dma Wr_err => open -- Not used by axi_dma ); end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/lib_srl_fifo_v1_0/292dd5ac/hdl/src/vhdl/srl_fifo_f.vhd	11	9367	-- srl_fifo_f - entity / architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: srl_fifo_f.vhd -- -- Description: A small-to-medium depth FIFO. For -- data storage, the SRL elements native to the -- target FGPA family are used. If the FIFO depth -- exceeds the available depth of the SRL elements, -- then SRLs are cascaded and MUXFN elements are -- used to select the output of the appropriate SRL stage. -- -- Features: -- - Width and depth are arbitrary, but each doubling of -- depth, starting from the native SRL depth, adds -- a level of MUXFN. Generally, in performance-oriented -- applications, the fifo depth may need to be limited to -- not exceed the SRL cascade depth supported by local -- fast interconnect or the number of MUXFN levels. -- However, deeper fifos will correctly build. -- - Commands: read, write. -- - Flags: empty and full. -- - The Addr output is always one less than the current -- occupancy when the FIFO is non-empty, and is all ones -- otherwise. Therefore, the value <FIFO_Empty, Addr>-- -- i.e. FIFO_Empty concatenated on the left to Addr-- -- when taken as a signed value, is one less than the -- current occupancy. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- srl_fifo_f.vhd -- srl_fifo_rbu_f.vhd -- proc_common_pkg.vhd -- ------------------------------------------------------------------------------- -- Author: Farrell Ostler -- -- History: -- FLO 12/13/05 First Version. -- -- FLO 04/27/06 -- ^^^^^^ -- C_FAMILY made to default to "nofamily". -- ~~~~~~ -- FLO 2007-12-12 -- ^^^^^^ -- Using function clog2 now instead of log2 to eliminate superfluous warnings. -- ~~~~~~ -- -- DET 1/17/2008 v5_0 -- ~~~~~~ -- - Changed proc_common library version to v5_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- -- predecessor value by # clks: "_p#" library ieee; use ieee.std_logic_1164.all; library lib_srl_fifo_v1_0; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.clog2; -- entity srl_fifo_f is generic ( C_DWIDTH : natural; C_DEPTH : positive := 16; C_FAMILY : string := "nofamily" ); port ( Clk : in std_logic; Reset : in std_logic; FIFO_Write : in std_logic; Data_In : in std_logic_vector(0 to C_DWIDTH-1); FIFO_Read : in std_logic; Data_Out : out std_logic_vector(0 to C_DWIDTH-1); FIFO_Empty : out std_logic; FIFO_Full : out std_logic; Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1) ); end entity srl_fifo_f; -- architecture imp of srl_fifo_f is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0'); begin I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0.srl_fifo_rbu_f generic map ( C_DWIDTH => C_DWIDTH, C_DEPTH => C_DEPTH, C_FAMILY => C_FAMILY ) port map ( Clk => Clk, Reset => Reset, FIFO_Write => FIFO_Write, Data_In => Data_In, FIFO_Read => FIFO_Read, Data_Out => Data_Out, FIFO_Full => FIFO_Full, FIFO_Empty => FIFO_Empty, Addr => Addr, Num_To_Reread => ZEROES, Underflow => open, Overflow => open ); end architecture imp;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/axi_lite.vhd	7	95564	------------------------------------------------------------------------------- -- axi_lite.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: axi_lite.vhd -- -- Description: This file is the top level module for the AXI-Lite -- instantiation of the BRAM controller interface. -- -- Responsible for shared address pipelining between the -- write address (AW) and read address (AR) channels. -- Controls (seperately) the data flows for the write data -- (W), write response (B), and read data (R) channels. -- -- Creates a shared port to BRAM (for all read and write -- transactions) or dual BRAM port utilization based on a -- generic parameter setting. -- -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- \| -- \|-- full_axi.vhd -- \| -- sng_port_arb.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- wr_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- ecc_gen.vhd -- \| -- \| -- rd_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- ecc_gen.vhd -- \| -- \|-- axi_lite.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- ecc_gen.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/22/2011 v1.03a -- ~~~~~~ -- Update BRAM address mapping to lite_ecc_reg module. Corrected -- signal size for XST detected unused bits in vector. -- Plus minor code cleanup. -- -- Add top level parameter, C_ECC_TYPE for Hsiao ECC algorithm. -- ^^^^^^ -- JLJ 2/23/2011 v1.03a -- ~~~~~~ -- Add Hsiao ECC algorithm logic (similar to full_axi module HDL). -- ^^^^^^ -- JLJ 2/24/2011 v1.03a -- ~~~~~~ -- Move REG_RDATA register process out from C_ECC_TYPE generate block -- to C_ECC generate block. -- ^^^^^^ -- JLJ 3/22/2011 v1.03a -- ~~~~~~ -- Add LUT level with reset signal to combinatorial outputs, AWREADY -- and WREADY. This will ensure that the output remains LOW during reset, -- regardless of AWVALID or WVALID input signals. -- ^^^^^^ -- JLJ 3/28/2011 v1.03a -- ~~~~~~ -- Remove combinatorial output paths on AWREADY and WREADY. -- Combine AWREADY and WREADY registers. -- Remove combinatorial output path on ARREADY. Can pre-assert ARREADY -- (but only for non ECC configurations). -- Create 3-bit counter for BVALID response, seperate from AW/W channels. -- -- Delay assertion of WREADY in ECC configurations to minimize register -- resource utilization. -- No pre-assertion of ARREADY in ECC configurations (due to write latency -- with ECC enabled). -- -- ^^^^^^ -- JLJ 3/30/2011 v1.03a -- ~~~~~~ -- Update Sl_CE and Sl_UE flag assertions to a single clock cycle. -- Clean up comments. -- ^^^^^^ -- JLJ 4/19/2011 v1.03a -- ~~~~~~ -- Update BVALID assertion when ECC is enabled to match the implementation -- when C_ECC = 0. Optimize back to back write performance when C_ECC = 1. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Modify FaultInjectClr signal assertion. With BVALID counter, delay -- when fault inject register gets cleared. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Code clean up. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove usage of C_FAMILY. -- Hard code C_USE_LUT6 constant. -- ^^^^^^ -- JLJ 7/7/2011 v1.03a -- ~~~~~~ -- Fix DV regression failure with reset. -- Hold off BRAM enable output with active reset signal. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.lite_ecc_reg; use work.parity; use work.checkbit_handler; use work.correct_one_bit; use work.ecc_gen; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity axi_lite is generic ( C_S_AXI_PROTOCOL : string := "AXI4LITE"; -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_SINGLE_PORT_BRAM : integer := 1; -- Enable single port usage of BRAM -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_TYPE : integer := 0; -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Interface Signals -- AXI Clock and Reset S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; ECC_Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- * AXI Write Address Channel Signals (AW) * AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); AXI_AWVALID : in std_logic; AXI_AWREADY : out std_logic; -- Unused AW AXI-Lite Signals -- AXI_AWID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); -- AXI_AWLEN : in std_logic_vector(7 downto 0); -- AXI_AWSIZE : in std_logic_vector(2 downto 0); -- AXI_AWBURST : in std_logic_vector(1 downto 0); -- AXI_AWLOCK : in std_logic; -- Currently unused -- AXI_AWCACHE : in std_logic_vector(3 downto 0); -- Currently unused -- AXI_AWPROT : in std_logic_vector(2 downto 0); -- Currently unused -- * AXI Write Data Channel Signals (W) * AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0); AXI_WVALID : in std_logic; AXI_WREADY : out std_logic; -- Unused W AXI-Lite Signals -- AXI_WLAST : in std_logic; -- * AXI Write Data Response Channel Signals (B) * AXI_BRESP : out std_logic_vector(1 downto 0); AXI_BVALID : out std_logic; AXI_BREADY : in std_logic; -- Unused B AXI-Lite Signals -- AXI_BID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); -- * AXI Read Address Channel Signals (AR) * AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); AXI_ARVALID : in std_logic; AXI_ARREADY : out std_logic; -- * AXI Read Data Channel Signals (R) * AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); AXI_RRESP : out std_logic_vector(1 downto 0); AXI_RLAST : out std_logic; AXI_RVALID : out std_logic; AXI_RREADY : in std_logic; -- * AXI-Lite ECC Register Interface Signals * -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk : in std_logic; -- S_AXI_CTRL_AResetn : in std_logic; -- AXI-Lite Write Address Channel Signals (AW) AXI_CTRL_AWVALID : in std_logic; AXI_CTRL_AWREADY : out std_logic; AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_WVALID : in std_logic; AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); AXI_CTRL_BVALID : out std_logic; AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); AXI_CTRL_ARVALID : in std_logic; AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); AXI_CTRL_RVALID : out std_logic; AXI_CTRL_RREADY : in std_logic; -- * BRAM Port A Interface Signals * -- Note: Clock handled at top level (axi_bram_ctrl module) BRAM_En_A : out std_logic; BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0); BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC -- Note: Remove BRAM_RdData_A port (unused in dual port mode) -- Platgen will keep port open on BRAM block -- * BRAM Port B Interface Signals * -- Note: Clock handled at top level (axi_bram_ctrl module) BRAM_En_B : out std_logic; BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0); BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) -- @ port level = 8-bits wide ECC ); end entity axi_lite; ------------------------------------------------------------------------------- architecture implementation of axi_lite is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- All functions defined in axi_bram_ctrl_funcs package. ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_RESET_ACTIVE : std_logic := '0'; constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error -- For future implementation. -- constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response -- constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error -- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width -- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00" -- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000" -- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000" -- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000" constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8); constant C_BRAM_ADDR_ADJUST : integer := C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR; constant C_AXI_DATA_WIDTH_BYTES : integer := C_S_AXI_DATA_WIDTH/8; -- Internal data width based on C_S_AXI_DATA_WIDTH. constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH); -- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6; -- Remove usage of C_FAMILY. -- All architectures supporting AXI will support a LUT6. -- Hard code this internal constant used in ECC algorithm. -- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6; constant C_USE_LUT6 : boolean := TRUE; ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal axi_aresetn_d1 : std_logic := '0'; signal axi_aresetn_re : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Write & Read Address Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type LITE_SM_TYPE is ( IDLE, SNG_WR_DATA, RD_DATA, RMW_RD_DATA, RMW_MOD_DATA, RMW_WR_DATA ); signal lite_sm_cs, lite_sm_ns : LITE_SM_TYPE; signal axi_arready_cmb : std_logic := '0'; signal axi_arready_reg : std_logic := '0'; signal axi_arready_int : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Write Data Channel Signals ------------------------------------------------------------------------------- signal axi_wready_cmb : std_logic := '0'; signal axi_wready_int : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Write Response Channel Signals ------------------------------------------------------------------------------- signal axi_bresp_int : std_logic_vector (1 downto 0) := (others => '0'); signal axi_bvalid_int : std_logic := '0'; signal bvalid_cnt_inc : std_logic := '0'; signal bvalid_cnt_inc_d1 : std_logic := '0'; signal bvalid_cnt_dec : std_logic := '0'; signal bvalid_cnt : std_logic_vector (2 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- AXI Read Data Channel Signals ------------------------------------------------------------------------------- signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0'); signal axi_rvalid_set : std_logic := '0'; signal axi_rvalid_set_r : std_logic := '0'; signal axi_rvalid_int : std_logic := '0'; signal axi_rlast_set : std_logic := '0'; signal axi_rlast_set_r : std_logic := '0'; signal axi_rlast_int : std_logic := '0'; signal axi_rdata_int : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal axi_rdata_int_corr : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Internal BRAM Signals ------------------------------------------------------------------------------- signal bram_we_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0) := (others => '0'); signal bram_en_a_cmb : std_logic := '0'; signal bram_en_b_cmb : std_logic := '0'; signal bram_en_a_int : std_logic := '0'; signal bram_en_b_int : std_logic := '0'; signal bram_addr_a_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_a_int_q : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_b_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal bram_wrdata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Port level signal, 8-bits ECC ------------------------------------------------------------------------------- -- Internal ECC Signals ------------------------------------------------------------------------------- signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register signal Sl_CE : std_logic := '0'; -- Correctable Error Flag signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag signal Sl_CE_i : std_logic := '0'; signal Sl_UE_i : std_logic := '0'; signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal FaultInjectECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width signal CorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal UnCorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal CE_Q : std_logic := '0'; signal UE_Q : std_logic := '0'; signal Enable_ECC : std_logic := '0'; signal RdModifyWr_Read : std_logic := '0'; -- Read cycle in read modify write sequence signal RdModifyWr_Check : std_logic := '0'; -- Read cycle in read modify write sequence signal RdModifyWr_Modify : std_logic := '0'; -- Modify cycle in read modify write sequence signal RdModifyWr_Write : std_logic := '0'; -- Write cycle in read modify write sequence signal WrData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal WrData_cmb : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal Active_Wr : std_logic := '0'; signal BRAM_Addr_En : std_logic := '0'; signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Specific to 32-bit ECC signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to 32-bit ECC signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Specific for 32-bit ECC signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- * AXI-Lite ECC Register Output Signals * --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NO_REGS -- Purpose: Generate default values if ECC registers are disabled (or when -- ECC is disabled). -- Include both AXI-Lite default signal values & internal -- core signal values. --------------------------------------------------------------------------- -- For future implementation. -- GEN_NO_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) or (C_ECC = 0) generate GEN_NO_REGS: if (C_ECC = 0) generate begin AXI_CTRL_AWREADY <= '0'; AXI_CTRL_WREADY <= '0'; AXI_CTRL_BRESP <= (others => '0'); AXI_CTRL_BVALID <= '0'; AXI_CTRL_ARREADY <= '0'; AXI_CTRL_RDATA <= (others => '0'); AXI_CTRL_RRESP <= (others => '0'); AXI_CTRL_RVALID <= '0'; -- No fault injection FaultInjectData <= (others => '0'); FaultInjectECC <= (others => '0'); -- Interrupt only enabled when ECC status/interrupt registers enabled ECC_Interrupt <= '0'; ECC_UE <= '0'; BRAM_Addr_En <= '0'; ----------------------------------------------------------------------- -- Generate: GEN_DIS_ECC -- Purpose: Disable ECC in read path when ECC is disabled in core. ----------------------------------------------------------------------- GEN_DIS_ECC: if C_ECC = 0 generate Enable_ECC <= '0'; end generate GEN_DIS_ECC; -- For future implementation. -- -- ----------------------------------------------------------------------- -- -- Generate: GEN_EN_ECC -- -- Purpose: Enable ECC when C_ECC = 1 and no ECC registers are available. -- -- ECC on/off control register is not accessible (so ECC is always -- -- enabled in this configuraiton). -- ----------------------------------------------------------------------- -- GEN_EN_ECC: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) generate -- Enable_ECC <= '1'; -- ECC ON/OFF register can not be enabled (as no ECC -- -- ECC registers are available. Therefore, ECC -- -- is always enabled. -- end generate GEN_EN_ECC; end generate GEN_NO_REGS; --------------------------------------------------------------------------- -- Generate: GEN_REGS -- Purpose: Generate ECC register module when ECC is enabled and -- ECC registers are enabled. --------------------------------------------------------------------------- -- For future implementation. -- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate GEN_REGS: if (C_ECC = 1) generate begin --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- Description: This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. --------------------------------------------------------------------------- I_LITE_ECC_REG : entity work.lite_ecc_reg generic map ( C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width C_FAULT_INJECT => C_FAULT_INJECT , C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS , C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS , C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS , C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER , C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE , C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH ) port map ( S_AXI_AClk => S_AXI_AClk , -- AXI clock S_AXI_AResetn => S_AXI_AResetn , -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock -- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn , Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , AXI_CTRL_AWVALID => AXI_CTRL_AWVALID , AXI_CTRL_AWREADY => AXI_CTRL_AWREADY , AXI_CTRL_AWADDR => AXI_CTRL_AWADDR , AXI_CTRL_WDATA => AXI_CTRL_WDATA , AXI_CTRL_WVALID => AXI_CTRL_WVALID , AXI_CTRL_WREADY => AXI_CTRL_WREADY , AXI_CTRL_BRESP => AXI_CTRL_BRESP , AXI_CTRL_BVALID => AXI_CTRL_BVALID , AXI_CTRL_BREADY => AXI_CTRL_BREADY , AXI_CTRL_ARADDR => AXI_CTRL_ARADDR , AXI_CTRL_ARVALID => AXI_CTRL_ARVALID , AXI_CTRL_ARREADY => AXI_CTRL_ARREADY , AXI_CTRL_RDATA => AXI_CTRL_RDATA , AXI_CTRL_RRESP => AXI_CTRL_RRESP , AXI_CTRL_RVALID => AXI_CTRL_RVALID , AXI_CTRL_RREADY => AXI_CTRL_RREADY , Enable_ECC => Enable_ECC , FaultInjectClr => FaultInjectClr , CE_Failing_We => CE_Failing_We , CE_CounterReg_Inc => CE_Failing_We , Sl_CE => Sl_CE , Sl_UE => Sl_UE , BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a BRAM_Addr_En => BRAM_Addr_En , Active_Wr => Active_Wr , FaultInjectData => FaultInjectData , FaultInjectECC => FaultInjectECC ); FaultInjectClr <= '1' when (bvalid_cnt_inc_d1 = '1') else '0'; CE_Failing_We <= '1' when Enable_ECC = '1' and CE_Q = '1' else '0'; Active_Wr <= '1' when (RdModifyWr_Read = '1' or RdModifyWr_Check = '1' or RdModifyWr_Modify = '1' or RdModifyWr_Write = '1') else '0'; ----------------------------------------------------------------------- -- Add register delay on BVALID counter increment -- Used to clear fault inject register. REG_BVALID_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then bvalid_cnt_inc_d1 <= '0'; else bvalid_cnt_inc_d1 <= bvalid_cnt_inc; end if; end if; end process REG_BVALID_CNT; ----------------------------------------------------------------------- end generate GEN_REGS; --------------------------------------------------------------------------- -- * AXI Output Signals * --------------------------------------------------------------------------- -- AXI Write Address Channel Output Signals -- AXI_AWREADY <= axi_awready_cmb; -- AXI_AWREADY <= '0' when (S_AXI_AResetn = '0') else axi_awready_cmb; -- v1.03a AXI_AWREADY <= axi_wready_int; -- v1.03a -- AXI Write Data Channel Output Signals -- AXI_WREADY <= axi_wready_cmb; -- AXI_WREADY <= '0' when (S_AXI_AResetn = '0') else axi_wready_cmb; -- v1.03a AXI_WREADY <= axi_wready_int; -- v1.03a -- AXI Write Response Channel Output Signals AXI_BRESP <= axi_bresp_int; AXI_BVALID <= axi_bvalid_int; -- AXI Read Address Channel Output Signals -- AXI_ARREADY <= axi_arready_cmb; -- v1.03a AXI_ARREADY <= axi_arready_int; -- v1.03a -- AXI Read Data Channel Output Signals -- AXI_RRESP <= axi_rresp_int; AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int; -- AXI_RDATA <= axi_rdata_int; -- Move assignment of RDATA to generate statements based on C_ECC. AXI_RVALID <= axi_rvalid_int; AXI_RLAST <= axi_rlast_int; ---------------------------------------------------------------------------- -- Need to detect end of reset cycle to assert AWREADY on AXI bus REG_ARESETN: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then axi_aresetn_d1 <= S_AXI_AResetn; end if; end process REG_ARESETN; -- Create combinatorial RE detect of S_AXI_AResetn axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0'; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- * AXI Write Address Channel Interface * --------------------------------------------------------------------------- -- Notes: -- No address pipelining for AXI-Lite. -- PDR feedback. -- Remove address register stage to BRAM. -- Rely on registers in AXI Interconnect. --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Generate all valid bits in the address(es) to BRAM. -- If dual port, generate Port B address signal. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin --------------------------------------------------------------------------- -- Generate: GEN_ADDR_SNG_PORT -- Purpose: Generate BRAM address when a single port to BRAM. -- Mux read and write addresses from AXI AW and AR channels. --------------------------------------------------------------------------- GEN_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate begin -- Read takes priority over AWADDR -- bram_addr_a_int (i) <= AXI_ARADDR (i) when (AXI_ARVALID = '1') else AXI_AWADDR (i); -- ISE should optimize away this mux when connected to the AXI Interconnect -- as the AXI Interconnect duplicates the write or read address on both channels. -- v1.03a -- ARVALID may get asserted while handling ECC read-modify-write. -- With the delay in assertion of AWREADY/WREADY, must add some logic to the -- control on this mux select. bram_addr_a_int (i) <= AXI_ARADDR (i) when ((AXI_ARVALID = '1' and (lite_sm_cs = IDLE or lite_sm_cs = SNG_WR_DATA)) or (lite_sm_cs = RD_DATA)) else AXI_AWADDR (i); end generate GEN_ADDR_SNG_PORT; --------------------------------------------------------------------------- -- Generate: GEN_ADDR_DUAL_PORT -- Purpose: Generate BRAM address when a single port to BRAM. -- Mux read and write addresses from AXI AW and AR channels. --------------------------------------------------------------------------- GEN_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate begin bram_addr_a_int (i) <= AXI_AWADDR (i); bram_addr_b_int (i) <= AXI_ARADDR (i); end generate GEN_ADDR_DUAL_PORT; end generate GEN_ADDR; --------------------------------------------------------------------------- -- * AXI Read Address Channel Interface * --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_ARREADY -- Purpose: Only pre-assert ARREADY for non ECC designs. -- With ECC, a write requires a read-modify-write and -- will miss the address associated with the ARVALID -- (due to the # of clock cycles). --------------------------------------------------------------------------- GEN_ARREADY: if (C_ECC = 0) generate begin REG_ARREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- ARREADY is asserted until we detect the ARVALID. -- Check for back-to-back ARREADY assertions (add axi_arready_int). if (S_AXI_AResetn = C_RESET_ACTIVE) or (AXI_ARVALID = '1' and axi_arready_int = '1') then axi_arready_int <= '0'; -- Then ARREADY is asserted again when the read operation completes. elsif (axi_aresetn_re = '1') or (axi_rlast_int = '1' and AXI_RREADY = '1') then axi_arready_int <= '1'; else axi_arready_int <= axi_arready_int; end if; end if; end process REG_ARREADY; end generate GEN_ARREADY; --------------------------------------------------------------------------- -- Generate: GEN_ARREADY_ECC -- Purpose: Generate ARREADY from SM logic. ARREADY is not pre-asserted -- as in the non ECC configuration. --------------------------------------------------------------------------- GEN_ARREADY_ECC: if (C_ECC = 1) generate begin axi_arready_int <= axi_arready_reg; end generate GEN_ARREADY_ECC; --------------------------------------------------------------------------- -- * AXI Write Data Channel Interface * --------------------------------------------------------------------------- -- No AXI_WLAST --------------------------------------------------------------------------- -- Generate: GEN_WRDATA -- Purpose: Generate BRAM port A write data. For AXI-Lite, pass -- through from AXI bus. If ECC is enabled, merge with fault -- inject vector. -- Write data bits are in lower order bit lanes. -- (31:0) or (63:0) --------------------------------------------------------------------------- GEN_WRDATA: for i in C_S_AXI_DATA_WIDTH-1 downto 0 generate begin --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Generate output write data when ECC is disabled. -- Remove write data path register to BRAM --------------------------------------------------------------------------- GEN_NO_ECC : if C_ECC = 0 generate begin bram_wrdata_a_int (i) <= AXI_WDATA (i); end generate GEN_NO_ECC; --------------------------------------------------------------------------- -- Generate: GEN_W_ECC -- Purpose: Generate output write data when ECC is enable -- (use fault vector). -- (N:0) --------------------------------------------------------------------------- GEN_W_ECC : if C_ECC = 1 generate begin bram_wrdata_a_int (i) <= WrData (i) xor FaultInjectData (i); end generate GEN_W_ECC; end generate GEN_WRDATA; --------------------------------------------------------------------------- -- * AXI Write Response Channel Interface * --------------------------------------------------------------------------- -- No BID support (wrap around in Interconnect) -- In AXI-Lite, no WLAST assertion -- Drive constant value out on BRESP -- axi_bresp_int <= RESP_OKAY; axi_bresp_int <= RESP_SLVERR when (C_ECC = 1 and UE_Q = '1') else RESP_OKAY; --------------------------------------------------------------------------- -- Implement BVALID with counter regardless of IP configuration. -- -- BVALID counter to track the # of required BVALID/BREADY handshakes -- needed to occur on the AXI interface. Based on early and seperate -- AWVALID/AWREADY and WVALID/WREADY handshake exchanges. REG_BVALID_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then bvalid_cnt <= (others => '0'); -- Ensure we only increment counter wyhen BREADY is not asserted elsif (bvalid_cnt_inc = '1') and (bvalid_cnt_dec = '0') then bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) + 1); -- Ensure that we only decrement when SM is not incrementing elsif (bvalid_cnt_dec = '1') and (bvalid_cnt_inc = '0') then bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) - 1); else bvalid_cnt <= bvalid_cnt; end if; end if; end process REG_BVALID_CNT; bvalid_cnt_dec <= '1' when (AXI_BREADY = '1' and axi_bvalid_int = '1' and bvalid_cnt /= "000") else '0'; -- Replace BVALID output register -- Assert BVALID as long as BVALID counter /= zero REG_BVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (bvalid_cnt = "001" and bvalid_cnt_dec = '1') then axi_bvalid_int <= '0'; elsif (bvalid_cnt /= "000") then axi_bvalid_int <= '1'; else axi_bvalid_int <= '0'; end if; end if; end process REG_BVALID; --------------------------------------------------------------------------- -- * AXI Read Data Channel Interface * --------------------------------------------------------------------------- -- For reductions on AXI-Lite, drive constant value on RESP axi_rresp_int <= RESP_OKAY; --------------------------------------------------------------------------- -- Generate: GEN_R -- Purpose: Generate AXI R channel outputs when ECC is disabled. -- No register delay on AXI_RVALID and AXI_RLAST. --------------------------------------------------------------------------- GEN_R: if C_ECC = 0 generate begin --------------------------------------------------------------------------- -- AXI_RVALID Output Register -- -- Set AXI_RVALID when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then -- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1' -- May be able to remove from this if clause (and simplify logic) axi_rvalid_int <= '0'; elsif (axi_rvalid_set = '1') then axi_rvalid_int <= '1'; else axi_rvalid_int <= axi_rvalid_int; end if; end if; end process REG_RVALID; --------------------------------------------------------------------------- -- AXI_RLAST Output Register -- -- Set AXI_RLAST when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RLAST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then -- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1' -- May be able to remove from this if clause (and simplify logic) axi_rlast_int <= '0'; elsif (axi_rlast_set = '1') then axi_rlast_int <= '1'; else axi_rlast_int <= axi_rlast_int; end if; end if; end process REG_RLAST; end generate GEN_R; --------------------------------------------------------------------------- -- Generate: GEN_R_ECC -- Purpose: Generate AXI R channel outputs when ECC is enabled. -- Must use registered delayed control signals for RLAST -- and RVALID to align with register inclusion for corrected -- read data in ECC logic. --------------------------------------------------------------------------- GEN_R_ECC: if C_ECC = 1 generate begin --------------------------------------------------------------------------- -- AXI_RVALID Output Register -- -- Set AXI_RVALID when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then -- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1' -- May be able to remove from this if clause (and simplify logic) axi_rvalid_int <= '0'; elsif (axi_rvalid_set_r = '1') then axi_rvalid_int <= '1'; else axi_rvalid_int <= axi_rvalid_int; end if; end if; end process REG_RVALID; --------------------------------------------------------------------------- -- AXI_RLAST Output Register -- -- Set AXI_RLAST when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RLAST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then -- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1' -- May be able to remove from this if clause (and simplify logic) axi_rlast_int <= '0'; elsif (axi_rlast_set_r = '1') then axi_rlast_int <= '1'; else axi_rlast_int <= axi_rlast_int; end if; end if; end process REG_RLAST; end generate GEN_R_ECC; --------------------------------------------------------------------------- -- -- Generate AXI bus read data. No register. Pass through -- read data from BRAM. Determine source on single port -- vs. dual port configuration. -- --------------------------------------------------------------------------- ----------------------------------------------------------------------- -- Generate: RDATA_NO_ECC -- Purpose: Define port A/B from BRAM on AXI_RDATA when ECC disabled. ----------------------------------------------------------------------- RDATA_NO_ECC: if (C_ECC = 0) generate begin AXI_RDATA <= axi_rdata_int; ----------------------------------------------------------------------- -- Generate: GEN_RDATA_SNG_PORT -- Purpose: Source of read data: Port A in single port configuration. ----------------------------------------------------------------------- GEN_RDATA_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate begin axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_A(C_S_AXI_DATA_WIDTH-1 downto 0); end generate GEN_RDATA_SNG_PORT; ----------------------------------------------------------------------- -- Generate: GEN_RDATA_DUAL_PORT -- Purpose: Source of read data: Port B in dual port configuration. ----------------------------------------------------------------------- GEN_RDATA_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate begin axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0); end generate GEN_RDATA_DUAL_PORT; end generate RDATA_NO_ECC; ----------------------------------------------------------------------- -- Generate: RDATA_W_ECC -- Purpose: Connect AXI_RDATA from ECC module when ECC enabled. ----------------------------------------------------------------------- RDATA_W_ECC: if (C_ECC = 1) generate subtype syndrome_bits is std_logic_vector (0 to 6); type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits; constant correct_data_table : correct_data_table_type := ( 0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001", 4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001", 8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101", 12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101", 16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101", 20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101", 24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011", 28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011" ); begin -- Logic common to either type of ECC encoding/decoding -- Renove bit reversal on AXI_RDATA output. AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr; CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0); -- Remove GEN_RDATA that was doing bit reversal. -- Read back data is registered prior to any single bit error correction. REG_RDATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rdata_int <= (others => '0'); else axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1); end if; end if; end process REG_RDATA; --------------------------------------------------------------------------- -- Generate: RDATA_W_HAMMING -- Purpose: Add generate statement for Hamming Code ECC algorithm -- specific logic. --------------------------------------------------------------------------- RDATA_W_HAMMING: if C_ECC_TYPE = 0 generate begin -- Move correct_one_bit logic to output side of AXI_RDATA output register. -- Improves timing by balancing logic on both sides of pipeline stage. -- Utilizing registers in AXI interconnect makes this feasible. --------------------------------------------------------------------------- -- Register ECC syndrome value to correct any single bit errors -- post-register on AXI read data. REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_reg <= Syndrome; syndrome_4_reg <= Syndrome_4; syndrome_6_reg <= Syndrome_6; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Do last XOR on select syndrome bits outside of checkbit_handler (to match rd_chnl -- w/ balanced pipeline stage) before correct_one_bit module. syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3); PARITY_CHK4: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2) port map ( InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (4) ); -- [out std_logic] syndrome_reg_i (5) <= syndrome_reg (5); PARITY_CHK6: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (6) ); -- [out std_logic] --------------------------------------------------------------------------- -- Generate: GEN_CORR_32 -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_32: for i in 0 to C_S_AXI_DATA_WIDTH-1 generate begin --------------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_32 -- Description: Generate ECC bits for checking data read from BRAM. --------------------------------------------------------------------------- CORR_ONE_BIT_32: entity work.correct_one_bit generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table (i)) port map ( DIn => axi_rdata_int (31-i), Syndrome => syndrome_reg_i, DCorr => axi_rdata_int_corr (31-i)); end generate GEN_CORR_32; end generate RDATA_W_HAMMING; -- Hsiao ECC done in seperate generate statement (GEN_HSIAO_ECC) end generate RDATA_W_ECC; --------------------------------------------------------------------------- -- Main AXI-Lite State Machine -- -- Description: Central processing unit for AXI-Lite write and read address -- channel interface handling and handshaking. -- Handles all arbitration between write and read channels -- to utilize single port to BRAM -- -- Outputs: axi_wready_int Registered -- axi_arready_reg Registered (used in ECC configurations) -- bvalid_cnt_inc Combinatorial -- axi_rvalid_set Combinatorial -- axi_rlast_set Combinatorial -- bram_en_a_cmb Combinatorial -- bram_en_b_cmb Combinatorial -- bram_we_a_int Combinatorial -- -- -- LITE_SM_CMB_PROCESS: Combinational process to determine next state. -- LITE_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- LITE_SM_CMB_PROCESS: process ( AXI_AWVALID, AXI_WVALID, AXI_WSTRB, AXI_ARVALID, AXI_RREADY, bvalid_cnt, axi_rvalid_int, lite_sm_cs ) begin -- assign default values for state machine outputs lite_sm_ns <= lite_sm_cs; axi_wready_cmb <= '0'; axi_arready_cmb <= '0'; bvalid_cnt_inc <= '0'; axi_rvalid_set <= '0'; axi_rlast_set <= '0'; bram_en_a_cmb <= '0'; bram_en_b_cmb <= '0'; bram_we_a_int <= (others => '0'); case lite_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- AXI Interconnect will only issue AWVALID OR ARVALID -- at a time. In the case when the core is attached -- to another AXI master IP, arbitrate between read -- and write operation. Read operation will always win. if (AXI_ARVALID = '1') then lite_sm_ns <= RD_DATA; -- Initiate BRAM read transfer -- For single port BRAM, use Port A -- For dual port BRAM, use Port B if (C_SINGLE_PORT_BRAM = 1) then bram_en_a_cmb <= '1'; else bram_en_b_cmb <= '1'; end if; bram_we_a_int <= (others => '0'); -- RVALID to be asserted in next clock cycle -- Only 1 clock cycle latency on reading data from BRAM axi_rvalid_set <= '1'; -- Due to single data beat with AXI-Lite -- Assert RLAST on AXI axi_rlast_set <= '1'; -- Only in ECC configurations -- Must assert ARREADY here (no pre-assertion) if (C_ECC = 1) then axi_arready_cmb <= '1'; end if; -- Write operations are lower priority than reads -- when an AXI master asserted both operations simultaneously. elsif (AXI_AWVALID = '1') and (AXI_WVALID = '1') and (bvalid_cnt /= "111") then -- Initiate BRAM write transfer bram_en_a_cmb <= '1'; -- Always perform a read-modify-write sequence with ECC is enabled. if (C_ECC = 1) then lite_sm_ns <= RMW_RD_DATA; -- Disable Port A write enables bram_we_a_int <= (others => '0'); else -- Non ECC operation or an ECC full 32-bit word write -- Assert acknowledge of data & address on AXI. -- Wait to assert AWREADY and WREADY in ECC designs. axi_wready_cmb <= '1'; -- Increment counter to track # of required BVALID responses. bvalid_cnt_inc <= '1'; lite_sm_ns <= SNG_WR_DATA; bram_we_a_int <= AXI_WSTRB; end if; end if; ------------------------- SNG_WR_DATA State ------------------------- when SNG_WR_DATA => -- With early assertion of ARREADY, the SM -- must be able to accept a read address at any clock cycle. -- Check here for active ARVALID and directly handle read -- and do not proceed back to IDLE (no empty clock cycle in which -- read address may be missed). if (AXI_ARVALID = '1') and (C_ECC = 0) then lite_sm_ns <= RD_DATA; -- Initiate BRAM read transfer -- For single port BRAM, use Port A -- For dual port BRAM, use Port B if (C_SINGLE_PORT_BRAM = 1) then bram_en_a_cmb <= '1'; else bram_en_b_cmb <= '1'; end if; bram_we_a_int <= (others => '0'); -- RVALID to be asserted in next clock cycle -- Only 1 clock cycle latency on reading data from BRAM axi_rvalid_set <= '1'; -- Due to single data beat with AXI-Lite -- Assert RLAST on AXI axi_rlast_set <= '1'; -- Only in ECC configurations -- Must assert ARREADY here (no pre-assertion) -- Pre-assertion of ARREADY is only for non ECC configurations. if (C_ECC = 1) then axi_arready_cmb <= '1'; end if; else lite_sm_ns <= IDLE; end if; ---------------------------- RD_DATA State --------------------------- when RD_DATA => -- Data is presented to AXI bus -- Wait for acknowledgment to process any next transfers -- RVALID may not be asserted as we transition into this state. if (AXI_RREADY = '1') and (axi_rvalid_int = '1') then lite_sm_ns <= IDLE; end if; ------------------------- RMW_RD_DATA State ------------------------- when RMW_RD_DATA => lite_sm_ns <= RMW_MOD_DATA; ------------------------- RMW_MOD_DATA State ------------------------- when RMW_MOD_DATA => lite_sm_ns <= RMW_WR_DATA; -- Hold off on assertion of WREADY and AWREADY until -- here, so no pipeline registers necessary. -- Assert acknowledge of data & address on AXI axi_wready_cmb <= '1'; -- Increment counter to track # of required BVALID responses. -- Able to assert this signal early, then BVALID counter -- will get incremented in the next clock cycle when WREADY -- is asserted. bvalid_cnt_inc <= '1'; ------------------------- RMW_WR_DATA State ------------------------- when RMW_WR_DATA => -- Initiate BRAM write transfer bram_en_a_cmb <= '1'; -- Enable all WEs to BRAM bram_we_a_int <= (others => '1'); -- Complete write operation lite_sm_ns <= IDLE; --coverage off ------------------------------ Default ---------------------------- when others => lite_sm_ns <= IDLE; --coverage on end case; end process LITE_SM_CMB_PROCESS; --------------------------------------------------------------------------- LITE_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then lite_sm_cs <= IDLE; axi_wready_int <= '0'; axi_arready_reg <= '0'; axi_rvalid_set_r <= '0'; axi_rlast_set_r <= '0'; else lite_sm_cs <= lite_sm_ns; axi_wready_int <= axi_wready_cmb; axi_arready_reg <= axi_arready_cmb; axi_rvalid_set_r <= axi_rvalid_set; axi_rlast_set_r <= axi_rlast_set; end if; end if; end process LITE_SM_REG_PROCESS; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- * ECC Logic * --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_ECC -- Purpose: Generate BRAM ECC write data and check ECC on read operations. -- Create signals to update ECC registers (lite_ecc_reg module interface). -- --------------------------------------------------------------------------- GEN_ECC: if C_ECC = 1 generate constant null7 : std_logic_vector(0 to 6) := "0000000"; -- Specific to 32-bit data width (AXI-Lite) signal WrECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0); -- Specific to BRAM data width signal WrECC_i : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0'); signal wrdata_i : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0); signal AXI_WDATA_Q : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0); signal AXI_WSTRB_Q : std_logic_vector ((C_S_AXI_DATA_WIDTH/8 - 1) downto 0); signal bram_din_a_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width signal bram_rddata_in : std_logic_vector (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); subtype syndrome_bits is std_logic_vector (0 to 6); type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits; constant correct_data_table : correct_data_table_type := ( 0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001", 4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001", 8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101", 12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101", 16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101", 20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101", 24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011", 28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011" ); type bool_array is array (natural range 0 to 6) of boolean; constant inverted_bit : bool_array := (false,false,true,false,true,false,false); begin -- Read on Port A -- or any operation on Port B (it will be read only). BRAM_Addr_En <= '1' when (bram_en_a_int = '1' and bram_we_a_int = "00000") or (bram_en_b_int = '1') else '0'; -- BRAM_WE generated from SM -- Remember byte write enables one clock cycle to properly mux bytes to write, -- with read data in read/modify write operation -- Write in Read/Write always 1 cycle after Read REG_RMW_SIGS : process (S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Add reset values if (S_AXI_AResetn = C_RESET_ACTIVE) then RdModifyWr_Check <= '0'; RdModifyWr_Modify <= '0'; RdModifyWr_Write <= '0'; else RdModifyWr_Check <= RdModifyWr_Read; RdModifyWr_Modify <= RdModifyWr_Check; RdModifyWr_Write <= RdModifyWr_Modify; end if; end if; end process REG_RMW_SIGS; -- v1.03a -- Delay assertion of WREADY to minimize registers in core. -- Use SM transition to RMW "read" to assert this signal. RdModifyWr_Read <= '1' when (lite_sm_ns = RMW_RD_DATA) else '0'; -- Remember write data one cycle to be available after read has been completed in a -- read/modify write operation STORE_WRITE_DBUS : process (S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then AXI_WDATA_Q <= (others => '0'); AXI_WSTRB_Q <= (others => '0'); -- v1.03a -- With the delay assertion of WREADY, use WVALID -- to register in WDATA and WSTRB signals. elsif (AXI_WVALID = '1') then AXI_WDATA_Q <= AXI_WDATA; AXI_WSTRB_Q <= AXI_WSTRB; end if; end if; end process STORE_WRITE_DBUS; wrdata_i <= AXI_WDATA_Q when RdModifyWr_Modify = '1' else AXI_WDATA; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_WRDATA_CMB -- Purpose: Replace manual signal assignment for WrData_cmb with -- generate funtion. -- -- Ensure correct byte swapping occurs with -- CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) assignment -- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0). -- -- AXI_WSTRB_Q (C_S_AXI_DATA_WIDTH_BYTES-1 downto 0) matches -- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0). -- ------------------------------------------------------------------------ GEN_WRDATA_CMB: for i in C_AXI_DATA_WIDTH_BYTES-1 downto 0 generate begin WrData_cmb ( (((i+1)8)-1) downto i8 ) <= wrdata_i ((((i+1)8)-1) downto i8) when (RdModifyWr_Modify = '1' and AXI_WSTRB_Q(i) = '1') else CorrectedRdData ( (C_S_AXI_DATA_WIDTH - ((i+1)8)) to (C_S_AXI_DATA_WIDTH - (i8) - 1) ); end generate GEN_WRDATA_CMB; REG_WRDATA : process (S_AXI_AClk) is begin -- Remove reset value to minimize resources & improve timing if (S_AXI_AClk'event and S_AXI_AClk = '1') then WrData <= WrData_cmb; end if; end process REG_WRDATA; ------------------------------------------------------------------------ -- New assignment of ECC bits to BRAM write data outside generate -- blocks. Same signal assignment regardless of ECC type. bram_wrdata_a_int (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) <= '0'; bram_wrdata_a_int ((C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH - 1) downto C_S_AXI_DATA_WIDTH) <= WrECC xor FaultInjectECC; ------------------------------------------------------------------------ -- No need to use RdModifyWr_Write in the data path. -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HAMMING_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. ------------------------------------------------------------------------ GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate begin --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_WR_32 -- Description: Generate ECC bits for writing into BRAM. -- WrData (N:0) --------------------------------------------------------------------------- CHK_HANDLER_WR_32: entity work.checkbit_handler generic map ( C_ENCODE => true, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( DataIn => WrData, -- [in std_logic_vector(0 to 31)] CheckIn => null7, -- [in std_logic_vector(0 to 6)] CheckOut => WrECC, -- [out std_logic_vector(0 to 6)] Syndrome_4 => open, -- [out std_logic_vector(0 to 1)] Syndrome_6 => open, -- [out std_logic_vector(0 to 5)] Syndrome => open, -- [out std_logic_vector(0 to 6)] Enable_ECC => '1', -- [in std_logic] Syndrome_Chk => null7, -- [in std_logic_vector(0 to 6)] UE_Q => '0', -- [in std_logic] CE_Q => '0', -- [in std_logic] UE => open, -- [out std_logic] CE => open ); -- [out std_logic] --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_RD_32 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) --------------------------------------------------------------------------- CHK_HANDLER_RD_32: entity work.checkbit_handler generic map ( C_ENCODE => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( -- DataIn (8:39) -- CheckIn (1:7) -- Bit swapping done at port level on checkbit_handler (31:0) & (6:0) DataIn => bram_din_a_i (C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_S_AXI_DATA_WIDTH), -- [in std_logic_vector(8 to 39)] CheckIn => bram_din_a_i (1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(1 to 7)] CheckOut => open, -- [out std_logic_vector(0 to 6)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)] Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)] Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)] Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 6)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] -- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate -- of AXI RDATA output register logic to use registered syndrome value. end generate GEN_HAMMING_ECC; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HSIAO_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Derived from MIG v3.7 Hsiao HDL. ------------------------------------------------------------------------ GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate constant CODE_WIDTH : integer := C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH; constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; type type_int0 is array (C_S_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0); signal syndrome_ns : std_logic_vector(ECC_WIDTH - 1 downto 0); signal syndrome_r : std_logic_vector(ECC_WIDTH - 1 downto 0); signal ecc_rddata_r : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); signal h_matrix : type_int0; signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0); signal flip_bits : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); begin ---------------------- Hsiao ECC Write Logic ---------------------- -- Instantiate ecc_gen module, generated from MIG ECC_GEN_HSIAO: entity work.ecc_gen generic map ( code_width => CODE_WIDTH, ecc_width => ECC_WIDTH, data_width => C_S_AXI_DATA_WIDTH ) port map ( -- Output h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0) ); -- Merge muxed rd/write data to gen HSIAO_ECC: process (h_rows, WrData) constant DQ_WIDTH : integer := CODE_WIDTH; variable ecc_wrdata_tmp : std_logic_vector(DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH); begin -- Loop to generate all ECC bits for k in 0 to ECC_WIDTH - 1 loop ecc_wrdata_tmp (CODE_WIDTH - k - 1) := REDUCTION_XOR ( (WrData (C_S_AXI_DATA_WIDTH - 1 downto 0) and h_rows (k * CODE_WIDTH + C_S_AXI_DATA_WIDTH - 1 downto k * CODE_WIDTH))); end loop; WrECC (C_INT_ECC_WIDTH-1 downto 0) <= ecc_wrdata_tmp (DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH); end process HSIAO_ECC; ---------------------- Hsiao ECC Read Logic ----------------------- GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate begin syndrome_ns (m) <= REDUCTION_XOR ( bram_rddata_in (CODE_WIDTH-1 downto 0) and h_rows ((mCODE_WIDTH)+CODE_WIDTH-1 downto (mCODE_WIDTH))); end generate GEN_RD_ECC; -- Insert register stage for syndrome REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_r <= syndrome_ns; -- Replicate BRAM read back data register for Hamming ECC ecc_rddata_r <= bram_rddata_in (C_S_AXI_DATA_WIDTH-1 downto 0); end if; end process REG_SYNDROME; -- Reconstruct H-matrix H_COL: for n in 0 to C_S_AXI_DATA_WIDTH - 1 generate begin H_BIT: for p in 0 to ECC_WIDTH - 1 generate begin h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n); end generate H_BIT; end generate H_COL; GEN_FLIP_BIT: for r in 0 to C_S_AXI_DATA_WIDTH - 1 generate begin flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r); end generate GEN_FLIP_BIT; axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0) <= ecc_rddata_r (C_S_AXI_DATA_WIDTH-1 downto 0) xor flip_bits (C_S_AXI_DATA_WIDTH-1 downto 0); Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); end generate GEN_HSIAO_ECC; -- Capture correctable/uncorrectable error from BRAM read. -- Either during RMW of write operation or during BRAM read. CORR_REG: process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if RdModifyWr_Modify = '1' or ((Enable_ECC = '1') and (axi_rvalid_int = '1' and AXI_RREADY = '1')) then -- Capture error signals CE_Q <= Sl_CE_i; UE_Q <= Sl_UE_i; else CE_Q <= '0'; UE_Q <= '0'; end if; end if; end process CORR_REG; -- Register CE and UE flags to register block. Sl_CE <= CE_Q; Sl_UE <= UE_Q; --------------------------------------------------------------------------- -- Generate: GEN_DIN_A -- Purpose: Generate BRAM read data vector assignment to always be from Port A -- in a single port BRAM configuration. -- Map BRAM_RdData_A (N:0) to bram_din_a_i (0:N) -- Including read back ECC bits. --------------------------------------------------------------------------- GEN_DIN_A: if C_SINGLE_PORT_BRAM = 1 generate begin --------------------------------------------------------------------------- -- Generate: GEN_DIN_A_HAMMING -- Purpose: Standard input for Hamming ECC code generation. -- MSB '0' is removed in port mapping to checkbit_handler module. --------------------------------------------------------------------------- GEN_DIN_A_HAMMING: if C_ECC_TYPE = 0 generate begin bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); end generate GEN_DIN_A_HAMMING; --------------------------------------------------------------------------- -- Generate: GEN_DIN_A_HSIAO -- Purpose: For Hsiao ECC implementation configurations. -- Remove MSB '0' on 32-bit implementation with fixed -- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix). --------------------------------------------------------------------------- GEN_DIN_A_HSIAO: if C_ECC_TYPE = 1 generate begin bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0); end generate GEN_DIN_A_HSIAO; end generate GEN_DIN_A; --------------------------------------------------------------------------- -- Generate: GEN_DIN_B -- Purpose: Generate BRAM read data vector assignment in a dual port -- configuration to be either from Port B, or from Port A in a -- read-modify-write sequence. -- Map BRAM_RdData_A/B (N:0) to bram_din_a_i (0:N) -- Including read back ECC bits. --------------------------------------------------------------------------- GEN_DIN_B: if C_SINGLE_PORT_BRAM = 0 generate begin --------------------------------------------------------------------------- -- Generate: GEN_DIN_B_HAMMING -- Purpose: Standard input for Hamming ECC code generation. -- MSB '0' is removed in port mapping to checkbit_handler module. --------------------------------------------------------------------------- GEN_DIN_B_HAMMING: if C_ECC_TYPE = 0 generate begin bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) when (RdModifyWr_Check = '1') else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); end generate GEN_DIN_B_HAMMING; --------------------------------------------------------------------------- -- Generate: GEN_DIN_B_HSIAO -- Purpose: For Hsiao ECC implementation configurations. -- Remove MSB '0' on 32-bit implementation with fixed -- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix). --------------------------------------------------------------------------- GEN_DIN_B_HSIAO: if C_ECC_TYPE = 1 generate begin bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0) when (RdModifyWr_Check = '1') else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0); end generate GEN_DIN_B_HSIAO; end generate GEN_DIN_B; -- Map data vector from BRAM to use in correct_one_bit module with -- register syndrome (post AXI RDATA register). UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_S_AXI_DATA_WIDTH-1) when (C_ECC_TYPE = 0) else bram_rddata_in(C_S_AXI_DATA_WIDTH-1 downto 0); end generate GEN_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- * BRAM Interface Signals * --------------------------------------------------------------------------- -- With AXI-LITE no narrow operations are allowed. -- AXI_WSTRB is ignored and all byte lanes are written. bram_en_a_int <= bram_en_a_cmb; -- BRAM_En_A <= bram_en_a_int; -- DV regression failure with reset -- 7/7/11 BRAM_En_A <= '0' when (S_AXI_AResetn = C_RESET_ACTIVE) else bram_en_a_int; ----------------------------------------------------------------------- -- Generate: GEN_BRAM_EN_DUAL_PORT -- Purpose: Only generate Port B BRAM enable signal when -- configured for dual port BRAM. ----------------------------------------------------------------------- GEN_BRAM_EN_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate begin bram_en_b_int <= bram_en_b_cmb; BRAM_En_B <= bram_en_b_int; end generate GEN_BRAM_EN_DUAL_PORT; ----------------------------------------------------------------------- -- Generate: GEN_BRAM_EN_SNG_PORT -- Purpose: Drive default for unused BRAM Port B in single -- port BRAM configuration. ----------------------------------------------------------------------- GEN_BRAM_EN_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate begin BRAM_En_B <= '0'; end generate GEN_BRAM_EN_SNG_PORT; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_WE -- Purpose: BRAM WE generate process -- One WE per 8-bits of BRAM data. --------------------------------------------------------------------------- GEN_BRAM_WE: for i in (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH)/8-1 downto 0 generate begin BRAM_WE_A (i) <= bram_we_a_int (i); end generate GEN_BRAM_WE; --------------------------------------------------------------------------- BRAM_Addr_A <= BRAM_Addr_A_i; BRAM_Addr_B <= BRAM_Addr_B_i; --------------------------------------------------------------------------- -- Generate: GEN_L_BRAM_ADDR -- Purpose: Generate zeros on lower order address bits adjustable -- based on BRAM data width. --------------------------------------------------------------------------- GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin BRAM_Addr_A_i (i) <= '0'; BRAM_Addr_B_i (i) <= '0'; end generate GEN_L_BRAM_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_ADDR -- Purpose: Assign BRAM address output from address counter. --------------------------------------------------------------------------- GEN_U_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin BRAM_Addr_A_i (i) <= bram_addr_a_int (i); ----------------------------------------------------------------------- -- Generate: GEN_BRAM_ADDR_DUAL_PORT -- Purpose: Only generate Port B BRAM address when -- configured for dual port BRAM. ----------------------------------------------------------------------- GEN_BRAM_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate begin BRAM_Addr_B_i (i) <= bram_addr_b_int (i); end generate GEN_BRAM_ADDR_DUAL_PORT; ----------------------------------------------------------------------- -- Generate: GEN_BRAM_ADDR_SNG_PORT -- Purpose: Drive default for unused BRAM Port B in single -- port BRAM configuration. ----------------------------------------------------------------------- GEN_BRAM_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate begin BRAM_Addr_B_i (i) <= '0'; end generate GEN_BRAM_ADDR_SNG_PORT; end generate GEN_U_BRAM_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_WRDATA -- Purpose: Generate BRAM Write Data for Port A. --------------------------------------------------------------------------- -- When C_ECC = 0, C_ECC_WIDTH = 0 (at top level HDL) GEN_BRAM_WRDATA: for i in (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) downto 0 generate begin BRAM_WrData_A (i) <= bram_wrdata_a_int (i); end generate GEN_BRAM_WRDATA; BRAM_WrData_B <= (others => '0'); BRAM_WE_B <= (others => '0'); --------------------------------------------------------------------------- end architecture implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/FIFO_image_filter_p_src_data_stream_2_V.vhd	2	4629	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_p_src_data_stream_2_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_p_src_data_stream_2_V_shiftReg; architecture rtl of FIFO_image_filter_p_src_data_stream_2_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_p_src_data_stream_2_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_p_src_data_stream_2_V is component FIFO_image_filter_p_src_data_stream_2_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_p_src_data_stream_2_V_shiftReg : FIFO_image_filter_p_src_data_stream_2_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_p_src_data_stream_2_V.vhd	2	4629	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_p_src_data_stream_2_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_p_src_data_stream_2_V_shiftReg; architecture rtl of FIFO_image_filter_p_src_data_stream_2_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_p_src_data_stream_2_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_p_src_data_stream_2_V is component FIFO_image_filter_p_src_data_stream_2_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_p_src_data_stream_2_V_shiftReg : FIFO_image_filter_p_src_data_stream_2_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_slice.vhd	19	4781	-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; entity axi_datamover_slice is generic ( C_DATA_WIDTH : Integer range 1 to 200 := 64 ); port ( ACLK : in std_logic; ARESET : in std_logic; -- Slave side S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0); S_VALID : in std_logic; S_READY : out std_logic; -- Master side M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0); M_VALID : out std_logic; M_READY : in std_logic ); end entity axi_datamover_slice; architecture working of axi_datamover_slice is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes"; signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0); signal s_ready_i : std_logic; signal m_valid_i : std_logic; signal areset_d : std_logic_vector (1 downto 0); begin -- assign local signal to its output signal S_READY <= s_ready_i; M_VALID <= m_valid_i; process (ACLK) begin if (ACLK'event and ACLK = '1') then areset_d(0) <= ARESET; areset_d(1) <= areset_d(0); end if; end process; -- Save payload data whenever we have a transaction on the slave side process (ACLK) begin if (ACLK'event and ACLK = '1') then if (S_VALID = '1' and s_ready_i = '1') then storage_data <= S_PAYLOAD_DATA; else storage_data <= storage_data; end if; end if; end process; M_PAYLOAD_DATA <= storage_data; -- M_Valid set to high when we have a completed transfer on slave side -- Is removed on a M_READY except if we have a new transfer on the slave side process (ACLK) begin if (ACLK'event and ACLK = '1') then if (areset_d (1) = '1') then m_valid_i <= '0'; elsif (S_VALID = '1') then m_valid_i <= '1'; elsif (M_READY = '1') then m_valid_i <= '0'; else m_valid_i <= m_valid_i; end if; end if; end process; -- Slave Ready is either when Master side drives M_Ready or we have space in our storage data s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0)); end working;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_updt_noqueue.vhd	3	30514	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ********************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_noqueue.vhd -- Description: This entity provides the descriptor update for the No Queue mode -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_noqueue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 -- 1 IOC bit + 32 Update Status Bits ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Channel 1 Control -- updt_curdesc_wren : out std_logic ; -- updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_active : in std_logic ; -- updt_queue_empty : out std_logic ; -- updt_ioc : out std_logic ; -- updt_ioc_irq_set : in std_logic ; -- -- dma_interr : out std_logic ; -- dma_slverr : out std_logic ; -- dma_decerr : out std_logic ; -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- updt2_active : in std_logic ; -- updt2_queue_empty : out std_logic ; -- updt2_ioc : out std_logic ; -- updt2_ioc_irq_set : in std_logic ; -- -- dma2_interr : out std_logic ; -- dma2_slverr : out std_logic ; -- dma2_decerr : out std_logic ; -- dma2_interr_set : in std_logic ; -- dma2_slverr_set : in std_logic ; -- dma2_decerr_set : in std_logic ; -- -- --*****************************-- -- -- Channel Update Interface In -- -- --*****************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis_updtptr_tvalid : in std_logic ; -- s_axis_updtptr_tready : out std_logic ; -- s_axis_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_updtsts_tvalid : in std_logic ; -- s_axis_updtsts_tready : out std_logic ; -- s_axis_updtsts_tlast : in std_logic ; -- -- Update Pointer Stream -- s_axis2_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis2_updtptr_tvalid : in std_logic ; -- s_axis2_updtptr_tready : out std_logic ; -- s_axis2_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis2_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis2_updtsts_tvalid : in std_logic ; -- s_axis2_updtsts_tready : out std_logic ; -- s_axis2_updtsts_tlast : in std_logic ; -- -- --*****************************-- -- -- Channel Update Interface Out-- -- --*****************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata : out std_logic_vector -- (C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); -- m_axis_updt_tlast : out std_logic ; -- m_axis_updt_tvalid : out std_logic ; -- m_axis_updt_tready : in std_logic -- ); end axi_sg_updt_noqueue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_noqueue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Contstants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel signals signal writing_curdesc : std_logic := '0'; signal write_curdesc_lsb : std_logic := '0'; signal write_curdesc_msb : std_logic := '0'; signal updt_active_d1 : std_logic := '0'; signal updt_active_re : std_logic := '0'; type PNTR_STATE_TYPE is (IDLE, READ_CURDESC_LSB, READ_CURDESC_MSB, WRITE_STATUS ); signal pntr_cs : PNTR_STATE_TYPE; signal pntr_ns : PNTR_STATE_TYPE; signal writing_status : std_logic := '0'; signal curdesc_tready : std_logic := '0'; signal writing_status_d1 : std_logic := '0'; signal writing_status_re : std_logic := '0'; signal writing_status_re_ch1 : std_logic := '0'; signal writing_status_re_ch2 : std_logic := '0'; signal updt_active_int : std_logic := '0'; signal s_axis_updtptr_tvalid_int : std_logic := '0'; signal s_axis_updtsts_tvalid_int : std_logic := '0'; signal s_axis_updtsts_tlast_int : std_logic := '0'; signal s_axis_updtptr_tdata_int : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); signal s_axis_qual : std_logic := '0'; signal s_axis2_qual : std_logic := '0'; signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); -- signal m_axis_updt_tlast_mm2s : std_logic ; -- signal m_axis_updt_tvalid_mm2s : std_logic ; signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); -- signal m_axis_updt_tlast_s2mm : std_logic ; -- signal m_axis_updt_tvalid_s2mm : std_logic ; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else m_axis_updt_tdata_s2mm; m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else m_axis_updt_tvalid_s2mm; m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else m_axis_updt_tlast_s2mm; updt_active_int <= updt_active or updt2_active; s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid; s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid; s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast; s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active; s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active; -- Asset active strobe on rising edge of update active -- asertion. This kicks off the update process for -- the channel REG_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_active_d1 <= '0'; else updt_active_d1 <= updt_active or updt2_active; end if; end if; end process REG_ACTIVE; updt_active_re <= (updt_active or updt2_active) and not updt_active_d1; -- Current Descriptor Pointer Fetch. This state machine controls -- reading out the current pointer from the Queue or channel port -- and writing it to the update manager for use in command -- generation to the DataMover for Descriptor update. CURDESC_PNTR_STATE : process(pntr_cs, updt_active_int, s_axis_updtptr_tvalid_int, updt_active, updt2_active, s_axis_qual, s_axis2_qual, s_axis_updtptr_tvalid, s_axis2_updtptr_tvalid, s_axis_updtsts_tvalid_int, m_axis_updt_tready) begin write_curdesc_lsb <= '0'; write_curdesc_msb <= '0'; writing_status <= '0'; writing_curdesc <= '0'; curdesc_tready <= '0'; pntr_ns <= pntr_cs; case pntr_cs is when IDLE => if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or (s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then writing_curdesc <= '1'; pntr_ns <= READ_CURDESC_LSB; else pntr_ns <= IDLE; end if; --------------------------------------------------------------- -- Get lower current descriptor when READ_CURDESC_LSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- on tvalid from Queue or channel port then register -- lsb curdesc and setup to register msb curdesc if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then write_curdesc_lsb <= '1'; -- pntr_ns <= READ_CURDESC_MSB; pntr_ns <= WRITE_STATUS; else -- coverage off pntr_ns <= READ_CURDESC_LSB; -- coverage on end if; -- coverage off --------------------------------------------------------------- -- Get upper current descriptor when READ_CURDESC_MSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- On tvalid from Queue or channel port then register -- msb. This will also write curdesc out to update -- manager. if(s_axis_updtptr_tvalid_int = '1')then write_curdesc_msb <= '1'; pntr_ns <= WRITE_STATUS; else pntr_ns <= READ_CURDESC_MSB; end if; -- coverage on --------------------------------------------------------------- -- Hold in this state until remainder of descriptor is -- written out. when WRITE_STATUS => writing_status <= '1'; --s_axis_updtsts_tvalid_int; if((s_axis_qual = '1' and m_axis_updt_tready = '1') or (s_axis2_qual = '1' and m_axis_updt_tready = '1')) then pntr_ns <= IDLE; else pntr_ns <= WRITE_STATUS; end if; -- coverage off when others => pntr_ns <= IDLE; -- coverage on end case; end process CURDESC_PNTR_STATE; --------------------------------------------------------------------------- -- Register for CURDESC Pointer state machine --------------------------------------------------------------------------- REG_PNTR_STATES : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then pntr_cs <= IDLE; else pntr_cs <= pntr_ns; end if; end if; end process REG_PNTR_STATES; -- Status stream signals m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0); m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status; m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status; s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active; -- Pointer stream signals s_axis_updtptr_tready <= curdesc_tready and updt_active; -- Indicate need for channel service for update state machine updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status); m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0); m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status; m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status; s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active; -- Pointer stream signals s_axis2_updtptr_tready <= curdesc_tready and updt2_active; -- Indicate need for channel service for update state machine updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status); --***************************************************************** -- POINTER CAPTURE LOGIC --******************************************************************* s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else s_axis2_updtptr_tdata; --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_LSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(31 downto 0) <= (others => '0'); -- Capture lower pointer from FIFO or channel port elsif(write_curdesc_lsb = '1')then updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); end if; end if; end process REG_LSB_CURPNTR; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(63 downto 32) <= (others => '0'); updt_curdesc_wren <= '0'; -- Capture upper pointer from FIFO or channel port -- and also write curdesc out elsif(write_curdesc_msb = '1')then updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); updt_curdesc_wren <= '1'; -- Assert tready/wren for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_UPPER_MSB_CURDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc_wren <= '0'; -- Throw away second word, only write curdesc out with msb -- set to zero elsif(write_curdesc_lsb = '1')then -- elsif(write_curdesc_msb = '1')then updt_curdesc_wren <= '1'; -- Assert for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_NO_UPR_MSB_CURDESC; --***************************************************************** -- ERROR CAPTURE LOGIC --********************************************************************* ----------------------------------------------------------------------- -- Generate rising edge pulse on writing status signal. This will -- assert at the beginning of the status write. Coupled with status -- fifo set to first word fall through status will be on dout -- regardless of target ready. ----------------------------------------------------------------------- REG_WRITE_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then writing_status_d1 <= '0'; else writing_status_d1 <= writing_status; end if; end if; end process REG_WRITE_STATUS; writing_status_re <= writing_status and not writing_status_d1; writing_status_re_ch1 <= writing_status_re and updt_active; writing_status_re_ch2 <= writing_status_re and updt2_active; --------------------------------------------------------------------------- -- Caputure IOC begin set --------------------------------------------------------------------------- REG_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then updt_ioc <= '0'; elsif(writing_status_re_ch1 = '1')then updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then dma_interr <= '0'; elsif(writing_status_re_ch1 = '1')then dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then dma_slverr <= '0'; elsif(writing_status_re_ch1 = '1')then dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then dma_decerr <= '0'; elsif(writing_status_re_ch1 = '1')then dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC_ERROR; --------------------------------------------------------------------------- -- Caputure IOC begin set --------------------------------------------------------------------------- REG2_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then updt2_ioc <= '0'; elsif(writing_status_re_ch2 = '1')then updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT); end if; end if; end process REG2_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then dma2_interr <= '0'; elsif(writing_status_re_ch2 = '1')then dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE2_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then dma2_slverr <= '0'; elsif(writing_status_re_ch2 = '1')then dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE2_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then dma2_decerr <= '0'; elsif(writing_status_re_ch2 = '1')then dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE2_DMADEC_ERROR; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_dre_mux2_1_x_n.vhd	18	5142	------------------------------------------------------------------------------- -- axi_datamover_dre_mux2_1_x_n.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_dre_mux2_1_x_n.vhd -- -- Description: -- -- This VHDL file provides a 2 to 1 xn bit wide mux for the AXI Data Realignment -- Engine (DRE). -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use ieee.STD_LOGIC_UNSIGNED.all; use ieee.std_logic_arith.all; ------------------------------------------------------------------------------- -- Start 2 to 1 xN Mux ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- Entity axi_datamover_dre_mux2_1_x_n is generic ( C_WIDTH : Integer := 8 -- Sets the bit width of the 2x Mux slice ); port ( Sel : In std_logic; -- Mux select control I0 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 0 input I1 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 1 inputl Y : Out std_logic_vector(C_WIDTH-1 downto 0) -- Mux output value ); end entity axi_datamover_dre_mux2_1_x_n; -- Architecture implementation of axi_datamover_dre_mux2_1_x_n is begin ------------------------------------------------------------- -- Combinational Process -- -- Label: SELECT2_1 -- -- Process Description: -- This process implements an 2 to 1 mux. -- ------------------------------------------------------------- SELECT2_1 : process (Sel, I0, I1) begin case Sel is when '0' => Y <= I0; when '1' => Y <= I1; when others => Y <= I0; end case; end process SELECT2_1; end implementation; -- axi_datamover_dre_mux2_1_x_n ------------------------------------------------------------------------------- -- End 2 to 1 xN Mux -------------------------------------------------------------------------------	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/impl/vhdl/FIFO_image_filter_img_0_data_stream_0_V.vhd	4	4629	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_img_0_data_stream_0_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_img_0_data_stream_0_V_shiftReg; architecture rtl of FIFO_image_filter_img_0_data_stream_0_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_img_0_data_stream_0_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_img_0_data_stream_0_V is component FIFO_image_filter_img_0_data_stream_0_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_img_0_data_stream_0_V_shiftReg : FIFO_image_filter_img_0_data_stream_0_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/rd_chnl.vhd	5	207533	------------------------------------------------------------------------------- -- rd_chnl.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: rd_chnl.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller read channel interfaces. Controls all -- handshaking and data flow on the AXI read address (AR) -- and read data (R) channels. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- \| -- \|-- full_axi.vhd -- \| -- sng_port_arb.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- wr_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- ecc_gen.vhd -- \| -- \| -- rd_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- ecc_gen.vhd -- \| -- \|-- axi_lite.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- -- ------------------------------------------------------------------------------- -- -- History: -- -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/3/2011 v1.03a -- ~~~~~~ -- Edits for scalability and support of 512 and 1024-bit data widths. -- ^^^^^^ -- JLJ 2/14/2011 v1.03a -- ~~~~~~ -- Initial integration of Hsiao ECC algorithm. -- Add C_ECC_TYPE top level parameter. -- Similar edits as wr_chnl on Hsiao ECC code. -- ^^^^^^ -- JLJ 2/18/2011 v1.03a -- ~~~~~~ -- Update for usage of ecc_gen.vhd module directly from MIG. -- Clean-up XST warnings. -- ^^^^^^ -- JLJ 2/22/2011 v1.03a -- ~~~~~~ -- Found issue with ECC decoding on read path. Remove MSB '0' usage -- in syndrome calculation, since h_matrix is based on 32 + 7 = 39 bits. -- Modify read data signal used in single bit error correction. -- ^^^^^^ -- JLJ 2/23/2011 v1.03a -- ~~~~~~ -- Move all MIG functions to package body. -- ^^^^^^ -- JLJ 3/2/2011 v1.03a -- ~~~~~~ -- Fix XST handling for DIV functions. Create seperate process when -- divisor is not constant and a power of two. -- ^^^^^^ -- JLJ 3/15/2011 v1.03a -- ~~~~~~ -- Clean-up unused signal, narrow_addr_inc. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Add comments as noted in Spyglass runs. And general code clean-up. -- ^^^^^^ -- JLJ 4/21/2011 v1.03a -- ~~~~~~ -- Code clean up. -- Add defaults to araddr_pipe_sel & axi_arready_int when in single port mode. -- Remove use of IF_IS_AXI4 constant. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Code clean up. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove usage of C_FAMILY. -- Hard code C_USE_LUT6 constant. -- ^^^^^^ -- JLJ 5/26/2011 v1.03a -- ~~~~~~ -- With CR # 609695, update else clause for narrow_burst_cnt_ld to -- remove simulation warnings when axi_byte_div_curr_arsize = zero. -- ^^^^^^ -- -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.wrap_brst; use work.ua_narrow; use work.checkbit_handler; use work.checkbit_handler_64; use work.correct_one_bit; use work.correct_one_bit_64; use work.ecc_gen; use work.parity; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity rd_chnl is generic ( -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type C_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) C_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_AXI_ID_WIDTH : integer := 4; -- AXI ID vector width C_S_AXI_SUPPORTS_NARROW : integer := 1; -- Support for narrow burst operations C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to "AXI4LITE" to optimize out burst transaction support C_SINGLE_PORT_BRAM : integer := 0; -- Enable single port usage of BRAM C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_ECC_TYPE : integer := 0 -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code ); port ( -- AXI Global Signals S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI Read Address Channel Signals (AR) AXI_ARID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); AXI_ARADDR : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0); AXI_ARLEN : in std_logic_vector(7 downto 0); -- Specifies the number of data transfers in the burst -- "0000 0000" 1 data transfer -- "0000 0001" 2 data transfers -- ... -- "1111 1111" 256 data transfers AXI_ARSIZE : in std_logic_vector(2 downto 0); -- Specifies the max number of data bytes to transfer in each data beat -- "000" 1 byte to transfer -- "001" 2 bytes to transfer -- "010" 3 bytes to transfer -- ... AXI_ARBURST : in std_logic_vector(1 downto 0); -- Specifies burst type -- "00" FIXED = Fixed burst address (handled as INCR) -- "01" INCR = Increment burst address -- "10" WRAP = Incrementing address burst that wraps to lower order address at boundary -- "11" Reserved (not checked) AXI_ARLOCK : in std_logic; AXI_ARCACHE : in std_logic_vector(3 downto 0); AXI_ARPROT : in std_logic_vector(2 downto 0); AXI_ARVALID : in std_logic; AXI_ARREADY : out std_logic; -- AXI Read Data Channel Signals (R) AXI_RID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); AXI_RDATA : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0); AXI_RRESP : out std_logic_vector(1 downto 0); AXI_RLAST : out std_logic; AXI_RVALID : out std_logic; AXI_RREADY : in std_logic; -- ECC Register Interface Signals Enable_ECC : in std_logic; BRAM_Addr_En : out std_logic; CE_Failing_We : out std_logic := '0'; Sl_CE : out std_logic := '0'; Sl_UE : out std_logic := '0'; -- Single Port Arbitration Signals Arb2AR_Active : in std_logic; AR2Arb_Active_Clr : out std_logic := '0'; Sng_BRAM_Addr_Ld_En : out std_logic := '0'; Sng_BRAM_Addr_Ld : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); Sng_BRAM_Addr_Inc : out std_logic := '0'; Sng_BRAM_Addr : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- BRAM Read Port Interface Signals BRAM_En : out std_logic; BRAM_Addr : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0); BRAM_RdData : in std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) ); end entity rd_chnl; ------------------------------------------------------------------------------- architecture implementation of rd_chnl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- All functions defined in axi_bram_ctrl_funcs package. ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- -- Reset active level (common through core) constant C_RESET_ACTIVE : std_logic := '0'; constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error -- For future support. constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response -- For future support. constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error -- Set constants for ARLEN equal to a count of one or two beats. constant AXI_ARLEN_ONE : std_logic_vector(7 downto 0) := (others => '0'); constant AXI_ARLEN_TWO : std_logic_vector(7 downto 0) := "00000001"; -- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width -- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00" -- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000" -- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000" -- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000" -- Move to full_axi module -- constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_AXI_DATA_WIDTH/8); -- Not used -- constant C_BRAM_ADDR_ADJUST : integer := C_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR; -- Determine maximum size for narrow burst length counter -- When C_AXI_DATA_WIDTH = 32, minimum narrow width burst is 8 bits -- resulting in a count 3 downto 0 => so minimum counter width = 2 bits. -- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst is 8 bits -- resulting in a count 31 downto 0 => so minimum counter width = 5 bits. constant C_NARROW_BURST_CNT_LEN : integer := log2 (C_AXI_DATA_WIDTH/8); constant NARROW_CNT_MAX : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); -- Max length burst count AXI4 specification constant C_MAX_BRST_CNT : integer := 256; constant C_BRST_CNT_SIZE : integer := log2 (C_MAX_BRST_CNT); -- When the burst count = 0 constant C_BRST_CNT_ZERO : std_logic_vector(C_BRST_CNT_SIZE-1 downto 0) := (others => '0'); -- Burst count = 1 constant C_BRST_CNT_ONE : std_logic_vector(7 downto 0) := "00000001"; -- Burst count = 2 constant C_BRST_CNT_TWO : std_logic_vector(7 downto 0) := "00000010"; -- Read data mux select constants (for signal rddata_mux_sel) -- '0' selects BRAM -- '1' selects read skid buffer constant C_RDDATA_MUX_BRAM : std_logic := '0'; constant C_RDDATA_MUX_SKID_BUF : std_logic := '1'; -- Determine the number of bytes based on the AXI data width. constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8; -- AXI Burst Types -- AXI Spec 4.4 constant C_AXI_BURST_WRAP : std_logic_vector (1 downto 0) := "10"; constant C_AXI_BURST_INCR : std_logic_vector (1 downto 0) := "01"; constant C_AXI_BURST_FIXED : std_logic_vector (1 downto 0) := "00"; -- AXI Size Constants -- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte -- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes -- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM -- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM -- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM -- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM -- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM -- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM -- Determine max value of ARSIZE based on the AXI data width. -- Use function in axi_bram_ctrl_funcs package. constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH); -- Internal ECC data width size. constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_AXI_DATA_WIDTH); -- For use with ECC functions (to use LUT6 components or let synthesis infer the optimal implementation). -- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6; -- Remove usage of C_FAMILY. -- All architectures supporting AXI will support a LUT6. -- Hard code this internal constant used in ECC algorithm. constant C_USE_LUT6 : boolean := TRUE; ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Read Address Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type RD_ADDR_SM_TYPE is ( IDLE, LD_ARADDR ); signal rd_addr_sm_cs, rd_addr_sm_ns : RD_ADDR_SM_TYPE; signal ar_active_set : std_logic := '0'; signal ar_active_set_i : std_logic := '0'; signal ar_active_clr : std_logic := '0'; signal ar_active : std_logic := '0'; signal ar_active_d1 : std_logic := '0'; signal ar_active_re : std_logic := '0'; signal axi_araddr_pipe : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal curr_araddr_lsb : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0'); signal araddr_pipe_ld : std_logic := '0'; signal araddr_pipe_ld_i : std_logic := '0'; signal araddr_pipe_sel : std_logic := '0'; -- '0' indicates mux select from AXI -- '1' indicates mux select from AR Addr Register signal axi_araddr_full : std_logic := '0'; signal axi_arready_int : std_logic := '0'; signal axi_early_arready_int : std_logic := '0'; signal axi_aresetn_d1 : std_logic := '0'; signal axi_aresetn_d2 : std_logic := '0'; signal axi_aresetn_re : std_logic := '0'; signal axi_aresetn_re_reg : std_logic := '0'; signal no_ar_ack_cmb : std_logic := '0'; signal no_ar_ack : std_logic := '0'; signal pend_rd_op_cmb : std_logic := '0'; signal pend_rd_op : std_logic := '0'; signal axi_arid_pipe : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_arsize_pipe : std_logic_vector (2 downto 0) := (others => '0'); signal axi_arsize_pipe_4byte : std_logic := '0'; signal axi_arsize_pipe_8byte : std_logic := '0'; signal axi_arsize_pipe_16byte : std_logic := '0'; signal axi_arsize_pipe_32byte : std_logic := '0'; -- v1.03a signal axi_arsize_pipe_max : std_logic := '0'; signal curr_arsize : std_logic_vector (2 downto 0) := (others => '0'); signal curr_arsize_reg : std_logic_vector (2 downto 0) := (others => '0'); signal axi_arlen_pipe : std_logic_vector(7 downto 0) := (others => '0'); signal axi_arlen_pipe_1_or_2 : std_logic := '0'; signal curr_arlen : std_logic_vector(7 downto 0) := (others => '0'); signal curr_arlen_reg : std_logic_vector(7 downto 0) := (others => '0'); signal axi_arburst_pipe : std_logic_vector(1 downto 0) := (others => '0'); signal axi_arburst_pipe_fixed : std_logic := '0'; signal curr_arburst : std_logic_vector(1 downto 0) := (others => '0'); signal curr_wrap_burst : std_logic := '0'; signal curr_wrap_burst_reg : std_logic := '0'; signal max_wrap_burst : std_logic := '0'; signal curr_incr_burst : std_logic := '0'; signal curr_fixed_burst : std_logic := '0'; signal curr_fixed_burst_reg : std_logic := '0'; -- BRAM Address Counter signal bram_addr_ld_en : std_logic := '0'; signal bram_addr_ld_en_i : std_logic := '0'; signal bram_addr_ld_en_mod : std_logic := '0'; signal bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_ld_wrap : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_inc : std_logic := '0'; signal bram_addr_inc_mod : std_logic := '0'; signal bram_addr_inc_wrap_mod : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Read Data Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type RD_DATA_SM_TYPE is ( IDLE, SNG_ADDR, SEC_ADDR, FULL_PIPE, FULL_THROTTLE, LAST_ADDR, LAST_THROTTLE, LAST_DATA, LAST_DATA_AR_PEND ); signal rd_data_sm_cs, rd_data_sm_ns : RD_DATA_SM_TYPE; signal rd_adv_buf : std_logic := '0'; signal axi_rd_burst : std_logic := '0'; signal axi_rd_burst_two : std_logic := '0'; signal act_rd_burst : std_logic := '0'; signal act_rd_burst_set : std_logic := '0'; signal act_rd_burst_clr : std_logic := '0'; signal act_rd_burst_two : std_logic := '0'; -- Rd Data Buffer/Register signal rd_skid_buf_ld_cmb : std_logic := '0'; signal rd_skid_buf_ld_reg : std_logic := '0'; signal rd_skid_buf_ld : std_logic := '0'; signal rd_skid_buf_ld_imm : std_logic := '0'; signal rd_skid_buf : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal rddata_mux_sel_cmb : std_logic := '0'; signal rddata_mux_sel : std_logic := '0'; signal axi_rdata_en : std_logic := '0'; signal axi_rdata_mux : std_logic_vector (C_AXI_DATA_WIDTH+8C_ECC-1 downto 0) := (others => '0'); -- Read Burst Counter signal brst_cnt_max : std_logic := '0'; signal brst_cnt_max_d1 : std_logic := '0'; signal brst_cnt_max_re : std_logic := '0'; signal end_brst_rd_clr_cmb : std_logic := '0'; signal end_brst_rd_clr : std_logic := '0'; signal end_brst_rd : std_logic := '0'; signal brst_zero : std_logic := '0'; signal brst_one : std_logic := '0'; signal brst_cnt_ld : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0'); signal brst_cnt_rst : std_logic := '0'; signal brst_cnt_ld_en : std_logic := '0'; signal brst_cnt_ld_en_i : std_logic := '0'; signal brst_cnt_dec : std_logic := '0'; signal brst_cnt : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0'); -- AXI Read Response Signals signal axi_rid_temp : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_rid_temp_full : std_logic := '0'; signal axi_rid_temp_full_d1 : std_logic := '0'; signal axi_rid_temp_full_fe : std_logic := '0'; signal axi_rid_temp2 : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_rid_temp2_full : std_logic := '0'; signal axi_b2b_rid_adv : std_logic := '0'; signal axi_rid_int : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0'); signal axi_rvalid_clr_ok : std_logic := '0'; signal axi_rvalid_set_cmb : std_logic := '0'; signal axi_rvalid_set : std_logic := '0'; signal axi_rvalid_int : std_logic := '0'; signal axi_rlast_int : std_logic := '0'; signal axi_rlast_set : std_logic := '0'; -- Internal BRAM Signals signal bram_en_cmb : std_logic := '0'; signal bram_en_int : std_logic := '0'; signal bram_addr_int : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- Narrow Burst Signals signal curr_narrow_burst_cmb : std_logic := '0'; signal curr_narrow_burst : std_logic := '0'; signal narrow_burst_cnt_ld : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_burst_cnt_ld_reg : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_burst_cnt_ld_mod : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_addr_rst : std_logic := '0'; signal narrow_addr_ld_en : std_logic := '0'; signal narrow_addr_dec : std_logic := '0'; signal narrow_bram_addr_inc : std_logic := '0'; signal narrow_bram_addr_inc_d1 : std_logic := '0'; signal narrow_bram_addr_inc_re : std_logic := '0'; signal narrow_addr_int : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal curr_ua_narrow_wrap : std_logic := '0'; signal curr_ua_narrow_incr : std_logic := '0'; signal ua_narrow_load : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); -- State machine type declarations type RLAST_SM_TYPE is ( IDLE, W8_THROTTLE, W8_2ND_LAST_DATA, W8_LAST_DATA, -- W8_LAST_DATA_B2, W8_THROTTLE_B2 ); signal rlast_sm_cs, rlast_sm_ns : RLAST_SM_TYPE; signal last_bram_addr : std_logic := '0'; signal set_last_bram_addr : std_logic := '0'; signal alast_bram_addr : std_logic := '0'; signal rd_b2b_elgible : std_logic := '0'; signal rd_b2b_elgible_no_thr_check : std_logic := '0'; signal throttle_last_data : std_logic := '0'; signal disable_b2b_brst_cmb : std_logic := '0'; signal disable_b2b_brst : std_logic := '0'; signal axi_b2b_brst_cmb : std_logic := '0'; signal axi_b2b_brst : std_logic := '0'; signal do_cmplt_burst_cmb : std_logic := '0'; signal do_cmplt_burst : std_logic := '0'; signal do_cmplt_burst_clr : std_logic := '0'; ------------------------------------------------------------------------------- -- ECC Signals ------------------------------------------------------------------------------- signal UnCorrectedRdData : std_logic_vector (0 to C_AXI_DATA_WIDTH-1) := (others => '0'); -- Move vector from core ECC module to use in AXI RDATA register output signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to ECC @ 32-bit data width signal Syndrome_7 : std_logic_vector (0 to 11) := (others => '0'); -- Specific to ECC @ 64-bit data width signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal Sl_UE_i : std_logic := '0'; signal UE_Q : std_logic := '0'; -- v1.03a -- Hsiao ECC signal syndrome_r : std_logic_vector (C_INT_ECC_WIDTH - 1 downto 0) := (others => '0'); constant CODE_WIDTH : integer := C_AXI_DATA_WIDTH + C_INT_ECC_WIDTH; constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; signal h_rows : std_logic_vector (CODE_WIDTH ECC_WIDTH - 1 downto 0); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- AXI Read Address Channel Output Signals --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_ARREADY_DUAL -- Purpose: Generate AXI_ARREADY when in dual port mode. --------------------------------------------------------------------------- GEN_ARREADY_DUAL: if C_SINGLE_PORT_BRAM = 0 generate begin -- Ensure ARREADY only gets asserted early when acknowledge recognized -- on AXI read data channel. AXI_ARREADY <= axi_arready_int or (axi_early_arready_int and rd_adv_buf); end generate GEN_ARREADY_DUAL; --------------------------------------------------------------------------- -- Generate: GEN_ARREADY_SNG -- Purpose: Generate AXI_ARREADY when in single port mode. --------------------------------------------------------------------------- GEN_ARREADY_SNG: if C_SINGLE_PORT_BRAM = 1 generate begin -- ARREADY generated by sng_port_arb module AXI_ARREADY <= '0'; axi_arready_int <= '0'; end generate GEN_ARREADY_SNG; --------------------------------------------------------------------------- -- AXI Read Data Channel Output Signals --------------------------------------------------------------------------- -- UE flag is detected is same clock cycle that read data is presented on -- the AXI bus. Must drive SLVERR combinatorially to align with corrupted -- detected data word. AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int; AXI_RVALID <= axi_rvalid_int; AXI_RID <= axi_rid_int; AXI_RLAST <= axi_rlast_int; --------------------------------------------------------------------------- -- -- * AXI Read Address Channel Interface * -- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_AR_PIPE_SNG -- Purpose: Only generate pipeline registers when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AR_PIPE_SNG: if C_SINGLE_PORT_BRAM = 1 generate begin -- Unused AW pipeline (set default values) araddr_pipe_ld <= '0'; axi_araddr_pipe <= AXI_ARADDR; axi_arid_pipe <= AXI_ARID; axi_arsize_pipe <= AXI_ARSIZE; axi_arlen_pipe <= AXI_ARLEN; axi_arburst_pipe <= AXI_ARBURST; axi_arlen_pipe_1_or_2 <= '0'; axi_arburst_pipe_fixed <= '0'; axi_araddr_full <= '0'; end generate GEN_AR_PIPE_SNG; --------------------------------------------------------------------------- -- Generate: GEN_AR_PIPE_DUAL -- Purpose: Only generate pipeline registers when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AR_PIPE_DUAL: if C_SINGLE_PORT_BRAM = 0 generate begin ----------------------------------------------------------------------- -- AXI Read Address Buffer/Register -- (mimic behavior of address pipeline for AXI_ARID) ----------------------------------------------------------------------- GEN_ARADDR: for i in C_AXI_ADDR_WIDTH-1 downto 0 generate begin REG_ARADDR: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- No reset condition to save resources/timing if (araddr_pipe_ld = '1') then axi_araddr_pipe (i) <= AXI_ARADDR (i); else axi_araddr_pipe (i) <= axi_araddr_pipe (i); end if; end if; end process REG_ARADDR; end generate GEN_ARADDR; ------------------------------------------------------------------- -- Register ARID -- No reset condition to save resources/timing ------------------------------------------------------------------- REG_ARID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (araddr_pipe_ld = '1') then axi_arid_pipe <= AXI_ARID; else axi_arid_pipe <= axi_arid_pipe; end if; end if; end process REG_ARID; --------------------------------------------------------------------------- -- In parallel to ARADDR pipeline and ARID -- Use same control signals to capture AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST. -- Register AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST -- No reset condition to save resources/timing REG_ARCTRL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (araddr_pipe_ld = '1') then axi_arsize_pipe <= AXI_ARSIZE; axi_arlen_pipe <= AXI_ARLEN; axi_arburst_pipe <= AXI_ARBURST; else axi_arsize_pipe <= axi_arsize_pipe; axi_arlen_pipe <= axi_arlen_pipe; axi_arburst_pipe <= axi_arburst_pipe; end if; end if; end process REG_ARCTRL; --------------------------------------------------------------------------- -- Create signals that indicate value of AXI_ARLEN in pipeline stage -- Used to decode length of burst when BRAM address can be loaded early -- when pipeline is full. -- -- Add early decode of ARBURST in pipeline. -- Copy logic from WR_CHNL module (similar logic). -- Add early decode of ARSIZE = 4 bytes in pipeline. REG_ARLEN_PIPE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- No reset condition to save resources/timing if (araddr_pipe_ld = '1') then -- Create merge to decode ARLEN of ONE or TWO if (AXI_ARLEN = AXI_ARLEN_ONE) or (AXI_ARLEN = AXI_ARLEN_TWO) then axi_arlen_pipe_1_or_2 <= '1'; else axi_arlen_pipe_1_or_2 <= '0'; end if; -- Early decode on value in pipeline of ARBURST if (AXI_ARBURST = C_AXI_BURST_FIXED) then axi_arburst_pipe_fixed <= '1'; else axi_arburst_pipe_fixed <= '0'; end if; else axi_arlen_pipe_1_or_2 <= axi_arlen_pipe_1_or_2; axi_arburst_pipe_fixed <= axi_arburst_pipe_fixed; end if; end if; end process REG_ARLEN_PIPE; --------------------------------------------------------------------------- -- Create full flag for ARADDR pipeline -- Set when read address register is loaded. -- Cleared when read address stored in register is loaded into BRAM -- address counter. REG_RDADDR_FULL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- (bram_addr_ld_en = '1' and araddr_pipe_sel = '1') then (bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and araddr_pipe_ld = '0') then axi_araddr_full <= '0'; elsif (araddr_pipe_ld = '1') then axi_araddr_full <= '1'; else axi_araddr_full <= axi_araddr_full; end if; end if; end process REG_RDADDR_FULL; --------------------------------------------------------------------------- end generate GEN_AR_PIPE_DUAL; --------------------------------------------------------------------------- -- v1.03a -- Add early decode of ARSIZE = max size in pipeline based on AXI data -- bus width (use constant, C_AXI_SIZE_MAX) REG_ARSIZE_PIPE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_arsize_pipe_max <= '0'; elsif (araddr_pipe_ld = '1') then -- Early decode of ARSIZE in pipeline equal to max # of bytes -- based on AXI data bus width if (AXI_ARSIZE = C_AXI_SIZE_MAX) then axi_arsize_pipe_max <= '1'; else axi_arsize_pipe_max <= '0'; end if; else axi_arsize_pipe_max <= axi_arsize_pipe_max; end if; end if; end process REG_ARSIZE_PIPE; --------------------------------------------------------------------------- -- Generate: GE_ARREADY -- Purpose: ARREADY is only created here when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_ARREADY: if (C_SINGLE_PORT_BRAM = 0) generate begin ---------------------------------------------------------------------------- -- AXI_ARREADY Output Register -- Description: Keep AXI_ARREADY output asserted until ARADDR pipeline -- is full. When a full condition is reached, negate -- ARREADY as another AR address can not be accepted. -- Add condition to keep ARReady asserted if loading current --- ARADDR pipeline value into the BRAM address counter. -- Indicated by assertion of bram_addr_ld_en & araddr_pipe_sel. -- ---------------------------------------------------------------------------- REG_ARREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_arready_int <= '0'; -- Detect end of S_AXI_AResetn to assert AWREADY and accept -- new AWADDR values elsif (axi_aresetn_re_reg = '1') or -- Add condition for early ARREADY to keep pipeline full (bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and axi_early_arready_int = '0') then axi_arready_int <= '1'; -- Add conditional check if ARREADY is asserted (with ARVALID) (one clock cycle later) -- when the address pipeline is full. elsif (araddr_pipe_ld = '1') or (AXI_ARVALID = '1' and axi_arready_int = '1' and axi_araddr_full = '1') then axi_arready_int <= '0'; else axi_arready_int <= axi_arready_int; end if; end if; end process REG_ARREADY; ---------------------------------------------------------------------------- REG_EARLY_ARREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_early_arready_int <= '0'; -- Pending ARADDR and ARREADY is not yet asserted to accept -- operation (due to ARADDR being full) elsif (AXI_ARVALID = '1' and axi_arready_int = '0' and axi_araddr_full = '1') and (alast_bram_addr = '1') and -- Add check for elgible back-to-back BRAM load (rd_b2b_elgible = '1') then axi_early_arready_int <= '1'; else axi_early_arready_int <= '0'; end if; end if; end process REG_EARLY_ARREADY; --------------------------------------------------------------------------- -- Need to detect end of reset cycle to assert ARREADY on AXI bus REG_ARESETN: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then axi_aresetn_d1 <= S_AXI_AResetn; axi_aresetn_d2 <= axi_aresetn_d1; axi_aresetn_re_reg <= axi_aresetn_re; end if; end process REG_ARESETN; -- Create combinatorial RE detect of S_AXI_AResetn axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0'; ---------------------------------------------------------------------------- end generate GEN_ARREADY; --------------------------------------------------------------------------- -- Generate: GEN_DUAL_ADDR_CNT -- Purpose: Instantiate BRAM address counter unique for wr_chnl logic -- only when controller configured in dual port mode. --------------------------------------------------------------------------- GEN_DUAL_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 0) generate begin --------------------------------------------------------------------------- -- Replace I_ADDR_CNT module usage of pf_counter in proc_common library. -- Only need to use lower 12-bits of address due to max AXI burst size -- Since AXI guarantees bursts do not cross 4KB boundary, the counting part -- of I_ADDR_CNT can be reduced to max 4KB. -- -- No reset on bram_addr_int. -- Increment ONLY. REG_ADDR_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (bram_addr_ld_en_mod = '1') then bram_addr_int <= bram_addr_ld; elsif (bram_addr_inc_mod = '1') then bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12) <= bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12); bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <= std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1); end if; end if; end process REG_ADDR_CNT; --------------------------------------------------------------------------- -- Set defaults to shared address counter -- Only used in single port configurations Sng_BRAM_Addr_Ld_En <= '0'; Sng_BRAM_Addr_Ld <= (others => '0'); Sng_BRAM_Addr_Inc <= '0'; end generate GEN_DUAL_ADDR_CNT; --------------------------------------------------------------------------- -- Generate: GEN_SNG_ADDR_CNT -- Purpose: When configured in single port BRAM mode, address counter -- is shared with rd_chnl module. Assign output signals here -- to counter instantiation at full_axi module level. --------------------------------------------------------------------------- GEN_SNG_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 1) generate begin Sng_BRAM_Addr_Ld_En <= bram_addr_ld_en_mod; Sng_BRAM_Addr_Ld <= bram_addr_ld; Sng_BRAM_Addr_Inc <= bram_addr_inc_mod; bram_addr_int <= Sng_BRAM_Addr; end generate GEN_SNG_ADDR_CNT; --------------------------------------------------------------------------- -- BRAM address load mux. -- Either load BRAM counter directly from AXI bus or from stored registered value -- Use registered signal to indicate current operation is a WRAP burst -- -- Match bram_addr_ld to what asserts bram_addr_ld_en_mod -- Include bram_addr_inc_mod when asserted to use bram_addr_ld_wrap value -- (otherwise use pipelined or AXI bus value to load BRAM address counter) bram_addr_ld <= bram_addr_ld_wrap when (max_wrap_burst = '1' and curr_wrap_burst_reg = '1' and bram_addr_inc_wrap_mod = '1') else axi_araddr_pipe (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) when (araddr_pipe_sel = '1') else AXI_ARADDR (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); --------------------------------------------------------------------------- -- On wrap burst max loads (simultaneous BRAM address increment is asserted). -- Ensure that load has higher priority over increment. -- Use registered signal to indicate current operation is a WRAP burst bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or (max_wrap_burst = '1' and curr_wrap_burst_reg = '1' and bram_addr_inc_wrap_mod = '1')) else '0'; -- Create a special bram_addr_inc_mod for use in the bram_addr_ld_en_mod signal -- logic. No need for the check if the current operation is NOT a fixed AND a wrap -- burst. The transfer will be one or the other. -- Found issue when narrow FIXED length burst is incorrectly -- incrementing BRAM address counter bram_addr_inc_wrap_mod <= bram_addr_inc when (curr_narrow_burst = '0') else narrow_bram_addr_inc_re; ---------------------------------------------------------------------------- -- Narrow bursting -- -- Handle read burst addressing on narrow burst operations -- Intercept BRAM address increment flag, bram_addr_inc and only -- increment address when the number of BRAM reads match the width of the -- AXI data bus. -- For a 32-bit BRAM, byte burst will increment the BRAM address -- after four reads from BRAM. -- For a 256-bit BRAM, a byte burst will increment the BRAM address -- after 32 reads from BRAM. -- Based on current operation being a narrow burst, hold off BRAM -- address increment until narrow burst fits BRAM data width. -- For non narrow burst operations, use bram_addr_inc from data SM. -- -- Add in check that burst type is not FIXED, curr_fixed_burst_reg -- bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else -- narrow_bram_addr_inc_re; -- -- -- Replace w/ below generate statements based on supporting narrow transfers or not. -- Create generate statement around the signal assignment for bram_addr_inc_mod. --------------------------------------------------------------------------- -- Generate: GEN_BRAM_INC_MOD_W_NARROW -- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers -- are supported in design instantiation. --------------------------------------------------------------------------- GEN_BRAM_INC_MOD_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin -- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else (narrow_bram_addr_inc_re and not (curr_fixed_burst_reg)); end generate GEN_BRAM_INC_MOD_W_NARROW; --------------------------------------------------------------------------- -- Generate: GEN_WO_NARROW -- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers -- are not supported in the design instantiation. -- Drive default values for narrow counter and logic when -- narrow operation support is disabled. --------------------------------------------------------------------------- GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate begin -- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter bram_addr_inc_mod <= bram_addr_inc and not (curr_fixed_burst_reg); narrow_addr_rst <= '0'; narrow_burst_cnt_ld_mod <= (others => '0'); narrow_addr_dec <= '0'; narrow_addr_ld_en <= '0'; narrow_bram_addr_inc <= '0'; narrow_bram_addr_inc_d1 <= '0'; narrow_bram_addr_inc_re <= '0'; narrow_addr_int <= (others => '0'); curr_narrow_burst <= '0'; end generate GEN_WO_NARROW; --------------------------------------------------------------------------- -- -- Only instantiate NARROW_CNT and supporting logic when narrow transfers -- are supported and utilized by masters in the AXI system. -- The design parameter, C_S_AXI_SUPPORTS_NARROW will indicate this. -- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NARROW_CNT -- Purpose: Instantiate narrow counter and logic when narrow -- operation support is enabled. --------------------------------------------------------------------------- GEN_NARROW_CNT: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin --------------------------------------------------------------------------- -- -- Generate seperate smaller counter for narrow burst operations -- Replace I_NARROW_CNT module usage of pf_counter_top from proc_common library. -- -- Counter size is adjusted based on size of data burst. -- -- For example, 32-bit data width BRAM, minimum narrow width -- burst is 8 bits resulting in a count 3 downto 0. So the -- minimum counter width = 2 bits. -- -- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst -- is 8 bits resulting in a count 31 downto 0. So the -- minimum counter width = 5 bits. -- -- Size of counter = C_NARROW_BURST_CNT_LEN -- --------------------------------------------------------------------------- REG_NARROW_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (narrow_addr_rst = '1') then narrow_addr_int <= (others => '0'); -- Load enable elsif (narrow_addr_ld_en = '1') then narrow_addr_int <= narrow_burst_cnt_ld_mod; -- Decrement ONLY (no increment functionality) elsif (narrow_addr_dec = '1') then narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0) <= std_logic_vector (unsigned (narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0)) - 1); end if; end if; end process REG_NARROW_CNT; --------------------------------------------------------------------------- narrow_addr_rst <= not (S_AXI_AResetn); -- Modify narrow burst count load value based on -- unalignment of AXI address value narrow_burst_cnt_ld_mod <= ua_narrow_load when (curr_ua_narrow_wrap = '1' or curr_ua_narrow_incr = '1') else narrow_burst_cnt_ld when (bram_addr_ld_en = '1') else narrow_burst_cnt_ld_reg; narrow_addr_dec <= bram_addr_inc when (curr_narrow_burst = '1') else '0'; narrow_addr_ld_en <= (curr_narrow_burst_cmb and bram_addr_ld_en) or narrow_bram_addr_inc_re; narrow_bram_addr_inc <= '1' when (narrow_addr_int = NARROW_CNT_MAX) and (curr_narrow_burst = '1') -- Ensure that narrow address counter doesn't -- flag max or get loaded to -- reset narrow counter until AXI read data -- bus has acknowledged current -- data on the AXI bus. Use rd_adv_buf signal -- to indicate the non throttle -- condition on the AXI bus. and (bram_addr_inc = '1') else '0'; ---------------------------------------------------------------------------- -- Detect rising edge of narrow_bram_addr_inc REG_NARROW_BRAM_ADDR_INC: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then narrow_bram_addr_inc_d1 <= '0'; else narrow_bram_addr_inc_d1 <= narrow_bram_addr_inc; end if; end if; end process REG_NARROW_BRAM_ADDR_INC; narrow_bram_addr_inc_re <= '1' when (narrow_bram_addr_inc = '1') and (narrow_bram_addr_inc_d1 = '0') else '0'; --------------------------------------------------------------------------- end generate GEN_NARROW_CNT; ---------------------------------------------------------------------------- -- Specify current ARSIZE signal -- Address pipeline MUX curr_arsize <= axi_arsize_pipe when (araddr_pipe_sel = '1') else AXI_ARSIZE; REG_ARSIZE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then curr_arsize_reg <= (others => '0'); -- Register curr_arsize when bram_addr_ld_en = '1' elsif (bram_addr_ld_en = '1') then curr_arsize_reg <= curr_arsize; else curr_arsize_reg <= curr_arsize_reg; end if; end if; end process REG_ARSIZE; --------------------------------------------------------------------------- -- Generate: GEN_NARROW_EN -- Purpose: Only instantiate logic to determine if current burst -- is a narrow burst when narrow bursting logic is supported. --------------------------------------------------------------------------- GEN_NARROW_EN: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin ----------------------------------------------------------------------- -- Determine "narrow" burst transfers -- Compare the ARSIZE to the BRAM data width ----------------------------------------------------------------------- -- v1.03a -- Detect if current burst operation is of size /= to the full -- AXI data bus width. If not, then the current operation is a -- "narrow" burst. curr_narrow_burst_cmb <= '1' when (curr_arsize /= C_AXI_SIZE_MAX) else '0'; --------------------------------------------------------------------------- -- Register flag indicating the current operation -- is a narrow read burst NARROW_BURST_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Need to reset this flag at end of narrow burst operation -- Ensure if curr_narrow_burst got set during previous transaction, axi_rlast_set -- doesn't clear the flag (add check for pend_rd_op negated). if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_set = '1' and pend_rd_op = '0' and bram_addr_ld_en = '0') then curr_narrow_burst <= '0'; -- Add check for burst operation using ARLEN value -- Ensure that narrow burst flag does not get set during FIXED burst types elsif (bram_addr_ld_en = '1') and (curr_arlen /= AXI_ARLEN_ONE) and (curr_fixed_burst = '0') then curr_narrow_burst <= curr_narrow_burst_cmb; end if; end if; end process NARROW_BURST_REG; end generate GEN_NARROW_EN; --------------------------------------------------------------------------- -- Generate: GEN_NARROW_CNT_LD -- Purpose: Only instantiate logic to determine narrow burst counter -- load value when narrow bursts are enabled. --------------------------------------------------------------------------- GEN_NARROW_CNT_LD: if (C_S_AXI_SUPPORTS_NARROW = 1) generate signal curr_arsize_unsigned : unsigned (2 downto 0) := (others => '0'); signal axi_byte_div_curr_arsize : integer := 1; begin -- v1.03a -- Create narrow burst counter load value based on current operation -- "narrow" data width (indicated by value of AWSIZE). curr_arsize_unsigned <= unsigned (curr_arsize); -- XST does not support divisors that are not constants and powers of 2. -- Create process to create a fixed value for divisor. -- Replace this statement: -- narrow_burst_cnt_ld <= std_logic_vector ( -- to_unsigned ( -- (C_AXI_DATA_WIDTH_BYTES / (2*(to_integer (curr_arsize_unsigned))) ) - 1, -- C_NARROW_BURST_CNT_LEN)); -- -- With this new process and subsequent signal assignment: -- DIV_AWSIZE: process (curr_arsize_unsigned) -- begin -- -- case (to_integer (curr_arsize_unsigned)) is -- when 0 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1; -- when 1 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2; -- when 2 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4; -- when 3 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8; -- when 4 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16; -- when 5 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32; -- when 6 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64; -- when 7 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128; -- --coverage off -- when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES; -- --coverage on -- end case; -- -- end process DIV_AWSIZE; -- w/ CR # 609695 -- With this new process and subsequent signal assignment: DIV_AWSIZE: process (curr_arsize_unsigned) begin case (curr_arsize_unsigned) is when "000" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1; when "001" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2; when "010" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4; when "011" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8; when "100" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16; when "101" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32; when "110" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64; when "111" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128; --coverage off when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES; --coverage on end case; end process DIV_AWSIZE; -- v1.03a -- Replace with new signal assignment. -- For synthesis to support only divisors that are constant and powers of two. -- Updated else clause for simulation warnings w/ CR # 609695 narrow_burst_cnt_ld <= std_logic_vector ( to_unsigned ( (axi_byte_div_curr_arsize) - 1, C_NARROW_BURST_CNT_LEN)) when (axi_byte_div_curr_arsize > 0) else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN)); --------------------------------------------------------------------------- -- Register narrow burst count load indicator REG_NAR_BRST_CNT_LD: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then narrow_burst_cnt_ld_reg <= (others => '0'); elsif (bram_addr_ld_en = '1') then narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld; else narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld_reg; end if; end if; end process REG_NAR_BRST_CNT_LD; --------------------------------------------------------------------------- end generate GEN_NARROW_CNT_LD; ---------------------------------------------------------------------------- -- Handling for WRAP burst types -- -- For WRAP burst types, the counter value will roll over when the burst -- boundary is reached. -- Boundary is reached based on ARSIZE and ARLEN. -- -- Goal is to minimize muxing on initial load of counter value. -- On WRAP burst types, detect when the max address is reached. -- When the max address is reached, re-load counter with lower -- address value set to '0'. ---------------------------------------------------------------------------- -- Detect valid WRAP burst types curr_wrap_burst <= '1' when (curr_arburst = C_AXI_BURST_WRAP) else '0'; curr_incr_burst <= '1' when (curr_arburst = C_AXI_BURST_INCR) else '0'; curr_fixed_burst <= '1' when (curr_arburst = C_AXI_BURST_FIXED) else '0'; ---------------------------------------------------------------------------- -- Register curr_wrap_burst & curr_fixed_burst signals when BRAM -- address counter is initially loaded REG_CURR_BRST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then curr_wrap_burst_reg <= '0'; curr_fixed_burst_reg <= '0'; elsif (bram_addr_ld_en = '1') then curr_wrap_burst_reg <= curr_wrap_burst; curr_fixed_burst_reg <= curr_fixed_burst; else curr_wrap_burst_reg <= curr_wrap_burst_reg; curr_fixed_burst_reg <= curr_fixed_burst_reg; end if; end if; end process REG_CURR_BRST; --------------------------------------------------------------------------- -- Instance: I_WRAP_BRST -- -- Description: -- -- Instantiate WRAP_BRST module -- Logic to generate the wrap around value to load into the BRAM address -- counter on WRAP burst transactions. -- WRAP value is based on current ARLEN, ARSIZE (for narrows) and -- data width of BRAM module. -- --------------------------------------------------------------------------- I_WRAP_BRST : entity work.wrap_brst generic map ( C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , curr_axlen => curr_arlen , curr_axsize => curr_arsize , curr_narrow_burst => curr_narrow_burst , narrow_bram_addr_inc_re => narrow_bram_addr_inc_re , bram_addr_ld_en => bram_addr_ld_en , bram_addr_ld => bram_addr_ld , bram_addr_int => bram_addr_int , bram_addr_ld_wrap => bram_addr_ld_wrap , max_wrap_burst_mod => max_wrap_burst ); ---------------------------------------------------------------------------- -- Specify current ARBURST signal -- Input address pipeline MUX curr_arburst <= axi_arburst_pipe when (araddr_pipe_sel = '1') else AXI_ARBURST; ---------------------------------------------------------------------------- -- Specify current AWBURST signal -- Input address pipeline MUX curr_arlen <= axi_arlen_pipe when (araddr_pipe_sel = '1') else AXI_ARLEN; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_UA_NARROW -- Purpose: Only instantiate logic for burst narrow WRAP operations when -- AXI bus protocol is not set for AXI-LITE and narrow -- burst operations are supported. -- --------------------------------------------------------------------------- GEN_UA_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin --------------------------------------------------------------------------- -- -- New logic to detect unaligned address on a narrow WRAP burst transaction. -- If this condition is met, then the narrow burst counter will be -- initially loaded with an offset value corresponding to the unalignment -- in the ARADDR value. -- -- -- Create a sub module for all logic to determine the narrow burst counter -- offset value on unaligned WRAP burst operations. -- -- Module generates the following signals: -- -- => curr_ua_narrow_wrap, to indicate the current -- operation is an unaligned narrow WRAP burst. -- -- => curr_ua_narrow_incr, to load narrow burst counter -- for unaligned INCR burst operations. -- -- => ua_narrow_load, narrow counter load value. -- Sized, (C_NARROW_BURST_CNT_LEN-1 downto 0) -- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Instance: I_UA_NARROW -- -- Description: -- -- Creates a narrow burst count load value when an operation -- is an unaligned narrow WRAP or INCR burst type. Used by -- I_NARROW_CNT module. -- -- Logic is customized for each C_AXI_DATA_WIDTH. -- --------------------------------------------------------------------------- I_UA_NARROW : entity work.ua_narrow generic map ( C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_NARROW_BURST_CNT_LEN => C_NARROW_BURST_CNT_LEN ) port map ( curr_wrap_burst => curr_wrap_burst , -- in curr_incr_burst => curr_incr_burst , -- in bram_addr_ld_en => bram_addr_ld_en , -- in curr_axlen => curr_arlen , -- in curr_axsize => curr_arsize , -- in curr_axaddr_lsb => curr_araddr_lsb , -- in curr_ua_narrow_wrap => curr_ua_narrow_wrap , -- out curr_ua_narrow_incr => curr_ua_narrow_incr , -- out ua_narrow_load => ua_narrow_load -- out ); -- Use in all C_AXI_DATA_WIDTH generate statements -- Only probe least significant BRAM address bits -- C_BRAM_ADDR_ADJUST_FACTOR offset down to 0. curr_araddr_lsb <= axi_araddr_pipe (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) when (araddr_pipe_sel = '1') else AXI_ARADDR (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0); end generate GEN_UA_NARROW; ---------------------------------------------------------------------------- -- -- New logic to detect if pending operation in ARADDR pipeline is -- elgible for back-to-back no "bubble" performance. And BRAM address -- counter can be loaded upon last BRAM address presented for the current -- operation. -- This condition exists when the ARADDR pipeline is full and the pending -- operation is a burst >= length of two data beats. -- And not a FIXED burst type (must be INCR or WRAP type). -- The DATA SM handles detecting a throttle condition and will void -- the capability to be a back-to-back in performance transaction. -- -- Add check if new operation is a narrow burst (to be loaded into BRAM -- counter) -- Add check for throttling condition on after last BRAM address is -- presented -- ---------------------------------------------------------------------------- -- v1.03a rd_b2b_elgible_no_thr_check <= '1' when (axi_araddr_full = '1') and (axi_arlen_pipe_1_or_2 /= '1') and (axi_arburst_pipe_fixed /= '1') and (disable_b2b_brst = '0') and (axi_arsize_pipe_max = '1') else '0'; rd_b2b_elgible <= '1' when (rd_b2b_elgible_no_thr_check = '1') and (throttle_last_data = '0') else '0'; -- Check if SM is in LAST_THROTTLE state which also indicates we are throttling at -- the last data beat in the read burst. Ensures that the bursts are not implemented -- as back-to-back bursts and RVALID will negate upon recognition of RLAST and RID -- pipeline will be advanced properly. -- Fix timing path on araddr_pipe_sel generated in RDADDR SM -- SM uses rd_b2b_elgible signal which checks throttle condition on -- last data beat to hold off loading new BRAM address counter for next -- back-to-back operation. -- Attempt to modify logic in generation of throttle_last_data signal. throttle_last_data <= '1' when ((brst_zero = '1') and (rd_adv_buf = '0')) or (rd_data_sm_cs = LAST_THROTTLE) else '0'; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_AR_SNG -- Purpose: If single port BRAM configuration, set all AR flags from -- logic generated in sng_port_arb module. -- --------------------------------------------------------------------------- GEN_AR_SNG: if (C_SINGLE_PORT_BRAM = 1) generate begin araddr_pipe_sel <= '0'; -- Unused in single port configuration ar_active <= Arb2AR_Active; bram_addr_ld_en <= ar_active_re; brst_cnt_ld_en <= ar_active_re; AR2Arb_Active_Clr <= axi_rlast_int and AXI_RREADY; -- Rising edge detect of Arb2AR_Active RE_AR_ACT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Clear ar_active_d1 early w/ ar_active -- So back to back ar_active assertions see the new transaction -- and initiate the read transfer. if (S_AXI_AResetn = C_RESET_ACTIVE) or ((axi_rlast_int and AXI_RREADY) = '1') then ar_active_d1 <= '0'; else ar_active_d1 <= ar_active; end if; end if; end process RE_AR_ACT; ar_active_re <= '1' when (ar_active = '1' and ar_active_d1 = '0') else '0'; end generate GEN_AR_SNG; --------------------------------------------------------------------------- -- -- Generate: GEN_AW_DUAL -- Purpose: Generate AW control state machine logic only when AXI4 -- controller is configured for dual port mode. In dual port -- mode, wr_chnl has full access over AW & port A of BRAM. -- --------------------------------------------------------------------------- GEN_AR_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate begin AR2Arb_Active_Clr <= '0'; -- Only used in single port case --------------------------------------------------------------------------- -- RD ADDR State Machine -- -- Description: Central processing unit for AXI write address -- channel interface handling and handshaking. -- -- Outputs: araddr_pipe_ld Not Registered -- araddr_pipe_sel Not Registered -- bram_addr_ld_en Not Registered -- brst_cnt_ld_en Not Registered -- ar_active_set Not Registered -- -- WR_ADDR_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_ADDR_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- RD_ADDR_SM_CMB_PROCESS: process ( AXI_ARVALID, axi_araddr_full, ar_active, no_ar_ack, pend_rd_op, last_bram_addr, rd_b2b_elgible, rd_addr_sm_cs ) begin -- assign default values for state machine outputs rd_addr_sm_ns <= rd_addr_sm_cs; araddr_pipe_ld_i <= '0'; bram_addr_ld_en_i <= '0'; brst_cnt_ld_en_i <= '0'; ar_active_set_i <= '0'; case rd_addr_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Reload BRAM address counter on last BRAM address of current burst -- if a new address is pending in the AR pipeline and is elgible to -- be loaded for subsequent back-to-back performance. if (last_bram_addr = '1' and rd_b2b_elgible = '1') then -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; brst_cnt_ld_en_i <= '1'; ar_active_set_i <= '1'; -- If loading BRAM counter for subsequent operation -- AND ARVALID is pending on the bus, go ahead and respond -- and fill ARADDR pipeline with next operation. -- -- Asserting the signal to load the ARADDR pipeline here -- allows the full bandwidth utilization to BRAM on -- back to back bursts of two data beats. if (AXI_ARVALID = '1') then araddr_pipe_ld_i <= '1'; rd_addr_sm_ns <= LD_ARADDR; else rd_addr_sm_ns <= IDLE; end if; elsif (AXI_ARVALID = '1') then -- If address pipeline is full -- ARReady output is negated -- Remain in this state -- -- Add check for already pending read operation -- in data SM, but waiting on throttle (even though ar_active is -- already set to '0'). if (ar_active = '0') and (no_ar_ack = '0') and (pend_rd_op = '0') then rd_addr_sm_ns <= IDLE; bram_addr_ld_en_i <= '1'; brst_cnt_ld_en_i <= '1'; ar_active_set_i <= '1'; -- Address counter is currently busy else -- Check if ARADDR pipeline is not full and can be loaded if (axi_araddr_full = '0') then rd_addr_sm_ns <= LD_ARADDR; araddr_pipe_ld_i <= '1'; end if; end if; -- ar_active -- Pending operation in pipeline that is waiting -- until current operation is complete (ar_active = '0') elsif (axi_araddr_full = '1') and (ar_active = '0') and (no_ar_ack = '0') and (pend_rd_op = '0') then rd_addr_sm_ns <= IDLE; -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; brst_cnt_ld_en_i <= '1'; ar_active_set_i <= '1'; end if; -- ARVALID ---------------------------- LD_ARADDR State --------------------------- when LD_ARADDR => -- Check here for subsequent BRAM address load when ARADDR pipe is loaded -- in previous clock cycle. -- -- Reload BRAM address counter on last BRAM address of current burst -- if a new address is pending in the AR pipeline and is elgible to -- be loaded for subsequent back-to-back performance. if (last_bram_addr = '1' and rd_b2b_elgible = '1') then -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; brst_cnt_ld_en_i <= '1'; ar_active_set_i <= '1'; -- If loading BRAM counter for subsequent operation -- AND ARVALID is pending on the bus, go ahead and respond -- and fill ARADDR pipeline with next operation. -- -- Asserting the signal to load the ARADDR pipeline here -- allows the full bandwidth utilization to BRAM on -- back to back bursts of two data beats. if (AXI_ARVALID = '1') then araddr_pipe_ld_i <= '1'; rd_addr_sm_ns <= LD_ARADDR; -- Stay in this state another clock cycle else rd_addr_sm_ns <= IDLE; end if; else rd_addr_sm_ns <= IDLE; end if; --coverage off ------------------------------ Default ---------------------------- when others => rd_addr_sm_ns <= IDLE; --coverage on end case; end process RD_ADDR_SM_CMB_PROCESS; --------------------------------------------------------------------------- -- CR # 582705 -- Ensure combinatorial SM output signals do not get set before -- the end of the reset (and ARREAADY can be set). bram_addr_ld_en <= bram_addr_ld_en_i and axi_aresetn_d2; brst_cnt_ld_en <= brst_cnt_ld_en_i and axi_aresetn_d2; ar_active_set <= ar_active_set_i and axi_aresetn_d2; araddr_pipe_ld <= araddr_pipe_ld_i and axi_aresetn_d2; RD_ADDR_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- if (S_AXI_AResetn = C_RESET_ACTIVE) then -- CR # 582705 -- Ensure that ar_active does not get asserted (from SM) before -- the end of reset and the ARREADY flag is set. if (axi_aresetn_d2 = C_RESET_ACTIVE) then rd_addr_sm_cs <= IDLE; else rd_addr_sm_cs <= rd_addr_sm_ns; end if; end if; end process RD_ADDR_SM_REG_PROCESS; --------------------------------------------------------------------------- -- Assert araddr_pipe_sel outside of SM logic -- The BRAM address counter will get loaded with value in ARADDR pipeline -- when data is stored in the ARADDR pipeline. araddr_pipe_sel <= '1' when (axi_araddr_full = '1') else '0'; --------------------------------------------------------------------------- -- Register for ar_active REG_AR_ACT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- if (S_AXI_AResetn = C_RESET_ACTIVE) then -- CR # 582705 if (axi_aresetn_d2 = C_RESET_ACTIVE) then ar_active <= '0'; elsif (ar_active_set = '1') then ar_active <= '1'; -- For code coverage closure, ensure priority encoding in if/else clause -- to prevent checking ar_active_set in reset clause. elsif (ar_active_clr = '1') then ar_active <= '0'; else ar_active <= ar_active; end if; end if; end process REG_AR_ACT; end generate GEN_AR_DUAL; --------------------------------------------------------------------------- -- -- REG_BRST_CNT. -- Read Burst Counter. -- No need to decrement burst counter. -- Able to load with fixed burst length value. -- Replace usage of proc_common_v4_0 library with direct HDL. -- -- Size of counter = C_BRST_CNT_SIZE -- Max size of burst transfer = 256 data beats -- --------------------------------------------------------------------------- REG_BRST_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (brst_cnt_rst = '1') then brst_cnt <= (others => '0'); -- Load burst counter elsif (brst_cnt_ld_en = '1') then brst_cnt <= brst_cnt_ld; -- Decrement ONLY (no increment functionality) elsif (brst_cnt_dec = '1') then brst_cnt (C_BRST_CNT_SIZE-1 downto 0) <= std_logic_vector (unsigned (brst_cnt (C_BRST_CNT_SIZE-1 downto 0)) - 1); end if; end if; end process REG_BRST_CNT; --------------------------------------------------------------------------- brst_cnt_rst <= not (S_AXI_AResetn); -- Determine burst count load value -- Either load BRAM counter directly from AXI bus or from stored registered value. -- Use mux signal for ARLEN BRST_CNT_LD_PROCESS : process (curr_arlen) variable brst_cnt_ld_int : integer := 0; begin brst_cnt_ld_int := to_integer (unsigned (curr_arlen (7 downto 0))); brst_cnt_ld <= std_logic_vector (to_unsigned (brst_cnt_ld_int, 8)); end process BRST_CNT_LD_PROCESS; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_BRST_MAX_W_NARROW -- Purpose: Generate registered logic for brst_cnt_max when the -- design instantiation supports narrow operations. -- --------------------------------------------------------------------------- GEN_BRST_MAX_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin REG_BRST_MAX: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1') -- Added with single port (13.1 release) or (end_brst_rd_clr = '1') then brst_cnt_max <= '0'; -- Replace usage of brst_cnt in this logic. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then -- Hold off assertion of brst_cnt_max on narrow burst transfers -- Must wait until narrow burst count = 0. if (curr_narrow_burst = '1') then if (narrow_bram_addr_inc = '1') then brst_cnt_max <= '1'; end if; else brst_cnt_max <= '1'; end if; else brst_cnt_max <= brst_cnt_max; end if; end if; end process REG_BRST_MAX; end generate GEN_BRST_MAX_W_NARROW; --------------------------------------------------------------------------- -- -- Generate: GEN_BRST_MAX_WO_NARROW -- Purpose: Generate registered logic for brst_cnt_max when the -- design instantiation does not support narrow operations. -- --------------------------------------------------------------------------- GEN_BRST_MAX_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate begin REG_BRST_MAX: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1') then brst_cnt_max <= '0'; -- Replace usage of brst_cnt in this logic. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then -- When narrow operations are not supported in the core -- configuration, no check for curr_narrow_burst on assertion. brst_cnt_max <= '1'; else brst_cnt_max <= brst_cnt_max; end if; end if; end process REG_BRST_MAX; end generate GEN_BRST_MAX_WO_NARROW; --------------------------------------------------------------------------- REG_BRST_MAX_D1: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then brst_cnt_max_d1 <= '0'; else brst_cnt_max_d1 <= brst_cnt_max; end if; end if; end process REG_BRST_MAX_D1; brst_cnt_max_re <= '1' when (brst_cnt_max = '1') and (brst_cnt_max_d1 = '0') else '0'; -- Set flag that end of burst is reached -- Need to capture this condition as the burst -- counter may get reloaded for a subsequent read burst REG_END_BURST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- SM may assert clear flag early (in case of narrow bursts) -- Wait until the end_brst_rd flag is asserted to clear the flag. if (S_AXI_AResetn = C_RESET_ACTIVE) or (end_brst_rd_clr = '1' and end_brst_rd = '1') then end_brst_rd <= '0'; elsif (brst_cnt_max_re = '1') then end_brst_rd <= '1'; end if; end if; end process REG_END_BURST; --------------------------------------------------------------------------- -- Create flag that indicates burst counter is reaching ZEROs (max of burst -- length) REG_BURST_ZERO: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or ((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ZERO)) then brst_zero <= '0'; elsif (brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE) then brst_zero <= '1'; else brst_zero <= brst_zero; end if; end if; end process REG_BURST_ZERO; --------------------------------------------------------------------------- -- Create additional flag that indicates burst counter is reaching ONEs -- (near end of burst length). Used to disable back-to-back condition in SM. REG_BURST_ONE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or ((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ONE)) or ((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE)) then brst_one <= '0'; elsif ((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_TWO)) or ((brst_cnt_ld_en = '1') and (brst_cnt_ld = C_BRST_CNT_ONE)) then brst_one <= '1'; else brst_one <= brst_one; end if; end if; end process REG_BURST_ONE; --------------------------------------------------------------------------- -- Register flags for read burst operation REG_RD_BURST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Clear axi_rd_burst flags when burst count gets to zeros (unless the burst -- counter is getting subsequently loaded for the new burst operation) -- -- Replace usage of brst_cnt in this logic. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_zero = '1' and brst_cnt_ld_en = '0') then axi_rd_burst <= '0'; axi_rd_burst_two <= '0'; elsif (brst_cnt_ld_en = '1') then if (curr_arlen /= AXI_ARLEN_ONE and curr_arlen /= AXI_ARLEN_TWO) then axi_rd_burst <= '1'; else axi_rd_burst <= '0'; end if; if (curr_arlen = AXI_ARLEN_TWO) then axi_rd_burst_two <= '1'; else axi_rd_burst_two <= '0'; end if; else axi_rd_burst <= axi_rd_burst; axi_rd_burst_two <= axi_rd_burst_two; end if; end if; end process REG_RD_BURST; --------------------------------------------------------------------------- -- Seeing issue with axi_rd_burst getting cleared too soon -- on subsquent brst_cnt_ld_en early assertion and pend_rd_op is asserted. -- Create flag for currently active read burst operation -- Gets asserted when burst counter is loaded, but does not -- get cleared until the RD_DATA_SM has completed the read -- burst operation REG_ACT_RD_BURST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (act_rd_burst_clr = '1') then act_rd_burst <= '0'; act_rd_burst_two <= '0'; elsif (act_rd_burst_set = '1') then -- If not loading the burst counter for a B2B operation -- Then act_rd_burst follows axi_rd_burst and -- act_rd_burst_two follows axi_rd_burst_two. -- Get registered value of axi_ signal. if (brst_cnt_ld_en = '0') then act_rd_burst <= axi_rd_burst; act_rd_burst_two <= axi_rd_burst_two; else -- Otherwise, duplicate logic for axi_* signals if burst counter -- is getting loaded. -- For improved code coverage here -- The act_rd_burst_set signal will never get asserted if the burst -- size is less than two data beats. So, the conditional check -- for (curr_arlen /= AXI_ARLEN_ONE) is never evaluated. Removed -- from this if clause. if (curr_arlen /= AXI_ARLEN_TWO) then act_rd_burst <= '1'; else act_rd_burst <= '0'; end if; if (curr_arlen = AXI_ARLEN_TWO) then act_rd_burst_two <= '1'; else act_rd_burst_two <= '0'; end if; -- Note: re-code this if/else clause. end if; else act_rd_burst <= act_rd_burst; act_rd_burst_two <= act_rd_burst_two; end if; end if; end process REG_ACT_RD_BURST; --------------------------------------------------------------------------- rd_adv_buf <= axi_rvalid_int and AXI_RREADY; --------------------------------------------------------------------------- -- RD DATA State Machine -- -- Description: Central processing unit for AXI write data -- channel interface handling and AXI write data response -- handshaking. -- -- Outputs: Name Type -- -- bram_en_int Registered -- bram_addr_inc Not Registered -- brst_cnt_dec Not Registered -- rddata_mux_sel Registered -- axi_rdata_en Not Registered -- axi_rvalid_set Registered -- -- -- RD_DATA_SM_CMB_PROCESS: Combinational process to determine next state. -- RD_DATA_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- RD_DATA_SM_CMB_PROCESS: process ( bram_addr_ld_en, rd_adv_buf, ar_active, axi_araddr_full, rd_b2b_elgible_no_thr_check, disable_b2b_brst, curr_arlen, axi_rd_burst, axi_rd_burst_two, act_rd_burst, act_rd_burst_two, end_brst_rd, brst_zero, brst_one, axi_b2b_brst, bram_en_int, rddata_mux_sel, end_brst_rd_clr, no_ar_ack, pend_rd_op, axi_rlast_int, rd_data_sm_cs ) begin -- assign default values for state machine outputs rd_data_sm_ns <= rd_data_sm_cs; bram_en_cmb <= bram_en_int; bram_addr_inc <= '0'; brst_cnt_dec <= '0'; rd_skid_buf_ld_cmb <= '0'; rd_skid_buf_ld_imm <= '0'; rddata_mux_sel_cmb <= rddata_mux_sel; -- Change axi_rdata_en generated from SM to be a combinatorial signal -- Can't afford the latency when throttling on the AXI bus. axi_rdata_en <= '0'; axi_rvalid_set_cmb <= '0'; end_brst_rd_clr_cmb <= end_brst_rd_clr; no_ar_ack_cmb <= no_ar_ack; pend_rd_op_cmb <= pend_rd_op; act_rd_burst_set <= '0'; act_rd_burst_clr <= '0'; set_last_bram_addr <= '0'; alast_bram_addr <= '0'; axi_b2b_brst_cmb <= axi_b2b_brst; disable_b2b_brst_cmb <= disable_b2b_brst; ar_active_clr <= '0'; case rd_data_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Initiate BRAM read when address is available in controller -- Indicated by load of BRAM address counter -- Remove use of pend_rd_op signal. -- Never asserted as we transition back to IDLE -- Detected in code coverage if (bram_addr_ld_en = '1') then -- At start of new read, clear end burst signal end_brst_rd_clr_cmb <= '0'; -- Initiate BRAM read transfer bram_en_cmb <= '1'; -- Only count addresses & burst length for read -- burst operations -- If currently loading BRAM address counter -- Must check curr_arlen (mux output from pipe or AXI bus) -- to determine length of next operation. -- If ARLEN = 1 data beat, then set last_bram_addr signal -- Otherwise, increment BRAM address counter. if (curr_arlen /= AXI_ARLEN_ONE) then -- Start of new operation, update act_rd_burst and -- act_rd_burst_two signals act_rd_burst_set <= '1'; else -- Set flag for last_bram_addr on transition -- to SNG_ADDR on single operations. set_last_bram_addr <= '1'; end if; -- Go to single active read address state rd_data_sm_ns <= SNG_ADDR; end if; ------------------------- SNG_ADDR State -------------------------- when SNG_ADDR => -- Clear flag once pending read is recognized -- Duplicate logic here in case combinatorial flag was getting -- set as the SM transitioned into this state. if (pend_rd_op = '1') then pend_rd_op_cmb <= '0'; end if; -- At start of new read, clear end burst signal end_brst_rd_clr_cmb <= '0'; -- Reach this state on first BRAM address & enable assertion -- For burst operation, create next BRAM address and keep enable -- asserted -- Note: -- No ability to throttle yet as RVALID has not yet been -- asserted on the AXI bus -- Reset data mux select between skid buffer and BRAM -- Ensure read data mux is set for BRAM data rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM; -- Assert RVALID on AXI when 1st data beat available -- from BRAM axi_rvalid_set_cmb <= '1'; -- Reach this state when BRAM address counter is loaded -- Use axi_rd_burst and axi_rd_burst_two to indicate if -- operation is a single data beat burst. if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then -- Proceed directly to get BRAM read data rd_data_sm_ns <= LAST_ADDR; -- End of active current read address ar_active_clr <= '1'; -- Negate BRAM enable bram_en_cmb <= '0'; -- Load read data skid buffer for BRAM capture -- in next clock cycle rd_skid_buf_ld_cmb <= '1'; -- Assert new flag to disable back-to-back bursts -- due to throttling disable_b2b_brst_cmb <= '1'; -- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM -- address is loaded) and we are waiting for the current read burst to complete. if (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; end if; -- Read burst else -- Increment BRAM address counter (2nd data beat) bram_addr_inc <= '1'; -- Decrement BRAM burst counter (2nd data beat) brst_cnt_dec <= '1'; -- Keep BRAM enable asserted bram_en_cmb <= '1'; rd_data_sm_ns <= SEC_ADDR; -- Load read data skid buffer for BRAM capture -- in next clock cycle rd_skid_buf_ld_cmb <= '1'; -- Start of new operation, update act_rd_burst and -- act_rd_burst_two signals act_rd_burst_set <= '1'; -- If new burst is 2 data beats -- Then disable capability on back-to-back bursts if (axi_rd_burst_two = '1') then -- Assert new flag to disable back-to-back bursts -- due to throttling disable_b2b_brst_cmb <= '1'; else -- Support back-to-back for all other burst lengths disable_b2b_brst_cmb <= '0'; end if; end if; ------------------------- SEC_ADDR State -------------------------- when SEC_ADDR => -- Reach this state when the 2nd incremented address of the burst -- is presented to the BRAM. -- Only reach this state when axi_rd_burst = '1', -- an active read burst. -- Note: -- No ability to throttle yet as RVALID has not yet been -- asserted on the AXI bus -- Enable AXI read data register axi_rdata_en <= '1'; -- Only in dual port mode can the address counter get loaded early if C_SINGLE_PORT_BRAM = 0 then -- If we see the next address get loaded into the BRAM counter -- then set flag for pending operation if (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; end if; end if; -- Check here for burst length of two data transfers -- If so, then the SM will NOT hit the condition of a full -- pipeline: -- Operation A) 1st BRAM address data on AXI bus -- Operation B) 2nd BRAm address data read from BRAM -- Operation C) 3rd BRAM address presented to BRAM -- -- Full pipeline condition is hit for any read burst -- length greater than 2 data beats. if (axi_rd_burst_two = '1') then -- No increment of BRAM address -- or decrement of burst counter -- Burst counter should be = zero rd_data_sm_ns <= LAST_ADDR; -- End of active current read address ar_active_clr <= '1'; -- Ensure read data mux is set for BRAM data rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM; -- Negate BRAM enable bram_en_cmb <= '0'; -- Load read data skid buffer for BRAM capture -- in next clock cycle. -- This signal will negate in the next state -- if the data is not accepted on the AXI bus. -- So that no new data from BRAM is registered into the -- read channel controller. rd_skid_buf_ld_cmb <= '1'; else -- Burst length will hit full pipeline condition -- Increment BRAM address counter (3rd data beat) bram_addr_inc <= '1'; -- Decrement BRAM burst counter (3rd data beat) brst_cnt_dec <= '1'; -- Keep BRAM enable asserted bram_en_cmb <= '1'; rd_data_sm_ns <= FULL_PIPE; -- Assert almost last BRAM address flag -- so that ARVALID logic output can remain registered -- -- Replace usage of brst_cnt with signal, brst_one. if (brst_one = '1') then alast_bram_addr <= '1'; end if; -- Load read data skid buffer for BRAM capture -- in next clock cycle rd_skid_buf_ld_cmb <= '1'; end if; -- ARLEN = "0000 0001" ------------------------- FULL_PIPE State ------------------------- when FULL_PIPE => -- Reach this state when all three data beats in the burst -- are active -- -- Operation A) 1st BRAM address data on AXI bus -- Operation B) 2nd BRAM address data read from BRAM -- Operation C) 3rd BRAM address presented to BRAM -- Ensure read data mux is set for BRAM data rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM; -- With new pipelining capability BRAM address counter may be -- loaded in this state. This only occurs on back-to-back -- bursts (when enabled). -- No flag set for pending operation. -- Modify the if clause here to check for back-to-back burst operations -- If we load the BRAM address in this state for a subsequent burst, then -- this condition indicates a back-to-back burst and no need to assert -- the pending read operation flag. -- Seeing corner case when pend_rd_op needs to be asserted and cleared -- in this state. If the BRAM address counter is loaded early, but -- axi_rlast_set is delayed in getting asserted (all while in this state). -- The signal, curr_narrow_burst can not get cleared. -- Only in dual port mode can the address counter get loaded early if C_SINGLE_PORT_BRAM = 0 then -- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM -- address is loaded) and we are waiting for the current read burst to complete. if (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; -- Clear flag once pending read is recognized and -- earlier read data phase is complete. elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then pend_rd_op_cmb <= '0'; end if; end if; -- Check AXI throttling condition -- If AXI bus advances and accepts read data, SM can -- proceed with next data beat of burst. -- If not, then go to FULL_THROTTLE state to wait for -- AXI_RREADY = '1'. if (rd_adv_buf = '1') then -- Assert AXI read data enable for BRAM capture axi_rdata_en <= '1'; -- Load read data skid buffer for BRAM capture in next clock cycle rd_skid_buf_ld_cmb <= '1'; -- Assert almost last BRAM address flag -- so that ARVALID logic output can remain registered -- -- Replace usage of brst_cnt with signal, brst_one. if (brst_one = '1') then alast_bram_addr <= '1'; end if; -- Check burst counter for max -- If max burst count is reached, no new addresses -- presented to BRAM, advance to last capture data states. -- -- For timing, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (brst_zero = '1') or (end_brst_rd = '1' and axi_b2b_brst = '0') then -- Check for elgible pending read operation to support back-to-back performance. -- If so, load BRAM address counter. -- -- Replace rd_b2b_elgible signal check to remove path from -- arlen_pipe through rd_b2b_elgible -- (with data throttle check) if (rd_b2b_elgible_no_thr_check = '1') then rd_data_sm_ns <= FULL_PIPE; -- Set flag to indicate back-to-back read burst -- RVALID will not clear in this case and remain asserted axi_b2b_brst_cmb <= '1'; -- Set flag to update active read burst or -- read burst of two flag act_rd_burst_set <= '1'; -- Otherwise, complete current transaction else -- No increment of BRAM address -- or decrement of burst counter -- Burst counter should be = zero bram_addr_inc <= '0'; brst_cnt_dec <= '0'; rd_data_sm_ns <= LAST_ADDR; -- Negate BRAM enable bram_en_cmb <= '0'; -- End of active current read address ar_active_clr <= '1'; end if; else -- Remain in this state until burst count reaches zero -- Increment BRAM address counter (Nth data beat) bram_addr_inc <= '1'; -- Decrement BRAM burst counter (Nth data beat) brst_cnt_dec <= '1'; -- Keep BRAM enable asserted bram_en_cmb <= '1'; -- Skid buffer load will remain asserted -- AXI read data register is asserted end if; else -- Throttling condition detected rd_data_sm_ns <= FULL_THROTTLE; -- Ensure that AXI read data output register is disabled -- due to throttle condition. axi_rdata_en <= '0'; -- Skid buffer gets loaded from BRAM read data in next clock -- cycle ONLY. -- Only on transition to THROTTLE state does skid buffer get loaded. -- Negate load of read data skid buffer for BRAM capture -- in next clock cycle due to detection of Throttle condition rd_skid_buf_ld_cmb <= '0'; -- BRAM address is NOT getting incremented -- (same for burst counter) bram_addr_inc <= '0'; brst_cnt_dec <= '0'; -- If transitioning to throttle state -- Then next register enable assertion of the AXI read data -- output register needs to come from the skid buffer -- Set read data mux select here for SKID_BUFFER data rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; -- Detect if at end of burst read as we transition to FULL_THROTTLE -- If so, negate the BRAM enable even if prior to throttle condition -- on AXI bus. Read skid buffer will hold last beat of data in burst. -- -- For timing purposes, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (brst_zero = '1') or (end_brst_rd = '1') then -- No back to back "non bubble" support when AXI master -- is throttling on current burst. -- Seperate signal throttle_last_data will be asserted outside SM. -- End of burst read, negate BRAM enable bram_en_cmb <= '0'; -- Assert new flag to disable back-to-back bursts -- due to throttling disable_b2b_brst_cmb <= '1'; -- Disable B2B capability if throttling detected when -- burst count is equal to one. -- -- For timing purposes, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_one, indicating the -- brst_cnt to be one when decrement. elsif (brst_one = '1') then -- Assert new flag to disable back-to-back bursts -- due to throttling disable_b2b_brst_cmb <= '1'; -- Throttle, but not end of burst else bram_en_cmb <= '1'; end if; end if; -- rd_adv_buf (RREADY throttle) ------------------------- FULL_THROTTLE State --------------------- when FULL_THROTTLE => -- Reach this state when the AXI bus throttles on the AXI data -- beat read from BRAM (when the read pipeline is fully active) -- Flag disable_b2b_brst_cmb should be asserted as we transition -- to this state. Flag is asserted near the end of a read burst -- to prevent the back-to-back performance pipelining in the BRAM -- address counter. -- Detect if at end of burst read -- If so, negate the BRAM enable even if prior to throttle condition -- on AXI bus. Read skid buffer will hold last beat of data in burst. -- -- For timing, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (brst_zero = '1') or (end_brst_rd = '1') then bram_en_cmb <= '0'; end if; -- Set new flag for pending operation if bram_addr_ld_en is asserted (BRAM -- address is loaded) and we are waiting for the current read burst to complete. if (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; -- Clear flag once pending read is recognized and -- earlier read data phase is complete. elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then pend_rd_op_cmb <= '0'; end if; -- Wait for RREADY to be asserted w/ RVALID on AXI bus if (rd_adv_buf = '1') then -- Ensure read data mux is set for skid buffer data rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; -- Ensure that AXI read data output register is enabled axi_rdata_en <= '1'; -- Must reload skid buffer here from BRAM data -- so if needed can be presented to AXI bus on the following clock cycle rd_skid_buf_ld_imm <= '1'; -- When detecting end of throttle condition -- Check first if burst count is complete -- Check burst counter for max -- If max burst count is reached, no new addresses -- presented to BRAM, advance to last capture data states. -- -- For timing, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (brst_zero = '1') or (end_brst_rd = '1') then -- No back-to-back performance when AXI master throttles -- If we reach the end of the burst, proceed to LAST_ADDR state. -- No increment of BRAM address -- or decrement of burst counter -- Burst counter should be = zero bram_addr_inc <= '0'; brst_cnt_dec <= '0'; rd_data_sm_ns <= LAST_ADDR; -- Negate BRAM enable bram_en_cmb <= '0'; -- End of active current read address ar_active_clr <= '1'; -- Not end of current burst w/ throttle condition else -- Go back to FULL_PIPE rd_data_sm_ns <= FULL_PIPE; -- Assert almost last BRAM address flag -- so that ARVALID logic output can remain registered -- -- For timing purposes, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_one, indicating the -- brst_cnt to be one when decrement. if (brst_one = '1') then alast_bram_addr <= '1'; end if; -- Increment BRAM address counter (Nth data beat) bram_addr_inc <= '1'; -- Decrement BRAM burst counter (Nth data beat) brst_cnt_dec <= '1'; -- Keep BRAM enable asserted bram_en_cmb <= '1'; end if; -- Burst Max else -- Stay in this state -- Ensure that AXI read data output register is disabled -- due to throttle condition. axi_rdata_en <= '0'; -- Ensure that skid buffer is not getting loaded with -- current read data from BRAM rd_skid_buf_ld_cmb <= '0'; -- BRAM address is NOT getting incremented -- (same for burst counter) bram_addr_inc <= '0'; brst_cnt_dec <= '0'; end if; -- rd_adv_buf (RREADY throttle) ------------------------- LAST_ADDR State ------------------------- when LAST_ADDR => -- Reach this state in the clock cycle following the last address -- presented to the BRAM. Capture the last BRAM data beat in the -- next clock cycle. -- -- Data is presented to AXI bus (if no throttling detected) and -- loaded into the skid buffer. -- If we reach this state after back to back burst transfers -- then clear the flag to ensure that RVALID will clear when RLAST -- is recognized if (axi_b2b_brst = '1') then axi_b2b_brst_cmb <= '0'; end if; -- Clear flag that indicates end of read burst -- Once we reach this state, we have recognized the burst complete. -- -- It is getting asserted too early -- and recognition of the end of the burst is missed when throttling -- on the last two data beats in the read. end_brst_rd_clr_cmb <= '1'; -- Set new flag for pending operation if ar_active is asserted (BRAM -- address has already been loaded) and we are waiting for the current -- read burst to complete. If those two conditions apply, set this flag. -- For dual port, support checking for early writes into BRAM address counter if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then -- Support back-to-backs for single AND dual port modes. -- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then -- if (ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; end if; -- Load read data skid buffer for BRAM is asserted on transition -- into this state. Only gets negated if done with operation -- as detected in below if clause. -- Check flag for no subsequent operations -- Clear that now, with current operation completing if (no_ar_ack = '1') then no_ar_ack_cmb <= '0'; end if; -- Check for single AXI read operations -- If so, wait for RREADY to be asserted -- Check for burst and bursts of two as seperate signals. if (act_rd_burst = '0') and (act_rd_burst_two = '0') then -- Create rvalid_set to only be asserted for a single clock -- cycle. -- Will get set as transitioning to LAST_ADDR on single read operations -- Only assert RVALID here on single operations -- Enable AXI read data register axi_rdata_en <= '1'; -- Data will not yet be acknowledged on AXI -- in this state. -- Go to wait for last data beat rd_data_sm_ns <= LAST_DATA; -- Set read data mux select for SKID BUF rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; else -- Only check throttling on AXI during read data burst operations -- Check AXI throttling condition -- If AXI bus advances and accepts read data, SM can -- proceed with next data beat. -- If not, then go to LAST_THROTTLE state to wait for -- AXI_RREADY = '1'. if (rd_adv_buf = '1') then -- Assert AXI read data enable for BRAM capture -- in next clock cycle -- Enable AXI read data register axi_rdata_en <= '1'; -- Ensure read data mux is set for BRAM data rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM; -- Burst counter already at zero. Reached this state due to NO -- pending ARADDR in the read address pipeline. However, check -- here for any new read addresses. -- New ARADDR detected and loaded into BRAM address counter -- Add check here for previously loaded BRAM address -- ar_active will be asserted (and qualify that with the -- condition that the read burst is complete, for narrow reads). if (bram_addr_ld_en = '1') then -- Initiate BRAM read transfer bram_en_cmb <= '1'; -- Instead of transitioning to SNG_ADDR -- go to wait for last data beat. rd_data_sm_ns <= LAST_DATA_AR_PEND; else -- No pending read address to initiate next read burst -- Go to capture last data beat from BRAM and present on AXI bus. rd_data_sm_ns <= LAST_DATA; end if; -- bram_addr_ld_en (New read burst) else -- Throttling condition detected rd_data_sm_ns <= LAST_THROTTLE; -- Ensure that AXI read data output register is disabled -- due to throttle condition. axi_rdata_en <= '0'; -- Skid buffer gets loaded from BRAM read data in next clock -- cycle ONLY. -- Only on transition to THROTTLE state does skid buffer get loaded. -- Set read data mux select for SKID BUF rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; end if; -- rd_adv_buf (RREADY throttle) end if; -- AXI read burst ------------------------- LAST_THROTTLE State --------------------- when LAST_THROTTLE => -- Reach this state when the AXI bus throttles on the last data -- beat read from BRAM -- Data to be sourced from read skid buffer -- Add check in LAST_THROTTLE as well as LAST_ADDR -- as we may miss the setting of this flag for a subsequent operation. -- For dual port, support checking for early writes into BRAM address counter if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then -- Support back-to-back for single AND dual port modes. -- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then pend_rd_op_cmb <= '1'; end if; -- Wait for RREADY to be asserted w/ RVALID on AXI bus if (rd_adv_buf = '1') then -- Assert AXI read data enable for BRAM capture axi_rdata_en <= '1'; -- Set read data mux select for SKID BUF rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; -- No pending read address to initiate next read burst -- Go to capture last data beat from BRAM and present on AXI bus. rd_data_sm_ns <= LAST_DATA; -- Load read data skid buffer for BRAM capture in next clock cycle -- of last data read -- Read Skid buffer already loaded with last data beat from BRAM -- Does not need to be asserted again in this state else -- Stay in this state -- Ensure that AXI read data output register is disabled axi_rdata_en <= '0'; -- Ensure that skid buffer is not getting loaded with -- current read data from BRAM rd_skid_buf_ld_cmb <= '0'; -- BRAM address is NOT getting incremented -- (same for burst counter) bram_addr_inc <= '0'; brst_cnt_dec <= '0'; -- Keep RVALID asserted on AXI -- No need to assert RVALID again end if; -- rd_adv_buf (RREADY throttle) ------------------------- LAST_DATA State ------------------------- when LAST_DATA => -- Reach this state when last BRAM data beat is -- presented on AXI bus. -- For a read burst, RLAST is not asserted until SM reaches -- this state. -- Ok to accept new operation if throttling detected -- during current operation (and flag was previously set -- to disable the back-to-back performance). disable_b2b_brst_cmb <= '0'; -- Stay in this state until RREADY is asserted on AXI bus -- Indicated by assertion of rd_adv_buf if (rd_adv_buf = '1') then -- Last data beat acknowledged on AXI bus -- Check for new read burst or proceed back to IDLE -- New ARADDR detected and loaded into BRAM address counter -- Note: this condition may occur when C_SINGLE_PORT_BRAM = 0 or 1 if (bram_addr_ld_en = '1') or (pend_rd_op = '1') then -- Clear flag once pending read is recognized if (pend_rd_op = '1') then pend_rd_op_cmb <= '0'; end if; -- Initiate BRAM read transfer bram_en_cmb <= '1'; -- Only count addresses & burst length for read -- burst operations -- Go to SNG_ADDR state rd_data_sm_ns <= SNG_ADDR; -- If current operation was a burst, clear the active -- burst flag if (act_rd_burst = '1') or (act_rd_burst_two = '1') then act_rd_burst_clr <= '1'; end if; -- If we are loading the BRAM, then we have to view the curr_arlen -- signal to determine if the next operation is a single transfer. -- Or if the BRAM address counter is already loaded (and we reach -- this if clause due to pend_rd_op then the axi_* signals will indicate -- if the next operation is a burst or not. -- If the operation is a single transaction, then set the last_bram_addr -- signal when we reach SNG_ADDR. if (bram_addr_ld_en = '1') then if (curr_arlen = AXI_ARLEN_ONE) then -- Set flag for last_bram_addr on transition -- to SNG_ADDR on single operations. set_last_bram_addr <= '1'; end if; elsif (pend_rd_op = '1') then if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then set_last_bram_addr <= '1'; end if; end if; else -- No pending read address to initiate next read burst. -- Go to IDLE rd_data_sm_ns <= IDLE; -- If current operation was a burst, clear the active -- burst flag if (act_rd_burst = '1') or (act_rd_burst_two = '1') then act_rd_burst_clr <= '1'; end if; end if; else -- Throttling condition detected -- Ensure that AXI read data output register is disabled -- due to throttle condition. axi_rdata_en <= '0'; -- If new ARADDR detected and loaded into BRAM address counter if (bram_addr_ld_en = '1') then -- Initiate BRAM read transfer bram_en_cmb <= '1'; -- Only count addresses & burst length for read -- burst operations -- Instead of transitioning to SNG_ADDR -- to wait for last data beat. rd_data_sm_ns <= LAST_DATA_AR_PEND; -- For singles, block any subsequent loads into BRAM address -- counter from AR SM no_ar_ack_cmb <= '1'; end if; end if; -- rd_adv_buf (RREADY throttle) ------------------------ LAST_DATA_AR_PEND -------------------- when LAST_DATA_AR_PEND => -- Ok to accept new operation if throttling detected -- during current operation (and flag was previously set -- to disable the back-to-back performance). disable_b2b_brst_cmb <= '0'; -- Reach this state when new BRAM address is loaded into -- BRAM address counter -- But waiting for last RREADY/RVALID/RLAST to be asserted -- Once this occurs, continue with pending AR operation if (rd_adv_buf = '1') then -- Go to SNG_ADDR state rd_data_sm_ns <= SNG_ADDR; -- If current operation was a burst, clear the active -- burst flag if (act_rd_burst = '1') or (act_rd_burst_two = '1') then act_rd_burst_clr <= '1'; end if; -- In this state, the BRAM address counter is already loaded, -- the axi_rd_burst and axi_rd_burst_two signals will indicate -- if the next operation is a burst or not. -- If the operation is a single transaction, then set the last_bram_addr -- signal when we reach SNG_ADDR. if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then set_last_bram_addr <= '1'; end if; -- Code coverage tests are reporting that reaching this state -- always when axi_rd_burst = '0' and axi_rd_burst_two = '0', -- so no bursting operations. end if; --coverage off ------------------------------ Default ---------------------------- when others => rd_data_sm_ns <= IDLE; --coverage on end case; end process RD_DATA_SM_CMB_PROCESS; --------------------------------------------------------------------------- RD_DATA_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then rd_data_sm_cs <= IDLE; bram_en_int <= '0'; rd_skid_buf_ld_reg <= '0'; rddata_mux_sel <= C_RDDATA_MUX_BRAM; axi_rvalid_set <= '0'; end_brst_rd_clr <= '0'; no_ar_ack <= '0'; pend_rd_op <= '0'; axi_b2b_brst <= '0'; disable_b2b_brst <= '0'; else rd_data_sm_cs <= rd_data_sm_ns; bram_en_int <= bram_en_cmb; rd_skid_buf_ld_reg <= rd_skid_buf_ld_cmb; rddata_mux_sel <= rddata_mux_sel_cmb; axi_rvalid_set <= axi_rvalid_set_cmb; end_brst_rd_clr <= end_brst_rd_clr_cmb; no_ar_ack <= no_ar_ack_cmb; pend_rd_op <= pend_rd_op_cmb; axi_b2b_brst <= axi_b2b_brst_cmb; disable_b2b_brst <= disable_b2b_brst_cmb; end if; end if; end process RD_DATA_SM_REG_PROCESS; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Create seperate registered process for last_bram_addr signal. -- Only asserted for a single clock cycle -- Gets set when the burst counter is loaded with 0's (for a single data beat operation) -- (indicated by set_last_bram_addr from DATA SM) -- or when the burst counter is decrement and the current value = 1 REG_LAST_BRAM_ADDR: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then last_bram_addr <= '0'; -- The signal, set_last_bram_addr, is asserted when the DATA SM transitions to SNG_ADDR -- on a single data beat burst. Can not use condition of loading burst counter -- with the value of 0's (as the burst counter may be loaded during prior single operation -- when waiting on last throttle/data beat, ie. rd_adv_buf not yet asserted). elsif (set_last_bram_addr = '1') or -- On burst operations at the last BRAM address presented to BRAM (brst_cnt_dec = '1' and brst_cnt = C_BRST_CNT_ONE) then last_bram_addr <= '1'; else last_bram_addr <= '0'; end if; end if; end process REG_LAST_BRAM_ADDR; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- * AXI Read Data Channel Interface * -- --------------------------------------------------------------------------- rd_skid_buf_ld <= rd_skid_buf_ld_reg or rd_skid_buf_ld_imm; --------------------------------------------------------------------------- -- Generate: GEN_RDATA_NO_ECC -- Purpose: Generation of AXI_RDATA output register without ECC -- logic (C_ECC = 0 parameterization in design) --------------------------------------------------------------------------- GEN_RDATA_NO_ECC: if C_ECC = 0 generate signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); begin --------------------------------------------------------------------------- -- AXI RdData Skid Buffer/Register -- Sized according to size of AXI/BRAM data width --------------------------------------------------------------------------- REG_RD_BUF: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then rd_skid_buf <= (others => '0'); -- Add immediate load of read skid buffer -- Occurs in the case when at full throttle and RREADY/RVALID are asserted elsif (rd_skid_buf_ld = '1') then rd_skid_buf <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0); else rd_skid_buf <= rd_skid_buf; end if; end if; end process REG_RD_BUF; -- Rd Data Mux (selects between skid buffer and BRAM read data) -- Select control signal from SM determines register load value axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else rd_skid_buf; --------------------------------------------------------------------------- -- Generate: GEN_RDATA -- Purpose: Generate each bit of AXI_RDATA. --------------------------------------------------------------------------- GEN_RDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate begin REG_RDATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Clear output after last data beat accepted by requesting AXI master if (S_AXI_AResetn = C_RESET_ACTIVE) or -- Don't clear RDDATA when a back to back burst is occuring on RLAST & RVALID assertion -- For improved code coverage, can remove the signal, axi_rvalid_int from this if clause. -- It will always be asserted in this case. (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then axi_rdata_int (i) <= '0'; elsif (axi_rdata_en = '1') then axi_rdata_int (i) <= axi_rdata_mux (i); else axi_rdata_int (i) <= axi_rdata_int (i); end if; end if; end process REG_RDATA; end generate GEN_RDATA; -- If C_ECC = 0, direct output assignment to AXI_RDATA AXI_RDATA <= axi_rdata_int; end generate GEN_RDATA_NO_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_RDATA_ECC -- Purpose: Generation of AXI_RDATA output register when ECC -- logic is enabled (C_ECC = 1 parameterization in design) --------------------------------------------------------------------------- GEN_RDATA_ECC: if C_ECC = 1 generate subtype syndrome_bits is std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- 0:6 for 32-bit ECC -- 0:7 for 64-bit ECC type correct_data_table_type is array (natural range 0 to C_AXI_DATA_WIDTH-1) of syndrome_bits; signal rd_skid_buf_i : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal axi_rdata_int_corr : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); begin -- Remove GEN_RD_BUF that was doing bit reversal. -- Replace with direct register assignments. Sized according to AXI data width. REG_RD_BUF: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then rd_skid_buf_i <= (others => '0'); -- Add immediate load of read skid buffer -- Occurs in the case when at full throttle and RREADY/RVALID are asserted elsif (rd_skid_buf_ld = '1') then rd_skid_buf_i (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1); else rd_skid_buf_i <= rd_skid_buf_i; end if; end if; end process REG_RD_BUF; -- Rd Data Mux (selects between skid buffer and BRAM read data) -- Select control signal from SM determines register load value -- axi_rdata_mux holds data + ECC bits. -- Previous mux on input to checkbit_handler logic. -- Removed now (mux inserted after checkbit_handler logic before register stage) -- -- axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else -- rd_skid_buf_i; -- Remove GEN_RDATA that was doing bit reversal. REG_RDATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then axi_rdata_int <= (others => '0'); elsif (axi_rdata_en = '1') then -- Track uncorrected data vector with AXI RDATA output pipeline -- Mimic mux logic here (from previous post checkbit XOR logic register) if (rddata_mux_sel = C_RDDATA_MUX_BRAM) then axi_rdata_int (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1); else axi_rdata_int <= rd_skid_buf_i; end if; else axi_rdata_int <= axi_rdata_int; end if; end if; end process REG_RDATA; -- When C_ECC = 1, correct any single bit errors on output read data. -- Post register stage to improve timing on ECC logic data path. -- Use registers in AXI Interconnect IP core. -- Perform bit swapping on output of correct_one_bit -- module (axi_rdata_int_corr signal). -- AXI_RDATA (i) <= axi_rdata_int (i) when (Enable_ECC = '0') -- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i); -- Found in HW debug -- axi_rdata_int is reversed to be returned on AXI bus. -- AXI_RDATA (i) <= axi_rdata_int (C_AXI_DATA_WIDTH-1-i) when (Enable_ECC = '0') -- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i); -- Remove bit reversal on AXI_RDATA output. AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HAMMING_ECC_CORR -- -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Generate statements to correct BRAM read data -- dependent on ECC type. ------------------------------------------------------------------------ GEN_HAMMING_ECC_CORR: if C_ECC_TYPE = 0 generate begin ------------------------------------------------------------------------ -- Generate: CHK_ECC_32 -- Purpose: Check ECC data unique for 32-bit BRAM. ------------------------------------------------------------------------ CHK_ECC_32: if C_AXI_DATA_WIDTH = 32 generate constant correct_data_table_32 : correct_data_table_type := ( 0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001", 4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001", 8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101", 12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101", 16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101", 20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101", 24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011", 28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011" ); signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC begin --------------------------------------------------------------------------- -- Register ECC syndrome value to correct any single bit errors -- post-register on AXI read data. REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then syndrome_reg <= (others => '0'); syndrome_4_reg <= (others => '0'); syndrome_6_reg <= (others => '0'); -- Align register stage of syndrome with AXI read data pipeline elsif (axi_rdata_en = '1') then syndrome_reg <= Syndrome; syndrome_4_reg <= Syndrome_4; syndrome_6_reg <= Syndrome_6; else syndrome_reg <= syndrome_reg; syndrome_4_reg <= syndrome_4_reg; syndrome_6_reg <= syndrome_6_reg; end if; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Do last XOR on specific syndrome bits after pipeline stage before -- correct_one_bit module. syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3); PARITY_CHK4: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2) port map ( InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (4) ); -- [out std_logic] syndrome_reg_i (5) <= syndrome_reg (5); PARITY_CHK6: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (6) ); -- [out std_logic] --------------------------------------------------------------------------- -- Generate: GEN_CORR_32 -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_32: for i in 0 to C_AXI_DATA_WIDTH-1 generate begin ----------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_32 -- Description: Correct output read data based on syndrome vector. -- A single error can be corrected by decoding the -- syndrome value. -- Input signal is declared (N:0). -- Output signal is (N:0). -- In order to reuse correct_one_bit module, -- the single data bit correction is done LSB to MSB -- in generate statement loop. ----------------------------------------------------------------------- CORR_ONE_BIT_32: entity work.correct_one_bit generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table_32 (i)) port map ( DIn => axi_rdata_int (31-i), -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal) Syndrome => syndrome_reg_i, DCorr => axi_rdata_int_corr (31-i)); -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal) end generate GEN_CORR_32; end generate CHK_ECC_32; ------------------------------------------------------------------------ -- Generate: CHK_ECC_64 -- Purpose: Check ECC data unique for 64-bit BRAM. ------------------------------------------------------------------------ CHK_ECC_64: if C_AXI_DATA_WIDTH = 64 generate constant correct_data_table_64 : correct_data_table_type := ( 0 => "11000001", 1 => "10100001", 2 => "01100001", 3 => "11100001", 4 => "10010001", 5 => "01010001", 6 => "11010001", 7 => "00110001", 8 => "10110001", 9 => "01110001", 10 => "11110001", 11 => "10001001", 12 => "01001001", 13 => "11001001", 14 => "00101001", 15 => "10101001", 16 => "01101001", 17 => "11101001", 18 => "00011001", 19 => "10011001", 20 => "01011001", 21 => "11011001", 22 => "00111001", 23 => "10111001", 24 => "01111001", 25 => "11111001", 26 => "10000101", 27 => "01000101", 28 => "11000101", 29 => "00100101", 30 => "10100101", 31 => "01100101", 32 => "11100101", 33 => "00010101", 34 => "10010101", 35 => "01010101", 36 => "11010101", 37 => "00110101", 38 => "10110101", 39 => "01110101", 40 => "11110101", 41 => "00001101", 42 => "10001101", 43 => "01001101", 44 => "11001101", 45 => "00101101", 46 => "10101101", 47 => "01101101", 48 => "11101101", 49 => "00011101", 50 => "10011101", 51 => "01011101", 52 => "11011101", 53 => "00111101", 54 => "10111101", 55 => "01111101", 56 => "11111101", 57 => "10000011", 58 => "01000011", 59 => "11000011", 60 => "00100011", 61 => "10100011", 62 => "01100011", 63 => "11100011" ); signal syndrome_7_reg : std_logic_vector (0 to 11) := (others => '0'); -- Specific for 64-bit ECC signal syndrome_7_a : std_logic; signal syndrome_7_b : std_logic; begin --------------------------------------------------------------------------- -- Register ECC syndrome value to correct any single bit errors -- post-register on AXI read data. REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Align register stage of syndrome with AXI read data pipeline if (axi_rdata_en = '1') then syndrome_reg <= Syndrome; syndrome_7_reg <= Syndrome_7; else syndrome_reg <= syndrome_reg; syndrome_7_reg <= syndrome_7_reg; end if; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Do last XOR on select syndrome bits after pipeline stage -- before correct_one_bit_64 module. PARITY_CHK7_A: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_7_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_7_a ); -- [out std_logic] PARITY_CHK7_B: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_7_reg (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_7_b ); -- [out std_logic] -- Do last XOR on Syndrome MSB after pipeline stage before correct_one_bit module -- PASSES: syndrome_reg_i (7) <= syndrome_reg (7) xor syndrome_7_b_reg; syndrome_reg_i (7) <= syndrome_7_a xor syndrome_7_b; syndrome_reg_i (0 to 6) <= syndrome_reg (0 to 6); --------------------------------------------------------------------------- -- Generate: GEN_CORR_64 -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_64: for i in 0 to C_AXI_DATA_WIDTH-1 generate begin ----------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_64 -- Description: Correct output read data based on syndrome vector. -- A single error can be corrected by decoding the -- syndrome value. ----------------------------------------------------------------------- CORR_ONE_BIT_64: entity work.correct_one_bit_64 generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table_64 (i)) port map ( DIn => axi_rdata_int (i), Syndrome => syndrome_reg_i, DCorr => axi_rdata_int_corr (i)); end generate GEN_CORR_64; end generate CHK_ECC_64; end generate GEN_HAMMING_ECC_CORR; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HSIAO_ECC_CORR -- -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Derived from MIG v3.7 Hsiao HDL. -- Generate statements to correct BRAM read data -- dependent on ECC type. ------------------------------------------------------------------------ GEN_HSIAO_ECC_CORR: if C_ECC_TYPE = 1 generate type type_int0 is array (C_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0); signal h_matrix : type_int0; signal flip_bits : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0); signal ecc_rddata_r : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0); begin -- Reconstruct H-matrix H_COL: for n in 0 to C_AXI_DATA_WIDTH - 1 generate begin H_BIT: for p in 0 to ECC_WIDTH - 1 generate begin h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n); end generate H_BIT; end generate H_COL; -- Based on syndrome value, determine bits to flip in BRAM read data. GEN_FLIP_BIT: for r in 0 to C_AXI_DATA_WIDTH - 1 generate begin flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r); end generate GEN_FLIP_BIT; ecc_rddata_r <= axi_rdata_int; axi_rdata_int_corr (C_AXI_DATA_WIDTH-1 downto 0) <= -- UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) xor ecc_rddata_r (C_AXI_DATA_WIDTH-1 downto 0) xor flip_bits (C_AXI_DATA_WIDTH-1 downto 0); end generate GEN_HSIAO_ECC_CORR; end generate GEN_RDATA_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_RID_SNG -- Purpose: Generate RID output pipeline when the core is configured -- in a single port mode. --------------------------------------------------------------------------- GEN_RID_SNG: if (C_SINGLE_PORT_BRAM = 1) generate begin REG_RID_TEMP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rid_temp <= (others => '0'); elsif (bram_addr_ld_en = '1') then axi_rid_temp <= AXI_ARID; else axi_rid_temp <= axi_rid_temp; end if; end if; end process REG_RID_TEMP; REG_RID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then axi_rid_int <= (others => '0'); elsif (bram_addr_ld_en = '1') then axi_rid_int <= AXI_ARID; elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then axi_rid_int <= axi_rid_temp; else axi_rid_int <= axi_rid_int; end if; end if; end process REG_RID; -- Advance RID pipeline values axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '1') else '0'; end generate GEN_RID_SNG; --------------------------------------------------------------------------- -- Generate: GEN_RID -- Purpose: Generate RID in dual port mode (with read address pipeline). --------------------------------------------------------------------------- GEN_RID: if (C_SINGLE_PORT_BRAM = 0) generate begin --------------------------------------------------------------------------- -- RID Output Register -- -- Output RID value either comes from pipelined value or directly wrapped -- ARID value. Determined by address pipeline usage. --------------------------------------------------------------------------- -- Create intermediate temporary RID output register REG_RID_TEMP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rid_temp <= (others => '0'); -- When BRAM address counter gets loaded -- Set output RID value based on address source elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '0') then -- If BRAM address counter gets loaded directly from -- AXI bus, then save ARID value for wrapping to RID if (araddr_pipe_sel = '0') then axi_rid_temp <= AXI_ARID; else -- Use pipelined AWID value axi_rid_temp <= axi_arid_pipe; end if; -- Add condition to check for temp utilized (temp_full now = '0'), but a -- pending RID is stored in temp2. Must advance the pipeline. elsif ((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or (axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then axi_rid_temp <= axi_rid_temp2; else axi_rid_temp <= axi_rid_temp; end if; end if; end process REG_RID_TEMP; -- Create flag that indicates if axi_rid_temp is full REG_RID_TEMP_FULL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rid_temp_full = '1' and (axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and axi_rid_temp2_full = '0') then axi_rid_temp_full <= '0'; elsif (bram_addr_ld_en = '1') or ((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or (axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then axi_rid_temp_full <= '1'; else axi_rid_temp_full <= axi_rid_temp_full; end if; end if; end process REG_RID_TEMP_FULL; -- Create flag to detect falling edge of axi_rid_temp_full flag REG_RID_TEMP_FULL_D1: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rid_temp_full_d1 <= '0'; else axi_rid_temp_full_d1 <= axi_rid_temp_full; end if; end if; end process REG_RID_TEMP_FULL_D1; axi_rid_temp_full_fe <= '1' when (axi_rid_temp_full = '0' and axi_rid_temp_full_d1 = '1') else '0'; --------------------------------------------------------------------------- -- Create intermediate temporary RID output register REG_RID_TEMP2: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rid_temp2 <= (others => '0'); -- When BRAM address counter gets loaded -- Set output RID value based on address source elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then -- If BRAM address counter gets loaded directly from -- AXI bus, then save ARID value for wrapping to RID if (araddr_pipe_sel = '0') then axi_rid_temp2 <= AXI_ARID; else -- Use pipelined AWID value axi_rid_temp2 <= axi_arid_pipe; end if; else axi_rid_temp2 <= axi_rid_temp2; end if; end if; end process REG_RID_TEMP2; -- Create flag that indicates if axi_rid_temp2 is full REG_RID_TEMP2_FULL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rid_temp2_full = '1' and (axi_rvalid_set = '1' or axi_b2b_rid_adv = '1')) or (axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then axi_rid_temp2_full <= '0'; elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then axi_rid_temp2_full <= '1'; else axi_rid_temp2_full <= axi_rid_temp2_full; end if; end if; end process REG_RID_TEMP2_FULL; --------------------------------------------------------------------------- -- Output RID register is enabeld when RVALID is asserted on the AXI bus -- Clear RID when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. REG_RID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- For improved code coverage, can remove the signal, axi_rvalid_int from statement. (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then axi_rid_int <= (others => '0'); -- Add back to back case to advance RID elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then axi_rid_int <= axi_rid_temp; else axi_rid_int <= axi_rid_int; end if; end if; end process REG_RID; -- Advance RID pipeline values axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '1') else '0'; end generate GEN_RID; --------------------------------------------------------------------------- -- Generate: GEN_RRESP -- Purpose: Create register output unique when ECC is disabled. -- Only possible output value = OKAY response. --------------------------------------------------------------------------- GEN_RRESP: if C_ECC = 0 generate begin ----------------------------------------------------------------------- -- AXI_RRESP Output Register -- -- Set when RVALID is asserted on AXI bus. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking -- sequence and recognized by AXI requesting master. ----------------------------------------------------------------------- REG_RRESP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted. (axi_rlast_int = '1' and AXI_RREADY = '1') then axi_rresp_int <= (others => '0'); elsif (axi_rvalid_set = '1') then -- AXI BRAM only supports OK response for normal operations -- Exclusive operations not yet supported axi_rresp_int <= RESP_OKAY; else axi_rresp_int <= axi_rresp_int; end if; end if; end process REG_RRESP; end generate GEN_RRESP; --------------------------------------------------------------------------- -- Generate: GEN_RRESP_ECC -- Purpose: Create register output unique when ECC is disabled. -- Only possible output value = OKAY response. --------------------------------------------------------------------------- GEN_RRESP_ECC: if C_ECC = 1 generate begin ----------------------------------------------------------------------- -- AXI_RRESP Output Register -- -- Set when RVALID is asserted on AXI bus. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking -- sequence and recognized by AXI requesting master. ----------------------------------------------------------------------- REG_RRESP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted. (axi_rlast_int = '1' and AXI_RREADY = '1') then axi_rresp_int <= (others => '0'); elsif (axi_rvalid_set = '1') then -- AXI BRAM only supports OK response for normal operations -- Exclusive operations not yet supported -- For ECC implementation -- Check that an uncorrectable error has not occured. -- If so, then respond with RESP_SLVERR on AXI. -- Ok to use combinatorial signal here. The Sl_UE_i -- flag is generated based on the registered syndrome value. -- if (Sl_UE_i = '1') then -- axi_rresp_int <= RESP_SLVERR; -- else axi_rresp_int <= RESP_OKAY; -- end if; else axi_rresp_int <= axi_rresp_int; end if; end if; end process REG_RRESP; end generate GEN_RRESP_ECC; --------------------------------------------------------------------------- -- AXI_RVALID Output Register -- -- Set AXI_RVALID when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- Clear AXI_RVALID at the end of tranfer when able to clear -- (axi_rlast_int = '1' and axi_rvalid_int = '1' and AXI_RREADY = '1' and -- For improved code coverage, remove signal axi_rvalid_int. (axi_rlast_int = '1' and AXI_RREADY = '1' and -- Added axi_rvalid_clr_ok to check if during a back-to-back burst -- and the back-to-back is elgible for streaming performance axi_rvalid_clr_ok = '1') then axi_rvalid_int <= '0'; elsif (axi_rvalid_set = '1') then axi_rvalid_int <= '1'; else axi_rvalid_int <= axi_rvalid_int; end if; end if; end process REG_RVALID; -- Create flag that gets set when we load BRAM address early in a B2B scenario -- This will prevent the RVALID from getting cleared at the end of the current burst -- Otherwise, the RVALID gets cleared after RLAST/RREADY dual assertion REG_RVALID_CLR: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rvalid_clr_ok <= '0'; -- When the new address loaded into the BRAM counter is for a back-to-back operation -- Do not clear the RVALID elsif (rd_b2b_elgible = '1' and bram_addr_ld_en = '1') then axi_rvalid_clr_ok <= '0'; -- Else when we start a new transaction (that is not back-to-back) -- Then enable the RVALID to get cleared upon RLAST/RREADY elsif (bram_addr_ld_en = '1') or (axi_rvalid_clr_ok = '0' and (disable_b2b_brst = '1' or disable_b2b_brst_cmb = '1') and last_bram_addr = '1') or -- Add check for current SM state -- If LAST_ADDR state reached, no longer performing back-to-back -- transfers and keeping data streaming on AXI bus. (rd_data_sm_cs = LAST_ADDR) then axi_rvalid_clr_ok <= '1'; else axi_rvalid_clr_ok <= axi_rvalid_clr_ok; end if; end if; end process REG_RVALID_CLR; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- AXI_RLAST Output Register -- -- Set AXI_RLAST when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RLAST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- To improve code coverage, remove -- use of axi_rvalid_int (it will always be asserted with RLAST). if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_rlast_set = '0') then axi_rlast_int <= '0'; elsif (axi_rlast_set = '1') then axi_rlast_int <= '1'; else axi_rlast_int <= axi_rlast_int; end if; end if; end process REG_RLAST; --------------------------------------------------------------------------- -- Generate complete flag do_cmplt_burst_cmb <= '1' when (last_bram_addr = '1' and axi_rd_burst = '1' and axi_rd_burst_two = '0') else '0'; -- Register complete flags REG_CMPLT_BURST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (do_cmplt_burst_clr = '1') then do_cmplt_burst <= '0'; elsif (do_cmplt_burst_cmb = '1') then do_cmplt_burst <= '1'; else do_cmplt_burst <= do_cmplt_burst; end if; end if; end process REG_CMPLT_BURST; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- RLAST State Machine -- -- Description: SM to generate axi_rlast_set signal. -- Created based on IR # 555346 to track when RLAST needs -- to be asserted for back to back transfers -- Uses the indication when last BRAM address is presented -- and then counts the handshaking cycles on the AXI bus -- (RVALID and RREADY both asserted). -- Uses rd_adv_buf to perform this operation. -- -- Output: Name Type -- axi_rlast_set Not Registered -- do_cmplt_burst_clr Not Registered -- -- -- RLAST_SM_CMB_PROCESS: Combinational process to determine next state. -- RLAST_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- RLAST_SM_CMB_PROCESS: process ( do_cmplt_burst, last_bram_addr, rd_adv_buf, act_rd_burst, axi_rd_burst, act_rd_burst_two, axi_rd_burst_two, axi_rlast_int, rlast_sm_cs ) begin -- assign default values for state machine outputs rlast_sm_ns <= rlast_sm_cs; axi_rlast_set <= '0'; do_cmplt_burst_clr <= '0'; case rlast_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- If last read address is presented to BRAM if (last_bram_addr = '1') then -- If the operation is a single read operation if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then -- Go to wait for last data beat rlast_sm_ns <= W8_LAST_DATA; -- Else the transaction is a burst else -- Throttle condition on 3rd to last data beat if (rd_adv_buf = '0') then -- If AXI read burst = 2 (only two data beats to capture) if (axi_rd_burst_two = '1' or act_rd_burst_two = '1') then rlast_sm_ns <= W8_THROTTLE_B2; else rlast_sm_ns <= W8_THROTTLE; end if; -- No throttle on 3rd to last data beat else -- Only back-to-back support when burst size is greater -- than two data beats. We will never toggle on a burst > 2 -- when last_bram_addr is asserted (as this is no toggle -- condition) -- Go to wait for 2nd to last data beat rlast_sm_ns <= W8_2ND_LAST_DATA; do_cmplt_burst_clr <= '1'; end if; end if; end if; ------------------------- W8_THROTTLE State ----------------------- when W8_THROTTLE => if (rd_adv_buf = '1') then -- Go to wait for 2nd to last data beat rlast_sm_ns <= W8_2ND_LAST_DATA; -- If do_cmplt_burst flag is set, then clear it if (do_cmplt_burst = '1') then do_cmplt_burst_clr <= '1'; end if; end if; ---------------------- W8_2ND_LAST_DATA State --------------------- when W8_2ND_LAST_DATA => if (rd_adv_buf = '1') then -- Assert RLAST on AXI axi_rlast_set <= '1'; rlast_sm_ns <= W8_LAST_DATA; end if; ------------------------- W8_LAST_DATA State ---------------------- when W8_LAST_DATA => -- If pending single to complete, keep RLAST asserted -- Added to only assert axi_rlast_set for a single clock cycle -- when we enter this state and are here waiting for the -- throttle on the AXI bus. if (axi_rlast_int = '1') then axi_rlast_set <= '0'; else axi_rlast_set <= '1'; end if; -- Wait for last data beat to transition back to IDLE if (rd_adv_buf = '1') then rlast_sm_ns <= IDLE; end if; -------------------------- W8_THROTTLE_B2 ------------------------ when W8_THROTTLE_B2 => -- Wait for last data beat to transition back to IDLE -- and set RLAST if (rd_adv_buf = '1') then rlast_sm_ns <= IDLE; axi_rlast_set <= '1'; end if; --coverage off ------------------------------ Default ---------------------------- when others => rlast_sm_ns <= IDLE; --coverage on end case; end process RLAST_SM_CMB_PROCESS; --------------------------------------------------------------------------- RLAST_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then rlast_sm_cs <= IDLE; else rlast_sm_cs <= rlast_sm_ns; end if; end if; end process RLAST_SM_REG_PROCESS; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- * ECC Logic * --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_ECC -- Purpose: Generate BRAM ECC write data and check ECC on read operations. -- Create signals to update ECC registers (lite_ecc_reg module interface). -- --------------------------------------------------------------------------- GEN_ECC: if C_ECC = 1 generate signal bram_din_a_i : std_logic_vector(0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width signal CE_Q : std_logic := '0'; signal Sl_CE_i : std_logic := '0'; signal bram_en_int_d1 : std_logic := '0'; signal bram_en_int_d2 : std_logic := '0'; begin -- Generate signal to advance BRAM read address pipeline to -- capture address for ECC error conditions (in lite_ecc_reg module). -- BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or -- ((bram_en_int or bram_en_int_reg) and not (axi_rd_burst) and not (axi_rd_burst_two)); BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or rd_adv_buf or ((bram_en_int or bram_en_int_d1 or bram_en_int_d2) and not (axi_rd_burst) and not (axi_rd_burst_two)); -- Enable 2nd & 3rd pipeline stage for BRAM address storage with single read transfers. BRAM_EN_REG: process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then bram_en_int_d1 <= bram_en_int; bram_en_int_d2 <= bram_en_int_d1; end if; end process BRAM_EN_REG; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HAMMING_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. ------------------------------------------------------------------------ GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate begin ------------------------------------------------------------------------ -- Generate: GEN_ECC_32 -- Purpose: Check ECC data unique for 32-bit BRAM. -- Add extra '0' at MSB of ECC vector for data2mem alignment -- w/ 32-bit BRAM data widths. -- ECC bits are in upper order bits. ------------------------------------------------------------------------ GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate signal bram_din_a_rev : std_logic_vector(31 downto 0) := (others => '0'); -- Specific to BRAM data width signal bram_din_ecc_a_rev : std_logic_vector(6 downto 0) := (others => '0'); -- Specific to BRAM data width begin --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_32 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) --------------------------------------------------------------------------- -- process (bram_din_a_i) begin -- for k in 0 to 31 loop -- bram_din_a_rev(k) <= bram_din_a_i(39-k); -- end loop; -- for k in 0 to 6 loop -- bram_din_ecc_a_rev(0) <= bram_din_a_i(6-k); -- end loop; -- end process; CHK_HANDLER_32: entity work.checkbit_handler generic map ( C_ENCODE => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( -- In 32-bit BRAM use case: DataIn (8:39) -- CheckIn (1:7) DataIn => bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH), -- [in std_logic_vector(0 to 31)] CheckIn => bram_din_a_i(1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(0 to 6)] --DataIn => bram_din_a_rev, -- [in std_logic_vector(0 to 31)] --CheckIn => bram_din_ecc_a_rev, -- [in std_logic_vector(0 to 6)] CheckOut => open, -- [out std_logic_vector(0 to 6)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)] Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)] Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)] Syndrome_Chk => syndrome_reg_i, -- [out std_logic_vector(0 to 6)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] -- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate -- of AXI RDATA output register logic. end generate GEN_ECC_32; ------------------------------------------------------------------------ -- Generate: GEN_ECC_64 -- Purpose: Check ECC data unique for 64-bit BRAM. -- No extra '0' at MSB of ECC vector for data2mem alignment -- w/ 64-bit BRAM data widths. -- ECC bits are in upper order bits. ------------------------------------------------------------------------ GEN_ECC_64: if C_AXI_DATA_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_64 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) --------------------------------------------------------------------------- CHK_HANDLER_64: entity work.checkbit_handler_64 generic map ( C_ENCODE => false, -- [boolean] C_REG => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( Clk => S_AXI_AClk, -- [in std_logic] -- In 64-bit BRAM use case: DataIn (8:71) -- CheckIn (0:7) DataIn => bram_din_a_i (C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1), -- [in std_logic_vector(0 to 63)] CheckIn => bram_din_a_i (0 to C_INT_ECC_WIDTH-1), -- [in std_logic_vector(0 to 7)] CheckOut => open, -- [out std_logic_vector(0 to 7)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 7)] Syndrome_7 => Syndrome_7, Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 7)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] -- GEN_CORR_64 generate & correct_one_bit instantiation moved to generate -- of AXI RDATA output register logic. end generate GEN_ECC_64; end generate GEN_HAMMING_ECC; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HSIAO_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Derived from MIG v3.7 Hsiao HDL. ------------------------------------------------------------------------ GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; signal syndrome_ns : std_logic_vector (ECC_WIDTH - 1 downto 0) := (others => '0'); begin -- Generate ECC check bits and syndrome values based on -- BRAM read data. -- Generate appropriate single or double bit error flags. -- Instantiate ecc_gen_hsiao module, generated from MIG I_ECC_GEN_HSIAO: entity work.ecc_gen generic map ( code_width => CODE_WIDTH, ecc_width => ECC_WIDTH, data_width => C_AXI_DATA_WIDTH ) port map ( -- Output h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0) ); GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate begin syndrome_ns (m) <= REDUCTION_XOR ( -- bram_din_a_i (0 to CODE_WIDTH-1) BRAM_RdData (CODE_WIDTH-1 downto 0) and h_rows ((mCODE_WIDTH)+CODE_WIDTH-1 downto (mCODE_WIDTH))); end generate GEN_RD_ECC; -- Insert register stage for syndrome. -- Same as Hamming ECC code. Syndrome value is registered. REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_r <= syndrome_ns; end if; end process REG_SYNDROME; Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not(REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); end generate GEN_HSIAO_ECC; -- Capture correctable/uncorrectable error from BRAM read CORR_REG: process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (Enable_ECC = '1') and (axi_rvalid_int = '1' and AXI_RREADY = '1') then -- Capture error flags CE_Q <= Sl_CE_i; UE_Q <= Sl_UE_i; else CE_Q <= '0'; UE_Q <= '0'; end if; end if; end process CORR_REG; -- The signal, axi_rdata_en loads the syndrome_reg. -- Use the AXI RVALID/READY signals to capture state of UE and CE. -- Since flag generation uses the registered syndrome value. -- ECC register block gets registered UE or CE conditions to update -- ECC registers/interrupt/flag outputs. Sl_CE <= CE_Q; Sl_UE <= UE_Q; -- CE_Failing_We <= Sl_CE_i and Enable_ECC and axi_rvalid_set; CE_Failing_We <= CE_Q; --------------------------------------------------------------------------- -- Generate BRAM read data vector assignment to always be from Port A -- in a single port BRAM configuration. -- Map BRAM_RdData (Port A) (N:0) to bram_din_a_i (0:N) -- Including read back ECC bits. -- -- Port A or Port B sourcing done at full_axi module level --------------------------------------------------------------------------- -- Original design with mux (BRAM vs. Skid Buffer) on input side of checkbit_handler logic. -- Move mux to enable on AXI RDATA register. bram_din_a_i (0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- Map data vector from BRAM to use in correct_one_bit module with -- register syndrome (post AXI RDATA register). UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_AXI_DATA_WIDTH-1); end generate GEN_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Drive default output signals when ECC is diabled. --------------------------------------------------------------------------- GEN_NO_ECC: if C_ECC = 0 generate begin BRAM_Addr_En <= '0'; CE_Failing_We <= '0'; Sl_CE <= '0'; Sl_UE <= '0'; end generate GEN_NO_ECC; --------------------------------------------------------------------------- -- -- * BRAM Interface Signals * -- --------------------------------------------------------------------------- BRAM_En <= bram_en_int; --------------------------------------------------------------------------- -- BRAM Address Generate --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_L_BRAM_ADDR -- Purpose: Generate zeros on lower order address bits adjustable -- based on BRAM data width. -- --------------------------------------------------------------------------- GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin BRAM_Addr (i) <= '0'; end generate GEN_L_BRAM_ADDR; --------------------------------------------------------------------------- -- -- Generate: GEN_BRAM_ADDR -- Purpose: Assign BRAM address output from address counter. -- --------------------------------------------------------------------------- GEN_BRAM_ADDR: for i in C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin BRAM_Addr (i) <= bram_addr_int (i); end generate GEN_BRAM_ADDR; --------------------------------------------------------------------------- end architecture implementation;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/zpu/vhdl_source/zpu_8bit_ok.vhd	5	28212	------------------------------------------------------------------------------ ---- ---- ---- ZPU 8-bit version ---- ---- ---- ---- http://www.opencores.org/ ---- ---- ---- ---- Description: ---- ---- ZPU is a 32 bits small stack cpu. This is a modified version of ---- ---- the zpu_small implementation. This one has a third (8-bit) port for ---- ---- fetching instructions. This modification reduces the LUT size by ---- ---- approximately 10% and increases the performance with 21%. ---- ---- Needs external dual ported memory, plus single cycle external ---- ---- program memory. It also requires a different linker script to ---- ---- place the text segment on a logically different address to stick to ---- ---- the single-, flat memory model programming paradigm. ---- ---- ---- ---- To Do: ---- ---- Add a 'ready' for the external code memory ---- ---- More thorough testing, cleanup code a bit more ---- ---- ---- ---- Author: ---- ---- - Øyvind Harboe, oyvind.harboe zylin.com ---- ---- - Salvador E. Tropea, salvador inti.gob.ar ---- ---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ---- ---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- ---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- ---- ---- ---- Distributed under the BSD license ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Design unit: zpu_8bit(Behave) (Entity and architecture) ---- ---- File name: zpu_8bit.vhdl ---- ---- Note: None ---- ---- Limitations: None known ---- ---- Errors: None known ---- ---- Library: work ---- ---- Dependencies: ieee.std_logic_1164 ---- ---- ieee.numeric_std ---- ---- work.zpupkg ---- ---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ---- ---- Language: VHDL ---- ---- Wishbone: No ---- ---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ---- ---- Simulation tools: Modelsim ---- ---- Text editor: UltraEdit 11.00a+ ---- ---- ---- ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.zpupkg.all; entity zpu_8bit is generic( g_addr_size : integer := 16; -- Total address space width (incl. I/O) g_stack_size : integer := 12; -- Memory (stack+data) width g_prog_size : integer := 14; -- Program size g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0' port( clk_i : in std_logic; -- System Clock reset_i : in std_logic; -- Synchronous Reset interrupt_i : in std_logic; -- Interrupt break_o : out std_logic; -- Breakpoint opcode executed -- synthesis translate_off dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) -- synthesis translate_on -- BRAM (stack ONLY) a_en_o : out std_logic; a_we_o : out std_logic; -- BRAM A port Write Enable a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port a_i : in unsigned(31 downto 0); -- Data from BRAM A port b_en_o : out std_logic; b_we_o : out std_logic; -- BRAM B port Write Enable b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port b_i : in unsigned(31 downto 0); -- Data from BRAM B port -- memory port for text, bss, data c_i : in unsigned(c_opcode_width-1 downto 0); c_valid_i : in std_logic; c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0'); c_o : out unsigned(c_opcode_width-1 downto 0); c_en_o : out std_logic; c_we_o : out std_logic ); end entity zpu_8bit; architecture Behave of zpu_8bit is constant c_max_addr_bit : integer:=g_addr_size-1; -- Stack Pointer initial value: BRAM size-8 constant SP_START_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2*g_stack_size)-8, g_addr_size); constant SP_START : unsigned(g_stack_size-1 downto 2):= SP_START_1(g_stack_size-1 downto 2); -- constant IO_BIT : integer:=g_addr_size-1; -- Address bit to determine this is an I/O -- Program counter signal pc_r : unsigned(c_max_addr_bit downto 0):=(others => '0'); -- Stack pointer signal sp_r : unsigned(g_stack_size-1 downto 2):=SP_START; signal idim_r : std_logic:='0'; -- BRAM (text, some data, bss and stack) -- a_r is a register for the top of the stack [SP] -- Note: as this is a stack CPU this is a very important register. signal a_we_r : std_logic:='0'; signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0'); signal a_r : unsigned(31 downto 0):=(others => '0'); -- b_r is a register for the next value in the stack [SP+1] signal b_we_r : std_logic:='0'; signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0'); signal b_r : unsigned(31 downto 0):=(others => '0'); signal c_we_r : std_logic := '0'; signal c_en_r : std_logic := '0'; signal c_mux_r : std_logic := '0'; signal c_mux_d : std_logic := '0'; signal first : std_logic := '0'; signal byte_cnt : unsigned(1 downto 0) := "00"; signal byte_cnt_d : unsigned(1 downto 0) := "00"; signal posted_wr_a : std_logic := '0'; -- State machine. type state_t is (st_fetch, st_execute, st_add, st_or, st_and, st_store, st_read_mem, st_write_mem, st_add_sp, st_decode, st_resync); signal state : state_t:=st_resync; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "one-hot"; -- Decoded Opcode type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp, dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add, dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store, dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb); signal dec_valid : std_logic; signal d_opcode_r : decode_t; signal d_opcode : decode_t; signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered -- IRQ flag signal in_irq_r : std_logic:='0'; -- I/O space address signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0'); begin a_en_o <= '1'; b_en_o <= '1'; c_en_o <= '1' when state = st_fetch else c_en_r; -- Dual ported memory interface a_we_o <= a_we_r; a_addr_o <= a_addr_r(g_stack_size-1 downto 2); a_o <= a_r; b_we_o <= b_we_r; b_addr_o <= b_addr_r(g_stack_size-1 downto 2); b_o <= b_r; opcode <= c_i; c_addr_o <= resize(pc_r(g_prog_size-1 downto 0), g_addr_size) when c_mux_r = '0' else addr_r; c_we_o <= c_we_r; ------------------------- -- Instruction Decoder -- ------------------------- -- Note: We use a separate memory port to fetch opcodes. decode_control: process(opcode) begin if (opcode(7 downto 7)=OPCODE_IM) then d_opcode <= dec_im; elsif (opcode(7 downto 5)=OPCODE_STORESP) then d_opcode <= dec_store_sp; elsif (opcode(7 downto 5)=OPCODE_LOADSP) then d_opcode <= dec_load_sp; elsif (opcode(7 downto 5)=OPCODE_EMULATE) then -- if opcode(5 downto 0) = OPCODE_LOADB then -- d_opcode <= dec_loadb; -- elsif opcode(5 downto 0) = OPCODE_STOREB then -- d_opcode <= dec_storeb; -- else d_opcode <= dec_emulate; -- end if; elsif (opcode(7 downto 4)=OPCODE_ADDSP) then d_opcode <= dec_add_sp; else -- OPCODE_SHORT case opcode(3 downto 0) is when OPCODE_BREAK => d_opcode <= dec_break; when OPCODE_PUSHSP => d_opcode <= dec_push_sp; when OPCODE_POPPC => d_opcode <= dec_pop_pc; when OPCODE_ADD => d_opcode <= dec_add; when OPCODE_OR => d_opcode <= dec_or; when OPCODE_AND => d_opcode <= dec_and; when OPCODE_LOAD => d_opcode <= dec_load; when OPCODE_NOT => d_opcode <= dec_not; when OPCODE_FLIP => d_opcode <= dec_flip; when OPCODE_STORE => d_opcode <= dec_store; when OPCODE_POPSP => d_opcode <= dec_pop_sp; when others => -- OPCODE_NOP and others d_opcode <= dec_nop; end case; end if; end process decode_control; opcode_control: process (clk_i) variable sp_offset : unsigned(4 downto 0); begin if rising_edge(clk_i) then break_o <= '0'; -- synthesis translate_off dbg_o.b_inst <= '0'; -- synthesis translate_on posted_wr_a <= '0'; c_we_r <= '0'; byte_cnt_d <= byte_cnt; c_mux_d <= c_mux_r; d_opcode_r <= d_opcode; dec_valid <= not c_mux_d and c_valid_i; opcode_r <= opcode; a_we_r <= '0'; b_we_r <= '0'; -- a_r <= (others => g_dont_care); b_r <= (others => g_dont_care); sp_offset:=(others => g_dont_care); a_addr_r <= (others => g_dont_care); -- b_addr_r <= (others => g_dont_care); -- addr_r <= a_i(g_addr_size-1 downto 0); if interrupt_i='0' then in_irq_r <= '0'; -- no longer in an interrupt end if; case state is when st_execute => if dec_valid = '1' then state <= st_fetch; -- At this point: -- b_i contains opcode word -- a_i contains top of stack pc_r <= pc_r+1; -- synthesis translate_off -- Debug info (Trace) dbg_o.b_inst <= '1'; dbg_o.pc <= (others => '0'); dbg_o.pc(g_addr_size-1 downto 0) <= pc_r; dbg_o.opcode <= opcode_r; dbg_o.sp <= (others => '0'); dbg_o.sp(g_stack_size-1 downto 2) <= sp_r; dbg_o.stk_a <= a_i; dbg_o.stk_b <= b_i; -- synthesis translate_on -- During the next cycle we'll be reading the next opcode sp_offset(4):=not opcode_r(4); sp_offset(3 downto 0):=opcode_r(3 downto 0); idim_r <= '0'; -------------------- -- Execution Unit -- -------------------- case d_opcode_r is when dec_interrupt => -- Not a real instruction, but an interrupt -- Push(PC); PC=32 sp_r <= sp_r-1; a_addr_r <= sp_r-1; a_we_r <= '1'; a_r <= (others => g_dont_care); a_r(c_max_addr_bit downto 0) <= pc_r; -- Jump to ISR pc_r <= to_unsigned(32, c_max_addr_bit+1); -- interrupt address --report "ZPU jumped to interrupt!" severity note; when dec_im => idim_r <= '1'; a_we_r <= '1'; if idim_r='0' then -- First IM -- Push the 7 bits (extending the sign) sp_r <= sp_r-1; a_addr_r <= sp_r-1; a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32)); else -- Next IMs, shift the word and put the new value in the lower -- bits a_addr_r <= sp_r; a_r(31 downto 7) <= a_i(24 downto 0); a_r(6 downto 0) <= opcode_r(6 downto 0); end if; when dec_store_sp => -- [SP+Offset]=Pop() b_we_r <= '1'; b_addr_r <= sp_r+sp_offset; b_r <= a_i; sp_r <= sp_r+1; state <= st_resync; when dec_load_sp => -- Push([SP+Offset]) sp_r <= sp_r-1; a_addr_r <= sp_r+sp_offset; posted_wr_a <= '1'; state <= st_resync; when dec_emulate => -- Push(PC+1), PC=Opcode[4:0]32 sp_r <= sp_r-1; a_we_r <= '1'; a_addr_r <= sp_r-1; a_r <= (others => g_dont_care); a_r(c_max_addr_bit downto 0) <= pc_r+1; -- Jump to NUM*32 -- The emulate address is: -- 98 7654 3210 -- 0000 00aa aaa0 0000 pc_r <= (others => '0'); pc_r(9 downto 5) <= opcode_r(4 downto 0); when dec_add_sp => -- Push(Pop()+[SP+Offset]) a_addr_r <= sp_r; b_addr_r <= sp_r+sp_offset; state <= st_add_sp; when dec_break => --report "Break instruction encountered" severity failure; break_o <= '1'; when dec_push_sp => -- Push(SP) sp_r <= sp_r-1; a_we_r <= '1'; a_addr_r <= sp_r-1; a_r <= (others => '0'); a_r(sp_r'range) <= sp_r; a_r(31) <= '1'; -- DEBUG when dec_pop_pc => -- Pop(PC) pc_r <= a_i(pc_r'range); sp_r <= sp_r+1; state <= st_resync; when dec_add => -- Push(Pop()+Pop()) sp_r <= sp_r+1; state <= st_add; when dec_or => -- Push(Pop() or Pop()) sp_r <= sp_r+1; state <= st_or; when dec_and => -- Push(Pop() and Pop()) sp_r <= sp_r+1; state <= st_and; -- when dec_loadb => -- addr_r <= a_i(g_addr_size-1 downto 0); -- -- assert a_i(31)='0' -- report "LoadB only works from external memory!" -- severity error; -- -- c_en_r <= '1'; -- c_mux_r <= '1'; -- byte_cnt <= "00"; -- 1 byte -- byte_cnt_d <= "11"; -- state <= st_read_mem; when dec_load => -- Push([Pop()]) addr_r <= a_i(g_addr_size-1 downto 0); if a_i(31)='1' then -- stack a_addr_r <= a_i(a_addr_r'range); posted_wr_a <= '1'; state <= st_resync; else c_en_r <= '1'; c_mux_r <= '1'; state <= st_read_mem; byte_cnt <= "11"; -- 4 bytes byte_cnt_d <= "11"; end if; when dec_not => -- Push(not(Pop())) a_addr_r <= sp_r; a_we_r <= '1'; a_r <= not a_i; when dec_flip => -- Push(flip(Pop())) a_addr_r <= sp_r; a_we_r <= '1'; for i in 0 to 31 loop a_r(i) <= a_i(31-i); end loop; when dec_store => -- a=Pop(), b=Pop(), [a]=b sp_r <= sp_r+1; b_addr_r <= sp_r+1; -- added from store/io_store if a_i(31) = '1' then state <= st_store; b_addr_r <= sp_r+1; else state <= st_write_mem; byte_cnt <= "11"; -- 4 bytes first <= '1'; c_mux_r <= '1'; end if; when dec_pop_sp => -- SP=Pop() sp_r <= a_i(g_stack_size-1 downto 2); state <= st_resync; when dec_nop => -- Default, keep addressing to of the stack (A) a_addr_r <= sp_r; when others => null; end case; end if; -- decode valid when st_store => sp_r <= sp_r+1; a_we_r <= '1'; a_addr_r <= a_i(g_stack_size-1 downto 2); a_r <= b_i; state <= st_resync; when st_read_mem => -- BIG ENDIAN if c_valid_i = '1' then case byte_cnt_d is when "00" => a_r(7 downto 0) <= c_i; when "01" => a_r(15 downto 8) <= c_i; when "10" => a_r(23 downto 16) <= c_i; when others => -- 11 a_r(31 downto 24) <= c_i; end case; addr_r(1 downto 0) <= addr_r(1 downto 0) + 1; byte_cnt <= byte_cnt - 1; if byte_cnt_d = "00" then a_addr_r <= sp_r; a_we_r <= '1'; state <= st_fetch; end if; if byte_cnt = "00" then c_mux_r <= '0'; c_en_r <= '0'; end if; end if; when st_write_mem => case byte_cnt is when "00" => c_o <= b_i(7 downto 0); when "01" => c_o <= b_i(15 downto 8); when "10" => c_o <= b_i(23 downto 16); when others => -- 11 c_o <= b_i(31 downto 24); end case; if first='1' then first <= '0'; addr_r <= a_i(g_addr_size-1 downto 0); else addr_r(1 downto 0) <= addr_r(1 downto 0) + 1; end if; c_en_r <= '1'; c_we_r <= '1'; byte_cnt <= byte_cnt - 1; if byte_cnt = "00" then sp_r <= sp_r+1; state <= st_resync; end if; when st_fetch => -- We need to resync. During this cycle -- we'll fetch the opcode @ pc and thus it will -- be available for st_execute in the next cycle -- At this point a_i contains the value that is from the top of the stack -- or that was fetched from the stack with an offset (loadsp) a_we_r <= posted_wr_a; a_r <= a_i; a_addr_r <= sp_r; b_addr_r <= sp_r+1; state <= st_decode; when st_decode => if interrupt_i='1' and in_irq_r='0' and idim_r='0' then -- We got an interrupt, execute interrupt instead of next instruction in_irq_r <= '1'; d_opcode_r <= dec_interrupt; end if; -- during the st_execute cycle we'll be fetching SP+1 a_addr_r <= sp_r; b_addr_r <= sp_r+1; state <= st_execute; when st_add_sp => state <= st_add; when st_add => a_addr_r <= sp_r; a_we_r <= '1'; a_r <= a_i+b_i; state <= st_fetch; when st_or => a_addr_r <= sp_r; a_we_r <= '1'; a_r <= a_i or b_i; state <= st_fetch; when st_and => a_addr_r <= sp_r; a_we_r <= '1'; a_r <= a_i and b_i; state <= st_fetch; when st_resync => c_en_r <= '0'; c_mux_r <= '0'; a_addr_r <= sp_r; state <= st_fetch; posted_wr_a <= posted_wr_a; -- keep when others => null; end case; if reset_i='1' then state <= st_resync; sp_r <= SP_START; pc_r <= (others => '0'); idim_r <= '0'; in_irq_r <= '0'; c_mux_r <= '0'; first <= '0'; end if; end if; -- rising_edge(clk_i) end process opcode_control; end architecture Behave; -- Entity: zpu_8bit	gpl-3.0
Netzpfuscher/stmbl	hw/kicad/bob/firmware/PIN_stmbl_bob_001_34.vhd	2	9826	library IEEE; use IEEE.std_logic_1164.all; -- defines std_logic types use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics -- http://www.mesanet.com -- -- This program is is licensed under a disjunctive dual license giving you -- the choice of one of the two following sets of free software/open source -- licensing terms: -- -- * GNU General Public License (GPL), version 2.0 or later -- * 3-clause BSD License -- -- -- The GNU GPL License: -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -- -- -- The 3-clause BSD License: -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- * Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- * Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- * Neither the name of Mesa Electronics nor the names of its -- contributors may be used to endorse or promote products -- derived from this software without specific prior written -- permission. -- -- -- Disclaimer: -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- use work.IDROMConst.all; package PIN_stmbl_bob_001_34 is constant ModuleID : ModuleIDType :=( (WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask), (IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask), (SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask), (LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000") ); constant PinDesc : PinDescType :=( -- Base func sec unit sec func sec pin external DB25 IOPortTag & x"00" & NullTag & x"00", -- I/O 00 PIN 1 LED IOPortTag & x"00" & NullTag & x"00", -- I/O 01 PIN 14 in0 IOPortTag & x"00" & NullTag & x"00", -- I/O 02 PIN 2 out0 IOPortTag & x"00" & NullTag & x"00", -- I/O 03 PIN 15 in1 IOPortTag & x"00" & NullTag & x"00", -- I/O 04 PIN 3 out1 IOPortTag & x"00" & NullTag & x"00", -- I/O 05 PIN 16 in2 IOPortTag & x"00" & NullTag & x"00", -- I/O 06 PIN 4 out2 IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, -- I/O 07 PIN 17 5. port(top right) IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, -- I/O 08 PIN 5 IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 09 PIN 6 4. port IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 10 PIN 7 IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 11 PIN 8 3. port IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 12 PIN 9 IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 13 PIN 10 2. port IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 14 PIN 11 IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 15 PIN 12 1. port(top left) IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 16 PIN 13 -- 26 HDR IDC DB25 IOPortTag & x"00" & NullTag & x"00", -- I/O 17 PIN 1 PIN 1 IOPortTag & x"00" & NullTag & x"00", -- I/O 18 PIN 2 PIN 14 IOPortTag & x"00" & NullTag & x"00", -- I/O 19 PIN 3 PIN 2 IOPortTag & x"00" & NullTag & x"00", -- I/O 20 PIN 4 PIN 15 IOPortTag & x"00" & NullTag & x"00", -- I/O 21 PIN 5 PIN 3 IOPortTag & x"00" & NullTag & x"00", -- I/O 22 PIN 6 PIN 16 IOPortTag & x"00" & NullTag & x"00", -- I/O 23 PIN 7 PIN 4 IOPortTag & x"00" & NullTag & x"00", -- I/O 24 PIN 8 PIN 17 IOPortTag & x"00" & NullTag & x"00", -- I/O 25 PIN 9 PIN 5 IOPortTag & x"00" & NullTag & x"00", -- I/O 26 PIN 11 PIN 6 IOPortTag & x"00" & NullTag & x"00", -- I/O 27 PIN 13 PIN 7 IOPortTag & x"00" & NullTag & x"00", -- I/O 28 PIN 15 PIN 8 IOPortTag & x"00" & NullTag & x"00", -- I/O 29 PIN 17 PIN 9 IOPortTag & x"00" & NullTag & x"00", -- I/O 30 PIN 19 PIN 10 IOPortTag & x"00" & NullTag & x"00", -- I/O 31 PIN 21 PIN 11 IOPortTag & x"00" & NullTag & x"00", -- I/O 32 PIN 23 PIN 12 IOPortTag & x"00" & NullTag & x"00", -- I/O 33 PIN 25 PIN 13 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin); end package PIN_stmbl_bob_001_34;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/sid6581/vhdl_source/sid_regs.vhd	4	11455	------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 Gideon's Logic Architectures' -- ------------------------------------------------------------------------------- -- -- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) -- -- Note that this file is copyrighted, and is not supposed to be used in other -- projects without written permission from the author. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity sid_regs is port ( clock : in std_logic; reset : in std_logic; addr : in unsigned(7 downto 0); wren : in std_logic; wdata : in std_logic_vector(7 downto 0); rdata : out std_logic_vector(7 downto 0); --- comb_wave_l : in std_logic; comb_wave_r : in std_logic; --- voice_osc : in unsigned(3 downto 0); voice_wave : in unsigned(3 downto 0); voice_adsr : in unsigned(3 downto 0); voice_mul : in unsigned(3 downto 0); -- Oscillator parameters freq : out unsigned(15 downto 0); test : out std_logic; sync : out std_logic; -- Wave map parameters comb_mode : out std_logic; ring_mod : out std_logic; wave_sel : out std_logic_vector(3 downto 0); sq_width : out unsigned(11 downto 0); -- ADSR parameters gate : out std_logic; attack : out std_logic_vector(3 downto 0); decay : out std_logic_vector(3 downto 0); sustain : out std_logic_vector(3 downto 0); release : out std_logic_vector(3 downto 0); -- mixer 1 parameters filter_en : out std_logic; -- globals volume_l : out unsigned(3 downto 0) := (others => '0'); filter_co_l : out unsigned(10 downto 0) := (others => '0'); filter_res_l : out unsigned(3 downto 0) := (others => '0'); filter_ex_l : out std_logic := '0'; filter_hp_l : out std_logic := '0'; filter_bp_l : out std_logic := '0'; filter_lp_l : out std_logic := '0'; voice3_off_l : out std_logic := '0'; volume_r : out unsigned(3 downto 0) := (others => '0'); filter_co_r : out unsigned(10 downto 0) := (others => '0'); filter_res_r : out unsigned(3 downto 0) := (others => '0'); filter_ex_r : out std_logic := '0'; filter_hp_r : out std_logic := '0'; filter_bp_r : out std_logic := '0'; filter_lp_r : out std_logic := '0'; voice3_off_r : out std_logic := '0'; -- readback osc3 : in std_logic_vector(7 downto 0); env3 : in std_logic_vector(7 downto 0) ); attribute keep_hierarchy : string; attribute keep_hierarchy of sid_regs : entity is "yes"; end sid_regs; architecture gideon of sid_regs is type byte_array_t is array(natural range <>) of std_logic_vector(7 downto 0); type nibble_array_t is array(natural range <>) of std_logic_vector(3 downto 0); signal freq_lo : byte_array_t(0 to 15) := (others => (others => '0')); signal freq_hi : byte_array_t(0 to 15) := (others => (others => '0')); signal phase_lo : byte_array_t(0 to 15) := (others => (others => '0')); signal phase_hi : nibble_array_t(0 to 15):= (others => (others => '0')); signal control : byte_array_t(0 to 15) := (others => (others => '0')); signal att_dec : byte_array_t(0 to 15) := (others => (others => '0')); signal sust_rel : byte_array_t(0 to 15) := (others => (others => '0')); signal do_write : std_logic; signal wdata_d : std_logic_vector(7 downto 0); signal filt_en_i: std_logic_vector(15 downto 0) := (others => '0'); constant address_remap : byte_array_t(0 to 255) := ( X"00", X"01", X"02", X"03", X"04", X"05", X"06", -- 00 Voice 1 X"10", X"11", X"12", X"13", X"14", X"15", X"16", -- 07 Voice 2 X"20", X"21", X"22", X"23", X"24", X"25", X"26", -- 0E Voice 3 X"08", X"09", X"0A", X"0B", -- 15 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 19 X"30", X"31", X"32", X"33", X"34", X"35", X"36", -- 20 Voice 4 X"40", X"41", X"42", X"43", X"44", X"45", X"46", -- 27 Voice 5 X"50", X"51", X"52", X"53", X"54", X"55", X"56", -- 2E Voice 6 X"60", X"61", X"62", X"63", X"64", X"65", X"66", -- 35 Voice 7 X"70", X"71", X"72", X"73", X"74", X"75", X"76", -- 3C Voice 8 X"0C", X"0D", X"0E", -- 43 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 46 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 4D X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 54 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 5B X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 62 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 69 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 70 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 77 X"FF", X"FF", -- 7E X"80", X"81", X"82", X"83", X"84", X"85", X"86", -- 80 Voice 9 X"90", X"91", X"92", X"93", X"94", X"95", X"96", -- 87 Voice 10 X"A0", X"A1", X"A2", X"A3", X"A4", X"A5", X"A6", -- 8E Voice 11 X"88", X"89", X"8A", X"8B", -- 95 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 99 X"B0", X"B1", X"B2", X"B3", X"B4", X"B5", X"B6", -- A0 Voice 12 X"C0", X"C1", X"C2", X"C3", X"C4", X"C5", X"C6", -- A7 Voice 13 X"D0", X"D1", X"D2", X"D3", X"D4", X"D5", X"D6", -- AE Voice 14 X"E0", X"E1", X"E2", X"E3", X"E4", X"E5", X"E6", -- B5 Voice 15 X"F0", X"F1", X"F2", X"F3", X"F4", X"F5", X"F6", -- BC Voice 16 X"8C", X"8D", X"8E", -- C3 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- C6 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- CD X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- D4 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- DB X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E2 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E9 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F0 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F7 X"FF", X"FF" ); -- FE signal address : unsigned(7 downto 0); begin process(clock) begin if rising_edge(clock) then address <= unsigned(address_remap(to_integer(addr))); do_write <= wren; wdata_d <= wdata; if do_write='1' then if address(3)='0' then -- Voice register case address(2 downto 0) is when "000" => freq_lo(to_integer(address(7 downto 4))) <= wdata_d; when "001" => freq_hi(to_integer(address(7 downto 4))) <= wdata_d; when "010" => phase_lo(to_integer(address(7 downto 4))) <= wdata_d; when "011" => phase_hi(to_integer(address(7 downto 4))) <= wdata_d(3 downto 0); when "100" => control(to_integer(address(7 downto 4))) <= wdata_d; when "101" => att_dec(to_integer(address(7 downto 4))) <= wdata_d; when "110" => sust_rel(to_integer(address(7 downto 4))) <= wdata_d; when others => null; end case; elsif address(7)='0' then -- Global register for left case address(2 downto 0) is when "000" => filter_co_l(2 downto 0) <= unsigned(wdata_d(2 downto 0)); when "001" => filter_co_l(10 downto 3) <= unsigned(wdata_d); when "010" => filter_res_l <= unsigned(wdata_d(7 downto 4)); filter_ex_l <= wdata_d(3); filt_en_i(2 downto 0) <= wdata_d(2 downto 0); when "011" => voice3_off_l <= wdata_d(7); filter_hp_l <= wdata_d(6); filter_bp_l <= wdata_d(5); filter_lp_l <= wdata_d(4); volume_l <= unsigned(wdata_d(3 downto 0)); when "100" => filt_en_i(7 downto 0) <= wdata_d; when others => null; end case; else -- Global register for right case address(2 downto 0) is when "000" => filter_co_r(2 downto 0) <= unsigned(wdata_d(2 downto 0)); when "001" => filter_co_r(10 downto 3) <= unsigned(wdata_d); when "010" => filter_res_r <= unsigned(wdata_d(7 downto 4)); filter_ex_r <= wdata_d(3); filt_en_i(10 downto 8) <= wdata_d(2 downto 0); when "011" => voice3_off_r <= wdata_d(7); filter_hp_r <= wdata_d(6); filter_bp_r <= wdata_d(5); filter_lp_r <= wdata_d(4); volume_r <= unsigned(wdata_d(3 downto 0)); when "100" => filt_en_i(15 downto 8) <= wdata_d; when others => null; end case; end if; end if; -- Readback (unmapped address) case addr is when "00011011" => rdata <= osc3; when "00011100" => rdata <= env3; when others => rdata <= (others => '0'); end case; if reset='1' then filt_en_i <= (others => '0'); voice3_off_l <= '0'; voice3_off_r <= '0'; volume_l <= X"0"; volume_r <= X"0"; end if; end if; end process; freq <= unsigned(freq_hi(to_integer(voice_osc))) & unsigned(freq_lo(to_integer(voice_osc))); test <= control(to_integer(voice_osc))(3); sync <= control(to_integer(voice_osc))(1); -- Wave map parameters ring_mod <= control(to_integer(voice_wave))(2); wave_sel <= control(to_integer(voice_wave))(7 downto 4); sq_width <= unsigned(phase_hi(to_integer(voice_wave))) & unsigned(phase_lo(to_integer(voice_wave))); comb_mode <= (voice_wave(3) and comb_wave_r) or (not voice_wave(3) and comb_wave_l); -- ADSR parameters gate <= control(to_integer(voice_adsr))(0); attack <= att_dec(to_integer(voice_adsr))(7 downto 4); decay <= att_dec(to_integer(voice_adsr))(3 downto 0); sustain <= sust_rel(to_integer(voice_adsr))(7 downto 4); release <= sust_rel(to_integer(voice_adsr))(3 downto 0); -- Mixer 1 parameters filter_en <= filt_en_i(to_integer(voice_mul)); end gideon;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v4b.vhd	3	12673	------------------------------------------------------------------------------- -- Title : External Memory controller for SDRAM (burst capable) ------------------------------------------------------------------------------- -- Description: This module implements a simple, single access memory controller. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; library work; use work.mem_bus_pkg.all; entity ext_mem_ctrl_v4b is generic ( g_simulation : boolean := false; A_Width : integer := 15; SDRAM_WakeupTime : integer := 40; -- refresh periods SDRAM_Refr_period : integer := 375 ); port ( clock : in std_logic := '0'; clk_shifted : in std_logic := '0'; reset : in std_logic := '0'; inhibit : in std_logic; is_idle : out std_logic; req : in t_mem_req; resp : out t_mem_resp; SDRAM_CLK : out std_logic; SDRAM_CKE : out std_logic; SDRAM_CSn : out std_logic := '1'; SDRAM_RASn : out std_logic := '1'; SDRAM_CASn : out std_logic := '1'; SDRAM_WEn : out std_logic := '1'; SDRAM_DQM : out std_logic := '0'; MEM_A : out std_logic_vector(A_Width-1 downto 0); MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z')); end ext_mem_ctrl_v4b; -- ADDR: 25 24 23 ... -- 0 X X ... SDRAM (32MB) architecture Gideon of ext_mem_ctrl_v4b is -- SRCW constant c_cmd_inactive : std_logic_vector(3 downto 0) := "1111"; constant c_cmd_nop : std_logic_vector(3 downto 0) := "0111"; constant c_cmd_active : std_logic_vector(3 downto 0) := "0011"; constant c_cmd_read : std_logic_vector(3 downto 0) := "0101"; constant c_cmd_write : std_logic_vector(3 downto 0) := "0100"; constant c_cmd_bterm : std_logic_vector(3 downto 0) := "0110"; constant c_cmd_precharge : std_logic_vector(3 downto 0) := "0010"; constant c_cmd_refresh : std_logic_vector(3 downto 0) := "0001"; constant c_cmd_mode_reg : std_logic_vector(3 downto 0) := "0000"; type t_init is record addr : std_logic_vector(15 downto 0); cmd : std_logic_vector(3 downto 0); end record; type t_init_array is array(natural range <>) of t_init; constant c_init_array : t_init_array(0 to 7) := ( ( X"0400", c_cmd_precharge ), ( X"0222", c_cmd_mode_reg ), -- mode register, burstlen=4, writelen=1, CAS lat = 2 ( X"0000", c_cmd_refresh ), ( X"0000", c_cmd_refresh ), ( X"0000", c_cmd_refresh ), ( X"0000", c_cmd_refresh ), ( X"0000", c_cmd_refresh ), ( X"0000", c_cmd_refresh ) ); type t_state is (boot, init, idle, sd_read, read_single, read_single_end, sd_write, wait_for_precharge, delay_to_terminate); signal state : t_state; signal sdram_cmd : std_logic_vector(3 downto 0) := "1111"; signal sdram_d_o : std_logic_vector(MEM_D'range) := (others => '1'); signal sdram_d_t : std_logic := '0'; signal delay : integer range 0 to 15; signal inhibit_d : std_logic; signal rwn_i : std_logic; signal tag : std_logic_vector(req.tag'range); signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0'); signal col_addr : std_logic_vector(9 downto 0) := (others => '0'); signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1; signal do_refresh : std_logic := '0'; signal refresh_inhibit: std_logic := '0'; signal not_clock : std_logic; signal reg_out : integer range 0 to 3 := 0; signal rdata_i : std_logic_vector(7 downto 0) := (others => '0'); signal dout_sel : std_logic := '0'; signal refr_delay : integer range 0 to 3; signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1; signal init_cnt : integer range 0 to c_init_array'high; signal enable_sdram : std_logic := '1'; signal req_i : std_logic; signal dack_count : unsigned(1 downto 0) := "00"; signal count_out : unsigned(1 downto 0) := "00"; signal dack : std_logic := '0'; signal dack_pre : std_logic := '0'; signal rack : std_logic := '0'; signal dack_tag_pre : std_logic_vector(req.tag'range) := (others => '0'); signal rack_tag : std_logic_vector(req.tag'range) := (others => '0'); signal dack_tag : std_logic_vector(req.tag'range) := (others => '0'); -- attribute fsm_encoding : string; -- attribute fsm_encoding of state : signal is "sequential"; -- attribute register_duplication : string; -- attribute register_duplication of mem_a_i : signal is "no"; attribute iob : string; attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB attribute iob of sdram_cmd : signal is "true"; attribute iob of mem_a_i : signal is "true"; attribute iob of SDRAM_CKE : signal is "false"; begin is_idle <= '1' when state = idle else '0'; req_i <= req.request; resp.data <= rdata_i; resp.rack <= rack; resp.rack_tag <= rack_tag; resp.dack_tag <= dack_tag; resp.count <= count_out; process(clock) procedure send_refresh_cmd is begin do_refresh <= '0'; sdram_cmd <= c_cmd_refresh; refr_delay <= 3; end procedure; procedure accept_req is begin rack <= '1'; rack_tag <= req.tag; tag <= req.tag; rwn_i <= req.read_writen; dack_count <= req.size; sdram_d_o <= req.data; mem_a_i(12 downto 0) <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits mem_a_i(14 downto 13) <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits sdram_cmd <= c_cmd_active; end procedure; begin if rising_edge(clock) then rack <= '0'; rack_tag <= (others => '0'); dack_pre <= '0'; dack_tag_pre <= (others => '0'); dack <= dack_pre; dack_tag <= dack_tag_pre; if dack='1' then count_out <= count_out + 1; else count_out <= "00"; end if; dout_sel <= '0'; inhibit_d <= inhibit; rdata_i <= MEM_D; -- clock in sdram_cmd <= c_cmd_inactive; SDRAM_CKE <= enable_sdram; sdram_d_t <= '0'; if refr_delay /= 0 then refr_delay <= refr_delay - 1; end if; if delay /= 0 then delay <= delay - 1; end if; if inhibit='1' then refresh_inhibit <= '1'; end if; case state is when boot => refresh_inhibit <= '0'; enable_sdram <= '1'; if refresh_cnt = 0 then boot_cnt <= boot_cnt - 1; if boot_cnt = 1 then state <= init; end if; elsif g_simulation then state <= idle; end if; when init => mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range); sdram_cmd(3) <= '1'; sdram_cmd(2 downto 0) <= c_init_array(init_cnt).cmd(2 downto 0); if delay = 0 then delay <= 7; sdram_cmd(3) <= '0'; if init_cnt = c_init_array'high then state <= idle; else init_cnt <= init_cnt + 1; end if; end if; when idle => -- first cycle after inhibit goes 1, should not be a refresh -- this enables putting cartridge images in sdram, because we guarantee the first access after inhibit to be a cart cycle if do_refresh='1' and refresh_inhibit='0' then send_refresh_cmd; elsif inhibit='0' then -- make sure we are allowed to start a new cycle if req_i='1' and refr_delay = 0 then accept_req; refresh_inhibit <= '0'; if req.read_writen = '1' then state <= sd_read; else state <= sd_write; end if; end if; end if; when sd_read => mem_a_i(10) <= '0'; -- no auto precharge mem_a_i(9 downto 0) <= col_addr; sdram_cmd <= c_cmd_read; if dack_count = "00" then state <= read_single; else state <= delay_to_terminate; end if; when read_single => dack_pre <= '1'; dack_tag_pre <= tag; sdram_cmd <= c_cmd_bterm; state <= read_single_end; when read_single_end => sdram_cmd <= c_cmd_precharge; state <= idle; when delay_to_terminate => dack_pre <= '1'; dack_tag_pre <= tag; dack_count <= dack_count - 1; delay <= 2; if dack_count = "00" then sdram_cmd <= c_cmd_precharge; state <= idle; end if; when sd_write => if delay = 0 then mem_a_i(10) <= '1'; -- auto precharge mem_a_i(9 downto 0) <= col_addr; sdram_cmd <= c_cmd_write; sdram_d_t <= '1'; delay <= 2; state <= wait_for_precharge; end if; when wait_for_precharge => if delay = 0 then state <= idle; end if; when others => null; end case; if refresh_cnt = SDRAM_Refr_period-1 then do_refresh <= '1'; refresh_cnt <= 0; else refresh_cnt <= refresh_cnt + 1; end if; if reset='1' then state <= boot; sdram_d_t <= '0'; delay <= 0; tag <= (others => '0'); do_refresh <= '0'; boot_cnt <= SDRAM_WakeupTime-1; init_cnt <= 0; enable_sdram <= '1'; refresh_inhibit <= '0'; end if; end if; end process; MEM_D <= sdram_d_o when sdram_d_t='1' else (others => 'Z'); MEM_A <= mem_a_i; SDRAM_CSn <= sdram_cmd(3); SDRAM_RASn <= sdram_cmd(2); SDRAM_CASn <= sdram_cmd(1); SDRAM_WEn <= sdram_cmd(0); not_clock <= not clk_shifted; clkout: FDDRRSE port map ( CE => '1', C0 => clk_shifted, C1 => not_clock, D0 => '0', D1 => enable_sdram, Q => SDRAM_CLK, R => '0', S => '0' ); end Gideon; -- ACT to READ: tRCD = 20 ns ( = 1 CLK) -- ACT to PRCH: tRAS = 44 ns ( = 3 CLKs) -- ACT to ACT: tRC = 66 ns ( = 4 CLKs) -- ACT to ACTb: tRRD = 15 ns ( = 1 CLK) -- PRCH time; tRP = 20 ns ( = 1 CLK) -- wr. recov. tWR=8ns+1clk ( = 2 CLKs) (starting from last data word) -- CL=2 -- 0 1 2 3 4 5 6 7 8 9 -- BL1 A R P + -- - - - D -- +: ONLY if same bank, otherwise we don't meet tRC. -- BL2 A R - P -- - - - D D -- BL3 A R - - P -- - - - D D D -- BL4 A r - - - p -- - - - D D D D -- BL1W A(W)= = p -- - D - - - -- BL4 A r - - - p - A -- - - - D D D D -- BL1W A(W)= = p -- - D - - -	gpl-3.0
davidhorrocks/1541UltimateII	fpga/ip/busses/vhdl_bfm/dma_bus_slave_bfm.vhd	5	1680	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.dma_bus_pkg.all; use work.tl_flat_memory_model_pkg.all; entity dma_bus_slave_bfm is generic ( g_name : string; g_latency : positive := 2 ); port ( clock : in std_logic; req : in t_dma_req; resp : out t_dma_resp ); end dma_bus_slave_bfm; architecture bfm of dma_bus_slave_bfm is shared variable mem : h_mem_object; signal bound : boolean := false; signal pipe : t_dma_req_array(0 to g_latency-1) := (others => c_dma_req_init); signal resp_i : t_dma_resp; begin -- this process registers this instance of the bfm to the server package bind: process begin register_mem_model(dma_bus_slave_bfm'path_name, g_name, mem); bound <= true; wait; end process; resp <= resp_i; process(clock) begin if rising_edge(clock) then pipe(0 to g_latency-2) <= pipe(1 to g_latency-1); pipe(g_latency-1) <= req; if resp_i.rack='1' then pipe(g_latency-1).request <= '0'; end if; resp_i.data <= (others => '0'); resp_i.dack <= '0'; resp_i.rack <= '0'; if bound then resp_i.rack <= req.request and not resp_i.rack; if pipe(0).request='1' then if pipe(0).read_writen='1' then resp_i.data <= read_memory_8(mem, X"0000" & std_logic_vector(pipe(0).address)); resp_i.dack <= '1'; else write_memory_8(mem, X"0000" & std_logic_vector(pipe(0).address), pipe(0).data); end if; end if; end if; end if; end process; end bfm;	gpl-3.0
davidhorrocks/1541UltimateII	target/simulation/packages/vhdl_source/tl_math_pkg.vhd	5	12297	------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 - Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : Miscelaneous mathematic operations ------------------------------------------------------------------------------- -- Description: This file contains math functions ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package tl_math_pkg is --------------------------------------------------------------------------- -- increment/decrement functions --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- wrapping decrement/increment --------------------------------------------------------------------------- -- Description: These functions give an increment/decrement that wraps when -- the maximal vector range is reached. --------------------------------------------------------------------------- function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector; function incr(old_value: unsigned; increment: natural := 1) return unsigned; function incr(old_value: signed; increment: natural := 1) return signed; function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector; function decr(old_value: unsigned; decrement: natural := 1) return unsigned; function decr(old_value: signed; decrement: natural := 1) return signed; --------------------------------------------------------------------------- -- clipping decrement/increment --------------------------------------------------------------------------- -- Description: These functions give an increment/decrement that clips when -- the maximal vector range is reached. --------------------------------------------------------------------------- function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector; function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned; function incr_clip(old_value: signed; increment: natural := 1) return signed; function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector; function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned; function decr_clip(old_value: signed; decrement: natural := 1) return signed; --------------------------------------------------------------------------- -- log functions --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- log2 --------------------------------------------------------------------------- -- Description: This functions returns the log2 value of a number. The -- result is in the natural range and rounded depended on the -- selected mode. -- NOTE: use an argument of type unsigned when using this function for -- synthesis --------------------------------------------------------------------------- type log2mode is (ceil, floor); function log2(arg: integer) return natural; function log2(arg: integer; mode: log2mode) return natural; function log2_floor(arg: integer) return natural; function log2_ceil(arg: integer) return natural; function log2(arg: unsigned) return natural; function log2(arg: unsigned; mode: log2mode) return natural; function log2_floor(arg: unsigned) return natural; function log2_ceil(arg: unsigned) return natural; --------------------------------------------------------------------------- -- min/max --------------------------------------------------------------------------- -- Description: These functions return the minimum/maximum of two values --------------------------------------------------------------------------- function max(a, b: integer) return integer; function max(a, b: unsigned) return unsigned; function min(a, b: integer) return integer; function min(a, b: unsigned) return unsigned; end tl_math_pkg; library work; use work.tl_vector_pkg.all; package body tl_math_pkg is --------------------------------------------------------------------------- -- increment/decrement functions --------------------------------------------------------------------------- function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is begin return std_logic_vector(incr(unsigned(old_value), increment)); end function; function incr(old_value: unsigned; increment: natural := 1) return unsigned is variable v_result : unsigned(old_value'range); begin v_result := (old_value + increment) mod 2old_value'length; return v_result; end function; function incr(old_value: signed; increment: natural := 1) return signed is begin return signed(incr(unsigned(old_value), increment)); end function; function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is begin return std_logic_vector(decr(unsigned(old_value), decrement)); end function; function decr(old_value: unsigned; decrement: natural := 1) return unsigned is constant c_norm_decrement : integer := decrement mod 2old_value'length; variable v_result : unsigned(old_value'range); begin v_result := (2old_value'length + (old_value - c_norm_decrement)) mod 2old_value'length; return v_result; end function; function decr(old_value: signed; decrement: natural := 1) return signed is begin return signed(decr(unsigned(old_value), decrement)); end function; --------------------------------------------------------------------------- -- clipping decrement/increment --------------------------------------------------------------------------- -- Description: These functions give an increment/decrement that clips when -- the maximal vector range is reached. --------------------------------------------------------------------------- function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is begin return std_logic_vector(incr_clip(unsigned(old_value), increment)); end function; function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned is constant c_max_value : unsigned(old_value'range) := (others => '1'); variable v_result : unsigned(old_value'range); begin assert increment < 2old_value'length report "ERROR: Increment value is larger than vector range" severity error; if old_value <= (c_max_value - increment) then v_result := old_value + increment; else v_result := c_max_value; end if; return v_result; end function; function incr_clip(old_value: signed; increment: natural := 1) return signed is variable c_max_value : signed(old_value'range) := to_signed(2old_value'length / 2 - 1, old_value'length); variable v_result : signed(old_value'range); begin if old_value <= (c_max_value - increment) then v_result := old_value + increment; else v_result := c_max_value; end if; return v_result; end function; function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is begin return std_logic_vector(decr_clip(unsigned(old_value), decrement)); end function; function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned is constant c_min_value : unsigned(old_value'range) := (others => '0'); variable v_result : unsigned(old_value'range); begin if old_value >= (c_min_value + decrement) then v_result := old_value - decrement; else v_result := c_min_value; end if; return v_result; end function; function decr_clip(old_value: signed; decrement: natural := 1) return signed is constant c_min_value : signed(old_value'range) := to_signed(2old_value'length / 2, old_value'length); variable v_result : signed(old_value'range); begin if old_value >= (c_min_value + decrement) then v_result := old_value - decrement; else v_result := c_min_value; end if; return v_result; end function; --------------------------------------------------------------------------- -- log functions --------------------------------------------------------------------------- function log2(arg: integer) return natural is begin return log2_ceil(arg); end function; function log2(arg: integer; mode: log2mode) return natural is begin if mode = floor then return log2_floor(arg); else return log2_ceil(arg); end if; end; function log2_ceil(arg: integer) return natural is variable v_temp : integer; variable v_result : natural; begin v_result := log2_floor(arg); if 2v_result < arg then return v_result + 1; else return v_result; end if; end function; function log2_floor(arg: integer) return natural is variable v_temp : integer; variable v_result : natural; begin v_result := 0; v_temp := arg / 2; while v_temp /= 0 loop v_temp := v_temp / 2; v_result := v_result + 1; end loop; return v_result; end function; function log2(arg: unsigned) return natural is begin return log2_ceil(arg); end function; function log2(arg: unsigned; mode: log2mode) return natural is begin if mode = ceil then return log2_ceil(arg); else return log2_floor(arg); end if; end function; function log2_floor(arg: unsigned) return natural is alias w : unsigned(arg'length - 1 downto 0) is arg; begin return highest_bit(w); end function; function log2_ceil(arg: unsigned) return natural is alias w : unsigned(arg'length - 1 downto 0) is arg; begin if ones(arg) > 1 then return highest_bit(w) + 1; else return highest_bit(w); end if; end function; --------------------------------------------------------------------------- -- min/max --------------------------------------------------------------------------- -- Description: These functions return the minimum/maximum of two values --------------------------------------------------------------------------- function max(a, b: integer) return integer is begin if a > b then return a; else return b; end if; end function; function max(a, b: unsigned) return unsigned is begin if a > b then return a; else return b; end if; end function; function min(a, b: integer) return integer is begin if a < b then return a; else return b; end if; end function; function min(a, b: unsigned) return unsigned is begin if a < b then return a; else return b; end if; end function; end tl_math_pkg;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/ip/nano_cpu/vhdl_sim/nano_tb.vhd	5	807	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nano_tb is end entity; architecture tb of nano_tb is signal clock : std_logic := '0'; signal reset : std_logic; signal io_addr : unsigned(7 downto 0); signal io_write : std_logic; signal io_wdata : std_logic_vector(15 downto 0); signal io_rdata : std_logic_vector(15 downto 0); begin clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; i_cpu: entity work.nano port map ( clock => clock, reset => reset, -- i/o interface io_addr => io_addr, io_write => io_write, io_wdata => io_wdata, io_rdata => io_rdata ); end architecture;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/1541/vhdl_sim/tb_hardware_gcr.vhd	5	3010	library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity tb_hardware_gcr is end tb_hardware_gcr; architecture tb of tb_hardware_gcr is signal clock : std_logic := '0'; signal reset : std_logic; signal cpu_clock_en: std_logic := '1'; signal cpu_addr : std_logic_vector(2 downto 0) := "000"; signal cpu_access : std_logic := '0'; signal cpu_write : std_logic := '0'; signal cpu_wdata : std_logic_vector(7 downto 0) := X"00"; signal cpu_rdata : std_logic_vector(7 downto 0) := X"00"; signal busy : std_logic; signal mem_req : std_logic; signal mem_ack : std_logic := '1'; signal mem_addr : std_logic_vector(23 downto 0); signal mem_rwn : std_logic; signal mem_wdata : std_logic_vector(7 downto 0); signal mem_rdata : std_logic_vector(7 downto 0) := X"00"; begin clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; hw: entity work.hardware_gcr port map ( clock => clock, reset => reset, cpu_clock_en => cpu_clock_en, cpu_addr => cpu_addr, cpu_access => cpu_access, cpu_write => cpu_write, cpu_wdata => cpu_wdata, cpu_rdata => cpu_rdata, busy => busy, --- mem_req => mem_req, mem_ack => mem_ack, mem_addr => mem_addr, mem_rwn => mem_rwn, mem_wdata => mem_wdata, mem_rdata => mem_rdata ); process procedure do_write(a: std_logic_vector(2 downto 0); d: std_logic_vector(7 downto 0)) is begin wait until clock='1'; cpu_access <= '1'; cpu_write <= '1'; cpu_addr <= a; cpu_wdata <= d; wait until clock='1'; cpu_access <= '0'; cpu_write <= '0'; for i in 0 to 9 loop wait until clock='1'; end loop; end procedure do_write; begin wait until reset='0'; do_write("000", X"56"); do_write("001", X"34"); do_write("010", X"12"); do_write("100", X"47"); do_write("100", X"47"); do_write("100", X"47"); do_write("100", X"47"); do_write("101", X"00"); do_write("101", X"00"); do_write("101", X"00"); do_write("101", X"00"); do_write("101", X"00"); do_write("101", X"00"); do_write("101", X"00"); do_write("100", X"47"); do_write("100", X"47"); do_write("100", X"47"); do_write("100", X"47"); wait; end process; end tb;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/ip/memory/vhdl_source/spram.vhd	5	1660	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity spram is generic ( g_width_bits : positive := 16; g_depth_bits : positive := 9; g_read_first : boolean := false; g_storage : string := "auto" -- can also be "block" or "distributed" ); port ( clock : in std_logic; address : in unsigned(g_depth_bits-1 downto 0); rdata : out std_logic_vector(g_width_bits-1 downto 0); wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); en : in std_logic := '1'; we : in std_logic ); attribute keep_hierarchy : string; attribute keep_hierarchy of spram : entity is "yes"; end entity; architecture xilinx of spram is type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0); shared variable ram : t_ram := (others => (others => '0')); -- Xilinx and Altera attributes attribute ram_style : string; attribute ram_style of ram : variable is g_storage; begin p_port: process(clock) begin if rising_edge(clock) then if en = '1' then if g_read_first then rdata <= ram(to_integer(address)); end if; if we = '1' then ram(to_integer(address)) := wdata; end if; if not g_read_first then rdata <= ram(to_integer(address)); end if; end if; end if; end process; end architecture;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/sid6581/vhdl_source/adsr_multi.vhd	5	8478	------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 Gideon's Logic Architectures' -- ------------------------------------------------------------------------------- -- -- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) -- -- Note that this file is copyrighted, and is not supposed to be used in other -- projects without written permission from the author. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.sid_debug_pkg.all; -- LUT: 195, FF:68 entity adsr_multi is generic ( g_num_voices : integer := 8 ); port ( clock : in std_logic; reset : in std_logic; voice_i : in unsigned(3 downto 0); enable_i : in std_logic; voice_o : out unsigned(3 downto 0); enable_o : out std_logic; gate : in std_logic; attack : in std_logic_vector(3 downto 0); decay : in std_logic_vector(3 downto 0); sustain : in std_logic_vector(3 downto 0); release : in std_logic_vector(3 downto 0); env_state: out std_logic_vector(1 downto 0); -- for testing only env_out : out unsigned(7 downto 0) ); end adsr_multi; -- 158 1 62 .. FF -- 45 2 35 .. 61 -- 26 4 1C .. 34 -- 13 8 0D .. 1B -- 6 16 07 .. 0C -- 7 30 00 .. 06 architecture gideon of adsr_multi is type presc_array_t is array(natural range <>) of unsigned(15 downto 0); constant prescalers : presc_array_t(0 to 15) := ( X"0008", X"001F", X"003E", X"005E", X"0094", X"00DB", X"010A", X"0138", X"0187", X"03D0", X"07A1", X"0C35", X"0F42", X"2DC7", X"4C4B", X"7A12" ); signal enveloppe : unsigned(7 downto 0) := (others => '0'); signal state : unsigned(1 downto 0) := (others => '0'); constant st_release : unsigned(1 downto 0) := "00"; constant st_attack : unsigned(1 downto 0) := "01"; constant st_decay : unsigned(1 downto 0) := "11"; type state_array_t is array(natural range <>) of unsigned(29 downto 0); signal state_array : state_array_t(0 to g_num_voices-1) := (others => (others => '0')); signal voice_dbg : t_voice_debug_array(0 to g_num_voices-1); begin env_out <= enveloppe; env_state <= std_logic_vector(state); -- FF-5E 01 -- 5D-37 02 -- 36-1B 04 -- 1A-0F 08 -- 0E-07 10 -- 06-01 1E process(clock) function logarithmic(lev: unsigned(7 downto 0)) return unsigned is variable res : unsigned(4 downto 0); begin if lev = X"00" then res := "00000"; -- prescaler off elsif lev < X"07" then res := "11101"; -- 1E-1 elsif lev < X"0F" then res := "01111"; -- 10-1 elsif lev < X"1B" then res := "00111"; -- 08-1 elsif lev < X"37" then res := "00011"; -- 04-1 elsif lev < X"5E" then res := "00001"; -- 02-1 else res := "00000"; -- 01-1 end if; return res; end function logarithmic; variable presc_select : integer range 0 to 15; variable cur_state : unsigned(1 downto 0); variable cur_env : unsigned(7 downto 0); variable cur_pre15 : unsigned(14 downto 0); variable cur_pre5 : unsigned(4 downto 0); variable next_state : unsigned(1 downto 0); variable next_env : unsigned(7 downto 0); variable next_pre15 : unsigned(14 downto 0); variable next_pre5 : unsigned(4 downto 0); variable presc_val : unsigned(14 downto 0); variable log_div : unsigned(4 downto 0); variable do_count_15 : std_logic; variable do_count_5 : std_logic; variable voice_x : integer; begin if rising_edge(clock) then cur_state := state_array(0)(1 downto 0); cur_env := state_array(0)(9 downto 2); cur_pre15 := state_array(0)(24 downto 10); cur_pre5 := state_array(0)(29 downto 25); voice_o <= voice_i; enable_o <= enable_i; next_state := cur_state; next_env := cur_env; next_pre15 := cur_pre15; next_pre5 := cur_pre5; -- PRESCALER LOGIC, output: do_count -- -- 15 bit prescaler select -- case cur_state is when st_attack => presc_select := to_integer(unsigned(attack)); when st_decay => presc_select := to_integer(unsigned(decay)); when others => -- includes release and idle presc_select := to_integer(unsigned(release)); end case; presc_val := prescalers(presc_select)(14 downto 0); -- 15 bit prescaler counter -- do_count_15 := '0'; if cur_pre15 = presc_val then next_pre15 := (others => '0'); do_count_15 := '1'; else next_pre15 := cur_pre15 + 1; end if; -- 5 bit prescaler -- log_div := logarithmic(cur_env); do_count_5 := '0'; if do_count_15='1' then if (cur_state = st_attack) or cur_pre5 = log_div then next_pre5 := "00000"; do_count_5 := '1'; else next_pre5 := cur_pre5 + 1; end if; end if; -- END PRESCALER LOGIC -- case cur_state is when st_attack => if gate = '0' then next_state := st_release; elsif cur_env = X"FF" then next_state := st_decay; end if; if do_count_15='1' then next_env := cur_env + 1; -- if cur_env = X"FE" or cur_env = X"FF" then -- result could be FF, but also 00!! -- next_state := st_decay; -- end if; end if; when st_decay => if gate = '0' then next_state := st_release; end if; if do_count_15='1' and do_count_5='1' and std_logic_vector(cur_env) /= (sustain & sustain) and cur_env /= X"00" then next_env := cur_env - 1; end if; when st_release => if gate = '1' then next_state := st_attack; end if; if do_count_15='1' and do_count_5='1' and cur_env /= X"00" then next_env := cur_env - 1; end if; when others => next_state := st_release; end case; if enable_i='1' then state_array(0 to g_num_voices-2) <= state_array(1 to g_num_voices-1); state_array(g_num_voices-1) <= next_pre5 & next_pre15 & next_env & next_state; enveloppe <= next_env; state <= next_state; voice_x := to_integer(voice_i); voice_dbg(voice_x).state <= next_state; voice_dbg(voice_x).enveloppe <= next_env; voice_dbg(voice_x).pre15 <= next_pre15; voice_dbg(voice_x).pre5 <= next_pre5; voice_dbg(voice_x).presc <= presc_val; voice_dbg(voice_x).gate <= gate; voice_dbg(voice_x).attack <= attack; voice_dbg(voice_x).decay <= decay; voice_dbg(voice_x).sustain <= sustain; voice_dbg(voice_x).release <= release; end if; if reset='1' then state <= "00"; enveloppe <= (others => '0'); enable_o <= '0'; end if; end if; end process; end gideon;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/ip/busses/vhdl_bfm/slot_bus_master_bfm_pkg.vhd	5	5996	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library std; use std.textio.all; library work; use work.slot_bus_pkg.all; package slot_bus_master_bfm_pkg is type t_slot_bus_master_bfm_object; type p_slot_bus_master_bfm_object is access t_slot_bus_master_bfm_object; type t_slot_bus_bfm_command is ( e_slot_none, e_slot_io_read, e_slot_bus_read, e_slot_io_write, e_slot_bus_write ); type t_slot_bus_master_bfm_object is record next_bfm : p_slot_bus_master_bfm_object; name : string(1 to 256); command : t_slot_bus_bfm_command; poll_time : time; address : unsigned(15 downto 0); data : std_logic_vector(7 downto 0); irq_pending : boolean; end record; ------------------------------------------------------------------------------------ shared variable slot_bus_master_bfms : p_slot_bus_master_bfm_object := null; ------------------------------------------------------------------------------------ procedure register_slot_bus_master_bfm(named : string; variable pntr: inout p_slot_bus_master_bfm_object); procedure bind_slot_bus_master_bfm(named : string; variable pntr: inout p_slot_bus_master_bfm_object); ------------------------------------------------------------------------------------ procedure slot_io_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0)); procedure slot_io_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0)); procedure slot_bus_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0)); procedure slot_bus_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0)); procedure slot_wait_irq(variable m : inout p_slot_bus_master_bfm_object); end slot_bus_master_bfm_pkg; package body slot_bus_master_bfm_pkg is procedure register_slot_bus_master_bfm(named : string; variable pntr : inout p_slot_bus_master_bfm_object) is begin -- Allocate a new BFM object in memory pntr := new t_slot_bus_master_bfm_object; -- Initialize object pntr.next_bfm := null; pntr.name(named'range) := named; -- add this pointer to the head of the linked list if slot_bus_master_bfms = null then -- first entry slot_bus_master_bfms := pntr; else -- insert new entry pntr.next_bfm := slot_bus_master_bfms; slot_bus_master_bfms := pntr; end if; pntr.irq_pending := false; pntr.poll_time := 10 ns; end register_slot_bus_master_bfm; procedure bind_slot_bus_master_bfm(named : string; variable pntr : inout p_slot_bus_master_bfm_object) is variable p : p_slot_bus_master_bfm_object; begin pntr := null; wait for 1 ns; -- needed to make sure that binding takes place after registration p := slot_bus_master_bfms; -- start at the root L1: while p /= null loop if p.name(named'range) = named then pntr := p; exit L1; else p := p.next_bfm; end if; end loop; end bind_slot_bus_master_bfm; ------------------------------------------------------------------------------ procedure slot_bus_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0)) is variable a_i : unsigned(15 downto 0); begin a_i := (others => '0'); a_i(addr'length-1 downto 0) := addr; m.address := a_i; m.command := e_slot_bus_read; while m.command /= e_slot_none loop wait for m.poll_time; end loop; data := m.data; end procedure; procedure slot_io_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0)) is variable a_i : unsigned(15 downto 0); begin a_i := (others => '0'); a_i(addr'length-1 downto 0) := addr; m.address := a_i; m.command := e_slot_io_read; while m.command /= e_slot_none loop wait for m.poll_time; end loop; data := m.data; end procedure; procedure slot_bus_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0)) is variable a_i : unsigned(15 downto 0); begin a_i := (others => '0'); a_i(addr'length-1 downto 0) := addr; m.address := a_i; m.command := e_slot_bus_write; m.data := data; while m.command /= e_slot_none loop wait for m.poll_time; end loop; end procedure; procedure slot_io_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0)) is variable a_i : unsigned(15 downto 0); begin a_i := (others => '0'); a_i(addr'length-1 downto 0) := addr; m.address := a_i; m.command := e_slot_io_write; m.data := data; while m.command /= e_slot_none loop wait for m.poll_time; end loop; end procedure; procedure slot_wait_irq(variable m : inout p_slot_bus_master_bfm_object) is begin while not m.irq_pending loop wait for m.poll_time; end loop; end procedure; end; ------------------------------------------------------------------------------	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/sampler/vhdl_sim/sampler_tb.vhd	4	4560	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.io_bus_pkg.all; use work.mem_bus_pkg.all; use work.sampler_pkg.all; use work.io_bus_bfm_pkg.all; use work.tl_flat_memory_model_pkg.all; entity sampler_tb is end entity; architecture tb of sampler_tb is signal clock : std_logic := '0'; signal reset : std_logic; signal io_req : t_io_req; signal io_resp : t_io_resp; signal mem_req : t_mem_req; signal mem_resp : t_mem_resp; signal sample_L : signed(17 downto 0); signal sample_R : signed(17 downto 0); signal new_sample : std_logic; begin clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; i_dut: entity work.sampler generic map ( g_num_voices => 8 ) port map ( clock => clock, reset => reset, io_req => io_req, io_resp => io_resp, mem_req => mem_req, mem_resp => mem_resp, sample_L => sample_L, sample_R => sample_R, new_sample => new_sample ); i_io_bfm: entity work.io_bus_bfm generic map ( g_name => "io_bfm" ) port map ( clock => clock, req => io_req, resp => io_resp ); i_mem_bfm: entity work.mem_bus_slave_bfm generic map ( g_name => "mem_bfm", g_latency => 2 ) port map ( clock => clock, req => mem_req, resp => mem_resp ); test: process variable io : p_io_bus_bfm_object; variable mem : h_mem_object; variable d : std_logic_vector(7 downto 0); begin wait until reset='0'; bind_io_bus_bfm("io_bfm", io); bind_mem_model("mem_bfm", mem); for i in 0 to 255 loop d := std_logic_vector(to_signed(integer(127.0*sin(real(i) / 40.58451048843)), 8)); write_memory_8(mem, std_logic_vector(to_unsigned(16#1234500#+i, 32)), d); end loop; io_write(io, X"00" + c_sample_volume , X"3F"); io_write(io, X"00" + c_sample_pan , X"07"); io_write(io, X"00" + c_sample_start_addr_h , X"01"); io_write(io, X"00" + c_sample_start_addr_mh , X"23"); io_write(io, X"00" + c_sample_start_addr_ml , X"45"); io_write(io, X"00" + c_sample_start_addr_l , X"00"); io_write(io, X"00" + c_sample_length_h , X"00"); io_write(io, X"00" + c_sample_length_m , X"01"); io_write(io, X"00" + c_sample_length_l , X"00"); io_write(io, X"00" + c_sample_rate_h , X"00"); io_write(io, X"00" + c_sample_rate_l , X"18"); io_write(io, X"00" + c_sample_control , X"01"); io_write(io, X"10" + c_sample_volume , X"28"); io_write(io, X"10" + c_sample_pan , X"0F"); io_write(io, X"10" + c_sample_start_addr_h , X"01"); io_write(io, X"10" + c_sample_start_addr_mh , X"23"); io_write(io, X"10" + c_sample_start_addr_ml , X"45"); io_write(io, X"10" + c_sample_start_addr_l , X"00"); io_write(io, X"10" + c_sample_length_h , X"00"); io_write(io, X"10" + c_sample_length_m , X"01"); io_write(io, X"10" + c_sample_length_l , X"00"); io_write(io, X"10" + c_sample_rate_h , X"00"); io_write(io, X"10" + c_sample_rate_l , X"05"); io_write(io, X"10" + c_sample_control , X"03"); -- repeat on io_write(io, X"20" + c_sample_volume , X"38"); io_write(io, X"20" + c_sample_pan , X"04"); io_write(io, X"20" + c_sample_start_addr_h , X"01"); io_write(io, X"20" + c_sample_start_addr_mh , X"23"); io_write(io, X"20" + c_sample_start_addr_ml , X"45"); io_write(io, X"20" + c_sample_start_addr_l , X"00"); io_write(io, X"20" + c_sample_length_h , X"00"); io_write(io, X"20" + c_sample_length_m , X"00"); io_write(io, X"20" + c_sample_length_l , X"80"); io_write(io, X"20" + c_sample_rate_h , X"00"); io_write(io, X"20" + c_sample_rate_l , X"09"); io_write(io, X"20" + c_sample_control , X"13"); -- repeat on, 16 bit wait; end process; end architecture;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/ip/sync_fifo/vhdl_source/sync_fifo.vhd	4	5506	library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sync_fifo is generic ( g_depth : integer := 512; -- Actual depth. g_data_width : integer := 32; g_threshold : integer := 13; g_storage : string := "auto"; -- can also be "blockram" or "distributed" g_fall_through : boolean := false); port ( clock : in std_logic; reset : in std_logic; rd_en : in std_logic; wr_en : in std_logic; din : in std_logic_vector(g_data_width-1 downto 0); dout : out std_logic_vector(g_data_width-1 downto 0); flush : in std_logic; full : out std_logic; almost_full : out std_logic; empty : out std_logic; count : out integer range 0 to g_depth ); end sync_fifo; architecture rtl of sync_fifo is subtype t_data_element is std_logic_vector(g_data_width-1 downto 0); type t_data_array is array (0 to g_depth-1) of t_data_element; signal data_array : t_data_array; attribute ram_style : string; attribute ram_style of data_array : signal is g_storage; signal rd_data : std_logic_vector(g_data_width-1 downto 0); signal din_reg : std_logic_vector(g_data_width-1 downto 0); signal rd_inhibit : std_logic; signal rd_inhibit_d : std_logic; signal rd_en_flt : std_logic; signal rd_enable : std_logic; signal rd_pnt : integer range 0 to g_depth-1; signal rd_pnt_next : integer range 0 to g_depth-1; signal rd_index : integer range 0 to g_depth-1; signal wr_en_flt : std_logic; signal wr_pnt : integer range 0 to g_depth-1; signal num_el : integer range 0 to g_depth; begin -- Check generic values (also for synthesis) assert(g_threshold <= g_depth) report "Invalid parameter 'g_threshold'" severity failure; -- Filter fifo read/write enables for full/empty conditions rd_en_flt <= '1' when (num_el /= 0) and (rd_en='1') else '0'; wr_en_flt <= '1' when (num_el /= g_depth) and (wr_en='1') else '0'; -- Read enable depends on 'fall through' mode. In case fall through: prevent -- read & write at same address (when fifo is empty) rd_enable <= rd_en_flt when not(g_fall_through) else '0' when rd_inhibit = '1' else '1'; rd_inhibit <= '1' when rd_index = wr_pnt and wr_en_flt = '1' and g_fall_through else '0'; rd_index <= rd_pnt_next when g_fall_through and rd_en_flt = '1' and num_el /= 0 else rd_pnt; -- FIFO output data. Combinatoric switch to fix simultaneous read/write issues. dout <= din_reg when rd_inhibit_d = '1' else rd_data; p_dpram: process(clock) begin if rising_edge(clock) then if (wr_en_flt = '1') then data_array(wr_pnt) <= din; end if; if (rd_enable = '1') then rd_data <= data_array(rd_index); end if; end if; end process; rd_pnt_next <= 0 when (rd_pnt=g_depth-1) else rd_pnt + 1; process(clock) variable v_new_cnt : integer range 0 to g_depth; begin if (clock'event and clock='1') then rd_inhibit_d <= rd_inhibit; -- Modify read/write pointers if (rd_en_flt='1') then rd_pnt <= rd_pnt_next; end if; if (wr_en_flt='1') then -- Registered din is needed for BlockRAM based 'fall through' FIFO din_reg <= din; if (wr_pnt=g_depth-1) then wr_pnt <= 0; else wr_pnt <= wr_pnt + 1; end if; end if; -- Update number of elements in fifo for next clock cycle if (rd_en_flt = '1') and (wr_en_flt = '0') then v_new_cnt := num_el - 1; elsif (rd_en_flt = '0') and (wr_en_flt = '1') then v_new_cnt := num_el + 1; elsif (flush='1') then v_new_cnt := 0; else v_new_cnt := num_el; end if; num_el <= v_new_cnt; -- update (almost)full and empty indications almost_full <= '0'; if (v_new_cnt >= g_threshold) then almost_full <= '1'; end if; empty <= '0'; if (v_new_cnt = 0) then empty <= '1'; end if; full <= '0'; if (v_new_cnt = g_depth) then full <= '1'; end if; if (flush='1') or (reset='1') then rd_pnt <= 0; wr_pnt <= 0; num_el <= 0; rd_inhibit_d <= '0'; if (reset='1') then full <= '0'; empty <= '1'; almost_full <= '0'; end if; end if; end if; end process; count <= num_el; end rtl;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/mem_ctrl/vhdl_source/fpga_mem_test_v7.vhd	5	2933	------------------------------------------------------------------------------- -- Title : External Memory controller for SDRAM ------------------------------------------------------------------------------- -- Description: This module implements a simple, single burst memory controller. -- User interface is 16 bit (burst of 4), externally 8x 8 bit. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.mem_bus_pkg.all; entity fpga_mem_test_v7 is port ( CLOCK_50 : in std_logic; SDRAM_CLK : out std_logic; SDRAM_CKE : out std_logic; SDRAM_CSn : out std_logic := '1'; SDRAM_RASn : out std_logic := '1'; SDRAM_CASn : out std_logic := '1'; SDRAM_WEn : out std_logic := '1'; SDRAM_DQM : out std_logic := '0'; SDRAM_A : out std_logic_vector(14 downto 0); SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z'); MOTOR_LEDn : out std_logic; ACT_LEDn : out std_logic ); end fpga_mem_test_v7; architecture tb of fpga_mem_test_v7 is signal clock : std_logic := '1'; signal clk_2x : std_logic := '1'; signal reset : std_logic := '0'; signal inhibit : std_logic := '0'; signal is_idle : std_logic := '0'; signal req : t_mem_burst_32_req := c_mem_burst_32_req_init; signal resp : t_mem_burst_32_resp; signal okay : std_logic; begin i_clk: entity work.s3a_clockgen port map ( clk_50 => CLOCK_50, reset_in => '0', dcm_lock => open, sys_clock => clock, -- 50 MHz sys_reset => reset, sys_clock_2x => clk_2x ); i_checker: entity work.ext_mem_test_32 port map ( clock => clock, reset => reset, req => req, resp => resp, okay => ACT_LEDn ); i_mem_ctrl: entity work.ext_mem_ctrl_v7 generic map ( q_tcko_data => 5 ns, g_simulation => false ) port map ( clock => clock, clk_2x => clk_2x, reset => reset, inhibit => inhibit, is_idle => is_idle, req => req, resp => resp, SDRAM_CLK => SDRAM_CLK, SDRAM_CKE => SDRAM_CKE, SDRAM_CSn => SDRAM_CSn, SDRAM_RASn => SDRAM_RASn, SDRAM_CASn => SDRAM_CASn, SDRAM_WEn => SDRAM_WEn, SDRAM_DQM => SDRAM_DQM, SDRAM_BA => SDRAM_A(14 downto 13), SDRAM_A => SDRAM_A(12 downto 0), SDRAM_DQ => SDRAM_DQ ); MOTOR_LEDn <= 'Z'; end;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/usb2/vhdl_source/bridge_to_mem_ctrl.vhd	4	2777	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity bridge_to_mem_ctrl is port ( ulpi_clock : in std_logic; ulpi_reset : in std_logic; nano_addr : in unsigned(7 downto 0); nano_write : in std_logic; nano_wdata : in std_logic_vector(15 downto 0); -- cmd interface sys_clock : in std_logic; sys_reset : in std_logic; cmd_addr : out std_logic_vector(3 downto 0); cmd_valid : out std_logic; cmd_write : out std_logic; cmd_wdata : out std_logic_vector(15 downto 0); cmd_ack : in std_logic ); end entity; architecture gideon of bridge_to_mem_ctrl is signal fifo_data_in : std_logic_vector(19 downto 0); signal fifo_data_out : std_logic_vector(19 downto 0); signal fifo_get : std_logic; signal fifo_empty : std_logic; signal fifo_write : std_logic; signal cmd_data_out : std_logic_vector(19 downto 0); begin fifo_data_in <= std_logic_vector(nano_addr(3 downto 0)) & nano_wdata; fifo_write <= '1' when (nano_addr(7 downto 4)=X"7" and nano_write='1') else '0'; i_cmd_fifo: entity work.async_fifo generic map ( g_data_width => 20, g_depth_bits => 3, g_count_bits => 3, g_threshold => 3, g_storage => "distributed" ) port map ( -- write port signals (synchronized to write clock) wr_clock => ulpi_clock, wr_reset => ulpi_reset, wr_en => fifo_write, wr_din => fifo_data_in, wr_flush => '0', wr_count => open, wr_full => open, wr_almost_full => open, wr_error => open, wr_inhibit => open, -- read port signals (synchronized to read clock) rd_clock => sys_clock, rd_reset => sys_reset, rd_en => fifo_get, rd_dout => fifo_data_out, rd_count => open, rd_empty => fifo_empty, rd_almost_empty => open, rd_error => open ); i_ft: entity work.fall_through_add_on generic map ( g_data_width => 20) port map ( clock => sys_clock, reset => sys_reset, -- fifo side rd_dout => fifo_data_out, rd_empty => fifo_empty, rd_en => fifo_get, -- consumer side data_out => cmd_data_out, data_valid => cmd_valid, data_next => cmd_ack ); cmd_addr <= cmd_data_out(19 downto 16); cmd_wdata <= cmd_data_out(15 downto 0); cmd_write <= '1'; -- we don't support reads yet end architecture;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v4.vhd	5	9586	------------------------------------------------------------------------------- -- Title : External Memory controller for SDRAM (no burst) ------------------------------------------------------------------------------- -- Description: This module implements a simple, single access memory controller. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; library work; use work.mem_bus_pkg.all; entity ext_mem_ctrl_v4 is generic ( g_simulation : boolean := false; A_Width : integer := 15; SDRAM_WakeupTime : integer := 40; -- refresh periods SDRAM_Refr_period : integer := 375 ); port ( clock : in std_logic := '0'; clk_shifted : in std_logic := '0'; reset : in std_logic := '0'; inhibit : in std_logic; is_idle : out std_logic; req : in t_mem_req; resp : out t_mem_resp; SDRAM_CLK : out std_logic; SDRAM_CKE : out std_logic; SDRAM_CSn : out std_logic := '1'; SDRAM_RASn : out std_logic := '1'; SDRAM_CASn : out std_logic := '1'; SDRAM_WEn : out std_logic := '1'; SDRAM_DQM : out std_logic := '0'; MEM_A : out std_logic_vector(A_Width-1 downto 0); MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z')); end ext_mem_ctrl_v4; -- ADDR: 25 24 23 ... -- 0 X X ... SDRAM (32MB) architecture Gideon of ext_mem_ctrl_v4 is type t_init is record addr : std_logic_vector(15 downto 0); cmd : std_logic_vector(2 downto 0); -- we-cas-ras end record; type t_init_array is array(natural range <>) of t_init; constant c_init_array : t_init_array(0 to 7) := ( ( X"0400", "010" ), -- auto precharge ( X"0220", "000" ), -- mode register, burstlen=1, writelen=1, CAS lat = 2 ( X"0000", "001" ), -- auto refresh ( X"0000", "001" ), -- auto refresh ( X"0000", "001" ), -- auto refresh ( X"0000", "001" ), -- auto refresh ( X"0000", "001" ), -- auto refresh ( X"0000", "001" ) ); type t_state is (boot, init, idle, sd_cas, sd_wait); signal state : t_state; signal sram_d_o : std_logic_vector(MEM_D'range) := (others => '1'); signal sram_d_t : std_logic := '0'; signal delay : integer range 0 to 15; signal inhibit_d : std_logic; signal rwn_i : std_logic; signal tag : std_logic_vector(req.tag'range); signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0'); signal col_addr : std_logic_vector(9 downto 0) := (others => '0'); signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1; signal do_refresh : std_logic := '0'; signal not_clock : std_logic; signal reg_out : integer range 0 to 3 := 0; signal rdata_i : std_logic_vector(7 downto 0) := (others => '0'); signal dout_sel : std_logic := '0'; signal refr_delay : integer range 0 to 3; signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1; signal init_cnt : integer range 0 to c_init_array'high; signal enable_sdram : std_logic := '1'; signal req_i : std_logic; signal dack : std_logic; signal rack : std_logic; signal rack_tag : std_logic_vector(req.tag'range); signal dack_tag : std_logic_vector(req.tag'range); -- attribute fsm_encoding : string; -- attribute fsm_encoding of state : signal is "sequential"; -- attribute register_duplication : string; -- attribute register_duplication of mem_a_i : signal is "no"; attribute iob : string; attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB attribute iob of SDRAM_CKE : signal is "false"; begin is_idle <= '1' when state = idle else '0'; req_i <= req.request; resp.data <= rdata_i; resp.rack <= rack; resp.rack_tag <= rack_tag; resp.dack_tag <= dack_tag; process(clock) procedure send_refresh_cmd is begin do_refresh <= '0'; SDRAM_CSn <= '0'; SDRAM_RASn <= '0'; SDRAM_CASn <= '0'; SDRAM_WEn <= '1'; -- Auto Refresh refr_delay <= 3; end procedure; procedure accept_req is begin rack <= '1'; rack_tag <= req.tag; tag <= req.tag; rwn_i <= req.read_writen; sram_d_t <= '0'; --not req.read_writen; sram_d_o <= req.data; mem_a_i(12 downto 0) <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits mem_a_i(14 downto 13) <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits SDRAM_CSn <= '0'; SDRAM_RASn <= '0'; SDRAM_CASn <= '1'; SDRAM_WEn <= '1'; -- Command = ACTIVE sram_d_t <= '0'; -- no data yet delay <= 1; state <= sd_cas; end procedure; begin if rising_edge(clock) then rack <= '0'; dack <= '0'; rack_tag <= (others => '0'); dack_tag <= (others => '0'); dout_sel <= '0'; inhibit_d <= inhibit; rdata_i <= MEM_D; -- clock in SDRAM_CSn <= '1'; SDRAM_CKE <= enable_sdram; if refr_delay /= 0 then refr_delay <= refr_delay - 1; end if; case state is when boot => enable_sdram <= '1'; if refresh_cnt = 0 then boot_cnt <= boot_cnt - 1; if boot_cnt = 1 then state <= init; end if; elsif g_simulation then state <= idle; end if; when init => mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range); SDRAM_RASn <= c_init_array(init_cnt).cmd(0); SDRAM_CASn <= c_init_array(init_cnt).cmd(1); SDRAM_WEn <= c_init_array(init_cnt).cmd(2); if delay = 0 then delay <= 7; SDRAM_CSn <= '0'; if init_cnt = c_init_array'high then state <= idle; else init_cnt <= init_cnt + 1; end if; else delay <= delay - 1; end if; when idle => -- first cycle after inhibit goes 0, do not do refresh -- this enables putting cartridge images in sdram if do_refresh='1' and not (inhibit_d='1' or inhibit='1') then send_refresh_cmd; elsif inhibit='0' then if req_i='1' and refr_delay = 0 then accept_req; end if; end if; when sd_cas => mem_a_i(10) <= '1'; -- auto precharge mem_a_i(9 downto 0) <= col_addr; sram_d_t <= not rwn_i; -- enable for writes if delay = 0 then -- read or write with auto precharge SDRAM_CSn <= '0'; SDRAM_RASn <= '1'; SDRAM_CASn <= '0'; SDRAM_WEn <= rwn_i; if rwn_i='0' then -- write delay <= 2; else delay <= 2; end if; state <= sd_wait; else delay <= delay - 1; end if; when sd_wait => sram_d_t <= '0'; if delay=0 then if rwn_i = '1' then -- read dack <= '1'; dack_tag <= tag; end if; state <= idle; else delay <= delay - 1; end if; when others => null; end case; if refresh_cnt = SDRAM_Refr_period-1 then do_refresh <= '1'; refresh_cnt <= 0; else refresh_cnt <= refresh_cnt + 1; end if; if reset='1' then state <= boot; sram_d_t <= '0'; delay <= 0; tag <= (others => '0'); do_refresh <= '0'; boot_cnt <= SDRAM_WakeupTime-1; init_cnt <= 0; enable_sdram <= '1'; end if; end if; end process; MEM_D <= sram_d_o when sram_d_t='1' else (others => 'Z'); MEM_A <= mem_a_i; not_clock <= not clk_shifted; clkout: FDDRRSE port map ( CE => '1', C0 => clk_shifted, C1 => not_clock, D0 => '0', D1 => enable_sdram, Q => SDRAM_CLK, R => '0', S => '0' ); end Gideon;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/mem_ctrl/vhdl_sim/ext_mem_ctrl_v7_tb.vhd	5	10543	------------------------------------------------------------------------------- -- Title : External Memory controller for SDRAM ------------------------------------------------------------------------------- -- Description: This module implements a simple, single burst memory controller. -- User interface is 16 bit (burst of 4), externally 8x 8 bit. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.vital_timing.all; library work; use work.mem_bus_pkg.all; entity ext_mem_ctrl_v7_tb is end ext_mem_ctrl_v7_tb; architecture tb of ext_mem_ctrl_v7_tb is signal clock : std_logic := '1'; signal clk_2x : std_logic := '1'; signal reset : std_logic := '0'; signal inhibit : std_logic := '0'; signal is_idle : std_logic; signal req : t_mem_burst_32_req := c_mem_burst_32_req_init; signal resp : t_mem_burst_32_resp; signal SDRAM_CLK : std_logic; signal SDRAM_CKE : std_logic; signal SDRAM_CSn : std_logic := '1'; signal SDRAM_RASn : std_logic := '1'; signal SDRAM_CASn : std_logic := '1'; signal SDRAM_WEn : std_logic := '1'; signal SDRAM_DQM : std_logic := '0'; signal SDRAM_A : std_logic_vector(12 downto 0); signal SDRAM_BA : std_logic_vector(1 downto 0); signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z'); signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H'); signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H'); constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns ); begin clock <= not clock after 12 ns; clk_2x <= not clk_2x after 6 ns; reset <= '1', '0' after 100 ns; i_mut: entity work.ext_mem_ctrl_v7 generic map ( q_tcko_data => 5 ns, g_simulation => true ) port map ( clock => clock, clk_2x => clk_2x, reset => reset, inhibit => inhibit, is_idle => is_idle, req => req, resp => resp, SDRAM_CLK => SDRAM_CLK, SDRAM_CKE => SDRAM_CKE, SDRAM_CSn => SDRAM_CSn, SDRAM_RASn => SDRAM_RASn, SDRAM_CASn => SDRAM_CASn, SDRAM_WEn => SDRAM_WEn, SDRAM_DQM => SDRAM_DQM, SDRAM_BA => SDRAM_BA, SDRAM_A => SDRAM_A, SDRAM_DQ => SDRAM_DQ ); p_test: process procedure queue_req(rw : std_logic; bank : integer; row : integer; col : integer) is begin req.request <= '1'; req.read_writen <= rw; req.address <= to_unsigned(bank8192 + col8 + row*32768, req.address'length); wait for 2 ns; while resp.ready='0' loop wait until clock='1'; end loop; wait until clock='1'; req.request <= '0'; end procedure; begin req.read_writen <= '1'; -- read req.request <= '0'; req.address <= unsigned(to_signed(-32, req.address'length)); req.data_pop <= '0'; wait until reset='0'; wait until clock='1'; -- simple write / readback test queue_req('0', 0, 0, 0); queue_req('1', 0, 0, 0); while true loop -- read-read, other row, other bank queue_req('1', 0, 16, 127); queue_req('1', 1, 17, 0); -- read-read, other row, same bank queue_req('1', 1, 18, 1); -- read-read, same row, other bank queue_req('1', 2, 18, 2); -- read-read, same row, same bank queue_req('1', 2, 18, 3); -- read-write, other row, other bank queue_req('0', 0, 16, 4); -- read-write, other row, same bank queue_req('1', 0, 16, 127); queue_req('0', 0, 17, 5); -- read-write, same row, other bank queue_req('1', 0, 18, 127); queue_req('0', 1, 18, 6); -- read-write, same row, same bank queue_req('1', 2, 19, 127); queue_req('0', 2, 19, 7); -- write-read, other row, other bank queue_req('1', 3, 20, 8); -- write-read, other row, same bank queue_req('0', 0, 16, 127); queue_req('1', 0, 17, 9); -- write-read, same row, other bank queue_req('0', 1, 18, 127); queue_req('1', 2, 18, 10); -- write-read, same row, same bank queue_req('0', 3, 19, 127); queue_req('1', 3, 19, 11); -- write-write, other row, other bank queue_req('0', 0, 20, 127); queue_req('0', 1, 21, 12); -- write-write, other row, same bank queue_req('0', 1, 22, 13); -- write-write, same row, other bank queue_req('0', 2, 22, 14); -- write-write, same row, same bank queue_req('0', 2, 22, 15); -- read write toggle performance tests.. for i in 1 to 10 loop queue_req('1', 0, 0, i); queue_req('0', 1, 0, i); end loop; for i in 1 to 10 loop queue_req('1', 0, 0, i); queue_req('0', 0, 0, i); end loop; for i in 1 to 10 loop queue_req('1', 0, 0, i); queue_req('0', 0, 1, i); end loop; for i in 1 to 1000 loop queue_req('1', 0, 0, i); end loop; end loop; wait; end process; p_write: process(clock) variable v_data : unsigned(31 downto 0) := X"DEAD4001"; begin if rising_edge(clock) then if resp.wdata_full='0' and reset='0' then req.data_push <= '1'; req.data <= std_logic_vector(v_data); req.byte_en <= "0111"; v_data := v_data + 1; else req.data_push <= '0'; end if; end if; end process; i_sdram : entity work.mt48lc16m16a2 generic map( tipd_BA0 => c_wire_delay, tipd_BA1 => c_wire_delay, tipd_DQMH => c_wire_delay, tipd_DQML => c_wire_delay, tipd_DQ0 => c_wire_delay, tipd_DQ1 => c_wire_delay, tipd_DQ2 => c_wire_delay, tipd_DQ3 => c_wire_delay, tipd_DQ4 => c_wire_delay, tipd_DQ5 => c_wire_delay, tipd_DQ6 => c_wire_delay, tipd_DQ7 => c_wire_delay, tipd_DQ8 => c_wire_delay, tipd_DQ9 => c_wire_delay, tipd_DQ10 => c_wire_delay, tipd_DQ11 => c_wire_delay, tipd_DQ12 => c_wire_delay, tipd_DQ13 => c_wire_delay, tipd_DQ14 => c_wire_delay, tipd_DQ15 => c_wire_delay, tipd_CLK => c_wire_delay, tipd_CKE => c_wire_delay, tipd_A0 => c_wire_delay, tipd_A1 => c_wire_delay, tipd_A2 => c_wire_delay, tipd_A3 => c_wire_delay, tipd_A4 => c_wire_delay, tipd_A5 => c_wire_delay, tipd_A6 => c_wire_delay, tipd_A7 => c_wire_delay, tipd_A8 => c_wire_delay, tipd_A9 => c_wire_delay, tipd_A10 => c_wire_delay, tipd_A11 => c_wire_delay, tipd_A12 => c_wire_delay, tipd_WENeg => c_wire_delay, tipd_RASNeg => c_wire_delay, tipd_CSNeg => c_wire_delay, tipd_CASNeg => c_wire_delay, -- tpd delays tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ), tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ), -- -- tpw values: pulse widths -- tpw_CLK_posedge : VitalDelayType := UnitDelay; -- tpw_CLK_negedge : VitalDelayType := UnitDelay; -- -- tsetup values: setup times -- tsetup_DQ0_CLK : VitalDelayType := UnitDelay; -- -- thold values: hold times -- thold_DQ0_CLK : VitalDelayType := UnitDelay; -- -- tperiod_min: minimum clock period = 1/max freq -- tperiod_CLK_posedge : VitalDelayType := UnitDelay; -- mem_file_name => "none", tpowerup => 100 ns ) port map( BA0 => SDRAM_BA(0), BA1 => SDRAM_BA(1), DQMH => dummy_dqm(1), DQML => SDRAM_DQM, DQ0 => SDRAM_DQ(0), DQ1 => SDRAM_DQ(1), DQ2 => SDRAM_DQ(2), DQ3 => SDRAM_DQ(3), DQ4 => SDRAM_DQ(4), DQ5 => SDRAM_DQ(5), DQ6 => SDRAM_DQ(6), DQ7 => SDRAM_DQ(7), DQ8 => dummy_data(8), DQ9 => dummy_data(9), DQ10 => dummy_data(10), DQ11 => dummy_data(11), DQ12 => dummy_data(12), DQ13 => dummy_data(13), DQ14 => dummy_data(14), DQ15 => dummy_data(15), CLK => SDRAM_CLK, CKE => SDRAM_CKE, A0 => SDRAM_A(0), A1 => SDRAM_A(1), A2 => SDRAM_A(2), A3 => SDRAM_A(3), A4 => SDRAM_A(4), A5 => SDRAM_A(5), A6 => SDRAM_A(6), A7 => SDRAM_A(7), A8 => SDRAM_A(8), A9 => SDRAM_A(9), A10 => SDRAM_A(10), A11 => SDRAM_A(11), A12 => SDRAM_A(12), WENeg => SDRAM_WEn, RASNeg => SDRAM_RASn, CSNeg => SDRAM_CSn, CASNeg => SDRAM_CASn ); end;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/ip/memory/vhdl_source/dpram.vhd	5	3149	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity dpram is generic ( g_width_bits : positive := 16; g_depth_bits : positive := 9; g_read_first_a : boolean := false; g_read_first_b : boolean := false; g_storage : string := "auto" -- can also be "block" or "distributed" ); port ( a_clock : in std_logic; a_address : in unsigned(g_depth_bits-1 downto 0); a_rdata : out std_logic_vector(g_width_bits-1 downto 0); a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); a_en : in std_logic := '1'; a_we : in std_logic := '0'; b_clock : in std_logic := '0'; b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0'); b_rdata : out std_logic_vector(g_width_bits-1 downto 0); b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); b_en : in std_logic := '1'; b_we : in std_logic := '0' ); attribute keep_hierarchy : string; attribute keep_hierarchy of dpram : entity is "yes"; end entity; architecture xilinx of dpram is type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0); shared variable ram : t_ram := (others => (others => '0')); -- Xilinx and Altera attributes attribute ram_style : string; attribute ram_style of ram : variable is g_storage; begin ----------------------------------------------------------------------- -- PORT A ----------------------------------------------------------------------- p_port_a: process(a_clock) begin if rising_edge(a_clock) then if a_en = '1' then if g_read_first_a then a_rdata <= ram(to_integer(a_address)); end if; if a_we = '1' then ram(to_integer(a_address)) := a_wdata; end if; if not g_read_first_a then a_rdata <= ram(to_integer(a_address)); end if; end if; end if; end process; ----------------------------------------------------------------------- -- PORT B ----------------------------------------------------------------------- p_port_b: process(b_clock) begin if rising_edge(b_clock) then if b_en = '1' then if g_read_first_b then b_rdata <= ram(to_integer(b_address)); end if; if b_we = '1' then ram(to_integer(b_address)) := b_wdata; end if; if not g_read_first_b then b_rdata <= ram(to_integer(b_address)); end if; end if; end if; end process; end architecture;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/icap/vhdl_source/icap_pkg.vhd	5	312	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package icap_pkg is constant c_icap_fpga_type : unsigned(3 downto 0) := X"0"; constant c_icap_write : unsigned(3 downto 0) := X"4"; constant c_icap_pulse : unsigned(3 downto 0) := X"8"; end package;	gpl-3.0
JamesHyunKim/myhdl	tests/counter/testbench/counter_tb/vhdl/counter_tb.vhd	2	1403	---------------------------------------------------------- -- Design : Simple testbench for an 8-bit VHDL counter -- Author : Javier D. Garcia-Lasheras ---------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity counter_tb is -- entity declaration end counter_tb; ----------------------------------------------------------------------- architecture testbench of counter_tb is component counter port( clock: in std_logic; clear: in std_logic; count: in std_logic; Q: out std_logic_vector(7 downto 0) ); end component; signal t_clock: std_logic; signal t_clear: std_logic; signal t_count: std_logic; signal t_Q: std_logic_vector(7 downto 0); begin U_counter: counter port map (t_clock, t_clear, t_count, t_Q); process begin t_clock <= '0'; -- clock cycle is 10 ns wait for 5 ns; t_clock <= '1'; wait for 5 ns; end process; process begin t_clear <= '1'; -- start counting t_count <= '1'; wait for 50 ns; t_clear <= '0'; -- clear output wait for 1000 ns; report "Testbench of Adder completed successfully!" severity note; wait; end process; end testbench; ----------------------------------------------------------------	gpl-3.0
davidhorrocks/1541UltimateII	fpga/1541/vhdl_source/c1541_timing.vhd	4	2249	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity c1541_timing is port ( clock : in std_logic; reset : in std_logic; use_c64_reset : in std_logic; c64_reset_n : in std_logic; iec_reset_n : in std_logic; iec_reset_o : out std_logic; drive_stop : in std_logic; drv_clock_en : out std_logic; -- 1/12.5 (4 MHz) cpu_clock_en : out std_logic ); -- 1/50 (1 MHz) end c1541_timing; architecture Gideon of c1541_timing is signal div_cnt : unsigned(3 downto 0) := "0000"; signal pre_cnt : unsigned(1 downto 0) := "00"; signal cpu_clock_en_i : std_logic := '0'; signal toggle : std_logic := '0'; signal iec_reset_sh : std_logic_vector(0 to 2) := "000"; signal c64_reset_sh : std_logic_vector(0 to 2) := "000"; begin process(clock) begin if rising_edge(clock) then drv_clock_en <= '0'; cpu_clock_en_i <= '0'; if drive_stop='0' then if (div_cnt = X"B" and toggle='0') or (div_cnt = X"C" and toggle='1') then div_cnt <= X"0"; drv_clock_en <= '1'; toggle <= not toggle; pre_cnt <= pre_cnt + 1; if pre_cnt = "11" then cpu_clock_en_i <= '1'; end if; else div_cnt <= div_cnt + 1; end if; end if; if cpu_clock_en_i = '1' then iec_reset_sh(0) <= not iec_reset_n; iec_reset_sh(1 to 2) <= iec_reset_sh(0 to 1); c64_reset_sh(0) <= use_c64_reset and not c64_reset_n; c64_reset_sh(1 to 2) <= c64_reset_sh(0 to 1); end if; if reset='1' then toggle <= '0'; pre_cnt <= (others => '0'); div_cnt <= (others => '0'); end if; end if; end process; cpu_clock_en <= cpu_clock_en_i; iec_reset_o <= '1' when (iec_reset_sh="111") or (c64_reset_sh="111") else '0'; end Gideon;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/ip/busses/vhdl_bfm/slot_bus_master_bfm.vhd	5	2373	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.slot_bus_pkg.all; use work.slot_bus_master_bfm_pkg.all; entity slot_bus_master_bfm is generic ( g_name : string ); port ( clock : in std_logic; req : out t_slot_req; resp : in t_slot_resp ); end slot_bus_master_bfm; architecture bfm of slot_bus_master_bfm is shared variable this : p_slot_bus_master_bfm_object := null; signal bound : boolean := false; type t_state is (idle, exec); signal state : t_state := idle; signal delay : integer := 0; begin -- this process registers this instance of the bfm to the server package bind: process begin register_slot_bus_master_bfm(g_name, this); bound <= true; wait; end process; process(clock) begin if rising_edge(clock) then req.bus_write <= '0'; req.io_read <= '0'; req.io_write <= '0'; this.irq_pending := (resp.irq = '1'); case state is when idle => req <= c_slot_req_init; if bound then delay <= 3; if this.command /= e_slot_none then req.io_address <= this.address; req.bus_address <= this.address; req.data <= this.data; end if; case this.command is when e_slot_io_read => state <= exec; when e_slot_io_write => state <= exec; when e_slot_bus_read => state <= exec; when e_slot_bus_write => req.bus_write <= '1'; state <= exec; when others => null; end case; end if; when exec => if delay=0 then case this.command is when e_slot_io_read => req.io_read <= '1'; when e_slot_io_write => req.io_write <= '1'; when others => null; end case; if resp.reg_output='1' then this.data := resp.data; else this.data := (others => 'X'); end if; this.command := e_slot_none; state <= idle; else delay <= delay - 1; end if; when others => null; end case; end if; end process; end bfm;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/sigma_delta_dac/vhdl_sim/sine_osc_tb.vhd	5	931	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity sine_osc_tb is end sine_osc_tb; architecture tb of sine_osc_tb is signal clock : std_logic := '0'; signal reset : std_logic; signal sine : signed(15 downto 0); signal cosine : signed(15 downto 0); begin clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; osc: entity work.sine_osc port map ( clock => clock, reset => reset, sine => sine, cosine => cosine ); process variable n: time; variable p: integer; begin wait until reset='0'; n := now; while true loop wait until sine(15)='1'; p := (now - n) / 20 ns; n := now; report "Period: " & integer'image(p) & " samples" severity note; end loop; end process; end tb;	gpl-3.0
hanw/Open-Source-FPGA-Bitcoin-Miner	projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_status_flags_as.vhd	9	15251	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block kS5RyUqA0GEmQjNgWngWZVAacB7b+BQQcD6vmZxeLh0UFKV8v4e0wPlb9UEnetDuLG1UOtRsoWM+ JpY3jji2PQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block B7zNu769eR7bKWAGHj9/0eNDSGvXiqMj82G0EY6o/uh/SIFwA1KhTmzWtWnLu0Jp7RP5GNPk6sLY pX0/g+4u3yb3eGFjoMEUR7Xuyx+NxR236QDSWH4PQ8KaiWgTsqL4LXAaH8NNqk0FYEvapaZB1sh2 oBKwlNZSL5S4Jgt6Nnk= `protect key_keyowner = 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256) `protect key_block oCMO5tL93wlgNUGroUmDvsCr7HxeK09GoIfyiC3nD2bFXJlUFLliNDZIamCS4mHI4d6Rmtl58DMV 1VjKpBhEiVPJsul3pBINwh9W5fR3ySXWN7lVBV53GTKJ8/C1FDSTxhDoVwAPJSRLTuafgoj9B9Da zYWxK6QMpuRMbjQLMMOkg7Kvs8qRJ72+tkaE5YzIyfoyl5QufTJ+WdGO93hpTj9wz4RFqTLbyH7y iSbDe2jKNf/L4SMT8ygwfICbgBci+gaPo1wFfCgtrZhOzB5u1plII7x0F/IagztWEo/NlUkYpF0E FZ6GvcV+Et6/1qG+pSxYpyReQitneYmZbmeIPA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9552) `protect data_block EMB54fzb2m/ojBf5NEjDriNP+SdECfgqc38NJnAMI2f+v4q4WpG7EluA5kR1/etwwySfDdS2VvZs g56lDD6utmz9ihEvWiYFbAnAcDVKIFVCUDshyayz9LMw9iYVzJnjS+G/OehVtRMoapv0suSEbotq KSa9MBKwG49vlkIi6FPSFzvYjaowLPcbtGxyvcNzE7a6Wy3lUeNZpwyHt026FFIuD6OQ0iNTPIo+ yyWkJt7lwLL65wjUUnXXX+FGOKws24En1Pa+lDdFFnGEGZttfcdXlIQzKEhFOuzAqEeC9Rs+RrCK VL3Q6nxtCj0S9QBmUdMDugNvxQ9nF5OPpLTuqdBwwqcQLwRAWB/WT7u0cpL0lvw/HiQWgVm6e0ft ddUEvdyl70g91B7AiXDsrvMad3aNn4B1ae9cHxavZWHuNOyRuFH7LBHg8eP/VbyaBRgHDQHoS5am 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Project-Bonfire/EHA	RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/ParityChecker_for_LBDR.vhd	9	681	--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; entity parity_checker_for_LBDR is generic(DATA_WIDTH : integer := 32); port( RX: in std_logic_vector(DATA_WIDTH-1 downto 0); empty: in std_logic; faulty: out std_logic ); end parity_checker_for_LBDR; architecture behavior of parity_checker_for_LBDR is signal xor_all: std_logic; begin process(empty, RX) begin if empty = '0' then xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1)); else xor_all <= '0'; end if; end process; process(RX, xor_all)begin faulty <= '0'; if xor_all /= RX(0) then faulty <= '1'; end if; end process; end;	gpl-3.0
hanw/Open-Source-FPGA-Bitcoin-Miner	projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_axi_write_wrapper.vhd	9	65399	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Ay7yUo344MX/HpMjaa/BfEnxojenX57nfZN9+kMuLNQKkNFQNMwwKXWYirwn8AeviwFh8Ye8bBwr 07jpMsc3Ww== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block GtKHFr1bTEO3BDZPZ8B11z5mN8Sou0TY2F19SmGWFzX1kEzsWibDjneI2l/UloaSNmCpkBvA5It+ 3v5N0cX3jTFQb6WArjXcGBdkY+96yJsuL/xjolKd2zK29DYDPjWDcqAAYun1mT7vy+P/RlE+qcEV 8d59OQmsYNVgHec5WPI= `protect key_keyowner = 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256) `protect key_block HMC1xZTYCW9uKI/iOVB+HbW1Fk8igaZ0GW4GX10ep8GryNiF3nTt2tXE6SAQBlcnwq8dGFEuZIEa 78S7xWlsTIkfalU5gV8iQUgF9QGTvFWvNcqZp4IFp1M92HcBKD6UyYOR4IE2Iet+H4n1TdbexufL rd/lEOWR1yTOyh91DoLfuWiPbO2tz0PONLRCkt9aIqO2UrRCYB1XERLzis7XV8vWUUDMhnEBkOCn 8OZTCAyyhyiZ5qX3NuWAI2jizuNFR59tUtVbEvgPhtvazz+Yd8Dn3eTNVyTQLCl3UjkDec3TmPW6 8+jBfuHbkDVmjmD4n4EoAlCcxXCv1+w1Ny1A5Q== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 46672) `protect data_block wpzK0ZYQ2FQI97GHW5mbVEX5542GwUa8gcBfWbo9AJztFVn7RL//rT36Q0fg3I7WJ6oj46fHLL+O 07OPbOKxkI8VvsSJkbc6Su4FSkH/b6uQXddNshKgWU0udrnlZx6p9x9T5reuD7EJeGHqIkOIiyhw //ismLzEN1stk0/jtSe7iQRkpDfMD5sh0HiSx0jcoNevOqu1i8wFFPiJnUcves9gEU+Yw+Xi+q8X Tqw97R4KlvjoudMaw/kSPwBhzLAR0n9S397vC1qR8DESc8JTa4Ls48D+CKPKk1s4CXU60kS4vQBj Y/sd2yIuXqeI5RjIDOpKnDDN7Z95s+ysp6CqthLGMElD+G1RgySSJP9pxLfXJoqHdAxSAbmy9EDk GVP4c1hsRRemcUtmOwZXE5+jVjRNWHWYHs9yLl0Za8URqOKaMoJ3R7h4Lsw9+3yT1mFBt8And6mz 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julioamerico/prj_crc_ip	src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@a@c@e_@p@p@e_@d@p@r@a@m/_primary.vhd	3	1382	library verilog; use verilog.vl_types.all; entity F2DSS_ACE_PPE_DPRAM is port( CLKA : in vl_logic; CSBA : in vl_logic; RWBA : in vl_logic; AA : in vl_logic_vector(8 downto 0); DIA : in vl_logic_vector(31 downto 0); DOA : out vl_logic_vector(31 downto 0); CLKB : in vl_logic; CSBB : in vl_logic; RWBB : in vl_logic; AB : in vl_logic_vector(8 downto 0); DIB : in vl_logic_vector(31 downto 0); DOB : out vl_logic_vector(31 downto 0); TEST_MODE : in vl_logic; RB_TEST : in vl_logic; RB_CSBA : in vl_logic; RB_CSBB : in vl_logic; RB_RWBA : in vl_logic; RB_RWBB : in vl_logic; RB_ADA : in vl_logic_vector(8 downto 0); RB_ADB : in vl_logic_vector(8 downto 0); RB_WDA : in vl_logic_vector(31 downto 0); RB_WDB : in vl_logic_vector(31 downto 0); RB_RDA : out vl_logic_vector(31 downto 0); RB_RDB : out vl_logic_vector(31 downto 0) ); end F2DSS_ACE_PPE_DPRAM;	gpl-3.0
hanw/Open-Source-FPGA-Bitcoin-Miner	projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo16_patch/input_block_fifo16_patch.vhd	9	15036	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block a72d+j/QkZDkv8eDO5pA9BEngzdbQGQHhuxY2nDNAEhnIoRf0SgDQdLQUGAjqTT/LgQ/F0Cs+16w c1P7TVYYIQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block l/1IXczTwKQBVElHEsh+Zvo7KblkXaJxo8UlygCcRw3ZY3tWBi5BiOQVA9yqXhof3R4G5ULkurKn 46GuEoIAY3OUXtbKoFE/fg9ET9kDVkPf1jISgRyi7rAeyld9i/Cbc18E0R0zSIcXYm0KkBSXRMxF 9wuwdCtkYN244/gGxpo= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block l2DcCPLVR8IEoJU3RMy+SjLkstHNjHjhsTPyvJyG55CosrmHYPJF1hv5Q2QL/s+a8qVVv/FshWre ZhgfOLKwFsPfAotMElv4nD87vdWuiTfoT02uJ3qo+dMgqdK1NTGcrQz44sHgvLPLWzKe7hlF6k6o Rvf27QkEmCc2RIz/44tOQ/UppDCnrsrSVyntb+a+7BW1A9KnQCNSmFmxGUvHpVhP12cJTZtxVJbJ Gqk5MrAj6sMn7uGnVNgQNANDDB+DZgaG/rX6HKpInZYt8BzBk6ItkozY9t3z7oLm8gSHD9yIsJBO 9AMq0Li5R/GGkBoyk8LpfwkWqntHfUWm0bnNZg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block DjQz1cDtlzfTydRyrY+CZqTPGwZEHHaCGldw1iTUBh5QfXaAiR1uKl2S9PniOeC/cvZgRRDpmcaN zNVXhjOeHU3dnRVJvgmKq3SSiJA7PuJ5iq48dVkI+PqLpzJqKub/4QXlIW2D3K0jO9cEZznt4pz4 zGK6KgjZ7aPbC7aR/LU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block cCj1sFiXTorUE6cijFjReKgoLQpZZhe3m8TlSV9f5LlFUKu+l0WXSJg/leWTQZO2OtLniO0g6v1X Q3rtBRwm8GhMcNcwV8oh3DFFtIhPAWIx8pc1IWS1flBcINGtXYVzaV9N47/Rfvj7bD/mJLL+3Y8M w37oj3YyxkZJ4Qw01CkXNmjP9Jdaf9l8rl9mPrRqfpwkMT2Wu3jRZhr19CZISAVqAU1dUMwyXjha uuLdqvOh9S6lQlkmMyjmEIKbqZUMj9jqGdqIEgihmrcRH4TEim8XRv6avaaNKbCDz4oCy/pt1FkK 6Op5z2R8h8lf36/aCuM+cJu5Sxegm18sIBuy1w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9392) `protect data_block VvIw3u4z644M9oCnXrN11AFyy7KcxZsZdyLbnBx3LqVMsNcmmsh1iowZ5ub3Cw5awQgWRQ7wnJ1Z BFJWLXjtihrCL6nd2ENzmEtmUjzQroqjkhWIhGczCePlbDZGh+xle1VT1ImwLIHiJX2U7Vg1xQOz rxEV+8WYJtP7X80ztNSsy8Z+wRQnNeNHz2UBN08bcEd8nr0bVgWmJNpOGVz6/MihqxlHNXdZuS35 iiiCwUClBpNi/pVXiEyw00gmNhN/pys+TsAZJ0hVVwH1tdgqXQPQ2q0mPdIjOhQ3CGb4FtveZq0C d7qo04frJZMQ8OoaCLzu6EyWNQUjqAJUw8nPEMG39SHNyK7PRLdEEXg+AoLmHY9WaVGf/FgZppDK cpwuLLRukVN7yyJkZ1Fgh+ixcPoaiKjebdS9mlZvXKyquMxa9EbvJllsgghk0KzVjfLD37ERzOJf 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meaepeppe/FIR_ISA	VHDL/FIR_filter.vhd	1	4881	LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE ieee.math_real.all; USE work.FIR_constants.all; ENTITY FIR_filter IS PORT( CLK, RST_n: IN STD_LOGIC; VIN: IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); Coeffs: IN STD_LOGIC_VECTOR(((Ord+1)Nb)-1 DOWNTO 0); --# of coeffs IS Ord+1 VOUT: OUT STD_LOGIC; DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0) ); END ENTITY; ARCHITECTURE beh_fir OF FIR_filter IS TYPE sum_array IS ARRAY (Ord DOWNTO 0) OF STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0); TYPE sig_array IS ARRAY (Ord DOWNTO 0) OF STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); SIGNAL Bi: sig_array; -- there IS Ord instead of Ord-1 becaUSE the coeffs are Ord+1 SIGNAL REG_OUT_array: sig_array; SIGNAL SUM_OUT_array: sum_array; SIGNAL VIN_delay_line: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL Coeffs_delayed: STD_LOGIC_VECTOR(((Ord+1)Nb)-1 DOWNTO 0); SIGNAL DIN_mult: STD_LOGIC_VECTOR(2Nb-1 DOWNTO 0); SIGNAL mult_ext: STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0); COMPONENT Cell IS PORT( CLK, RST_n, EN : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); SUM_IN: IN STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0); Bi: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); REG_OUT : OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); ADD_OUT: OUT STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0) -- aggiunti 9 bit di guardia ); END COMPONENT; COMPONENT Reg_n IS GENERIC(Nb: INTEGER :=9); PORT( CLK, RST_n, EN: IN STD_LOGIC; DIN: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0) ); END COMPONENT; COMPONENT mult_n IS GENERIC( Nb: INTEGER := 9 ); PORT( in_a: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); in_b: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); mult_out: OUT STD_LOGIC_VECTOR(2Nb-1 DOWNTO 0) ); END COMPONENT; BEGIN ----------------------------------------------------------- ------------------------ Input Buffers -------------------- In_buffers_1: IF IO_buffers GENERATE VIN_delay_line(0) <= VIN; data_in_reg: Reg_n GENERIC MAP (Nb => Nb) PORT MAP ( CLK => CLK, RST_n => RST_n, EN => VIN, DIN => DIN, DOUT => REG_OUT_array(0) ); Coeffs_in_reg: Reg_n GENERIC MAP (Nb => ((Ord+1)Nb)) PORT MAP ( CLK => CLK, RST_n => RST_n, EN => VIN, DIN => Coeffs, DOUT => Coeffs_delayed ); VIN_in_reg: Reg_n GENERIC MAP (Nb => 1) PORT MAP ( CLK => CLK, RST_n => RST_n, EN => '1', DIN => VIN_delay_line(0 DOWNTO 0), DOUT => VIN_delay_line(1 DOWNTO 1) ); END GENERATE; In_buffers_0: IF NOT(IO_buffers) GENERATE Coeffs_delayed <= Coeffs; REG_OUT_array(0) <= DIN; VIN_delay_line(1) <= VIN; END GENERATE; -------------------------------------------------------------- ------------------------ First Multiplier -------------------- Coeff_gen: FOR i IN 0 to Ord GENERATE Bi(i) <= Coeffs_delayed(((i+1)Nb)-1 DOWNTO (i*Nb)); END GENERATE; DIN_mult_gen: mult_n GENERIC MAP(Nb => Nb) PORT MAP ( in_a => REG_OUT_array(0), in_b => Bi(0), mult_out => DIN_mult ); DIN_mult_extension_0: IF (Nbadder <= Nbmult) GENERATE mult_ext <= DIN_mult((DIN_mult'LENGTH - (Nbmult - Nbadder) -1) DOWNTO (DIN_mult'LENGTH)-1-(Nbmult-1)); END GENERATE; DIN_mult_extension_1: IF (Nbadder > Nbmult) GENERATE mult_ext(Nbmult-1 DOWNTO 0)<= DIN_mult((DIN_mult'LENGTH -1) DOWNTO ((DIN_mult'LENGTH)-1-(Nbmult-1)) ); mult_ext(Nbadder-1 DOWNTO Nbmult) <= (OTHERS => mult_ext(Nbmult-1)); END GENERATE; SUM_OUT_array(0) <= mult_ext; ------------------------------------------------------------- ------------------------ Matrix of Cells -------------------- Cells_gen: FOR j IN 0 to Ord-1 GENERATE Single_cell: Cell PORT MAP ( CLK => CLK, RST_n => RST_n, EN => VIN_delay_line(1), DIN => REG_OUT_array(j), SUM_IN => SUM_OUT_array(j), Bi => Bi(j+1), REG_OUT => REG_OUT_array(j+1), ADD_OUT => SUM_OUT_array(j+1) ); END GENERATE; ----------------------------------------------------------- ----------------------- Output Buffers -------------------- Out_buffers_1: IF IO_buffers GENERATE data_out_reg: Reg_n GENERIC MAP (Nb => Nb) PORT MAP ( CLK => CLK, RST_n => RST_n, EN => VIN_delay_line(1), DIN => SUM_OUT_array(Ord)(Nb-1 DOWNTO 0), DOUT => DOUT ); VIN_out_reg: Reg_n GENERIC MAP (Nb => 1) PORT MAP ( CLK => CLK, RST_n => RST_n, EN => '1', DIN => VIN_delay_line(1 DOWNTO 1), DOUT => VIN_delay_line(2 DOWNTO 2) ); VOUT <= VIN_delay_line(2); END GENERATE; Out_buffers_0: IF NOT(IO_buffers) GENERATE DOUT <= SUM_OUT_array(Ord)(Nb-1 DOWNTO 0); VOUT <= VIN; END GENERATE; END beh_fir;	gpl-3.0
hanw/Open-Source-FPGA-Bitcoin-Miner	projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_status_flags_ss.vhd	9	17955	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block f2+u8rrKz+aRj2l97hS/lgQYsNHnPNXGUhkhHOtp35Q1MZZbGQ/InkVJ9iM99NSrspoaaHjQ8YbX RBsHYdSqRg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block RHoEjL1eMTFznVV16U9m20PUhZfShaTI/uXl3wndj38r/6kf4mlAyxDMEl3a69bnOJrNsrUlhJOP 7T961sKqAatosnanTctgWqebY0w/xnFcoHWaY+FkgOil7Jf5fsi2RdBRqiwB1mga+89dNGjNvsr1 MFLz6HnG5RFmCwPK5VI= `protect key_keyowner = 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256) `protect key_block KSbKYK1S/TunYdw+Z+kzk7bOuAFWgrxZ3D4/AwHbTt7U+4nRhRnL+GS+YxFGzIrGqIgBchZA5rDf 3yivmzsJJgD+M7mbH64DEaTqM9l7Ya7wyEZ7e0O975v9baKCG2kg1duJDwbh6h3AjL7mWT8+UUM2 p/zO/nhfjf7vRI1dNJEMEolnvUpT3dyt3SaVa5Lzs8qSx3oopl14iLO/v06IlQY1wNZvSJGFzjCI xz4asUemg1SX1/UHrl3lDYzXKWFV2OCfhDXz9VGxYV/wO9b6JnRzOndZroKfg1oehFUmN7zteu9L sZRN51atDolmOLf3hKO51qva8oK6MmvfDkSIJQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11552) `protect data_block P79w0YVbuzBvOaqJNymjZs6O5mlDxSv6DVmKrRmhIcYWT1pLlm5H3FtaHN3tBype7hkyq0AoTyA5 veK5JE0LlzJ56u5Uv3OD+GYvgMlW5SHTLZr02lfT+31/NQnYx7x3//msJUmpcqKj/5qKwPUrmdzp 89LK9yiwUvNc8d2E+Sr3PKzXir8fz/luPwVz4qoigH0Ib/EeOvth8E1eO0lHyu8YOEaEs63r3iW3 1IFHwtzk5jWUYlZo+vSMxkvRH3uKhjVU5He3qR1nfSRzDXW0RxCluxXI+vvtC5yq+daMU1n3rXyt CTfLFao+BicLXdxaCAe62w49xXEuTYxIWMJdpIsnPMtttyfe1mk90pV8VFypceg/1dK0fskLrKAH vIaMZBrKrsTVA3K3ZeA74NT7tyZaB/cKuPOK5FCJrjfMvPTzFN45raH4VE/2hil4mNy8mA3rDLqm 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nickg/nvc

test/jit/proc1.vhd

1

1066

package proc1_pack0 is procedure add_n (x : inout integer; n : in integer); end package; package body proc1_pack0 is procedure add_n (x : inout integer; n : in integer) is begin if x = 10 then wait for 1 ns; else x := x + n; end if; end procedure; end package body; ------------------------------------------------------------------------------- package proc1_pack1 is procedure add1 (x : inout integer); end package; use work.proc1_pack0.all; package body proc1_pack1 is procedure add1 (x : inout integer) is begin add_n(x, 1); end procedure; end package body; ------------------------------------------------------------------------------- package proc1_pack2 is function add2 (x : integer) return integer; end package; use work.proc1_pack1.all; package body proc1_pack2 is function add2 (x : integer) return integer is variable r : integer := x; begin add1(r); add1(r); return r; end function; end package body;

gpl-3.0

nickg/nvc

test/regress/comp1.vhd

5

707

entity comp1_bot is port ( x : in integer; y : out integer ); end entity; architecture rtl of comp1_bot is begin y <= x + 1; end architecture; ------------------------------------------------------------------------------- entity comp1 is end entity; architecture rtl of comp1 is signal a, b : integer; component comp1_bot is port ( x : in integer; y : out integer ); end component; begin c1: component comp1_bot port map ( 1, a ); c2: comp1_bot port map ( 2, b ); process is begin wait for 1 ns; assert a = 2; assert b = 3; wait; end process; end architecture;

gpl-3.0

nickg/nvc

test/regress/bounds18.vhd

1

609

entity bounds18 is end entity; architecture test of bounds18 is function func(x : bit_vector(1 to 5)) return bit is begin return x(1) and x(5); end function; procedure proc(n : positive) is variable v : bit_vector(1 to n); begin assert func(v) = '0'; end procedure; begin process is variable v : bit_vector(1 to 4); begin --assert func(v) = '0'; -- Caught during analysis proc(5); -- OK proc(3); -- Failure here wait; end process; end architecture;

gpl-3.0

Darkin47/Zynq-TX-UTT

Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_register_s2mm.vhd

3

174357

-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_register_s2mm.vhd -- -- Description: This entity encompasses the channel register set. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_9; use axi_dma_v7_1_9.axi_dma_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_register_s2mm is generic( C_NUM_REGISTERS : integer := 11 ; C_INCLUDE_SG : integer := 1 ; C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ; C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ; C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ; C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ; C_MICRO_DMA : integer range 0 to 1 := 0 ; C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0 --C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034 ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- AXI Interface Control -- axi2ip_wrce : in std_logic_vector -- (C_NUM_REGISTERS-1 downto 0) ; -- axi2ip_wrdata : in std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- -- -- DMASR Control -- stop_dma : in std_logic ; -- halted_clr : in std_logic ; -- halted_set : in std_logic ; -- idle_set : in std_logic ; -- idle_clr : in std_logic ; -- ioc_irq_set : in std_logic ; -- dly_irq_set : in std_logic ; -- irqdelay_status : in std_logic_vector(7 downto 0) ; -- irqthresh_status : in std_logic_vector(7 downto 0) ; -- irqthresh_wren : out std_logic ; -- irqdelay_wren : out std_logic ; -- dlyirq_dsble : out std_logic ; -- CR605888 -- -- Error Control -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- ftch_interr_set : in std_logic ; -- ftch_slverr_set : in std_logic ; -- ftch_decerr_set : in std_logic ; -- ftch_error_addr : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_interr_set : in std_logic ; -- updt_slverr_set : in std_logic ; -- updt_decerr_set : in std_logic ; -- updt_error_addr : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- error_in : in std_logic ; -- error_out : out std_logic ; -- introut : out std_logic ; -- soft_reset_in : in std_logic ; -- soft_reset_clr : in std_logic ; -- -- -- CURDESC Update -- update_curdesc : in std_logic ; -- tdest_in : in std_logic_vector (5 downto 0) ; new_curdesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- -- TAILDESC Update -- tailpntr_updated : out std_logic ; -- -- -- Channel Register Out -- sg_ctl : out std_logic_vector (7 downto 0) ; dmacr : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- dmasr : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc1_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc1_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc1_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc1_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc2_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc2_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc2_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc2_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc3_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc3_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc3_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc3_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc4_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc4_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc4_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc4_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc5_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc5_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc5_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc5_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc6_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc6_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc6_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc6_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc7_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc7_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc7_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc7_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc8_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc8_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc8_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc8_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc9_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc9_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc9_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc9_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc10_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc10_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc10_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc10_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc11_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc11_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc11_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc11_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc12_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc12_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc12_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc12_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc13_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc13_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc13_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc13_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc14_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc14_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc14_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc14_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc15_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc15_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc15_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc15_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- buffer_address : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0); -- buffer_length : out std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- buffer_length_wren : out std_logic ; -- bytes_received : in std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- bytes_received_wren : in std_logic -- ); -- end axi_dma_register_s2mm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_register_s2mm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- constant SGCTL_INDEX : integer := 0; constant DMACR_INDEX : integer := 1; -- DMACR Register index constant DMASR_INDEX : integer := 2; -- DMASR Register index constant CURDESC_LSB_INDEX : integer := 3; -- CURDESC LSB Reg index constant CURDESC_MSB_INDEX : integer := 4; -- CURDESC MSB Reg index constant TAILDESC_LSB_INDEX : integer := 5; -- TAILDESC LSB Reg index constant TAILDESC_MSB_INDEX : integer := 6; -- TAILDESC MSB Reg index constant CURDESC1_LSB_INDEX : integer := 17; -- CURDESC LSB Reg index constant CURDESC1_MSB_INDEX : integer := 18; -- CURDESC MSB Reg index constant TAILDESC1_LSB_INDEX : integer := 19; -- TAILDESC LSB Reg index constant TAILDESC1_MSB_INDEX : integer := 20; -- TAILDESC MSB Reg index constant CURDESC2_LSB_INDEX : integer := 25; -- CURDESC LSB Reg index constant CURDESC2_MSB_INDEX : integer := 26; -- CURDESC MSB Reg index constant TAILDESC2_LSB_INDEX : integer := 27; -- TAILDESC LSB Reg index constant TAILDESC2_MSB_INDEX : integer := 28; -- TAILDESC MSB Reg index constant CURDESC3_LSB_INDEX : integer := 33; -- CURDESC LSB Reg index constant CURDESC3_MSB_INDEX : integer := 34; -- CURDESC MSB Reg index constant TAILDESC3_LSB_INDEX : integer := 35; -- TAILDESC LSB Reg index constant TAILDESC3_MSB_INDEX : integer := 36; -- TAILDESC MSB Reg index constant CURDESC4_LSB_INDEX : integer := 41; -- CURDESC LSB Reg index constant CURDESC4_MSB_INDEX : integer := 42; -- CURDESC MSB Reg index constant TAILDESC4_LSB_INDEX : integer := 43; -- TAILDESC LSB Reg index constant TAILDESC4_MSB_INDEX : integer := 44; -- TAILDESC MSB Reg index constant CURDESC5_LSB_INDEX : integer := 49; -- CURDESC LSB Reg index constant CURDESC5_MSB_INDEX : integer := 50; -- CURDESC MSB Reg index constant TAILDESC5_LSB_INDEX : integer := 51; -- TAILDESC LSB Reg index constant TAILDESC5_MSB_INDEX : integer := 52; -- TAILDESC MSB Reg index constant CURDESC6_LSB_INDEX : integer := 57; -- CURDESC LSB Reg index constant CURDESC6_MSB_INDEX : integer := 58; -- CURDESC MSB Reg index constant TAILDESC6_LSB_INDEX : integer := 59; -- TAILDESC LSB Reg index constant TAILDESC6_MSB_INDEX : integer := 60; -- TAILDESC MSB Reg index constant CURDESC7_LSB_INDEX : integer := 65; -- CURDESC LSB Reg index constant CURDESC7_MSB_INDEX : integer := 66; -- CURDESC MSB Reg index constant TAILDESC7_LSB_INDEX : integer := 67; -- TAILDESC LSB Reg index constant TAILDESC7_MSB_INDEX : integer := 68; -- TAILDESC MSB Reg index constant CURDESC8_LSB_INDEX : integer := 73; -- CURDESC LSB Reg index constant CURDESC8_MSB_INDEX : integer := 74; -- CURDESC MSB Reg index constant TAILDESC8_LSB_INDEX : integer := 75; -- TAILDESC LSB Reg index constant TAILDESC8_MSB_INDEX : integer := 76; -- TAILDESC MSB Reg index constant CURDESC9_LSB_INDEX : integer := 81; -- CURDESC LSB Reg index constant CURDESC9_MSB_INDEX : integer := 82; -- CURDESC MSB Reg index constant TAILDESC9_LSB_INDEX : integer := 83; -- TAILDESC LSB Reg index constant TAILDESC9_MSB_INDEX : integer := 84; -- TAILDESC MSB Reg index constant CURDESC10_LSB_INDEX : integer := 89; -- CURDESC LSB Reg index constant CURDESC10_MSB_INDEX : integer := 90; -- CURDESC MSB Reg index constant TAILDESC10_LSB_INDEX : integer := 91; -- TAILDESC LSB Reg index constant TAILDESC10_MSB_INDEX : integer := 92; -- TAILDESC MSB Reg index constant CURDESC11_LSB_INDEX : integer := 97; -- CURDESC LSB Reg index constant CURDESC11_MSB_INDEX : integer := 98; -- CURDESC MSB Reg index constant TAILDESC11_LSB_INDEX : integer := 99; -- TAILDESC LSB Reg index constant TAILDESC11_MSB_INDEX : integer := 100; -- TAILDESC MSB Reg index constant CURDESC12_LSB_INDEX : integer := 105; -- CURDESC LSB Reg index constant CURDESC12_MSB_INDEX : integer := 106; -- CURDESC MSB Reg index constant TAILDESC12_LSB_INDEX : integer := 107; -- TAILDESC LSB Reg index constant TAILDESC12_MSB_INDEX : integer := 108; -- TAILDESC MSB Reg index constant CURDESC13_LSB_INDEX : integer := 113; -- CURDESC LSB Reg index constant CURDESC13_MSB_INDEX : integer := 114; -- CURDESC MSB Reg index constant TAILDESC13_LSB_INDEX : integer := 115; -- TAILDESC LSB Reg index constant TAILDESC13_MSB_INDEX : integer := 116; -- TAILDESC MSB Reg index constant CURDESC14_LSB_INDEX : integer := 121; -- CURDESC LSB Reg index constant CURDESC14_MSB_INDEX : integer := 122; -- CURDESC MSB Reg index constant TAILDESC14_LSB_INDEX : integer := 123; -- TAILDESC LSB Reg index constant TAILDESC14_MSB_INDEX : integer := 124; -- TAILDESC MSB Reg index constant CURDESC15_LSB_INDEX : integer := 129; -- CURDESC LSB Reg index constant CURDESC15_MSB_INDEX : integer := 130; -- CURDESC MSB Reg index constant TAILDESC15_LSB_INDEX : integer := 131; -- TAILDESC LSB Reg index constant TAILDESC15_MSB_INDEX : integer := 132; -- TAILDESC MSB Reg index -- CR603034 moved s2mm back to offset 6 --constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA) --constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA) -- -- --constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA) -- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx -- SA_ADDRESS_INDEX, -- Source Address Index -- DA_ADDRESS_INDEX); -- Destination Address Index constant BUFF_ADDRESS_INDEX : integer := 7; constant BUFF_ADDRESS_MSB_INDEX : integer := 8; constant BUFF_LENGTH_INDEX : integer := 11; -- Buffer Length Reg constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0'); constant DMA_CONFIG : std_logic_vector(0 downto 0) := std_logic_vector(to_unsigned(C_INCLUDE_SG,1)); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal dmacr_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal dmasr_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0'); signal curdesc_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0'); signal taildesc_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal buffer_address_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal buffer_address_64_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal buffer_length_i : std_logic_vector (C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal curdesc1_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc1_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc1_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc1_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc2_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc2_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc2_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc2_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc3_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc3_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc3_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc3_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc4_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc4_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc4_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc4_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc5_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc5_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc5_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc5_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc6_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc6_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc6_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc6_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc7_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc7_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc7_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc7_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc8_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc8_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc8_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc8_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc9_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc9_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc9_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc9_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc10_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc10_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc10_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc10_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc11_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc11_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc11_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc11_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc12_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc12_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc12_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc12_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc13_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc13_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc13_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc13_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc14_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc14_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc14_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc14_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc15_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc15_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc15_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc15_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal update_curdesc1 : std_logic := '0'; signal update_curdesc2 : std_logic := '0'; signal update_curdesc3 : std_logic := '0'; signal update_curdesc4 : std_logic := '0'; signal update_curdesc5 : std_logic := '0'; signal update_curdesc6 : std_logic := '0'; signal update_curdesc7 : std_logic := '0'; signal update_curdesc8 : std_logic := '0'; signal update_curdesc9 : std_logic := '0'; signal update_curdesc10 : std_logic := '0'; signal update_curdesc11 : std_logic := '0'; signal update_curdesc12 : std_logic := '0'; signal update_curdesc13 : std_logic := '0'; signal update_curdesc14 : std_logic := '0'; signal update_curdesc15 : std_logic := '0'; signal dest0 : std_logic := '0'; signal dest1 : std_logic := '0'; signal dest2 : std_logic := '0'; signal dest3 : std_logic := '0'; signal dest4 : std_logic := '0'; signal dest5 : std_logic := '0'; signal dest6 : std_logic := '0'; signal dest7 : std_logic := '0'; signal dest8 : std_logic := '0'; signal dest9 : std_logic := '0'; signal dest10 : std_logic := '0'; signal dest11 : std_logic := '0'; signal dest12 : std_logic := '0'; signal dest13 : std_logic := '0'; signal dest14 : std_logic := '0'; signal dest15 : std_logic := '0'; -- DMASR Signals signal halted : std_logic := '0'; signal idle : std_logic := '0'; signal cmplt : std_logic := '0'; signal error : std_logic := '0'; signal dma_interr : std_logic := '0'; signal dma_slverr : std_logic := '0'; signal dma_decerr : std_logic := '0'; signal sg_interr : std_logic := '0'; signal sg_slverr : std_logic := '0'; signal sg_decerr : std_logic := '0'; signal ioc_irq : std_logic := '0'; signal dly_irq : std_logic := '0'; signal error_d1 : std_logic := '0'; signal error_re : std_logic := '0'; signal err_irq : std_logic := '0'; signal sg_ftch_error : std_logic := '0'; signal sg_updt_error : std_logic := '0'; signal error_pointer_set : std_logic := '0'; signal error_pointer_set1 : std_logic := '0'; signal error_pointer_set2 : std_logic := '0'; signal error_pointer_set3 : std_logic := '0'; signal error_pointer_set4 : std_logic := '0'; signal error_pointer_set5 : std_logic := '0'; signal error_pointer_set6 : std_logic := '0'; signal error_pointer_set7 : std_logic := '0'; signal error_pointer_set8 : std_logic := '0'; signal error_pointer_set9 : std_logic := '0'; signal error_pointer_set10 : std_logic := '0'; signal error_pointer_set11 : std_logic := '0'; signal error_pointer_set12 : std_logic := '0'; signal error_pointer_set13 : std_logic := '0'; signal error_pointer_set14 : std_logic := '0'; signal error_pointer_set15 : std_logic := '0'; -- interrupt coalescing support signals signal different_delay : std_logic := '0'; signal different_thresh : std_logic := '0'; signal threshold_is_zero : std_logic := '0'; -- soft reset support signals signal soft_reset_i : std_logic := '0'; signal run_stop_clr : std_logic := '0'; signal tail_update_lsb : std_logic := '0'; signal tail_update_msb : std_logic := '0'; signal sg_cache_info : std_logic_vector (7 downto 0); signal halt_free : std_logic := '0'; signal tmp11 : std_logic := '0'; signal sig_cur_updated : std_logic := '0'; signal tailpntr_updated_d1 : std_logic; signal tailpntr_updated_d2 : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin GEN_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate begin halt_free <= '1'; end generate GEN_MULTI_CH; GEN_NOMULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate begin halt_free <= dmasr_i(DMASR_HALTED_BIT); end generate GEN_NOMULTI_CH; GEN_DESC_UPDATE_FOR_SG : if C_NUM_S2MM_CHANNELS = 1 generate begin update_curdesc1 <= '0'; update_curdesc2 <= '0'; update_curdesc3 <= '0'; update_curdesc4 <= '0'; update_curdesc5 <= '0'; update_curdesc6 <= '0'; update_curdesc7 <= '0'; update_curdesc8 <= '0'; update_curdesc9 <= '0'; update_curdesc10 <= '0'; update_curdesc11 <= '0'; update_curdesc12 <= '0'; update_curdesc13 <= '0'; update_curdesc14 <= '0'; update_curdesc15 <= '0'; end generate GEN_DESC_UPDATE_FOR_SG; dest0 <= '1' when tdest_in (4 downto 0) = "00000" else '0'; dest1 <= '1' when tdest_in (4 downto 0) = "00001" else '0'; dest2 <= '1' when tdest_in (4 downto 0) = "00010" else '0'; dest3 <= '1' when tdest_in (4 downto 0) = "00011" else '0'; dest4 <= '1' when tdest_in (4 downto 0) = "00100" else '0'; dest5 <= '1' when tdest_in (4 downto 0) = "00101" else '0'; dest6 <= '1' when tdest_in (4 downto 0) = "00110" else '0'; dest7 <= '1' when tdest_in (4 downto 0) = "00111" else '0'; dest8 <= '1' when tdest_in (4 downto 0) = "01000" else '0'; dest9 <= '1' when tdest_in (4 downto 0) = "01001" else '0'; dest10 <= '1' when tdest_in (4 downto 0) = "01010" else '0'; dest11 <= '1' when tdest_in (4 downto 0) = "01011" else '0'; dest12 <= '1' when tdest_in (4 downto 0) = "01100" else '0'; dest13 <= '1' when tdest_in (4 downto 0) = "01101" else '0'; dest14 <= '1' when tdest_in (4 downto 0) = "01110" else '0'; dest15 <= '1' when tdest_in (4 downto 0) = "01111" else '0'; GEN_DESC_UPDATE_FOR_SG_CH : if C_NUM_S2MM_CHANNELS > 1 generate update_curdesc1 <= update_curdesc when tdest_in (4 downto 0) = "00001" else '0'; update_curdesc2 <= update_curdesc when tdest_in (4 downto 0) = "00010" else '0'; update_curdesc3 <= update_curdesc when tdest_in (4 downto 0) = "00011" else '0'; update_curdesc4 <= update_curdesc when tdest_in (4 downto 0) = "00100" else '0'; update_curdesc5 <= update_curdesc when tdest_in (4 downto 0) = "00101" else '0'; update_curdesc6 <= update_curdesc when tdest_in (4 downto 0) = "00110" else '0'; update_curdesc7 <= update_curdesc when tdest_in (4 downto 0) = "00111" else '0'; update_curdesc8 <= update_curdesc when tdest_in (4 downto 0) = "01000" else '0'; update_curdesc9 <= update_curdesc when tdest_in (4 downto 0) = "01001" else '0'; update_curdesc10 <= update_curdesc when tdest_in (4 downto 0) = "01010" else '0'; update_curdesc11 <= update_curdesc when tdest_in (4 downto 0) = "01011" else '0'; update_curdesc12 <= update_curdesc when tdest_in (4 downto 0) = "01100" else '0'; update_curdesc13 <= update_curdesc when tdest_in (4 downto 0) = "01101" else '0'; update_curdesc14 <= update_curdesc when tdest_in (4 downto 0) = "01110" else '0'; update_curdesc15 <= update_curdesc when tdest_in (4 downto 0) = "01111" else '0'; end generate GEN_DESC_UPDATE_FOR_SG_CH; GEN_DA_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate begin buffer_address <= buffer_address_64_i & buffer_address_i ; end generate GEN_DA_ADDR_EQL64; GEN_DA_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin buffer_address <= buffer_address_i ; end generate GEN_DA_ADDR_EQL32; dmacr <= dmacr_i ; dmasr <= dmasr_i ; curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ; curdesc_msb <= curdesc_msb_i ; taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ; taildesc_msb <= taildesc_msb_i ; buffer_length <= buffer_length_i ; curdesc1_lsb <= curdesc1_lsb_i ; curdesc1_msb <= curdesc1_msb_i ; taildesc1_lsb <= taildesc1_lsb_i ; taildesc1_msb <= taildesc1_msb_i ; curdesc2_lsb <= curdesc2_lsb_i ; curdesc2_msb <= curdesc2_msb_i ; taildesc2_lsb <= taildesc2_lsb_i ; taildesc2_msb <= taildesc2_msb_i ; curdesc3_lsb <= curdesc3_lsb_i ; curdesc3_msb <= curdesc3_msb_i ; taildesc3_lsb <= taildesc3_lsb_i ; taildesc3_msb <= taildesc3_msb_i ; curdesc4_lsb <= curdesc4_lsb_i ; curdesc4_msb <= curdesc4_msb_i ; taildesc4_lsb <= taildesc4_lsb_i ; taildesc4_msb <= taildesc4_msb_i ; curdesc5_lsb <= curdesc5_lsb_i ; curdesc5_msb <= curdesc5_msb_i ; taildesc5_lsb <= taildesc5_lsb_i ; taildesc5_msb <= taildesc5_msb_i ; curdesc6_lsb <= curdesc6_lsb_i ; curdesc6_msb <= curdesc6_msb_i ; taildesc6_lsb <= taildesc6_lsb_i ; taildesc6_msb <= taildesc6_msb_i ; curdesc7_lsb <= curdesc7_lsb_i ; curdesc7_msb <= curdesc7_msb_i ; taildesc7_lsb <= taildesc7_lsb_i ; taildesc7_msb <= taildesc7_msb_i ; curdesc8_lsb <= curdesc8_lsb_i ; curdesc8_msb <= curdesc8_msb_i ; taildesc8_lsb <= taildesc8_lsb_i ; taildesc8_msb <= taildesc8_msb_i ; curdesc9_lsb <= curdesc9_lsb_i ; curdesc9_msb <= curdesc9_msb_i ; taildesc9_lsb <= taildesc9_lsb_i ; taildesc9_msb <= taildesc9_msb_i ; curdesc10_lsb <= curdesc10_lsb_i ; curdesc10_msb <= curdesc10_msb_i ; taildesc10_lsb <= taildesc10_lsb_i ; taildesc10_msb <= taildesc10_msb_i ; curdesc11_lsb <= curdesc11_lsb_i ; curdesc11_msb <= curdesc11_msb_i ; taildesc11_lsb <= taildesc11_lsb_i ; taildesc11_msb <= taildesc11_msb_i ; curdesc12_lsb <= curdesc12_lsb_i ; curdesc12_msb <= curdesc12_msb_i ; taildesc12_lsb <= taildesc12_lsb_i ; taildesc12_msb <= taildesc12_msb_i ; curdesc13_lsb <= curdesc13_lsb_i ; curdesc13_msb <= curdesc13_msb_i ; taildesc13_lsb <= taildesc13_lsb_i ; taildesc13_msb <= taildesc13_msb_i ; curdesc14_lsb <= curdesc14_lsb_i ; curdesc14_msb <= curdesc14_msb_i ; taildesc14_lsb <= taildesc14_lsb_i ; taildesc14_msb <= taildesc14_msb_i ; curdesc15_lsb <= curdesc15_lsb_i ; curdesc15_msb <= curdesc15_msb_i ; taildesc15_lsb <= taildesc15_lsb_i ; taildesc15_msb <= taildesc15_msb_i ; --------------------------------------------------------------------------- -- DMA Control Register --------------------------------------------------------------------------- -- DMACR - Interrupt Delay Value ------------------------------------------------------------------------------- DMACR_DELAY : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0'); elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT); end if; end if; end process DMACR_DELAY; -- If written delay is different than previous value then assert write enable different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) /= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) else '0'; -- delay value different, drive write of delay value to interrupt controller NEW_DELAY_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then irqdelay_wren <= '0'; -- If AXI Lite write to DMACR and delay different than current -- setting then update delay value elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then irqdelay_wren <= '1'; else irqdelay_wren <= '0'; end if; end if; end process NEW_DELAY_WRITE; ------------------------------------------------------------------------------- -- DMACR - Interrupt Threshold Value ------------------------------------------------------------------------------- threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD else '0'; DMACR_THRESH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD; -- On AXI Lite write elsif(axi2ip_wrce(DMACR_INDEX) = '1')then -- If value is 0 then set threshold to 1 if(threshold_is_zero='1')then dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD; -- else set threshold to axi lite wrdata value else dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT); end if; end if; end if; end process DMACR_THRESH; -- If written threshold is different than previous value then assert write enable different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) /= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) else '0'; -- new treshold written therefore drive write of threshold out NEW_THRESH_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then irqthresh_wren <= '0'; -- If AXI Lite write to DMACR and threshold different than current -- setting then update threshold value elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then irqthresh_wren <= '1'; else irqthresh_wren <= '0'; end if; end if; end process NEW_THRESH_WRITE; ------------------------------------------------------------------------------- -- DMACR - Remainder of DMA Control Register, Key Hole write bit (3) ------------------------------------------------------------------------------- DMACR_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 downto DMACR_RESERVED5_BIT) <= (others => '0'); elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15 downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT) -- bit 14 & axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 13 & axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 12 & axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bits 11 downto 3 & ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT); end if; end if; end process DMACR_REGISTER; DMACR_REGISTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then dmacr_i(DMACR_KH_BIT) <= '0'; dmacr_i(CYCLIC_BIT) <= '0'; elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT); dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT); end if; end if; end process DMACR_REGISTER1; ------------------------------------------------------------------------------- -- DMACR - Reset Bit ------------------------------------------------------------------------------- DMACR_RESET : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(soft_reset_clr = '1')then dmacr_i(DMACR_RESET_BIT) <= '0'; -- If soft reset set in other channel then set -- reset bit here too elsif(soft_reset_in = '1')then dmacr_i(DMACR_RESET_BIT) <= '1'; -- If DMACR Write then pass axi lite write bus to DMARC reset bit elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT); end if; end if; end process DMACR_RESET; soft_reset_i <= dmacr_i(DMACR_RESET_BIT); ------------------------------------------------------------------------------- -- Tail Pointer Enable fixed at 1 for this release of axi dma ------------------------------------------------------------------------------- dmacr_i(DMACR_TAILPEN_BIT) <= '1'; ------------------------------------------------------------------------------- -- DMACR - Run/Stop Bit ------------------------------------------------------------------------------- run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error or error_in = '1' -- S2MM Error or stop_dma = '1' -- Stop due to error or soft_reset_i = '1' -- MM2S Soft Reset or soft_reset_in = '1' -- S2MM Soft Reset else '0'; DMACR_RUNSTOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_RS_BIT) <= '0'; -- Clear on sg error (i.e. error) or other channel -- error (i.e. error_in) or dma error or soft reset elsif(run_stop_clr = '1')then dmacr_i(DMACR_RS_BIT) <= '0'; elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT); end if; end if; end process DMACR_RUNSTOP; --------------------------------------------------------------------------- -- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA -- channel is halted. --------------------------------------------------------------------------- DMASR_HALTED : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or halted_set = '1')then halted <= '1'; elsif(halted_clr = '1')then halted <= '0'; end if; end if; end process DMASR_HALTED; --------------------------------------------------------------------------- -- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA -- channel is IDLE waiting at tail pointer. Update of Tail Pointer -- will cause engine to resume. Note: Halted channels return to a -- reset condition. --------------------------------------------------------------------------- DMASR_IDLE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or idle_clr = '1' or halted_set = '1')then idle <= '0'; elsif(idle_set = '1')then idle <= '1'; end if; end if; end process DMASR_IDLE; --------------------------------------------------------------------------- -- DMA Status Error bit (BIT 3) -- Note: any error will cause entire engine to halt --------------------------------------------------------------------------- error <= dma_interr or dma_slverr or dma_decerr or sg_interr or sg_slverr or sg_decerr; -- Scatter Gather Error --sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set; -- SG Update Errors or DMA errors assert flag on descriptor update -- Used to latch current descriptor pointer --sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set -- or dma_interr or dma_slverr or dma_decerr; -- Map out to halt opposing channel error_out <= error; SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_ftch_error <= '0'; sg_updt_error <= '0'; else sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set; sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set or dma_interr or dma_slverr or dma_decerr; end if; end if; end process SG_FTCH_ERROR_PROC; --------------------------------------------------------------------------- -- DMA Status DMA Internal Error bit (BIT 4) --------------------------------------------------------------------------- DMASR_DMAINTERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_interr <= '0'; elsif(dma_interr_set = '1' )then dma_interr <= '1'; end if; end if; end process DMASR_DMAINTERR; --------------------------------------------------------------------------- -- DMA Status DMA Slave Error bit (BIT 5) --------------------------------------------------------------------------- DMASR_DMASLVERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_slverr <= '0'; elsif(dma_slverr_set = '1' )then dma_slverr <= '1'; end if; end if; end process DMASR_DMASLVERR; --------------------------------------------------------------------------- -- DMA Status DMA Decode Error bit (BIT 6) --------------------------------------------------------------------------- DMASR_DMADECERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_decerr <= '0'; elsif(dma_decerr_set = '1' )then dma_decerr <= '1'; end if; end if; end process DMASR_DMADECERR; --------------------------------------------------------------------------- -- DMA Status SG Internal Error bit (BIT 8) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGINTERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_interr <= '0'; elsif(ftch_interr_set = '1' or updt_interr_set = '1')then sg_interr <= '1'; end if; end if; end process DMASR_SGINTERR; --------------------------------------------------------------------------- -- DMA Status SG Slave Error bit (BIT 9) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGSLVERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_slverr <= '0'; elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then sg_slverr <= '1'; end if; end if; end process DMASR_SGSLVERR; --------------------------------------------------------------------------- -- DMA Status SG Decode Error bit (BIT 10) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGDECERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_decerr <= '0'; elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then sg_decerr <= '1'; end if; end if; end process DMASR_SGDECERR; --------------------------------------------------------------------------- -- DMA Status IOC Interrupt status bit (BIT 11) --------------------------------------------------------------------------- DMASR_IOCIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then ioc_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT))) or ioc_irq_set; elsif(ioc_irq_set = '1')then ioc_irq <= '1'; end if; end if; end process DMASR_IOCIRQ; --------------------------------------------------------------------------- -- DMA Status Delay Interrupt status bit (BIT 12) --------------------------------------------------------------------------- DMASR_DLYIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dly_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT))) or dly_irq_set; elsif(dly_irq_set = '1')then dly_irq <= '1'; end if; end if; end process DMASR_DLYIRQ; -- CR605888 Disable delay timer if halted or on delay irq set --dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348 dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348 or dmasr_i(DMASR_DLYIRQ_BIT); --------------------------------------------------------------------------- -- DMA Status Error Interrupt status bit (BIT 12) --------------------------------------------------------------------------- -- Delay error setting for generation of error strobe GEN_ERROR_RE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then error_d1 <= '0'; else error_d1 <= error; end if; end if; end process GEN_ERROR_RE; -- Generate rising edge pulse on error error_re <= error and not error_d1; DMASR_ERRIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then err_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT))) or error_re; elsif(error_re = '1')then err_irq <= '1'; end if; end if; end process DMASR_ERRIRQ; --------------------------------------------------------------------------- -- DMA Interrupt OUT --------------------------------------------------------------------------- REG_INTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then introut <= '0'; else introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT)) or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT)) or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT)); end if; end if; end process; --------------------------------------------------------------------------- -- DMA Status Register --------------------------------------------------------------------------- dmasr_i <= irqdelay_status -- Bits 31 downto 24 & irqthresh_status -- Bits 23 downto 16 & '0' -- Bit 15 & err_irq -- Bit 14 & dly_irq -- Bit 13 & ioc_irq -- Bit 12 & '0' -- Bit 11 & sg_decerr -- Bit 10 & sg_slverr -- Bit 9 & sg_interr -- Bit 8 & '0' -- Bit 7 & dma_decerr -- Bit 6 & dma_slverr -- Bit 5 & dma_interr -- Bit 4 & DMA_CONFIG -- Bit 3 & '0' -- Bit 2 & idle -- Bit 1 & halted; -- Bit 0 -- Generate current descriptor and tail descriptor register for Scatter Gather Mode GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate begin GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate begin MM2S_SGCTL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_cache_info <= "00000011"; --(others => '0'); elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0); else sg_cache_info <= sg_cache_info; end if; end if; end process MM2S_SGCTL; sg_ctl <= sg_cache_info; end generate GEN_SG_CTL_REG; GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate begin sg_ctl <= "00000011"; --(others => '0'); end generate GEN_SG_NO_CTL_REG; -- Signals not used for Scatter Gather Mode, only simple mode buffer_address_i <= (others => '0'); buffer_length_i <= (others => '0'); buffer_length_wren <= '0'; --------------------------------------------------------------------------- -- Current Descriptor LSB Register --------------------------------------------------------------------------- CURDESC_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc_lsb_i <= (others => '0'); error_pointer_set <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6); error_pointer_set <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest0 = '1')then -- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6); error_pointer_set <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and halt_free = '1')then curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT); -- & ZERO_VALUE(CURDESC_RESERVED_BIT5 -- downto CURDESC_RESERVED_BIT0); error_pointer_set <= '0'; end if; end if; end if; end process CURDESC_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT); -- & ZERO_VALUE(TAILDESC_RESERVED_BIT5 -- downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC_LSB_REGISTER; GEN_DESC1_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate CURDESC1_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc1_lsb_i <= (others => '0'); error_pointer_set1 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set1 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then curdesc1_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set1 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest1 = '1')then -- curdesc1_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set1 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then curdesc1_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set1 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC1_LSB_INDEX) = '1' and halt_free = '1')then curdesc1_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set1 <= '0'; end if; end if; end if; end process CURDESC1_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC1_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc1_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC1_LSB_INDEX) = '1')then taildesc1_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC1_LSB_REGISTER; end generate GEN_DESC1_REG_FOR_SG; GEN_DESC2_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate CURDESC2_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc2_lsb_i <= (others => '0'); error_pointer_set2 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set2 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then curdesc2_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set2 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest2 = '1')then -- curdesc2_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set2 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then curdesc2_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set2 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC2_LSB_INDEX) = '1' and halt_free = '1')then curdesc2_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set2 <= '0'; end if; end if; end if; end process CURDESC2_LSB_REGISTER; TAILDESC2_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc2_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC2_LSB_INDEX) = '1')then taildesc2_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC2_LSB_REGISTER; end generate GEN_DESC2_REG_FOR_SG; GEN_DESC3_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate CURDESC3_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc3_lsb_i <= (others => '0'); error_pointer_set3 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set3 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then curdesc3_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set3 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest3 = '1')then -- curdesc3_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set3 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then curdesc3_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set3 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC3_LSB_INDEX) = '1' and halt_free = '1')then curdesc3_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set3 <= '0'; end if; end if; end if; end process CURDESC3_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC3_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc3_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC3_LSB_INDEX) = '1')then taildesc3_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC3_LSB_REGISTER; end generate GEN_DESC3_REG_FOR_SG; GEN_DESC4_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate CURDESC4_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc4_lsb_i <= (others => '0'); error_pointer_set4 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set4 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then curdesc4_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set4 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest4 = '1')then -- curdesc4_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set4 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then curdesc4_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set4 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC4_LSB_INDEX) = '1' and halt_free = '1')then curdesc4_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set4 <= '0'; end if; end if; end if; end process CURDESC4_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC4_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc4_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC4_LSB_INDEX) = '1')then taildesc4_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC4_LSB_REGISTER; end generate GEN_DESC4_REG_FOR_SG; GEN_DESC5_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate CURDESC5_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc5_lsb_i <= (others => '0'); error_pointer_set5 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set5 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then curdesc5_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set5 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest5 = '1')then -- curdesc5_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set5 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then curdesc5_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set5 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC5_LSB_INDEX) = '1' and halt_free = '1')then curdesc5_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set5 <= '0'; end if; end if; end if; end process CURDESC5_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC5_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc5_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC5_LSB_INDEX) = '1')then taildesc5_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC5_LSB_REGISTER; end generate GEN_DESC5_REG_FOR_SG; GEN_DESC6_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate CURDESC6_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc6_lsb_i <= (others => '0'); error_pointer_set6 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set6 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then curdesc6_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set6 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest6 = '1')then -- curdesc6_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set6 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then curdesc6_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set6 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC6_LSB_INDEX) = '1' and halt_free = '1')then curdesc6_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set6 <= '0'; end if; end if; end if; end process CURDESC6_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC6_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc6_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC6_LSB_INDEX) = '1')then taildesc6_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC6_LSB_REGISTER; end generate GEN_DESC6_REG_FOR_SG; GEN_DESC7_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate CURDESC7_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc7_lsb_i <= (others => '0'); error_pointer_set7 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set7 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then curdesc7_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set7 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest7 = '1')then -- curdesc7_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set7 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then curdesc7_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set7 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC7_LSB_INDEX) = '1' and halt_free = '1')then curdesc7_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set7 <= '0'; end if; end if; end if; end process CURDESC7_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC7_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc7_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC7_LSB_INDEX) = '1')then taildesc7_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC7_LSB_REGISTER; end generate GEN_DESC7_REG_FOR_SG; GEN_DESC8_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate CURDESC8_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc8_lsb_i <= (others => '0'); error_pointer_set8 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set8 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then curdesc8_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set8 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest8 = '1')then -- curdesc8_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set8 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then curdesc8_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set8 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC8_LSB_INDEX) = '1' and halt_free = '1')then curdesc8_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set8 <= '0'; end if; end if; end if; end process CURDESC8_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC8_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc8_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC8_LSB_INDEX) = '1')then taildesc8_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC8_LSB_REGISTER; end generate GEN_DESC8_REG_FOR_SG; GEN_DESC9_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate CURDESC9_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc9_lsb_i <= (others => '0'); error_pointer_set9 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set9 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then curdesc9_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set9 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest9 = '1')then -- curdesc9_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set9 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then curdesc9_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set9 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC9_LSB_INDEX) = '1' and halt_free = '1')then curdesc9_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set9 <= '0'; end if; end if; end if; end process CURDESC9_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC9_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc9_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC9_LSB_INDEX) = '1')then taildesc9_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC9_LSB_REGISTER; end generate GEN_DESC9_REG_FOR_SG; GEN_DESC10_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate CURDESC10_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc10_lsb_i <= (others => '0'); error_pointer_set10 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set10 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then curdesc10_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set10 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest10 = '1')then -- curdesc10_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set10 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then curdesc10_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set10 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC10_LSB_INDEX) = '1' and halt_free = '1')then curdesc10_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set10 <= '0'; end if; end if; end if; end process CURDESC10_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC10_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc10_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC10_LSB_INDEX) = '1')then taildesc10_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC10_LSB_REGISTER; end generate GEN_DESC10_REG_FOR_SG; GEN_DESC11_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate CURDESC11_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc11_lsb_i <= (others => '0'); error_pointer_set11 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set11 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then curdesc11_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set11 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest11 = '1')then -- curdesc11_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set11 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then curdesc11_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set11 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC11_LSB_INDEX) = '1' and halt_free = '1')then curdesc11_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set11 <= '0'; end if; end if; end if; end process CURDESC11_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC11_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc11_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC11_LSB_INDEX) = '1')then taildesc11_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC11_LSB_REGISTER; end generate GEN_DESC11_REG_FOR_SG; GEN_DESC12_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate CURDESC12_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc12_lsb_i <= (others => '0'); error_pointer_set12 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set12 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then curdesc12_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set12 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest12 = '1')then -- curdesc12_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set12 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then curdesc12_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set12 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC12_LSB_INDEX) = '1' and halt_free = '1')then curdesc12_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set12 <= '0'; end if; end if; end if; end process CURDESC12_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC12_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc12_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC12_LSB_INDEX) = '1')then taildesc12_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC12_LSB_REGISTER; end generate GEN_DESC12_REG_FOR_SG; GEN_DESC13_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate CURDESC13_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc13_lsb_i <= (others => '0'); error_pointer_set13 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set13 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then curdesc13_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set13 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest13 = '1')then -- curdesc13_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set13 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then curdesc13_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set13 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC13_LSB_INDEX) = '1' and halt_free = '1')then curdesc13_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set13 <= '0'; end if; end if; end if; end process CURDESC13_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC13_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc13_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC13_LSB_INDEX) = '1')then taildesc13_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC13_LSB_REGISTER; end generate GEN_DESC13_REG_FOR_SG; GEN_DESC14_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate CURDESC14_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc14_lsb_i <= (others => '0'); error_pointer_set14 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set14 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then curdesc14_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set14 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest14 = '1')then -- curdesc14_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set14 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then curdesc14_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set14 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC14_LSB_INDEX) = '1' and halt_free = '1')then curdesc14_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set14 <= '0'; end if; end if; end if; end process CURDESC14_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC14_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc14_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC14_LSB_INDEX) = '1')then taildesc14_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC14_LSB_REGISTER; end generate GEN_DESC14_REG_FOR_SG; GEN_DESC15_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate CURDESC15_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc15_lsb_i <= (others => '0'); error_pointer_set15 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set15 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then curdesc15_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set15 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest15 = '1')then -- curdesc15_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set15 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then curdesc15_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set15 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC15_LSB_INDEX) = '1' and halt_free = '1')then curdesc15_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set15 <= '0'; end if; end if; end if; end process CURDESC15_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC15_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc15_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC15_LSB_INDEX) = '1')then taildesc15_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC15_LSB_REGISTER; end generate GEN_DESC15_REG_FOR_SG; --------------------------------------------------------------------------- -- Current Descriptor MSB Register --------------------------------------------------------------------------- -- Scatter Gather Interface configured for 64-Bit SG Addresses GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin CURDESC_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc_msb_i <= (others => '0'); elsif(error_pointer_set = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then curdesc_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error elsif(sg_updt_error = '1' and dest0 = '1')then curdesc_msb_i <= updt_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then curdesc_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and halt_free = '1')then curdesc_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then taildesc_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC_MSB_REGISTER; GEN_DESC1_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate CURDESC1_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc1_msb_i <= (others => '0'); elsif(error_pointer_set1 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then curdesc1_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest1 = '1')then -- curdesc1_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then curdesc1_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC1_MSB_INDEX) = '1' and halt_free = '1')then curdesc1_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC1_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC1_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc1_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC1_MSB_INDEX) = '1')then taildesc1_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC1_MSB_REGISTER; end generate GEN_DESC1_MSB_FOR_SG; GEN_DESC2_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate CURDESC2_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc2_msb_i <= (others => '0'); elsif(error_pointer_set2 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then curdesc2_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest2 = '1')then -- curdesc2_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then curdesc2_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC2_MSB_INDEX) = '1' and halt_free = '1')then curdesc2_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC2_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC2_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc2_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC2_MSB_INDEX) = '1')then taildesc2_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC2_MSB_REGISTER; end generate GEN_DESC2_MSB_FOR_SG; GEN_DESC3_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate CURDESC3_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc3_msb_i <= (others => '0'); elsif(error_pointer_set3 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then curdesc3_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest3 = '1')then -- curdesc3_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then curdesc3_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC3_MSB_INDEX) = '1' and halt_free = '1')then curdesc3_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC3_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC3_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc3_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC3_MSB_INDEX) = '1')then taildesc3_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC3_MSB_REGISTER; end generate GEN_DESC3_MSB_FOR_SG; GEN_DESC4_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate CURDESC4_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc4_msb_i <= (others => '0'); elsif(error_pointer_set4 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then curdesc4_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest4 = '1')then -- curdesc4_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then curdesc4_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC4_MSB_INDEX) = '1' and halt_free = '1')then curdesc4_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC4_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC4_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc4_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC4_MSB_INDEX) = '1')then taildesc4_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC4_MSB_REGISTER; end generate GEN_DESC4_MSB_FOR_SG; GEN_DESC5_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate CURDESC5_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc5_msb_i <= (others => '0'); elsif(error_pointer_set5 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then curdesc5_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest5 = '1')then -- curdesc5_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then curdesc5_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC5_MSB_INDEX) = '1' and halt_free = '1')then curdesc5_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC5_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC5_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc5_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC5_MSB_INDEX) = '1')then taildesc5_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC5_MSB_REGISTER; end generate GEN_DESC5_MSB_FOR_SG; GEN_DESC6_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate CURDESC6_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc6_msb_i <= (others => '0'); elsif(error_pointer_set6 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then curdesc6_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest6 = '1')then -- curdesc6_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then curdesc6_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC6_MSB_INDEX) = '1' and halt_free = '1')then curdesc6_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC6_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC6_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc6_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC6_MSB_INDEX) = '1')then taildesc6_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC6_MSB_REGISTER; end generate GEN_DESC6_MSB_FOR_SG; GEN_DESC7_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate CURDESC7_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc7_msb_i <= (others => '0'); elsif(error_pointer_set7 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then curdesc7_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest7 = '1')then -- curdesc7_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then curdesc7_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC7_MSB_INDEX) = '1' and halt_free = '1')then curdesc7_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC7_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC7_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc7_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC7_MSB_INDEX) = '1')then taildesc7_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC7_MSB_REGISTER; end generate GEN_DESC7_MSB_FOR_SG; GEN_DESC8_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate CURDESC8_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc8_msb_i <= (others => '0'); elsif(error_pointer_set8 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then curdesc8_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest8 = '1')then -- curdesc8_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then curdesc8_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC8_MSB_INDEX) = '1' and halt_free = '1')then curdesc8_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC8_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC8_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc8_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC8_MSB_INDEX) = '1')then taildesc8_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC8_MSB_REGISTER; end generate GEN_DESC8_MSB_FOR_SG; GEN_DESC9_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate CURDESC9_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc9_msb_i <= (others => '0'); elsif(error_pointer_set9 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then curdesc9_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest9 = '1')then -- curdesc9_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then curdesc9_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC9_MSB_INDEX) = '1' and halt_free = '1')then curdesc9_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC9_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC9_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc9_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC9_MSB_INDEX) = '1')then taildesc9_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC9_MSB_REGISTER; end generate GEN_DESC9_MSB_FOR_SG; GEN_DESC10_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate CURDESC10_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc10_msb_i <= (others => '0'); elsif(error_pointer_set10 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then curdesc10_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest10 = '1')then -- curdesc10_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then curdesc10_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC10_MSB_INDEX) = '1' and halt_free = '1')then curdesc10_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC10_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC10_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc10_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC10_MSB_INDEX) = '1')then taildesc10_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC10_MSB_REGISTER; end generate GEN_DESC10_MSB_FOR_SG; GEN_DESC11_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate CURDESC11_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc11_msb_i <= (others => '0'); elsif(error_pointer_set11 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then curdesc11_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest11 = '1')then -- curdesc11_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then curdesc11_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC11_MSB_INDEX) = '1' and halt_free = '1')then curdesc11_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC11_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC11_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc11_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC11_MSB_INDEX) = '1')then taildesc11_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC11_MSB_REGISTER; end generate GEN_DESC11_MSB_FOR_SG; GEN_DESC12_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate CURDESC12_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc12_msb_i <= (others => '0'); elsif(error_pointer_set12 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then curdesc12_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest12 = '1')then -- curdesc12_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then curdesc12_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC12_MSB_INDEX) = '1' and halt_free = '1')then curdesc12_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC12_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC12_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc12_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC12_MSB_INDEX) = '1')then taildesc12_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC12_MSB_REGISTER; end generate GEN_DESC12_MSB_FOR_SG; GEN_DESC13_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate CURDESC13_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc13_msb_i <= (others => '0'); elsif(error_pointer_set13 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then curdesc13_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest13 = '1')then -- curdesc13_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then curdesc13_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC13_MSB_INDEX) = '1' and halt_free = '1')then curdesc13_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC13_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC13_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc13_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC13_MSB_INDEX) = '1')then taildesc13_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC13_MSB_REGISTER; end generate GEN_DESC13_MSB_FOR_SG; GEN_DESC14_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate CURDESC14_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc14_msb_i <= (others => '0'); elsif(error_pointer_set14 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then curdesc14_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest14 = '1')then -- curdesc14_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then curdesc14_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC14_MSB_INDEX) = '1' and halt_free = '1')then curdesc14_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC14_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC14_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc14_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC14_MSB_INDEX) = '1')then taildesc14_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC14_MSB_REGISTER; end generate GEN_DESC14_MSB_FOR_SG; GEN_DESC15_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate CURDESC15_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc15_msb_i <= (others => '0'); elsif(error_pointer_set15 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then curdesc15_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest15 = '1')then -- curdesc15_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then curdesc15_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC15_MSB_INDEX) = '1' and halt_free = '1')then curdesc15_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC15_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC15_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc15_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC15_MSB_INDEX) = '1')then taildesc15_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC15_MSB_REGISTER; end generate GEN_DESC15_MSB_FOR_SG; end generate GEN_SG_ADDR_EQL64; -- Scatter Gather Interface configured for 32-Bit SG Addresses GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin curdesc_msb_i <= (others => '0'); taildesc_msb_i <= (others => '0'); -- Extending this to the extra registers curdesc1_msb_i <= (others => '0'); taildesc1_msb_i <= (others => '0'); curdesc2_msb_i <= (others => '0'); taildesc2_msb_i <= (others => '0'); curdesc3_msb_i <= (others => '0'); taildesc3_msb_i <= (others => '0'); curdesc4_msb_i <= (others => '0'); taildesc4_msb_i <= (others => '0'); curdesc5_msb_i <= (others => '0'); taildesc5_msb_i <= (others => '0'); curdesc6_msb_i <= (others => '0'); taildesc6_msb_i <= (others => '0'); curdesc7_msb_i <= (others => '0'); taildesc7_msb_i <= (others => '0'); curdesc8_msb_i <= (others => '0'); taildesc8_msb_i <= (others => '0'); curdesc9_msb_i <= (others => '0'); taildesc9_msb_i <= (others => '0'); curdesc10_msb_i <= (others => '0'); taildesc10_msb_i <= (others => '0'); curdesc11_msb_i <= (others => '0'); taildesc11_msb_i <= (others => '0'); curdesc12_msb_i <= (others => '0'); taildesc12_msb_i <= (others => '0'); curdesc13_msb_i <= (others => '0'); taildesc13_msb_i <= (others => '0'); curdesc14_msb_i <= (others => '0'); taildesc14_msb_i <= (others => '0'); curdesc15_msb_i <= (others => '0'); taildesc15_msb_i <= (others => '0'); end generate GEN_SG_ADDR_EQL32; -- Scatter Gather Interface configured for 32-Bit SG Addresses GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin -- Added dest so that BD can be dynamically updated GENERATE_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0) or (axi2ip_wrce(TAILDESC1_LSB_INDEX) and dest1) or (axi2ip_wrce(TAILDESC2_LSB_INDEX) and dest2) or (axi2ip_wrce(TAILDESC3_LSB_INDEX) and dest3) or (axi2ip_wrce(TAILDESC4_LSB_INDEX) and dest4) or (axi2ip_wrce(TAILDESC5_LSB_INDEX) and dest5) or (axi2ip_wrce(TAILDESC6_LSB_INDEX) and dest6) or (axi2ip_wrce(TAILDESC7_LSB_INDEX) and dest7) or (axi2ip_wrce(TAILDESC8_LSB_INDEX) and dest8) or (axi2ip_wrce(TAILDESC9_LSB_INDEX) and dest9) or (axi2ip_wrce(TAILDESC10_LSB_INDEX) and dest10) or (axi2ip_wrce(TAILDESC11_LSB_INDEX) and dest11) or (axi2ip_wrce(TAILDESC12_LSB_INDEX) and dest12) or (axi2ip_wrce(TAILDESC13_LSB_INDEX) and dest13) or (axi2ip_wrce(TAILDESC14_LSB_INDEX) and dest14) or (axi2ip_wrce(TAILDESC15_LSB_INDEX) and dest15); end generate GENERATE_MULTI_CH; GENERATE_NO_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0); end generate GENERATE_NO_MULTI_CH; TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then tailpntr_updated_d1 <= '0'; elsif (tail_update_lsb = '1' and tdest_in(5) = '0')then tailpntr_updated_d1 <= '1'; else tailpntr_updated_d1 <= '0'; end if; end if; end process TAILPNTR_UPDT_PROCESS; TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tailpntr_updated_d2 <= '0'; else tailpntr_updated_d2 <= tailpntr_updated_d1; end if; end if; end process TAILPNTR_UPDT_PROCESS_DEL; tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2); end generate GEN_TAILUPDATE_EQL32; -- Scatter Gather Interface configured for 64-Bit SG Addresses GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin -- Added dest so that BD can be dynamically updated GENERATE_NO_MULTI_CH1 : if C_ENABLE_MULTI_CHANNEL = 1 generate tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0) or (axi2ip_wrce(TAILDESC1_MSB_INDEX) and dest1) or (axi2ip_wrce(TAILDESC2_MSB_INDEX) and dest2) or (axi2ip_wrce(TAILDESC3_MSB_INDEX) and dest3) or (axi2ip_wrce(TAILDESC4_MSB_INDEX) and dest4) or (axi2ip_wrce(TAILDESC5_MSB_INDEX) and dest5) or (axi2ip_wrce(TAILDESC6_MSB_INDEX) and dest6) or (axi2ip_wrce(TAILDESC7_MSB_INDEX) and dest7) or (axi2ip_wrce(TAILDESC8_MSB_INDEX) and dest8) or (axi2ip_wrce(TAILDESC9_MSB_INDEX) and dest9) or (axi2ip_wrce(TAILDESC10_MSB_INDEX) and dest10) or (axi2ip_wrce(TAILDESC11_MSB_INDEX) and dest11) or (axi2ip_wrce(TAILDESC12_MSB_INDEX) and dest12) or (axi2ip_wrce(TAILDESC13_MSB_INDEX) and dest13) or (axi2ip_wrce(TAILDESC14_MSB_INDEX) and dest14) or (axi2ip_wrce(TAILDESC15_MSB_INDEX) and dest15); end generate GENERATE_NO_MULTI_CH1; GENERATE_NO_MULTI_CH2 : if C_ENABLE_MULTI_CHANNEL = 0 generate tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0); end generate GENERATE_NO_MULTI_CH2; TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then tailpntr_updated_d1 <= '0'; elsif (tail_update_msb = '1' and tdest_in(5) = '0')then tailpntr_updated_d1 <= '1'; else tailpntr_updated_d1 <= '0'; end if; end if; end process TAILPNTR_UPDT_PROCESS; TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tailpntr_updated_d2 <= '0'; else tailpntr_updated_d2 <= tailpntr_updated_d1; end if; end if; end process TAILPNTR_UPDT_PROCESS_DEL; tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2); end generate GEN_TAILUPDATE_EQL64; end generate GEN_DESC_REG_FOR_SG; -- Generate Buffer Address and Length Register for Simple DMA Mode GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate begin -- Signals not used for simple dma mode, only for sg mode curdesc_lsb_i <= (others => '0'); curdesc_msb_i <= (others => '0'); taildesc_lsb_i <= (others => '0'); taildesc_msb_i <= (others => '0'); -- Extending this to new registers curdesc1_msb_i <= (others => '0'); taildesc1_msb_i <= (others => '0'); curdesc2_msb_i <= (others => '0'); taildesc2_msb_i <= (others => '0'); curdesc3_msb_i <= (others => '0'); taildesc3_msb_i <= (others => '0'); curdesc4_msb_i <= (others => '0'); taildesc4_msb_i <= (others => '0'); curdesc5_msb_i <= (others => '0'); taildesc5_msb_i <= (others => '0'); curdesc6_msb_i <= (others => '0'); taildesc6_msb_i <= (others => '0'); curdesc7_msb_i <= (others => '0'); taildesc7_msb_i <= (others => '0'); curdesc8_msb_i <= (others => '0'); taildesc8_msb_i <= (others => '0'); curdesc9_msb_i <= (others => '0'); taildesc9_msb_i <= (others => '0'); curdesc10_msb_i <= (others => '0'); taildesc10_msb_i <= (others => '0'); curdesc11_msb_i <= (others => '0'); taildesc11_msb_i <= (others => '0'); curdesc12_msb_i <= (others => '0'); taildesc12_msb_i <= (others => '0'); curdesc13_msb_i <= (others => '0'); taildesc13_msb_i <= (others => '0'); curdesc14_msb_i <= (others => '0'); taildesc14_msb_i <= (others => '0'); curdesc15_msb_i <= (others => '0'); taildesc15_msb_i <= (others => '0'); curdesc1_lsb_i <= (others => '0'); taildesc1_lsb_i <= (others => '0'); curdesc2_lsb_i <= (others => '0'); taildesc2_lsb_i <= (others => '0'); curdesc3_lsb_i <= (others => '0'); taildesc3_lsb_i <= (others => '0'); curdesc4_lsb_i <= (others => '0'); taildesc4_lsb_i <= (others => '0'); curdesc5_lsb_i <= (others => '0'); taildesc5_lsb_i <= (others => '0'); curdesc6_lsb_i <= (others => '0'); taildesc6_lsb_i <= (others => '0'); curdesc7_lsb_i <= (others => '0'); taildesc7_lsb_i <= (others => '0'); curdesc8_lsb_i <= (others => '0'); taildesc8_lsb_i <= (others => '0'); curdesc9_lsb_i <= (others => '0'); taildesc9_lsb_i <= (others => '0'); curdesc10_lsb_i <= (others => '0'); taildesc10_lsb_i <= (others => '0'); curdesc11_lsb_i <= (others => '0'); taildesc11_lsb_i <= (others => '0'); curdesc12_lsb_i <= (others => '0'); taildesc12_lsb_i <= (others => '0'); curdesc13_lsb_i <= (others => '0'); taildesc13_lsb_i <= (others => '0'); curdesc14_lsb_i <= (others => '0'); taildesc14_lsb_i <= (others => '0'); curdesc15_lsb_i <= (others => '0'); taildesc15_lsb_i <= (others => '0'); tailpntr_updated <= '0'; error_pointer_set <= '0'; -- Buffer Address register. Used for Source Address (SA) if MM2S -- and used for Destination Address (DA) if S2MM BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_address_i <= (others => '0'); elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then buffer_address_i <= axi2ip_wrdata; end if; end if; end process BUFFER_ADDR_REGISTER; GEN_BUF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate begin BUFFER_ADDR_REGISTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_address_64_i <= (others => '0'); elsif(axi2ip_wrce(BUFF_ADDRESS_MSB_INDEX) = '1')then buffer_address_64_i <= axi2ip_wrdata; end if; end if; end process BUFFER_ADDR_REGISTER1; end generate GEN_BUF_ADDR_EQL64; -- Buffer Length register. Used for number of bytes to transfer if MM2S -- and used for size of receive buffer is S2MM BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_length_i <= (others => '0'); -- Update with actual bytes received (Only for S2MM channel) elsif(bytes_received_wren = '1' and C_MICRO_DMA = 0)then buffer_length_i <= bytes_received; elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0); end if; end if; end process BUFFER_LNGTH_REGISTER; -- Buffer Length Write Enable control. Assertion of wren will -- begin a transfer if channel is Idle. BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_length_wren <= '0'; -- Non-zero length value written elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1' and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then buffer_length_wren <= '1'; else buffer_length_wren <= '0'; end if; end if; end process BUFFER_LNGTH_WRITE; end generate GEN_REG_FOR_SMPL; end implementation;

gpl-3.0

nickg/nvc

test/bounds/bounds2.vhd

1

3770

entity bounds2 is end entity; architecture test of bounds2 is begin asssignment_delays: block signal b1,b2,b3,b4,b5,b6,b7 : boolean; begin b1 <= true; -- OK b2 <= true after 10 ns; -- OK b3 <= true after 0 ns; -- OK b4 <= true after -1 ns; -- Error process begin b5 <= true; -- OK b5 <= true after 0 ns; -- OK b5 <= true after 1 fs; -- OK b5 <= true after -1 fs; -- Error wait; end process; b6 <= true after -10 ns when now = 5 ns else false; b7 <= true when now = 1 ns else false after -10 ns; end block; rejection_limits: block signal b1,b2,b3 : boolean; begin b1 <= reject 10 ns inertial true after 10 ns; -- OK b2 <= reject -10 ns inertial true; -- Error b3 <= reject 10 ns inertial true after 5 ns; -- Error end block; process begin wait for -10 ns; -- Error wait; end process; default_values: block type r is range 0 to 1; constant ok1 : integer range 0 to 1 := 1; -- OK constant ok2 : character range 'a' to 'z' := 'b'; -- OK constant ok3 : real range 0.0 to 1.0 := 0.0; -- OK constant ok4 : time range 10 ns to 20 ns := 10 ns; -- OK constant ok5 : r := 0; -- OK signal s : integer range 0 to 9 := 20; -- Error constant c1 : character range 'a' to 'z' := 'Z'; -- Error shared variable v : real range 0.0 to 5.0 := 10.0; -- Error constant t : time range 10 ns to 10 us := 0 fs; -- Error constant c2 : r := 10; -- Error subtype subint is integer range 1 to 10; procedure test(a : subint := 30) is begin end procedure; function test(a : character range 'a' to 'b' := 'c') return integer is begin return 1; end function; component comp is generic ( g2 : integer range 10 downto 0 := 20 ); port ( p2 : in integer range 0 to 1 := 2 ); end component; begin process is variable v2 : real range 0.0 to 5.0 := 5.1; -- Error begin end process; end block; ascending_time: block signal s : integer; signal del : time; begin process begin s <= 0 after 10 ns, 1 after 11 ns; -- OK s <= 0, 1 after 1 ns; -- OK s <= 10 after del; -- OK s <= 10 after del, 20 after del + 1 ns; -- OK s <= 0, 1; -- Error s <= 0 after 1 ns, 1; -- Error s <= 0 after 2 ns, 1 after 1 ns; -- Error s <= 0 after 1 ns, 1 after del, 2; -- Error s <= 1 after del, 2; -- Error wait; end process; end block; textio1: block is function unit_string (unit : time) return string is begin if unit = fs then -- OK return " fs"; elsif unit = ps then return " ps"; elsif unit = ns then return " ns"; else report "invalid unit " & time'image(unit); end if; end function; begin end block; end architecture;

gpl-3.0

nickg/nvc

test/regress/implicit3.vhd

5

675

entity sub is port ( x : in integer; y : out boolean ); end entity; architecture test of sub is begin y <= x'delayed(5 ns) > x; end architecture; ------------------------------------------------------------------------------- entity implicit3 is end entity; architecture test of implicit3 is signal x : integer := 0; signal y : boolean; begin sub_i: entity work.sub port map (x, y); process is begin x <= 1; wait for 1 ns; assert not y; wait for 5 ns; assert not y; x <= -1; wait for 5 ns; assert y; wait; end process; end architecture;

gpl-3.0

nickg/nvc

test/regress/func21.vhd

1

489

entity func21 is end entity; architecture test of func21 is type rec is record x, y : integer; end record; function func (r : rec) return integer is begin return r.x + r.y; end function; begin p1: process is variable a, b : integer; begin assert func(r.x => 1, r.y => 2) = 3; a := 4; b := 5; wait for 1 ns; assert func(r.x => a, r.y => b) = 9; wait; end process; end architecture;

gpl-3.0

Darkin47/Zynq-TX-UTT

Vivado_HLS/image_histogram/solution1/sim/vhdl/AESL_sim_pkg.vhd

2

8773

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2016.1 -- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== -- synthesis translate_off library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; use std.textio.all; --library work; --use work.AESL_components.all; package AESL_sim_components is -- simulation routines procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER); procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING); procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR; variable RHS : in STRING); procedure esl_assign_l (signal LHS : out STD_LOGIC; variable RHS : in STRING); procedure esl_compare_l (signal LHS: in STD_LOGIC; variable RHS: in STRING; variable dontcare: in BOOLEAN; variable isok: out BOOLEAN); procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR; variable RHS: in STRING; variable dontcare: in BOOLEAN; variable isok: out BOOLEAN); function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING; function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING; function esl_conv_lv (str : string; base : integer; len : integer) return STD_LOGIC_VECTOR; end package; package body AESL_sim_components is --simulation routines procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is variable whitespace : CHARACTER; variable i : INTEGER; variable ok: BOOLEAN; variable buff: STRING(1 to token'length); begin ok := false; i := 1; loop_main: while not endfile(textfile) loop if textline = null or textline'length = 0 then readline(textfile, textline); end if; loop_remove_whitespace: while textline'length > 0 loop if textline(textline'left) = ' ' or textline(textline'left) = HT or textline(textline'left) = CR or textline(textline'left) = LF then read(textline, whitespace); else exit loop_remove_whitespace; end if; end loop; loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop if textline(textline'left) = ' ' or textline(textline'left) = HT or textline(textline'left) = CR or textline(textline'left) = LF then exit loop_aesl_read_token; else read(textline, buff(i)); i := i + 1; end if; ok := true; end loop; if ok = true then exit loop_main; end if; end loop; buff(i) := ' '; token := buff; token_len:= i-1; end procedure esl_read_token; procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING) is variable i : INTEGER; begin esl_read_token (textfile, textline, token, i); end procedure esl_read_token; procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR; variable RHS : in STRING) is variable i : INTEGER; variable bitwidth : INTEGER; begin bitwidth := LHS'length; for i in 1 to bitwidth loop if RHS(i) = '1' then LHS(bitwidth - i) <= '1'; elsif RHS(i) = '0' then LHS(bitwidth - i) <= '0'; else LHS(bitwidth - i) <= 'X'; end if; end loop; end procedure; procedure esl_assign_l (signal LHS : out STD_LOGIC; variable RHS : in STRING) is begin if RHS(1) = '1' then LHS <= '1'; elsif RHS(1) = '0' then LHS <= '0'; else LHS <= 'X'; end if; end procedure; procedure esl_compare_l (signal LHS: in STD_LOGIC; variable RHS: in STRING; variable dontcare: in BOOLEAN; variable isok: out BOOLEAN) is begin if dontcare then isok := true; elsif RHS(1) = '1' then if LHS = '1' then isok := true; else isok := false; end if; elsif RHS(1) = '0' then if LHS = '0' then isok := true; else isok := false; end if; else isok := true; end if; end procedure; procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR; variable RHS: in STRING; variable dontcare: in BOOLEAN; variable isok: out BOOLEAN) is variable i : INTEGER; variable bitwidth : INTEGER; begin bitwidth := LHS'length; if dontcare then isok := true; else isok := true; loop_compare: for i in 1 to bitwidth loop if RHS(i) = '1' then if LHS(bitwidth - i) /= '1' then isok := false; exit loop_compare; end if; elsif RHS(i) = '0' then if LHS(bitwidth - i) /= '0' then isok := false; exit loop_compare; end if; end if; end loop; end if; end procedure; function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING is variable ret : STRING (1 to lv'length); variable i: INTEGER; begin for i in 1 to lv'length loop if lv(lv'length - i) = '1' then ret(i) := '1'; elsif lv(lv'length - i) = '0' then ret(i) := '0'; else ret(i) := 'X'; end if; end loop; return ret; end function; function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is constant LEN : integer := (lv'length + 3)/4; variable ret : STRING (1 to LEN); variable i, tmp: INTEGER; variable normal_lv : STD_LOGIC_VECTOR(LEN * 4 - 1 downto 0); variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0); begin normal_lv := (others => '0'); normal_lv(lv'length - 1 downto 0) := lv; for i in 0 to LEN - 1 loop tmp_lv := normal_lv(LEN * 4 - 1 - i * 4 downto LEN * 4 - 4 - i * 4); case tmp_lv is when "0000" => ret(i + 1) := '0'; when "0001" => ret(i + 1) := '1'; when "0010" => ret(i + 1) := '2'; when "0011" => ret(i + 1) := '3'; when "0100" => ret(i + 1) := '4'; when "0101" => ret(i + 1) := '5'; when "0110" => ret(i + 1) := '6'; when "0111" => ret(i + 1) := '7'; when "1000" => ret(i + 1) := '8'; when "1001" => ret(i + 1) := '9'; when "1010" => ret(i + 1) := 'a'; when "1011" => ret(i + 1) := 'b'; when "1100" => ret(i + 1) := 'c'; when "1101" => ret(i + 1) := 'd'; when "1110" => ret(i + 1) := 'e'; when "1111" => ret(i + 1) := 'f'; when others => ret(i + 1) := '0'; end case; end loop; return ret; end function; function esl_conv_lv (str : STRING; base : integer; len : integer) return STD_LOGIC_VECTOR is variable ret : STD_LOGIC_VECTOR(len - 1 downto 0); variable val : integer := 0; variable pos : boolean := true; variable i : integer; begin loop_main: for i in 1 to str'length loop if str(i) = ' ' or str(i) = HT or str(i) = CR or str(i) = LF then exit loop_main; elsif str(i) = '-' then pos := false; else case base is when 10 => if '0' <= str(i) and str(i) <= '9' then val := val*10 + character'pos(str(i)) - character'pos('0'); else val := val*10; end if; when others => val := 0; end case; end if; end loop; if pos = false then val := val * (-1); end if; ret := conv_std_logic_vector(val, len); return ret; end function; end package body; -- synthesis translate_on -- XSIP watermark, do not delete 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689

gpl-3.0

makestuff/comm-fpga

ss/vhdl/sync-recv/tb_unit/sync_recv_tb.vhdl

1

3670

-- -- Copyright (C) 2009-2012 Chris McClelland -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Lesser General Public License for more details. -- -- You should have received a copy of the GNU Lesser General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; entity sync_recv_tb is end entity; architecture behavioural of sync_recv_tb is signal sysClk : std_logic; -- main system clock signal dispClk : std_logic; -- display version of sysClk, which leads it by 4ns -- Serial in signal serClk : std_logic; signal serData : std_logic; -- Parallel out signal recvData : std_logic_vector(7 downto 0); signal recvValid : std_logic; -- Detect rising serClk edges signal serClk_prev : std_logic; signal serClkFE : std_logic; begin -- Instantiate sync_recv module for testing uut: entity work.sync_recv port map( clk_in => sysClk, -- Serial in serClkFE_in => serClkFE, serData_in => serData, -- Parallel out recvData_out => recvData, recvValid_out => recvValid ); -- Infer registers process(sysClk) begin if ( rising_edge(sysClk) ) then serClk_prev <= serClk; end if; end process; -- Detect rising edges on serClk serClkFE <= '1' when serClk = '0' and serClk_prev = '1' else '0'; -- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time -- for signals in GTKWave. process begin sysClk <= '0'; dispClk <= '1'; wait for 10 ns; dispClk <= '0'; wait for 10 ns; loop dispClk <= '1'; wait for 4 ns; sysClk <= '1'; wait for 6 ns; dispClk <= '0'; wait for 4 ns; sysClk <= '0'; wait for 6 ns; end loop; end process; -- Drive serClk process begin serClk <= '0'; loop wait until rising_edge(sysClk); wait until rising_edge(sysClk); wait until rising_edge(sysClk); wait until rising_edge(sysClk); serClk <= not(serClk); end loop; end process; -- Drive the sync serial signals process procedure sendByte(constant b : in std_logic_vector(7 downto 0)) is begin serData <= '0'; -- start bit wait until rising_edge(serClk); serData <= b(0); -- bit 0 wait until rising_edge(serClk); serData <= b(1); -- bit 1 wait until rising_edge(serClk); serData <= b(2); -- bit 2 wait until rising_edge(serClk); serData <= b(3); -- bit 3 wait until rising_edge(serClk); serData <= b(4); -- bit 4 wait until rising_edge(serClk); serData <= b(5); -- bit 5 wait until rising_edge(serClk); serData <= b(6); -- bit 6 wait until rising_edge(serClk); serData <= b(7); -- bit 7 wait until rising_edge(serClk); serData <= '1'; -- stop bit wait until rising_edge(serClk); end procedure; procedure pause(constant n : in integer) is variable i : integer; begin for i in 1 to n loop wait until rising_edge(serClk); end loop; end procedure; begin serData <= '1'; pause(4); sendByte(x"55"); sendByte(x"5B"); sendByte(x"5A"); serData <= 'Z'; -- tri-state data line after final send (AVR disables sender) wait; end process; end architecture;

gpl-3.0

nickg/nvc

test/regress/link3.vhd

1

2986

-- From OSVVM -- use std.textio.all ; package NamePkg is type NamePType is protected procedure Set (NameIn : String) ; impure function Get (DefaultName : string := "") return string ; impure function GetOpt return string ; impure function IsSet return boolean ; procedure Clear ; -- clear name procedure Deallocate ; -- effectively alias to clear name end protected NamePType ; end package NamePkg ; package body NamePkg is type NamePType is protected body variable NamePtr : line ; ------------------------------------------------------------ procedure Set (NameIn : String) is ------------------------------------------------------------ begin deallocate(NamePtr) ; NamePtr := new string'(NameIn) ; end procedure Set ; ------------------------------------------------------------ impure function Get (DefaultName : string := "") return string is ------------------------------------------------------------ begin if NamePtr = NULL then return DefaultName ; else return NamePtr.all ; end if ; end function Get ; ------------------------------------------------------------ impure function GetOpt return string is ------------------------------------------------------------ begin if NamePtr = NULL then return NUL & "" ; else return NamePtr.all ; end if ; end function GetOpt ; ------------------------------------------------------------ impure function IsSet return boolean is ------------------------------------------------------------ begin return NamePtr /= NULL ; end function IsSet ; ------------------------------------------------------------ procedure Clear is -- clear name ------------------------------------------------------------ begin deallocate(NamePtr) ; end procedure Clear ; ------------------------------------------------------------ procedure Deallocate is -- clear name ------------------------------------------------------------ begin Clear ; end procedure Deallocate ; end protected body NamePType ; end package body NamePkg ; ------------------------------------------------------------------------------- use work.namepkg.all; package other_pkg is type otherptype is protected procedure do_clear; end protected; end package; package body other_pkg is type otherptype is protected body variable n : nameptype; procedure do_clear is begin n.clear; end procedure; end protected body; end package body; ------------------------------------------------------------------------------- entity link3 is end entity; use work.other_pkg.all; architecture test of link3 is shared variable p : otherptype; begin p1: process is begin p.do_clear; wait; end process; end architecture;

gpl-3.0

Darkin47/Zynq-TX-UTT

Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_indet_btt.vhd

3

60736

------------------------------------------------------------------------------- -- axi_datamover_indet_btt.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_indet_btt.vhd -- -- Description: -- This file implements the DataMover S2MM Indeterminate BTT support module. -- This Module keeps track of the incoming data stream and generates a transfer -- descriptor for each AXI MMap Burst worth of data loaded in the Data FIFO. -- This information is stored in a separate FIFO that the Predictive Transfer -- Calculator fetches sequentially as it is generating commands for the AXI MMap -- bus. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library lib_pkg_v1_0_2; Use lib_pkg_v1_0_2.lib_pkg.clog2; library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_sfifo_autord; use axi_datamover_v5_1_10.axi_datamover_skid_buf; Use axi_datamover_v5_1_10.axi_datamover_stbs_set; Use axi_datamover_v5_1_10.axi_datamover_stbs_set_nodre; ------------------------------------------------------------------------------- entity axi_datamover_indet_btt is generic ( C_SF_FIFO_DEPTH : integer range 128 to 8192 := 128; -- Sets the depth of the Data FIFO C_IBTT_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8; -- Sets the width of the sf2pcc_xfer_bytes port C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2; -- Sets the bit width of the starting address offset port -- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH) C_MAX_BURST_LEN : Integer range 2 to 256 := 16; -- Indicates what is set as the allowed max burst length for AXI4 -- transfers C_MMAP_DWIDTH : Integer range 32 to 1024 := 32; -- Indicates the width of the AXI4 MMap data path C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Indicates the width of the stream data path C_ENABLE_SKID_BUF : string := "11111"; C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_ENABLE_DRE : Integer range 0 to 1 := 0; C_FAMILY : String := "virtex7" -- Specifies the target FPGA Family ); port ( -- Clock input -------------------------------------------- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ----------------------------------------------------------- -- Write Data Controller I/O ---------------------------------------------------------- -- ibtt2wdc_stbs_asserted : Out std_logic_vector(7 downto 0); -- -- Indicates the number of asserted WSTRB bits for the -- -- associated output stream data beat -- -- ibtt2wdc_eop : Out std_logic; -- -- Write End of Packet flag output to Write Data Controller -- -- ibtt2wdc_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); -- -- Write DATA output to Write Data Controller -- -- ibtt2wdc_tstrb : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); -- -- Write DATA output to Write Data Controller -- -- ibtt2wdc_tlast : Out std_logic; -- -- Write LAST output to Write Data Controller -- -- ibtt2wdc_tvalid : Out std_logic; -- -- Write VALID output to Write Data Controller -- -- wdc2ibtt_tready : In std_logic; -- -- Write READY input from Write Data Controller -- --------------------------------------------------------------------------------------- -- DRE Stream In ---------------------------------------------------------------------- -- dre2ibtt_tvalid : In std_logic; -- -- DRE Stream VALID Output -- -- ibtt2dre_tready : Out Std_logic; -- -- DRE Stream READY input -- -- dre2ibtt_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- DRE Stream DATA input -- -- dre2ibtt_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- DRE Stream STRB input -- -- dre2ibtt_tlast : In std_logic; -- -- DRE Xfer LAST input -- -- dre2ibtt_eop : In std_logic; -- -- DRE Stream end of Stream packet flag -- -------------------------------------------------------------------------------------- -- Starting Address Offset Input ------------------------------------------------- -- dre2ibtt_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); -- -- Used by Packing logic to set the initial data slice position for the -- -- packing operation. Packing is only needed if the MMap and Stream Data -- -- widths do not match. This input is sampled on the first valid DRE Stream In -- -- input databeat of a packet. -- -- -- ----------------------------------------------------------------------------------- -- Store and Forward Command Calculator Interface --------------------------------------- -- sf2pcc_xfer_valid : Out std_logic; -- -- Indicates that at least 1 xfer descriptor entry is in in the XFER_DESCR_FIFO -- -- pcc2sf_xfer_ready : in std_logic; -- -- Indicates that a full burst of data has been loaded into the data FIFO -- -- -- sf2pcc_cmd_cmplt : Out std_logic; -- -- Indicates that this is the final xfer for an associated command loaded -- -- into the Realigner by the IBTTCC interface -- -- -- sf2pcc_packet_eop : Out std_logic; -- -- Indicates the end of a Stream Packet corresponds to the pending -- -- xfer data described by this xfer descriptor -- -- sf2pcc_xfer_bytes : Out std_logic_vector(C_IBTT_XFER_BYTES_WIDTH-1 downto 0) -- -- This byte count is used by the IBTTCC for setting up the spawned child -- -- commands. The IBTTCC must use this count to generate the appropriate -- -- LEN value to put out on the AXI4 Write Addr Channel and the WSTRB on the AXI4 -- -- Write Data Channel. -- ----------------------------------------------------------------------------------------- ); end entity axi_datamover_indet_btt; architecture implementation of axi_datamover_indet_btt is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Functions ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_cntr_width -- -- Function Description: -- This function calculates the needed counter bit width from the -- number of count sates needed (input). -- ------------------------------------------------------------------- function funct_get_cntr_width (num_cnt_values : integer) return integer is Variable temp_cnt_width : Integer := 0; begin if (num_cnt_values <= 2) then temp_cnt_width := 1; elsif (num_cnt_values <= 4) then temp_cnt_width := 2; elsif (num_cnt_values <= 8) then temp_cnt_width := 3; elsif (num_cnt_values <= 16) then temp_cnt_width := 4; elsif (num_cnt_values <= 32) then temp_cnt_width := 5; elsif (num_cnt_values <= 64) then temp_cnt_width := 6; elsif (num_cnt_values <= 128) then temp_cnt_width := 7; else temp_cnt_width := 8; end if; Return (temp_cnt_width); end function funct_get_cntr_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 4 and 32. THis is used for sizing the SRL based XD FIFO. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 4) then temp_pwr2 := 4; elsif (input_value <= 8) then temp_pwr2 := 8; elsif (input_value <= 16) then temp_pwr2 := 16; else temp_pwr2 := 32; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- -- Constants Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant BITS_PER_BYTE : integer := 8; Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH; Constant STRM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/BITS_PER_BYTE; Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/BITS_PER_BYTE; Constant STRM_STRBS_ASSERTED_WIDTH : integer := clog2(STRM_WSTB_WIDTH)+1; -- Constant DATA_FIFO_DFACTOR : integer := 4; -- set buffer to 4 times the Max allowed Burst Length -- Constant DATA_FIFO_DEPTH : integer := C_MAX_BURST_LEN*DATA_FIFO_DFACTOR; Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH; Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+MMAP_WSTB_WIDTH*C_ENABLE_S2MM_TKEEP+2; -- Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+STRB_CNTR_WIDTH+2; Constant DATA_FIFO_CNT_WIDTH : integer := clog2(DATA_FIFO_DEPTH)+1; Constant BURST_CNTR_WIDTH : integer := clog2(C_MAX_BURST_LEN); Constant MAX_BURST_DBEATS : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(C_MAX_BURST_LEN-1, BURST_CNTR_WIDTH); Constant DBC_ONE : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, BURST_CNTR_WIDTH); Constant BYTE_CNTR_WIDTH : integer := C_IBTT_XFER_BYTES_WIDTH; Constant BYTES_PER_MMAP_DBEAT : integer := C_MMAP_DWIDTH/BITS_PER_BYTE; Constant BYTES_PER_STRM_DBEAT : integer := C_STREAM_DWIDTH/BITS_PER_BYTE; --Constant MAX_BYTE_CNT : integer := C_MAX_BURST_LEN*BYTES_PER_DBEAT; --Constant NUM_STRB_BITS : integer := BYTES_PER_DBEAT; Constant BCNTR_ONE : Unsigned(BYTE_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, BYTE_CNTR_WIDTH); --Constant XD_FIFO_DEPTH : integer := 16; Constant XD_FIFO_DEPTH : integer := funct_rnd2pwr_of_2(DATA_FIFO_DEPTH/C_MAX_BURST_LEN); Constant XD_FIFO_CNT_WIDTH : integer := clog2(XD_FIFO_DEPTH)+1; Constant XD_FIFO_WIDTH : integer := BYTE_CNTR_WIDTH+2; Constant MMAP_STBS_ASSERTED_WIDTH : integer := 8; Constant SKIDBUF2WDC_DWIDTH : integer := C_MMAP_DWIDTH + MMAP_STBS_ASSERTED_WIDTH; Constant SKIDBUF2WDC_STRB_WIDTH : integer := SKIDBUF2WDC_DWIDTH/BITS_PER_BYTE; --Constant NUM_ZEROS_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH; Constant STRB_CNTR_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH; -- Signals signal sig_wdc2ibtt_tready : std_logic := '0'; signal sig_ibtt2wdc_tvalid : std_logic := '0'; signal sig_ibtt2wdc_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tstrb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tlast : std_logic := '0'; signal sig_ibtt2wdc_eop : std_logic := '0'; signal sig_push_data_fifo : std_logic := '0'; signal sig_pop_data_fifo : std_logic := '0'; signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_data_fifo_dvalid : std_logic := '0'; signal sig_data_fifo_full : std_logic := '0'; signal sig_data_fifo_rd_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0'); signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0'); signal sig_push_xd_fifo : std_logic := '0'; signal sig_pop_xd_fifo : std_logic := '0'; signal sig_xd_fifo_data_in : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_xd_fifo_data_out : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_xd_fifo_dvalid : std_logic := '0'; signal sig_xd_fifo_full : std_logic := '0'; signal sig_tmp : std_logic := '0'; signal sig_strm_in_ready : std_logic := '0'; signal sig_good_strm_dbeat : std_logic := '0'; signal sig_good_tlast_dbeat : std_logic := '0'; signal sig_dre2ibtt_tlast_reg : std_logic := '0'; signal sig_dre2ibtt_eop_reg : std_logic := '0'; signal sig_burst_dbeat_cntr : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_incr_dbeat_cntr : std_logic := '0'; signal sig_clr_dbeat_cntr : std_logic := '0'; signal sig_clr_dbc_reg : std_logic := '0'; signal sig_dbc_max : std_logic := '0'; signal sig_pcc2ibtt_xfer_ready : std_logic := '0'; signal sig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_ld_byte_cntr : std_logic := '0'; signal sig_incr_byte_cntr : std_logic := '0'; signal sig_clr_byte_cntr : std_logic := '0'; signal sig_fifo_tstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); signal sig_num_ls_zeros : integer range 0 to STRM_WSTB_WIDTH := 0; signal sig_ls_assert_found : std_logic := '0'; signal sig_num_ms_zeros : integer range 0 to STRM_WSTB_WIDTH := 0; signal sig_ms_assert_found : std_logic := '0'; -- signal sig_num_zeros : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0'); -- signal sig_num_ones : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0'); signal sig_stbs2sfcc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0'); signal sig_stbs2wdc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0'); signal sig_skidbuf_in_tready : std_logic := '0'; signal sig_skidbuf_in_tvalid : std_logic := '0'; signal sig_skidbuf_in_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0'); signal sig_skidbuf_in_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_skidbuf_in_tlast : std_logic := '0'; signal sig_skidbuf_in_eop : std_logic := '0'; signal sig_skidbuf_out_tready : std_logic := '0'; signal sig_skidbuf_out_tvalid : std_logic := '0'; signal sig_skidbuf_out_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0'); signal sig_skidbuf_out_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_skidbuf_out_tlast : std_logic := '0'; signal sig_skidbuf_out_eop : std_logic := '0'; signal sig_enable_dbcntr : std_logic := '0'; signal sig_good_fifo_write : std_logic := '0'; begin --(architecture implementation) -- Write Data Controller I/O sig_wdc2ibtt_tready <= wdc2ibtt_tready ; ibtt2wdc_tvalid <= sig_ibtt2wdc_tvalid ; ibtt2wdc_tdata <= sig_ibtt2wdc_tdata ; ibtt2wdc_tstrb <= sig_ibtt2wdc_tstrb ; ibtt2wdc_tlast <= sig_ibtt2wdc_tlast ; ibtt2wdc_eop <= sig_ibtt2wdc_eop ; ibtt2wdc_stbs_asserted <= sig_ibtt2wdc_stbs_asserted; -- PCC I/O sf2pcc_xfer_valid <= sig_xd_fifo_dvalid; sig_pcc2ibtt_xfer_ready <= pcc2sf_xfer_ready; sf2pcc_packet_eop <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH+1); sf2pcc_cmd_cmplt <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH); sf2pcc_xfer_bytes <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH-1 downto 0); -- DRE Stream In ibtt2dre_tready <= sig_strm_in_ready; -- sig_strm_in_ready <= not(sig_xd_fifo_full) and -- not(sig_data_fifo_full); sig_good_strm_dbeat <= dre2ibtt_tvalid and sig_strm_in_ready; sig_good_tlast_dbeat <= sig_good_strm_dbeat and dre2ibtt_tlast; -- Burst Packet Counter Logic ------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_DBC_STUFF -- -- Process Description: -- Just a register for data beat counter signals. -- ------------------------------------------------------------- REG_DBC_STUFF : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_dre2ibtt_tlast_reg <= '0'; sig_dre2ibtt_eop_reg <= '0'; sig_clr_dbc_reg <= '0'; else sig_dre2ibtt_tlast_reg <= dre2ibtt_tlast; sig_dre2ibtt_eop_reg <= dre2ibtt_eop; sig_clr_dbc_reg <= sig_clr_dbeat_cntr; end if; end if; end process REG_DBC_STUFF; -- sig_clr_dbc_reg <= sig_clr_dbeat_cntr; -- Increment the dataBeat counter on a data fifo wide -- load condition. If packer logic is enabled, this will -- only occur when a full fifo data width has been collected -- from the Stream input. sig_incr_dbeat_cntr <= sig_good_strm_dbeat and sig_enable_dbcntr; -- Check to see if a max burst len of databeats have been -- loaded into the FIFO sig_dbc_max <= '1' when (sig_burst_dbeat_cntr = MAX_BURST_DBEATS) Else '0'; -- Start the counter over at a max burst len boundary or at -- the end of the packet. sig_clr_dbeat_cntr <= '1' when (sig_dbc_max = '1' and sig_good_strm_dbeat = '1' and sig_enable_dbcntr = '1') or (sig_good_tlast_dbeat = '1' and sig_enable_dbcntr = '1') Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DBC_CMTR -- -- Process Description: -- The Databeat Counter keeps track of how many databeats have -- been loaded into the Data FIFO. When a max burst worth of -- databeats have been loaded (or a TLAST encountered), the -- XD FIFO can be loaded with a transfer data set to be sent -- to the IBTTCC. -- ------------------------------------------------------------- IMP_DBC_CMTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_clr_dbeat_cntr = '1') then sig_burst_dbeat_cntr <= (others => '0'); elsif (sig_incr_dbeat_cntr = '1') then sig_burst_dbeat_cntr <= sig_burst_dbeat_cntr + DBC_ONE; else null; -- hold current value end if; end if; end process IMP_DBC_CMTR; ----- Byte Counter Logic ----------------------------------------------- sig_clr_byte_cntr <= sig_clr_dbc_reg and not(sig_good_strm_dbeat); sig_ld_byte_cntr <= sig_clr_dbc_reg and sig_good_strm_dbeat; sig_incr_byte_cntr <= sig_good_strm_dbeat; sig_byte_cntr_incr_value <= RESIZE(UNSIGNED(sig_stbs2sfcc_asserted), BYTE_CNTR_WIDTH); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_BYTE_CMTR -- -- Process Description: -- Keeps a running byte count per burst packet loaded into the -- xfer FIFO. It is based on the strobes set on the incoming -- Stream dbeat. -- ------------------------------------------------------------- IMP_BYTE_CMTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_clr_byte_cntr = '1') then sig_byte_cntr <= (others => '0'); elsif (sig_ld_byte_cntr = '1') then sig_byte_cntr <= sig_byte_cntr_incr_value; elsif (sig_incr_byte_cntr = '1') then sig_byte_cntr <= sig_byte_cntr + sig_byte_cntr_incr_value; else null; -- hold current value end if; end if; end process IMP_BYTE_CMTR; ------------------------------------------------------------ -- Instance: I_IBTTCC_STBS_SET -- -- Description: -- Instance of the asserted strobe counter for the IBTTCC -- interface. -- ------------------------------------------------------------ SAME_WIDTH_NO_DRE : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate begin I_IBTTCC_STBS_SET : entity axi_datamover_v5_1_10.axi_datamover_stbs_set_nodre generic map ( C_STROBE_WIDTH => STRM_WSTB_WIDTH ) port map ( tstrb_in => dre2ibtt_tstrb, num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv ); end generate SAME_WIDTH_NO_DRE; DIFF_WIDTH_OR_DRE : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate begin I_IBTTCC_STBS_SET : entity axi_datamover_v5_1_10.axi_datamover_stbs_set generic map ( C_STROBE_WIDTH => STRM_WSTB_WIDTH ) port map ( tstrb_in => dre2ibtt_tstrb, num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv ); end generate DIFF_WIDTH_OR_DRE; ----- Xfer Descriptor FIFO Logic ----------------------------------------------- sig_push_xd_fifo <= sig_clr_dbc_reg ; sig_pop_xd_fifo <= sig_pcc2ibtt_xfer_ready and sig_xd_fifo_dvalid ; sig_xd_fifo_data_in <= sig_dre2ibtt_eop_reg & -- (TLAST for the input Stream) sig_dre2ibtt_tlast_reg & -- (TLAST for the IBTTCC command) std_logic_vector(sig_byte_cntr); -- Number of bytes in this xfer ------------------------------------------------------------ -- Instance: I_XD_FIFO -- -- Description: -- Implement the Transfer Desciptor (XD) FIFO. This FIFO holds -- the individual child command xfer descriptors used by the -- IBTTCC to generate the commands sent to the Address Cntlr and -- the Data Cntlr. -- ------------------------------------------------------------ I_XD_FIFO : entity axi_datamover_v5_1_10.axi_datamover_sfifo_autord generic map ( C_DWIDTH => XD_FIFO_WIDTH , C_DEPTH => XD_FIFO_DEPTH , C_DATA_CNT_WIDTH => XD_FIFO_CNT_WIDTH , C_NEED_ALMOST_EMPTY => 0 , C_NEED_ALMOST_FULL => 1 , C_USE_BLKMEM => 0 , C_FAMILY => C_FAMILY ) port map ( -- Inputs SFIFO_Sinit => mmap_reset , SFIFO_Clk => primary_aclk , SFIFO_Wr_en => sig_push_xd_fifo , SFIFO_Din => sig_xd_fifo_data_in , SFIFO_Rd_en => sig_pop_xd_fifo , SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW , -- Outputs SFIFO_DValid => sig_xd_fifo_dvalid , SFIFO_Dout => sig_xd_fifo_data_out , SFIFO_Full => sig_xd_fifo_full , SFIFO_Empty => open , SFIFO_Almost_full => sig_tmp , SFIFO_Almost_empty => open , SFIFO_Rd_count => open , SFIFO_Rd_count_minus1 => open , SFIFO_Wr_count => open , SFIFO_Rd_ack => open ); ---------------------------------------------------------------- -- Packing Logic ------------------------------------------ ---------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: OMIT_PACKING -- -- If Generate Description: -- Omits any packing logic in the Store and Forward module. -- The Stream and MMap data widths are the same. -- ------------------------------------------------------------ OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate begin -- The data beat counter is always enabled when the packer -- is omitted. sig_enable_dbcntr <= '1'; sig_good_fifo_write <= sig_good_strm_dbeat; sig_strm_in_ready <= not(sig_xd_fifo_full) and not(sig_data_fifo_full) and not (sig_tmp); GEN_S2MM_TKEEP_ENABLE5 : if C_ENABLE_S2MM_TKEEP = 1 generate begin -- Concatonate the Stream inputs into the single FIFO data -- word input value sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker dre2ibtt_tlast & -- Tlast marker dre2ibtt_tstrb & -- TSTRB Value dre2ibtt_tdata; -- data value end generate GEN_S2MM_TKEEP_ENABLE5; GEN_S2MM_TKEEP_DISABLE5 : if C_ENABLE_S2MM_TKEEP = 0 generate begin -- Concatonate the Stream inputs into the single FIFO data -- word input value sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker dre2ibtt_tlast & -- Tlast marker --dre2ibtt_tstrb & -- TSTRB Value dre2ibtt_tdata; -- data value end generate GEN_S2MM_TKEEP_DISABLE5; end generate OMIT_PACKING; ------------------------------------------------------------ -- If Generate -- -- Label: INCLUDE_PACKING -- -- If Generate Description: -- Includes packing logic in the IBTT Store and Forward -- module. The MMap Data bus is wider than the Stream width. -- ------------------------------------------------------------ INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate Constant TLAST_WIDTH : integer := 1; -- bit Constant EOP_WIDTH : integer := 1; -- bit Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH; Constant STRB_SLICE_WIDTH : integer := STRM_WSTB_WIDTH; Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH + EOP_WIDTH; Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO); Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, OFFSET_CNTR_WIDTH); Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH); -- Types ----------------------------------------------------------------------------- type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of std_logic_vector(DATA_SLICE_WIDTH-1 downto 0); type lsig_strb_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of std_logic_vector(STRB_SLICE_WIDTH-1 downto 0); type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0); -- local signals signal lsig_data_slice_reg : lsig_data_slice_type; signal lsig_strb_slice_reg : lsig_strb_slice_type; signal lsig_flag_slice_reg : lsig_flag_slice_type; signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0'); signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0'); signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0'); signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0'); signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0'); signal lsig_ld_offset : std_logic := '0'; signal lsig_incr_offset : std_logic := '0'; signal lsig_offset_cntr_eq_max : std_logic := '0'; signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0'); signal lsig_combined_strb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); signal lsig_tlast_or : std_logic := '0'; signal lsig_eop_or : std_logic := '0'; signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0'); signal lsig_partial_eop_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0'); signal lsig_packer_full : std_logic := '0'; signal lsig_packer_empty : std_logic := '0'; signal lsig_set_packer_full : std_logic := '0'; signal lsig_good_push2fifo : std_logic := '0'; signal lsig_first_dbeat : std_logic := '0'; begin -- Generate the stream ready sig_strm_in_ready <= not(sig_xd_fifo_full) and not(sig_tmp) and (not(lsig_packer_full) or lsig_good_push2fifo) ; -- Enable the Data Beat counter when the packer is -- going full sig_enable_dbcntr <= lsig_set_packer_full; -- Assign the flag indicating that a fifo write is going -- to occur at the next rising clock edge. sig_good_fifo_write <= lsig_good_push2fifo; GEN_S2MM_TKEEP_ENABLE6 : if C_ENABLE_S2MM_TKEEP = 1 generate begin -- Format the composite FIFO input data word sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit lsig_tlast_or & lsig_combined_strb & lsig_combined_data ; -- LS Bits end generate GEN_S2MM_TKEEP_ENABLE6; GEN_S2MM_TKEEP_DISABLE6 : if C_ENABLE_S2MM_TKEEP = 0 generate begin -- Format the composite FIFO input data word sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit lsig_tlast_or & --lsig_combined_strb & lsig_combined_data ; -- LS Bits end generate GEN_S2MM_TKEEP_DISABLE6; -- Generate a flag indicating a write to the DataFIFO -- is going to complete lsig_good_push2fifo <= lsig_packer_full and not(sig_data_fifo_full); -- Generate the control that loads the starting address -- offset for the next input packet lsig_ld_offset <= lsig_first_dbeat and sig_good_strm_dbeat; -- Generate the control for incrementing the offset counter lsig_incr_offset <= sig_good_strm_dbeat; -- Generate a flag indicating the packer input register -- array is full or has loaded the last data beat of -- the input paket lsig_set_packer_full <= sig_good_strm_dbeat and (dre2ibtt_tlast or lsig_offset_cntr_eq_max); -- Check to see if the offset counter has reached its max -- value lsig_offset_cntr_eq_max <= '1' --when (lsig_0ffset_cntr = OFFSET_CNT_MAX) when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX) Else '0'; -- Mux between the input start offset and the offset counter -- output to use for the packer slice load control. lsig_0ffset_to_to_use <= UNSIGNED(dre2ibtt_strt_addr_offset) when (lsig_first_dbeat = '1') Else lsig_0ffset_cntr; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_OFFSET_LD_MARKER -- -- Process Description: -- Implements the flop indicating the first databeat of -- an input data packet. -- ------------------------------------------------------------- IMP_OFFSET_LD_MARKER : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_first_dbeat <= '1'; elsif (sig_good_strm_dbeat = '1' and dre2ibtt_tlast = '0') then lsig_first_dbeat <= '0'; Elsif (sig_good_strm_dbeat = '1' and dre2ibtt_tlast = '1') Then lsig_first_dbeat <= '1'; else null; -- Hold Current State end if; end if; end process IMP_OFFSET_LD_MARKER; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_OFFSET_CNTR -- -- Process Description: -- Implements the address offset counter that is used to -- steer the data loads into the packer register slices. -- Note that the counter has to be loaded with the starting -- offset plus one to sync up with the data input. ------------------------------------------------------------- IMP_OFFSET_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_0ffset_cntr <= (others => '0'); Elsif (lsig_ld_offset = '1') Then lsig_0ffset_cntr <= UNSIGNED(dre2ibtt_strt_addr_offset) + OFFSET_CNT_ONE; elsif (lsig_incr_offset = '1') then lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE; else null; -- Hold Current State end if; end if; end process IMP_OFFSET_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PACK_REG_FULL -- -- Process Description: -- Implements the Packer Register full/empty flags -- ------------------------------------------------------------- IMP_PACK_REG_FULL : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_packer_full <= '0'; lsig_packer_empty <= '1'; Elsif (lsig_set_packer_full = '1' and lsig_packer_full = '0') Then lsig_packer_full <= '1'; lsig_packer_empty <= '0'; elsif (lsig_set_packer_full = '0' and lsig_good_push2fifo = '1') then lsig_packer_full <= '0'; lsig_packer_empty <= '1'; else null; -- Hold Current State end if; end if; end process IMP_PACK_REG_FULL; ------------------------------------------------------------ -- For Generate -- -- Label: DO_REG_SLICES -- -- For Generate Description: -- -- Implements the Packng Register Slices -- -- ------------------------------------------------------------ DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate begin -- generate the register load enable for each slice segment based -- on the address offset count value lsig_segment_ld(slice_index) <= '1' when (sig_good_strm_dbeat = '1' and TO_INTEGER(lsig_0ffset_to_to_use) = slice_index) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DATA_SLICE -- -- Process Description: -- Implement a data register slice abd Strobe register slice -- for the packer (upsizer). -- ------------------------------------------------------------- IMP_DATA_SLICE : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_data_slice_reg(slice_index) <= (others => '0'); lsig_strb_slice_reg(slice_index) <= (others => '0'); elsif (lsig_segment_ld(slice_index) = '1') then lsig_data_slice_reg(slice_index) <= dre2ibtt_tdata; lsig_strb_slice_reg(slice_index) <= dre2ibtt_tstrb; -- optional clear of slice reg elsif (lsig_segment_ld(slice_index) = '0' and lsig_good_push2fifo = '1') then lsig_data_slice_reg(slice_index) <= (others => '0'); lsig_strb_slice_reg(slice_index) <= (others => '0'); else null; -- Hold Current State end if; end if; end process IMP_DATA_SLICE; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FLAG_SLICE -- -- Process Description: -- Implement a flag register slice for the packer. -- ------------------------------------------------------------- IMP_FLAG_SLICE : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_flag_slice_reg(slice_index) <= (others => '0'); elsif (lsig_segment_ld(slice_index) = '1') then lsig_flag_slice_reg(slice_index) <= dre2ibtt_tlast & -- bit 1 dre2ibtt_eop; -- bit 0 elsif (lsig_segment_ld(slice_index) = '0' and lsig_good_push2fifo = '1') then lsig_flag_slice_reg(slice_index) <= (others => '0'); else null; -- Hold Current State end if; end if; end process IMP_FLAG_SLICE; end generate DO_REG_SLICES; -- Do the OR functions of the Flags ------------------------------------- lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ; lsig_eop_or <= lsig_partial_eop_or(MMAP2STRM_WIDTH_RATO-1); lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1); lsig_partial_eop_or(0) <= lsig_flag_slice_reg(0)(0); ------------------------------------------------------------ -- For Generate -- -- Label: DO_FLAG_OR -- -- For Generate Description: -- Implement the OR of the TLAST and EOP Error flags. -- -- -- ------------------------------------------------------------ DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate begin lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or --lsig_partial_tlast_or(slice_index); lsig_flag_slice_reg(slice_index)(1); lsig_partial_eop_or(slice_index) <= lsig_partial_eop_or(slice_index-1) or --lsig_partial_eop_or(slice_index); lsig_flag_slice_reg(slice_index)(0); end generate DO_FLAG_OR; ------------------------------------------------------------ -- For Generate -- -- Label: DO_DATA_COMBINER -- -- For Generate Description: -- Combines the Data Slice register and Strobe slice register -- outputs into a single data and single strobe vector used for -- input data to the Data FIFO. -- -- ------------------------------------------------------------ DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate begin lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto (slice_index-1)*DATA_SLICE_WIDTH) <= lsig_data_slice_reg(slice_index-1); lsig_combined_strb((slice_index*STRB_SLICE_WIDTH)-1 downto (slice_index-1)*STRB_SLICE_WIDTH) <= lsig_strb_slice_reg(slice_index-1); end generate DO_DATA_COMBINER; end generate INCLUDE_PACKING; -- Data FIFO Logic ------------------------------------------ --sig_push_data_fifo <= sig_good_strm_dbeat; sig_push_data_fifo <= sig_good_fifo_write; sig_pop_data_fifo <= sig_skidbuf_in_tready and sig_data_fifo_dvalid; -- -- Concatonate the Stream inputs into the single FIFO data in value -- sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker -- dre2ibtt_tlast & -- dre2ibtt_tstrb & -- dre2ibtt_tdata; ------------------------------------------------------------ -- Instance: I_DATA_FIFO -- -- Description: -- Implements the Store and Forward data FIFO -- ------------------------------------------------------------ I_DATA_FIFO : entity axi_datamover_v5_1_10.axi_datamover_sfifo_autord generic map ( C_DWIDTH => DATA_FIFO_WIDTH , C_DEPTH => DATA_FIFO_DEPTH , C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH , C_NEED_ALMOST_EMPTY => 0 , C_NEED_ALMOST_FULL => 0 , C_USE_BLKMEM => 1 , C_FAMILY => C_FAMILY ) port map ( -- Inputs SFIFO_Sinit => mmap_reset , SFIFO_Clk => primary_aclk , SFIFO_Wr_en => sig_push_data_fifo , SFIFO_Din => sig_data_fifo_data_in , SFIFO_Rd_en => sig_pop_data_fifo , SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW , -- Outputs SFIFO_DValid => sig_data_fifo_dvalid , SFIFO_Dout => sig_data_fifo_data_out , SFIFO_Full => sig_data_fifo_full , SFIFO_Empty => open , SFIFO_Almost_full => open , SFIFO_Almost_empty => open , SFIFO_Rd_count => sig_data_fifo_rd_cnt , SFIFO_Rd_count_minus1 => open , SFIFO_Wr_count => sig_data_fifo_wr_cnt , SFIFO_Rd_ack => open ); ------------------------------------------------------------------------- ---------------- Asserted TSTRB calculation logic --------------------- ------------------------------------------------------------------------- GEN_S2MM_TKEEP_ENABLE7 : if C_ENABLE_S2MM_TKEEP = 1 generate begin -- Rip the write strobe value from the FIFO output data sig_fifo_tstrb_out <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto C_MMAP_DWIDTH); end generate GEN_S2MM_TKEEP_ENABLE7; GEN_S2MM_TKEEP_DISBALE7 : if C_ENABLE_S2MM_TKEEP = 0 generate begin sig_fifo_tstrb_out <= (others => '1'); end generate GEN_S2MM_TKEEP_DISBALE7; ------------------------------------------------------------ -- Instance: I_WDC_STBS_SET -- -- Description: -- Instance of the asserted strobe counter for the WDC -- interface. -- ------------------------------------------------------------ SAME_WIDTH_NO_DRE_WDC : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate begin I_WDC_STBS_SET : entity axi_datamover_v5_1_10.axi_datamover_stbs_set_nodre generic map ( C_STROBE_WIDTH => MMAP_WSTB_WIDTH ) port map ( tstrb_in => sig_fifo_tstrb_out, num_stbs_asserted => sig_stbs2wdc_asserted ); end generate SAME_WIDTH_NO_DRE_WDC; DIFF_WIDTH_OR_DRE_WDC : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate begin I_WDC_STBS_SET : entity axi_datamover_v5_1_10.axi_datamover_stbs_set generic map ( C_STROBE_WIDTH => MMAP_WSTB_WIDTH ) port map ( tstrb_in => sig_fifo_tstrb_out, num_stbs_asserted => sig_stbs2wdc_asserted ); end generate DIFF_WIDTH_OR_DRE_WDC; ------------------------------------------------------------------------- ------- Isolation Skid Buffer Logic (needed for Fmax timing) ----------- ------------------------------------------------------------------------- -- Skid Buffer output assignments ----------- sig_skidbuf_out_tready <= sig_wdc2ibtt_tready; sig_ibtt2wdc_tvalid <= sig_skidbuf_out_tvalid; sig_ibtt2wdc_tdata <= sig_skidbuf_out_tdata(C_MMAP_DWIDTH-1 downto 0) ; sig_ibtt2wdc_tstrb <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH-1 downto 0) ; sig_ibtt2wdc_tlast <= sig_skidbuf_out_tlast ; -- Rip the EOP marker from the MS bit of the skid output strobes sig_ibtt2wdc_eop <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH) ; -- Rip the upper 8 bits of the skid output data for the strobes asserted value sig_ibtt2wdc_stbs_asserted <= sig_skidbuf_out_tdata(SKIDBUF2WDC_DWIDTH-1 downto C_MMAP_DWIDTH); -- Skid Buffer input assignments ----------- sig_skidbuf_in_tvalid <= sig_data_fifo_dvalid; sig_skidbuf_in_eop <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-1); sig_skidbuf_in_tlast <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-2); -- Steal the extra input strobe bit and use it for the EOP marker ---- sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop & ---- sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto ---- C_MMAP_DWIDTH); ---- sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop & sig_fifo_tstrb_out; -- Insert the Strobes Asserted count in the extra (MS) data byte -- for the skid buffer sig_skidbuf_in_tdata <= sig_stbs2wdc_asserted & sig_data_fifo_data_out(C_MMAP_DWIDTH-1 downto 0); ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '1' generate begin ------------------------------------------------------------ -- Instance: I_INDET_BTT_SKID_BUF -- -- Description: -- Instance for the Store and Forward isolation Skid Buffer -- which is required to achieve Fmax timing. Note that this -- skid buffer is 1 byte wider than the stream data width to -- allow for the asserted strobes count to be passed through -- it. The EOP marker is inserted in the extra strobe slot. -- ------------------------------------------------------------ I_INDET_BTT_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => SKIDBUF2WDC_DWIDTH ) port map ( -- System Ports aclk => primary_aclk , arst => mmap_reset , -- Shutdown control (assert for 1 clk pulse) skid_stop => LOGIC_LOW , -- Slave Side (Stream Data Input) s_valid => sig_skidbuf_in_tvalid , s_ready => sig_skidbuf_in_tready , s_data => sig_skidbuf_in_tdata , s_strb => sig_skidbuf_in_tstrb , s_last => sig_skidbuf_in_tlast , -- Master Side (Stream Data Output m_valid => sig_skidbuf_out_tvalid , m_ready => sig_skidbuf_out_tready , m_data => sig_skidbuf_out_tdata , m_strb => sig_skidbuf_out_tstrb , m_last => sig_skidbuf_out_tlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '0' generate begin sig_skidbuf_out_tvalid <= sig_skidbuf_in_tvalid; sig_skidbuf_in_tready <= sig_skidbuf_out_tready ; sig_skidbuf_out_tdata <= sig_skidbuf_in_tdata ; sig_skidbuf_out_tstrb <= sig_skidbuf_in_tstrb ; sig_skidbuf_out_tlast <= sig_skidbuf_in_tlast ; end generate DISABLE_AXIS_SKID; end implementation;

gpl-3.0

nickg/nvc

test/regress/elab32.vhd

1

358

entity sub is port ( x : in bit_vector ); end entity; architecture test of sub is begin end architecture; ------------------------------------------------------------------------------- entity elab32 is end entity; architecture test of elab32 is signal b : bit; begin uut: entity work.sub port map ( x(0) => b ); end architecture;

gpl-3.0

Darkin47/Zynq-TX-UTT

Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_sg_v4_1/hdl/src/vhdl/axi_sg_pkg.vhd

13

6615

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_pkg.vhd -- Description: This package contains various constants and functions for -- AXI SG Engine. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package axi_sg_pkg is ------------------------------------------------------------------------------- -- Function declarations ------------------------------------------------------------------------------- -- Convert boolean to a std_logic function bo2int (value : boolean) return integer; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- AXI Response Values constant OKAY_RESP : std_logic_vector(1 downto 0) := "00"; constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01"; constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10"; constant DECERR_RESP : std_logic_vector(1 downto 0) := "11"; -- Misc Constants constant CMD_BASE_WIDTH : integer := 40; constant SG_BTT_WIDTH : integer := 7; constant SG_ADDR_LSB : integer := 6; -- Interrupt Coalescing constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0'); constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001"; constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0'); -- Constants Used in Desc Updates constant DESC_STS_TYPE : std_logic := '1'; constant DESC_DATA_TYPE : std_logic := '0'; -- DataMover Command / Status Constants constant DATAMOVER_STS_CMDDONE_BIT : integer := 7; constant DATAMOVER_STS_SLVERR_BIT : integer := 6; constant DATAMOVER_STS_DECERR_BIT : integer := 5; constant DATAMOVER_STS_INTERR_BIT : integer := 4; constant DATAMOVER_STS_TAGMSB_BIT : integer := 3; constant DATAMOVER_STS_TAGLSB_BIT : integer := 0; constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0; constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22; constant DATAMOVER_CMD_TYPE_BIT : integer := 23; constant DATAMOVER_CMD_DSALSB_BIT : integer := 24; constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29; constant DATAMOVER_CMD_EOF_BIT : integer := 30; constant DATAMOVER_CMD_DRR_BIT : integer := 31; constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32; -- Note: Bit offset require adding ADDR WIDTH to get to actual bit index constant DATAMOVER_CMD_ADDRMSB_BOFST : integer := 31; constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32; constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35; constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36; constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39; -- Descriptor field bits constant DESC_STS_INTERR_BIT : integer := 28; constant DESC_STS_SLVERR_BIT : integer := 29; constant DESC_STS_DECERR_BIT : integer := 30; constant DESC_STS_CMPLTD_BIT : integer := 31; -- IOC Bit on descriptor update -- Stored in LSB of TAG field then catinated on status word from primary -- datamover (i.e. DESCTYPE & IOC & STATUS & Bytes Transferred). constant DESC_IOC_TAG_BIT : integer := 32; end axi_sg_pkg; ------------------------------------------------------------------------------- -- PACKAGE BODY ------------------------------------------------------------------------------- package body axi_sg_pkg is ------------------------------------------------------------------------------- -- Boolean to Integer ------------------------------------------------------------------------------- function bo2int ( value : boolean) return integer is variable value_int : integer; begin if(value)then value_int := 1; else value_int := 0; end if; return value_int; end function bo2int; end package body axi_sg_pkg;

gpl-3.0

nickg/nvc

test/regress/issue29.vhd

5

769

entity sub is generic ( width : integer ); port ( x : in bit_vector(width - 1 downto 0); y : in bit_vector; z : out bit_vector(width - 1 downto 0) ); end entity; architecture test of sub is begin z <= x and y after 1 us; end architecture; ------------------------------------------------------------------------------- entity issue29 is end entity; architecture rtl of issue29 is signal z : bit_vector(7 downto 0); begin sub_i: entity work.sub generic map ( width => 8 ) port map ( x => X"ab", y => X"cd", z => z ); process is begin wait for 2 us; assert z = "10001001"; wait; end process; end architecture;

gpl-3.0

nickg/nvc

lib/std.08/textio.vhd

1

6827

------------------------------------------------------------------------------- -- Copyright (C) 2012-2021 Nick Gasson -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- TEXTIO package as defined by IEEE 1076-2008 ------------------------------------------------------------------------------- package textio is type line is access string; type text is file of string; type side is (RIGHT, LEFT); subtype width is natural; function justify (value : string; justified : side := right; field : width := 0) return string; file input : text open READ_MODE is "STD_INPUT"; file output : text open WRITE_MODE is "STD_OUTPUT"; procedure readline (file f: text; l: inout line); procedure read (l : inout line; value : out bit; good : out boolean ); procedure read (l : inout line; value : out bit ); procedure read (l : inout line; value : out bit_vector; good : out boolean ); procedure read (l : inout line; value : out bit_vector ); procedure read (l : inout line; value : out boolean; good : out boolean ); procedure read (l : inout line; value : out boolean ); procedure read (l : inout line; value : out character; good : out boolean ); procedure read (l : inout line; value : out character ); procedure read (l : inout line; value : out integer; good : out boolean ); procedure read (l : inout line; value : out integer ); procedure read (l : inout line; value : out real; good : out boolean ); procedure read (l : inout line; value : out real ); procedure read (l : inout line; value : out string; good : out boolean ); procedure read (l : inout line; value : out string ); procedure read (l : inout line; value : out time; good : out boolean ); procedure read (l : inout line; value : out time ); procedure sread (l : inout line; value : out string; strlen : out natural); alias string_read is sread [line, string, natural]; alias bread is read [line, bit_vector, boolean]; alias bread is read [line, bit_vector]; alias binary_read is read [line, bit_vector, boolean]; alias binary_read is read [line, bit_vector]; procedure oread (l : inout line; value : out bit_vector; good : out boolean); procedure oread (l : inout line; value : out bit_vector); alias octal_read is oread [line, bit_vector, boolean]; alias octal_read is oread [line, bit_vector]; procedure hread (l : inout line; value : out bit_vector; good : out boolean); procedure hread (l : inout line; value : out bit_vector); alias hex_read is hread [line, bit_vector, boolean]; alias hex_read is hread [line, bit_vector]; procedure writeline (file f : text; l : inout line); procedure tee (file f : text; l : inout line); procedure write (l : inout line; value : in bit; justified : in side := right; field : in width := 0 ); procedure write (l : inout line; value : in bit_vector; justified : in side := right; field : in width := 0 ); procedure write (l : inout line; value : in boolean; justified : in side := right; field : in width := 0 ); procedure write (l : inout line; value : in character; justified : in side := right; field : in width := 0 ); procedure write (l : inout line; value : in integer; justified : in side := right; field : in width := 0 ); procedure write (l : inout line; value : in real; justified : in side:= right; field : in width := 0; digits : in natural:= 0 ); procedure write (l : inout line; value : in real; format : in string ); procedure write (l : inout line; value : in string; justified : in side := right; field : in width := 0 ); procedure write (l : inout line; value : in time; justified : in side := right; field : in width := 0; unit : in time := ns ); alias swrite is write [line, string, side, width]; alias string_write is write [line, string, side, width]; alias bwrite is write [line, bit_vector, side, width]; alias binary_write is write [line, bit_vector, side, width]; procedure owrite (l : inout line; value : in bit_vector; justified : in side := right; field : in width := 0); alias octal_write is owrite [line, bit_vector, side, width]; procedure hwrite (l : inout line; value : in bit_vector; justified : in side := right; field : in width := 0); alias hex_write is hwrite [line, bit_vector, side, width]; end package;

gpl-3.0

nickg/nvc

test/regress/ieee1.vhd

5

688

library ieee; use ieee.std_logic_1164.all; entity ieee1 is end entity; architecture test of ieee1 is begin process is variable a, b, c : std_logic_vector(3 downto 0); variable d : std_logic_vector(5 downto 0); begin a := ( '0', '1', '0', '0' ); b := ( '1', '0', '1', '0' ); assert_a: assert ((a(3) or b(3)) = '1') report "a"; c := (a or b); assert c(3) = '1' report "c(3)"; assert c(0) = '0' report "c(0)"; assert_b: assert c = ( '1', '1', '1', '0' ) report "b"; d(4 downto 1) := (a or b); assert d = ( 'U', '1', '1', '1', '0', 'U' ); wait; end process; end architecture;

gpl-3.0

nickg/nvc

test/regress/textio7.vhd

1

1237

-- -- Test READ for real types -- entity textio7 is end entity; use std.textio.all; architecture test of textio7 is procedure check(value, expect : real) is variable l : line; begin assert abs(value - expect) < 0.0001 report "value=" & real'image(value) & " expect=" & real'image(expect) severity failure; write(l, value); writeline(output, l); deallocate(l); end procedure; begin main: process is variable r : real; variable l : line; begin l := new string'("1.23"); read(l, r); check(r, 1.23); deallocate(l); l := new string'("+4"); read(l, r); check(r, 4.0); deallocate(l); l := new string'("-0.001"); read(l, r); check(r, -0.001); deallocate(l); l := new string'("1.23e2"); read(l, r); check(r, 123.0); deallocate(l); l := new string'("1.994500e+03"); read(l, r); check(r, 1994.5); deallocate(l); l := new string'(" 1.994500e+03"); read(l, r); check(r, 1994.5); deallocate(l); wait; end process; end architecture;

gpl-3.0

nickg/nvc

test/jit/ieeewarn.vhd

1

485

package ieeewarn is constant enabled : boolean; end package; library nvc; use nvc.sim_pkg.all; package body ieeewarn is constant enabled : boolean := ieee_warnings; -- Should not be folded end package body; ------------------------------------------------------------------------------- entity ieeewarn_e is end entity; use work.ieeewarn; architecture a of ieeewarn_e is constant e : boolean := ieeewarn.enabled; -- Also shouldn't be folded begin end architecture;

gpl-3.0

Darkin47/Zynq-TX-UTT

Vivado_HLS/image_contrast_adj/solution1/impl/vhdl/project.srcs/sources_1/ip/doHistStretch_ap_fmul_2_max_dsp_32/xbip_bram18k_v3_0_2/hdl/xbip_bram18k_v3_0_vh_rfs.vhd

9

96728

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block obXXhxRlTaHjCpJV4uPTkRwgR3GpcvDfot0y8VTPyFxY1NMmmd9nxF2yYzxY4op4aE47wJsPh3ch Ifk4Z8Oulg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hmzRe/Qr+6nIcxuhkGdjIkYxpmHpO2VQJwayWf2lxaeB8TRqxhanf79tJphTIT7qZJNlaejd5WBb CQ1aMumla5wg4w9VFCJ3RfIX218tcMJOolbR14I3sidO+tsZwyzxKpPgnD/kd4T877IMOTrRvnIx 6PdsYAvnCf3xQFi7I2w= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 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gpl-3.0

Darkin47/Zynq-TX-UTT

Vivado_HLS/image_contrast_adj/solution1/impl/ip/tmp.srcs/sources_1/ip/doHistStretch_ap_fmul_2_max_dsp_32/xbip_bram18k_v3_0_2/hdl/xbip_bram18k_v3_0_vh_rfs.vhd

9

96728

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block obXXhxRlTaHjCpJV4uPTkRwgR3GpcvDfot0y8VTPyFxY1NMmmd9nxF2yYzxY4op4aE47wJsPh3ch Ifk4Z8Oulg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hmzRe/Qr+6nIcxuhkGdjIkYxpmHpO2VQJwayWf2lxaeB8TRqxhanf79tJphTIT7qZJNlaejd5WBb CQ1aMumla5wg4w9VFCJ3RfIX218tcMJOolbR14I3sidO+tsZwyzxKpPgnD/kd4T877IMOTrRvnIx 6PdsYAvnCf3xQFi7I2w= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block x0fTehxzghnOkOVVaF5ZPRso1LEjaAT4Ij9Za1bH3Oj/tMEqkw6sMVwuBHCx+9OVt2006A4ekCrO o6bGNZkP9ZTi3rPDQxJqDp8sg5+LnJfN79zDXHa15RdmKwVkjgf3nwhk4ny+EFYVb0Y54aV8MR9O zAXbiBIex84Cf/eo0y4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Ic1yv1cEiezEPDPgDJrMxh9C2VwWquV93tLinJarxYj+AmqpzKzI5K1H2OQZe7dbFN/MWnbwXkU3 VZ4HTFO2LNY6CAQ7agHefFUAhNGwX0QRTr7VGuTBYmzhsAHdeMqszybd5GeRvJKr6TK24gNATQrN nT2+HjrdVmQVjknT/su1Hfhm/cYUP3DwaHb/YUh3OhjGRMtE/ZGv2ChKMu2k7R9vmk5m/gNYJ2nE 08anLKgzUjVJXgO49+Y0G/wzgXuirkniHC7vyzJoNICrYz2RxJ622p1143uKw66xJyQQhrd2qIBT Jl/KhVnIuyuaJXAkrqwFPiigy+IHyR/snmCbug== `protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block LFux42eTG7g9Qxp237PDkKB2zzr08ZwHBtwQiK5Ci6HPYEcDQC5ARtEmy5K+FX4t3iGvCUCf7B7w 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gpl-3.0

nickg/nvc

test/lower/access1.vhd

2

433

entity access1 is end entity; architecture test of access1 is type list; type list_ptr is access list; type list is record link : list_ptr; value : integer; end record; procedure list_add(l : inout list_ptr; v : integer) is variable n : list_ptr; begin n := new list; n.link := l; n.value := v; l := n; end procedure; begin end architecture;

gpl-3.0

Darkin47/Zynq-TX-UTT

Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/doHistStretch_fdiv_32ns_32ns_32_16.vhd

5

3100

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2016.1 -- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity doHistStretch_fdiv_32ns_32ns_32_16 is generic ( ID : integer := 2; NUM_STAGE : integer := 16; din0_WIDTH : integer := 32; din1_WIDTH : integer := 32; dout_WIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); din1 : in std_logic_vector(din1_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of doHistStretch_fdiv_32ns_32ns_32_16 is --------------------- Component --------------------- component doHistStretch_ap_fdiv_14_no_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); s_axis_b_tvalid : in std_logic; s_axis_b_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(31 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal b_tvalid : std_logic; signal b_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(31 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- doHistStretch_ap_fdiv_14_no_dsp_32_u : component doHistStretch_ap_fdiv_14_no_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, s_axis_b_tvalid => b_tvalid, s_axis_b_tdata => b_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; b_tvalid <= '1'; b_tdata <= din1_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; din1_buf1 <= din1; end if; end if; end process; end architecture;

gpl-3.0

nickg/nvc

test/jit/record2.vhd

1

804

package pack3 is type int_vector is array (natural range <>) of integer; type rec is record x : integer; y : integer; a : int_vector(1 to 3); z : integer; end record; constant r : rec; end package; package body pack3 is constant r : rec := (1, 2, (3, 4, 5), 6); end package body; ------------------------------------------------------------------------------- package pack4 is function sum_fields return integer; end package; use work.pack3.all; package body pack4 is function sum_fields return integer is variable sum : integer := r.x + r.y + r.z; begin --for i in r.a'range loop for i in 1 to 3 loop sum := sum + r.a(i); end loop; return sum; end function; end package body;

gpl-3.0

nickg/nvc

test/regress/issue352.vhd

1

1177

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; -- use ieee.numeric_std.all; -- use ieee.std_logic_unsigned.all; entity issue352 is end entity; architecture arch of issue352 is signal FixRealKCM_F400_uid2_Rtemp : std_logic_vector(4 downto 0) := "11111"; signal R :std_logic_vector(5 downto 0); function check_dims(x : unsigned) return unsigned is alias ax : unsigned(1 to x'length) is x; variable s : string(1 to x'length); begin assert x'low >= unsigned'low; assert x'high <= unsigned'high; for i in 1 to x'length loop s(i) := std_logic'image(ax(i))(2); end loop; report s; return x; end function; begin -- R <= "000000" - (FixRealKCM_F400_uid2_Rtemp(4) & FixRealKCM_F400_uid2_Rtemp(4 downto 0)); R <= std_logic_vector(unsigned'(unsigned'("00000") - check_dims(unsigned (FixRealKCM_F400_uid2_Rtemp(4) & FixRealKCM_F400_uid2_Rtemp(4 downto 0))))); process is begin wait for 1 ns; assert R = "000001"; assert FixRealKCM_F400_uid2_Rtemp'last_event = time'high; wait; end process; end architecture;

gpl-3.0

nickg/nvc

test/regress/wait18.vhd

1

580

entity wait18 is end entity; library ieee; use ieee.std_logic_1164.all; architecture test of wait18 is signal clk, d, q : std_logic := '0'; begin process (clk) is begin if rising_edge(clk) then q <= d; end if; end process; process is begin clk <= '1' after 10 ns; d <= '1'; wait for 11 ns; assert q = '1'; wait; end process; postponed process (clk) is begin if rising_edge(clk) then assert q = '1'; end if; end process; end architecture;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_gpio_v2_0/58435b11/hdl/src/vhdl/axi_gpio.vhd

5

33293

------------------------------------------------------------------------------- -- AXI_GPIO - entity/architecture pair ------------------------------------------------------------------------------- -- -- *************************************************************************** -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- *************************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_gpio.vhd -- Version: v2.0 -- Description: General Purpose I/O for AXI Interface -- ------------------------------------------------------------------------------- -- Structure: -- axi_gpio.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- gpio_core.vhd ------------------------------------------------------------------------------- -- Author: KSB -- History: -- ~~~~~~~~~~~~~~ -- KSB 07/28/09 -- ^^^^^^^^^^^^^^ -- First version of axi_gpio. Based on xps_gpio 2.00a -- -- KSB 05/20/10 -- ^^^^^^^^^^^^^^ -- Updated for holes in address range -- ~~~~~~~~~~~~~~ -- VB 09/23/10 -- ^^^^^^^^^^^^^^ -- Updated for axi_lite_ipfi_v1_01_a -- ~~~~~~~~~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; use std.textio.all; ------------------------------------------------------------------------------- -- AXI common package of the proc common library is used for different -- function declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- axi_gpio_v2_0 library is used for axi4 component declarations ------------------------------------------------------------------------------- library axi_lite_ipif_v3_0; use axi_lite_ipif_v3_0.ipif_pkg.calc_num_ce; use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE; use axi_lite_ipif_v3_0.ipif_pkg.SLV64_ARRAY_TYPE; ------------------------------------------------------------------------------- -- axi_gpio_v2_0 library is used for interrupt controller component -- declarations ------------------------------------------------------------------------------- library interrupt_control_v3_1; ------------------------------------------------------------------------------- -- axi_gpio_v2_0 library is used for axi_gpio component declarations ------------------------------------------------------------------------------- library axi_gpio_v2_0; ------------------------------------------------------------------------------- -- Defination of Generics : -- ------------------------------------------------------------------------------- -- AXI generics -- C_BASEADDR -- Base address of the core -- C_HIGHADDR -- Permits alias of address space -- by making greater than xFFF -- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits) -- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits) -- C_FAMILY -- XILINX FPGA family -- C_INSTANCE -- Instance name ot the core in the EDK system -- C_GPIO_WIDTH -- GPIO Data Bus width. -- C_ALL_INPUTS -- Inputs Only. -- C_INTERRUPT_PRESENT -- GPIO Interrupt. -- C_IS_BIDIR -- Selects gpio_io_i as input. -- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. -- C_TRI_DEFAULT -- GPIO_TRI Register reset value. -- C_IS_DUAL -- Dual Channel GPIO. -- C_ALL_INPUTS_2 -- Channel2 Inputs only. -- C_IS_BIDIR_2 -- Selects gpio2_io_i as input. -- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. -- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Defination of Ports -- ------------------------------------------------------------------------------- -- AXI signals -- s_axi_awaddr -- AXI Write address -- s_axi_awvalid -- Write address valid -- s_axi_awready -- Write address ready -- s_axi_wdata -- Write data -- s_axi_wstrb -- Write strobes -- s_axi_wvalid -- Write valid -- s_axi_wready -- Write ready -- s_axi_bresp -- Write response -- s_axi_bvalid -- Write response valid -- s_axi_bready -- Response ready -- s_axi_araddr -- Read address -- s_axi_arvalid -- Read address valid -- s_axi_arready -- Read address ready -- s_axi_rdata -- Read data -- s_axi_rresp -- Read response -- s_axi_rvalid -- Read valid -- s_axi_rready -- Read ready -- GPIO Signals -- gpio_io_i -- Channel 1 General purpose I/O in port -- gpio_io_o -- Channel 1 General purpose I/O out port -- gpio_io_t -- Channel 1 General purpose I/O -- TRI-STATE control port -- gpio2_io_i -- Channel 2 General purpose I/O in port -- gpio2_io_o -- Channel 2 General purpose I/O out port -- gpio2_io_t -- Channel 2 General purpose I/O -- TRI-STATE control port -- System Signals -- s_axi_aclk -- AXI Clock -- s_axi_aresetn -- AXI Reset -- ip2intc_irpt -- AXI GPIO Interrupt ------------------------------------------------------------------------------- entity axi_gpio is generic ( -- -- System Parameter C_FAMILY : string := "virtex7"; -- -- AXI Parameters C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9; C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32; -- -- GPIO Parameter C_GPIO_WIDTH : integer range 1 to 32 := 32; C_GPIO2_WIDTH : integer range 1 to 32 := 32; C_ALL_INPUTS : integer range 0 to 1 := 0; C_ALL_INPUTS_2 : integer range 0 to 1 := 0; C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 C_INTERRUPT_PRESENT : integer range 0 to 1 := 0; C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF"; C_IS_DUAL : integer range 0 to 1 := 0; C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF" ); port ( -- AXI interface Signals -------------------------------------------------- s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; -- Interrupt--------------------------------------------------------------- ip2intc_irpt : out std_logic; -- GPIO Signals------------------------------------------------------------ gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0) ); ------------------------------------------------------------------------------- -- fan-out attributes for XST ------------------------------------------------------------------------------- attribute MAX_FANOUT : string; attribute MAX_FANOUT of s_axi_aclk : signal is "10000"; attribute MAX_FANOUT of s_axi_aresetn : signal is "10000"; ------------------------------------------------------------------------------- -- Attributes for MPD file ------------------------------------------------------------------------------- attribute IP_GROUP : string ; attribute IP_GROUP of axi_gpio : entity is "LOGICORE"; attribute SIGIS : string ; attribute SIGIS of s_axi_aclk : signal is "Clk"; attribute SIGIS of s_axi_aresetn : signal is "Rst"; attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH"; end entity axi_gpio; ------------------------------------------------------------------------------- -- Architecture Section ------------------------------------------------------------------------------- architecture imp of axi_gpio is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ------------------------------------------------------------------------------- -- constant added for webtalk information ------------------------------------------------------------------------------- --function chr(sl: std_logic) return character is -- variable c: character; -- begin -- case sl is -- when '0' => c:= '0'; -- when '1' => c:= '1'; -- when 'Z' => c:= 'Z'; -- when 'U' => c:= 'U'; -- when 'X' => c:= 'X'; -- when 'W' => c:= 'W'; -- when 'L' => c:= 'L'; -- when 'H' => c:= 'H'; -- when '-' => c:= '-'; -- end case; -- return c; -- end chr; -- --function str(slv: std_logic_vector) return string is -- variable result : string (1 to slv'length); -- variable r : integer; -- begin -- r := 1; -- for i in slv'range loop -- result(r) := chr(slv(i)); -- r := r + 1; -- end loop; -- return result; -- end str; type bo2na_type is array (boolean) of natural; -- boolean to --natural conversion constant bo2na : bo2na_type := (false => 0, true => 1); ------------------------------------------------------------------------------- -- Function Declarations ------------------------------------------------------------------------------- type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean; ---------------------------------------------------------------------------- -- This function returns the number of elements that are true in -- a boolean array. ---------------------------------------------------------------------------- function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is variable n : natural := 0; begin for i in ba'range loop n := n + bo2na(ba(i)); end loop; return n; end; ---------------------------------------------------------------------------- -- This function returns a num_ce integer array that is constructed by -- taking only those elements of superset num_ce integer array -- that will be defined by the current case. -- The superset num_ce array is given by parameter num_ce_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE; num_ce_by_ard : INTEGER_ARRAY_TYPE ) return INTEGER_ARRAY_TYPE is variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := num_ce_by_ard(j); i := i+1; j := j+1; end loop; return res; end; ---------------------------------------------------------------------------- -- This function returns a addr_range array that is constructed by -- taking only those elements of superset addr_range array -- that will be defined by the current case. -- The superset addr_range array is given by parameter addr_range_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE; addr_range_by_ard : SLV64_ARRAY_TYPE ) return SLV64_ARRAY_TYPE is variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := addr_range_by_ard(2*j); res(i+1) := addr_range_by_ard((2*j)+1); i := i+2; j := j+1; end loop; return res; end; function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE ) return std_logic_vector is variable res : std_logic_vector(0 to 31); begin res := (others => '0'); if defined_ards(defined_ards'right) then res(0 to 3) := "1111"; res(12) := '1'; res(13) := '1'; res(15) := '1'; else res(0 to 3) := "1111"; end if; return res; end; ---------------------------------------------------------------------------- -- This function returns the maximum width amongst the two GPIO Channels -- and if there is only one channel, it returns just the width of that -- channel. ---------------------------------------------------------------------------- function max_width( dual_channel : INTEGER; channel1_width : INTEGER; channel2_width : INTEGER ) return INTEGER is begin if (dual_channel = 0) then return channel1_width; else if (channel1_width > channel2_width) then return channel1_width; else return channel2_width; end if; end if; end; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant INTR_TYPE : integer := 5; constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100"; constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF"; constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F"; constant MAX_GPIO_WIDTH : integer := max_width (C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH); constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := qual_ard_addr_range_array( (true,C_INTERRUPT_PRESENT=1), (ZERO_ADDR_PAD & X"00000000", ZERO_ADDR_PAD & GPIO_HIGHADDR, ZERO_ADDR_PAD & INTR_BASEADDR, ZERO_ADDR_PAD & INTR_HIGHADDR ) ); constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := qual_ard_num_ce_array( (true,C_INTERRUPT_PRESENT=1), (4,16) ); constant ARD_CE_VALID : std_logic_vector(0 to 31) := qual_ard_ce_valid( (true,C_INTERRUPT_PRESENT=1) ); constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1)) := (others => 5); constant C_USE_WSTRB : integer := 0; constant C_DPHASE_TIMEOUT : integer := 8; ------------------------------------------------------------------------------- -- Signal and Type Declarations ------------------------------------------------------------------------------- signal ip2bus_intrevent : std_logic_vector(0 to 1); signal GPIO_xferAck_i : std_logic; signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); -- IPIC Used Signals signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1); signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_rnw : std_logic; signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na (C_INTERRUPT_PRESENT=1)); signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15); signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15); signal intr_wr_ce_or_reduce : std_logic; signal intr_rd_ce_or_reduce : std_logic; signal ip2Bus_RdAck_intr_reg_hole : std_logic; signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic; signal ip2Bus_WrAck_intr_reg_hole : std_logic; signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic; signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1); signal bus2ip_clk : std_logic; signal bus2ip_reset : std_logic; signal bus2ip_resetn : std_logic; signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal intr2bus_wrack : std_logic; signal intr2bus_rdack : std_logic; signal intr2bus_error : std_logic; signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_wrack_i : std_logic; signal ip2bus_wrack_i_D1 : std_logic; signal ip2bus_rdack_i : std_logic; signal ip2bus_rdack_i_D1 : std_logic; signal ip2bus_error_i : std_logic; signal IP2INTC_Irpt_i : std_logic; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- begin -- architecture IMP AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, C_FAMILY => C_FAMILY ) port map ( S_AXI_ACLK => s_axi_aclk, S_AXI_ARESETN => s_axi_aresetn, S_AXI_AWADDR => s_axi_awaddr, S_AXI_AWVALID => s_axi_awvalid, S_AXI_AWREADY => s_axi_awready, S_AXI_WDATA => s_axi_wdata, S_AXI_WSTRB => s_axi_wstrb, S_AXI_WVALID => s_axi_wvalid, S_AXI_WREADY => s_axi_wready, S_AXI_BRESP => s_axi_bresp, S_AXI_BVALID => s_axi_bvalid, S_AXI_BREADY => s_axi_bready, S_AXI_ARADDR => s_axi_araddr, S_AXI_ARVALID => s_axi_arvalid, S_AXI_ARREADY => s_axi_arready, S_AXI_RDATA => s_axi_rdata, S_AXI_RRESP => s_axi_rresp, S_AXI_RVALID => s_axi_rvalid, S_AXI_RREADY => s_axi_rready, -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, Bus2IP_Resetn => bus2ip_resetn, IP2Bus_Data => ip2bus_data_i_D1, IP2Bus_WrAck => ip2bus_wrack_i_D1, IP2Bus_RdAck => ip2bus_rdack_i_D1, --IP2Bus_WrAck => ip2bus_wrack_i, --IP2Bus_RdAck => ip2bus_rdack_i, IP2Bus_Error => ip2bus_error_i, Bus2IP_Addr => bus2ip_addr, Bus2IP_Data => bus2ip_data, Bus2IP_RNW => bus2ip_rnw, Bus2IP_BE => bus2ip_be, Bus2IP_CS => bus2ip_cs, Bus2IP_RdCE => bus2ip_rdce, Bus2IP_WrCE => bus2ip_wrce ); ip2bus_data_i <= intr2bus_data or ip2bus_data; ip2bus_wrack_i <= intr2bus_wrack or (GPIO_xferAck_i and not(bus2ip_rnw)) or ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range ip2bus_rdack_i <= intr2bus_rdack or (GPIO_xferAck_i and bus2ip_rnw) or ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2bus_wrack_i_D1 <= '0'; ip2bus_rdack_i_D1 <= '0'; ip2bus_data_i_D1 <= (others => '0'); else ip2bus_wrack_i_D1 <= ip2bus_wrack_i; ip2bus_rdack_i_D1 <= ip2bus_rdack_i; ip2bus_data_i_D1 <= ip2bus_data_i; end if; end if; end process I_WRACK_RDACK_DELAYS; ip2bus_error_i <= intr2bus_error; ---------------------- --REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of -- the core. ---------------------- REG_RESET_FROM_IPIF: process (s_axi_aclk) is begin if(s_axi_aclk'event and s_axi_aclk = '1') then bus2ip_reset <= not(bus2ip_resetn); end if; end process REG_RESET_FROM_IPIF; --------------------------------------------------------------------------- -- Interrupts --------------------------------------------------------------------------- INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate constant NUM_IPIF_IRPT_SRC : natural := 1; constant NUM_CE : integer := 16; signal errack_reserved : std_logic_vector(0 to 1); signal ipif_lvl_interrupts : std_logic_vector(0 to NUM_IPIF_IRPT_SRC-1); begin ipif_lvl_interrupts <= (others => '0'); errack_reserved <= (others => '0'); --- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0' & bus2ip_rdce(14) & "00000"; Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0' & bus2ip_wrce(14) & "00000"; intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or Bus2IP_RdCE(13) or or_reduce(Bus2IP_RdCE(15 to 19)); intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or bus2ip_wrce(13) or or_reduce(bus2ip_wrce(15 to 19)); I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_RdAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole_d1 <= '0'; else ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce; ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and (not ip2Bus_RdAck_intr_reg_hole_d1); end if; end if; end process I_READ_ACK_INTR_HOLES; I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_WrAck_intr_reg_hole_d1 <= '0'; else ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce; ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and (not ip2Bus_WrAck_intr_reg_hole_d1); end if; end if; end process I_WRITE_ACK_INTR_HOLES; INTERRUPT_CONTROL_I : entity interrupt_control_v3_1.interrupt_control generic map ( C_NUM_CE => NUM_CE, C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC, C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, C_INCLUDE_DEV_PENCODER => false, C_INCLUDE_DEV_ISC => false, C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH ) port map ( -- Inputs From the IPIF Bus Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Reset => bus2ip_reset, Bus2IP_Data => bus2ip_data, Bus2IP_BE => bus2ip_be, Interrupt_RdCE => Intrpt_bus2ip_rdce, Interrupt_WrCE => Intrpt_bus2ip_wrce, -- Interrupt inputs from the IPIF sources that will -- get registered in this design IPIF_Reg_Interrupts => errack_reserved, -- Level Interrupt inputs from the IPIF sources IPIF_Lvl_Interrupts => ipif_lvl_interrupts, -- Inputs from the IP Interface IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range), -- Final Device Interrupt Output Intr2Bus_DevIntr => IP2INTC_Irpt_i, -- Status Reply Outputs to the Bus Intr2Bus_DBus => intr2bus_data, Intr2Bus_WrAck => intr2bus_wrack, Intr2Bus_RdAck => intr2bus_rdack, Intr2Bus_Error => intr2bus_error, Intr2Bus_Retry => open, Intr2Bus_ToutSup => open ); -- registering interrupt I_INTR_DELAY: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2intc_irpt <= '0'; else ip2intc_irpt <= IP2INTC_Irpt_i; end if; end if; end process I_INTR_DELAY; end generate INTR_CTRLR_GEN; ----------------------------------------------------------------------- -- Assigning the intr2bus signal to zero's when interrupt is not -- present ----------------------------------------------------------------------- REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate intr2bus_data <= (others => '0'); ip2intc_irpt <= '0'; intr2bus_error <= '0'; intr2bus_rdack <= '0'; intr2bus_wrack <= '0'; ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole <= '0'; end generate REMOVE_INTERRUPT; gpio_core_1 : entity axi_gpio_v2_0.gpio_core generic map ( C_DW => C_S_AXI_DATA_WIDTH, C_AW => C_S_AXI_ADDR_WIDTH, C_GPIO_WIDTH => C_GPIO_WIDTH, C_GPIO2_WIDTH => C_GPIO2_WIDTH, C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH, C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT, C_DOUT_DEFAULT => C_DOUT_DEFAULT, C_TRI_DEFAULT => C_TRI_DEFAULT, C_IS_DUAL => C_IS_DUAL, C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2, C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2, C_FAMILY => C_FAMILY ) port map ( Clk => Bus2IP_Clk, Rst => bus2ip_reset, ABus_Reg => Bus2IP_Addr, BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1), DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1), RNW_Reg => Bus2IP_RNW, GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1), GPIO_xferAck => GPIO_xferAck_i, GPIO_Select => bus2ip_cs(0), GPIO_intr => ip2bus_intrevent(0), GPIO2_intr => ip2bus_intrevent(1), GPIO_IO_I => gpio_io_i, GPIO_IO_O => gpio_io_o, GPIO_IO_T => gpio_io_t, GPIO2_IO_I => gpio2_io_i, GPIO2_IO_O => gpio2_io_o, GPIO2_IO_T => gpio2_io_t ); Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1' and bus2ip_addr (5) = '0'else Bus2IP2_Data_i; BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate Bus2IP1_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH); end generate BUS_CONV_ch1; BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate Bus2IP2_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH); end generate BUS_CONV_ch2; end architecture imp;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/lib_fifo_v1_0/ca55fafe/hdl/src/vhdl/async_fifo_fg.vhd

11

123226

-- async_fifo_fg.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: async_fifo_fg.vhd -- -- Description: -- This HDL file adapts the legacy CoreGen Async FIFO interface to the new -- FIFO Generator async FIFO interface. This wrapper facilitates the "on -- the fly" call of FIFO Generator during design implementation. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- async_fifo_fg.vhd -- | -- |-- fifo_generator_v4_3 -- | -- |-- fifo_generator_v9_3 -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- Revision: $Revision: 1.5.2.68 $ -- Date: $1/15/2008$ -- -- History: -- DET 1/15/2008 Initial Version -- -- DET 7/30/2008 for EDK 11.1 -- ~~~~~~ -- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator -- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs -- only allowed (2**N)-1 depth specification. Parameter is defalted to -- the legacy CoreGen method so current users are not impacted. -- - Incorporated calculation and assignment corrections for the Read and -- Write Pointer Widths. -- - Upgraded to FIFO Generator Version 4.3. -- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO -- Generator instance. -- ^^^^^^ -- -- MSH and DET 3/2/2009 For Lava SP2 -- ~~~~~~ -- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6 -- devices. -- - IfGen used so that legacy FPGA families still use Fifo Generator -- version 4.3. -- ^^^^^^ -- -- DET 2/9/2010 for EDK 12.1 -- ~~~~~~ -- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3. -- ^^^^^^ -- -- DET 3/10/2010 For EDK 12.x -- ~~~~~~ -- -- Per CR553307 -- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1. -- ^^^^^^ -- -- DET 6/18/2010 EDK_MS2 -- ~~~~~~ -- -- Per IR565916 -- - Added derivative part type checks for S6 or V6. -- ^^^^^^ -- -- DET 8/30/2010 EDK_MS4 -- ~~~~~~ -- -- Per CR573867 -- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2. -- - Added all of the AXI parameters and ports. They are not used -- in this application. -- - Updated method for derivative part support using new family -- aliasing function in family_support.vhd. -- - Incorporated an implementation to deal with unsupported FPGA -- parts passed in on the C_FAMILY parameter. -- ^^^^^^ -- -- DET 10/4/2010 EDK 13.1 -- ~~~~~~ -- - Updated the FIFO Generator version from V7.2 to 7.3. -- ^^^^^^ -- -- DET 12/8/2010 EDK 13.1 -- ~~~~~~ -- -- Per CR586109 -- - Updated the FIFO Generator version from V7.3 to 8.1. -- ^^^^^^ -- -- DET 3/2/2011 EDK 13.2 -- ~~~~~~ -- -- Per CR595473 -- - Update to use fifo_generator_v8_2 -- ^^^^^^ -- -- -- RBODDU 08/18/2011 EDK 13.3 -- ~~~~~~ -- - Update to use fifo_generator_v8_3 -- ^^^^^^ -- -- RBODDU 06/07/2012 EDK 14.2 -- ~~~~~~ -- - Update to use fifo_generator_v9_1 -- ^^^^^^ -- RBODDU 06/11/2012 EDK 14.4 -- ~~~~~~ -- - Update to use fifo_generator_v9_2 -- ^^^^^^ -- RBODDU 07/12/2012 EDK 14.5 -- ~~~~~~ -- - Update to use fifo_generator_v9_3 -- ^^^^^^ -- RBODDU 07/12/2012 EDK 14.5 -- ~~~~~~ -- - Update to use fifo_generator_v12_0 -- - Added sleep, wr_rst_busy, and rd_rst_busy signals -- - Changed FULL_FLAGS_RST_VAL to '1' -- ^^^^^^ -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library fifo_generator_v12_0; use fifo_generator_v12_0.all; --library lib_fifo_v1_0; --use lib_fifo_v1_0.lib_fifo_pkg.all; --use lib_fifo_v1_0.family_support.all; -- synopsys translate_off --library XilinxCoreLib; --use XilinxCoreLib.all; -- synopsys translate_on ------------------------------------------------------------------------------- entity async_fifo_fg is generic ( C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth C_FAMILY : String := "virtex5"; -- new for FIFO Gen C_DATA_WIDTH : integer := 16; C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG C_FIFO_DEPTH : integer := 15; C_HAS_ALMOST_EMPTY : integer := 1 ; C_HAS_ALMOST_FULL : integer := 1 ; C_HAS_RD_ACK : integer := 0 ; C_HAS_RD_COUNT : integer := 1 ; C_HAS_RD_ERR : integer := 0 ; C_HAS_WR_ACK : integer := 0 ; C_HAS_WR_COUNT : integer := 1 ; C_HAS_WR_ERR : integer := 0 ; C_RD_ACK_LOW : integer := 0 ; C_RD_COUNT_WIDTH : integer := 3 ; C_RD_ERR_LOW : integer := 0 ; C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0 C_PRELOAD_REGS : integer := 0 ; C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1 C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM C_WR_ACK_LOW : integer := 0 ; C_WR_COUNT_WIDTH : integer := 3 ; C_WR_ERR_LOW : integer := 0 ; C_SYNCHRONIZER_STAGE : integer := 2 -- valid values are 0 to 8 ); port ( Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0'); Wr_en : in std_logic := '1'; Wr_clk : in std_logic := '1'; Rd_en : in std_logic := '0'; Rd_clk : in std_logic := '1'; Ainit : in std_logic := '1'; Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0); Full : out std_logic; Empty : out std_logic; Almost_full : out std_logic; Almost_empty : out std_logic; Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0); Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0); Rd_ack : out std_logic; Rd_err : out std_logic; Wr_ack : out std_logic; Wr_err : out std_logic ); end entity async_fifo_fg; architecture implementation of async_fifo_fg is -- Function delarations ------------------------------------------------------------------- -- Function -- -- Function Name: GetMemType -- -- Function Description: -- Generates the required integer value for the FG instance assignment -- of the C_MEMORY_TYPE parameter. Derived from -- the input memory type parameter C_USE_BLOCKMEM. -- -- FIFO Generator values -- 0 = Any -- 1 = BRAM -- 2 = Distributed Memory -- 3 = Shift Registers -- ------------------------------------------------------------------- function GetMemType (inputmemtype : integer) return integer is Variable memtype : Integer := 0; begin If (inputmemtype = 0) Then -- distributed Memory memtype := 2; else memtype := 1; -- BRAM End if; return(memtype); end function GetMemType; function log2(x : natural) return integer is variable i : integer := 0; variable val: integer := 1; begin if x = 0 then return 0; else for j in 0 to 29 loop -- for loop for XST if val >= x then null; else i := i+1; val := val*2; end if; end loop; -- Fix per CR520627 XST was ignoring this anyway and printing a -- Warning in SRP file. This will get rid of the warning and not -- impact simulation. -- synthesis translate_off assert val >= x report "Function log2 received argument larger" & " than its capability of 2^30. " severity failure; -- synthesis translate_on return i; end if; end function log2; -- Constant Declarations ---------------------------------------------- -- C_FAMILY is directly passed. No need to have family_support function Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd -- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily")); -- Proc_common supports all families Constant FAMILY_IS_SUPPORTED : boolean := true; --not(FAMILY_NOT_SUPPORTED); -- Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or -- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or -- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and -- FAMILY_IS_SUPPORTED; -- Changing this to true Constant FAM_IS_NOT_S3_V4_V5 : boolean := true; -- Get the integer value for a Block memory type fifo generator call Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM); -- Set the required integer value for the FG instance assignment -- of the C_IMPLEMENTATION_TYPE parameter. Derived from -- the input memory type parameter C_MEMORY_TYPE. -- -- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO) -- 1 = Common Clock Shift Register (Synchronous FIFO) -- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO) -- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls -- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls -- Constant FG_IMP_TYPE : integer := 2; --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal PROG_FULL : std_logic; signal PROG_EMPTY : std_logic; signal SBITERR : std_logic; signal DBITERR : std_logic; signal WR_RST_BUSY : std_logic; signal RD_RST_BUSY : std_logic; signal S_AXI_AWREADY : std_logic; signal S_AXI_WREADY : std_logic; signal S_AXI_BID : std_logic_vector(3 DOWNTO 0); signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_BUSER : std_logic_vector(0 downto 0); signal S_AXI_BVALID : std_logic; -- AXI Full/Lite Master Write Channel (Read side) signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0); signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWUSER : std_logic_vector(0 downto 0); signal M_AXI_AWVALID : std_logic; signal M_AXI_WID : std_logic_vector(3 DOWNTO 0); signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0); signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0); signal M_AXI_WLAST : std_logic; signal M_AXI_WUSER : std_logic_vector(0 downto 0); signal M_AXI_WVALID : std_logic; signal M_AXI_BREADY : std_logic; -- AXI Full/Lite Slave Read Channel (Write side) signal S_AXI_ARREADY : std_logic; signal S_AXI_RID : std_logic_vector(3 DOWNTO 0); signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0); signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_RLAST : std_logic; signal S_AXI_RUSER : std_logic_vector(0 downto 0); signal S_AXI_RVALID : std_logic; -- AXI Full/Lite Master Read Channel (Read side) signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0); signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARUSER : std_logic_vector(0 downto 0); signal M_AXI_ARVALID : std_logic; signal M_AXI_RREADY : std_logic; -- AXI Streaming Slave Signals (Write side) signal S_AXIS_TREADY : std_logic; -- AXI Streaming Master Signals (Read side) signal M_AXIS_TVALID : std_logic; signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0); signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TLAST : std_logic; signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0); signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_SBITERR : std_logic; signal AXI_AW_DBITERR : std_logic; signal AXI_AW_OVERFLOW : std_logic; signal AXI_AW_UNDERFLOW : std_logic; signal AXI_AW_PROG_FULL : STD_LOGIC; signal AXI_AW_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Data Channel Signals signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_SBITERR : std_logic; signal AXI_W_DBITERR : std_logic; signal AXI_W_OVERFLOW : std_logic; signal AXI_W_UNDERFLOW : std_logic; signal AXI_W_PROG_FULL : STD_LOGIC; signal AXI_W_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Response Channel Signals signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_SBITERR : std_logic; signal AXI_B_DBITERR : std_logic; signal AXI_B_OVERFLOW : std_logic; signal AXI_B_UNDERFLOW : std_logic; signal AXI_B_PROG_FULL : STD_LOGIC; signal AXI_B_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Address Channel Signals signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_SBITERR : std_logic; signal AXI_AR_DBITERR : std_logic; signal AXI_AR_OVERFLOW : std_logic; signal AXI_AR_UNDERFLOW : std_logic; signal AXI_AR_PROG_FULL : STD_LOGIC; signal AXI_AR_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Data Channel Signals signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_SBITERR : std_logic; signal AXI_R_DBITERR : std_logic; signal AXI_R_OVERFLOW : std_logic; signal AXI_R_UNDERFLOW : std_logic; signal AXI_R_PROG_FULL : STD_LOGIC; signal AXI_R_PROG_EMPTY : STD_LOGIC; -- AXI Streaming FIFO Related Signals signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_SBITERR : std_logic; signal AXIS_DBITERR : std_logic; signal AXIS_OVERFLOW : std_logic; signal AXIS_UNDERFLOW : std_logic; signal AXIS_PROG_FULL : STD_LOGIC; signal AXIS_PROG_EMPTY : STD_LOGIC; begin --(architecture implementation) ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_FAMILY -- -- If Generate Description: -- This IfGen is implemented if an unsupported FPGA family -- is passed in on the C_FAMILY parameter, -- ------------------------------------------------------------ -- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate -- begin -- synthesis translate_off ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_ASSERTION -- -- Process Description: -- Generate a simulation error assertion for an unsupported -- FPGA family string passed in on the C_FAMILY parameter. -- ------------------------------------------------------------- -- DO_ASSERTION : process -- begin -- Wait until second rising wr clock edge to issue assertion -- Wait until Wr_clk = '1'; -- wait until Wr_clk = '0'; -- Wait until Wr_clk = '1'; -- Report an error in simulation environment -- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!" -- severity ERROR; -- Wait; -- halt this process -- end process DO_ASSERTION; -- synthesis translate_on -- Tie outputs to logic low or logic high as required -- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Full <= '0' ; -- : out std_logic; -- Empty <= '1' ; -- : out std_logic; -- Almost_full <= '0' ; -- : out std_logic; -- Almost_empty <= '0' ; -- : out std_logic; -- Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0); -- Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0); -- Rd_ack <= '0' ; -- : out std_logic; -- Rd_err <= '1' ; -- : out std_logic; -- Wr_ack <= '0' ; -- : out std_logic; -- Wr_err <= '1' ; -- : out std_logic -- end generate GEN_NO_FAMILY; ------------------------------------------------------------ -- If Generate -- -- Label: LEGACY_COREGEN_DEPTH -- -- If Generate Description: -- This IfGen implements the FIFO Generator call where -- the User specified depth and count widths follow the -- legacy CoreGen Async FIFO requirements of depth being -- (2**N)-1 and the count widths set to reflect the (2**N)-1 -- FIFO depth. -- -- Special Note: -- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1 -- and the Dcount widths were 1 less than if a full 2**n depth were supported. -- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths -- specified and the Dcount widths smaller by 1 bit. -- This wrapper file has to account for this since the new FIFO Generator -- does not follow this convention for Async FIFOs and expects depths to -- be specified in full 2**n values. -- ------------------------------------------------------------ LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and FAMILY_IS_SUPPORTED) generate -- IfGen Constant Declarations ------------- -- See Special Note above for reasoning behind -- this adjustment of the requested FIFO depth and data count -- widths. Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1; Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH; Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH; -- The programable thresholds are not used so this is housekeeping. Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3; Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4; -- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core -- must be in the range of 4 thru 22. The setting is dependant upon the -- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs -- previous to development of fifo generator do not support separate read and -- write fifo widths (and depths dependant upon the widths) both of the pointer value -- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for -- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it -- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 - -- Asynchronous FIFO v6.1) Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH); Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH); -- Constant zeros for programmable threshold inputs signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- IfGen Signal Declarations -------------- Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0); Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0); --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0); begin -- Rip the LS bits of the write data count and assign to Write Count -- output port Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0); -- Rip the LS bits of the read data count and assign to Read Count -- output port Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0); ------------------------------------------------------------ -- If Generate -- -- Label: V6_S6_AND_LATER -- -- If Generate Description: -- This IFGen Implements the FIFO using fifo_generator_v9_3 -- for FPGA Families that are Virtex-6, Spartan-6, and later. -- ------------------------------------------------------------ V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate begin ------------------------------------------------------------------------------- -- Instantiate the generalized FIFO Generator instance -- -- NOTE: -- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!! -- This is a Coregen FIFO Generator Call module for -- legacy BRAM implementations of an Async FIFo. -- ------------------------------------------------------------------------------- I_ASYNC_FIFO_BRAM : entity fifo_generator_v12_0.fifo_generator_v12_0 generic map( C_COMMON_CLOCK => 0, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => C_DATA_WIDTH, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => C_DATA_WIDTH, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_FAMILY => FAMILY_TO_USE, C_FULL_FLAGS_RST_VAL => 1, C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY, C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 0, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => C_HAS_WR_ERR, C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_HAS_UNDERFLOW => C_HAS_RD_ERR, C_HAS_VALID => C_HAS_RD_ACK, C_HAS_WR_ACK => C_HAS_WR_ACK, C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => FG_IMP_TYPE, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => FG_MEM_TYPE, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => C_WR_ERR_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129 C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129 C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL, C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH, C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH, C_UNDERFLOW_LOW => C_RD_ERR_LOW, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129 C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH, C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE, -- AXI Interface related parameters start here C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0; C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0; C_HAS_SLAVE_CE => 0, -- : integer := 0; C_HAS_MASTER_CE => 0, -- : integer := 0; C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0; C_USE_COMMON_OVERFLOW => 0, -- : integer := 0; C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0; C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH => 4 , -- : integer := 0; C_AXI_ADDR_WIDTH => 32, -- : integer := 0; C_AXI_DATA_WIDTH => 64, -- : integer := 0; C_AXI_LEN_WIDTH => 8, -- : integer := 8; C_AXI_LOCK_WIDTH => 2, -- : integer := 2; C_HAS_AXI_ID => 0, -- : integer := 0; C_HAS_AXI_AWUSER => 0 , -- : integer := 0; C_HAS_AXI_WUSER => 0 , -- : integer := 0; C_HAS_AXI_BUSER => 0 , -- : integer := 0; C_HAS_AXI_ARUSER => 0 , -- : integer := 0; C_HAS_AXI_RUSER => 0 , -- : integer := 0; C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0; C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0; C_AXI_WUSER_WIDTH => 1 , -- : integer := 0; C_AXI_BUSER_WIDTH => 1 , -- : integer := 0; C_AXI_RUSER_WIDTH => 1 , -- : integer := 0; -- AXI Streaming C_HAS_AXIS_TDATA => 0 , -- : integer := 0; C_HAS_AXIS_TID => 0 , -- : integer := 0; C_HAS_AXIS_TDEST => 0 , -- : integer := 0; C_HAS_AXIS_TUSER => 0 , -- : integer := 0; C_HAS_AXIS_TREADY => 1 , -- : integer := 0; C_HAS_AXIS_TLAST => 0 , -- : integer := 0; C_HAS_AXIS_TSTRB => 0 , -- : integer := 0; C_HAS_AXIS_TKEEP => 0 , -- : integer := 0; C_AXIS_TDATA_WIDTH => 64, -- : integer := 1; C_AXIS_TID_WIDTH => 8 , -- : integer := 1; C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1; C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1; C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1; C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Data FIFO C_APPLICATION_TYPE_WACH => 0, -- : integer := 0; C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0; C_APPLICATION_TYPE_RACH => 0, -- : integer := 0; C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH => 0, -- : integer := 0; C_USE_ECC_WDCH => 0, -- : integer := 0; C_USE_ECC_WRCH => 0, -- : integer := 0; C_USE_ECC_RACH => 0, -- : integer := 0; C_USE_ECC_RDCH => 0, -- : integer := 0; C_USE_ECC_AXIS => 0, -- : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH => 32, -- : integer := 1; C_DIN_WIDTH_WDCH => 64, -- : integer := 1; C_DIN_WIDTH_WRCH => 2 , -- : integer := 1; C_DIN_WIDTH_RACH => 32, -- : integer := 1; C_DIN_WIDTH_RDCH => 64, -- : integer := 1; C_DIN_WIDTH_AXIS => 1 , -- : integer := 1; C_WR_DEPTH_WACH => 16 , -- : integer := 16; C_WR_DEPTH_WDCH => 1024, -- : integer := 16; C_WR_DEPTH_WRCH => 16 , -- : integer := 16; C_WR_DEPTH_RACH => 16 , -- : integer := 16; C_WR_DEPTH_RDCH => 1024, -- : integer := 16; C_WR_DEPTH_AXIS => 1024, -- : integer := 16; C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4; C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0; C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0; C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0; C_REG_SLICE_MODE_WACH => 0, -- : integer := 0; C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0; C_REG_SLICE_MODE_RACH => 0, -- : integer := 0; C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0 ) port map ( backup => '0', backup_marker => '0', clk => '0', rst => Ainit, srst => '0', wr_clk => Wr_clk, wr_rst => Ainit, rd_clk => Rd_clk, rd_rst => Ainit, din => Din, wr_en => Wr_en, rd_en => Rd_en, prog_empty_thresh => PROG_RDTHRESH_ZEROS, prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, prog_full_thresh => PROG_WRTHRESH_ZEROS, prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, int_clk => '0', injectdbiterr => '0', -- new FG 5.1/5.2 injectsbiterr => '0', -- new FG 5.1/5.2 sleep => '0', dout => Dout, full => Full, almost_full => Almost_full, wr_ack => Wr_ack, overflow => Wr_err, empty => Empty, almost_empty => Almost_empty, valid => Rd_ack, underflow => Rd_err, data_count => DATA_COUNT, rd_data_count => sig_full_fifo_rdcnt, wr_data_count => sig_full_fifo_wrcnt, prog_full => PROG_FULL, prog_empty => PROG_EMPTY, sbiterr => SBITERR, dbiterr => DBITERR, wr_rst_busy => WR_RST_BUSY, rd_rst_busy => RD_RST_BUSY, -- AXI Global Signal m_aclk => '0', -- : IN std_logic := '0'; s_aclk => '0', -- : IN std_logic := '0'; s_aresetn => '0', -- : IN std_logic := '0'; m_aclk_en => '0', -- : IN std_logic := '0'; s_aclk_en => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Slave Write Channel (write side) s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awvalid => '0', -- : IN std_logic := '0'; s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic; s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wlast => '0', -- : IN std_logic := '0'; s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wvalid => '0', -- : IN std_logic := '0'; s_axi_wready => S_AXI_WREADY, -- : OUT std_logic; s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0); s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic; s_axi_bready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Write Channel (Read side) m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0); m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic; m_axi_awready => '0', -- : IN std_logic := '0'; m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0); m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic; m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0); m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic; m_axi_wready => '0', -- : IN std_logic := '0'; m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bvalid => '0', -- : IN std_logic := '0'; m_axi_bready => M_AXI_BREADY, -- : OUT std_logic; -- AXI Full/Lite Slave Read Channel (Write side) s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arvalid => '0', -- : IN std_logic := '0'; s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic; s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic; s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0); s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic; s_axi_rready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Read Channel (Read side) m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0); m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic; m_axi_arready => '0', -- : IN std_logic := '0'; m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rlast => '0', -- : IN std_logic := '0'; m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rvalid => '0', -- : IN std_logic := '0'; m_axi_rready => M_AXI_RREADY, -- : OUT std_logic; -- AXI Streaming Slave Signals (Write side) s_axis_tvalid => '0', -- : IN std_logic := '0'; s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic; s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tlast => '0', -- : IN std_logic := '0'; s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- AXI Streaming Master Signals (Read side) m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic; m_axis_tready => '0', -- : IN std_logic := '0'; m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0); m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0); m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0); m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic; m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0); m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0); m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals axi_aw_injectsbiterr => '0', -- : IN std_logic := '0'; axi_aw_injectdbiterr => '0', -- : IN std_logic := '0'; axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic; axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic; axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic; axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic; axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Data Channel Signals axi_w_injectsbiterr => '0', -- : IN std_logic := '0'; axi_w_injectdbiterr => '0', -- : IN std_logic := '0'; axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic; axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic; axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic; axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic; axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Response Channel Signals axi_b_injectsbiterr => '0', -- : IN std_logic := '0'; axi_b_injectdbiterr => '0', -- : IN std_logic := '0'; axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic; axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic; axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic; axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic; axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Address Channel Signals axi_ar_injectsbiterr => '0', -- : IN std_logic := '0'; axi_ar_injectdbiterr => '0', -- : IN std_logic := '0'; axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic; axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic; axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic; axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic; axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Data Channel Signals axi_r_injectsbiterr => '0', -- : IN std_logic := '0'; axi_r_injectdbiterr => '0', -- : IN std_logic := '0'; axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic; axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic; axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic; axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic; axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Streaming FIFO Related Signals axis_injectsbiterr => '0', -- : IN std_logic := '0'; axis_injectdbiterr => '0', -- : IN std_logic := '0'; axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic; axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic; axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic; axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0'; axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1'; ); end generate V6_S6_AND_LATER; end generate LEGACY_COREGEN_DEPTH; ------------------------------------------------------------ -- If Generate -- -- Label: USE_2N_DEPTH -- -- If Generate Description: -- This IfGen implements the FIFO Generator call where -- the User may specify depth and count widths of 2**N -- for Async FIFOs The associated count widths are set to -- reflect the 2**N FIFO depth. -- ------------------------------------------------------------ USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and FAMILY_IS_SUPPORTED) generate -- The programable thresholds are not used so this is housekeeping. Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3; Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4; Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH); Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH); -- Constant zeros for programmable threshold inputs signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- Signals Declarations Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0); Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0); --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0); begin -- Rip the LS bits of the write data count and assign to Write Count -- output port Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0); -- Rip the LS bits of the read data count and assign to Read Count -- output port Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0); ------------------------------------------------------------ -- If Generate -- -- Label: V6_S6_AND_LATER -- -- If Generate Description: -- This IFGen Implements the FIFO using fifo_generator_v9_3 -- for FPGA Families that are Virtex-6, Spartan-6, and later. -- ------------------------------------------------------------ V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate begin ------------------------------------------------------------------------------- -- Instantiate the generalized FIFO Generator instance -- -- NOTE: -- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!! -- This is a Coregen FIFO Generator Call module for -- legacy BRAM implementations of an Async FIFo. -- ------------------------------------------------------------------------------- I_ASYNC_FIFO_BRAM : entity fifo_generator_v12_0.fifo_generator_v12_0 generic map( C_COMMON_CLOCK => 0, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => C_DATA_WIDTH, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => C_DATA_WIDTH, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_FAMILY => FAMILY_TO_USE, C_FULL_FLAGS_RST_VAL => 1, C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY, C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 0, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => C_HAS_WR_ERR, C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_HAS_UNDERFLOW => C_HAS_RD_ERR, C_HAS_VALID => C_HAS_RD_ACK, C_HAS_WR_ACK => C_HAS_WR_ACK, C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => FG_IMP_TYPE, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => FG_MEM_TYPE, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => C_WR_ERR_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129 C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129 C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL, C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH, C_RD_DEPTH => C_FIFO_DEPTH, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => RD_PNTR_WIDTH, C_UNDERFLOW_LOW => C_RD_ERR_LOW, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129 C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH, C_WR_DEPTH => C_FIFO_DEPTH, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => WR_PNTR_WIDTH, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, -- AXI Interface related parameters start here C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0; C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0; C_HAS_SLAVE_CE => 0, -- : integer := 0; C_HAS_MASTER_CE => 0, -- : integer := 0; C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0; C_USE_COMMON_OVERFLOW => 0, -- : integer := 0; C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0; C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH => 4 , -- : integer := 0; C_AXI_ADDR_WIDTH => 32, -- : integer := 0; C_AXI_DATA_WIDTH => 64, -- : integer := 0; C_HAS_AXI_AWUSER => 0 , -- : integer := 0; C_HAS_AXI_WUSER => 0 , -- : integer := 0; C_HAS_AXI_BUSER => 0 , -- : integer := 0; C_HAS_AXI_ARUSER => 0 , -- : integer := 0; C_HAS_AXI_RUSER => 0 , -- : integer := 0; C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0; C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0; C_AXI_WUSER_WIDTH => 1 , -- : integer := 0; C_AXI_BUSER_WIDTH => 1 , -- : integer := 0; C_AXI_RUSER_WIDTH => 1 , -- : integer := 0; -- AXI Streaming C_HAS_AXIS_TDATA => 0 , -- : integer := 0; C_HAS_AXIS_TID => 0 , -- : integer := 0; C_HAS_AXIS_TDEST => 0 , -- : integer := 0; C_HAS_AXIS_TUSER => 0 , -- : integer := 0; C_HAS_AXIS_TREADY => 1 , -- : integer := 0; C_HAS_AXIS_TLAST => 0 , -- : integer := 0; C_HAS_AXIS_TSTRB => 0 , -- : integer := 0; C_HAS_AXIS_TKEEP => 0 , -- : integer := 0; C_AXIS_TDATA_WIDTH => 64, -- : integer := 1; C_AXIS_TID_WIDTH => 8 , -- : integer := 1; C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1; C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1; C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1; C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Data FIFO C_APPLICATION_TYPE_WACH => 0, -- : integer := 0; C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0; C_APPLICATION_TYPE_RACH => 0, -- : integer := 0; C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH => 0, -- : integer := 0; C_USE_ECC_WDCH => 0, -- : integer := 0; C_USE_ECC_WRCH => 0, -- : integer := 0; C_USE_ECC_RACH => 0, -- : integer := 0; C_USE_ECC_RDCH => 0, -- : integer := 0; C_USE_ECC_AXIS => 0, -- : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH => 32, -- : integer := 1; C_DIN_WIDTH_WDCH => 64, -- : integer := 1; C_DIN_WIDTH_WRCH => 2 , -- : integer := 1; C_DIN_WIDTH_RACH => 32, -- : integer := 1; C_DIN_WIDTH_RDCH => 64, -- : integer := 1; C_DIN_WIDTH_AXIS => 1 , -- : integer := 1; C_WR_DEPTH_WACH => 16 , -- : integer := 16; C_WR_DEPTH_WDCH => 1024, -- : integer := 16; C_WR_DEPTH_WRCH => 16 , -- : integer := 16; C_WR_DEPTH_RACH => 16 , -- : integer := 16; C_WR_DEPTH_RDCH => 1024, -- : integer := 16; C_WR_DEPTH_AXIS => 1024, -- : integer := 16; C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4; C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0; C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0; C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0; C_REG_SLICE_MODE_WACH => 0, -- : integer := 0; C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0; C_REG_SLICE_MODE_RACH => 0, -- : integer := 0; C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0 ) port map ( backup => '0', -- : IN std_logic := '0'; backup_marker => '0', -- : IN std_logic := '0'; clk => '0', -- : IN std_logic := '0'; rst => Ainit, -- : IN std_logic := '0'; srst => '0', -- : IN std_logic := '0'; wr_clk => Wr_clk, -- : IN std_logic := '0'; wr_rst => Ainit, -- : IN std_logic := '0'; rd_clk => Rd_clk, -- : IN std_logic := '0'; rd_rst => Ainit, -- : IN std_logic := '0'; din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); wr_en => Wr_en, -- : IN std_logic := '0'; rd_en => Rd_en, -- : IN std_logic := '0'; prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); int_clk => '0', -- : IN std_logic := '0'; injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0'; injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0'; sleep => '0', -- : IN std_logic := '0'; dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); full => Full, -- : OUT std_logic; almost_full => Almost_full, -- : OUT std_logic; wr_ack => Wr_ack, -- : OUT std_logic; overflow => Rd_err, -- : OUT std_logic; empty => Empty, -- : OUT std_logic; almost_empty => Almost_empty, -- : OUT std_logic; valid => Rd_ack, -- : OUT std_logic; underflow => Wr_err, -- : OUT std_logic; data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0); rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0); wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0); prog_full => PROG_FULL, -- : OUT std_logic; prog_empty => PROG_EMPTY, -- : OUT std_logic; sbiterr => SBITERR, -- : OUT std_logic; dbiterr => DBITERR, -- : OUT std_logic wr_rst_busy => WR_RST_BUSY, rd_rst_busy => RD_RST_BUSY, -- AXI Global Signal m_aclk => '0', -- : IN std_logic := '0'; s_aclk => '0', -- : IN std_logic := '0'; s_aresetn => '0', -- : IN std_logic := '0'; m_aclk_en => '0', -- : IN std_logic := '0'; s_aclk_en => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Slave Write Channel (write side) s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awvalid => '0', -- : IN std_logic := '0'; s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic; s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wlast => '0', -- : IN std_logic := '0'; s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wvalid => '0', -- : IN std_logic := '0'; s_axi_wready => S_AXI_WREADY, -- : OUT std_logic; s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0); s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic; s_axi_bready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Write Channel (Read side) m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0); m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic; m_axi_awready => '0', -- : IN std_logic := '0'; m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0); m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic; m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0); m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic; m_axi_wready => '0', -- : IN std_logic := '0'; m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bvalid => '0', -- : IN std_logic := '0'; m_axi_bready => M_AXI_BREADY, -- : OUT std_logic; -- AXI Full/Lite Slave Read Channel (Write side) s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arvalid => '0', -- : IN std_logic := '0'; s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic; s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic; s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0); s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic; s_axi_rready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Read Channel (Read side) m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0); m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic; m_axi_arready => '0', -- : IN std_logic := '0'; m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rlast => '0', -- : IN std_logic := '0'; m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rvalid => '0', -- : IN std_logic := '0'; m_axi_rready => M_AXI_RREADY, -- : OUT std_logic; -- AXI Streaming Slave Signals (Write side) s_axis_tvalid => '0', -- : IN std_logic := '0'; s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic; s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tlast => '0', -- : IN std_logic := '0'; s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- AXI Streaming Master Signals (Read side) m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic; m_axis_tready => '0', -- : IN std_logic := '0'; m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0); m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0); m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0); m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic; m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0); m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0); m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals axi_aw_injectsbiterr => '0', -- : IN std_logic := '0'; axi_aw_injectdbiterr => '0', -- : IN std_logic := '0'; axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic; axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic; axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic; axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic; axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Data Channel Signals axi_w_injectsbiterr => '0', -- : IN std_logic := '0'; axi_w_injectdbiterr => '0', -- : IN std_logic := '0'; axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic; axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic; axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic; axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic; axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Response Channel Signals axi_b_injectsbiterr => '0', -- : IN std_logic := '0'; axi_b_injectdbiterr => '0', -- : IN std_logic := '0'; axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic; axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic; axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic; axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic; axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Address Channel Signals axi_ar_injectsbiterr => '0', -- : IN std_logic := '0'; axi_ar_injectdbiterr => '0', -- : IN std_logic := '0'; axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic; axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic; axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic; axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic; axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Data Channel Signals axi_r_injectsbiterr => '0', -- : IN std_logic := '0'; axi_r_injectdbiterr => '0', -- : IN std_logic := '0'; axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic; axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic; axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic; axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic; axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Streaming FIFO Related Signals axis_injectsbiterr => '0', -- : IN std_logic := '0'; axis_injectdbiterr => '0', -- : IN std_logic := '0'; axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic; axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic; axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic; axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0'; axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1'; ); end generate V6_S6_AND_LATER; end generate USE_2N_DEPTH; ----------------------------------------------------------------------- end implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/syn/vhdl/FIFO_image_filter_img_1_data_stream_1_V.vhd

4

4629

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_img_1_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_img_1_data_stream_1_V_shiftReg; architecture rtl of FIFO_image_filter_img_1_data_stream_1_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_img_1_data_stream_1_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_img_1_data_stream_1_V is component FIFO_image_filter_img_1_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_img_1_data_stream_1_V_shiftReg : FIFO_image_filter_img_1_data_stream_1_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_skid2mm_buf.vhd

5

17065

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_skid2mm_buf.vhd -- -- Description: -- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode. -- -- This Module also provides Write Data Bus Mirroring and WSTRB -- Demuxing to match a narrow Stream to a wider MMap Write -- Channel. By doing this in the skid buffer, the resource -- utilization of the skid buffer can be minimized by only -- having to buffer/mux the Stream data width, not the MMap -- Data width. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_wr_demux; ------------------------------------------------------------------------------- entity axi_sg_skid2mm_buf is generic ( C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ; -- Width of the MMap Write Data bus (in bits) C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ; -- Width of the Stream Data bus (in bits) C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5 -- Width of the LS address bus needed to Demux the WSTRB ); port ( -- Clock and Reset Inputs ------------------------------------------- -- ACLK : In std_logic ; -- ARST : In std_logic ; -- --------------------------------------------------------------------- -- Slave Side (Wr Data Controller Input Side) ----------------------- -- S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); -- S_VALID : In std_logic ; -- S_READY : Out std_logic ; -- S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); -- S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); -- S_LAST : In std_logic ; -- --------------------------------------------------------------------- -- Master Side (MMap Write Data Output Side) ------------------------ M_VALID : Out std_logic ; -- M_READY : In std_logic ; -- M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); -- M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); -- M_LAST : Out std_logic -- --------------------------------------------------------------------- ); end entity axi_sg_skid2mm_buf; architecture implementation of axi_sg_skid2mm_buf is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH; Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH; -- Signals decalrations ------------------------- Signal sig_reset_reg : std_logic := '0'; signal sig_spcl_s_ready_set : std_logic := '0'; signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_skid_reg : std_logic := '0'; signal sig_skid_reg_en : std_logic := '0'; signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_skid_mux_out : std_logic := '0'; signal sig_skid_mux_sel : std_logic := '0'; signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_reg_out : std_logic := '0'; signal sig_data_reg_out_en : std_logic := '0'; signal sig_m_valid_out : std_logic := '0'; signal sig_m_valid_dup : std_logic := '0'; signal sig_m_valid_comb : std_logic := '0'; signal sig_s_ready_out : std_logic := '0'; signal sig_s_ready_dup : std_logic := '0'; signal sig_s_ready_comb : std_logic := '0'; signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); -- Register duplication attribute assignments to control fanout -- on handshake output signals Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no"; begin --(architecture implementation) M_VALID <= sig_m_valid_out; S_READY <= sig_s_ready_out; M_STRB <= sig_strb_reg_out; M_LAST <= sig_last_reg_out; M_DATA <= sig_mirror_data_out; -- Assign the special S_READY FLOP set signal sig_spcl_s_ready_set <= sig_reset_reg; -- Generate the ouput register load enable control sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup); -- Generate the skid inpit register load enable control sig_skid_reg_en <= sig_s_ready_dup; -- Generate the skid mux select control sig_skid_mux_sel <= not(sig_s_ready_dup); -- Skid Mux sig_data_skid_mux_out <= sig_data_skid_reg When (sig_skid_mux_sel = '1') Else S_DATA; sig_strb_skid_mux_out <= sig_strb_skid_reg When (sig_skid_mux_sel = '1') --Else S_STRB; Else sig_wstrb_demux_out; sig_last_skid_mux_out <= sig_last_skid_reg When (sig_skid_mux_sel = '1') Else S_LAST; -- m_valid combinational logic sig_m_valid_comb <= S_VALID or (sig_m_valid_dup and (not(sig_s_ready_dup) or not(M_READY))); -- s_ready combinational logic sig_s_ready_comb <= M_READY or (sig_s_ready_dup and (not(sig_m_valid_dup) or not(S_VALID))); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_THE_RST -- -- Process Description: -- Register input reset -- ------------------------------------------------------------- REG_THE_RST : process (ACLK) begin if (ACLK'event and ACLK = '1') then sig_reset_reg <= ARST; end if; end process REG_THE_RST; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: S_READY_FLOP -- -- Process Description: -- Registers S_READY handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- S_READY_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_s_ready_out <= '0'; sig_s_ready_dup <= '0'; Elsif (sig_spcl_s_ready_set = '1') Then sig_s_ready_out <= '1'; sig_s_ready_dup <= '1'; else sig_s_ready_out <= sig_s_ready_comb; sig_s_ready_dup <= sig_s_ready_comb; end if; end if; end process S_READY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: M_VALID_FLOP -- -- Process Description: -- Registers M_VALID handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- M_VALID_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1' or sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA sig_m_valid_out <= '0'; sig_m_valid_dup <= '0'; else sig_m_valid_out <= sig_m_valid_comb; sig_m_valid_dup <= sig_m_valid_comb; end if; end if; end process M_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_DATA_REG -- -- Process Description: -- This process implements the Skid register for the -- Skid Buffer Data signals. -- ------------------------------------------------------------- SKID_DATA_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (sig_skid_reg_en = '1') then sig_data_skid_reg <= S_DATA; else null; -- hold current state end if; end if; end process SKID_DATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_CNTL_REG -- -- Process Description: -- This process implements the Output registers for the -- Skid Buffer Control signals -- ------------------------------------------------------------- SKID_CNTL_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_strb_skid_reg <= (others => '0'); sig_last_skid_reg <= '0'; elsif (sig_skid_reg_en = '1') then sig_strb_skid_reg <= sig_wstrb_demux_out; sig_last_skid_reg <= S_LAST; else null; -- hold current state end if; end if; end process SKID_CNTL_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_DATA_REG -- -- Process Description: -- This process implements the Output register for the -- Data signals. -- ------------------------------------------------------------- OUTPUT_DATA_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (sig_data_reg_out_en = '1') then sig_data_reg_out <= sig_data_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_DATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_CNTL_REG -- -- Process Description: -- This process implements the Output registers for the -- control signals. -- ------------------------------------------------------------- OUTPUT_CNTL_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_strb_reg_out <= (others => '0'); sig_last_reg_out <= '0'; elsif (sig_data_reg_out_en = '1') then sig_strb_reg_out <= sig_strb_skid_mux_out; sig_last_reg_out <= sig_last_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_CNTL_REG; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_WR_DATA_MIRROR -- -- Process Description: -- Implement the Write Data Mirror structure -- -- Note that it is required that the Stream Width be less than -- or equal to the MMap WData width. -- ------------------------------------------------------------- DO_WR_DATA_MIRROR : process (sig_data_reg_out) begin for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1 downto C_SDATA_WIDTH*slice_index) <= sig_data_reg_out; end loop; end process DO_WR_DATA_MIRROR; ------------------------------------------------------------ -- Instance: I_WSTRB_DEMUX -- -- Description: -- Instance for the Write Strobe DeMux. -- ------------------------------------------------------------ I_WSTRB_DEMUX : entity axi_sg_v4_1.axi_sg_wr_demux generic map ( C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH , C_MMAP_DWIDTH => C_MDATA_WIDTH , C_STREAM_DWIDTH => C_SDATA_WIDTH ) port map ( wstrb_in => S_STRB , demux_wstrb_out => sig_wstrb_demux_out , debeat_saddr_lsb => S_ADDR_LSB ); end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_mm2s_basic_wrap.vhd

5

44186

------------------------------------------------------------------------------- -- axi_datamover_mm2s_basic_wrap.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mm2s_basic_wrap.vhd -- -- Description: -- This file implements the DataMover MM2S Basic Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- axi_datamover Library Modules library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_reset; use axi_datamover_v5_1.axi_datamover_cmd_status; use axi_datamover_v5_1.axi_datamover_scc; use axi_datamover_v5_1.axi_datamover_addr_cntl; use axi_datamover_v5_1.axi_datamover_rddata_cntl; use axi_datamover_v5_1.axi_datamover_rd_status_cntl; use axi_datamover_v5_1.axi_datamover_skid_buf; ------------------------------------------------------------------------------- entity axi_datamover_mm2s_basic_wrap is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 2; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Basic MM2S functionality C_MM2S_ARID : Integer range 0 to 255 := 8; -- Specifies the constant value to output on -- the ARID output port C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 64 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_MICRO_DMA : integer range 0 to 1 := 0; C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock and Reset inputs ----------------------- mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- -------------------------------------------------------------- -- MM2S Halt request input control --------------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- -------------------------------------------------------------- -- Error discrete output ------------------------------------- mm2s_err : Out std_logic; -- -- Composite Error indication -- -------------------------------------------------------------- -- Optional MM2S Command and Status Clock and Reset ---------- -- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 -- mm2s_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- -------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) ------------------------------------------------- mm2s_cmd_wvalid : in std_logic; -- mm2s_cmd_wready : out std_logic; -- mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); -- ---------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ----------------- mm2s_sts_wvalid : out std_logic; -- mm2s_sts_wready : in std_logic; -- mm2s_sts_wdata : out std_logic_vector(7 downto 0); -- mm2s_sts_wstrb : out std_logic_vector(0 downto 0); -- mm2s_sts_wlast : out std_logic; -- ------------------------------------------------------------- -- Address Posting contols ---------------------------------- mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- ------------------------------------------------------------- -- MM2S AXI Address Channel I/O -------------------------------------- mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel USER output -- -- mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ------- -- addr2axi_alock : out std_logic_vector(2 downto 0); -- -- addr2axi_acache : out std_logic_vector(4 downto 0); -- -- addr2axi_aqos : out std_logic_vector(3 downto 0); -- -- addr2axi_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------- -- MM2S AXI MMap Read Data Channel I/O ------------------------------------------ mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); -- mm2s_rresp : In std_logic_vector(1 downto 0); -- mm2s_rlast : In std_logic; -- mm2s_rvalid : In std_logic; -- mm2s_rready : Out std_logic; -- ---------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ----------------------------------------------- mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); -- mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); -- mm2s_strm_wlast : Out std_logic; -- mm2s_strm_wvalid : Out std_logic; -- mm2s_strm_wready : In std_logic; -- -------------------------------------------------------------------------------------- -- Testing Support I/O -------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) -- ------------------------------------------------------------------- ); end entity axi_datamover_mm2s_basic_wrap; architecture implementation of axi_datamover_mm2s_basic_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_rdmux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Read data mux select control. -- ------------------------------------------------------------------- function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 5 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when others => -- 256 bits num_addr_bits_needed := 5; end case; Return (num_addr_bits_needed); end function func_calc_rdmux_sel_bits; -- Constant Declarations ---------------------------------------- Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant INCLUDE_MM2S : integer range 0 to 2 := 2; Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID; Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH; Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH; Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH; Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH; Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32); Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1; Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := C_MM2S_STSCMD_FIFO_DEPTH; Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC; Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0; Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2; Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16; Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH; Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH; Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH); Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); -- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0; -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0); signal sig_mm2s_cache_data : std_logic_vector(7 downto 0); signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_cmplt : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2rsc_calc_error : std_logic := '0'; signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2rsc_calc_err : std_logic := '0'; signal sig_data2rsc_okay : std_logic := '0'; signal sig_data2rsc_decerr : std_logic := '0'; signal sig_data2rsc_slverr : std_logic := '0'; signal sig_data2rsc_cmd_cmplt : std_logic := '0'; signal sig_rsc2data_ready : std_logic := '0'; signal sig_data2rsc_valid : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_data2skid_wvalid : std_logic := '0'; signal sig_data2skid_wready : std_logic := '0'; signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_data2skid_wlast : std_logic := '0'; signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2rsc_status_ready : std_logic := '0'; signal sig_rsc2stat_status_valid : std_logic := '0'; signal sig_rsc2mstr_halt_pipe : std_logic := '0'; signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal mm2s_arcache_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug Support ------------------------------------------ mm2s_dbg_data <= sig_dbg_data_mux_out; -- Note that only the mm2s_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (mm2s_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2rsc_status_ready; sig_dbg_data_1(7) <= sig_rsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake -- Spare bits in debug1 sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off mm2s_arcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register mm2s_aruser <= "0000";--sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters -- sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96); sig_mm2s_cache_data <= mm2s_cmd_wdata(79 downto 72); end generate GEN_CACHE2; -- Cache signal tie-off -- Internal error output discrete ------------------------------ mm2s_err <= sig_calc2dm_calc_err; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ) port map ( primary_aclk => mm2s_aclk , primary_aresetn => mm2s_aresetn , secondary_awclk => mm2s_cmdsts_awclk , secondary_aresetn => mm2s_cmdsts_aresetn , halt_req => mm2s_halt , halt_cmplt => mm2s_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => LOGIC_HIGH , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO , C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_STS_WIDTH => MM2S_STS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , secondary_awclk => mm2s_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => mm2s_cmd_wvalid , cmd_wready => mm2s_cmd_wready , cmd_wdata => sig_mm2s_cmd_wdata , cache_data => sig_mm2s_cache_data , sts_wvalid => mm2s_sts_wvalid , sts_wready => mm2s_sts_wready , sts_wdata => mm2s_sts_wdata , sts_wstrb => mm2s_sts_wstrb , sts_wlast => mm2s_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_rsc2stat_status , stat2mstr_status_ready => sig_stat2rsc_status_ready , mst2stst_status_valid => sig_rsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_RD_STATUS_CNTLR -- -- Description: -- Read Status Controller Block -- ------------------------------------------------------------ I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl generic map ( C_STS_WIDTH => MM2S_STS_WIDTH , C_TAG_WIDTH => C_TAG_WIDTH ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , calc2rsc_calc_error => sig_calc2dm_calc_err , addr2rsc_calc_error => sig_addr2rsc_calc_error , addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty , data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_error => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2stat_status => sig_rsc2stat_status , stat2rsc_status_ready => sig_stat2rsc_status_ready , rsc2stat_status_valid => sig_rsc2stat_status_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ------------------------------------------------------------ -- Instance: I_MSTR_SCC -- -- Description: -- Simple Command Calculator Block -- ------------------------------------------------------------ I_MSTR_SCC : entity axi_datamover_v5_1.axi_datamover_scc generic map ( C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_MAX_BURST_LEN => C_MM2S_BURST_SIZE , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_MICRO_DMA => C_MICRO_DMA , C_TAG_WIDTH => C_TAG_WIDTH ) port map ( -- Clock input primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_sof => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , calc_error => sig_calc2dm_calc_err ); ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl generic map ( -- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA , --C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH , C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_ADDR_ID => MM2S_ARID_VALUE , C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH , C_TAG_WIDTH => C_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => mm2s_arid , addr2axi_aaddr => mm2s_araddr , addr2axi_alen => mm2s_arlen , addr2axi_asize => mm2s_arsize , addr2axi_aburst => mm2s_arburst , addr2axi_aprot => mm2s_arprot , addr2axi_avalid => mm2s_arvalid , addr2axi_acache => open , addr2axi_auser => open , axi2addr_aready => mm2s_arready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => mm2s_allow_addr_req , addr_req_posted => mm2s_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => LOGIC_LOW , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2rsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_RD_DATA_CNTL -- -- Description: -- Read Data Controller Block -- ------------------------------------------------------------ I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl generic map ( C_INCLUDE_DRE => INCLUDE_MM2S_DRE , C_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => MM2S_MDATA_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_TAG_WIDTH => C_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset ----------------------------------- primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , -- Soft Shutdown Interface ----------------------------- rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , -- External Address Pipelining Contol support mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt , -- AXI Read Data Channel I/O ------------------------------- mm2s_rdata => mm2s_rdata , mm2s_rresp => mm2s_rresp , mm2s_rlast => mm2s_rlast , mm2s_rvalid => mm2s_rvalid , mm2s_rready => mm2s_rready , -- MM2S DRE Control ----------------------------------- mm2s_dre_new_align => open , mm2s_dre_use_autodest => open , mm2s_dre_src_align => open , mm2s_dre_dest_align => open , mm2s_dre_flush => open , -- AXI Master Stream ----------------------------------- mm2s_strm_wvalid => sig_data2skid_wvalid , mm2s_strm_wready => sig_data2skid_wready , mm2s_strm_wdata => sig_data2skid_wdata , mm2s_strm_wstrb => sig_data2skid_wstrb , mm2s_strm_wlast => sig_data2skid_wlast , -- MM2S Store and Forward Supplimental Control ----------- mm2s_data2sf_cmd_cmplt => open , -- Command Calculator Interface -------------------------- mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => LOGIC_LOW , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => DRE_ALIGN_ZEROS , mstr2data_dre_dest_align => DRE_ALIGN_ZEROS , -- Address Controller Interface -------------------------- addr2data_addr_posted => sig_addr2data_addr_posted , -- Data Controller Halted Status data2all_dcntlr_halted => sig_data2all_dcntlr_halted, -- Output Stream Skid Buffer Halt control data2skid_halt => sig_data2skid_halt , -- Read Status Controller Interface -------------------------- data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_err => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate begin ------------------------------------------------------------ -- Instance: I_MM2S_SKID_BUF -- -- Description: -- Instance for the MM2S Skid Buffer which provides for -- registerd Master Stream outputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => MM2S_SDATA_WIDTH ) port map ( -- System Ports aclk => mm2s_aclk , arst => sig_stream_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => sig_data2skid_wvalid , s_ready => sig_data2skid_wready , s_data => sig_data2skid_wdata , s_strb => sig_data2skid_wstrb , s_last => sig_data2skid_wlast , -- Master Side (Stream Data Output m_valid => mm2s_strm_wvalid , m_ready => mm2s_strm_wready , m_data => mm2s_strm_wdata , m_strb => mm2s_strm_wstrb , m_last => mm2s_strm_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate begin mm2s_strm_wvalid <= sig_data2skid_wvalid; sig_data2skid_wready <= mm2s_strm_wready; mm2s_strm_wdata <= sig_data2skid_wdata; mm2s_strm_wstrb <= sig_data2skid_wstrb; mm2s_strm_wlast <= sig_data2skid_wlast; end generate DISABLE_AXIS_SKID; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_mask_cols_V.vhd

2

4556

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_mask_cols_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_mask_cols_V_shiftReg; architecture rtl of FIFO_image_filter_mask_cols_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_mask_cols_V is generic ( MEM_STYLE : string := "shiftreg"; DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_mask_cols_V is component FIFO_image_filter_mask_cols_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_mask_cols_V_shiftReg : FIFO_image_filter_mask_cols_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/correct_one_bit_64.vhd

7

8400

------------------------------------------------------------------------------- -- correct_one_bit_64.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------ -- Filename: correct_one_bit_64.vhd -- -- Description: Identifies single bit to correct in 64-bit word of -- data read from memory as indicated by the syndrome input -- vector. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all; entity Correct_One_Bit_64 is generic ( C_USE_LUT6 : boolean := true; Correct_Value : std_logic_vector(0 to 7)); port ( DIn : in std_logic; Syndrome : in std_logic_vector(0 to 7); DCorr : out std_logic); end entity Correct_One_Bit_64; architecture IMP of Correct_One_Bit_64 is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; ----------------------------------------------------------------------------- -- Find which bit that has a '1' -- There is always one bit which has a '1' ----------------------------------------------------------------------------- function find_one (Syn : std_logic_vector(0 to 7)) return natural is begin -- function find_one for I in 0 to 7 loop if (Syn(I) = '1') then return I; end if; end loop; -- I return 0; -- Should never reach this statement end function find_one; constant di_index : natural := find_one(Correct_Value); signal corr_sel : std_logic; signal corr_c : std_logic; signal lut_compare : std_logic_vector(0 to 6); signal lut_corr_val : std_logic_vector(0 to 6); begin -- architecture IMP Remove_DI_Index : process (Syndrome) is begin -- process Remove_DI_Index if (di_index = 0) then lut_compare <= Syndrome(1 to 7); lut_corr_val <= Correct_Value(1 to 7); elsif (di_index = 6) then lut_compare <= Syndrome(0 to 6); lut_corr_val <= Correct_Value(0 to 6); else lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 7); lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 7); end if; end process Remove_DI_Index; corr_sel <= '0' when lut_compare = lut_corr_val else '1'; Corr_MUXCY : MUXCY_L port map ( DI => Syndrome(di_index), CI => '0', S => corr_sel, LO => corr_c); Corr_XORCY : XORCY port map ( LI => DIn, CI => corr_c, O => DCorr); end architecture IMP;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_rd_status_cntl.vhd

18

19292

------------------------------------------------------------------------------- -- axi_datamover_rd_status_cntl.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_rd_status_cntl.vhd -- -- Description: -- This file implements the DataMover Master Read Status Controller. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_datamover_rd_status_cntl is generic ( C_STS_WIDTH : Integer := 8; -- sets the width of the Status ports C_TAG_WIDTH : Integer range 1 to 8 := 4 -- Sets the width of the Tag field in the Status reply ); port ( -- Clock and Reset input -------------------------------------- -- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- --------------------------------------------------------------- -- Command Calculator Status Interface --------------------------- -- calc2rsc_calc_error : in std_logic ; -- -- Indication from the Command Calculator that a calculation -- -- error has occured. -- ------------------------------------------------------------------- -- Address Controller Status Interface ---------------------------- -- addr2rsc_calc_error : In std_logic ; -- -- Indication from the Data Channel Controller FIFO that it -- -- is empty (no commands pending) -- -- addr2rsc_fifo_empty : In std_logic ; -- -- Indication from the Address Controller FIFO that it -- -- is empty (no commands pending) -- ------------------------------------------------------------------- -- Data Controller Status Interface --------------------------------------------- -- data2rsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The command tag -- -- data2rsc_calc_error : In std_logic ; -- -- Indication from the Data Channel Controller FIFO that it -- -- is empty (no commands pending) -- -- data2rsc_okay : In std_logic ; -- -- Indication that the AXI Read transfer completed with OK status -- -- data2rsc_decerr : In std_logic ; -- -- Indication that the AXI Read transfer completed with decode error status -- -- data2rsc_slverr : In std_logic ; -- -- Indication that the AXI Read transfer completed with slave error status -- -- data2rsc_cmd_cmplt : In std_logic ; -- -- Indication by the Data Channel Controller that the -- -- corresponding status is the last status for a parent command -- -- pulled from the command FIFO -- -- rsc2data_ready : Out std_logic; -- -- Handshake bit from the Read Status Controller Module indicating -- -- that the it is ready to accept a new Read status transfer -- -- data2rsc_valid : in std_logic ; -- -- Handshake bit output to the Read Status Controller Module -- -- indicating that the Data Controller has valid tag and status -- -- indicators to transfer -- ---------------------------------------------------------------------------------- -- Command/Status Module Interface ---------------------------------------------- -- rsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); -- -- Read Status value collected during a Read Data transfer -- -- Output to the Command/Status Module -- -- stat2rsc_status_ready : In std_logic; -- -- Input from the Command/Status Module indicating that the -- -- Status Reg/FIFO is ready to accept a transfer -- -- rsc2stat_status_valid : Out std_logic ; -- -- Control Signal to the Status Reg/FIFO indicating a new status -- -- output value is valid and ready for transfer -- --------------------------------------------------------------------------------- -- Address and Data Controller Pipe halt ---------------------------------- -- rsc2mstr_halt_pipe : Out std_logic -- -- Indication to Halt the Data and Address Command pipeline due -- -- to the Status FIFO going full or an internal error being logged -- --------------------------------------------------------------------------- ); end entity axi_datamover_rd_status_cntl; architecture implementation of axi_datamover_rd_status_cntl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Constant Declarations -------------------------------------------- Constant OKAY : std_logic_vector(1 downto 0) := "00"; Constant EXOKAY : std_logic_vector(1 downto 0) := "01"; Constant SLVERR : std_logic_vector(1 downto 0) := "10"; Constant DECERR : std_logic_vector(1 downto 0) := "11"; Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000"; Constant TAG_WIDTH : integer := C_TAG_WIDTH; Constant STAT_REG_TAG_WIDTH : integer := 4; -- Signal Declarations -------------------------------------------- signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_rsc2status_valid : std_logic := '0'; signal sig_rsc2data_ready : std_logic := '0'; signal sig_rd_sts_okay_reg : std_logic := '0'; signal sig_rd_sts_interr_reg : std_logic := '0'; signal sig_rd_sts_decerr_reg : std_logic := '0'; signal sig_rd_sts_slverr_reg : std_logic := '0'; signal sig_rd_sts_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_pop_rd_sts_reg : std_logic := '0'; signal sig_push_rd_sts_reg : std_logic := '0'; Signal sig_rd_sts_push_ok : std_logic := '0'; signal sig_rd_sts_reg_empty : std_logic := '0'; signal sig_rd_sts_reg_full : std_logic := '0'; begin --(architecture implementation) -- Assign the status write output control rsc2stat_status_valid <= sig_rsc2status_valid ; sig_rsc2status_valid <= sig_rd_sts_reg_full; -- Formulate the status outout value (assumes an 8-bit status width) rsc2stat_status <= sig_rd_sts_okay_reg & sig_rd_sts_slverr_reg & sig_rd_sts_decerr_reg & sig_rd_sts_interr_reg & sig_tag2status; -- Detect that a push of a new status word is completing sig_rd_sts_push_ok <= sig_rsc2status_valid and stat2rsc_status_ready; -- Signal a halt to the execution pipe if new status -- is valid but the Status FIFO is not accepting it rsc2mstr_halt_pipe <= sig_rsc2status_valid and (not(stat2rsc_status_ready) ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_TAG_LE_STAT -- -- If Generate Description: -- Populates the TAG bits into the availble Status bits when -- the TAG width is less than or equal to the available number -- of bits in the Status word. -- ------------------------------------------------------------ GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate -- local signals signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0'); begin sig_tag2status <= lsig_temp_tag_small; ------------------------------------------------------------- -- Combinational Process -- -- Label: POPULATE_SMALL_TAG -- -- Process Description: -- -- ------------------------------------------------------------- POPULATE_SMALL_TAG : process (sig_rd_sts_tag_reg) begin -- Set default value lsig_temp_tag_small <= (others => '0'); -- Now overload actual TAG bits lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_rd_sts_tag_reg; end process POPULATE_SMALL_TAG; end generate GEN_TAG_LE_STAT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_TAG_GT_STAT -- -- If Generate Description: -- Populates the TAG bits into the availble Status bits when -- the TAG width is greater than the available number of -- bits in the Status word. The upper bits of the TAG are -- clipped off (discarded). -- ------------------------------------------------------------ GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate -- local signals signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0); begin sig_tag2status <= lsig_temp_tag_big; ------------------------------------------------------------- -- Combinational Process -- -- Label: POPULATE_BIG_TAG -- -- Process Description: -- -- ------------------------------------------------------------- POPULATE_SMALL_TAG : process (sig_rd_sts_tag_reg) begin -- Set default value lsig_temp_tag_big <= (others => '0'); -- Now overload actual TAG bits lsig_temp_tag_big <= sig_rd_sts_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0); end process POPULATE_SMALL_TAG; end generate GEN_TAG_GT_STAT; ------- Read Status Collection Logic -------------------------------- rsc2data_ready <= sig_rsc2data_ready ; sig_rsc2data_ready <= sig_rd_sts_reg_empty; sig_push_rd_sts_reg <= data2rsc_valid and sig_rsc2data_ready; sig_pop_rd_sts_reg <= sig_rd_sts_push_ok; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: RD_STATUS_FIFO_REG -- -- Process Description: -- Implement Read status FIFO register. -- This register holds the Read status from the Data Controller -- until it is transfered to the Status FIFO. -- ------------------------------------------------------------- RD_STATUS_FIFO_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_pop_rd_sts_reg = '1') then sig_rd_sts_tag_reg <= (others => '0'); sig_rd_sts_interr_reg <= '0'; sig_rd_sts_decerr_reg <= '0'; sig_rd_sts_slverr_reg <= '0'; sig_rd_sts_okay_reg <= '1'; -- set back to default of "OKAY" sig_rd_sts_reg_full <= '0'; sig_rd_sts_reg_empty <= '1'; Elsif (sig_push_rd_sts_reg = '1') Then sig_rd_sts_tag_reg <= data2rsc_tag; sig_rd_sts_interr_reg <= data2rsc_calc_error or sig_rd_sts_interr_reg; sig_rd_sts_decerr_reg <= data2rsc_decerr or sig_rd_sts_decerr_reg; sig_rd_sts_slverr_reg <= data2rsc_slverr or sig_rd_sts_slverr_reg; sig_rd_sts_okay_reg <= data2rsc_okay and not(data2rsc_decerr or sig_rd_sts_decerr_reg or data2rsc_slverr or sig_rd_sts_slverr_reg or data2rsc_calc_error or sig_rd_sts_interr_reg ); sig_rd_sts_reg_full <= data2rsc_cmd_cmplt or data2rsc_calc_error; sig_rd_sts_reg_empty <= not(data2rsc_cmd_cmplt or data2rsc_calc_error); else null; -- hold current state end if; end if; end process RD_STATUS_FIFO_REG; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_cdma_v4_1/25515467/hdl/src/vhdl/axi_cdma_pulse_gen.vhd

1

15300

------------------------------------------------------------------------------- -- axi_cdma_pulse_gen.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_cdma_pulse_gen.vhd -- -- Description: -- This file is the design for a parameterizable pulse width generator. -- The input Sig_In is either Positive Edge or Negative detected -- which triggers a pulse generator. Allowed pulse widths are 1 to -- 64 input clock periods. -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library lib_cdc_v1_0; library axi_cdma_v4_1; use axi_cdma_v4_1.axi_cdma_pkg.all; ------------------------------------------------------------------------------ entity axi_cdma_pulse_gen is generic ( C_INCLUDE_SYNCHRO : Integer range 0 to 1 := 0; -- 0 = Do not include synchronizer registers -- 1 = Include synchronizer registers C_POS_EDGE_TRIG : Integer range 0 to 1 := 1; -- 0 = Negative Edge Triggered Pulse -- 1 = Positive Edge Triggered Pulse C_PULSE_WIDTH_CLKS : integer range 1 to 64 := 4 -- Desired Output Pulse width (in Clk_In periods) ); port ( -- Input synchronization clock Clk_In : In std_logic; -- Module reset (active high) Rst_In : In std_logic; -- Input trigger signal Sig_in : In std_logic; -- Output pulse Pulse_Out : Out std_logic ); end entity axi_cdma_pulse_gen; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_cdma_pulse_gen is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ATTRIBUTE async_reg : STRING; ------------------------------------------------------------------------------- -- Functions Declarations ------------------------------------------------------------------------------- -- none ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- Constant ADJUSTED_CLKs : integer := C_PULSE_WIDTH_CLKS+1; ------------------------------------------------------------------------------- -- Internal Signal Declaration ------------------------------------------------------------------------------- -- System module reset interconnect signals signal sig_pulse_out : std_logic; signal sig_to_edge_detect_reg : std_logic; signal sig_pulse_trigger : std_logic; signal sig_shift_reg : std_logic_vector(0 to ADJUSTED_CLKs-1); -- Addition of synchronizer front-end signal sig_synchro_reg1_cdc_tig : std_logic; signal sig_synchro_reg2 : std_logic; signal sig_to_edge_detect : std_logic; -- ATTRIBUTE async_reg OF sig_synchro_reg1_cdc_tig : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF sig_synchro_reg2 : SIGNAL IS "true"; ------------------------------------------------------------------------------- begin -- architecture body -- Output Port assignments Pulse_Out <= sig_pulse_out ; ------------------------------------------------------------ -- If Generate -- -- Label: OMIT_SYNCHRO_REGS -- -- If Generate Description: -- This IfGen omits the implementation of a double register -- synchronizer on the input signal. -- ------------------------------------------------------------ OMIT_SYNCHRO_REGS : if (C_INCLUDE_SYNCHRO = 0) generate begin sig_to_edge_detect <= Sig_In; end generate OMIT_SYNCHRO_REGS; ------------------------------------------------------------ -- If Generate -- -- Label: INCLUDE_SYNCHRO_REGS -- -- If Generate Description: -- This IfGen includes the implementation of a double -- register synchronizer on the input signal. -- ------------------------------------------------------------ INCLUDE_SYNCHRO_REGS : if (C_INCLUDE_SYNCHRO = 1) generate begin sig_to_edge_detect <= sig_synchro_reg2; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_SYNCHRO_REGS -- -- Process Description: -- -- ------------------------------------------------------------- DO_SYNCHRO_REGS : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => Sig_In, prmry_vect_in => (others => '0'), scndry_aclk => Clk_In, scndry_resetn => '0', scndry_out => sig_synchro_reg2, scndry_vect_out => open ); -- DO_SYNCHRO_REGS : process (Clk_In) -- begin -- if (Clk_In'event and Clk_In = '1') then -- if (Rst_In = '1') then -- sig_synchro_reg1_cdc_tig <= '0'; -- sig_synchro_reg2 <= '0'; -- else -- sig_synchro_reg1_cdc_tig <= Sig_In; -- sig_synchro_reg2 <= sig_synchro_reg1_cdc_tig; -- end if; -- end if; -- end process DO_SYNCHRO_REGS; end generate INCLUDE_SYNCHRO_REGS; ------------------------------------------------------------ -- If Generate -- -- Label: POSITIVE_EDGE_TRIGGER -- -- If Generate Description: -- Generate Pulse trigger from Positive edge detection on -- the input signal -- -- ------------------------------------------------------------ POSITIVE_EDGE_TRIGGER : if (C_POS_EDGE_TRIG = 1) generate begin -- Do positive edge detection on input signal, This becomes -- the trigger for generating the output pulse. sig_pulse_trigger <= sig_to_edge_detect and not(sig_to_edge_detect_reg); end generate POSITIVE_EDGE_TRIGGER; ------------------------------------------------------------ -- If Generate -- -- Label: NEGATIVE_EDGE_TRIGGER -- -- If Generate Description: -- Generate Pulse trigger from negative edge detection on -- the input signal -- -- ------------------------------------------------------------ NEGATIVE_EDGE_TRIGGER : if (C_POS_EDGE_TRIG = 0) generate begin -- Do negative edge detection on input signal, This becomes -- the trigger for generating the output pulse. sig_pulse_trigger <= not(sig_to_edge_detect) and sig_to_edge_detect_reg; end generate NEGATIVE_EDGE_TRIGGER; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SIG_IN -- -- Process Description: -- This process registers the input signal for use in the -- edge detection logic. -- ------------------------------------------------------------- REG_SIG_IN : process (Clk_In) begin if (Clk_In'event and Clk_In = '1') then if (Rst_In = '1') then sig_to_edge_detect_reg <= '0'; else sig_to_edge_detect_reg <= sig_to_edge_detect; end if; end if; end process REG_SIG_IN; ------------------------------------------------------------ -- If Generate -- -- Label: DO_SINGLE_CLK_PULSE -- -- If Generate Description: -- -- Handles single clock pulse width case -- ------------------------------------------------------------ DO_SINGLE_CLK_PULSE : if (C_PULSE_WIDTH_CLKS = 1) generate begin sig_shift_reg <= (others => '0'); -- house keeping ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SINGLE_PULSE -- -- Process Description: -- This process registers a single pulse case. -- ------------------------------------------------------------- REG_SINGLE_PULSE : process (Clk_In) begin if (Clk_In'event and Clk_In = '1') then if (Rst_In = '1') then sig_pulse_out <= '0'; else sig_pulse_out <= sig_pulse_trigger; end if; end if; end process REG_SINGLE_PULSE; end generate DO_SINGLE_CLK_PULSE; ------------------------------------------------------------ -- If Generate -- -- Label: DO_MULTI_CLK_PULSE -- -- If Generate Description: -- -- Handles Multi clock pulse width case -- ------------------------------------------------------------ DO_MULTI_CLK_PULSE : if (C_PULSE_WIDTH_CLKS >= 2) generate begin ----------------------------------------------------------------------------- -- Implement the Shift register logic ----------------------------------------------------------------------------- -- The output pulse is ripped from the final stage of the shift register sig_pulse_out <= sig_shift_reg(ADJUSTED_CLKs-1); -- Tie the shift register input stage to 0 sig_shift_reg(0) <= '0'; ------------------------------------------------------------ -- For Generate -- -- Label: DO_SHIF_REG -- -- For Generate Description: -- This For Gen implements a parameterizable shift -- register for the pulse generator. The trigger presets -- all of the register segments and then zeros are shifted -- into the pipe until all stages are cleared. The resulting -- pulse out is equal to the number of stages in the shift -- register. -- -- -- ------------------------------------------------------------ DO_SHIF_REG : for reg_index in 1 to ADJUSTED_CLKs-1 generate begin ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_SHIFT_REG_SEGMENT -- -- Process Description: -- This process implements a single register segment of -- of the pulse generator shift register. -- ------------------------------------------------------------- DO_SHIFT_REG_SEGMENT : process (Clk_In) begin if (Clk_In'event and Clk_In = '1') then if (Rst_In = '1') then -- Clear the reg sig_shift_reg(reg_index) <= '0'; elsif (sig_pulse_trigger = '1') then -- preset the reg sig_shift_reg(reg_index) <= '1'; else -- shift stuff through sig_shift_reg(reg_index) <= sig_shift_reg(reg_index-1); end if; end if; end process DO_SHIFT_REG_SEGMENT; end generate DO_SHIF_REG; ----------------------------------------------------------------------------- -- End of Shift register logic ----------------------------------------------------------------------------- end generate DO_MULTI_CLK_PULSE; end architecture implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/axi_bram_ctrl.vhd

4

43388

------------------------------------------------------------------------------- -- axi_bram_ctrl.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: axi_bram_ctrl_wrapper.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller IP core. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v4_0) -- | -- |--axi_bram_ctrl_top.vhd -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- ecc_gen.vhd -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; library work; use work.axi_bram_ctrl_top; use work.axi_bram_ctrl_funcs.all; --use work.coregen_comp_defs.all; library blk_mem_gen_v8_2; use blk_mem_gen_v8_2.all; ------------------------------------------------------------------------------ entity axi_bram_ctrl is generic ( C_BRAM_INST_MODE : string := "EXTERNAL"; -- external ; internal --determines whether the bmg is external or internal to axi bram ctrl wrapper C_MEMORY_DEPTH : integer := 4096; --Memory depth specified by the user C_BRAM_ADDR_WIDTH : integer := 12; -- Width of AXI address bus (in bits) C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH : INTEGER := 4; -- AXI ID vector width C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1; -- Support for narrow burst operations C_SINGLE_PORT_BRAM : INTEGER := 0; -- Enable single port usage of BRAM C_FAMILY : string := "virtex7"; -- Specify the target architecture type -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_TYPE : integer := 1; C_FAULT_INJECT : integer := 0; -- Enable fault injection registers -- (default = disabled) C_ECC_ONOFF_RESET_VALUE : integer := 1 -- By default, ECC checking is on -- (can disable ECC @ reset by setting this to 0) ); port ( -- AXI Interface Signals -- AXI Clock and Reset s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; ecc_interrupt : out std_logic := '0'; ecc_ue : out std_logic := '0'; -- axi write address channel Signals (AW) s_axi_awid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awlen : in std_logic_vector(7 downto 0); s_axi_awsize : in std_logic_vector(2 downto 0); s_axi_awburst : in std_logic_vector(1 downto 0); s_axi_awlock : in std_logic; s_axi_awcache : in std_logic_vector(3 downto 0); s_axi_awprot : in std_logic_vector(2 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; -- axi write data channel Signals (W) s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wstrb : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0); s_axi_wlast : in std_logic; s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; -- axi write data response Channel Signals (B) s_axi_bid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; -- axi read address channel Signals (AR) s_axi_arid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_arlen : in std_logic_vector(7 downto 0); s_axi_arsize : in std_logic_vector(2 downto 0); s_axi_arburst : in std_logic_vector(1 downto 0); s_axi_arlock : in std_logic; s_axi_arcache : in std_logic_vector(3 downto 0); s_axi_arprot : in std_logic_vector(2 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; -- axi read data channel Signals (R) s_axi_rid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rlast : out std_logic; s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; -- axi-lite ecc register Interface Signals -- axi-lite clock and Reset -- note: axi-lite control IF and AXI IF share the same clock. -- s_axi_ctrl_aclk : in std_logic; -- s_axi_ctrl_aresetn : in std_logic; -- axi-lite write address Channel Signals (AW) s_axi_ctrl_awvalid : in std_logic; s_axi_ctrl_awready : out std_logic; s_axi_ctrl_awaddr : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- axi-lite write data Channel Signals (W) s_axi_ctrl_wdata : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); s_axi_ctrl_wvalid : in std_logic; s_axi_ctrl_wready : out std_logic; -- axi-lite write data Response Channel Signals (B) s_axi_ctrl_bresp : out std_logic_vector(1 downto 0); s_axi_ctrl_bvalid : out std_logic; s_axi_ctrl_bready : in std_logic; -- axi-lite read address Channel Signals (AR) s_axi_ctrl_araddr : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); s_axi_ctrl_arvalid : in std_logic; s_axi_ctrl_arready : out std_logic; -- axi-lite read data Channel Signals (R) s_axi_ctrl_rdata : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); s_axi_ctrl_rresp : out std_logic_vector(1 downto 0); s_axi_ctrl_rvalid : out std_logic; s_axi_ctrl_rready : in std_logic; -- bram interface signals (Port A) bram_rst_a : out std_logic; bram_clk_a : out std_logic; bram_en_a : out std_logic; bram_we_a : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); bram_addr_a : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); bram_wrdata_a : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); bram_rddata_a : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); -- bram interface signals (Port B) bram_rst_b : out std_logic; bram_clk_b : out std_logic; bram_en_b : out std_logic; bram_we_b : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); bram_addr_b : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); bram_wrdata_b : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); bram_rddata_b : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) ); end entity axi_bram_ctrl; ------------------------------------------------------------------------------- architecture implementation of axi_bram_ctrl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------ -- FUNCTION: if_then_else -- This function is used to implement an IF..THEN when such a statement is not -- allowed. ------------------------------------------------------------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS VARIABLE retval : INTEGER := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; --------------------------------------------------------------------------- -- FUNCTION : log2roundup --------------------------------------------------------------------------- FUNCTION log2roundup (data_value : integer) RETURN integer IS VARIABLE width : integer := 0; VARIABLE cnt : integer := 1; CONSTANT lower_limit : integer := 1; CONSTANT upper_limit : integer := 8; BEGIN IF (data_value <= 1) THEN width := 0; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt *2; END LOOP; END IF; RETURN width; END log2roundup; ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- -- Only instantiate logic based on C_S_AXI_PROTOCOL. -- Determine external ECC width. -- Use function defined in axi_bram_ctrl_funcs package. -- Set internal parameters for ECC register enabling when C_ECC = 1 -- Catastrophic error indicated with ECC_UE & Interrupt flags. -- Counter only sized when C_ECC = 1. -- Selects CE counter width/threshold to assert ECC_Interrupt -- Hard coded at 8-bits to capture and count up to 256 correctable errors. -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code constant GND : std_logic := '0'; constant VCC : std_logic := '1'; constant ZERO1 : std_logic_vector(0 downto 0) := (others => '0'); constant ZERO2 : std_logic_vector(1 downto 0) := (others => '0'); constant ZERO3 : std_logic_vector(2 downto 0) := (others => '0'); constant ZERO4 : std_logic_vector(3 downto 0) := (others => '0'); constant ZERO8 : std_logic_vector(7 downto 0) := (others => '0'); constant WSTRB_ZERO : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); constant ZERO16 : std_logic_vector(15 downto 0) := (others => '0'); constant ZERO32 : std_logic_vector(31 downto 0) := (others => '0'); constant ZERO64 : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); CONSTANT MEM_TYPE : INTEGER := if_then_else((C_SINGLE_PORT_BRAM=1),0,2); CONSTANT BWE_B : INTEGER := if_then_else((C_SINGLE_PORT_BRAM=1),0,1); CONSTANT BMG_ADDR_WIDTH : INTEGER := log2roundup(C_MEMORY_DEPTH) + log2roundup(C_S_AXI_DATA_WIDTH/8) ; ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal clka_bram_clka_i : std_logic := '0'; signal rsta_bram_rsta_i : std_logic := '0'; signal ena_bram_ena_i : std_logic := '0'; signal REGCEA : std_logic := '0'; signal wea_bram_wea_i : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal addra_bram_addra_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal dina_bram_dina_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal douta_bram_douta_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); signal clkb_bram_clkb_i : std_logic := '0'; signal rstb_bram_rstb_i : std_logic := '0'; signal enb_bram_enb_i : std_logic := '0'; signal REGCEB : std_logic := '0'; signal web_bram_web_i : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal addrb_bram_addrb_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal dinb_bram_dinb_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal doutb_bram_doutb_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); ----------------------------------------------------------------------- -- Architecture Body ----------------------------------------------------------------------- begin gint_inst: IF (C_BRAM_INST_MODE = "INTERNAL" ) GENERATE constant c_addrb_width : INTEGER := log2roundup(C_MEMORY_DEPTH); constant C_WEA_WIDTH_I : INTEGER := (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) ; constant C_WRITE_WIDTH_A_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ; constant C_READ_WIDTH_A_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))); constant C_ADDRA_WIDTH_I : INTEGER := log2roundup(C_MEMORY_DEPTH); constant C_WEB_WIDTH_I : INTEGER := (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))); constant C_WRITE_WIDTH_B_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))); constant C_READ_WIDTH_B_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))); signal s_axi_rdaddrecc_bmg_int : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0); signal s_axi_dbiterr_bmg_int : STD_LOGIC; signal s_axi_sbiterr_bmg_int : STD_LOGIC; signal s_axi_rvalid_bmg_int : STD_LOGIC; signal s_axi_rlast_bmg_int : STD_LOGIC; signal s_axi_rresp_bmg_int : STD_LOGIC_VECTOR(1 DOWNTO 0); signal s_axi_rdata_bmg_int : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); signal s_axi_rid_bmg_int : STD_LOGIC_VECTOR(3 DOWNTO 0); signal s_axi_arready_bmg_int : STD_LOGIC; signal s_axi_bvalid_bmg_int : STD_LOGIC; signal s_axi_bresp_bmg_int : STD_LOGIC_VECTOR(1 DOWNTO 0); signal s_axi_bid_bmg_int : STD_LOGIC_VECTOR(3 DOWNTO 0); signal s_axi_wready_bmg_int : STD_LOGIC; signal s_axi_awready_bmg_int : STD_LOGIC; signal rdaddrecc_bmg_int : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0); signal dbiterr_bmg_int : STD_LOGIC; signal sbiterr_bmg_int : STD_LOGIC; begin bmgv81_inst : entity blk_mem_gen_v8_2.blk_mem_gen_v8_2 GENERIC MAP( ---------------------------------------------------------------------------- -- Generic Declarations ---------------------------------------------------------------------------- --Device Family & Elaboration Directory Parameters: C_FAMILY => C_FAMILY, C_XDEVICEFAMILY => C_FAMILY, ---- C_ELABORATION_DIR => "NULL" , C_INTERFACE_TYPE => 0 , --General Memory Parameters: ----- C_ENABLE_32BIT_ADDRESS => 0 , C_MEM_TYPE => MEM_TYPE , C_BYTE_SIZE => 8 , C_ALGORITHM => 1 , C_PRIM_TYPE => 1 , --Memory Initialization Parameters: C_LOAD_INIT_FILE => 0 , C_INIT_FILE_NAME => "no_coe_file_loaded" , C_USE_DEFAULT_DATA => 0 , C_DEFAULT_DATA => "NULL" , --Port A Parameters: --Reset Parameters: C_HAS_RSTA => 0 , --Enable Parameters: C_HAS_ENA => 1 , C_HAS_REGCEA => 0 , --Byte Write Enable Parameters: C_USE_BYTE_WEA => 1 , C_WEA_WIDTH => C_WEA_WIDTH_I, --(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) , --Write Mode: C_WRITE_MODE_A => "WRITE_FIRST" , --Data-Addr Width Parameters: C_WRITE_WIDTH_A => C_WRITE_WIDTH_A_I,--(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) , C_READ_WIDTH_A => C_READ_WIDTH_A_I,--(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) , C_WRITE_DEPTH_A => C_MEMORY_DEPTH , C_READ_DEPTH_A => C_MEMORY_DEPTH , C_ADDRA_WIDTH => C_ADDRA_WIDTH_I,--log2roundup(C_MEMORY_DEPTH) , --Port B Parameters: --Reset Parameters: C_HAS_RSTB => 0 , --Enable Parameters: C_HAS_ENB => 1 , C_HAS_REGCEB => 0 , --Byte Write Enable Parameters: C_USE_BYTE_WEB => BWE_B , C_WEB_WIDTH => C_WEB_WIDTH_I,--(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) , --Write Mode: C_WRITE_MODE_B => "WRITE_FIRST" , --Data-Addr Width Parameters: C_WRITE_WIDTH_B => C_WRITE_WIDTH_B_I,--(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) , C_READ_WIDTH_B => C_READ_WIDTH_B_I,--(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) , C_WRITE_DEPTH_B => C_MEMORY_DEPTH , C_READ_DEPTH_B => C_MEMORY_DEPTH , C_ADDRB_WIDTH => C_ADDRB_WIDTH,--log2roundup(C_MEMORY_DEPTH) , --Output Registers/ Pipelining Parameters: C_HAS_MEM_OUTPUT_REGS_A => 0 , C_HAS_MEM_OUTPUT_REGS_B => 0 , C_HAS_MUX_OUTPUT_REGS_A => 0 , C_HAS_MUX_OUTPUT_REGS_B => 0 , C_MUX_PIPELINE_STAGES => 0 , --Input/Output Registers for SoftECC : C_HAS_SOFTECC_INPUT_REGS_A => 0 , C_HAS_SOFTECC_OUTPUT_REGS_B=> 0 , --ECC Parameters C_USE_ECC => 0 , C_USE_SOFTECC => 0 , C_HAS_INJECTERR => 0 , C_EN_ECC_PIPE => 0, C_EN_SLEEP_PIN => 0, --Simulation Model Parameters: C_SIM_COLLISION_CHECK => "NONE" , C_COMMON_CLK => 1 , C_DISABLE_WARN_BHV_COLL => 1 , C_DISABLE_WARN_BHV_RANGE => 1 ) PORT MAP( ---------------------------------------------------------------------------- -- Input and Output Declarations ---------------------------------------------------------------------------- -- Native BMG Input and Output Port Declarations --Port A: clka => clka_bram_clka_i , rsta => rsta_bram_rsta_i , ena => ena_bram_ena_i , regcea => GND , wea => wea_bram_wea_i , addra => addra_bram_addra_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) , --addra => addra_bram_addra_i(C_S_AXI_ADDR_WIDTH-1 downto (C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) , dina => dina_bram_dina_i , douta => douta_bram_douta_i , --port b: clkb => clkb_bram_clkb_i , rstb => rstb_bram_rstb_i , enb => enb_bram_enb_i , regceb => GND , web => web_bram_web_i , addrb => addrb_bram_addrb_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) , --addrb => addrb_bram_addrb_i(C_S_AXI_ADDR_WIDTH-1 downto (C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) , dinb => dinb_bram_dinb_i , doutb => doutb_bram_doutb_i , --ecc: injectsbiterr => GND , injectdbiterr => GND , sbiterr => sbiterr_bmg_int, dbiterr => dbiterr_bmg_int, rdaddrecc => rdaddrecc_bmg_int, eccpipece => GND, sleep => GND, -- axi bmg input and output Port Declarations -- axi global signals s_aclk => GND , s_aresetn => GND , -- axi full/lite slave write (write side) s_axi_awid => ZERO4 , s_axi_awaddr => ZERO32 , s_axi_awlen => ZERO8 , s_axi_awsize => ZERO3 , s_axi_awburst => ZERO2 , s_axi_awvalid => GND , s_axi_awready => s_axi_awready_bmg_int, s_axi_wdata => ZERO64 , s_axi_wstrb => WSTRB_ZERO, s_axi_wlast => GND , s_axi_wvalid => GND , s_axi_wready => s_axi_wready_bmg_int, s_axi_bid => s_axi_bid_bmg_int, s_axi_bresp => s_axi_bresp_bmg_int, s_axi_bvalid => s_axi_bvalid_bmg_int, s_axi_bready => GND , -- axi full/lite slave read (Write side) s_axi_arid => ZERO4, s_axi_araddr => "00000000000000000000000000000000", s_axi_arlen => "00000000", s_axi_arsize => "000", s_axi_arburst => "00", s_axi_arvalid => '0', s_axi_arready => s_axi_arready_bmg_int, s_axi_rid => s_axi_rid_bmg_int, s_axi_rdata => s_axi_rdata_bmg_int, s_axi_rresp => s_axi_rresp_bmg_int, s_axi_rlast => s_axi_rlast_bmg_int, s_axi_rvalid => s_axi_rvalid_bmg_int, s_axi_rready => GND , -- axi full/lite sideband Signals s_axi_injectsbiterr => GND , s_axi_injectdbiterr => GND , s_axi_sbiterr => s_axi_sbiterr_bmg_int, s_axi_dbiterr => s_axi_dbiterr_bmg_int, s_axi_rdaddrecc => s_axi_rdaddrecc_bmg_int ); abcv4_0_int_inst : entity work.axi_bram_ctrl_top generic map( -- AXI Parameters C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , -- AXI ID vector width C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST , -- Support for narrow burst operations C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , -- Enable single port usage of BRAM -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC => C_ECC , -- Enables or disables ECC functionality C_ECC_TYPE => C_ECC_TYPE , C_FAULT_INJECT => C_FAULT_INJECT , -- Enable fault injection registers -- (default = disabled) C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE -- By default, ECC checking is on -- (can disable ECC @ reset by setting this to 0) ) port map( -- AXI Interface Signals -- AXI Clock and Reset S_AXI_ACLK => S_AXI_ACLK , S_AXI_ARESETN => S_AXI_ARESETN , ECC_Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , -- AXI Write Address Channel Signals (AW) S_AXI_AWID => S_AXI_AWID , S_AXI_AWADDR => S_AXI_AWADDR , S_AXI_AWLEN => S_AXI_AWLEN , S_AXI_AWSIZE => S_AXI_AWSIZE , S_AXI_AWBURST => S_AXI_AWBURST , S_AXI_AWLOCK => S_AXI_AWLOCK , S_AXI_AWCACHE => S_AXI_AWCACHE , S_AXI_AWPROT => S_AXI_AWPROT , S_AXI_AWVALID => S_AXI_AWVALID , S_AXI_AWREADY => S_AXI_AWREADY , -- AXI Write Data Channel Signals (W) S_AXI_WDATA => S_AXI_WDATA , S_AXI_WSTRB => S_AXI_WSTRB , S_AXI_WLAST => S_AXI_WLAST , S_AXI_WVALID => S_AXI_WVALID , S_AXI_WREADY => S_AXI_WREADY , -- AXI Write Data Response Channel Signals (B) S_AXI_BID => S_AXI_BID , S_AXI_BRESP => S_AXI_BRESP , S_AXI_BVALID => S_AXI_BVALID , S_AXI_BREADY => S_AXI_BREADY , -- AXI Read Address Channel Signals (AR) S_AXI_ARID => S_AXI_ARID , S_AXI_ARADDR => S_AXI_ARADDR , S_AXI_ARLEN => S_AXI_ARLEN , S_AXI_ARSIZE => S_AXI_ARSIZE , S_AXI_ARBURST => S_AXI_ARBURST , S_AXI_ARLOCK => S_AXI_ARLOCK , S_AXI_ARCACHE => S_AXI_ARCACHE , S_AXI_ARPROT => S_AXI_ARPROT , S_AXI_ARVALID => S_AXI_ARVALID , S_AXI_ARREADY => S_AXI_ARREADY , -- AXI Read Data Channel Signals (R) S_AXI_RID => S_AXI_RID , S_AXI_RDATA => S_AXI_RDATA , S_AXI_RRESP => S_AXI_RRESP , S_AXI_RLAST => S_AXI_RLAST , S_AXI_RVALID => S_AXI_RVALID , S_AXI_RREADY => S_AXI_RREADY , -- AXI-Lite ECC Register Interface Signals -- AXI-Lite Write Address Channel Signals (AW) S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID , S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY , S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR , -- AXI-Lite Write Data Channel Signals (W) S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA , S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID , S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY , -- AXI-Lite Write Data Response Channel Signals (B) S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP , S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID , S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY , -- AXI-Lite Read Address Channel Signals (AR) S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR , S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID , S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY , -- AXI-Lite Read Data Channel Signals (R) S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA , S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP , S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID , S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY , -- BRAM Interface Signals (Port A) BRAM_Rst_A => rsta_bram_rsta_i , BRAM_Clk_A => clka_bram_clka_i , BRAM_En_A => ena_bram_ena_i , BRAM_WE_A => wea_bram_wea_i , BRAM_Addr_A => addra_bram_addra_i, BRAM_WrData_A => dina_bram_dina_i , BRAM_RdData_A => douta_bram_douta_i , -- BRAM Interface Signals (Port B) BRAM_Rst_B => rstb_bram_rstb_i , BRAM_Clk_B => clkb_bram_clkb_i , BRAM_En_B => enb_bram_enb_i , BRAM_WE_B => web_bram_web_i , BRAM_Addr_B => addrb_bram_addrb_i , BRAM_WrData_B => dinb_bram_dinb_i , BRAM_RdData_B => doutb_bram_doutb_i ); -- The following signals are driven 0's to remove the synthesis warnings bram_rst_a <= '0'; bram_clk_a <= '0'; bram_en_a <= '0'; bram_we_a <= (others => '0'); bram_addr_a <= (others => '0'); bram_wrdata_a <= (others => '0'); bram_rst_b <= '0'; bram_clk_b <= '0'; bram_en_b <= '0'; bram_we_b <= (others => '0'); bram_addr_b <= (others => '0'); bram_wrdata_b <= (others => '0'); END GENERATE gint_inst; -- End of internal bram instance gext_inst: IF (C_BRAM_INST_MODE = "EXTERNAL" ) GENERATE abcv4_0_ext_inst : entity work.axi_bram_ctrl_top generic map( -- AXI Parameters C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , -- AXI ID vector width C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST , -- Support for narrow burst operations C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , -- Enable single port usage of BRAM -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC => C_ECC , -- Enables or disables ECC functionality C_ECC_TYPE => C_ECC_TYPE , C_FAULT_INJECT => C_FAULT_INJECT , -- Enable fault injection registers -- (default = disabled) C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE -- By default, ECC checking is on -- (can disable ECC @ reset by setting this to 0) ) port map( -- AXI Interface Signals -- AXI Clock and Reset s_axi_aclk => s_axi_aclk , s_axi_aresetn => s_axi_aresetn , ecc_interrupt => ecc_interrupt , ecc_ue => ecc_ue , -- axi write address channel signals (aw) s_axi_awid => s_axi_awid , s_axi_awaddr => s_axi_awaddr , s_axi_awlen => s_axi_awlen , s_axi_awsize => s_axi_awsize , s_axi_awburst => s_axi_awburst , s_axi_awlock => s_axi_awlock , s_axi_awcache => s_axi_awcache , s_axi_awprot => s_axi_awprot , s_axi_awvalid => s_axi_awvalid , s_axi_awready => s_axi_awready , -- axi write data channel signals (w) s_axi_wdata => s_axi_wdata , s_axi_wstrb => s_axi_wstrb , s_axi_wlast => s_axi_wlast , s_axi_wvalid => s_axi_wvalid , s_axi_wready => s_axi_wready , -- axi write data response channel signals (b) s_axi_bid => s_axi_bid , s_axi_bresp => s_axi_bresp , s_axi_bvalid => s_axi_bvalid , s_axi_bready => s_axi_bready , -- axi read address channel signals (ar) s_axi_arid => s_axi_arid , s_axi_araddr => s_axi_araddr , s_axi_arlen => s_axi_arlen , s_axi_arsize => s_axi_arsize , s_axi_arburst => s_axi_arburst , s_axi_arlock => s_axi_arlock , s_axi_arcache => s_axi_arcache , s_axi_arprot => s_axi_arprot , s_axi_arvalid => s_axi_arvalid , s_axi_arready => s_axi_arready , -- axi read data channel signals (r) s_axi_rid => s_axi_rid , s_axi_rdata => s_axi_rdata , s_axi_rresp => s_axi_rresp , s_axi_rlast => s_axi_rlast , s_axi_rvalid => s_axi_rvalid , s_axi_rready => s_axi_rready , -- axi-lite ecc register interface signals -- axi-lite write address channel signals (aw) s_axi_ctrl_awvalid => s_axi_ctrl_awvalid , s_axi_ctrl_awready => s_axi_ctrl_awready , s_axi_ctrl_awaddr => s_axi_ctrl_awaddr , -- axi-lite write data channel signals (w) s_axi_ctrl_wdata => s_axi_ctrl_wdata , s_axi_ctrl_wvalid => s_axi_ctrl_wvalid , s_axi_ctrl_wready => s_axi_ctrl_wready , -- axi-lite write data response channel signals (b) s_axi_ctrl_bresp => s_axi_ctrl_bresp , s_axi_ctrl_bvalid => s_axi_ctrl_bvalid , s_axi_ctrl_bready => s_axi_ctrl_bready , -- axi-lite read address channel signals (ar) s_axi_ctrl_araddr => s_axi_ctrl_araddr , s_axi_ctrl_arvalid => s_axi_ctrl_arvalid , s_axi_ctrl_arready => s_axi_ctrl_arready , -- axi-lite read data channel signals (r) s_axi_ctrl_rdata => s_axi_ctrl_rdata , s_axi_ctrl_rresp => s_axi_ctrl_rresp , s_axi_ctrl_rvalid => s_axi_ctrl_rvalid , s_axi_ctrl_rready => s_axi_ctrl_rready , -- bram interface signals (port a) bram_rst_a => bram_rst_a , bram_clk_a => bram_clk_a , bram_en_a => bram_en_a , bram_we_a => bram_we_a , bram_addr_a => bram_addr_a , bram_wrdata_a => bram_wrdata_a , bram_rddata_a => bram_rddata_a , -- bram interface signals (port b) bram_rst_b => bram_rst_b , bram_clk_b => bram_clk_b , bram_en_b => bram_en_b , bram_we_b => bram_we_b , bram_addr_b => bram_addr_b , bram_wrdata_b => bram_wrdata_b , bram_rddata_b => bram_rddata_b ); END GENERATE gext_inst; -- End of internal bram instance end architecture implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_ftch_q_mngr.vhd

3

45519

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_ftch_queue.vhd -- Description: This entity is the descriptor fetch queue interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_ftch_q_mngr is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Stream Data width C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch for channel 1 C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch for channel 1 C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1; -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1; -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check C_INCLUDE_CH1 : integer range 0 to 1 := 1; -- Include or Exclude channel 1 scatter gather engine -- 0 = Exclude Channel 1 SG Engine -- 1 = Include Channel 1 SG Engine C_INCLUDE_CH2 : integer range 0 to 1 := 1; -- Include or Exclude channel 2 scatter gather engine -- 0 = Exclude Channel 2 SG Engine -- 1 = Include Channel 2 SG Engine C_ENABLE_CDMA : integer range 0 to 1 := 0; C_FAMILY : string := "virtex7" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_mm2s_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- p_reset_n : in std_logic ; ch2_sg_idle : in std_logic ; -- -- Channel 1 Control -- ch1_desc_flush : in std_logic ; -- ch1_cyclic : in std_logic ; -- ch1_cntrl_strm_stop : in std_logic ; ch1_ftch_active : in std_logic ; -- ch1_nxtdesc_wren : out std_logic ; -- ch1_ftch_queue_empty : out std_logic ; -- ch1_ftch_queue_full : out std_logic ; -- ch1_ftch_pause : out std_logic ; -- -- -- Channel 2 Control -- ch2_desc_flush : in std_logic ; -- ch2_cyclic : in std_logic ; -- ch2_ftch_active : in std_logic ; -- ch2_nxtdesc_wren : out std_logic ; -- ch2_ftch_queue_empty : out std_logic ; -- ch2_ftch_queue_full : out std_logic ; -- ch2_ftch_pause : out std_logic ; -- nxtdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- -- DataMover Command -- ftch_cmnd_wr : in std_logic ; -- ftch_cmnd_data : in std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- ftch_stale_desc : out std_logic ; -- -- -- MM2S Stream In from DataMover -- m_axis_mm2s_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_mm2s_tkeep : in std_logic_vector -- ((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0); -- m_axis_mm2s_tlast : in std_logic ; -- m_axis_mm2s_tvalid : in std_logic ; -- m_axis_mm2s_tready : out std_logic ; -- -- -- -- Channel 1 AXI Fetch Stream Out -- m_axis_ch1_ftch_aclk : in std_logic ; m_axis_ch1_ftch_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); -- m_axis_ch1_ftch_tvalid : out std_logic ; -- m_axis_ch1_ftch_tready : in std_logic ; -- m_axis_ch1_ftch_tlast : out std_logic ; -- m_axis_ch1_ftch_tdata_new : out std_logic_vector -- (96+31*C_ENABLE_CDMA downto 0); -- m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis_ch1_ftch_tvalid_new : out std_logic ; -- m_axis_ftch1_desc_available : out std_logic ; -- m_axis_ch2_ftch_tdata_new : out std_logic_vector -- (96+31*C_ENABLE_CDMA downto 0); -- m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector -- (31 downto 0); -- m_axis_ch2_ftch_tvalid_new : out std_logic ; -- m_axis_ftch2_desc_available : out std_logic ; -- -- Channel 2 AXI Fetch Stream Out -- m_axis_ch2_ftch_aclk : in std_logic ; -- m_axis_ch2_ftch_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_ch2_ftch_tvalid : out std_logic ; -- m_axis_ch2_ftch_tready : in std_logic ; -- m_axis_ch2_ftch_tlast : out std_logic ; -- m_axis_mm2s_cntrl_tdata : out std_logic_vector -- (31 downto 0); -- m_axis_mm2s_cntrl_tkeep : out std_logic_vector -- (3 downto 0); -- m_axis_mm2s_cntrl_tvalid : out std_logic ; -- m_axis_mm2s_cntrl_tready : in std_logic := '0'; -- m_axis_mm2s_cntrl_tlast : out std_logic -- ); end axi_sg_ftch_q_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_ftch_q_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; attribute mark_debug : string; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Determine the maximum word count for use in setting the word counter width -- Set bit width on max num words to fetch constant FETCH_COUNT : integer := max2(C_SG_CH1_WORDS_TO_FETCH ,C_SG_CH2_WORDS_TO_FETCH); -- LOG2 to get width of counter constant WORDS2FETCH_BITWIDTH : integer := clog2(FETCH_COUNT); -- Zero value for counter constant WORD_ZERO : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0'); -- One value for counter constant WORD_ONE : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0) := std_logic_vector(to_unsigned(1,WORDS2FETCH_BITWIDTH)); -- Seven value for counter constant WORD_SEVEN : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0) := std_logic_vector(to_unsigned(7,WORDS2FETCH_BITWIDTH)); constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal m_axis_mm2s_tready_i : std_logic := '0'; signal ch1_ftch_tready : std_logic := '0'; signal ch2_ftch_tready : std_logic := '0'; -- Misc Signals signal writing_curdesc : std_logic := '0'; signal fetch_word_count : std_logic_vector (WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0'); signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0'); signal lsbnxtdesc_tready : std_logic := '0'; signal msbnxtdesc_tready : std_logic := '0'; signal nxtdesc_tready : std_logic := '0'; signal ch1_writing_curdesc : std_logic := '0'; signal ch2_writing_curdesc : std_logic := '0'; signal m_axis_ch2_ftch_tvalid_1 : std_logic := '0'; -- KAPIL signal ch_desc_flush : std_logic := '0'; signal m_axis_ch_ftch_tready : std_logic := '0'; signal ch_ftch_queue_empty : std_logic := '0'; signal ch_ftch_queue_full : std_logic := '0'; signal ch_ftch_pause : std_logic := '0'; signal ch_writing_curdesc : std_logic := '0'; signal ch_ftch_tready : std_logic := '0'; signal m_axis_ch_ftch_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal m_axis_ch_ftch_tvalid : std_logic := '0'; signal m_axis_ch_ftch_tlast : std_logic := '0'; signal data_concat : std_logic_vector (95 downto 0) := (others => '0'); signal data_concat_mcdma : std_logic_vector (63 downto 0) := (others => '0'); signal next_bd : std_logic_vector (31 downto 0) := (others => '0'); signal data_concat_valid, tvalid_new : std_logic; attribute mark_debug of data_concat_valid : signal is "true"; attribute mark_debug of tvalid_new : signal is "true"; signal data_concat_tlast, tlast_new : std_logic; attribute mark_debug of data_concat_tlast : signal is "true"; attribute mark_debug of tlast_new : signal is "true"; signal counter : std_logic_vector (C_SG_CH1_WORDS_TO_FETCH-1 downto 0); attribute mark_debug of counter : signal is "true"; signal sof_ftch_desc : std_logic; signal nxtdesc_int : std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- attribute mark_debug of nxtdesc_int : signal is "true"; signal cyclic_enable : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin cyclic_enable <= ch1_cyclic when ch1_ftch_active = '1' else ch2_cyclic; nxtdesc <= nxtdesc_int; TLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH = 13) generate -- TLAST is generated when 8th beat is received tlast_new <= counter (7) and m_axis_mm2s_tvalid; tvalid_new <= counter (7) and m_axis_mm2s_tvalid; SOF_CHECK : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tvalid = '1' and m_axis_mm2s_tlast = '1'))then sof_ftch_desc <= '0'; elsif(counter (6) = '1' and m_axis_mm2s_tready_i = '1' and m_axis_mm2s_tdata(27) = '1' )then sof_ftch_desc <= '1'; end if; end if; end process SOF_CHECK; end generate TLAST_GEN; NOTLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH /= 13) generate sof_ftch_desc <= '0'; CDMA : if C_ENABLE_CDMA = 1 generate -- For CDMA TLAST is generated when 7th beat is received -- because last one is not needed tlast_new <= counter (6) and m_axis_mm2s_tvalid; tvalid_new <=counter (6) and m_axis_mm2s_tvalid; end generate CDMA; NOCDMA : if C_ENABLE_CDMA = 0 generate -- For DMA tlast is generated with 8th beat tlast_new <= counter (7) and m_axis_mm2s_tvalid; tvalid_new <= counter (7) and m_axis_mm2s_tvalid; end generate NOCDMA; end generate NOTLAST_GEN; -- Following shift register keeps track of number of data beats -- of BD that is being read DATA_BEAT_REG : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1')) then counter (0) <= '1'; counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= (others => '0'); Elsif (m_axis_mm2s_tvalid = '1') then counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= counter (C_SG_CH1_WORDS_TO_FETCH-2 downto 0); counter (0) <= '0'; end if; end if; end process DATA_BEAT_REG; -- Registering the Buffer address from BD, 3rd beat -- Common for DMA, CDMA DATA_REG1 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (31 downto 0) <= (others => '0'); Elsif (counter (2) = '1') then data_concat (31 downto 0) <= m_axis_mm2s_tdata; end if; end if; end process DATA_REG1; DMA_REG2 : if C_ENABLE_CDMA = 0 generate begin -- For DMA, the 7th beat has the control information DATA_REG2 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (63 downto 32) <= (others => '0'); Elsif (counter (6) = '1') then data_concat (63 downto 32) <= m_axis_mm2s_tdata; end if; end if; end process DATA_REG2; end generate DMA_REG2; CDMA_REG2 : if C_ENABLE_CDMA = 1 generate begin -- For CDMA, the 5th beat has the DA information DATA_REG2 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (63 downto 32) <= (others => '0'); Elsif (counter (4) = '1') then data_concat (63 downto 32) <= m_axis_mm2s_tdata; end if; end if; end process DATA_REG2; end generate CDMA_REG2; NOFLOP_FOR_QUEUE : if C_SG_CH1_WORDS_TO_FETCH = 8 generate begin -- Last beat is directly concatenated and passed to FIFO -- Masking the CMPLT bit with cyclic_enable data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0); data_concat_valid <= tvalid_new; data_concat_tlast <= tlast_new; end generate NOFLOP_FOR_QUEUE; -- In absence of queuing option the last beat needs to be floped FLOP_FOR_NOQUEUE : if C_SG_CH1_WORDS_TO_FETCH = 13 generate begin NO_FETCH_Q : if C_SG_FTCH_DESC2QUEUE = 0 generate DATA_REG3 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (95 downto 64) <= (others => '0'); Elsif (counter (7) = '1') then data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0); end if; end if; end process DATA_REG3; end generate NO_FETCH_Q; FETCH_Q : if C_SG_FTCH_DESC2QUEUE /= 0 generate DATA_REG3 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat (95) <= '0'; Elsif (counter (7) = '1') then data_concat (95) <= m_axis_mm2s_tdata (31) and (not cyclic_enable); end if; end if; end process DATA_REG3; data_concat (94 downto 64) <= (others => '0'); end generate FETCH_Q; DATA_CNTRL : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat_valid <= '0'; data_concat_tlast <= '0'; Else data_concat_valid <= tvalid_new; data_concat_tlast <= tlast_new; end if; end if; end process DATA_CNTRL; end generate FLOP_FOR_NOQUEUE; -- Since the McDMA BD has two more fields to be captured -- following procedures are needed NOMCDMA_FTECH : if C_ENABLE_MULTI_CHANNEL = 0 generate begin data_concat_mcdma <= (others => '0'); end generate NOMCDMA_FTECH; MCDMA_BD_FETCH : if C_ENABLE_MULTI_CHANNEL = 1 generate begin DATA_MCDMA_REG1 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat_mcdma (31 downto 0) <= (others => '0'); Elsif (counter (4) = '1') then data_concat_mcdma (31 downto 0) <= m_axis_mm2s_tdata; end if; end if; end process DATA_MCDMA_REG1; DATA_MCDMA_REG2 : process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then data_concat_mcdma (63 downto 32) <= (others => '0'); Elsif (counter (5) = '1') then data_concat_mcdma (63 downto 32) <= m_axis_mm2s_tdata; end if; end if; end process DATA_MCDMA_REG2; end generate MCDMA_BD_FETCH; --------------------------------------------------------------------------- -- For 32-bit SG addresses then drive zero on msb --------------------------------------------------------------------------- GEN_CURDESC_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin msb_curdesc <= (others => '0'); end generate GEN_CURDESC_32; --------------------------------------------------------------------------- -- For 64-bit SG addresses then capture upper order adder to msb --------------------------------------------------------------------------- GEN_CURDESC_64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin CAPTURE_CURADDR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then msb_curdesc <= (others => '0'); elsif(ftch_cmnd_wr = '1')then msb_curdesc <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto DATAMOVER_CMD_ADDRMSB_BOFST + DATAMOVER_CMD_ADDRLSB_BIT + 1); end if; end if; end process CAPTURE_CURADDR; end generate GEN_CURDESC_64; --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_LSB_NXTPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then nxtdesc_int(31 downto 0) <= (others => '0'); -- On valid and word count at 0 and channel active capture LSB next pointer elsif(m_axis_mm2s_tvalid = '1' and counter (0) = '1')then nxtdesc_int(31 downto 6) <= m_axis_mm2s_tdata (31 downto 6); -- BD addresses are always 16 word 32-bit aligned nxtdesc_int(5 downto 0) <= (others => '0'); end if; end if; end process REG_LSB_NXTPNTR; lsbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1' and counter (0) = '1' --etch_word_count = WORD_ZERO else '0'; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_NXTPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then nxtdesc_int(63 downto 32) <= (others => '0'); ch1_nxtdesc_wren <= '0'; ch2_nxtdesc_wren <= '0'; -- Capture upper pointer, drive ready to progress DataMover -- and also write nxtdesc out elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then nxtdesc_int(63 downto 32) <= m_axis_mm2s_tdata; ch1_nxtdesc_wren <= ch1_ftch_active; ch2_nxtdesc_wren <= ch2_ftch_active; -- Assert tready/wren for only 1 clock else ch1_nxtdesc_wren <= '0'; ch2_nxtdesc_wren <= '0'; end if; end if; end process REG_MSB_NXTPNTR; msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1' and counter (1) = '1' --fetch_word_count = WORD_ONE else '0'; end generate GEN_UPPER_MSB_NXTDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_NO_UPR_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_NXTPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then ch1_nxtdesc_wren <= '0'; ch2_nxtdesc_wren <= '0'; -- Throw away second word but drive ready to progress DataMover -- and also write nxtdesc out elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then --fetch_word_count = WORD_ONE)then ch1_nxtdesc_wren <= ch1_ftch_active; ch2_nxtdesc_wren <= ch2_ftch_active; -- Assert for only 1 clock else ch1_nxtdesc_wren <= '0'; ch2_nxtdesc_wren <= '0'; end if; end if; end process REG_MSB_NXTPNTR; msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1' and counter (1) = '1' --fetch_word_count = WORD_ONE else '0'; end generate GEN_NO_UPR_MSB_NXTDESC; -- Drive ready to DataMover for ether lsb or msb capture nxtdesc_tready <= msbnxtdesc_tready or lsbnxtdesc_tready; -- Generate logic for checking stale descriptor GEN_STALE_DESC_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 or C_SG_CH2_ENBL_STALE_ERROR = 1 generate begin --------------------------------------------------------------------------- -- Examine Completed BIT to determine if stale descriptor fetched --------------------------------------------------------------------------- CMPLTD_CHECK : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then ftch_stale_desc <= '0'; -- On valid and word count at 0 and channel active capture LSB next pointer elsif(m_axis_mm2s_tvalid = '1' and counter (7) = '1' --fetch_word_count = WORD_SEVEN and m_axis_mm2s_tready_i = '1' and m_axis_mm2s_tdata(DESC_STS_CMPLTD_BIT) = '1' )then ftch_stale_desc <= '1' and (not cyclic_enable); else ftch_stale_desc <= '0'; end if; end if; end process CMPLTD_CHECK; end generate GEN_STALE_DESC_CHECK; -- No needed logic for checking stale descriptor GEN_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 and C_SG_CH2_ENBL_STALE_ERROR = 0 generate begin ftch_stale_desc <= '0'; end generate GEN_NO_STALE_CHECK; --------------------------------------------------------------------------- -- SG Queueing therefore pass stream signals to -- FIFO --------------------------------------------------------------------------- GEN_QUEUE : if C_SG_FTCH_DESC2QUEUE /= 0 generate begin -- Instantiate the queue version FTCH_QUEUE_I : entity axi_sg_v4_1.axi_sg_ftch_queue generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH , C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE , C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH , C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC , C_ASYNC => C_ASYNC , C_FAMILY => C_FAMILY , C_SG2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH , C_INCLUDE_MM2S => C_INCLUDE_CH1, C_INCLUDE_S2MM => C_INCLUDE_CH2, C_ENABLE_CDMA => C_ENABLE_CDMA, C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_primary_aclk => m_axi_mm2s_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , p_reset_n => p_reset_n , ch2_sg_idle => '0' , -- Channel Control desc1_flush => ch1_desc_flush , desc2_flush => ch2_desc_flush , ch1_cntrl_strm_stop => ch1_cntrl_strm_stop , ftch1_active => ch1_ftch_active , ftch2_active => ch2_ftch_active , ftch1_queue_empty => ch1_ftch_queue_empty , ftch2_queue_empty => ch2_ftch_queue_empty , ftch1_queue_full => ch1_ftch_queue_full , ftch2_queue_full => ch2_ftch_queue_full , ftch1_pause => ch1_ftch_pause , ftch2_pause => ch2_ftch_pause , writing_nxtdesc_in => nxtdesc_tready , writing1_curdesc_out => ch1_writing_curdesc , writing2_curdesc_out => ch2_writing_curdesc , -- DataMover Command ftch_cmnd_wr => ftch_cmnd_wr , ftch_cmnd_data => ftch_cmnd_data , -- MM2S Stream In from DataMover m_axis_mm2s_tdata => m_axis_mm2s_tdata , m_axis_mm2s_tlast => m_axis_mm2s_tlast , m_axis_mm2s_tvalid => m_axis_mm2s_tvalid , sof_ftch_desc => sof_ftch_desc , next_bd => nxtdesc_int , data_concat => data_concat, data_concat_mcdma => data_concat_mcdma, data_concat_valid => data_concat_valid, data_concat_tlast => data_concat_tlast, m_axis1_mm2s_tready => ch1_ftch_tready , m_axis2_mm2s_tready => ch2_ftch_tready , -- Channel 1 AXI Fetch Stream Out m_axis_ftch_aclk => m_axi_sg_aclk, --m_axis_ch_ftch_aclk , m_axis_ftch1_tdata => m_axis_ch1_ftch_tdata , m_axis_ftch1_tvalid => m_axis_ch1_ftch_tvalid , m_axis_ftch1_tready => m_axis_ch1_ftch_tready , m_axis_ftch1_tlast => m_axis_ch1_ftch_tlast , m_axis_ftch1_tdata_new => m_axis_ch1_ftch_tdata_new , m_axis_ftch1_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new , m_axis_ftch1_tvalid_new => m_axis_ch1_ftch_tvalid_new , m_axis_ftch1_desc_available => m_axis_ftch1_desc_available , m_axis_ftch2_tdata_new => m_axis_ch2_ftch_tdata_new , m_axis_ftch2_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new , m_axis_ftch2_tvalid_new => m_axis_ch2_ftch_tvalid_new , m_axis_ftch2_desc_available => m_axis_ftch2_desc_available , m_axis_ftch2_tdata => m_axis_ch2_ftch_tdata , m_axis_ftch2_tvalid => m_axis_ch2_ftch_tvalid , m_axis_ftch2_tready => m_axis_ch2_ftch_tready , m_axis_ftch2_tlast => m_axis_ch2_ftch_tlast , m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata , m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep , m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid , m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready , m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ); m_axis_ch2_ftch_tdata_mcdma_nxt <= (others => '0'); end generate GEN_QUEUE; -- No SG Queueing therefore pass stream signals straight -- out channel port GEN_NO_QUEUE : if C_SG_FTCH_DESC2QUEUE = 0 generate begin -- Instantiate the No queue version NO_FTCH_QUEUE_I : entity axi_sg_v4_1.axi_sg_ftch_noqueue generic map ( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH, C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL, C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC , C_ASYNC => C_ASYNC , C_FAMILY => C_FAMILY , C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH , C_ENABLE_CH1 => C_INCLUDE_CH1 ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_primary_aclk => m_axi_mm2s_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , p_reset_n => p_reset_n , -- Channel Control desc_flush => ch1_desc_flush , ch1_cntrl_strm_stop => ch1_cntrl_strm_stop , ftch_active => ch1_ftch_active , ftch_queue_empty => ch1_ftch_queue_empty , ftch_queue_full => ch1_ftch_queue_full , desc2_flush => ch2_desc_flush , ftch2_active => ch2_ftch_active , ftch2_queue_empty => ch2_ftch_queue_empty , ftch2_queue_full => ch2_ftch_queue_full , writing_nxtdesc_in => nxtdesc_tready , writing_curdesc_out => ch1_writing_curdesc , writing2_curdesc_out => ch2_writing_curdesc , -- DataMover Command ftch_cmnd_wr => ftch_cmnd_wr , ftch_cmnd_data => ftch_cmnd_data , -- MM2S Stream In from DataMover m_axis_mm2s_tdata => m_axis_mm2s_tdata , m_axis_mm2s_tlast => m_axis_mm2s_tlast , m_axis_mm2s_tvalid => m_axis_mm2s_tvalid , m_axis_mm2s_tready => ch1_ftch_tready , m_axis2_mm2s_tready => ch2_ftch_tready , sof_ftch_desc => sof_ftch_desc , next_bd => nxtdesc_int , data_concat => data_concat, data_concat_mcdma => data_concat_mcdma, data_concat_valid => data_concat_valid, data_concat_tlast => data_concat_tlast, -- Channel 1 AXI Fetch Stream Out m_axis_ftch_tdata => m_axis_ch1_ftch_tdata , m_axis_ftch_tvalid => m_axis_ch1_ftch_tvalid , m_axis_ftch_tready => m_axis_ch1_ftch_tready , m_axis_ftch_tlast => m_axis_ch1_ftch_tlast , m_axis_ftch_tdata_new => m_axis_ch1_ftch_tdata_new , m_axis_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new , m_axis_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new , m_axis_ftch_desc_available => m_axis_ftch1_desc_available , m_axis2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new , m_axis2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new , m_axis2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt , m_axis2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new , m_axis2_ftch_desc_available => m_axis_ftch2_desc_available , m_axis2_ftch_tdata => m_axis_ch2_ftch_tdata , m_axis2_ftch_tvalid => m_axis_ch2_ftch_tvalid , m_axis2_ftch_tready => m_axis_ch2_ftch_tready , m_axis2_ftch_tlast => m_axis_ch2_ftch_tlast , m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata , m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep , m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid , m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready , m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ); ch1_ftch_pause <= '0'; ch2_ftch_pause <= '0'; end generate GEN_NO_QUEUE; ------------------------------------------------------------------------------- -- DataMover TREADY MUX ------------------------------------------------------------------------------- writing_curdesc <= ch1_writing_curdesc or ch2_writing_curdesc or ftch_cmnd_wr; TREADY_MUX : process(writing_curdesc, fetch_word_count, nxtdesc_tready, -- channel 1 signals ch1_ftch_active, ch1_desc_flush, ch1_ftch_tready, -- channel 2 signals ch2_ftch_active, ch2_desc_flush, counter(0), counter(1), ch2_ftch_tready) begin -- If commmanded to flush descriptor then assert ready -- to datamover until active de-asserts. this allows -- any commanded fetches to complete. if( (ch1_desc_flush = '1' and ch1_ftch_active = '1') or(ch2_desc_flush = '1' and ch2_ftch_active = '1'))then m_axis_mm2s_tready_i <= '1'; -- NOT ready if cmnd being written because -- curdesc gets written to queue elsif(writing_curdesc = '1')then m_axis_mm2s_tready_i <= '0'; -- First two words drive ready from internal logic elsif(counter(0) = '1' or counter(1)='1')then m_axis_mm2s_tready_i <= nxtdesc_tready; -- Remainder stream words drive ready from channel input else m_axis_mm2s_tready_i <= (ch1_ftch_active and ch1_ftch_tready) or (ch2_ftch_active and ch2_ftch_tready); end if; end process TREADY_MUX; m_axis_mm2s_tready <= m_axis_mm2s_tready_i; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_s2mm_omit_wrap.vhd

18

17501

------------------------------------------------------------------------------- -- axi_datamover_s2mm_omit_wrap.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_omit_wrap.vhd -- -- Description: -- This file implements the DataMover MM2S Omit Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_omit_wrap is generic ( C_INCLUDE_S2MM : Integer range 0 to 2 := 0; -- Specifies the type of S2MM function to include -- 0 = Omit S2MM functionality -- 1 = Full S2MM Functionality -- 2 = Lite S2MM functionality C_S2MM_AWID : Integer range 0 to 255 := 9; -- Specifies the constant value to output on -- the ARID output port C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the S2MM ID port C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the S2MM Master Stream Data -- Channel data bus C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit S2MM Status FIFO -- 1 = Include S2MM Status FIFO C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the S2MM Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the S2MM function -- 0 = Omit DRE -- 1 = Include DRE C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the S2MM function C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if Store and Forward is enabled C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1; -- This parameter specifies the depth of the S2MM internal -- address pipeline queues in the Write Address Controller -- and the Write Data Controller. Increasing this value will -- allow more Write Addresses to be issued to the AXI4 Write -- Address Channel before transmission of the associated -- write data on the Write Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- S2MM Primary Clock and reset inputs ----------------------- s2mm_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- S2MM Primary Reset input -- s2mm_aresetn : in std_logic; -- -- Reset used for the internal master logic -- -------------------------------------------------------------- -- S2MM Halt request input control --------------------------- s2mm_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- S2MM Halt Complete status flag -- s2mm_halt_cmplt : out std_logic; -- -- Active high soft shutdown complete status -- -------------------------------------------------------------- -- S2MM Error discrete output -------------------------------- s2mm_err : Out std_logic; -- -- Composite Error indication -- -------------------------------------------------------------- -- Optional S2MM Command/Status Clock and Reset Inputs ------- -- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 -- s2mm_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- s2mm_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- -------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) ----------------------------------------------------- s2mm_cmd_wvalid : in std_logic; -- s2mm_cmd_wready : out std_logic; -- s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); -- -------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) -------------------------------------------------------- s2mm_sts_wvalid : out std_logic; -- s2mm_sts_wready : in std_logic; -- s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); -- s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); -- s2mm_sts_wlast : out std_logic; -- ---------------------------------------------------------------------------------------------------- -- Address posting controls ----------------------------------------- s2mm_allow_addr_req : in std_logic; -- s2mm_addr_req_posted : out std_logic; -- s2mm_wr_xfer_cmplt : out std_logic; -- s2mm_ld_nxt_len : out std_logic; -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- --------------------------------------------------------------------- -- S2MM AXI Address Channel I/O -------------------------------------- s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- s2mm_awlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- s2mm_awsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- s2mm_awburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- s2mm_awprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- s2mm_awuser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- s2mm_awready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ----------- -- s2mm__awlock : out std_logic_vector(2 downto 0); -- -- s2mm__awcache : out std_logic_vector(4 downto 0); -- -- s2mm__awqos : out std_logic_vector(3 downto 0); -- -- s2mm__awregion : out std_logic_vector(3 downto 0); -- ----------------------------------------------------------------------- -- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------- s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); -- s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); -- s2mm_wlast : Out std_logic; -- s2mm_wvalid : Out std_logic; -- s2mm_wready : In std_logic; -- --------------------------------------------------------------------------------------- -- S2MM AXI MMap Write response Channel I/O ------------------------------------------ s2mm_bresp : In std_logic_vector(1 downto 0); -- s2mm_bvalid : In std_logic; -- s2mm_bready : Out std_logic; -- --------------------------------------------------------------------------------------- -- S2MM AXI Master Stream Channel I/O ------------------------------------------------ s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); -- s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); -- s2mm_strm_wlast : In std_logic; -- s2mm_strm_wvalid : In std_logic; -- s2mm_strm_wready : Out std_logic; -- --------------------------------------------------------------------------------------- -- Testing Support I/O ----------------------------------------- s2mm_dbg_sel : in std_logic_vector( 3 downto 0); -- s2mm_dbg_data : out std_logic_vector(31 downto 0) -- ---------------------------------------------------------------- ); end entity axi_datamover_s2mm_omit_wrap; architecture implementation of axi_datamover_s2mm_omit_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; begin --(architecture implementation) -- Just tie off output ports s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type s2mm_addr_req_posted <= '0' ; s2mm_wr_xfer_cmplt <= '0' ; s2mm_ld_nxt_len <= '0' ; s2mm_wr_len <= (others => '0'); s2mm_halt_cmplt <= s2mm_halt ; s2mm_err <= '0' ; s2mm_cmd_wready <= '0' ; s2mm_sts_wvalid <= '0' ; s2mm_sts_wdata <= (others => '0'); s2mm_sts_wstrb <= (others => '0'); s2mm_sts_wlast <= '0' ; s2mm_awid <= (others => '0'); s2mm_awaddr <= (others => '0'); s2mm_awlen <= (others => '0'); s2mm_awsize <= (others => '0'); s2mm_awburst <= (others => '0'); s2mm_awprot <= (others => '0'); s2mm_awcache <= (others => '0'); s2mm_awuser <= (others => '0'); s2mm_awvalid <= '0' ; s2mm_wdata <= (others => '0'); s2mm_wstrb <= (others => '0'); s2mm_wlast <= '0' ; s2mm_wvalid <= '0' ; s2mm_bready <= '0' ; s2mm_strm_wready <= '0' ; -- Input ports are ignored end implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/FIFO_image_filter_p_src_cols_V_channel1.vhd

2

4636

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_p_src_cols_V_channel1_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_p_src_cols_V_channel1_shiftReg; architecture rtl of FIFO_image_filter_p_src_cols_V_channel1_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_p_src_cols_V_channel1 is generic ( MEM_STYLE : string := "shiftreg"; DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_p_src_cols_V_channel1 is component FIFO_image_filter_p_src_cols_V_channel1_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_p_src_cols_V_channel1_shiftReg : FIFO_image_filter_p_src_cols_V_channel1_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s06/AXI_STREAM_HLS_S06/HLS/simple_axi_stream_counter/solution1/impl/vhdl/axi_stream_counter.vhd

3

7508

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity axi_stream_counter is port ( ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; counter_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0); counter_TVALID : OUT STD_LOGIC; counter_TREADY : IN STD_LOGIC; ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) ); end; architecture behav of axi_stream_counter is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "axi_stream_counter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.440000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=34,HLS_SYN_LUT=34}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; signal ap_rst_n_inv : STD_LOGIC; signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_bdd_19 : BOOLEAN; signal counterValue : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal counterValue_assign_fu_34_p2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_ioackin_counter_TREADY : STD_LOGIC; signal ap_reg_ioackin_counter_TREADY : STD_LOGIC := '0'; signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_bdd_60 : BOOLEAN; begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_reg_ioackin_counter_TREADY assign process. -- ap_reg_ioackin_counter_TREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ioackin_counter_TREADY <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then if (not(((ap_start = ap_const_logic_0) or (ap_const_logic_0 = ap_sig_ioackin_counter_TREADY)))) then ap_reg_ioackin_counter_TREADY <= ap_const_logic_0; elsif (ap_sig_bdd_60) then ap_reg_ioackin_counter_TREADY <= ap_const_logic_1; end if; end if; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(((ap_start = ap_const_logic_0) or (ap_const_logic_0 = ap_sig_ioackin_counter_TREADY))))) then counterValue <= counterValue_assign_fu_34_p2; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_sig_ioackin_counter_TREADY) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => ap_NS_fsm <= ap_ST_st1_fsm_0; when others => ap_NS_fsm <= "X"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_ioackin_counter_TREADY) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(((ap_start = ap_const_logic_0) or (ap_const_logic_0 = ap_sig_ioackin_counter_TREADY))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_ioackin_counter_TREADY) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(((ap_start = ap_const_logic_0) or (ap_const_logic_0 = ap_sig_ioackin_counter_TREADY))))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_return <= ap_const_lv32_0; -- ap_rst_n_inv assign process. -- ap_rst_n_inv_assign_proc : process(ap_rst_n) begin ap_rst_n_inv <= not(ap_rst_n); end process; -- ap_sig_bdd_19 assign process. -- ap_sig_bdd_19_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_19 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; -- ap_sig_bdd_60 assign process. -- ap_sig_bdd_60_assign_proc : process(ap_start, counter_TREADY) begin ap_sig_bdd_60 <= (not((ap_start = ap_const_logic_0)) and (ap_const_logic_1 = counter_TREADY)); end process; -- ap_sig_cseq_ST_st1_fsm_0 assign process. -- ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_19) begin if (ap_sig_bdd_19) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; -- ap_sig_ioackin_counter_TREADY assign process. -- ap_sig_ioackin_counter_TREADY_assign_proc : process(counter_TREADY, ap_reg_ioackin_counter_TREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_counter_TREADY)) then ap_sig_ioackin_counter_TREADY <= counter_TREADY; else ap_sig_ioackin_counter_TREADY <= ap_const_logic_1; end if; end process; counterValue_assign_fu_34_p2 <= std_logic_vector(unsigned(counterValue) + unsigned(ap_const_lv32_1)); counter_TDATA <= std_logic_vector(unsigned(counterValue) + unsigned(ap_const_lv32_1)); -- counter_TVALID assign process. -- counter_TVALID_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_reg_ioackin_counter_TREADY) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (ap_const_logic_0 = ap_reg_ioackin_counter_TREADY))) then counter_TVALID <= ap_const_logic_1; else counter_TVALID <= ap_const_logic_0; end if; end process; end behav;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_ise/hw/xps_proj/pcores/logicvc_v3_00_a/doc/logicvc_comp.vhd

1

22930

package logicbricks is -- START COMPONENT component logicvc is generic ( -- Version generics C_IP_LICENSE_TYPE : integer := 0; -- IP encryption type: 0 = source, 1 = evaluation, 2 = release, 3 = university evaluation C_IP_MAJOR_REVISION : integer := 0; -- IP major revision: 0 - 31; vXX_yy_z C_IP_MINOR_REVISION : integer := 0; -- IP minor revision: 0 - 31; vxx_YY_z C_IP_PATCH_LEVEL : integer := 0; -- IP patch level: 0 - 25; vxx_yy_Z C_IP_LICENSE_CHECK : integer := 0; -- IP license check: 0 = no, 1 = yes C_IP_TIME_BEFORE_BREAK : integer := 0; -- IP time before break: 0 = infinite, 1 = 1h, 2 = 12h, 3 = 24h C_FAMILY : string := "spartan6"; -- Video memory generics C_VMEM_INTERFACE : integer := 0; -- Use PLB, XMB or AXI to access video memory: 0 - PLB, 1 - XMB, 2 - AXI C_VMEM_BASEADDR : std_logic_vector := x"FFFFFFFF"; C_VMEM_HIGHADDR : std_logic_vector := x"00000000"; C_MEM_BURST : integer := 4; -- Memory burst width; 4, 5 or 6. (4 means burst lasts 16 transfers), Used for XMB and AXI C_MEM_BYTE_SWAP : integer := 0; -- Memory access byte swap: 0 - Do not swap, 1 - Swap C_MEM_LITTLE_ENDIAN : integer := 1; -- Memory access endianness: 0 - Big endian, 1 - Little endian C_INCREASE_FIFO : integer := 1; -- FIFO size multiplication factor: 1=1x, 2=2x, 4=4x, 8=8x -- Master PLB generics C_MPLB_NUM_MASTERS : integer := 8; C_MPLB_AWIDTH : integer := 32; C_MPLB_DWIDTH : integer := 64; C_MPLB_PRIORITY : integer := 3; C_MPLB_SMALLEST_SLAVE : integer := 32; -- XMB generics C_XMB_DATA_BUS_WIDTH : integer := 64; -- XMB Memory interface data bus width -- Master AXI generics C_M_AXI_THREAD_ID_WIDTH : integer := 1; C_M_AXI_DATA_WIDTH : integer := 64; C_M_AXI_ADDR_WIDTH : integer := 32; -- Registers generics C_REGS_INTERFACE : integer := 0; -- Use OPB, PLB or AXI interface for registers: 0 - OPB, 1 - PLB, 2 - AXI C_READABLE_REGS : integer := 1; -- Are logiCVC registers readable?: 0 - no, 1 - yes C_REG_BYTE_SWAP : integer := 0; -- Registers access byte swap: 0 - Do not swap, 1 - Swap -- OPB generics C_REGS_BASEADDR : std_logic_vector := x"FFFFFFFF"; C_REGS_HIGHADDR : std_logic_vector := x"00000000"; C_OPB_AWIDTH : integer := 32; C_OPB_DWIDTH : integer := 32; -- Slave PLB generics C_SPLB_NUM_MASTERS : integer := 8; C_SPLB_MID_WIDTH : integer := 1; C_SPLB_AWIDTH : integer := 32; C_SPLB_DWIDTH : integer := 32; C_SPLB_NATIVE_DWIDTH : integer := 32; -- AXI4-Lite Slave generics C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_DATA_WIDTH : integer := 32; -- Output format C_PIXEL_DATA_WIDTH : integer := 24; -- Output data width: 12, 15, 16, 18 or 24 C_USE_VCLK2 : integer := 1; -- pix_clk rising edge will be in the middle of the DDR RGB data eye or synchronous if not used C_ROW_STRIDE : integer := 1024; -- Row stride in number of pixels C_XCOLOR : integer := 0; C_USE_SIZE_POSITION : integer := 0; -- Use layer size, position and offset functionality: 0 - no, 1 - yes C_DISPLAY_INTERFACE : integer := 0; -- Select output interface type: 0 - parallel only, 1 - ITU656, 2 - LVDS 4bit, 3 - camera link, 4 - LVDS 3bit, 5 - DVI C_DISPLAY_COLOR_SPACE : integer := 0; -- Select output interface color space: 0 - RGB, 1 - YCbCr 4:2:2, 2 - YCbCr 4:4:4 C_LVDS_DATA_WIDTH : integer := 4; -- 3 or 4 C_VCLK_PERIOD : integer := 25000; -- vclk clock period in ps -- Multilayer generics C_NUM_OF_LAYERS : positive := 3; -- Number of logiCVC layers: 1, 2, 3, 4 or 5 C_LAYER_0_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr C_LAYER_1_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr, 2 - Alpha C_LAYER_2_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr C_LAYER_3_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr, 2 - Alpha C_LAYER_4_TYPE : integer := 0; -- Layer 0 type: 0 - RGB, 1 - YCbCr C_LAYER_0_DATA_WIDTH : positive := 16; -- Layer 0 data width: 8, 16, 24 bit C_LAYER_1_DATA_WIDTH : positive := 16; -- Layer 1 data width: 8, 16, 24 bit C_LAYER_2_DATA_WIDTH : positive := 16; -- Layer 2 data width: 8, 16, 24 bit C_LAYER_3_DATA_WIDTH : positive := 16; -- Layer 3 data width: 8, 16, 24 bit C_LAYER_4_DATA_WIDTH : positive := 16; -- Layer 4 data width: 8, 16, 24 bit C_LAYER_0_ALPHA_MODE : integer := 0; -- Layer 0 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24 C_LAYER_1_ALPHA_MODE : integer := 0; -- Layer 1 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24 C_LAYER_2_ALPHA_MODE : integer := 0; -- Layer 2 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24 C_LAYER_3_ALPHA_MODE : integer := 0; -- Layer 3 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24 C_LAYER_4_ALPHA_MODE : integer := 0; -- Layer 4 alpha blending mode: 0 - layer, 1 - pixel, 2 - clut 16, 3 - clut 24 C_USE_BACKGROUND : integer := 0; -- configure last layer as background: 0 - no, 1 - yes C_USE_XTREME_DSP : integer := 2; -- enable or disable use of DSP resources: 0 - no, 1 - yes, 2 - auto C_USE_MULTIPLIER : integer := 2; -- control way in which multipliers in blender are implemented: 0 - lut, 1 - block, 2 - auto C_LAYER_0_OFFSET : natural := 0; -- address offset for layer 0 in 2k steps for 16bpp and 1k steps for 8bpp C_LAYER_1_OFFSET : natural := 2048; -- address offset for layer 1 in 2k steps for 16bpp and 1k steps for 8bpp C_LAYER_2_OFFSET : natural := 4096; -- address offset for layer 2 in 2k steps for 16bpp and 1k steps for 8bpp C_LAYER_3_OFFSET : natural := 6144; -- address offset for layer 3 in 2k steps for 16bpp and 1k steps for 8bpp C_LAYER_4_OFFSET : natural := 8192; -- address offset for layer 4 in 2k steps for 16bpp and 1k steps for 8bpp C_BUFFER_0_OFFSET : natural := 1024; -- address offset for layer 0 double buffer relative to LAYER_0_OFFSET C_BUFFER_1_OFFSET : natural := 1024; -- address offset for layer 1 double buffer relative to LAYER_1_OFFSET C_BUFFER_2_OFFSET : natural := 1024; -- address offset for layer 2 double buffer relative to LAYER_2_OFFSET C_BUFFER_3_OFFSET : natural := 1024; -- address offset for layer 3 double buffer relative to LAYER_3_OFFSET C_BUFFER_4_OFFSET : natural := 1024; -- address offset for layer 4 double buffer relative to LAYER_4_OFFSET -- Extern parallel input generics C_USE_E_PARALLEL_INPUT : integer := 0; -- Syncronize logiCVC to external parallel input and use data as one layer: 0 - no, 1 - yes C_USE_E_VCLK_BUFGMUX : integer := 1; -- Use BUFGMUX for switching video clock to e_vclk, else use vclk C_E_LAYER : integer := 0; -- External parallel input layer: 0, 1, 2, 3, 4 C_E_DATA_WIDTH : integer := 24 -- External parallel input data width: 8, 16, 24 bit ); port( rst : in std_logic; -- Global reset mclk : in std_logic; -- Memory clock vclk : in std_logic; -- Video clock vclk2 : in std_logic; -- Video clock x2 itu_clk_in : in std_logic; -- It has to be 27 MHz and synchronous to vclk lvds_clk : in std_logic; -- lvds clock is 3.5x video clock lvds_clkn : in std_logic; -- Inverted lvds_clk -- Xylon Memory Bus (XMB) mem_req : out std_logic; mem_wr : out std_logic; mem_ack : in std_logic := '0'; mem_addr : out std_logic_vector(31 downto 0); mem_data : out std_logic_vector(C_XMB_DATA_BUS_WIDTH - 1 downto 0); mem_data_be : out std_logic_vector(C_XMB_DATA_BUS_WIDTH / 8 - 1 downto 0); mem_wrack : in std_logic := '0'; mem_burst : out std_logic_vector(C_MEM_BURST - 1 downto 0); mem_data_valid : in std_logic := '0'; mem_data_in : in std_logic_vector(C_XMB_DATA_BUS_WIDTH - 1 downto 0) := (others => '0'); -- PLB -------------- -- Master mplb_rst : in std_logic; plb_maddrack : in std_logic; plb_mrearbitrate : in std_logic; plb_mssize : in std_logic_vector(0 to 1); plb_mbusy : in std_logic; plb_mrderr : in std_logic; plb_mwrerr : in std_logic; plb_mtimeout : in std_logic; plb_mirq : in std_logic; m_request : out std_logic; m_priority : out std_logic_vector(0 to 1); m_buslock : out std_logic; m_rnw : out std_logic; m_be : out std_logic_vector(0 to (C_MPLB_DWIDTH / 8) - 1); m_size : out std_logic_vector(0 to 3); m_type : out std_logic_vector(0 to 2); m_msize : out std_logic_vector(0 to 1); m_tattribute : out std_logic_vector(0 to 15); m_lockerr : out std_logic; m_abort : out std_logic; m_abus : out std_logic_vector(0 to (C_MPLB_AWIDTH - 1)); m_uabus : out std_logic_vector(0 to (C_MPLB_AWIDTH - 1)); plb_mwrdack : in std_logic; plb_mwrbterm : in std_logic; m_wrburst : out std_logic; m_wrdbus : out std_logic_vector(0 to (C_MPLB_DWIDTH - 1)); plb_mrddack : in std_logic; plb_mrdbterm : in std_logic; plb_mrdwdaddr : in std_logic_vector(0 to 3); plb_mrddbus : in std_logic_vector(0 to (C_MPLB_DWIDTH - 1)); m_rdburst : out std_logic; -- AXI -------------- -- Master M_AXI_ARESETN : in std_logic; M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0); M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0); M_AXI_AWLEN : out std_logic_vector(7 downto 0); M_AXI_AWSIZE : out std_logic_vector(2 downto 0); M_AXI_AWBURST : out std_logic_vector(1 downto 0); M_AXI_AWLOCK : out std_logic_vector(1 downto 0); M_AXI_AWCACHE : out std_logic_vector(3 downto 0); M_AXI_AWPROT : out std_logic_vector(2 downto 0); M_AXI_AWQOS : out std_logic_vector(3 downto 0); M_AXI_AWVALID : out std_logic; M_AXI_AWREADY : in std_logic; M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH - 1 downto 0); M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH / 8 - 1 downto 0); M_AXI_WLAST : out std_logic; M_AXI_WVALID : out std_logic; M_AXI_WREADY : in std_logic; M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0); M_AXI_BRESP : in std_logic_vector(1 downto 0); M_AXI_BVALID : in std_logic; M_AXI_BREADY : out std_logic; M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0); M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0); M_AXI_ARLEN : out std_logic_vector(7 downto 0); M_AXI_ARSIZE : out std_logic_vector(2 downto 0); M_AXI_ARBURST : out std_logic_vector(1 downto 0); M_AXI_ARLOCK : out std_logic_vector(1 downto 0); M_AXI_ARCACHE : out std_logic_vector(3 downto 0); M_AXI_ARPROT : out std_logic_vector(2 downto 0); M_AXI_ARQOS : out std_logic_vector(3 downto 0); M_AXI_ARVALID : out std_logic; M_AXI_ARREADY : in std_logic; M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH - 1 downto 0); M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH - 1 downto 0); M_AXI_RRESP : in std_logic_vector(1 downto 0); M_AXI_RLAST : in std_logic; M_AXI_RVALID : in std_logic; M_AXI_RREADY : out std_logic; ---------------------- -- OPB -------------- -- Slave OPB_Clk : in std_logic; OPB_Rst : in std_logic; OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH - 1); OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH / 8 - 1); OPB_RNW : in std_logic; OPB_select : in std_logic; OPB_seqAddr : in std_logic; OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH - 1); Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH - 1); Sl_errAck : out std_logic; Sl_retry : out std_logic; Sl_toutSup : out std_logic; Sl_xferAck : out std_logic; ---------------------- -- PLB -------------- -- Slave SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH - 1); PLB_UABus : in std_logic_vector(0 to C_SPLB_AWIDTH - 1); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH - 1); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH / 8 - 1); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_tattribute : in std_logic_vector(0 to 15); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH - 1); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH - 1); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1); Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1); Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1); Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS - 1); ---------------------- -- AXI4-Lite -------- -- Slave S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH / 8) - 1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; ---------------------- -- Video Outputs -------------- pix_clk_i : in std_logic; -- Pixel clock pix_clk_o : out std_logic; -- Pixel clock pix_clk_t : out std_logic; -- Pixel clock pix_clk_n_i : in std_logic; -- Pixel clock inverted pix_clk_n_o : out std_logic; -- Pixel clock inverted pix_clk_n_t : out std_logic; -- Pixel clock inverted d_pix_i : in std_logic_vector(C_PIXEL_DATA_WIDTH - 1 downto 0); -- Pixel data bus d_pix_o : out std_logic_vector(C_PIXEL_DATA_WIDTH - 1 downto 0); -- Pixel data bus d_pix_t : out std_logic; -- Pixel data bus hsync_i : in std_logic; -- Hsync hsync_o : out std_logic; -- Hsync hsync_t : out std_logic; -- Hsync vsync_i : in std_logic; -- Vsync vsync_o : out std_logic; -- Vsync vsync_t : out std_logic; -- Vsync blank_i : in std_logic; -- Blank blank_o : out std_logic; -- Blank blank_t : out std_logic; -- Blank itu656_clk_o : out std_logic; -- ITU656 clock output itu656_data_o : out std_logic_vector(7 downto 0); -- ITU656 data output lvds_data_out_p : out std_logic_vector(C_LVDS_DATA_WIDTH - 1 downto 0); -- lvds data, positive lvds_data_out_n : out std_logic_vector(C_LVDS_DATA_WIDTH - 1 downto 0); -- lvds data, negative lvds_clk_out_p : out std_logic; -- lvds clk, positive lvds_clk_out_n : out std_logic; -- lvds clk, negative pllvclk_locked : in std_logic; -- PLL_BASE LOCKED (spartan6, LVDS clk gen) dvi_clk_p : out std_logic; -- DVI clock, positive dvi_clk_n : out std_logic; -- DVI clock, negative dvi_data_p : out std_logic_vector(2 downto 0); -- DVI data, positive dvi_data_n : out std_logic_vector(2 downto 0); -- DVI data, negative ---------------------- -- External parallel input -------------- e_vclk : in std_logic; -- External video clock e_vsync : in std_logic; -- External vsync e_hsync : in std_logic; -- External hsync e_blank : in std_logic; -- External blank e_data : in std_logic_vector(C_E_DATA_WIDTH - 1 downto 0); -- External data e_video_present : in std_logic; -- External video present flag ---------------------- -- Other -------------- e_curr_vbuff : in std_logic_vector(C_NUM_OF_LAYERS * 2 - 1 downto 0); -- Current external stream vbuffer e_next_vbuff : out std_logic_vector(C_NUM_OF_LAYERS * 2 - 1 downto 0); -- Next external stream vbuffer to write to e_sw_vbuff : in std_logic_vector(C_NUM_OF_LAYERS - 1 downto 0); -- Switch video buffers from external source e_sw_grant : out std_logic_vector(C_NUM_OF_LAYERS - 1 downto 0); -- Video buffers switch req granted vcdivsel : out std_logic_vector(1 downto 0); -- vclk div select bits vclksel : out std_logic_vector(2 downto 0); -- vclk select bits en_vdd : out std_logic; -- vdd enable en_blight : out std_logic; -- backlight enable v_en : out std_logic; -- Enable display control/data signals en_vee : out std_logic; -- vee enable interrupt : out std_logic -- logiCVC interrupt signal, level sensitive, high active ); end component; end logicbricks;

gpl-3.0

mistryalok/Zedboard

learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_bram_ctrl_1_0/sim/design_1_axi_bram_ctrl_1_0.vhd

1

15629

-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_bram_ctrl_v4_0; USE axi_bram_ctrl_v4_0.axi_bram_ctrl; ENTITY design_1_axi_bram_ctrl_1_0 IS PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC; s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC; s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; bram_rst_a : OUT STD_LOGIC; bram_clk_a : OUT STD_LOGIC; bram_en_a : OUT STD_LOGIC; bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ); END design_1_axi_bram_ctrl_1_0; ARCHITECTURE design_1_axi_bram_ctrl_1_0_arch OF design_1_axi_bram_ctrl_1_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_1_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_bram_ctrl IS GENERIC ( C_BRAM_INST_MODE : STRING; C_MEMORY_DEPTH : INTEGER; C_BRAM_ADDR_WIDTH : INTEGER; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER; C_S_AXI_ID_WIDTH : INTEGER; C_S_AXI_PROTOCOL : STRING; C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER; C_SINGLE_PORT_BRAM : INTEGER; C_FAMILY : STRING; C_S_AXI_CTRL_ADDR_WIDTH : INTEGER; C_S_AXI_CTRL_DATA_WIDTH : INTEGER; C_ECC : INTEGER; C_ECC_TYPE : INTEGER; C_FAULT_INJECT : INTEGER; C_ECC_ONOFF_RESET_VALUE : INTEGER ); PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; ecc_interrupt : OUT STD_LOGIC; ecc_ue : OUT STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC; s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC; s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_ctrl_awvalid : IN STD_LOGIC; s_axi_ctrl_awready : OUT STD_LOGIC; s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_wvalid : IN STD_LOGIC; s_axi_ctrl_wready : OUT STD_LOGIC; s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_ctrl_bvalid : OUT STD_LOGIC; s_axi_ctrl_bready : IN STD_LOGIC; s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_arvalid : IN STD_LOGIC; s_axi_ctrl_arready : OUT STD_LOGIC; s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_ctrl_rvalid : OUT STD_LOGIC; s_axi_ctrl_rready : IN STD_LOGIC; bram_rst_a : OUT STD_LOGIC; bram_clk_a : OUT STD_LOGIC; bram_en_a : OUT STD_LOGIC; bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rst_b : OUT STD_LOGIC; bram_clk_b : OUT STD_LOGIC; bram_en_b : OUT STD_LOGIC; bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT axi_bram_ctrl; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST"; ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; BEGIN U0 : axi_bram_ctrl GENERIC MAP ( C_BRAM_INST_MODE => "EXTERNAL", C_MEMORY_DEPTH => 2048, C_BRAM_ADDR_WIDTH => 11, C_S_AXI_ADDR_WIDTH => 13, C_S_AXI_DATA_WIDTH => 32, C_S_AXI_ID_WIDTH => 12, C_S_AXI_PROTOCOL => "AXI4", C_S_AXI_SUPPORTS_NARROW_BURST => 0, C_SINGLE_PORT_BRAM => 1, C_FAMILY => "zynq", C_S_AXI_CTRL_ADDR_WIDTH => 32, C_S_AXI_CTRL_DATA_WIDTH => 32, C_ECC => 0, C_ECC_TYPE => 0, C_FAULT_INJECT => 0, C_ECC_ONOFF_RESET_VALUE => 0 ) PORT MAP ( s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awid => s_axi_awid, s_axi_awaddr => s_axi_awaddr, s_axi_awlen => s_axi_awlen, s_axi_awsize => s_axi_awsize, s_axi_awburst => s_axi_awburst, s_axi_awlock => s_axi_awlock, s_axi_awcache => s_axi_awcache, s_axi_awprot => s_axi_awprot, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wstrb => s_axi_wstrb, s_axi_wlast => s_axi_wlast, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bid => s_axi_bid, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_arid => s_axi_arid, s_axi_araddr => s_axi_araddr, s_axi_arlen => s_axi_arlen, s_axi_arsize => s_axi_arsize, s_axi_arburst => s_axi_arburst, s_axi_arlock => s_axi_arlock, s_axi_arcache => s_axi_arcache, s_axi_arprot => s_axi_arprot, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rid => s_axi_rid, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rlast => s_axi_rlast, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, s_axi_ctrl_awvalid => '0', s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_wvalid => '0', s_axi_ctrl_bready => '0', s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_arvalid => '0', s_axi_ctrl_rready => '0', bram_rst_a => bram_rst_a, bram_clk_a => bram_clk_a, bram_en_a => bram_en_a, bram_we_a => bram_we_a, bram_addr_a => bram_addr_a, bram_wrdata_a => bram_wrdata_a, bram_rddata_a => bram_rddata_a, bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)) ); END design_1_axi_bram_ctrl_1_0_arch;

gpl-3.0

freecores/usb_fpga_1_11

examples/usb-fpga-1.2/intraffic/fpga/intraffic.vhd

42

1939

library ieee; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity intraffic is port( RESET : in std_logic; CONT : in std_logic; IFCLK : in std_logic; FD : out std_logic_vector(15 downto 0); SLOE : out std_logic; SLRD : out std_logic; SLWR : out std_logic; FIFOADR0 : out std_logic; FIFOADR1 : out std_logic; PKTEND : out std_logic; FLAGB : in std_logic ); end intraffic; architecture RTL of intraffic is ---------------------------- -- test pattern generator -- ---------------------------- -- 30 bit counter signal GEN_CNT : std_logic_vector(29 downto 0); signal INT_CNT : std_logic_vector(6 downto 0); signal FIFO_WORD : std_logic; begin SLOE <= '1'; SLRD <= '1'; FIFOADR0 <= '0'; FIFOADR1 <= '0'; PKTEND <= '1'; -- no data alignment dpIFCLK: process (IFCLK, RESET) begin -- reset if RESET = '1' then GEN_CNT <= ( others => '0' ); INT_CNT <= ( others => '0' ); FIFO_WORD <= '0'; SLWR <= '1'; -- IFCLK elsif IFCLK'event and IFCLK = '1' then if CONT = '1' or FLAGB = '1' then if FIFO_WORD = '0' then FD(14 downto 0) <= GEN_CNT(14 downto 0); else FD(14 downto 0) <= GEN_CNT(29 downto 15); end if; FD(15) <= FIFO_WORD; if FIFO_WORD = '1' then GEN_CNT <= GEN_CNT + '1'; if INT_CNT = conv_std_logic_vector(99,7) then INT_CNT <= ( others => '0' ); else INT_CNT <= INT_CNT + '1'; end if; end if; FIFO_WORD <= not FIFO_WORD; end if; if ( INT_CNT >= conv_std_logic_vector(90,7) ) and ( CONT = '0' ) then SLWR <= '1'; else SLWR <= '0'; end if; end if; end process dpIFCLK; end RTL;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_s2mm_mngr.vhd

3

50534

-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_mngr.vhd -- Description: This entity is the top level entity for the AXI DMA S2MM -- manager. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_s2mm_mngr is generic( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1; -- Depth of DataMover command FIFO C_DM_STATUS_WIDTH : integer range 8 to 32 := 8; -- Width of DataMover status word -- 8 for Determinate BTT Mode -- 32 for Indterminate BTT Mode ----------------------------------------------------------------------- -- Scatter Gather Parameters ----------------------------------------------------------------------- C_INCLUDE_SG : integer range 0 to 1 := 1; -- Include or Exclude the Scatter Gather Engine -- 0 = Exclude SG Engine - Enables Simple DMA Mode -- 1 = Include SG Engine - Enables Scatter Gather Mode C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1; -- Include or Exclude AXI Status and AXI Control Streams -- 0 = Exclude Status and Control Streams -- 1 = Include Status and Control Streams C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0; -- Include or Exclude Scatter Gather Descriptor Queuing -- 0 = Exclude SG Descriptor Queuing -- 1 = Include SG Descriptor Queuing C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Descriptor Buffer Length, Transferred Bytes, and Status Stream -- Rx Length Width. Indicates the least significant valid bits of -- descriptor buffer length, transferred bytes, or Rx Length value -- in the status word coincident with tlast. C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32; -- AXI Master Stream in for descriptor fetch C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33; -- 1 IOC bit + 32 Update Status Bits C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32; -- Slave AXI Status Stream Data Width ----------------------------------------------------------------------- -- Stream to Memory Map (S2MM) Parameters ----------------------------------------------------------------------- C_INCLUDE_S2MM : integer range 0 to 1 := 1; -- Include or exclude S2MM primary data path -- 0 = Exclude S2MM primary data path -- 1 = Include S2MM primary data path C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for S2MM Write Port C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1; C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_MICRO_DMA : integer range 0 to 1 := 0; C_FAMILY : string := "virtex5" -- Target FPGA Device Family ); port ( -- Secondary Clock and Reset m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Primary Clock and Reset -- axi_prmry_aclk : in std_logic ; -- p_reset_n : in std_logic ; -- -- soft_reset : in std_logic ; -- -- MM2S Control and Status -- s2mm_run_stop : in std_logic ; -- s2mm_keyhole : in std_logic ; s2mm_halted : in std_logic ; -- s2mm_ftch_idle : in std_logic ; -- s2mm_updt_idle : in std_logic ; -- s2mm_tailpntr_enble : in std_logic ; -- s2mm_ftch_err_early : in std_logic ; -- s2mm_ftch_stale_desc : in std_logic ; -- s2mm_halt : in std_logic ; -- s2mm_halt_cmplt : in std_logic ; -- s2mm_packet_eof_out : out std_logic ; s2mm_halted_clr : out std_logic ; -- s2mm_halted_set : out std_logic ; -- s2mm_idle_set : out std_logic ; -- s2mm_idle_clr : out std_logic ; -- s2mm_new_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- s2mm_new_curdesc_wren : out std_logic ; -- s2mm_stop : out std_logic ; -- s2mm_desc_flush : out std_logic ; -- s2mm_all_idle : out std_logic ; -- s2mm_error : out std_logic ; -- mm2s_error : in std_logic ; -- s2mm_desc_info_in : in std_logic_vector (13 downto 0) ; -- Simple DMA Mode Signals s2mm_da : in std_logic_vector -- (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- s2mm_length : in std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- s2mm_length_wren : in std_logic ; -- s2mm_smple_done : out std_logic ; -- s2mm_interr_set : out std_logic ; -- s2mm_slverr_set : out std_logic ; -- s2mm_decerr_set : out std_logic ; -- s2mm_bytes_rcvd : out std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- s2mm_bytes_rcvd_wren : out std_logic ; -- -- -- SG S2MM Descriptor Fetch AXI Stream In -- m_axis_s2mm_ftch_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); -- m_axis_s2mm_ftch_tvalid : in std_logic ; -- m_axis_s2mm_ftch_tready : out std_logic ; -- m_axis_s2mm_ftch_tlast : in std_logic ; -- m_axis_s2mm_ftch_tdata_new : in std_logic_vector -- (96 downto 0); -- m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector -- (63 downto 0); -- m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector -- (31 downto 0); -- m_axis_s2mm_ftch_tvalid_new : in std_logic ; -- m_axis_ftch2_desc_available : in std_logic; -- -- -- SG S2MM Descriptor Update AXI Stream Out -- s_axis_s2mm_updtptr_tdata : out std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis_s2mm_updtptr_tvalid : out std_logic ; -- s_axis_s2mm_updtptr_tready : in std_logic ; -- s_axis_s2mm_updtptr_tlast : out std_logic ; -- -- s_axis_s2mm_updtsts_tdata : out std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; -- s_axis_s2mm_updtsts_tvalid : out std_logic ; -- s_axis_s2mm_updtsts_tready : in std_logic ; -- s_axis_s2mm_updtsts_tlast : out std_logic ; -- -- -- User Command Interface Ports (AXI Stream) -- s_axis_s2mm_cmd_tvalid : out std_logic ; -- s_axis_s2mm_cmd_tready : in std_logic ; -- s_axis_s2mm_cmd_tdata : out std_logic_vector -- ((2*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0); -- -- -- User Status Interface Ports (AXI Stream) -- m_axis_s2mm_sts_tvalid : in std_logic ; -- m_axis_s2mm_sts_tready : out std_logic ; -- m_axis_s2mm_sts_tdata : in std_logic_vector -- (C_DM_STATUS_WIDTH - 1 downto 0) ; -- m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8-1) downto 0); -- s2mm_err : in std_logic ; -- updt_error : in std_logic ; -- ftch_error : in std_logic ; -- -- -- Stream to Memory Map Status Stream Interface -- s_axis_s2mm_sts_tdata : in std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- s_axis_s2mm_sts_tkeep : in std_logic_vector -- ((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); -- s_axis_s2mm_sts_tvalid : in std_logic ; -- s_axis_s2mm_sts_tready : out std_logic ; -- s_axis_s2mm_sts_tlast : in std_logic -- ); end axi_dma_s2mm_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; attribute mark_debug : string; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Primary DataMover Command signals signal s2mm_cmnd_wr : std_logic := '0'; signal s2mm_cmnd_data : std_logic_vector ((2*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0'); signal s2mm_cmnd_pending : std_logic := '0'; attribute mark_debug of s2mm_cmnd_wr : signal is "true"; attribute mark_debug of s2mm_cmnd_data : signal is "true"; -- Primary DataMover Status signals signal s2mm_done : std_logic := '0'; signal s2mm_stop_i : std_logic := '0'; signal s2mm_interr : std_logic := '0'; signal s2mm_slverr : std_logic := '0'; signal s2mm_decerr : std_logic := '0'; attribute mark_debug of s2mm_interr : signal is "true"; attribute mark_debug of s2mm_slverr : signal is "true"; attribute mark_debug of s2mm_decerr : signal is "true"; signal s2mm_tag : std_logic_vector(3 downto 0) := (others => '0'); signal s2mm_brcvd : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal dma_s2mm_error : std_logic := '0'; signal soft_reset_d1 : std_logic := '0'; signal soft_reset_d2 : std_logic := '0'; signal soft_reset_re : std_logic := '0'; signal s2mm_error_i : std_logic := '0'; signal sts_strm_stop : std_logic := '0'; signal s2mm_halted_set_i : std_logic := '0'; signal s2mm_sts_received_clr : std_logic := '0'; signal s2mm_sts_received : std_logic := '0'; signal s2mm_cmnd_idle : std_logic := '0'; signal s2mm_sts_idle : std_logic := '0'; signal s2mm_eof_set : std_logic := '0'; signal s2mm_packet_eof : std_logic := '0'; -- Scatter Gather Interface signals signal desc_fetch_req : std_logic := '0'; signal desc_fetch_done : std_logic := '0'; signal desc_update_req : std_logic := '0'; signal desc_update_done : std_logic := '0'; signal desc_available : std_logic := '0'; signal s2mm_desc_baddress : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_info : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_cmplt : std_logic := '0'; signal s2mm_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); -- S2MM Status Stream Signals signal s2mm_rxlength_valid : std_logic := '0'; signal s2mm_rxlength_clr : std_logic := '0'; signal s2mm_rxlength : std_logic_vector(C_SG_LENGTH_WIDTH - 1 downto 0) := (others => '0'); signal stsstrm_fifo_rden : std_logic := '0'; signal stsstrm_fifo_empty : std_logic := '0'; signal stsstrm_fifo_dout : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0'); signal s2mm_desc_flush_i : std_logic := '0'; signal updt_pending : std_logic := '0'; signal s2mm_cmnd_wr_1 : std_logic := '0'; signal s2mm_eof_micro, s2mm_sof_micro : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Include S2MM (Received) Channel ------------------------------------------------------------------------------- GEN_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 1 generate begin -- pass out to register module s2mm_halted_set <= s2mm_halted_set_i; ------------------------------------------------------------------------------- -- Graceful shut down logic ------------------------------------------------------------------------------- -- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error -- or SG Fetch error, or Stale Descriptor Error s2mm_error_i <= dma_s2mm_error -- Primary data mover reports error or updt_error -- SG Update engine reports error or ftch_error -- SG Fetch engine reports error or s2mm_ftch_err_early -- SG Fetch engine reports early error on S2MM or s2mm_ftch_stale_desc; -- SG Fetch stale descriptor error -- pass out to shut down mm2s s2mm_error <= s2mm_error_i; -- Clear run/stop and stop state machines due to errors or soft reset -- Error based on datamover error report or sg update error or sg fetch error -- SG update error and fetch error included because need to shut down, no way -- to update descriptors on sg update error and on fetch error descriptor -- data is corrupt therefor do not want to issue the xfer command to primary datamover --CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore -- need to stop all processes regardless of the source of the error. -- s2mm_stop_i <= s2mm_error -- Error -- or soft_reset; -- Soft Reset issued s2mm_stop_i <= s2mm_error_i -- Error on s2mm or mm2s_error -- Error on mm2s or soft_reset; -- Soft Reset issued -- Register signals out REG_OUT : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_stop <= '0'; s2mm_desc_flush_i <= '0'; else s2mm_stop <= s2mm_stop_i; -- Flush any fetch descriptors if error or if run stop cleared s2mm_desc_flush_i <= s2mm_stop_i or not s2mm_run_stop; end if; end if; end process REG_OUT; -- Generate DMA Controller For Scatter Gather Mode GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate begin -- Not used in Scatter Gather mode s2mm_smple_done <= '0'; s2mm_interr_set <= '0'; s2mm_slverr_set <= '0'; s2mm_decerr_set <= '0'; s2mm_bytes_rcvd <= (others => '0'); s2mm_bytes_rcvd_wren <= '0'; -- Flush descriptors s2mm_desc_flush <= s2mm_desc_flush_i; OLD_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate begin s2mm_cmnd_wr <= s2mm_cmnd_wr_1; end generate OLD_CMD_WR; NEW_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate begin s2mm_cmnd_wr <= m_axis_s2mm_ftch_tvalid_new; end generate NEW_CMD_WR; --------------------------------------------------------------------------- -- S2MM Primary DMA Controller State Machine --------------------------------------------------------------------------- I_S2MM_SM : entity axi_dma_v7_1.axi_dma_s2mm_sm generic map( C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH , C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE , C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM , C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH , C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL , C_MICRO_DMA => C_MICRO_DMA , C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , s2mm_stop => s2mm_stop_i , -- Channel 1 Control and Status s2mm_run_stop => s2mm_run_stop , s2mm_keyhole => s2mm_keyhole , s2mm_ftch_idle => s2mm_ftch_idle , s2mm_desc_flush => s2mm_desc_flush_i , s2mm_cmnd_idle => s2mm_cmnd_idle , s2mm_sts_idle => s2mm_sts_idle , s2mm_eof_set => s2mm_eof_set , s2mm_eof_micro => s2mm_eof_micro, s2mm_sof_micro => s2mm_sof_micro, -- S2MM Status Stream RX Length s2mm_rxlength_valid => s2mm_rxlength_valid , s2mm_rxlength_clr => s2mm_rxlength_clr , s2mm_rxlength => s2mm_rxlength , -- S2MM Descriptor Fetch Request (from s2mm_sm) desc_fetch_req => desc_fetch_req , desc_fetch_done => desc_fetch_done , desc_update_done => desc_update_done , updt_pending => updt_pending , desc_available => desc_available , -- DataMover Command s2mm_cmnd_wr => s2mm_cmnd_wr_1 , s2mm_cmnd_data => s2mm_cmnd_data , s2mm_cmnd_pending => s2mm_cmnd_pending , -- Descriptor Fields s2mm_desc_baddress => s2mm_desc_baddress , s2mm_desc_info => s2mm_desc_info , s2mm_desc_blength => s2mm_desc_blength, s2mm_desc_blength_v => s2mm_desc_blength_v, s2mm_desc_blength_s => s2mm_desc_blength_s ); --------------------------------------------------------------------------- -- S2MM Scatter Gather State Machine --------------------------------------------------------------------------- I_S2MM_SG_IF : entity axi_dma_v7_1.axi_dma_s2mm_sg_if generic map( ------------------------------------------------------------------- -- Scatter Gather Parameters ------------------------------------------------------------------- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM , C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE , C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH , C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH , C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH , C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH , C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH , C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS , C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL , C_MICRO_DMA => C_MICRO_DMA , C_FAMILY => C_FAMILY ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , s2mm_desc_info_in => s2mm_desc_info_in , -- SG S2MM Descriptor Fetch AXI Stream In m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata , m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid , m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready , m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast , m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new , m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new , m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt , m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new , m_axis_ftch2_desc_available => m_axis_ftch2_desc_available , -- SG S2MM Descriptor Update AXI Stream Out s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata , s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid , s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready , s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast , s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata , s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid , s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready , s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast , -- S2MM Descriptor Fetch Request (from s2mm_sm) desc_available => desc_available , desc_fetch_req => desc_fetch_req , desc_fetch_done => desc_fetch_done , updt_pending => updt_pending , -- S2MM Status Stream Interface stsstrm_fifo_rden => stsstrm_fifo_rden , stsstrm_fifo_empty => stsstrm_fifo_empty , stsstrm_fifo_dout => stsstrm_fifo_dout , -- Update command write interface from s2mm sm s2mm_cmnd_wr => s2mm_cmnd_wr , s2mm_cmnd_data => s2mm_cmnd_data ( ((1+C_ENABLE_MULTI_CHANNEL)* C_M_AXI_S2MM_ADDR_WIDTH+ CMD_BASE_WIDTH)-1 downto 0) , -- S2MM Descriptor Update Request (from s2mm_sm) desc_update_done => desc_update_done , s2mm_sts_received_clr => s2mm_sts_received_clr , s2mm_sts_received => s2mm_sts_received , s2mm_desc_cmplt => s2mm_desc_cmplt , s2mm_done => s2mm_done , s2mm_interr => s2mm_interr , s2mm_slverr => s2mm_slverr , s2mm_decerr => s2mm_decerr , s2mm_tag => s2mm_tag , s2mm_brcvd => s2mm_brcvd , s2mm_eof_set => s2mm_eof_set , s2mm_packet_eof => s2mm_packet_eof , s2mm_halt => s2mm_halt , s2mm_eof_micro => s2mm_eof_micro, s2mm_sof_micro => s2mm_sof_micro, -- S2MM Descriptor Field Output s2mm_new_curdesc => s2mm_new_curdesc , s2mm_new_curdesc_wren => s2mm_new_curdesc_wren , s2mm_desc_baddress => s2mm_desc_baddress , s2mm_desc_blength => s2mm_desc_blength , s2mm_desc_blength_v => s2mm_desc_blength_v , s2mm_desc_blength_s => s2mm_desc_blength_s , s2mm_desc_info => s2mm_desc_info , s2mm_desc_app0 => s2mm_desc_app0 , s2mm_desc_app1 => s2mm_desc_app1 , s2mm_desc_app2 => s2mm_desc_app2 , s2mm_desc_app3 => s2mm_desc_app3 , s2mm_desc_app4 => s2mm_desc_app4 ); end generate GEN_SCATTER_GATHER_MODE; s2mm_packet_eof_out <= s2mm_packet_eof; -- Generate DMA Controller for Simple DMA Mode GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate begin -- Scatter Gather signals not used in Simple DMA Mode s2mm_desc_flush <= '0'; m_axis_s2mm_ftch_tready <= '0'; s_axis_s2mm_updtptr_tdata <= (others => '0'); s_axis_s2mm_updtptr_tvalid <= '0'; s_axis_s2mm_updtptr_tlast <= '0'; s_axis_s2mm_updtsts_tdata <= (others => '0'); s_axis_s2mm_updtsts_tvalid <= '0'; s_axis_s2mm_updtsts_tlast <= '0'; desc_fetch_req <= '0'; desc_available <= '0'; desc_fetch_done <= '0'; desc_update_done <= '0'; s2mm_rxlength_clr <= '0'; stsstrm_fifo_rden <= '0'; s2mm_new_curdesc <= (others => '0'); s2mm_new_curdesc_wren <= '0'; s2mm_desc_baddress <= (others => '0'); s2mm_desc_info <= (others => '0'); s2mm_desc_blength <= (others => '0'); s2mm_desc_blength_v <= (others => '0'); s2mm_desc_blength_s <= (others => '0'); s2mm_desc_cmplt <= '0'; s2mm_desc_app0 <= (others => '0'); s2mm_desc_app1 <= (others => '0'); s2mm_desc_app2 <= (others => '0'); s2mm_desc_app3 <= (others => '0'); s2mm_desc_app4 <= (others => '0'); -- Simple DMA State Machine I_S2MM_SMPL_SM : entity axi_dma_v7_1.axi_dma_smple_sm generic map( C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_MICRO_DMA => C_MICRO_DMA , C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Channel 1 Control and Status run_stop => s2mm_run_stop , keyhole => s2mm_keyhole , stop => s2mm_stop_i , cmnd_idle => s2mm_cmnd_idle , sts_idle => s2mm_sts_idle , -- DataMover Status sts_received => s2mm_sts_received , sts_received_clr => s2mm_sts_received_clr , -- DataMover Command cmnd_wr => s2mm_cmnd_wr , cmnd_data => s2mm_cmnd_data , cmnd_pending => s2mm_cmnd_pending , -- Trasnfer Qualifiers xfer_length_wren => s2mm_length_wren , xfer_address => s2mm_da , xfer_length => s2mm_length ); -- Pass Done/Error Status out to DMASR s2mm_interr_set <= s2mm_interr; s2mm_slverr_set <= s2mm_slverr; s2mm_decerr_set <= s2mm_decerr; s2mm_bytes_rcvd <= s2mm_brcvd; s2mm_bytes_rcvd_wren <= s2mm_done; -- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR. -- Receive clear when not shutting down s2mm_smple_done <= s2mm_sts_received_clr when s2mm_stop_i = '0' -- Else halt set prior to halted being set else s2mm_halted_set_i when s2mm_halted = '0' else '0'; end generate GEN_SIMPLE_DMA_MODE; ------------------------------------------------------------------------------- -- S2MM DataMover Command / Status Interface ------------------------------------------------------------------------------- I_S2MM_CMDSTS : entity axi_dma_v7_1.axi_dma_s2mm_cmdsts_if generic map( C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_DM_STATUS_WIDTH => C_DM_STATUS_WIDTH , C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM , C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH , C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH , C_INCLUDE_SG => C_INCLUDE_SG , C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL , C_MICRO_DMA => C_MICRO_DMA , C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Update command write interface from s2mm sm s2mm_cmnd_wr => s2mm_cmnd_wr , s2mm_cmnd_data => s2mm_cmnd_data , s2mm_cmnd_pending => s2mm_cmnd_pending , s2mm_packet_eof => s2mm_packet_eof , -- EOF Detected s2mm_sts_received_clr => s2mm_sts_received_clr , s2mm_sts_received => s2mm_sts_received , s2mm_tailpntr_enble => s2mm_tailpntr_enble , s2mm_desc_cmplt => s2mm_desc_cmplt , -- User Command Interface Ports (AXI Stream) s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid , s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready , s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata , -- User Status Interface Ports (AXI Stream) m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid , m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready , m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata , m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep , -- S2MM Primary DataMover Status s2mm_brcvd => s2mm_brcvd , s2mm_err => s2mm_err , s2mm_done => s2mm_done , s2mm_error => dma_s2mm_error , s2mm_interr => s2mm_interr , s2mm_slverr => s2mm_slverr , s2mm_decerr => s2mm_decerr , s2mm_tag => s2mm_tag ); --------------------------------------------------------------------------- -- Halt / Idle Status Manager --------------------------------------------------------------------------- I_S2MM_STS_MNGR : entity axi_dma_v7_1.axi_dma_s2mm_sts_mngr generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- dma control and sg engine status signals s2mm_run_stop => s2mm_run_stop , s2mm_ftch_idle => s2mm_ftch_idle , s2mm_updt_idle => s2mm_updt_idle , s2mm_cmnd_idle => s2mm_cmnd_idle , s2mm_sts_idle => s2mm_sts_idle , -- stop and halt control/status s2mm_stop => s2mm_stop_i , s2mm_halt_cmplt => s2mm_halt_cmplt , -- system state and control s2mm_all_idle => s2mm_all_idle , s2mm_halted_clr => s2mm_halted_clr , s2mm_halted_set => s2mm_halted_set_i , s2mm_idle_set => s2mm_idle_set , s2mm_idle_clr => s2mm_idle_clr ); -- S2MM Status Stream Included GEN_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate begin -- Register soft reset to create rising edge pulse to use for shut down. -- soft_reset from DMACR does not clear until after all reset processes -- are done. This causes stop to assert too long causing issue with -- status stream skid buffer. REG_SFT_RST : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then soft_reset_d1 <= '0'; soft_reset_d2 <= '0'; else soft_reset_d1 <= soft_reset; soft_reset_d2 <= soft_reset_d1; end if; end if; end process REG_SFT_RST; -- Rising edge soft reset pulse soft_reset_re <= soft_reset_d1 and not soft_reset_d2; -- Status Stream module stop requires rising edge of soft reset to -- shut down due to DMACR.SoftReset does not deassert on internal hard reset -- It clears after therefore do not want to issue another stop to sts strm -- skid buffer. sts_strm_stop <= s2mm_error_i -- Error or soft_reset_re; -- Soft Reset issued I_S2MM_STS_STREAM : entity axi_dma_v7_1.axi_dma_s2mm_sts_strm generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH , C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH , C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH , C_FAMILY => C_FAMILY ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , axi_prmry_aclk => axi_prmry_aclk , p_reset_n => p_reset_n , s2mm_stop => sts_strm_stop , s2mm_rxlength_valid => s2mm_rxlength_valid , s2mm_rxlength_clr => s2mm_rxlength_clr , s2mm_rxlength => s2mm_rxlength , stsstrm_fifo_rden => stsstrm_fifo_rden , stsstrm_fifo_empty => stsstrm_fifo_empty , stsstrm_fifo_dout => stsstrm_fifo_dout , -- Stream to Memory Map Status Stream Interface , s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata , s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep , s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid , s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready , s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast ); end generate GEN_STS_STREAM; -- S2MM Status Stream Not Included GEN_NO_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate begin s2mm_rxlength_valid <= '0'; s2mm_rxlength <= (others => '0'); stsstrm_fifo_empty <= '1'; stsstrm_fifo_dout <= (others => '0'); s_axis_s2mm_sts_tready <= '0'; end generate GEN_NO_STS_STREAM; end generate GEN_S2MM_DMA_CONTROL; ------------------------------------------------------------------------------- -- Do Not Include S2MM Channel ------------------------------------------------------------------------------- GEN_NO_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 0 generate begin m_axis_s2mm_ftch_tready <= '0'; s_axis_s2mm_updtptr_tdata <= (others =>'0'); s_axis_s2mm_updtptr_tvalid <= '0'; s_axis_s2mm_updtptr_tlast <= '0'; s_axis_s2mm_updtsts_tdata <= (others =>'0'); s_axis_s2mm_updtsts_tvalid <= '0'; s_axis_s2mm_updtsts_tlast <= '0'; s2mm_new_curdesc <= (others =>'0'); s2mm_new_curdesc_wren <= '0'; s_axis_s2mm_cmd_tvalid <= '0'; s_axis_s2mm_cmd_tdata <= (others =>'0'); m_axis_s2mm_sts_tready <= '0'; s2mm_halted_clr <= '0'; s2mm_halted_set <= '0'; s2mm_idle_set <= '0'; s2mm_idle_clr <= '0'; s_axis_s2mm_sts_tready <= '0'; s2mm_stop <= '0'; s2mm_desc_flush <= '0'; s2mm_all_idle <= '1'; s2mm_error <= '0'; -- CR#570587 s2mm_packet_eof_out <= '0'; s2mm_smple_done <= '0'; s2mm_interr_set <= '0'; s2mm_slverr_set <= '0'; s2mm_decerr_set <= '0'; s2mm_bytes_rcvd <= (others => '0'); s2mm_bytes_rcvd_wren <= '0'; end generate GEN_NO_S2MM_DMA_CONTROL; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/full_axi.vhd

7

43438

------------------------------------------------------------------------------- -- full_axi.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: full_axi.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller when configured in a full AXI4 mode. -- The rd_chnl and wr_chnl modules are instantiated. -- The ECC AXI-Lite register module is instantiated, if enabled. -- When single port BRAM mode is selected, the arbitration logic -- is instantiated (and connected to each wr_chnl & rd_chnl). -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen_hsiao.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen_hsiao.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/15/2011 v1.03a -- ~~~~~~ -- Initial integration of Hsiao ECC algorithm. -- Add C_ECC_TYPE top level parameter and mappings on instantiated modules. -- ^^^^^^ -- JLJ 2/18/2011 v1.03a -- ~~~~~~ -- Update WE & BRAM data sizes based on 128-bit ECC configuration. -- Plus XST clean-up. -- ^^^^^^ -- JLJ 3/31/2011 v1.03a -- ~~~~~~ -- Add coverage tags. -- ^^^^^^ -- JLJ 4/11/2011 v1.03a -- ~~~~~~ -- Add signal, AW2Arb_BVALID_Cnt, between wr_chnl and sng_port_arb modules. -- ^^^^^^ -- JLJ 4/20/2011 v1.03a -- ~~~~~~ -- Add default values for Arb2AW_Active & Arb2AR_Active when dual port mode. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove usage of C_FAMILY. -- ^^^^^^ -- -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_bram_ctrl_funcs.all; use work.lite_ecc_reg; use work.sng_port_arb; use work.wr_chnl; use work.rd_chnl; ------------------------------------------------------------------------------ entity full_axi is generic ( -- AXI Parameters C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH : INTEGER := 4; -- AXI ID vector width C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1; -- Support for narrow burst operations C_SINGLE_PORT_BRAM : INTEGER := 0; -- Enable single port usage of BRAM -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_ECC_TYPE : integer := 0; -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Interface Signals -- AXI Clock and Reset S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; ECC_Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- AXI Write Address Channel Signals (AW) S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWLEN : in std_logic_vector(7 downto 0); S_AXI_AWSIZE : in std_logic_vector(2 downto 0); S_AXI_AWBURST : in std_logic_vector(1 downto 0); S_AXI_AWLOCK : in std_logic; S_AXI_AWCACHE : in std_logic_vector(3 downto 0); S_AXI_AWPROT : in std_logic_vector(2 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; -- AXI Write Data Channel Signals (W) S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0); S_AXI_WLAST : in std_logic; S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; -- AXI Write Data Response Channel Signals (B) S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; -- AXI Read Address Channel Signals (AR) S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARLEN : in std_logic_vector(7 downto 0); S_AXI_ARSIZE : in std_logic_vector(2 downto 0); S_AXI_ARBURST : in std_logic_vector(1 downto 0); S_AXI_ARLOCK : in std_logic; S_AXI_ARCACHE : in std_logic_vector(3 downto 0); S_AXI_ARPROT : in std_logic_vector(2 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; -- AXI Read Data Channel Signals (R) S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RLAST : out std_logic; S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- AXI-Lite ECC Register Interface Signals -- AXI-Lite Clock and Reset -- TBD -- S_AXI_CTRL_ACLK : in std_logic; -- S_AXI_CTRL_ARESETN : in std_logic; -- AXI-Lite Write Address Channel Signals (AW) S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic; -- BRAM Interface Signals (Port A) BRAM_En_A : out std_logic; BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); -- BRAM Interface Signals (Port B) BRAM_En_B : out std_logic; BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) ); end entity full_axi; ------------------------------------------------------------------------------- architecture implementation of full_axi is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH); -- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width -- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00" -- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000" -- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000" -- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000" constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- -- Internal AXI Signals signal S_AXI_AWREADY_i : std_logic := '0'; signal S_AXI_ARREADY_i : std_logic := '0'; -- Internal BRAM Signals signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal BRAM_En_A_i : std_logic := '0'; signal BRAM_En_B_i : std_logic := '0'; signal BRAM_WE_A_i : std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal BRAM_RdData_i : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); -- Internal ECC Signals signal Enable_ECC : std_logic := '0'; signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers signal Sl_CE : std_logic := '0'; -- Correctable Error Flag signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag signal Wr_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers --signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers --signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register signal Wr_Sl_CE : std_logic := '0'; -- Correctable Error Flag signal Wr_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag signal Rd_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers signal Rd_Sl_CE : std_logic := '0'; -- Correctable Error Flag signal Rd_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal FaultInjectECC : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width signal FaultInjectECC_i : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width signal Active_Wr : std_logic := '0'; signal BRAM_Addr_En : std_logic := '0'; signal Wr_BRAM_Addr_En : std_logic := '0'; signal Rd_BRAM_Addr_En : std_logic := '0'; -- Internal Arbitration Signals signal Arb2AW_Active : std_logic := '0'; signal AW2Arb_Busy : std_logic := '0'; signal AW2Arb_Active_Clr : std_logic := '0'; signal AW2Arb_BVALID_Cnt : std_logic_vector (2 downto 0) := (others => '0'); signal Arb2AR_Active : std_logic := '0'; signal AR2Arb_Active_Clr : std_logic := '0'; signal WrChnl_BRAM_Addr_Rst : std_logic := '0'; signal WrChnl_BRAM_Addr_Ld_En : std_logic := '0'; signal WrChnl_BRAM_Addr_Inc : std_logic := '0'; signal WrChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal RdChnl_BRAM_Addr_Ld_En : std_logic := '0'; signal RdChnl_BRAM_Addr_Inc : std_logic := '0'; signal RdChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- *** BRAM Output Signals *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: ADDR_SNG_PORT -- Purpose: OR the BRAM_Addr outputs from each wr_chnl & rd_chnl -- Only one write or read will be active at a time. -- Ensure that ecah channel address is driven to '0' when not in use. --------------------------------------------------------------------------- ADDR_SNG_PORT: if C_SINGLE_PORT_BRAM = 1 generate signal sng_bram_addr_rst : std_logic := '0'; signal sng_bram_addr_ld_en : std_logic := '0'; signal sng_bram_addr_ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal sng_bram_addr_inc : std_logic := '0'; begin -- BRAM_Addr_A <= BRAM_Addr_A_i or BRAM_Addr_B_i; -- BRAM_Addr_A <= BRAM_Addr_A_i when (Arb2AW_Active = '1') else BRAM_Addr_B_i; -- BRAM_Addr_A <= BRAM_Addr_A_i when (Active_Wr = '1') else BRAM_Addr_B_i; -- Insert mux on address counter control signals sng_bram_addr_rst <= WrChnl_BRAM_Addr_Rst; sng_bram_addr_ld_en <= WrChnl_BRAM_Addr_Ld_En or RdChnl_BRAM_Addr_Ld_En; sng_bram_addr_ld <= RdChnl_BRAM_Addr_Ld when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Ld; sng_bram_addr_inc <= RdChnl_BRAM_Addr_Inc when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Inc; I_ADDR_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (sng_bram_addr_rst = '1') then bram_addr_int <= (others => '0'); elsif (sng_bram_addr_ld_en = '1') then bram_addr_int <= sng_bram_addr_ld; elsif (sng_bram_addr_inc = '1') then bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12) <= bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12); bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <= std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1); end if; end if; end process I_ADDR_CNT; BRAM_Addr_B <= (others => '0'); BRAM_En_A <= BRAM_En_A_i or BRAM_En_B_i; -- BRAM_En_A <= BRAM_En_A_i when (Arb2AW_Active = '1') else BRAM_En_B_i; BRAM_En_B <= '0'; BRAM_RdData_i <= BRAM_RdData_A; -- Assign read data port A BRAM_WE_A <= BRAM_WE_A_i when (Arb2AW_Active = '1') else (others => '0'); -- v1.03a -- Early register on WrData and WSTRB in wr_chnl. (Previous value was always cleared). --------------------------------------------------------------------------- -- Generate: GEN_L_BRAM_ADDR -- Purpose: Generate zeros on lower order address bits adjustable -- based on BRAM data width. --------------------------------------------------------------------------- GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin BRAM_Addr_A (i) <= '0'; end generate GEN_L_BRAM_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_ADDR -- Purpose: Assign BRAM address output from address counter. --------------------------------------------------------------------------- GEN_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin BRAM_Addr_A (i) <= bram_addr_int (i); end generate GEN_BRAM_ADDR; end generate ADDR_SNG_PORT; --------------------------------------------------------------------------- -- Generate: ADDR_DUAL_PORT -- Purpose: Assign each BRAM address when in a dual port controller -- configuration. --------------------------------------------------------------------------- ADDR_DUAL_PORT: if C_SINGLE_PORT_BRAM = 0 generate begin BRAM_Addr_A <= BRAM_Addr_A_i; BRAM_Addr_B <= BRAM_Addr_B_i; BRAM_En_A <= BRAM_En_A_i; BRAM_En_B <= BRAM_En_B_i; BRAM_WE_A <= BRAM_WE_A_i; BRAM_RdData_i <= BRAM_RdData_B; -- Assign read data port B end generate ADDR_DUAL_PORT; BRAM_WrData_B <= (others => '0'); BRAM_WE_B <= (others => '0'); --------------------------------------------------------------------------- -- *** AXI-Lite ECC Register Output Signals *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NO_REGS -- Purpose: Generate default values if ECC registers are disabled (or when -- ECC is disabled). -- Include both AXI-Lite default signal values & internal -- core signal values. --------------------------------------------------------------------------- GEN_NO_REGS: if (C_ECC = 0) generate begin S_AXI_CTRL_AWREADY <= '0'; S_AXI_CTRL_WREADY <= '0'; S_AXI_CTRL_BRESP <= (others => '0'); S_AXI_CTRL_BVALID <= '0'; S_AXI_CTRL_ARREADY <= '0'; S_AXI_CTRL_RDATA <= (others => '0'); S_AXI_CTRL_RRESP <= (others => '0'); S_AXI_CTRL_RVALID <= '0'; -- No fault injection FaultInjectData <= (others => '0'); FaultInjectECC <= (others => '0'); -- Interrupt only enabled when ECC status/interrupt registers enabled ECC_Interrupt <= '0'; ECC_UE <= '0'; Enable_ECC <= '0'; end generate GEN_NO_REGS; --------------------------------------------------------------------------- -- Generate: GEN_REGS -- Purpose: Generate ECC register module when ECC is enabled and -- ECC registers are enabled. --------------------------------------------------------------------------- -- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate -- For future implementation. GEN_REGS: if (C_ECC = 1) generate begin --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- Description: This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. --------------------------------------------------------------------------- I_LITE_ECC_REG : entity work.lite_ecc_reg generic map ( C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width C_FAULT_INJECT => C_FAULT_INJECT , C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS , C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS , C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS , C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER , C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE , C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH ) port map ( S_AXI_AClk => S_AXI_AClk , -- AXI clock S_AXI_AResetn => S_AXI_AResetn , -- TBD -- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock -- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn , Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , -- Add AXI-Lite ECC Register Ports AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID , AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY , AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR , AXI_CTRL_WDATA => S_AXI_CTRL_WDATA , AXI_CTRL_WVALID => S_AXI_CTRL_WVALID , AXI_CTRL_WREADY => S_AXI_CTRL_WREADY , AXI_CTRL_BRESP => S_AXI_CTRL_BRESP , AXI_CTRL_BVALID => S_AXI_CTRL_BVALID , AXI_CTRL_BREADY => S_AXI_CTRL_BREADY , AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR , AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID , AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY , AXI_CTRL_RDATA => S_AXI_CTRL_RDATA , AXI_CTRL_RRESP => S_AXI_CTRL_RRESP , AXI_CTRL_RVALID => S_AXI_CTRL_RVALID , AXI_CTRL_RREADY => S_AXI_CTRL_RREADY , Enable_ECC => Enable_ECC , FaultInjectClr => FaultInjectClr , CE_Failing_We => CE_Failing_We , CE_CounterReg_Inc => CE_Failing_We , Sl_CE => Sl_CE , Sl_UE => Sl_UE , BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a BRAM_Addr_En => BRAM_Addr_En , Active_Wr => Active_Wr , -- BRAM_RdData_A => BRAM_RdData_A (C_S_AXI_DATA_WIDTH-1 downto 0) , -- BRAM_RdData_B => BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0) , FaultInjectData => FaultInjectData , FaultInjectECC => FaultInjectECC_i ); BRAM_Addr_En <= Wr_BRAM_Addr_En or Rd_BRAM_Addr_En; -- v1.03a -- Add coverage tags for Wr_CE_Failing_We. -- No testing on forcing errors with RMW and AXI write transfers. --coverage off CE_Failing_We <= Wr_CE_Failing_We or Rd_CE_Failing_We; Sl_CE <= Wr_Sl_CE or Rd_Sl_CE; Sl_UE <= Wr_Sl_UE or Rd_Sl_UE; --coverage on ------------------------------------------------------------------- -- Generate: GEN_32 -- Purpose: Add MSB '0' on ECC vector as only 7-bits wide in 32-bit. ------------------------------------------------------------------- GEN_32: if C_S_AXI_DATA_WIDTH = 32 generate begin FaultInjectECC <= '0' & FaultInjectECC_i; end generate GEN_32; ------------------------------------------------------------------- -- Generate: GEN_NON_32 -- Purpose: Data widths match at 8-bits for ECC on 64-bit data. -- And 9-bits for 128-bit data. ------------------------------------------------------------------- GEN_NON_32: if C_S_AXI_DATA_WIDTH /= 32 generate begin FaultInjectECC <= FaultInjectECC_i; end generate GEN_NON_32; end generate GEN_REGS; --------------------------------------------------------------------------- -- Generate: GEN_ARB -- Purpose: Generate arbitration module when AXI4 is configured in -- single port mode. --------------------------------------------------------------------------- GEN_ARB: if (C_SINGLE_PORT_BRAM = 1) generate begin --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- Description: This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. --------------------------------------------------------------------------- I_SNG_PORT : entity work.sng_port_arb generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ) port map ( S_AXI_AClk => S_AXI_AClk , -- AXI clock S_AXI_AResetn => S_AXI_AResetn , AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0), AXI_AWVALID => S_AXI_AWVALID , AXI_AWREADY => S_AXI_AWREADY , AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0), AXI_ARVALID => S_AXI_ARVALID , AXI_ARREADY => S_AXI_ARREADY , Arb2AW_Active => Arb2AW_Active , AW2Arb_Busy => AW2Arb_Busy , AW2Arb_Active_Clr => AW2Arb_Active_Clr , AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt , Arb2AR_Active => Arb2AR_Active , AR2Arb_Active_Clr => AR2Arb_Active_Clr ); end generate GEN_ARB; --------------------------------------------------------------------------- -- Generate: GEN_DUAL -- Purpose: Dual mode. AWREADY and ARREADY are generated from each -- wr_chnl and rd_chnl module. --------------------------------------------------------------------------- GEN_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate begin S_AXI_AWREADY <= S_AXI_AWREADY_i; S_AXI_ARREADY <= S_AXI_ARREADY_i; Arb2AW_Active <= '0'; Arb2AR_Active <= '0'; end generate GEN_DUAL; --------------------------------------------------------------------------- -- Instance: I_WR_CHNL -- -- Description: -- BRAM controller write channel logic. Controls AXI bus handshaking and -- data flow on the write address (AW), write data (W) and -- write response (B) channels. -- -- BRAM signals are marked as output from Wr Chnl for future implementation -- of merging Wr/Rd channel outputs to a single port of the BRAM module. -- --------------------------------------------------------------------------- I_WR_CHNL : entity work.wr_chnl generic map ( -- C_FAMILY => C_FAMILY , C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_ECC => C_ECC , C_ECC_WIDTH => C_ECC_WIDTH , C_ECC_TYPE => C_ECC_TYPE -- v1.03a ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , AXI_AWID => S_AXI_AWID , AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0), AXI_AWLEN => S_AXI_AWLEN , AXI_AWSIZE => S_AXI_AWSIZE , AXI_AWBURST => S_AXI_AWBURST , AXI_AWLOCK => S_AXI_AWLOCK , AXI_AWCACHE => S_AXI_AWCACHE , AXI_AWPROT => S_AXI_AWPROT , AXI_AWVALID => S_AXI_AWVALID , AXI_AWREADY => S_AXI_AWREADY_i , AXI_WDATA => S_AXI_WDATA , AXI_WSTRB => S_AXI_WSTRB , AXI_WLAST => S_AXI_WLAST , AXI_WVALID => S_AXI_WVALID , AXI_WREADY => S_AXI_WREADY , AXI_BID => S_AXI_BID , AXI_BRESP => S_AXI_BRESP , AXI_BVALID => S_AXI_BVALID , AXI_BREADY => S_AXI_BREADY , -- Arb Ports Arb2AW_Active => Arb2AW_Active , AW2Arb_Busy => AW2Arb_Busy , AW2Arb_Active_Clr => AW2Arb_Active_Clr , AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt , Sng_BRAM_Addr_Rst => WrChnl_BRAM_Addr_Rst , Sng_BRAM_Addr_Ld_En => WrChnl_BRAM_Addr_Ld_En , Sng_BRAM_Addr_Ld => WrChnl_BRAM_Addr_Ld , Sng_BRAM_Addr_Inc => WrChnl_BRAM_Addr_Inc , Sng_BRAM_Addr => bram_addr_int , -- ECC Ports Enable_ECC => Enable_ECC , BRAM_Addr_En => Wr_BRAM_Addr_En , FaultInjectClr => FaultInjectClr , CE_Failing_We => Wr_CE_Failing_We , Sl_CE => Wr_Sl_CE , Sl_UE => Wr_Sl_UE , Active_Wr => Active_Wr , FaultInjectData => FaultInjectData , FaultInjectECC => FaultInjectECC , BRAM_En => BRAM_En_A_i , -- BRAM_WE => BRAM_WE_A , -- 4/13 BRAM_WE => BRAM_WE_A_i , BRAM_WrData => BRAM_WrData_A , BRAM_RdData => BRAM_RdData_A , BRAM_Addr => BRAM_Addr_A_i ); --------------------------------------------------------------------------- -- Instance: I_RD_CHNL -- -- Description: -- BRAM controller read channel logic. Controls all handshaking and data -- flow on read address (AR) and read data (R) AXI channels. -- -- BRAM signals are marked as Rd Chnl signals for future implementation -- of merging Rd/Wr BRAM signals to a single BRAM port. -- --------------------------------------------------------------------------- I_RD_CHNL : entity work.rd_chnl generic map ( -- C_FAMILY => C_FAMILY , C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_ECC => C_ECC , C_ECC_WIDTH => C_ECC_WIDTH , C_ECC_TYPE => C_ECC_TYPE -- v1.03a ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , AXI_ARID => S_AXI_ARID , AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0), AXI_ARLEN => S_AXI_ARLEN , AXI_ARSIZE => S_AXI_ARSIZE , AXI_ARBURST => S_AXI_ARBURST , AXI_ARLOCK => S_AXI_ARLOCK , AXI_ARCACHE => S_AXI_ARCACHE , AXI_ARPROT => S_AXI_ARPROT , AXI_ARVALID => S_AXI_ARVALID , AXI_ARREADY => S_AXI_ARREADY_i , AXI_RID => S_AXI_RID , AXI_RDATA => S_AXI_RDATA , AXI_RRESP => S_AXI_RRESP , AXI_RLAST => S_AXI_RLAST , AXI_RVALID => S_AXI_RVALID , AXI_RREADY => S_AXI_RREADY , -- Arb Ports Arb2AR_Active => Arb2AR_Active , AR2Arb_Active_Clr => AR2Arb_Active_Clr , Sng_BRAM_Addr_Ld_En => RdChnl_BRAM_Addr_Ld_En , Sng_BRAM_Addr_Ld => RdChnl_BRAM_Addr_Ld , Sng_BRAM_Addr_Inc => RdChnl_BRAM_Addr_Inc , Sng_BRAM_Addr => bram_addr_int , -- ECC Ports Enable_ECC => Enable_ECC , BRAM_Addr_En => Rd_BRAM_Addr_En , CE_Failing_We => Rd_CE_Failing_We , Sl_CE => Rd_Sl_CE , Sl_UE => Rd_Sl_UE , BRAM_En => BRAM_En_B_i , BRAM_Addr => BRAM_Addr_B_i , BRAM_RdData => BRAM_RdData_i ); end architecture implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/impl/vhdl/image_filter_Mat2AXIvideo.vhd

2

23118

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity image_filter_Mat2AXIvideo is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_0_V_empty_n : IN STD_LOGIC; img_data_stream_0_V_read : OUT STD_LOGIC; img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_1_V_empty_n : IN STD_LOGIC; img_data_stream_1_V_read : OUT STD_LOGIC; img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_2_V_empty_n : IN STD_LOGIC; img_data_stream_2_V_read : OUT STD_LOGIC; OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0); OUTPUT_STREAM_TVALID : OUT STD_LOGIC; OUTPUT_STREAM_TREADY : IN STD_LOGIC; OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) ); end; architecture behav of image_filter_Mat2AXIvideo is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010"; constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100"; constant ap_ST_st5_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111"; constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000"; constant ap_const_lv13_1FFF : STD_LOGIC_VECTOR (12 downto 0) := "1111111111111"; constant ap_const_lv12_1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001"; constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111"; signal ap_done_reg : STD_LOGIC := '0'; signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_bdd_23 : BOOLEAN; signal p_3_reg_170 : STD_LOGIC_VECTOR (11 downto 0); signal ap_sig_bdd_60 : BOOLEAN; signal op2_assign_fu_186_p2 : STD_LOGIC_VECTOR (12 downto 0); signal op2_assign_reg_267 : STD_LOGIC_VECTOR (12 downto 0); signal exitcond3_fu_197_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC; signal ap_sig_bdd_74 : BOOLEAN; signal i_V_fu_202_p2 : STD_LOGIC_VECTOR (11 downto 0); signal i_V_reg_276 : STD_LOGIC_VECTOR (11 downto 0); signal exitcond4_fu_208_p2 : STD_LOGIC_VECTOR (0 downto 0); signal exitcond4_reg_281 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC; signal ap_sig_bdd_85 : BOOLEAN; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0'; signal ap_sig_bdd_99 : BOOLEAN; signal ap_sig_ioackin_OUTPUT_STREAM_TREADY : STD_LOGIC; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal j_V_fu_213_p2 : STD_LOGIC_VECTOR (11 downto 0); signal axi_last_V_fu_223_p2 : STD_LOGIC_VECTOR (0 downto 0); signal axi_last_V_reg_290 : STD_LOGIC_VECTOR (0 downto 0); signal p_s_reg_159 : STD_LOGIC_VECTOR (11 downto 0); signal ap_sig_cseq_ST_st5_fsm_3 : STD_LOGIC; signal ap_sig_bdd_130 : BOOLEAN; signal tmp_user_V_fu_96 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ioackin_OUTPUT_STREAM_TREADY : STD_LOGIC := '0'; signal tmp_cast_fu_182_p1 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_cast_38_fu_219_p1 : STD_LOGIC_VECTOR (12 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0); begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_done_reg assign process. -- ap_done_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_done_reg <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_continue)) then ap_done_reg <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0)))) then ap_done_reg <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ioackin_OUTPUT_STREAM_TREADY assign process. -- ap_reg_ioackin_OUTPUT_STREAM_TREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0; else if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_99 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (ap_const_logic_1 = OUTPUT_STREAM_TREADY)))) then ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it0 assign process. -- ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0)))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_1; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0))))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; end if; end if; end if; end process; -- p_3_reg_170 assign process. -- p_3_reg_170_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then p_3_reg_170 <= j_V_fu_213_p2; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_197_p2 = ap_const_lv1_0))) then p_3_reg_170 <= ap_const_lv12_0; end if; end if; end process; -- p_s_reg_159 assign process. -- p_s_reg_159_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_3)) then p_s_reg_159 <= i_V_reg_276; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then p_s_reg_159 <= ap_const_lv12_0; end if; end if; end process; -- tmp_user_V_fu_96 assign process. -- tmp_user_V_fu_96_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then tmp_user_V_fu_96 <= ap_const_lv1_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then tmp_user_V_fu_96 <= ap_const_lv1_1; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond4_fu_208_p2 = ap_const_lv1_0))) then axi_last_V_reg_290 <= axi_last_V_fu_223_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then exitcond4_reg_281 <= exitcond4_fu_208_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then i_V_reg_276 <= i_V_fu_202_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_60))) then op2_assign_reg_267 <= op2_assign_fu_186_p2; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_60, exitcond3_fu_197_p2, exitcond4_fu_208_p2, exitcond4_reg_281, ap_reg_ppiten_pp0_it0, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not(ap_sig_bdd_60)) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => if (not((exitcond3_fu_197_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st1_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; end if; when ap_ST_pp0_stg0_fsm_2 => if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0))))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond4_fu_208_p2 = ap_const_lv1_0)))) then ap_NS_fsm <= ap_ST_st5_fsm_3; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; end if; when ap_ST_st5_fsm_3 => ap_NS_fsm <= ap_ST_st2_fsm_1; when others => ap_NS_fsm <= "XXXX"; end case; end process; OUTPUT_STREAM_TDATA <= (((ap_const_lv8_FF & img_data_stream_2_V_dout) & img_data_stream_1_V_dout) & img_data_stream_0_V_dout); OUTPUT_STREAM_TDEST <= ap_const_lv1_0; OUTPUT_STREAM_TID <= ap_const_lv1_0; OUTPUT_STREAM_TKEEP <= ap_const_lv4_F; OUTPUT_STREAM_TLAST <= axi_last_V_reg_290; OUTPUT_STREAM_TSTRB <= ap_const_lv4_0; OUTPUT_STREAM_TUSER <= tmp_user_V_fu_96; -- OUTPUT_STREAM_TVALID assign process. -- OUTPUT_STREAM_TVALID_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_reg_ppiten_pp0_it1, ap_reg_ioackin_OUTPUT_STREAM_TREADY) begin if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_99 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (ap_const_logic_0 = ap_reg_ioackin_OUTPUT_STREAM_TREADY)))) then OUTPUT_STREAM_TVALID <= ap_const_logic_1; else OUTPUT_STREAM_TVALID <= ap_const_logic_0; end if; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_done_reg, exitcond3_fu_197_p2, ap_sig_cseq_ST_st2_fsm_1) begin if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(exitcond3_fu_197_p2, ap_sig_cseq_ST_st2_fsm_1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_197_p2 = ap_const_lv1_0)))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_sig_bdd_130 assign process. -- ap_sig_bdd_130_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_130 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; -- ap_sig_bdd_23 assign process. -- ap_sig_bdd_23_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_23 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; -- ap_sig_bdd_60 assign process. -- ap_sig_bdd_60_assign_proc : process(ap_start, ap_done_reg) begin ap_sig_bdd_60 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1)); end process; -- ap_sig_bdd_74 assign process. -- ap_sig_bdd_74_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_74 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; -- ap_sig_bdd_85 assign process. -- ap_sig_bdd_85_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_85 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; -- ap_sig_bdd_99 assign process. -- ap_sig_bdd_99_assign_proc : process(img_data_stream_0_V_empty_n, img_data_stream_1_V_empty_n, img_data_stream_2_V_empty_n, exitcond4_reg_281) begin ap_sig_bdd_99 <= (((img_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond4_reg_281 = ap_const_lv1_0)) or ((exitcond4_reg_281 = ap_const_lv1_0) and (img_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond4_reg_281 = ap_const_lv1_0) and (img_data_stream_2_V_empty_n = ap_const_logic_0))); end process; -- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. -- ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_85) begin if (ap_sig_bdd_85) then ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st1_fsm_0 assign process. -- ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_23) begin if (ap_sig_bdd_23) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st2_fsm_1 assign process. -- ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_74) begin if (ap_sig_bdd_74) then ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st5_fsm_3 assign process. -- ap_sig_cseq_ST_st5_fsm_3_assign_proc : process(ap_sig_bdd_130) begin if (ap_sig_bdd_130) then ap_sig_cseq_ST_st5_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_st5_fsm_3 <= ap_const_logic_0; end if; end process; -- ap_sig_ioackin_OUTPUT_STREAM_TREADY assign process. -- ap_sig_ioackin_OUTPUT_STREAM_TREADY_assign_proc : process(OUTPUT_STREAM_TREADY, ap_reg_ioackin_OUTPUT_STREAM_TREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_OUTPUT_STREAM_TREADY)) then ap_sig_ioackin_OUTPUT_STREAM_TREADY <= OUTPUT_STREAM_TREADY; else ap_sig_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1; end if; end process; axi_last_V_fu_223_p2 <= "1" when (tmp_cast_38_fu_219_p1 = op2_assign_reg_267) else "0"; exitcond3_fu_197_p2 <= "1" when (p_s_reg_159 = img_rows_V_read) else "0"; exitcond4_fu_208_p2 <= "1" when (p_3_reg_170 = img_cols_V_read) else "0"; i_V_fu_202_p2 <= std_logic_vector(unsigned(p_s_reg_159) + unsigned(ap_const_lv12_1)); -- img_data_stream_0_V_read assign process. -- img_data_stream_0_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then img_data_stream_0_V_read <= ap_const_logic_1; else img_data_stream_0_V_read <= ap_const_logic_0; end if; end process; -- img_data_stream_1_V_read assign process. -- img_data_stream_1_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then img_data_stream_1_V_read <= ap_const_logic_1; else img_data_stream_1_V_read <= ap_const_logic_0; end if; end process; -- img_data_stream_2_V_read assign process. -- img_data_stream_2_V_read_assign_proc : process(exitcond4_reg_281, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_99, ap_sig_ioackin_OUTPUT_STREAM_TREADY, ap_reg_ppiten_pp0_it1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_99 or ((exitcond4_reg_281 = ap_const_lv1_0) and (ap_const_logic_0 = ap_sig_ioackin_OUTPUT_STREAM_TREADY))) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then img_data_stream_2_V_read <= ap_const_logic_1; else img_data_stream_2_V_read <= ap_const_logic_0; end if; end process; j_V_fu_213_p2 <= std_logic_vector(unsigned(p_3_reg_170) + unsigned(ap_const_lv12_1)); op2_assign_fu_186_p2 <= std_logic_vector(unsigned(tmp_cast_fu_182_p1) + unsigned(ap_const_lv13_1FFF)); tmp_cast_38_fu_219_p1 <= std_logic_vector(resize(unsigned(p_3_reg_170),13)); tmp_cast_fu_182_p1 <= std_logic_vector(resize(unsigned(img_cols_V_read),13)); end behav;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/FIFO_image_filter_src0_rows_V.vhd

2

4556

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_src0_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_src0_rows_V_shiftReg; architecture rtl of FIFO_image_filter_src0_rows_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_src0_rows_V is generic ( MEM_STYLE : string := "shiftreg"; DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_src0_rows_V is component FIFO_image_filter_src0_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_src0_rows_V_shiftReg : FIFO_image_filter_src0_rows_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/demo/ipi_proj/srcs/ip/vsrc_sel_v1_0/vhdl/video_src_sel.vhd

6

8306

-- *************************************************************************** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2010 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- *************************************************************************** ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Library UNISIM; use UNISIM.vcomponents.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_NUM_REG -- Number of software accessible registers -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Resetn -- Bus to IP reset -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity vsrc_sel is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_CHANNELS : integer := 1 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ -- User logic ports video_clk_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); video_clk_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); hsync_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); hsync_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); vsync_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); vsync_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); de_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); de_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); video_clk : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); hsync : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); vsync : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); de : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); video_sel : in std_logic ); attribute MAX_FANOUT : string; attribute SIGIS : string; -- attribute SIGIS of Bus2IP_Clk : signal is "CLK"; -- attribute SIGIS of Bus2IP_Resetn : signal is "RST"; end entity vsrc_sel; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of vsrc_sel is begin de <= de_1 when video_sel = '0' else de_2; hsync <= hsync_1 when video_sel = '0' else hsync_2; vsync <= vsync_1 when video_sel = '0' else vsync_2; VIDEO_SEL_GEN:for i in 0 to C_NUM_CHANNELS-1 generate begin BUFGMUX_INST : BUFGMUX generic map ( CLK_SEL_TYPE => "SYNC" -- Not supported. Must be "SYNC". ) port map ( O => video_clk(i), -- 1-bit output: Clock buffer output I0 => video_clk_1(i), -- 1-bit input: Clock buffer input (S=0) I1 => video_clk_2(i), -- 1-bit input: Clock buffer input (S=1) S => video_sel-- 1-bit input: Clock buffer select ); end generate VIDEO_SEL_GEN; end IMP;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_ftch_sm.vhd

4

47863

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_ftch_sm.vhd -- Description: This entity manages fetching of descriptors. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.clog2; ------------------------------------------------------------------------------- entity axi_sg_ftch_sm is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_INCLUDE_CH1 : integer range 0 to 1 := 1; -- Include or Exclude channel 1 scatter gather engine -- 0 = Exclude Channel 1 SG Engine -- 1 = Include Channel 1 SG Engine C_INCLUDE_CH2 : integer range 0 to 1 := 1; -- Include or Exclude channel 2 scatter gather engine -- 0 = Exclude Channel 2 SG Engine -- 1 = Include Channel 2 SG Engine C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1; -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1 -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- updt_error : in std_logic ; -- -- -- Channel 1 Control and Status -- ch1_run_stop : in std_logic ; -- ch1_desc_flush : in std_logic ; -- ch1_updt_done : in std_logic ; -- ch1_sg_idle : in std_logic ; -- ch1_tailpntr_enabled : in std_logic ; -- ch1_ftch_queue_full : in std_logic ; -- ch1_ftch_queue_empty : in std_logic ; -- ch1_ftch_pause : in std_logic ; -- ch1_fetch_address : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch1_ftch_active : out std_logic ; -- ch1_ftch_idle : out std_logic ; -- ch1_ftch_interr_set : out std_logic ; -- ch1_ftch_slverr_set : out std_logic ; -- ch1_ftch_decerr_set : out std_logic ; -- ch1_ftch_err_early : out std_logic ; -- ch1_ftch_stale_desc : out std_logic ; -- -- -- Channel 2 Control and Status -- ch2_run_stop : in std_logic ; -- ch2_desc_flush : in std_logic ; -- ch2_updt_done : in std_logic ; -- ch2_sg_idle : in std_logic ; -- ch2_tailpntr_enabled : in std_logic ; -- ch2_ftch_queue_full : in std_logic ; -- ch2_ftch_queue_empty : in std_logic ; -- ch2_ftch_pause : in std_logic ; -- ch2_fetch_address : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch2_ftch_active : out std_logic ; -- ch2_ftch_idle : out std_logic ; -- ch2_ftch_interr_set : out std_logic ; -- ch2_ftch_slverr_set : out std_logic ; -- ch2_ftch_decerr_set : out std_logic ; -- ch2_ftch_err_early : out std_logic ; -- ch2_ftch_stale_desc : out std_logic ; -- -- -- DataMover Command -- ftch_cmnd_wr : out std_logic ; -- ftch_cmnd_data : out std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- DataMover Status -- ftch_done : in std_logic ; -- ftch_error : in std_logic ; -- ftch_interr : in std_logic ; -- ftch_slverr : in std_logic ; -- ftch_decerr : in std_logic ; -- ftch_stale_desc : in std_logic ; -- ftch_error_early : in std_logic ; -- ftch_error_addr : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) -- ); end axi_sg_ftch_sm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_ftch_sm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; attribute mark_debug : string; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- DataMover Command Type constant FETCH_CMD_TYPE : std_logic := '1'; -- DataMover Cmnd Reserved Bits constant FETCH_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0'); -- DataMover Cmnd Reserved Bits constant FETCH_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0'); -- DataMover Cmnd Bytes to Xfer for Channel 1 constant FETCH_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0) := std_logic_vector(to_unsigned( (C_SG_CH1_WORDS_TO_FETCH*4),SG_BTT_WIDTH)); -- DataMover Cmnd Bytes to Xfer for Channel 2 constant FETCH_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0) := std_logic_vector(to_unsigned( (C_SG_CH2_WORDS_TO_FETCH*4),SG_BTT_WIDTH)); -- DataMover Cmnd Reserved Bits constant FETCH_CMD_RSVD : std_logic_vector( DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH) := (others => '0'); -- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate -- Required width in bits for C_SG_FTCH_DESC2QUEUE --constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1); -- ---- Vector version of C_SG_FTCH_DESC2QUEUE --constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) -- := std_logic_vector(to_unsigned -- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH)); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- DataMover Commmand TAG signal fetch_tag : std_logic_vector(3 downto 0) := (others => '0'); type SG_FTCH_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, FETCH_STATUS, FETCH_ERROR ); signal ftch_cs : SG_FTCH_STATE_TYPE; signal ftch_ns : SG_FTCH_STATE_TYPE; -- State Machine Signals signal ch1_active_set : std_logic := '0'; signal ch2_active_set : std_logic := '0'; signal write_cmnd_cmb : std_logic := '0'; signal ch1_ftch_sm_idle : std_logic := '0'; signal ch2_ftch_sm_idle : std_logic := '0'; signal ch1_pause_fetch : std_logic := '0'; signal ch2_pause_fetch : std_logic := '0'; signal ch2_pause_fetch1 : std_logic := '0'; signal ch2_pause_fetch2 : std_logic := '0'; signal ch2_pause_fetch3 : std_logic := '0'; signal ch2_updt_done1 : std_logic := '0'; signal ch2_updt_done2 : std_logic := '0'; -- Misc Signals signal fetch_cmd_addr : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal ch1_active_i : std_logic := '0'; signal service_ch1 : std_logic := '0'; signal ch2_active_i : std_logic := '0'; signal service_ch2 : std_logic := '0'; attribute mark_debug of ch1_active_i : signal is "true"; attribute mark_debug of ch2_active_i : signal is "true"; signal fetch_cmd_btt : std_logic_vector (SG_BTT_WIDTH-1 downto 0) := (others => '0'); signal ch1_stale_descriptor : std_logic := '0'; signal ch2_stale_descriptor : std_logic := '0'; attribute mark_debug of ch1_stale_descriptor : signal is "true"; attribute mark_debug of ch2_stale_descriptor : signal is "true"; signal ch1_ftch_interr_set_i : std_logic := '0'; signal ch2_ftch_interr_set_i : std_logic := '0'; -- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate -- counts for keeping track of queue descriptors to prevent -- fifo fill --signal ch1_desc_ftched_count : std_logic_vector -- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0'); --signal ch2_desc_ftched_count : std_logic_vector -- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ch1_ftch_active <= ch1_active_i; ch2_ftch_active <= ch2_active_i; ------------------------------------------------------------------------------- -- Scatter Gather Fetch State Machine ------------------------------------------------------------------------------- SG_FTCH_MACHINE : process(ftch_cs, ch1_active_i, ch2_active_i, service_ch1, service_ch2, ftch_error, ftch_done) begin -- Default signal assignment ch1_active_set <= '0'; ch2_active_set <= '0'; write_cmnd_cmb <= '0'; ch1_ftch_sm_idle <= '0'; ch2_ftch_sm_idle <= '0'; ftch_ns <= ftch_cs; case ftch_cs is ------------------------------------------------------------------- when IDLE => ch1_ftch_sm_idle <= not service_ch1; ch2_ftch_sm_idle <= not service_ch2; -- sg error during fetch - shut down if(ftch_error = '1')then ftch_ns <= FETCH_ERROR; -- If channel 1 is running and not idle and queue is not full -- then fetch descriptor for channel 1 elsif(service_ch1 = '1')then ch1_active_set <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- If channel 2 is running and not idle and queue is not full -- then fetch descriptor for channel 2 elsif(service_ch2 = '1')then ch2_active_set <= '1'; ftch_ns <= FETCH_DESCRIPTOR; else ftch_ns <= IDLE; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => -- sg error during fetch - shut down if(ftch_error = '1')then ftch_ns <= FETCH_ERROR; else ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1; ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2; write_cmnd_cmb <= '1'; ftch_ns <= FETCH_STATUS; end if; ------------------------------------------------------------------- when FETCH_STATUS => ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1; ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2; -- sg error during fetch - shut down if(ftch_error = '1')then ftch_ns <= FETCH_ERROR; elsif(ftch_done = '1')then -- If just finished fethcing for channel 2 then... if(ch2_active_i = '1')then -- If ready, fetch descriptor for channel 1 if(service_ch1 = '1')then ch1_active_set <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- Else if channel 2 still ready then fetch -- another descriptor for channel 2 elsif(service_ch2 = '1')then ch1_ftch_sm_idle <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- Otherwise return to IDLE else ftch_ns <= IDLE; end if; -- If just finished fethcing for channel 1 then... elsif(ch1_active_i = '1')then -- If ready, fetch descriptor for channel 2 if(service_ch2 = '1')then ch2_active_set <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- Else if channel 1 still ready then fetch -- another descriptor for channel 1 elsif(service_ch1 = '1')then ch2_ftch_sm_idle <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- Otherwise return to IDLE else ftch_ns <= IDLE; end if; else ftch_ns <= IDLE; end if; else ftch_ns <= FETCH_STATUS; end if; ------------------------------------------------------------------- when FETCH_ERROR => ch1_ftch_sm_idle <= '1'; ch2_ftch_sm_idle <= '1'; ftch_ns <= FETCH_ERROR; ------------------------------------------------------------------- -- coverage off when others => ftch_ns <= IDLE; -- coverage on end case; end process SG_FTCH_MACHINE; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then ftch_cs <= IDLE; else ftch_cs <= ftch_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- Channel included therefore generate fetch logic ------------------------------------------------------------------------------- GEN_CH1_FETCH : if C_INCLUDE_CH1 = 1 generate begin ------------------------------------------------------------------------------- -- Active channel flag. Indicates which channel is active. -- 0 = channel active -- 1 = channel active ------------------------------------------------------------------------------- CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or ch2_active_set = '1')then ch1_active_i <= '0'; elsif(ch1_active_set = '1')then ch1_active_i <= '1'; end if; end if; end process CH1_ACTIVE_PROCESS; ------------------------------------------------------------------------------- -- Channel 1 IDLE process. Indicates channel 1 fetch process is IDLE -- This is 1 part of determining IDLE for a channel ------------------------------------------------------------------------------- CH1_IDLE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch1_ftch_idle <= '1'; -- SG Error therefore force IDLE -- CR564855 - fetch idle asserted too soon when update error occured. -- fetch idle does not need to be concerned with updt_error. This is -- because on going fetch is guarentteed to complete regardless of dma -- controller or sg update engine. --elsif(updt_error = '1' or ftch_error = '1' elsif(ftch_error = '1' or ch1_ftch_interr_set_i = '1')then ch1_ftch_idle <= '1'; -- When SG Fetch no longer idle then clear fetch idle elsif(ch1_sg_idle = '0')then ch1_ftch_idle <= '0'; -- If tail = cur and fetch queue is empty then elsif(ch1_sg_idle = '1' and ch1_ftch_queue_empty = '1' and ch1_ftch_sm_idle = '1')then ch1_ftch_idle <= '1'; end if; end if; end process CH1_IDLE_PROCESS; ------------------------------------------------------------------------------- -- For No Fetch Queue, generate pause logic to prevent partial descriptor from -- being fetched and then endless throttle on AXI read bus ------------------------------------------------------------------------------- GEN_CH1_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate begin REG_PAUSE_FETCH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- On descriptor update done clear pause if(m_axi_sg_aresetn = '0' or ch1_updt_done = '1')then ch1_pause_fetch <= '0'; -- If channel active and command written then pause elsif(ch1_active_i='1' and write_cmnd_cmb = '1')then ch1_pause_fetch <= '1'; end if; end if; end process REG_PAUSE_FETCH; end generate GEN_CH1_FETCH_PAUSE; -- Fetch queues so do not need to pause GEN_CH1_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate -- -- CR585958 -- -- Required width in bits for C_SG_FTCH_DESC2QUEUE -- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1); -- -- Vector version of C_SG_FTCH_DESC2QUEUE -- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) -- := std_logic_vector(to_unsigned -- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH)); -- signal desc_queued_incr : std_logic := '0'; -- signal desc_queued_decr : std_logic := '0'; -- -- -- CR585958 -- signal ch1_desc_ftched_count: std_logic_vector -- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0'); -- begin -- -- desc_queued_incr <= '1' when ch1_active_i = '1' -- and write_cmnd_cmb = '1' -- and ch1_ftch_descpulled = '0' -- else '0'; -- -- desc_queued_decr <= '1' when ch1_ftch_descpulled = '1' -- and not (ch1_active_i = '1' and write_cmnd_cmb = '1') -- else '0'; -- -- -- Keep track of descriptors queued version descriptors updated -- DESC_FETCHED_CNTR : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ch1_desc_ftched_count <= (others => '0'); -- elsif(desc_queued_incr = '1')then -- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) + 1); -- elsif(desc_queued_decr = '1')then -- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) - 1); -- end if; -- end if; -- end process DESC_FETCHED_CNTR; -- -- REG_PAUSE_FETCH : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ch1_pause_fetch <= '0'; -- elsif(ch1_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then -- ch1_pause_fetch <= '1'; -- else -- ch1_pause_fetch <= '0'; -- end if; -- end if; -- end process REG_PAUSE_FETCH; -- -- -- ch1_pause_fetch <= ch1_ftch_pause; end generate GEN_CH1_NO_FETCH_PAUSE; ------------------------------------------------------------------------------- -- Channel 1 ready to be serviced? ------------------------------------------------------------------------------- service_ch1 <= '1' when ch1_run_stop = '1' -- Channel running and ch1_sg_idle = '0' -- SG Engine running and ch1_ftch_queue_full = '0' -- Queue not full and updt_error = '0' -- No SG Update error and ch1_stale_descriptor = '0' -- No Stale Descriptors and ch1_desc_flush = '0' -- Not flushing desc and ch1_pause_fetch = '0' -- Not pausing else '0'; ------------------------------------------------------------------------------- -- Log Fetch Errors ------------------------------------------------------------------------------- INT_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch1_ftch_interr_set_i <= '0'; -- Channel active and datamover int error or fetch done and descriptor stale elsif((ch1_active_i = '1' and ftch_interr = '1') or ((ftch_done = '1' or ftch_error = '1') and ch1_stale_descriptor = '1'))then ch1_ftch_interr_set_i <= '1'; end if; end if; end process INT_ERROR_PROCESS; ch1_ftch_interr_set <= ch1_ftch_interr_set_i; SLV_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch1_ftch_slverr_set <= '0'; elsif(ch1_active_i = '1' and ftch_slverr = '1')then ch1_ftch_slverr_set <= '1'; end if; end if; end process SLV_ERROR_PROCESS; DEC_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch1_ftch_decerr_set <= '0'; elsif(ch1_active_i = '1' and ftch_decerr = '1')then ch1_ftch_decerr_set <= '1'; end if; end if; end process DEC_ERROR_PROCESS; -- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor -- from being used by dma controller ch1_ftch_err_early <= '1' when ftch_error_early = '1' and ch1_active_i = '1' else '0'; -- Enable stale descriptor check GEN_CH1_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 generate begin ----------------------------------------------------------------------- -- Stale Descriptor Error ----------------------------------------------------------------------- CH1_STALE_DESC : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset then clear flag if(m_axi_sg_aresetn = '0')then ch1_stale_descriptor <= '0'; elsif(ftch_stale_desc = '1' and ch1_active_i = '1' )then ch1_stale_descriptor <= '1'; end if; end if; end process CH1_STALE_DESC; end generate GEN_CH1_STALE_CHECK; -- Disable stale descriptor check GEN_CH1_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 generate begin ch1_stale_descriptor <= '0'; end generate GEN_CH1_NO_STALE_CHECK; -- Early detection of Stale Descriptor (valid only in tailpntr mode) used -- to prevent error'ed descriptor from being used. ch1_ftch_stale_desc <= ch1_stale_descriptor; end generate GEN_CH1_FETCH; ------------------------------------------------------------------------------- -- Channel excluded therefore do not generate fetch logic ------------------------------------------------------------------------------- GEN_NO_CH1_FETCH : if C_INCLUDE_CH1 = 0 generate begin service_ch1 <= '0'; ch1_active_i <= '0'; ch1_ftch_idle <= '0'; ch1_ftch_interr_set <= '0'; ch1_ftch_slverr_set <= '0'; ch1_ftch_decerr_set <= '0'; ch1_ftch_err_early <= '0'; ch1_ftch_stale_desc <= '0'; end generate GEN_NO_CH1_FETCH; ------------------------------------------------------------------------------- -- Channel included therefore generate fetch logic ------------------------------------------------------------------------------- GEN_CH2_FETCH : if C_INCLUDE_CH2 = 1 generate begin ------------------------------------------------------------------------------- -- Active channel flag. Indicates which channel is active. -- 0 = channel active -- 1 = channel active ------------------------------------------------------------------------------- CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or ch1_active_set = '1')then ch2_active_i <= '0'; elsif(ch2_active_set = '1')then ch2_active_i <= '1'; end if; end if; end process CH2_ACTIVE_PROCESS; ------------------------------------------------------------------------------- -- Channel 2 IDLE process. Indicates channel 2 fetch process is IDLE -- This is 1 part of determining IDLE for a channel ------------------------------------------------------------------------------- CH2_IDLE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch2_ftch_idle <= '1'; -- SG Error therefore force IDLE -- CR564855 - fetch idle asserted too soon when update error occured. -- fetch idle does not need to be concerned with updt_error. This is -- because on going fetch is guarentteed to complete regardless of dma -- controller or sg update engine. -- elsif(updt_error = '1' or ftch_error = '1' elsif(ftch_error = '1' or ch2_ftch_interr_set_i = '1')then ch2_ftch_idle <= '1'; -- When SG Fetch no longer idle then clear fetch idle elsif(ch2_sg_idle = '0')then ch2_ftch_idle <= '0'; -- If tail = cur and fetch queue is empty then elsif(ch2_sg_idle = '1' and ch2_ftch_queue_empty = '1' and ch2_ftch_sm_idle = '1')then ch2_ftch_idle <= '1'; end if; end if; end process CH2_IDLE_PROCESS; ------------------------------------------------------------------------------- -- For No Fetch Queue, generate pause logic to prevent partial descriptor from -- being fetched and then endless throttle on AXI read bus ------------------------------------------------------------------------------- GEN_CH2_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate begin REG_PAUSE_FETCH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- On descriptor update done clear pause if(m_axi_sg_aresetn = '0' or ch2_updt_done = '1')then ch2_pause_fetch <= '0'; -- If channel active and command written then pause elsif(ch2_active_i='1' and write_cmnd_cmb = '1')then ch2_pause_fetch <= '1'; end if; ch2_pause_fetch1 <= ch2_pause_fetch; ch2_pause_fetch2 <= ch2_pause_fetch1; ch2_pause_fetch3 <= ch2_pause_fetch2; end if; end process REG_PAUSE_FETCH; end generate GEN_CH2_FETCH_PAUSE; -- Fetch queues so do not need to pause GEN_CH2_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate -- -- CR585958 -- -- Required width in bits for C_SG_FTCH_DESC2QUEUE -- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1); -- -- Vector version of C_SG_FTCH_DESC2QUEUE -- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) -- := std_logic_vector(to_unsigned -- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH)); -- signal desc_queued_incr : std_logic := '0'; -- signal desc_queued_decr : std_logic := '0'; -- -- -- CR585958 -- signal ch2_desc_ftched_count: std_logic_vector -- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0'); -- -- begin -- -- desc_queued_incr <= '1' when ch2_active_i = '1' -- and write_cmnd_cmb = '1' -- and ch2_ftch_descpulled = '0' -- else '0'; -- -- desc_queued_decr <= '1' when ch2_ftch_descpulled = '1' -- and not (ch2_active_i = '1' and write_cmnd_cmb = '1') -- else '0'; -- -- -- Keep track of descriptors queued version descriptors updated -- DESC_FETCHED_CNTR : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ch2_desc_ftched_count <= (others => '0'); -- elsif(desc_queued_incr = '1')then -- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) + 1); -- elsif(desc_queued_decr = '1')then -- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) - 1); -- end if; -- end if; -- end process DESC_FETCHED_CNTR; -- -- REG_PAUSE_FETCH : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ch2_pause_fetch <= '0'; -- elsif(ch2_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then -- ch2_pause_fetch <= '1'; -- else -- ch2_pause_fetch <= '0'; -- end if; -- end if; -- end process REG_PAUSE_FETCH; -- ch2_pause_fetch <= ch2_ftch_pause; end generate GEN_CH2_NO_FETCH_PAUSE; ------------------------------------------------------------------------------- -- Channel 2 ready to be serviced? ------------------------------------------------------------------------------- MCDMA : if (C_ENABLE_MULTI_CHANNEL = 1) generate NOQUEUE : if (C_SG_FTCH_DESC2QUEUE = 0) generate service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running and ch2_sg_idle = '0' -- SG Engine running and ch2_ftch_queue_full = '0' -- Queue not full and updt_error = '0' -- No SG Update error and ch2_stale_descriptor = '0' -- No Stale Descriptors and ch2_desc_flush = '0' -- Not flushing desc and ch2_pause_fetch3 = '0' -- No fetch pause else '0'; end generate NOQUEUE; QUEUE : if (C_SG_FTCH_DESC2QUEUE /= 0) generate service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running and ch2_sg_idle = '0' -- SG Engine running and ch2_ftch_queue_full = '0' -- Queue not full and updt_error = '0' -- No SG Update error and ch2_stale_descriptor = '0' -- No Stale Descriptors and ch2_desc_flush = '0' -- Not flushing desc and ch2_pause_fetch = '0' -- No fetch pause else '0'; end generate QUEUE; end generate MCDMA; NO_MCDMA : if (C_ENABLE_MULTI_CHANNEL = 0) generate service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running and ch2_sg_idle = '0' -- SG Engine running and ch2_ftch_queue_full = '0' -- Queue not full and updt_error = '0' -- No SG Update error and ch2_stale_descriptor = '0' -- No Stale Descriptors and ch2_desc_flush = '0' -- Not flushing desc and ch2_pause_fetch = '0' -- No fetch pause else '0'; end generate NO_MCDMA; ------------------------------------------------------------------------------- -- Log Fetch Errors ------------------------------------------------------------------------------- INT_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch2_ftch_interr_set_i <= '0'; -- Channel active and datamover int error or fetch done and descriptor stale elsif((ch2_active_i = '1' and ftch_interr = '1') or ((ftch_done = '1' or ftch_error = '1') and ch2_stale_descriptor = '1'))then ch2_ftch_interr_set_i <= '1'; end if; end if; end process INT_ERROR_PROCESS; ch2_ftch_interr_set <= ch2_ftch_interr_set_i; SLV_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch2_ftch_slverr_set <= '0'; elsif(ch2_active_i = '1' and ftch_slverr = '1')then ch2_ftch_slverr_set <= '1'; end if; end if; end process SLV_ERROR_PROCESS; DEC_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch2_ftch_decerr_set <= '0'; elsif(ch2_active_i = '1' and ftch_decerr = '1')then ch2_ftch_decerr_set <= '1'; end if; end if; end process DEC_ERROR_PROCESS; -- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor -- from being used by dma controller ch2_ftch_err_early <= '1' when ftch_error_early = '1' and ch2_active_i = '1' else '0'; -- Enable stale descriptor check GEN_CH2_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 1 generate begin ----------------------------------------------------------------------- -- Stale Descriptor Error ----------------------------------------------------------------------- CH2_STALE_DESC : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset then clear flag if(m_axi_sg_aresetn = '0')then ch2_stale_descriptor <= '0'; elsif(ftch_stale_desc = '1' and ch2_active_i = '1' )then ch2_stale_descriptor <= '1'; end if; end if; end process CH2_STALE_DESC; end generate GEN_CH2_STALE_CHECK; -- Disable stale descriptor check GEN_CH2_NO_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 0 generate begin ch2_stale_descriptor <= '0'; end generate GEN_CH2_NO_STALE_CHECK; -- Early detection of Stale Descriptor (valid only in tailpntr mode) used -- to prevent error'ed descriptor from being used. ch2_ftch_stale_desc <= ch2_stale_descriptor; end generate GEN_CH2_FETCH; ------------------------------------------------------------------------------- -- Channel excluded therefore do not generate fetch logic ------------------------------------------------------------------------------- GEN_NO_CH2_FETCH : if C_INCLUDE_CH2 = 0 generate begin service_ch2 <= '0'; ch2_active_i <= '0'; ch2_ftch_idle <= '0'; ch2_ftch_interr_set <= '0'; ch2_ftch_slverr_set <= '0'; ch2_ftch_decerr_set <= '0'; ch2_ftch_err_early <= '0'; ch2_ftch_stale_desc <= '0'; end generate GEN_NO_CH2_FETCH; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- Assign fetch address fetch_cmd_addr <= ch1_fetch_address when ch1_active_i = '1' else ch2_fetch_address; -- Assign bytes to transfer (BTT) fetch_cmd_btt <= FETCH_CH1_CMD_BTT when ch1_active_i = '1' else FETCH_CH2_CMD_BTT; fetch_tag <= "0001" when ch1_active_i = '1' else "0000"; -- When command by sm, drive command to ftch_cmdsts_if --GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ftch_cmnd_wr <= '0'; -- ftch_cmnd_data <= (others => '0'); -- -- Fetch SM issued a command write -- elsif(write_cmnd_cmb = '1')then -- ftch_cmnd_wr <= '1'; -- ftch_cmnd_data <= FETCH_CMD_RSVD -- & fetch_tag -- & fetch_cmd_addr -- & FETCH_MSB_IGNORED -- & FETCH_CMD_TYPE -- & FETCH_LSB_IGNORED -- & fetch_cmd_btt; -- else -- ftch_cmnd_wr <= '0'; -- end if; -- end if; -- end process GEN_DATAMOVER_CMND; ftch_cmnd_wr <= write_cmnd_cmb; ftch_cmnd_data <= FETCH_CMD_RSVD & fetch_tag & fetch_cmd_addr & FETCH_MSB_IGNORED & FETCH_CMD_TYPE & FETCH_LSB_IGNORED & fetch_cmd_btt; ------------------------------------------------------------------------------- -- Capture and hold fetch address in case an error occurs ------------------------------------------------------------------------------- LOG_ERROR_ADDR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then ftch_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= (others => '0'); elsif(write_cmnd_cmb = '1')then ftch_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= fetch_cmd_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB); end if; end if; end process LOG_ERROR_ADDR; ftch_error_addr (5 downto 0) <= "000000"; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_s2mm_full_wrap.vhd

5

92755

------------------------------------------------------------------------------- -- axi_datamover_s2mm_full_wrap.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_full_wrap.vhd -- -- Description: -- This file implements the DataMover S2MM FULL Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all ; -- axi_datamover Library Modules library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_reset ; use axi_datamover_v5_1.axi_datamover_cmd_status ; use axi_datamover_v5_1.axi_datamover_pcc ; use axi_datamover_v5_1.axi_datamover_ibttcc ; use axi_datamover_v5_1.axi_datamover_indet_btt ; use axi_datamover_v5_1.axi_datamover_s2mm_realign ; use axi_datamover_v5_1.axi_datamover_addr_cntl ; use axi_datamover_v5_1.axi_datamover_wrdata_cntl ; use axi_datamover_v5_1.axi_datamover_wr_status_cntl; Use axi_datamover_v5_1.axi_datamover_skid2mm_buf ; Use axi_datamover_v5_1.axi_datamover_skid_buf ; Use axi_datamover_v5_1.axi_datamover_wr_sf ; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_full_wrap is generic ( C_INCLUDE_S2MM : Integer range 0 to 2 := 1; -- Specifies the type of S2MM function to include -- 0 = Omit S2MM functionality -- 1 = Full S2MM Functionality -- 2 = Lite S2MM functionality C_S2MM_AWID : Integer range 0 to 255 := 9; -- Specifies the constant value to output on -- the ARID output port C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the S2MM ID port C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the S2MM Master Stream Data -- Channel data bus C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit S2MM Status FIFO -- 1 = Include S2MM Status FIFO C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the S2MM Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the S2MM function -- 0 = Omit DRE -- 1 = Include DRE C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the S2MM function C_S2MM_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the S2MM Command Interface C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if support for indeterminate packet lengths -- are to be received on the input Stream interface -- 0 = Omit support (User MUST transfer the exact number of -- bytes on the Stream interface as specified in the BTT -- field of the Corresponding DataMover Command) -- 1 = Include support for indeterminate packet lengths -- This causes FIFOs to be added and "Store and Forward" -- behavior of the S2MM function C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the S2MM internal -- address pipeline queues in the Write Address Controller -- and the Write Data Controller. Increasing this value will -- allow more Write Addresses to be issued to the AXI4 Write -- Address Channel before transmission of the associated -- write data on the Write Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_INCLUDE_S2MM_GP_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- S2MM (Write) General Purpose Store and Forward function -- 0 = Omit GP Store and Forward -- 1 = Include GP Store and Forward C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- S2MM Primary Clock and Reset inputs ---------------------------- s2mm_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- ------------------------------------------------------------------- -- S2MM Primary Reset input --------------------------------------- s2mm_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------------- -- S2MM Halt request input control -------------------------------- s2mm_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- S2MM Halt Complete status flag -- s2mm_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------------- -- S2MM Error discrete output ------------------------------------- s2mm_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------------------------- -- Optional Command and Status Clock and Reset ------------------- -- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 -- -- s2mm_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- s2mm_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------------ -- User Command Interface Ports (AXI Stream) ----------------------------------------------------- s2mm_cmd_wvalid : in std_logic; -- s2mm_cmd_wready : out std_logic; -- s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); -- -------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) -------------------------------------------------------- s2mm_sts_wvalid : out std_logic; -- s2mm_sts_wready : in std_logic; -- s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); -- s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); -- s2mm_sts_wlast : out std_logic; -- ---------------------------------------------------------------------------------------------------- -- Address posting controls --------------------------------------- s2mm_allow_addr_req : in std_logic; -- s2mm_addr_req_posted : out std_logic; -- s2mm_wr_xfer_cmplt : out std_logic; -- s2mm_ld_nxt_len : out std_logic; -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- ------------------------------------------------------------------- -- S2MM AXI Address Channel I/O -------------------------------------- s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- s2mm_awlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- s2mm_awsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- s2mm_awburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- s2mm_awprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- s2mm_awuser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- s2mm_awready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ----------- -- s2mm__awlock : out std_logic_vector(2 downto 0); -- -- s2mm__awcache : out std_logic_vector(4 downto 0); -- -- s2mm__awqos : out std_logic_vector(3 downto 0); -- -- s2mm__awregion : out std_logic_vector(3 downto 0); -- ----------------------------------------------------------------------- -- S2MM AXI MMap Write Data Channel I/O --------------------------------------------- s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); -- s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); -- s2mm_wlast : Out std_logic; -- s2mm_wvalid : Out std_logic; -- s2mm_wready : In std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI MMap Write response Channel I/O ----------------------------------------- s2mm_bresp : In std_logic_vector(1 downto 0); -- s2mm_bvalid : In std_logic; -- s2mm_bready : Out std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI Master Stream Channel I/O ----------------------------------------------- s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); -- s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); -- s2mm_strm_wlast : In std_logic; -- s2mm_strm_wvalid : In std_logic; -- s2mm_strm_wready : Out std_logic; -- -------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------ s2mm_dbg_sel : in std_logic_vector( 3 downto 0); -- s2mm_dbg_data : out std_logic_vector(31 downto 0) -- ----------------------------------------------------------------- ); end entity axi_datamover_s2mm_full_wrap; architecture implementation of axi_datamover_s2mm_full_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_wdemux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Write Strobe demux select control. -- ------------------------------------------------------------------- function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 7 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when 256 => num_addr_bits_needed := 5; when 512 => num_addr_bits_needed := 6; when others => -- 1024 bits num_addr_bits_needed := 7; end case; Return (num_addr_bits_needed); end function func_calc_wdemux_sel_bits; ------------------------------------------------------------------- -- Function -- -- Function Name: func_include_dre -- -- Function Description: -- This function desides if conditions are right for allowing DRE -- inclusion. -- ------------------------------------------------------------------- function func_include_dre (need_dre : integer; needed_data_width : integer) return integer is Variable include_dre : Integer := 0; begin if (need_dre = 1 and needed_data_width < 128 and needed_data_width > 8) Then include_dre := 1; Else include_dre := 0; End if; Return (include_dre); end function func_include_dre; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_align_width -- -- Function Description: -- This function calculates the needed DRE alignment port width\ -- based upon the inclusion of DRE and the needed bit width of the -- DRE. -- ------------------------------------------------------------------- function func_get_align_width (dre_included : integer; dre_data_width : integer) return integer is Variable align_port_width : Integer := 1; begin if (dre_included = 1) then If (dre_data_width = 64) Then align_port_width := 3; Elsif (dre_data_width = 32) Then align_port_width := 2; else -- 16 bit data width align_port_width := 1; End if; else align_port_width := 1; end if; Return (align_port_width); end function func_get_align_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_set_status_width -- -- Function Description: -- This function sets the width of the Status pipe depending on the -- Store and Forward inclusion or ommision. -- ------------------------------------------------------------------- function funct_set_status_width (store_forward_enabled : integer) return integer is Variable temp_status_bit_width : Integer := 8; begin If (store_forward_enabled = 1) Then temp_status_bit_width := 32; Else temp_status_bit_width := 8; End if; Return (temp_status_bit_width); end function funct_set_status_width; ------------------------------------------------------------------- -- Function -- -- Function Name: get_bits_needed -- -- Function Description: -- -- ------------------------------------------------------------------- function get_bits_needed (max_bytes : integer) return integer is Variable fvar_temp_bit_width : Integer := 1; begin if (max_bytes <= 1) then fvar_temp_bit_width := 1; elsif (max_bytes <= 3) then fvar_temp_bit_width := 2; elsif (max_bytes <= 7) then fvar_temp_bit_width := 3; elsif (max_bytes <= 15) then fvar_temp_bit_width := 4; elsif (max_bytes <= 31) then fvar_temp_bit_width := 5; elsif (max_bytes <= 63) then fvar_temp_bit_width := 6; elsif (max_bytes <= 127) then fvar_temp_bit_width := 7; elsif (max_bytes <= 255) then fvar_temp_bit_width := 8; elsif (max_bytes <= 511) then fvar_temp_bit_width := 9; elsif (max_bytes <= 1023) then fvar_temp_bit_width := 10; elsif (max_bytes <= 2047) then fvar_temp_bit_width := 11; elsif (max_bytes <= 4095) then fvar_temp_bit_width := 12; elsif (max_bytes <= 8191) then fvar_temp_bit_width := 13; else -- 8k - 16K fvar_temp_bit_width := 14; end if; Return (fvar_temp_bit_width); end function get_bits_needed; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 128 and 8192. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 128) then temp_pwr2 := 128; elsif (input_value <= 256) then temp_pwr2 := 256; elsif (input_value <= 512) then temp_pwr2 := 512; elsif (input_value <= 1024) then temp_pwr2 := 1024; elsif (input_value <= 2048) then temp_pwr2 := 2048; elsif (input_value <= 4096) then temp_pwr2 := 4096; else temp_pwr2 := 8192; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_need_realigner -- -- Function Description: -- Determines if the Realigner module needs to be included. -- ------------------------------------------------------------------- function funct_need_realigner (indet_btt_enabled : integer; dre_included : integer; gp_sf_included : integer) return integer is Variable temp_val : Integer := 0; begin If ((indet_btt_enabled = 1) or (dre_included = 1) or (gp_sf_included = 1)) Then temp_val := 1; else temp_val := 0; End if; Return (temp_val); end function funct_need_realigner; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_width -- -- Function Description: -- This function calculates the address offset width needed by -- the GP Store and Forward module with data packing. -- ------------------------------------------------------------------- function funct_get_sf_offset_width (mmap_dwidth : integer; stream_dwidth : integer) return integer is Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth; Variable fvar_temp_offset_width : Integer := 1; begin case FCONST_WIDTH_RATIO is when 1 => fvar_temp_offset_width := 1; when 2 => fvar_temp_offset_width := 1; when 4 => fvar_temp_offset_width := 2; when 8 => fvar_temp_offset_width := 3; when 16 => fvar_temp_offset_width := 4; when 32 => fvar_temp_offset_width := 5; when 64 => fvar_temp_offset_width := 6; when others => fvar_temp_offset_width := 7; end case; Return (fvar_temp_offset_width); end function funct_get_sf_offset_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stream_width2use -- -- Function Description: -- This function calculates the Stream width to use for S2MM -- modules downstream from the upsizing Store and Forward. If -- Store and forward is present, then the effective Stream width -- is the MMAP data width. If no Store and Forward then the Stream -- width is the input Stream width from the User. -- ------------------------------------------------------------------- function funct_get_stream_width2use (mmap_data_width : integer; stream_data_width : integer; sf_enabled : integer) return integer is Variable fvar_temp_width : Integer := 32; begin If (sf_enabled > 0) Then fvar_temp_width := mmap_data_width; Else fvar_temp_width := stream_data_width; End if; Return (fvar_temp_width); end function funct_get_stream_width2use; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_bytes_per_dbeat -- -- Function Description: -- This function calculates the number of bytes transfered per -- databeat on the MMap AXI4 Write Data Channel by the S2MM. The -- value is based on input parameterization of included functions -- in the S2MM block. -- ------------------------------------------------------------------- function funct_get_bytes_per_dbeat (ibtt_enabled : integer ; gpsf_enabled : integer ; stream_dwidth : integer ; mmap_dwidth : integer ) return integer is Variable fvar_temp_bytes_per_xfer : Integer := 4; begin If (ibtt_enabled > 0 or gpsf_enabled > 0) Then -- transfers will be upsized to mmap data width fvar_temp_bytes_per_xfer := mmap_dwidth/8; Else -- transfers will be in stream data widths (may be narrow transfers on mmap) fvar_temp_bytes_per_xfer := stream_dwidth/8; End if; Return (fvar_temp_bytes_per_xfer); end function funct_get_bytes_per_dbeat; -- Constant Declarations ---------------------------------------- Constant SF_ENABLED : integer := C_INCLUDE_S2MM_GP_SF + C_S2MM_SUPPORT_INDET_BTT; Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_S2MM_MDATA_WIDTH, C_S2MM_SDATA_WIDTH, SF_ENABLED); Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant IS_NOT_MM2S : integer range 0 to 1 := 0; Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID; Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH; Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH; Constant S2MM_MDATA_WIDTH : integer range 32 to 1024 := C_S2MM_MDATA_WIDTH; Constant S2MM_SDATA_WIDTH : integer range 8 to 1024 := C_S2MM_SDATA_WIDTH; Constant S2MM_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH; Constant S2MM_CMD_WIDTH : integer := (S2MM_TAG_WIDTH+S2MM_ADDR_WIDTH+32); Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := C_INCLUDE_S2MM_STSFIFO; Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH; Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC; Constant S2MM_BURST_SIZE : integer range 2 to 256 := C_S2MM_BURST_SIZE; Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH); Constant S2MM_BTT_USED : integer range 8 to 23 := C_S2MM_BTT_USED; Constant BITS_PER_BYTE : integer := 8; Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant S2MM_DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_SUPPORT_SCATTER : integer range 0 to 1 := 1; Constant ENABLE_INDET_BTT_SF : integer range 0 to 1 := C_S2MM_SUPPORT_INDET_BTT; Constant ENABLE_GP_SF : integer range 0 to 1 := C_INCLUDE_S2MM_GP_SF ; Constant BYTES_PER_MMAP_DBEAT : integer := funct_get_bytes_per_dbeat(ENABLE_INDET_BTT_SF , ENABLE_GP_SF , S2MM_SDATA_WIDTH , S2MM_MDATA_WIDTH); Constant MAX_BYTES_PER_BURST : integer := BYTES_PER_MMAP_DBEAT*S2MM_BURST_SIZE; Constant IBTT_XFER_BYTES_WIDTH : integer := get_bits_needed(MAX_BYTES_PER_BURST); Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going -- full thresholding -- in WSC Constant WSC_STATUS_WIDTH : integer range 8 to 32 := funct_set_status_width(ENABLE_INDET_BTT_SF); Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := S2MM_BTT_USED; Constant ADD_REALIGNER : integer := funct_need_realigner(ENABLE_INDET_BTT_SF , INCLUDE_S2MM_DRE , ENABLE_GP_SF); -- Calculates the minimum needed depth of the GP Store and Forward FIFO -- based on the S2MM pipeline depth and the max allowed Burst length Constant PIPEDEPTH_BURST_LEN_PROD : integer := (ADDR_CNTL_FIFO_DEPTH+2) * S2MM_BURST_SIZE; -- Assigns the depth of the optional GP Store and Forward FIFO to the nearest -- power of 2 Constant SF_FIFO_DEPTH : integer range 128 to 8192 := funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD); -- Calculate the width of the Store and Forward Starting Address Offset bus Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(S2MM_MDATA_WIDTH, S2MM_SDATA_WIDTH); -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0'); signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_last : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2addr_data_rdy : std_logic := '0'; signal sig_data2all_tlast_error : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2wsc_calc_error : std_logic := '0'; signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0'); signal sig_data2wsc_cmd_empty : std_logic := '0'; signal sig_data2wsc_calc_err : std_logic := '0'; signal sig_data2wsc_cmd_cmplt : std_logic := '0'; signal sig_data2wsc_last_err : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_wsc2stat_status : std_logic_vector(WSC_STATUS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2wsc_status_ready : std_logic := '0'; signal sig_wsc2stat_status_valid : std_logic := '0'; signal sig_wsc2mstr_halt_pipe : std_logic := '0'; signal sig_data2wsc_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wvalid : std_logic := '0'; signal sig_skid2data_wready : std_logic := '0'; signal sig_data2skid_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_data2skid_wlast : std_logic := '0'; signal sig_skid2axi_wvalid : std_logic := '0'; signal sig_axi2skid_wready : std_logic := '0'; signal sig_skid2axi_wdata : std_logic_vector(S2MM_MDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_skid2axi_wstrb : std_logic_vector((S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_skid2axi_wlast : std_logic := '0'; signal sig_data2wsc_sof : std_logic := '0'; signal sig_data2wsc_eof : std_logic := '0'; signal sig_data2wsc_valid : std_logic := '0'; signal sig_wsc2data_ready : std_logic := '0'; signal sig_data2wsc_eop : std_logic := '0'; signal sig_data2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_sf2pcc_xfer_valid : std_logic := '0'; signal sig_pcc2sf_xfer_ready : std_logic := '0'; signal sig_sf2pcc_cmd_cmplt : std_logic := '0'; signal sig_sf2pcc_packet_eop : std_logic := '0'; signal sig_sf2pcc_xfer_bytes : std_logic_vector(IBTT_XFER_BYTES_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tvalid : std_logic := '0'; signal sig_wdc2ibtt_tready : std_logic := '0'; signal sig_ibtt2wdc_tdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tlast : std_logic := '0'; signal sig_ibtt2wdc_eop : std_logic := '0'; signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0'); signal sig_dre2ibtt_tvalid : std_logic := '0'; signal sig_ibtt2dre_tready : std_logic := '0'; signal sig_dre2ibtt_tdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tlast : std_logic := '0'; signal sig_dre2ibtt_eop : std_logic := '0'; signal sig_dre2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2dre_cmd_valid : std_logic := '0'; signal sig_mstr2dre_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_src_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_dest_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_btt : std_logic_vector(S2MM_BTT_USED-1 downto 0) := (others => '0'); signal sig_mstr2dre_drr : std_logic := '0'; signal sig_mstr2dre_eof : std_logic := '0'; signal sig_mstr2dre_cmd_cmplt : std_logic := '0'; signal sig_mstr2dre_calc_error : std_logic := '0'; signal sig_realign2wdc_eop_error : std_logic := '0'; signal sig_dre2all_halted : std_logic := '0'; signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_wsc2rst_stop_cmplt : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal skid2dre_wvalid : std_logic := '0'; signal dre2skid_wready : std_logic := '0'; signal skid2dre_wdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal skid2dre_wstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal skid2dre_wlast : std_logic := '0'; signal sig_s2mm_allow_addr_req : std_logic := '0'; signal sig_ok_to_post_wr_addr : std_logic := '0'; signal sig_s2mm_addr_req_posted : std_logic := '0'; signal sig_s2mm_wr_xfer_cmplt : std_logic := '0'; signal sig_s2mm_ld_nxt_len : std_logic := '0'; signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_ibtt2wdc_error : std_logic := '0'; signal sig_sf_strt_addr_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal s2mm_awcache_int : std_logic_vector (3 downto 0); signal s2mm_awuser_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug/Test Port Assignments s2mm_dbg_data <= sig_dbg_data_mux_out; -- Note that only the s2mm_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (s2mm_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"CAFE1111" ; -- 32 bit Constant indicating S2MM FULL type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2wsc_status_ready; sig_dbg_data_1(7) <= sig_wsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error --sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADD_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen adds in the EOP status marker to the debug -- vector data when Indet BTT Store and Forward is enabled. -- ------------------------------------------------------------ GEN_ADD_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 1) generate begin sig_dbg_data_1(19) <= sig_wsc2stat_status(31) ; -- EOP Marker end generate GEN_ADD_DEBUG_EOP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen zeros the debug vector bit used for the EOP -- status marker when Indet BTT Store and Forward is not -- enabled. -- ------------------------------------------------------------ GEN_NO_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 0) generate begin sig_dbg_data_1(19) <= '0' ; -- EOP Marker end generate GEN_NO_DEBUG_EOP; ---- End of Debug/Test Support -------------------------------- -- Assign the Address posting control outputs s2mm_addr_req_posted <= sig_s2mm_addr_req_posted ; s2mm_wr_xfer_cmplt <= sig_s2mm_wr_xfer_cmplt ; s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len ; s2mm_wr_len <= sig_s2mm_wr_len ; -- Write Data Channel I/O s2mm_wvalid <= sig_skid2axi_wvalid; sig_axi2skid_wready <= s2mm_wready ; s2mm_wdata <= sig_skid2axi_wdata ; s2mm_wlast <= sig_skid2axi_wlast ; GEN_S2MM_TKEEP_ENABLE2 : if C_ENABLE_S2MM_TKEEP = 1 generate begin s2mm_wstrb <= sig_skid2axi_wstrb ; end generate GEN_S2MM_TKEEP_ENABLE2; GEN_S2MM_TKEEP_DISABLE2 : if C_ENABLE_S2MM_TKEEP = 0 generate begin s2mm_wstrb <= (others => '1'); end generate GEN_S2MM_TKEEP_DISABLE2; GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off s2mm_awcache <= s2mm_awcache_int; -- pre Interface-X guidelines for Masters s2mm_awuser <= s2mm_awuser_int; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= s2mm_cmd_wdata(79 downto 72); -- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE2; -- Internal error output discrete s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ) port map ( primary_aclk => s2mm_aclk , primary_aresetn => s2mm_aresetn , secondary_awclk => s2mm_cmdsts_awclk , secondary_aresetn => s2mm_cmdsts_aresetn , halt_req => s2mm_halt , halt_cmplt => s2mm_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => sig_wsc2rst_stop_cmplt , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO , C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , secondary_awclk => s2mm_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => s2mm_cmd_wvalid , cmd_wready => s2mm_cmd_wready , cmd_wdata => sig_s2mm_cmd_wdata , cache_data => sig_s2mm_cache_data , sts_wvalid => s2mm_sts_wvalid , sts_wready => s2mm_sts_wready , sts_wdata => s2mm_sts_wdata , sts_wstrb => s2mm_sts_wstrb , sts_wlast => s2mm_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_wsc2stat_status , stat2mstr_status_ready => sig_stat2wsc_status_ready , mst2stst_status_valid => sig_wsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_WR_STATUS_CNTLR -- -- Description: -- Write Status Controller Block -- ------------------------------------------------------------ I_WR_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_wr_status_cntl generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2wsc_stop_request => sig_rst2all_stop_request , wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt , addr2wsc_addr_posted => sig_addr2data_addr_posted , s2mm_bresp => s2mm_bresp , s2mm_bvalid => s2mm_bvalid , s2mm_bready => s2mm_bready , calc2wsc_calc_error => sig_calc2dm_calc_err , addr2wsc_calc_error => sig_addr2wsc_calc_error , addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_error => sig_data2wsc_calc_err , data2wsc_last_error => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , data2wsc_valid => sig_data2wsc_valid , wsc2data_ready => sig_wsc2data_ready , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2stat_status => sig_wsc2stat_status , stat2wsc_status_ready => sig_stat2wsc_status_ready , wsc2stat_status_valid => sig_wsc2stat_status_valid , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_PCC -- -- If Generate Description: -- Include the normal Predictive Command Calculator function, -- Store and Forward is not an included feature. -- -- ------------------------------------------------------------ GEN_INCLUDE_PCC : if (ENABLE_INDET_BTT_SF = 0) generate begin ------------------------------------------------------------ -- Instance: I_MSTR_PCC -- -- Description: -- Predictive Command Calculator Block -- ------------------------------------------------------------ I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc generic map ( C_IS_MM2S => IS_NOT_MM2S , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_SUPPORT_INDET_BTT => ENABLE_INDET_BTT_SF , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => open , mstr2data_dre_dest_align => open , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_PCC; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_IBTTCC -- -- If Generate Description: -- Include the Indeterminate BTT Command Calculator function, -- Store and Forward is enabled in the S2MM. -- -- ------------------------------------------------------------ GEN_INCLUDE_IBTTCC : if (ENABLE_INDET_BTT_SF = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_MSTR_SFCC -- -- Description: -- Instantiates the Store and Forward Command Calculator -- Block. -- ------------------------------------------------------------ I_S2MM_MSTR_IBTTCC : entity axi_datamover_v5_1.axi_datamover_ibttcc generic map ( C_SF_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_IBTTCC; ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate begin ------------------------------------------------------------ -- Instance: I_S2MM_STRM_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registerd Slave Stream inputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => s2mm_strm_wvalid , s_ready => s2mm_strm_wready , s_data => s2mm_strm_wdata , s_strb => s2mm_strm_wstrb , s_last => s2mm_strm_wlast , -- Master Side (Stream Data Output m_valid => skid2dre_wvalid , m_ready => dre2skid_wready , m_data => skid2dre_wdata , m_strb => skid2dre_wstrb , m_last => skid2dre_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate begin skid2dre_wvalid <= s2mm_strm_wvalid; s2mm_strm_wready <= dre2skid_wready; skid2dre_wdata <= s2mm_strm_wdata; skid2dre_wstrb <= s2mm_strm_wstrb; skid2dre_wlast <= s2mm_strm_wlast; end generate DISABLE_AXIS_SKID; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_REALIGNER -- -- If Generate Description: -- Omit the S2MM Realignment Engine -- -- ------------------------------------------------------------ GEN_NO_REALIGNER : if (ADD_REALIGNER = 0) generate begin -- Set to Always ready for DRE to PCC Command Interface sig_dre2mstr_cmd_ready <= LOGIC_HIGH; -- Without DRE and Scatter, the end of packet is the TLAST --sig_dre2ibtt_eop <= skid2dre_wlast ; sig_dre2ibtt_eop <= sig_dre2ibtt_tlast ; -- use skid buffered version -- Cant't detect undrrun/overrun here sig_realign2wdc_eop_error <= '0'; ENABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '1' generate begin ------------------------------------------------------------ -- Instance: I_NO_REALIGN_SKID_BUF -- -- Description: -- Instance for a Skid Buffer which provides for -- Fmax timing improvement between the Null Absorber and -- the Write Data controller when the Realigner is not -- present (no DRE and no Store and Forward case). -- ------------------------------------------------------------ I_NO_REALIGN_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => LOGIC_LOW , -- Slave Side (Null Absorber Input) s_valid => skid2dre_wvalid , s_ready => dre2skid_wready , s_data => skid2dre_wdata , s_strb => skid2dre_wstrb , s_last => skid2dre_wlast , -- Master Side (Stream Data Output to WData Cntlr) m_valid => sig_dre2ibtt_tvalid , m_ready => sig_ibtt2dre_tready , m_data => sig_dre2ibtt_tdata , m_strb => sig_dre2ibtt_tstrb , m_last => sig_dre2ibtt_tlast ); end generate ENABLE_NOREALIGNER_SKID; DISABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '0' generate begin sig_dre2ibtt_tvalid <= skid2dre_wvalid; dre2skid_wready <= sig_ibtt2dre_tready; sig_dre2ibtt_tdata <= skid2dre_wdata; sig_dre2ibtt_tstrb <= skid2dre_wstrb; sig_dre2ibtt_tlast <= skid2dre_wlast; end generate DISABLE_NOREALIGNER_SKID; end generate GEN_NO_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_REALIGNER -- -- If Generate Description: -- Include the S2MM realigner Module. It hosts the S2MM DRE -- and the Scatter Block. -- -- Note that the General Purpose Store and Forward Module -- needs the Scatter function to detect input overrun and -- underrun events on the AXI Stream input. Thus the Realigner -- is included whenever the GP Store and Forward is enabled. -- ------------------------------------------------------------ GEN_INCLUDE_REALIGNER : if (ADD_REALIGNER = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_REALIGNER -- -- Description: -- Instance for the S2MM Data Realignment Module. -- ------------------------------------------------------------ I_S2MM_REALIGNER : entity axi_datamover_v5_1.axi_datamover_s2mm_realign generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_INCLUDE_DRE => INCLUDE_S2MM_DRE , C_DRE_CNTL_FIFO_DEPTH => DRE_CNTL_FIFO_DEPTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SUPPORT_SCATTER => DRE_SUPPORT_SCATTER , C_BTT_USED => S2MM_BTT_USED , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , -- Write Data Controller or Store and Forward I/O ------- wdc2dre_wready => sig_ibtt2dre_tready , dre2wdc_wvalid => sig_dre2ibtt_tvalid , dre2wdc_wdata => sig_dre2ibtt_tdata , dre2wdc_wstrb => sig_dre2ibtt_tstrb , dre2wdc_wlast => sig_dre2ibtt_tlast , dre2wdc_eop => sig_dre2ibtt_eop , -- Starting offset output ------------------------------- dre2sf_strt_offset => sig_sf_strt_addr_offset , -- AXI Slave Stream In ----------------------------------- s2mm_strm_wready => dre2skid_wready , s2mm_strm_wvalid => skid2dre_wvalid , s2mm_strm_wdata => skid2dre_wdata , s2mm_strm_wstrb => skid2dre_wstrb , s2mm_strm_wlast => skid2dre_wlast , -- Command Calculator Interface -------------------------- dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset , -- Premature TLAST assertion error flag dre2all_tlast_error => sig_realign2wdc_eop_error , -- DRE Halted Status dre2all_halted => sig_dre2all_halted ); end generate GEN_INCLUDE_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT_SF -- -- If Generate Description: -- Include the Indeterminate BTT Logic with specialized -- Store and Forward function, This also requires the -- Scatter Engine in the Realigner module. -- -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT_SF : if (ENABLE_INDET_BTT_SF = 1) generate begin -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; ------------------------------------------------------------ -- Instance: I_INDET_BTT -- -- Description: -- Instance for the Indeterminate BTT with Store and Forward -- module. -- ------------------------------------------------------------ I_INDET_BTT : entity axi_datamover_v5_1.axi_datamover_indet_btt generic map ( C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_IBTT_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_ENABLE_DRE => INCLUDE_S2MM_DRE , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , ibtt2wdc_stbs_asserted => sig_ibtt2wdc_stbs_asserted, ibtt2wdc_eop => sig_ibtt2wdc_eop , ibtt2wdc_tdata => sig_ibtt2wdc_tdata , ibtt2wdc_tstrb => sig_ibtt2wdc_tstrb , ibtt2wdc_tlast => sig_ibtt2wdc_tlast , ibtt2wdc_tvalid => sig_ibtt2wdc_tvalid , wdc2ibtt_tready => sig_wdc2ibtt_tready , dre2ibtt_tvalid => sig_dre2ibtt_tvalid , ibtt2dre_tready => sig_ibtt2dre_tready , dre2ibtt_tdata => sig_dre2ibtt_tdata , dre2ibtt_tstrb => sig_dre2ibtt_tstrb , dre2ibtt_tlast => sig_dre2ibtt_tlast , dre2ibtt_eop => sig_dre2ibtt_eop , dre2ibtt_strt_addr_offset => sig_sf_strt_addr_offset , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes ); end generate GEN_ENABLE_INDET_BTT_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_SF -- -- If Generate Description: -- Bypasses any store and Forward functions. -- -- ------------------------------------------------------------ GEN_NO_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 0) generate begin -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; -- Housekeep unused signal in this case sig_ok_to_post_wr_addr <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; -- Just pass DRE signals through sig_ibtt2dre_tready <= sig_wdc2ibtt_tready ; sig_ibtt2wdc_tvalid <= sig_dre2ibtt_tvalid ; sig_ibtt2wdc_tdata <= sig_dre2ibtt_tdata ; sig_ibtt2wdc_tstrb <= sig_dre2ibtt_tstrb ; sig_ibtt2wdc_tlast <= sig_dre2ibtt_tlast ; sig_ibtt2wdc_eop <= sig_dre2ibtt_eop ; sig_ibtt2wdc_stbs_asserted <= (others => '0') ; -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; end generate GEN_NO_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_GP_SF -- -- If Generate Description: -- Include the General Purpose Store and Forward module. -- This If Generate can only be enabled when -- Indeterminate BTT mode is not enabled. The General Purpose -- Store and Forward is instantiated in place of the Indet -- BTT Store and Forward. -- ------------------------------------------------------------ GEN_INCLUDE_GP_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 1) generate begin -- Merge the external address posting control with the -- SF address posting control. sig_s2mm_allow_addr_req <= s2mm_allow_addr_req and sig_ok_to_post_wr_addr ; -- Zero these out since Indet BTT is not enabled, they -- are only used by the WDC in that mode sig_ibtt2wdc_stbs_asserted <= (others => '0') ; sig_ibtt2wdc_eop <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; ------------------------------------------------------------ -- Instance: I_S2MM_GP_SF -- -- Description: -- Instance for the S2MM (Write) General Purpose Store and -- Forward Module. This module can only be enabled when -- Indeterminate BTT mode is not enabled. It is connected -- in place of the IBTT Module when GP SF is enabled. -- ------------------------------------------------------------ I_S2MM_GP_SF : entity axi_datamover_v5_1.axi_datamover_wr_sf generic map ( C_WR_ADDR_PIPE_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset inputs ----------------------------- aclk => s2mm_aclk , reset => sig_mmap_rst , -- Slave Stream Input -------------------------------- sf2sin_tready => sig_ibtt2dre_tready , sin2sf_tvalid => sig_dre2ibtt_tvalid , sin2sf_tdata => sig_dre2ibtt_tdata , sin2sf_tkeep => sig_dre2ibtt_tstrb , sin2sf_tlast => sig_dre2ibtt_tlast , sin2sf_error => sig_realign2wdc_eop_error , -- Starting Address Offset Input --------------------- sin2sf_strt_addr_offset => sig_sf_strt_addr_offset , -- DataMover Write Side Address Pipelining Control Interface -------- ok_to_post_wr_addr => sig_ok_to_post_wr_addr , wr_addr_posted => sig_s2mm_addr_req_posted , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , wr_ld_nxt_len => sig_s2mm_ld_nxt_len , wr_len => sig_s2mm_wr_len , -- Write Side Stream Out to DataMover S2MM ------------- sout2sf_tready => sig_wdc2ibtt_tready , sf2sout_tvalid => sig_ibtt2wdc_tvalid , sf2sout_tdata => sig_ibtt2wdc_tdata , sf2sout_tkeep => sig_ibtt2wdc_tstrb , sf2sout_tlast => sig_ibtt2wdc_tlast , sf2sout_error => sig_ibtt2wdc_error ); end generate GEN_INCLUDE_GP_SF; ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl generic map ( C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_ADDR_ID => S2MM_AWID_VALUE , C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => s2mm_awid , addr2axi_aaddr => s2mm_awaddr , addr2axi_alen => s2mm_awlen , addr2axi_asize => s2mm_awsize , addr2axi_aburst => s2mm_awburst , addr2axi_aprot => s2mm_awprot , addr2axi_avalid => s2mm_awvalid , addr2axi_acache => s2mm_awcache_int , addr2axi_auser => s2mm_awuser_int , axi2addr_aready => s2mm_awready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , -- mstr2addr_cache_info => sig_cache2mstr_command , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => sig_s2mm_allow_addr_req , addr_req_posted => sig_s2mm_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2wsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_WR_DATA_CNTL -- -- Description: -- Write Data Controller Block -- ------------------------------------------------------------ I_WR_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_wrdata_cntl generic map ( C_REALIGNER_INCLUDED => ADD_REALIGNER , C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len , s2mm_wr_len => sig_s2mm_wr_len , data2skid_saddr_lsb => sig_data2skid_addr_lsb , data2skid_wdata => sig_data2skid_wdata , data2skid_wstrb => sig_data2skid_wstrb , data2skid_wlast => sig_data2skid_wlast , data2skid_wvalid => sig_data2skid_wvalid , skid2data_wready => sig_skid2data_wready , s2mm_strm_wvalid => sig_ibtt2wdc_tvalid , s2mm_strm_wready => sig_wdc2ibtt_tready , s2mm_strm_wdata => sig_ibtt2wdc_tdata , s2mm_strm_wstrb => sig_ibtt2wdc_tstrb , s2mm_strm_wlast => sig_ibtt2wdc_tlast , s2mm_strm_eop => sig_ibtt2wdc_eop , s2mm_stbs_asserted => sig_ibtt2wdc_stbs_asserted, realign2wdc_eop_error => sig_ibtt2wdc_error , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2all_tlast_error => sig_data2all_tlast_error , data2all_dcntlr_halted => sig_data2all_dcntlr_halted, data2skid_halt => sig_data2skid_halt , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_err => sig_data2wsc_calc_err , data2wsc_last_err => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , wsc2data_ready => sig_wsc2data_ready , data2wsc_valid => sig_data2wsc_valid , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); --ENABLE_AXIMMAP_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate --begin ------------------------------------------------------------ -- Instance: I_S2MM_MMAP_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registered outputs and supports bi-dir throttling. -- -- This Module also provides Write Data Bus Mirroring and WSTRB -- Demuxing to match a narrow Stream to a wider MMap Write -- Channel. By doing this in the skid buffer, the resource -- utilization of the skid buffer can be minimized by only -- having to buffer/mux the Stream data width, not the MMap -- Data width. -- ------------------------------------------------------------ I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid2mm_buf generic map ( C_MDATA_WIDTH => S2MM_MDATA_WIDTH , C_SDATA_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH ) port map ( -- System Ports ACLK => s2mm_aclk , ARST => sig_stream_rst , -- Slave Side (Wr Data Controller Input Side ) S_ADDR_LSB => sig_data2skid_addr_lsb, S_VALID => sig_data2skid_wvalid , S_READY => sig_skid2data_wready , S_Data => sig_data2skid_wdata , S_STRB => sig_data2skid_wstrb , S_Last => sig_data2skid_wlast , -- Master Side (MMap Write Data Output Side) M_VALID => sig_skid2axi_wvalid , M_READY => sig_axi2skid_wready , M_Data => sig_skid2axi_wdata , M_STRB => sig_skid2axi_wstrb , M_Last => sig_skid2axi_wlast ); --end generate ENABLE_AXIMMAP_SKID; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/FIFO_image_filter_img_0_data_stream_1_V.vhd

4

4629

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_img_0_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_img_0_data_stream_1_V_shiftReg; architecture rtl of FIFO_image_filter_img_0_data_stream_1_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_img_0_data_stream_1_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_img_0_data_stream_1_V is component FIFO_image_filter_img_0_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_img_0_data_stream_1_V_shiftReg : FIFO_image_filter_img_0_data_stream_1_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_skid_buf.vhd

12

16812

-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_skid_buf.vhd -- -- Description: -- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- entity axi_dma_skid_buf is generic ( C_WDATA_WIDTH : INTEGER range 8 to 256 := 32 -- Width of the Stream Data bus (in bits) ); port ( -- System Ports ACLK : In std_logic ; -- ARST : In std_logic ; -- -- -- Shutdown control (assert for 1 clk pulse) -- skid_stop : In std_logic ; -- -- Slave Side (Stream Data Input) -- S_VALID : In std_logic ; -- S_READY : Out std_logic ; -- S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); -- S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); -- S_Last : In std_logic ; -- -- -- Master Side (Stream Data Output -- M_VALID : Out std_logic ; -- M_READY : In std_logic ; -- M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); -- M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); -- M_Last : Out std_logic -- ); end entity axi_dma_skid_buf; architecture implementation of axi_dma_skid_buf is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Signals decalrations ------------------------- Signal sig_reset_reg : std_logic := '0'; signal sig_spcl_s_ready_set : std_logic := '0'; signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_skid_reg : std_logic := '0'; signal sig_skid_reg_en : std_logic := '0'; signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_skid_mux_out : std_logic := '0'; signal sig_skid_mux_sel : std_logic := '0'; signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_last_reg_out : std_logic := '0'; signal sig_data_reg_out_en : std_logic := '0'; signal sig_m_valid_out : std_logic := '0'; signal sig_m_valid_dup : std_logic := '0'; signal sig_m_valid_comb : std_logic := '0'; signal sig_s_ready_out : std_logic := '0'; signal sig_s_ready_dup : std_logic := '0'; signal sig_s_ready_comb : std_logic := '0'; signal sig_stop_request : std_logic := '0'; signal sig_stopped : std_logic := '0'; signal sig_sready_stop : std_logic := '0'; signal sig_sready_stop_reg : std_logic := '0'; signal sig_s_last_xfered : std_logic := '0'; signal sig_m_last_xfered : std_logic := '0'; signal sig_mvalid_stop_reg : std_logic := '0'; signal sig_mvalid_stop : std_logic := '0'; signal sig_slast_with_stop : std_logic := '0'; signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0'); -- Register duplication attribute assignments to control fanout -- on handshake output signals Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no"; begin --(architecture implementation) M_VALID <= sig_m_valid_out; S_READY <= sig_s_ready_out; M_STRB <= sig_strb_reg_out; M_Last <= sig_last_reg_out; M_Data <= sig_data_reg_out; -- Special shutdown logic version od Slast. -- A halt request forces a tlast through the skig buffer sig_slast_with_stop <= s_last or sig_stop_request; sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask; -- Assign the special S_READY FLOP set signal sig_spcl_s_ready_set <= sig_reset_reg; -- Generate the ouput register load enable control sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup); -- Generate the skid input register load enable control sig_skid_reg_en <= sig_s_ready_dup; -- Generate the skid mux select control sig_skid_mux_sel <= not(sig_s_ready_dup); -- Skid Mux sig_data_skid_mux_out <= sig_data_skid_reg When (sig_skid_mux_sel = '1') Else S_Data; sig_strb_skid_mux_out <= sig_strb_skid_reg When (sig_skid_mux_sel = '1') Else sig_sstrb_with_stop; sig_last_skid_mux_out <= sig_last_skid_reg When (sig_skid_mux_sel = '1') Else sig_slast_with_stop; -- m_valid combinational logic sig_m_valid_comb <= S_VALID or (sig_m_valid_dup and (not(sig_s_ready_dup) or not(M_READY))); -- s_ready combinational logic sig_s_ready_comb <= M_READY or (sig_s_ready_dup and (not(sig_m_valid_dup) or not(S_VALID))); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_THE_RST -- -- Process Description: -- Register input reset -- ------------------------------------------------------------- REG_THE_RST : process (ACLK) begin if (ACLK'event and ACLK = '1') then sig_reset_reg <= ARST; end if; end process REG_THE_RST; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: S_READY_FLOP -- -- Process Description: -- Registers S_READY handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- S_READY_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1' or sig_sready_stop = '1') then -- Special stop condition sig_s_ready_out <= '0'; sig_s_ready_dup <= '0'; Elsif (sig_spcl_s_ready_set = '1') Then sig_s_ready_out <= '1'; sig_s_ready_dup <= '1'; else sig_s_ready_out <= sig_s_ready_comb; sig_s_ready_dup <= sig_s_ready_comb; end if; end if; end process S_READY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: M_VALID_FLOP -- -- Process Description: -- Registers M_VALID handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- M_VALID_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1' or sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA sig_mvalid_stop = '1') then -- Special stop condition sig_m_valid_out <= '0'; sig_m_valid_dup <= '0'; else sig_m_valid_out <= sig_m_valid_comb; sig_m_valid_dup <= sig_m_valid_comb; end if; end if; end process M_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_REG -- -- Process Description: -- This process implements the output registers for the -- Skid Buffer Data signals -- ------------------------------------------------------------- SKID_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_data_skid_reg <= (others => '0'); sig_strb_skid_reg <= (others => '0'); sig_last_skid_reg <= '0'; elsif (sig_skid_reg_en = '1') then sig_data_skid_reg <= S_Data; sig_strb_skid_reg <= sig_sstrb_with_stop; sig_last_skid_reg <= sig_slast_with_stop; else null; -- hold current state end if; end if; end process SKID_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_REG -- -- Process Description: -- This process implements the output registers for the -- Skid Buffer Data signals -- ------------------------------------------------------------- OUTPUT_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1' or sig_mvalid_stop_reg = '1') then --sig_data_reg_out <= (others => '0'); -- CR585409 sig_strb_reg_out <= (others => '0'); sig_last_reg_out <= '0'; elsif (sig_data_reg_out_en = '1') then --sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409 sig_strb_reg_out <= sig_strb_skid_mux_out; sig_last_reg_out <= sig_last_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_REG; -- CR585409 - To lower reset fanout and improve FPGA fmax timing -- resets have been removed from AXI Stream data buses DATA_OUTPUT_REG : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (sig_data_reg_out_en = '1') then sig_data_reg_out <= sig_data_skid_mux_out; else null; -- hold current state end if; end if; end process DATA_OUTPUT_REG; -------- Special Stop Logic -------------------------------------- sig_s_last_xfered <= sig_s_ready_dup and s_valid and sig_slast_with_stop; sig_sready_stop <= (sig_s_last_xfered and sig_stop_request) or sig_sready_stop_reg; sig_m_last_xfered <= sig_m_valid_dup and m_ready and sig_last_reg_out; sig_mvalid_stop <= (sig_m_last_xfered and sig_stop_request) or sig_mvalid_stop_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_STOP_REQ_FLOP -- -- Process Description: -- This process implements the Stop request flop. It is a -- sample and hold register that can only be cleared by reset. -- ------------------------------------------------------------- IMP_STOP_REQ_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_stop_request <= '0'; sig_sstrb_stop_mask <= (others => '0'); elsif (skid_stop = '1') then sig_stop_request <= '1'; sig_sstrb_stop_mask <= (others => '1'); else null; -- hold current state end if; end if; end process IMP_STOP_REQ_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CLR_SREADY_FLOP -- -- Process Description: -- This process implements the flag to clear the s_ready -- flop at a stop condition. -- ------------------------------------------------------------- IMP_CLR_SREADY_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_sready_stop_reg <= '0'; elsif (sig_s_last_xfered = '1' and sig_stop_request = '1') then sig_sready_stop_reg <= '1'; else null; -- hold current state end if; end if; end process IMP_CLR_SREADY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CLR_MREADY_FLOP -- -- Process Description: -- This process implements the flag to clear the m_ready -- flop at a stop condition. -- ------------------------------------------------------------- IMP_CLR_MVALID_FLOP : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARST = '1') then sig_mvalid_stop_reg <= '0'; elsif (sig_m_last_xfered = '1' and sig_stop_request = '1') then sig_mvalid_stop_reg <= '1'; else null; -- hold current state end if; end if; end process IMP_CLR_MVALID_FLOP; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/checkbit_handler.vhd

7

25695

------------------------------------------------------------------------------- -- checkbit_handler.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: checkbit_handler.vhd -- -- Description: Generates the ECC checkbits for the input vector of data bits. -- -- VHDL-Standard: VHDL'93/02 ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity checkbit_handler is generic ( C_ENCODE : boolean := true; C_USE_LUT6 : boolean := true ); port ( DataIn : in std_logic_vector(0 to 31); --- changed from 31 downto 0 to 0 to 31 to make it compatabile with LMB Controller's hamming code. CheckIn : in std_logic_vector(0 to 6); CheckOut : out std_logic_vector(0 to 6); Syndrome : out std_logic_vector(0 to 6); Syndrome_4 : out std_logic_vector (0 to 1); Syndrome_6 : out std_logic_vector (0 to 5); Syndrome_Chk : in std_logic_vector (0 to 6); Enable_ECC : in std_logic; UE_Q : in std_logic; CE_Q : in std_logic; UE : out std_logic; CE : out std_logic ); end entity checkbit_handler; library unisim; use unisim.vcomponents.all; architecture IMP of checkbit_handler is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; component XOR18 is generic ( C_USE_LUT6 : boolean); port ( InA : in std_logic_vector(0 to 17); res : out std_logic); end component XOR18; component Parity is generic ( C_USE_LUT6 : boolean; C_SIZE : integer); port ( InA : in std_logic_vector(0 to C_SIZE - 1); Res : out std_logic); end component Parity; signal data_chk0 : std_logic_vector(0 to 17); signal data_chk1 : std_logic_vector(0 to 17); signal data_chk2 : std_logic_vector(0 to 17); signal data_chk3 : std_logic_vector(0 to 14); signal data_chk4 : std_logic_vector(0 to 14); signal data_chk5 : std_logic_vector(0 to 5); begin -- architecture IMP data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) & DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) & DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30); data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) & DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) & DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31); data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31); data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25); data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25); data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31); -- Encode bits for writing data Encode_Bits : if (C_ENCODE) generate signal data_chk3_i : std_logic_vector(0 to 17); signal data_chk4_i : std_logic_vector(0 to 17); signal data_chk6 : std_logic_vector(0 to 17); begin ------------------------------------------------------------------------------------------------ -- Checkbit 0 built up using XOR18 ------------------------------------------------------------------------------------------------ XOR18_I0 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk0, -- [in std_logic_vector(0 to 17)] res => CheckOut(0)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 1 built up using XOR18 ------------------------------------------------------------------------------------------------ XOR18_I1 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk1, -- [in std_logic_vector(0 to 17)] res => CheckOut(1)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 2 built up using XOR18 ------------------------------------------------------------------------------------------------ XOR18_I2 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk2, -- [in std_logic_vector(0 to 17)] res => CheckOut(2)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 3 built up using XOR18 ------------------------------------------------------------------------------------------------ data_chk3_i <= data_chk3 & "000"; XOR18_I3 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk3_i, -- [in std_logic_vector(0 to 17)] res => CheckOut(3)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 4 built up using XOR18 ------------------------------------------------------------------------------------------------ data_chk4_i <= data_chk4 & "000"; XOR18_I4 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk4_i, -- [in std_logic_vector(0 to 17)] res => CheckOut(4)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 5 built up from 1 LUT6 ------------------------------------------------------------------------------------------------ Parity_chk5_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => CheckOut(5)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 6 built up from 3 LUT7 and 4 LUT6 ------------------------------------------------------------------------------------------------ data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) & DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29); XOR18_I6 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk6, -- [in std_logic_vector(0 to 17)] res => CheckOut(6)); -- [out std_logic] end generate Encode_Bits; -------------------------------------------------------------------------------------------------- -- Decode bits to get syndrome and UE/CE signals -------------------------------------------------------------------------------------------------- Decode_Bits : if (not C_ENCODE) generate signal syndrome_i : std_logic_vector(0 to 6) := (others => '0'); signal chk0_1 : std_logic_vector(0 to 3); signal chk1_1 : std_logic_vector(0 to 3); signal chk2_1 : std_logic_vector(0 to 3); signal data_chk3_i : std_logic_vector(0 to 15); signal chk3_1 : std_logic_vector(0 to 1); signal data_chk4_i : std_logic_vector(0 to 15); signal chk4_1 : std_logic_vector(0 to 1); signal data_chk5_i : std_logic_vector(0 to 6); signal data_chk6 : std_logic_vector(0 to 38); signal chk6_1 : std_logic_vector(0 to 5); signal syndrome_0_to_2 : std_logic_vector (0 to 2); signal syndrome_3_to_5 : std_logic_vector (3 to 5); signal syndrome_3_to_5_multi : std_logic; signal syndrome_3_to_5_zero : std_logic; signal ue_i_0 : std_logic; signal ue_i_1 : std_logic; begin ------------------------------------------------------------------------------------------------ -- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4 ------------------------------------------------------------------------------------------------ chk0_1(3) <= CheckIn(0); Parity_chk0_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(0)); -- [out std_logic] Parity_chk0_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(1)); -- [out std_logic] Parity_chk0_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(2)); -- [out std_logic] Parity_chk0_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4) port map ( InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(0)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4 ------------------------------------------------------------------------------------------------ chk1_1(3) <= CheckIn(1); Parity_chk1_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(0)); -- [out std_logic] Parity_chk1_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(1)); -- [out std_logic] Parity_chk1_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(2)); -- [out std_logic] Parity_chk1_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4) port map ( InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(1)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4 ------------------------------------------------------------------------------------------------ chk2_1(3) <= CheckIn(2); Parity_chk2_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(0)); -- [out std_logic] Parity_chk2_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(1)); -- [out std_logic] Parity_chk2_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(2)); -- [out std_logic] Parity_chk2_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4) port map ( InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(2)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2 ------------------------------------------------------------------------------------------------ data_chk3_i <= data_chk3 & CheckIn(3); Parity_chk3_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk3_1(0)); -- [out std_logic] Parity_chk3_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk3_1(1)); -- [out std_logic] -- For improved timing, remove Enable_ECC signal in this LUT level Parity_chk3_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2) port map ( InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(3)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2 ------------------------------------------------------------------------------------------------ data_chk4_i <= data_chk4 & CheckIn(4); Parity_chk4_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk4_1(0)); -- [out std_logic] Parity_chk4_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk4_1(1)); -- [out std_logic] -- Set bit 4 output with default. Real ECC XOR value will be determined post register -- stage. syndrome_i (4) <= '0'; -- For improved timing, move last LUT level XOR to next side of pipeline -- stage in read path. Syndrome_4 <= chk4_1; ------------------------------------------------------------------------------------------------ -- Syndrome bit 5 built up from 1 LUT7 ------------------------------------------------------------------------------------------------ data_chk5_i <= data_chk5 & CheckIn(5); Parity_chk5_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(5)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6 ------------------------------------------------------------------------------------------------ data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) & CheckIn(1) & CheckIn(0) & CheckIn(6); Parity_chk6_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(0)); -- [out std_logic] Parity_chk6_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(1)); -- [out std_logic] Parity_chk6_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(2)); -- [out std_logic] Parity_chk6_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(3)); -- [out std_logic] Parity_chk6_5 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(4)); -- [out std_logic] Parity_chk6_6 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(5)); -- [out std_logic] -- No internal use for MSB of syndrome (it is created after the -- register stage, outside of this block) syndrome_i(6) <= '0'; Syndrome <= syndrome_i; -- (N:0) <= (0:N) -- Bring out seperate output to do final XOR stage on Syndrome (6) after -- the pipeline stage. Syndrome_6 <= chk6_1 (0 to 5); --------------------------------------------------------------------------- -- With final syndrome registered outside this module for pipeline balancing -- Use registered syndrome to generate any error flags. -- Use input signal, Syndrome_Chk which is the registered Syndrome used to -- correct any single bit errors. syndrome_0_to_2 <= Syndrome_Chk(0) & Syndrome_Chk(1) & Syndrome_Chk(2); syndrome_3_to_5 <= Syndrome_Chk(3) & Syndrome_Chk(4) & Syndrome_Chk(5); syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0'; syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or syndrome_3_to_5 = "011" or syndrome_3_to_5 = "101") else '0'; -- Ensure that CE flag is only asserted for a single clock cycle (and does not keep -- registered output value) CE <= (Enable_ECC and Syndrome_Chk(6)) when (syndrome_3_to_5_multi = '0') else '0'; -- Similar edit from CE flag. Ensure that UE flags are only asserted for a single -- clock cycle. The flags are registered outside this module for detection in -- register module. ue_i_0 <= Enable_ECC when (syndrome_3_to_5_zero = '0') or (syndrome_0_to_2 /= "000") else '0'; ue_i_1 <= Enable_ECC and (syndrome_3_to_5_multi); Use_LUT6: if (C_USE_LUT6) generate begin UE_MUXF7 : MUXF7 port map ( I0 => ue_i_0, I1 => ue_i_1, S => Syndrome_Chk(6), O => UE); end generate Use_LUT6; Use_RTL: if (not C_USE_LUT6) generate begin UE <= ue_i_1 when Syndrome_Chk(6) = '1' else ue_i_0; end generate Use_RTL; end generate Decode_Bits; end architecture IMP;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/daf00b91/hdl/src/vhdl/axi_lite_ipif.vhd

16

14520

------------------------------------------------------------------- -- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------------- -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: axi_lite_ipif.vhd -- Version: v2.0 -- Description: This is the top level design file for the axi_lite_ipif -- function. It provides a standardized slave interface -- between the IP and the AXI. This version supports -- single read/write transfers only. It does not provide -- address pipelining or simultaneous read and write -- operations. ------------------------------------------------------------------------------- -- Structure: This section shows the hierarchical structure of axi_lite_ipif. -- -- --axi_lite_ipif.vhd -- --slave_attachment.vhd -- --address_decoder.vhd ------------------------------------------------------------------------------- -- Author: BSB -- -- History: -- -- BSB 05/20/10 -- First version -- ~~~~~~ -- - Created the first version v1.00.a -- ^^^^^^ -- ~~~~~~ -- SK 06/09/10 -- v1.01.a -- 1. updated to reduce the utilization -- Closed CR #574507 -- 2. Optimized the state machine code -- 3. Optimized the address decoder logic to generate the CE's with common logic -- 4. Address GAP decoding logic is removed and timeout counter is made active -- for all transactions. -- ^^^^^^ -- ~~~~~~ -- SK 12/16/12 -- v2.0 -- 1. up reved to major version for 2013.1 Vivado release. No logic updates. -- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format -- 3. updated the proc common version to proc_common_base_v5_0 -- 4. No Logic Updates -- ^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; --library proc_common_base_v5_0; --use proc_common_base_v5_0.ipif_pkg.all; library axi_lite_ipif_v3_0; use axi_lite_ipif_v3_0.ipif_pkg.all; ------------------------------------------------------------------------------- -- Definition of Generics ------------------------------------------------------------------------------- -- C_S_AXI_DATA_WIDTH -- AXI data bus width -- C_S_AXI_ADDR_WIDTH -- AXI address bus width -- C_S_AXI_MIN_SIZE -- Minimum address range of the IP -- C_USE_WSTRB -- Use write strobs or not -- C_DPHASE_TIMEOUT -- Data phase time out counter -- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range -- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range -- C_FAMILY -- Target FPGA family ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- -- S_AXI_ACLK -- AXI Clock -- S_AXI_ARESETN -- AXI Reset -- S_AXI_AWADDR -- AXI Write address -- S_AXI_AWVALID -- Write address valid -- S_AXI_AWREADY -- Write address ready -- S_AXI_WDATA -- Write data -- S_AXI_WSTRB -- Write strobes -- S_AXI_WVALID -- Write valid -- S_AXI_WREADY -- Write ready -- S_AXI_BRESP -- Write response -- S_AXI_BVALID -- Write response valid -- S_AXI_BREADY -- Response ready -- S_AXI_ARADDR -- Read address -- S_AXI_ARVALID -- Read address valid -- S_AXI_ARREADY -- Read address ready -- S_AXI_RDATA -- Read data -- S_AXI_RRESP -- Read response -- S_AXI_RVALID -- Read valid -- S_AXI_RREADY -- Read ready -- Bus2IP_Clk -- Synchronization clock provided to User IP -- Bus2IP_Reset -- Active high reset for use by the User IP -- Bus2IP_Addr -- Desired address of read or write operation -- Bus2IP_RNW -- Read or write indicator for the transaction -- Bus2IP_BE -- Byte enables for the data bus -- Bus2IP_CS -- Chip select for the transcations -- Bus2IP_RdCE -- Chip enables for the read -- Bus2IP_WrCE -- Chip enables for the write -- Bus2IP_Data -- Write data bus to the User IP -- IP2Bus_Data -- Input Read Data bus from the User IP -- IP2Bus_WrAck -- Active high Write Data qualifier from the IP -- IP2Bus_RdAck -- Active high Read Data qualifier from the IP -- IP2Bus_Error -- Error signal from the IP ------------------------------------------------------------------------------- entity axi_lite_ipif is generic ( C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; C_USE_WSTRB : integer := 0; C_DPHASE_TIMEOUT : integer range 0 to 512 := 8; C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used ( X"0000_0000_7000_0000", -- IP user0 base address X"0000_0000_7000_00FF", -- IP user0 high address X"0000_0000_7000_0100", -- IP user1 base address X"0000_0000_7000_01FF" -- IP user1 high address ); C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used ( 4, -- User0 CE Number 12 -- User1 CE Number ); C_FAMILY : string := "virtex6" ); port ( --System signals S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector ((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- Controls to the IP/IPIF modules Bus2IP_Clk : out std_logic; Bus2IP_Resetn : out std_logic; Bus2IP_Addr : out std_logic_vector ((C_S_AXI_ADDR_WIDTH-1) downto 0); Bus2IP_RNW : out std_logic; Bus2IP_BE : out std_logic_vector (((C_S_AXI_DATA_WIDTH/8)-1) downto 0); Bus2IP_CS : out std_logic_vector (((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0); Bus2IP_RdCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0); Bus2IP_WrCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0); Bus2IP_Data : out std_logic_vector ((C_S_AXI_DATA_WIDTH-1) downto 0); IP2Bus_Data : in std_logic_vector ((C_S_AXI_DATA_WIDTH-1) downto 0); IP2Bus_WrAck : in std_logic; IP2Bus_RdAck : in std_logic; IP2Bus_Error : in std_logic ); end axi_lite_ipif; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture imp of axi_lite_ipif is ---------------------------------------------------------------------------------- -- below attributes are added to reduce the synth warnings in Vivado tool attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ---------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Slave Attachment ------------------------------------------------------------------------------- I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0.slave_attachment generic map( C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH, C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, C_FAMILY => C_FAMILY ) port map( -- AXI signals S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_RREADY => S_AXI_RREADY, -- IPIC signals Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Resetn => Bus2IP_Resetn, Bus2IP_Addr => Bus2IP_Addr, Bus2IP_RNW => Bus2IP_RNW, Bus2IP_BE => Bus2IP_BE, Bus2IP_CS => Bus2IP_CS, Bus2IP_RdCE => Bus2IP_RdCE, Bus2IP_WrCE => Bus2IP_WrCE, Bus2IP_Data => Bus2IP_Data, IP2Bus_Data => IP2Bus_Data, IP2Bus_WrAck => IP2Bus_WrAck, IP2Bus_RdAck => IP2Bus_RdAck, IP2Bus_Error => IP2Bus_Error ); end imp;

gpl-3.0

mistryalok/Zedboard

learning/training/my/adder/hls/adder/solution1/syn/vhdl/adder_AXI_CTRL_s_axi.vhd

1

13809

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity adder_AXI_CTRL_s_axi is generic ( C_ADDR_WIDTH : INTEGER := 6; C_DATA_WIDTH : INTEGER := 32); port ( -- axi4 lite slave signals ACLK :in STD_LOGIC; ARESET :in STD_LOGIC; ACLK_EN :in STD_LOGIC; AWADDR :in STD_LOGIC_VECTOR(C_ADDR_WIDTH-1 downto 0); AWVALID :in STD_LOGIC; AWREADY :out STD_LOGIC; WDATA :in STD_LOGIC_VECTOR(C_DATA_WIDTH-1 downto 0); WSTRB :in STD_LOGIC_VECTOR(C_DATA_WIDTH/8-1 downto 0); WVALID :in STD_LOGIC; WREADY :out STD_LOGIC; BRESP :out STD_LOGIC_VECTOR(1 downto 0); BVALID :out STD_LOGIC; BREADY :in STD_LOGIC; ARADDR :in STD_LOGIC_VECTOR(C_ADDR_WIDTH-1 downto 0); ARVALID :in STD_LOGIC; ARREADY :out STD_LOGIC; RDATA :out STD_LOGIC_VECTOR(C_DATA_WIDTH-1 downto 0); RRESP :out STD_LOGIC_VECTOR(1 downto 0); RVALID :out STD_LOGIC; RREADY :in STD_LOGIC; interrupt :out STD_LOGIC; -- user signals ap_start :out STD_LOGIC; ap_done :in STD_LOGIC; ap_ready :in STD_LOGIC; ap_idle :in STD_LOGIC; a :out STD_LOGIC_VECTOR(31 downto 0); b :out STD_LOGIC_VECTOR(31 downto 0); c :in STD_LOGIC_VECTOR(31 downto 0); c_ap_vld :in STD_LOGIC); end entity adder_AXI_CTRL_s_axi; --------------------------Address Info------------------- -- 0x00 : Control signals -- bit 0 - ap_start (Read/Write/SC) -- bit 1 - ap_done (Read/COR) -- bit 2 - ap_idle (Read) -- bit 3 - ap_ready (Read) -- bit 7 - auto_restart (Read/Write) -- others - reserved -- 0x04 : Global Interrupt Enable Register -- bit 0 - Global Interrupt Enable (Read/Write) -- others - reserved -- 0x08 : IP Interrupt Enable Register (Read/Write) -- bit 0 - Channel 0 (ap_done) -- others - reserved -- 0x0c : IP Interrupt Status Register (Read/TOW) -- bit 0 - Channel 0 (ap_done) -- others - reserved -- 0x10 : Data signal of a -- bit 31~0 - a[31:0] (Read/Write) -- 0x14 : reserved -- 0x18 : Data signal of b -- bit 31~0 - b[31:0] (Read/Write) -- 0x1c : reserved -- 0x20 : Data signal of c -- bit 31~0 - c[31:0] (Read) -- 0x24 : Control signal of c -- bit 0 - c_ap_vld (Read/COR) -- others - reserved -- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) architecture behave of adder_AXI_CTRL_s_axi is constant ADDR_BITS : INTEGER := 6; constant ADDR_AP_CTRL : INTEGER :=16#00#; constant ADDR_GIE : INTEGER :=16#04#; constant ADDR_IER : INTEGER :=16#08#; constant ADDR_ISR : INTEGER :=16#0c#; constant ADDR_A_DATA_0 : INTEGER :=16#10#; constant ADDR_A_CTRL : INTEGER :=16#14#; constant ADDR_B_DATA_0 : INTEGER :=16#18#; constant ADDR_B_CTRL : INTEGER :=16#1c#; constant ADDR_C_DATA_0 : INTEGER :=16#20#; constant ADDR_C_CTRL : INTEGER :=16#24#; type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write FSM states signal wstate, wnext, rstate, rnext: states; -- Local signal signal waddr : UNSIGNED(ADDR_BITS-1 downto 0); signal wmask : UNSIGNED(31 downto 0); signal aw_hs : STD_LOGIC; signal w_hs : STD_LOGIC; signal rdata_data : UNSIGNED(31 downto 0); signal ar_hs : STD_LOGIC; signal raddr : UNSIGNED(ADDR_BITS-1 downto 0); signal AWREADY_t : STD_LOGIC; signal WREADY_t : STD_LOGIC; signal ARREADY_t : STD_LOGIC; signal RVALID_t : STD_LOGIC; -- internal registers signal int_ap_idle : STD_LOGIC; signal int_ap_ready : STD_LOGIC; signal int_ap_done : STD_LOGIC; signal int_ap_start : STD_LOGIC; signal int_auto_restart : STD_LOGIC; signal int_gie : STD_LOGIC; signal int_ier : STD_LOGIC; signal int_isr : STD_LOGIC; signal int_a : UNSIGNED(31 downto 0); signal int_b : UNSIGNED(31 downto 0); signal int_c : UNSIGNED(31 downto 0); signal int_c_ap_vld : STD_LOGIC; begin -- axi write AWREADY_t <= '1' when wstate = wridle else '0'; AWREADY <= AWREADY_t; WREADY_t <= '1' when wstate = wrdata else '0'; WREADY <= WREADY_t; BRESP <= "00"; -- OKAY BVALID <= '1' when wstate = wrresp else '0'; wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0)); aw_hs <= AWVALID and AWREADY_t; w_hs <= WVALID and WREADY_t; -- write FSM process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (ARESET = '1') then wstate <= wridle; else wstate <= wnext; end if; end if; end process; process (wstate, AWVALID, WVALID, BREADY) begin case (wstate) is when wridle => if (AWVALID = '1') then wnext <= wrdata; else wnext <= wridle; end if; when wrdata => if (WVALID = '1') then wnext <= wrresp; else wnext <= wrdata; end if; when wrresp => if (BREADY = '1') then wnext <= wridle; else wnext <= wrresp; end if; when others => wnext <= wridle; end case; end process; waddr_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (aw_hs = '1') then waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)); end if; end if; end process; -- axi read ARREADY_t <= '1' when (rstate = rdidle) else '0'; ARREADY <= ARREADY_t; RDATA <= STD_LOGIC_VECTOR(rdata_data); RRESP <= "00"; -- OKAY RVALID_t <= '1' when (rstate = rddata) else '0'; RVALID <= RVALID_t; ar_hs <= ARVALID and ARREADY_t; raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0)); -- read FSM process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (ARESET = '1') then rstate <= rdidle; else rstate <= rnext; end if; end if; end process; process (rstate, ARVALID, RREADY, RVALID_t) begin case (rstate) is when rdidle => if (ARVALID = '1') then rnext <= rddata; else rnext <= rdidle; end if; when rddata => if (RREADY = '1' and RVALID_t = '1') then rnext <= rdidle; else rnext <= rddata; end if; when others => rnext <= rdidle; end case; end process; rdata_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (ar_hs = '1') then case (TO_INTEGER(raddr)) is when ADDR_AP_CTRL => rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0'); when ADDR_GIE => rdata_data <= (1 => int_gie, others => '0'); when ADDR_IER => rdata_data <= (1 => int_ier, others => '0'); when ADDR_ISR => rdata_data <= (1 => int_isr, others => '0'); when ADDR_A_DATA_0 => rdata_data <= RESIZE(int_a(31 downto 0), 32); when ADDR_B_DATA_0 => rdata_data <= RESIZE(int_b(31 downto 0), 32); when ADDR_C_DATA_0 => rdata_data <= RESIZE(int_c(31 downto 0), 32); when ADDR_C_CTRL => rdata_data <= (0 => int_c_ap_vld, others => '0'); when others => rdata_data <= (others => '0'); end case; end if; end if; end process; -- internal registers interrupt <= int_gie and int_isr; ap_start <= int_ap_start; int_ap_idle <= ap_idle; int_ap_ready <= ap_ready; a <= STD_LOGIC_VECTOR(int_a); b <= STD_LOGIC_VECTOR(int_b); process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_start <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then int_ap_start <= '1'; elsif (ap_done = '1' and int_auto_restart = '1') then int_ap_start <= '1'; -- auto restart else int_ap_start <= '0'; -- self clear end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_done <= '0'; elsif (ACLK_EN = '1') then if (ap_done = '1') then int_ap_done <= '1'; elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then int_ap_done <= '0'; -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_auto_restart <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then int_auto_restart <= WDATA(7); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_gie <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then int_gie <= WDATA(0); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ier <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then int_ier <= WDATA(0); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr <= '0'; elsif (ACLK_EN = '1') then if (int_ier = '1' and ap_done = '1') then int_isr <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr <= int_isr xor WDATA(0); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_A_DATA_0) then int_a(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_a(31 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_B_DATA_0) then int_b(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_b(31 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_c <= (others => '0'); elsif (ACLK_EN = '1') then if (c_ap_vld = '1') then int_c <= UNSIGNED(c); -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_c_ap_vld <= '0'; elsif (ACLK_EN = '1') then if (c_ap_vld = '1') then int_c_ap_vld <= '1'; elsif (ar_hs = '1' and raddr = ADDR_C_CTRL) then int_c_ap_vld <= '0'; -- clear on read end if; end if; end if; end process; end architecture behave;

gpl-3.0

freecores/usb_fpga_1_11

examples/usb-fpga-2.01/2.01b/ucecho/fpga/ucecho.vhd

42

580

library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity ucecho is port( pc : in unsigned(7 downto 0); pb : out unsigned(7 downto 0); CLK : in std_logic ); end ucecho; architecture RTL of ucecho is --signal declaration signal pb_buf : unsigned(7 downto 0); begin dpUCECHO: process(CLK) begin if CLK' event and CLK = '1' then if ( pc >= 97 ) and ( pc <= 122) then pb_buf <= pc - 32; else pb_buf <= pc; end if; pb <= pb_buf; end if; end process dpUCECHO; end RTL;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_reset.vhd

6

26422

------------------------------------------------------------------------------- -- axi_datamover_reset.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_reset.vhd -- -- Description: -- This file implements the DataMover Reset module. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library lib_cdc_v1_0; ------------------------------------------------------------------------------- entity axi_datamover_reset is generic ( C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0 -- 0 = Use Synchronous Command/Statys User Interface -- 1 = Use Asynchronous Command/Statys User Interface ); port ( -- Primary Clock and Reset Inputs ----------------- -- primary_aclk : in std_logic; -- primary_aresetn : in std_logic; -- --------------------------------------------------- -- Async operation clock and reset from User ------ -- Used for Command/Status User interface -- -- synchronization when C_STSCMD_IS_ASYNC = 1 -- -- secondary_awclk : in std_logic; -- secondary_aresetn : in std_logic; -- --------------------------------------------------- -- Halt request input control ------------------------------- halt_req : in std_logic; -- -- Active high soft shutdown request (can be a pulse) -- -- -- Halt Complete status flag -- halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------- -- Soft Shutdown internal interface ------------------------------------------------ -- flush_stop_request : Out std_logic; -- -- Active high soft stop request to modules -- -- data_cntlr_stopped : in std_logic; -- -- Active high flag indicating the data controller is flushed and stopped -- -- addr_cntlr_stopped : in std_logic; -- -- Active high flag indicating the address controller is flushed and stopped -- -- aux1_stopped : in std_logic; -- -- Active high flag flush complete for auxillary 1 module -- -- Tie high if unused -- -- aux2_stopped : in std_logic; -- -- Active high flag flush complete for auxillary 2 module -- -- Tie high if unused -- ------------------------------------------------------------------------------------ -- HW Reset outputs to reset groups ------------------------------------- -- cmd_stat_rst_user : Out std_logic; -- -- The reset to the Command/Status Module User interface side -- -- cmd_stat_rst_int : Out std_logic; -- -- The reset to the Command/Status Module internal interface side -- -- mmap_rst : Out std_logic; -- -- The reset to the Memory Map interface side -- -- stream_rst : Out std_logic -- -- The reset to the Stream interface side -- -------------------------------------------------------------------------- ); end entity axi_datamover_reset; architecture implementation of axi_datamover_reset is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; constant MTBF_STAGES : integer := 4; -- ATTRIBUTE async_reg : STRING; -- Signals signal sig_cmd_stat_rst_user_n : std_logic := '0'; signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0'; signal sig_cmd_stat_rst_int_reg_n : std_logic := '0'; signal sig_mmap_rst_reg_n : std_logic := '0'; signal sig_stream_rst_reg_n : std_logic := '0'; signal sig_syncd_sec_rst : std_logic := '0'; -- soft shutdown support signal sig_internal_reset : std_logic := '0'; signal sig_s_h_halt_reg : std_logic := '0'; signal sig_halt_cmplt : std_logic := '0'; -- additional CDC synchronization signals signal sig_sec_neg_edge_plus_delay : std_logic := '0'; signal sig_secondary_aresetn_reg : std_logic := '0'; signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0'; signal sig_prim2sec_rst_reg2_n : std_logic := '0'; -- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg1_n_cdc_to : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg2_n : SIGNAL IS "true"; begin --(architecture implementation) -- Assign outputs cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n); cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or sig_syncd_sec_rst; mmap_rst <= not(sig_mmap_rst_reg_n) or sig_syncd_sec_rst; stream_rst <= not(sig_stream_rst_reg_n) or sig_syncd_sec_rst; -- Internal logic Implmentation ------------------------------------------------------------ -- If Generate -- -- Label: GEN_SYNC_CMDSTAT_RESET -- -- If Generate Description: -- This IfGen assigns the reset for the -- Synchronous Command/Status User interface case -- ------------------------------------------------------------ GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate begin sig_syncd_sec_rst <= '0'; sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from); end generate GEN_SYNC_CMDSTAT_RESET; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ASYNC_CMDSTAT_RESET -- -- If Generate Description: -- This IfGen assigns the reset for the -- Asynchronous Command/Status User interface case -- ------------------------------------------------------------ GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate -- ATTRIBUTE async_reg : STRING; signal sig_sec_reset_in_reg_n : std_logic := '0'; signal sig_secondary_aresetn_reg_tmp : std_logic := '0'; -- Secondary reset pulse stretcher signal sig_secondary_dly1 : std_logic := '0'; signal sig_secondary_dly2 : std_logic := '0'; signal sig_neg_edge_detect : std_logic := '0'; signal sig_sec2prim_reset : std_logic := '0'; signal sig_sec2prim_reset_reg_cdc_tig : std_logic := '0'; signal sig_sec2prim_reset_reg2 : std_logic := '0'; signal sig_sec2prim_rst_syncro1_cdc_tig : std_logic := '0'; signal sig_sec2prim_rst_syncro2 : std_logic := '0'; -- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg_cdc_tig : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg2 : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro1_cdc_tig : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro2 : SIGNAL IS "true"; begin -- Generate the reset in the primary clock domain. Use the longer -- of the pulse stretched reset or the actual reset. sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or sig_sec2prim_rst_syncro2; -- Check for falling edge of secondary_aresetn input sig_neg_edge_detect <= '1' when (sig_sec_reset_in_reg_n = '1' and secondary_aresetn = '0') else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PUSE_STRETCH_FLOPS -- -- Process Description: -- This process implements a 3 clock wide pulse whenever the -- secondary reset is asserted -- ------------------------------------------------------------- IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then If (sig_secondary_dly2 = '1') Then sig_secondary_dly1 <= '0' ; sig_secondary_dly2 <= '0' ; Elsif (sig_neg_edge_detect = '1') Then sig_secondary_dly1 <= '1'; else sig_secondary_dly2 <= sig_secondary_dly1 ; End if; end if; end process IMP_PUSE_STRETCH_FLOPS; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SYNC_NEG_EDGE -- -- Process Description: -- First (source clock) stage synchronizer for CDC of -- negative edge detection, -- ------------------------------------------------------------- SYNC_NEG_EDGE : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or sig_secondary_dly1 or sig_secondary_dly2; end if; end process SYNC_NEG_EDGE; -- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SEC2PRIM_RST_SYNCRO -- -- Process Description: -- This process registers the secondary reset input to -- the primary clock domain. -- ------------------------------------------------------------- SEC2PRIM_RST_SYNCRO : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => sig_sec_neg_edge_plus_delay, prmry_vect_in => (others => '0'), scndry_aclk => primary_aclk, scndry_resetn => '0', scndry_out => sig_sec2prim_reset_reg2, scndry_vect_out => open ); -- SEC2PRIM_RST_SYNCRO : process (primary_aclk) -- begin -- if (primary_aclk'event and primary_aclk = '1') then -- -- -- sig_sec2prim_reset_reg_cdc_tig <= sig_sec_neg_edge_plus_delay ; -- -- sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg_cdc_tig; -- -- end if; -- end process SEC2PRIM_RST_SYNCRO; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SEC_RST -- -- Process Description: -- First (source clock) stage synchronizer for CDC of -- secondary reset input, -- ------------------------------------------------------------- REG_SEC_RST : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_secondary_aresetn_reg <= secondary_aresetn; end if; end process REG_SEC_RST; -- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SEC2PRIM_RST_SYNCRO_2 -- -- Process Description: -- Second stage (destination) synchronizers for the secondary -- reset CDC to the primary clock. -- ------------------------------------------------------------- sig_secondary_aresetn_reg_tmp <= not(sig_secondary_aresetn_reg); SEC2PRIM_RST_SYNCRO_2 : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => sig_secondary_aresetn_reg_tmp, prmry_vect_in => (others => '0'), scndry_aclk => primary_aclk, scndry_resetn => '0', scndry_out => sig_sec2prim_rst_syncro2, scndry_vect_out => open ); -- SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk) -- begin -- if (primary_aclk'event and primary_aclk = '1') then -- -- -- -- CDC sig_sec2prim_rst_syncro1_cdc_tig <= not(secondary_aresetn); -- sig_sec2prim_rst_syncro1_cdc_tig <= not(sig_secondary_aresetn_reg); -- sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1_cdc_tig; -- -- -- end if; -- end process SEC2PRIM_RST_SYNCRO_2; -- Generate the Command and Status side reset sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and sig_prim2sec_rst_reg2_n; -- CDC sig_cmd_stat_rst_user_reg_n_cdc_from; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_RESET_ASYNC -- -- Process Description: -- This process registers the secondary reset input to -- generate the Command/Status User interface reset. -- ------------------------------------------------------------- REG_RESET_ASYNC : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_sec_reset_in_reg_n <= secondary_aresetn; end if; end process REG_RESET_ASYNC; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SYNC_PRIM2SEC_RST -- -- Process Description: -- Second (destination clock) stage synchronizers for CDC of -- primary reset input, -- ------------------------------------------------------------- SYNC_PRIM2SEC_RST : entity lib_cdc_v1_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => sig_cmd_stat_rst_user_reg_n_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => secondary_awclk, scndry_resetn => '0', scndry_out => sig_prim2sec_rst_reg2_n, scndry_vect_out => open ); -- SYNC_PRIM2SEC_RST : process (secondary_awclk) -- begin -- if (secondary_awclk'event and secondary_awclk = '1') then -- -- sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from; -- sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to; -- -- end if; -- end process SYNC_PRIM2SEC_RST; -- end generate GEN_ASYNC_CMDSTAT_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_CMDSTAT_PRIM_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Command/Status User interface reset. -- ------------------------------------------------------------- REG_CMDSTAT_PRIM_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn; end if; end process REG_CMDSTAT_PRIM_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_CMDSTAT_INT_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Command/Status internal interface reset. -- ------------------------------------------------------------- REG_CMDSTAT_INT_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_cmd_stat_rst_int_reg_n <= primary_aresetn; end if; end process REG_CMDSTAT_INT_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_MMAP_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Memory Map interface reset. -- ------------------------------------------------------------- REG_MMAP_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_mmap_rst_reg_n <= primary_aresetn; end if; end process REG_MMAP_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_STREAM_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Stream interface reset. -- ------------------------------------------------------------- REG_STREAM_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_stream_rst_reg_n <= primary_aresetn; end if; end process REG_STREAM_RESET; -- Soft Shutdown logic ------------------------------------------------------ sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or sig_syncd_sec_rst; flush_stop_request <= sig_s_h_halt_reg; halt_cmplt <= sig_halt_cmplt; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_HALT_REQ -- -- Process Description: -- Implements a sample and hold flop for the halt request -- input. Can only be cleared on a HW reset. -- ------------------------------------------------------------- REG_HALT_REQ : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_internal_reset = '1') then sig_s_h_halt_reg <= '0'; elsif (halt_req = '1') then sig_s_h_halt_reg <= '1'; else null; -- hold current state end if; end if; end process REG_HALT_REQ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_CMPLT -- -- Process Description: -- Implements a the flop for the halt complete status -- output. Can only be cleared on a HW reset. -- ------------------------------------------------------------- IMP_HALT_CMPLT : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_internal_reset = '1') then sig_halt_cmplt <= '0'; elsif (data_cntlr_stopped = '1' and addr_cntlr_stopped = '1' and aux1_stopped = '1' and aux2_stopped = '1') then sig_halt_cmplt <= '1'; else null; -- hold current state end if; end if; end process IMP_HALT_CMPLT; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/FIFO_image_filter_img_1_cols_V.vhd

4

4564

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_img_1_cols_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_img_1_cols_V_shiftReg; architecture rtl of FIFO_image_filter_img_1_cols_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_img_1_cols_V is generic ( MEM_STYLE : string := "shiftreg"; DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_img_1_cols_V is component FIFO_image_filter_img_1_cols_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_img_1_cols_V_shiftReg : FIFO_image_filter_img_1_cols_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_register_s2mm.vhd

2

178198

-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_register_s2mm.vhd -- -- Description: This entity encompasses the channel register set. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_register_s2mm is generic( C_NUM_REGISTERS : integer := 11 ; C_INCLUDE_SG : integer := 1 ; C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ; C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ; C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ; C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ; C_MICRO_DMA : integer range 0 to 1 := 0 ; C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0 --C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034 ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- AXI Interface Control -- axi2ip_wrce : in std_logic_vector -- (C_NUM_REGISTERS-1 downto 0) ; -- axi2ip_wrdata : in std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- -- -- DMASR Control -- stop_dma : in std_logic ; -- halted_clr : in std_logic ; -- halted_set : in std_logic ; -- idle_set : in std_logic ; -- idle_clr : in std_logic ; -- ioc_irq_set : in std_logic ; -- dly_irq_set : in std_logic ; -- irqdelay_status : in std_logic_vector(7 downto 0) ; -- irqthresh_status : in std_logic_vector(7 downto 0) ; -- irqthresh_wren : out std_logic ; -- irqdelay_wren : out std_logic ; -- dlyirq_dsble : out std_logic ; -- CR605888 -- -- Error Control -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- ftch_interr_set : in std_logic ; -- ftch_slverr_set : in std_logic ; -- ftch_decerr_set : in std_logic ; -- ftch_error_addr : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_interr_set : in std_logic ; -- updt_slverr_set : in std_logic ; -- updt_decerr_set : in std_logic ; -- updt_error_addr : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- error_in : in std_logic ; -- error_out : out std_logic ; -- introut : out std_logic ; -- soft_reset_in : in std_logic ; -- soft_reset_clr : in std_logic ; -- -- -- CURDESC Update -- update_curdesc : in std_logic ; -- tdest_in : in std_logic_vector (5 downto 0) ; new_curdesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- -- TAILDESC Update -- tailpntr_updated : out std_logic ; -- -- -- Channel Register Out -- sg_ctl : out std_logic_vector (7 downto 0) ; dmacr : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- dmasr : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc1_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc1_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc1_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc1_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc2_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc2_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc2_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc2_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc3_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc3_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc3_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc3_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc4_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc4_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc4_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc4_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc5_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc5_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc5_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc5_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc6_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc6_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc6_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc6_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc7_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc7_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc7_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc7_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc8_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc8_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc8_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc8_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc9_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc9_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc9_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc9_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc10_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc10_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc10_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc10_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc11_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc11_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc11_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc11_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc12_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc12_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc12_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc12_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc13_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc13_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc13_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc13_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc14_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc14_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc14_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc14_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc15_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc15_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc15_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc15_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- buffer_address : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- buffer_length : out std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- buffer_length_wren : out std_logic ; -- bytes_received : in std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- bytes_received_wren : in std_logic -- ); -- end axi_dma_register_s2mm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_register_s2mm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- constant SGCTL_INDEX : integer := 0; constant DMACR_INDEX : integer := 1; -- DMACR Register index constant DMASR_INDEX : integer := 2; -- DMASR Register index constant CURDESC_LSB_INDEX : integer := 3; -- CURDESC LSB Reg index constant CURDESC_MSB_INDEX : integer := 4; -- CURDESC MSB Reg index constant TAILDESC_LSB_INDEX : integer := 5; -- TAILDESC LSB Reg index constant TAILDESC_MSB_INDEX : integer := 6; -- TAILDESC MSB Reg index constant CURDESC1_LSB_INDEX : integer := 17; -- CURDESC LSB Reg index constant CURDESC1_MSB_INDEX : integer := 18; -- CURDESC MSB Reg index constant TAILDESC1_LSB_INDEX : integer := 19; -- TAILDESC LSB Reg index constant TAILDESC1_MSB_INDEX : integer := 20; -- TAILDESC MSB Reg index constant CURDESC2_LSB_INDEX : integer := 25; -- CURDESC LSB Reg index constant CURDESC2_MSB_INDEX : integer := 26; -- CURDESC MSB Reg index constant TAILDESC2_LSB_INDEX : integer := 27; -- TAILDESC LSB Reg index constant TAILDESC2_MSB_INDEX : integer := 28; -- TAILDESC MSB Reg index constant CURDESC3_LSB_INDEX : integer := 33; -- CURDESC LSB Reg index constant CURDESC3_MSB_INDEX : integer := 34; -- CURDESC MSB Reg index constant TAILDESC3_LSB_INDEX : integer := 35; -- TAILDESC LSB Reg index constant TAILDESC3_MSB_INDEX : integer := 36; -- TAILDESC MSB Reg index constant CURDESC4_LSB_INDEX : integer := 41; -- CURDESC LSB Reg index constant CURDESC4_MSB_INDEX : integer := 42; -- CURDESC MSB Reg index constant TAILDESC4_LSB_INDEX : integer := 43; -- TAILDESC LSB Reg index constant TAILDESC4_MSB_INDEX : integer := 44; -- TAILDESC MSB Reg index constant CURDESC5_LSB_INDEX : integer := 49; -- CURDESC LSB Reg index constant CURDESC5_MSB_INDEX : integer := 50; -- CURDESC MSB Reg index constant TAILDESC5_LSB_INDEX : integer := 51; -- TAILDESC LSB Reg index constant TAILDESC5_MSB_INDEX : integer := 52; -- TAILDESC MSB Reg index constant CURDESC6_LSB_INDEX : integer := 57; -- CURDESC LSB Reg index constant CURDESC6_MSB_INDEX : integer := 58; -- CURDESC MSB Reg index constant TAILDESC6_LSB_INDEX : integer := 59; -- TAILDESC LSB Reg index constant TAILDESC6_MSB_INDEX : integer := 60; -- TAILDESC MSB Reg index constant CURDESC7_LSB_INDEX : integer := 65; -- CURDESC LSB Reg index constant CURDESC7_MSB_INDEX : integer := 66; -- CURDESC MSB Reg index constant TAILDESC7_LSB_INDEX : integer := 67; -- TAILDESC LSB Reg index constant TAILDESC7_MSB_INDEX : integer := 68; -- TAILDESC MSB Reg index constant CURDESC8_LSB_INDEX : integer := 73; -- CURDESC LSB Reg index constant CURDESC8_MSB_INDEX : integer := 74; -- CURDESC MSB Reg index constant TAILDESC8_LSB_INDEX : integer := 75; -- TAILDESC LSB Reg index constant TAILDESC8_MSB_INDEX : integer := 76; -- TAILDESC MSB Reg index constant CURDESC9_LSB_INDEX : integer := 81; -- CURDESC LSB Reg index constant CURDESC9_MSB_INDEX : integer := 82; -- CURDESC MSB Reg index constant TAILDESC9_LSB_INDEX : integer := 83; -- TAILDESC LSB Reg index constant TAILDESC9_MSB_INDEX : integer := 84; -- TAILDESC MSB Reg index constant CURDESC10_LSB_INDEX : integer := 89; -- CURDESC LSB Reg index constant CURDESC10_MSB_INDEX : integer := 90; -- CURDESC MSB Reg index constant TAILDESC10_LSB_INDEX : integer := 91; -- TAILDESC LSB Reg index constant TAILDESC10_MSB_INDEX : integer := 92; -- TAILDESC MSB Reg index constant CURDESC11_LSB_INDEX : integer := 97; -- CURDESC LSB Reg index constant CURDESC11_MSB_INDEX : integer := 98; -- CURDESC MSB Reg index constant TAILDESC11_LSB_INDEX : integer := 99; -- TAILDESC LSB Reg index constant TAILDESC11_MSB_INDEX : integer := 100; -- TAILDESC MSB Reg index constant CURDESC12_LSB_INDEX : integer := 105; -- CURDESC LSB Reg index constant CURDESC12_MSB_INDEX : integer := 106; -- CURDESC MSB Reg index constant TAILDESC12_LSB_INDEX : integer := 107; -- TAILDESC LSB Reg index constant TAILDESC12_MSB_INDEX : integer := 108; -- TAILDESC MSB Reg index constant CURDESC13_LSB_INDEX : integer := 113; -- CURDESC LSB Reg index constant CURDESC13_MSB_INDEX : integer := 114; -- CURDESC MSB Reg index constant TAILDESC13_LSB_INDEX : integer := 115; -- TAILDESC LSB Reg index constant TAILDESC13_MSB_INDEX : integer := 116; -- TAILDESC MSB Reg index constant CURDESC14_LSB_INDEX : integer := 121; -- CURDESC LSB Reg index constant CURDESC14_MSB_INDEX : integer := 122; -- CURDESC MSB Reg index constant TAILDESC14_LSB_INDEX : integer := 123; -- TAILDESC LSB Reg index constant TAILDESC14_MSB_INDEX : integer := 124; -- TAILDESC MSB Reg index constant CURDESC15_LSB_INDEX : integer := 129; -- CURDESC LSB Reg index constant CURDESC15_MSB_INDEX : integer := 130; -- CURDESC MSB Reg index constant TAILDESC15_LSB_INDEX : integer := 131; -- TAILDESC LSB Reg index constant TAILDESC15_MSB_INDEX : integer := 132; -- TAILDESC MSB Reg index -- CR603034 moved s2mm back to offset 6 --constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA) --constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA) -- -- --constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA) -- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx -- SA_ADDRESS_INDEX, -- Source Address Index -- DA_ADDRESS_INDEX); -- Destination Address Index constant BUFF_ADDRESS_INDEX : integer := 7; constant BUFF_LENGTH_INDEX : integer := 11; -- Buffer Length Reg constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0'); constant DMA_CONFIG : std_logic_vector(0 downto 0) := std_logic_vector(to_unsigned(C_INCLUDE_SG,1)); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal dmacr_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal dmasr_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0'); signal curdesc_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0'); signal taildesc_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal buffer_address_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal buffer_length_i : std_logic_vector (C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal curdesc1_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc1_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc1_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc1_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc2_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc2_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc2_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc2_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc3_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc3_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc3_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc3_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc4_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc4_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc4_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc4_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc5_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc5_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc5_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc5_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc6_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc6_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc6_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc6_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc7_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc7_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc7_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc7_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc8_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc8_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc8_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc8_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc9_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc9_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc9_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc9_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc10_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc10_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc10_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc10_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc11_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc11_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc11_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc11_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc12_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc12_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc12_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc12_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc13_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc13_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc13_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc13_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc14_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc14_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc14_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc14_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc15_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc15_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc15_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc15_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal update_curdesc1 : std_logic := '0'; signal update_curdesc2 : std_logic := '0'; signal update_curdesc3 : std_logic := '0'; signal update_curdesc4 : std_logic := '0'; signal update_curdesc5 : std_logic := '0'; signal update_curdesc6 : std_logic := '0'; signal update_curdesc7 : std_logic := '0'; signal update_curdesc8 : std_logic := '0'; signal update_curdesc9 : std_logic := '0'; signal update_curdesc10 : std_logic := '0'; signal update_curdesc11 : std_logic := '0'; signal update_curdesc12 : std_logic := '0'; signal update_curdesc13 : std_logic := '0'; signal update_curdesc14 : std_logic := '0'; signal update_curdesc15 : std_logic := '0'; signal dest0 : std_logic := '0'; signal dest1 : std_logic := '0'; signal dest2 : std_logic := '0'; signal dest3 : std_logic := '0'; signal dest4 : std_logic := '0'; signal dest5 : std_logic := '0'; signal dest6 : std_logic := '0'; signal dest7 : std_logic := '0'; signal dest8 : std_logic := '0'; signal dest9 : std_logic := '0'; signal dest10 : std_logic := '0'; signal dest11 : std_logic := '0'; signal dest12 : std_logic := '0'; signal dest13 : std_logic := '0'; signal dest14 : std_logic := '0'; signal dest15 : std_logic := '0'; -- DMASR Signals signal halted : std_logic := '0'; signal idle : std_logic := '0'; signal cmplt : std_logic := '0'; signal error : std_logic := '0'; signal dma_interr : std_logic := '0'; signal dma_slverr : std_logic := '0'; signal dma_decerr : std_logic := '0'; signal sg_interr : std_logic := '0'; signal sg_slverr : std_logic := '0'; signal sg_decerr : std_logic := '0'; signal ioc_irq : std_logic := '0'; signal dly_irq : std_logic := '0'; signal error_d1 : std_logic := '0'; signal error_re : std_logic := '0'; signal err_irq : std_logic := '0'; signal sg_ftch_error : std_logic := '0'; signal sg_updt_error : std_logic := '0'; signal error_pointer_set : std_logic := '0'; signal error_pointer_set1 : std_logic := '0'; signal error_pointer_set2 : std_logic := '0'; signal error_pointer_set3 : std_logic := '0'; signal error_pointer_set4 : std_logic := '0'; signal error_pointer_set5 : std_logic := '0'; signal error_pointer_set6 : std_logic := '0'; signal error_pointer_set7 : std_logic := '0'; signal error_pointer_set8 : std_logic := '0'; signal error_pointer_set9 : std_logic := '0'; signal error_pointer_set10 : std_logic := '0'; signal error_pointer_set11 : std_logic := '0'; signal error_pointer_set12 : std_logic := '0'; signal error_pointer_set13 : std_logic := '0'; signal error_pointer_set14 : std_logic := '0'; signal error_pointer_set15 : std_logic := '0'; -- interrupt coalescing support signals signal different_delay : std_logic := '0'; signal different_thresh : std_logic := '0'; signal threshold_is_zero : std_logic := '0'; -- soft reset support signals signal soft_reset_i : std_logic := '0'; signal run_stop_clr : std_logic := '0'; signal tail_update_lsb : std_logic := '0'; signal tail_update_msb : std_logic := '0'; signal sg_cache_info : std_logic_vector (7 downto 0); signal halt_free : std_logic := '0'; signal tmp11 : std_logic := '0'; signal sig_cur_updated : std_logic := '0'; signal tailpntr_updated_d1 : std_logic; signal tailpntr_updated_d2 : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin GEN_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate begin halt_free <= '1'; end generate GEN_MULTI_CH; GEN_NOMULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate begin halt_free <= dmasr_i(DMASR_HALTED_BIT); end generate GEN_NOMULTI_CH; GEN_DESC_UPDATE_FOR_SG : if C_NUM_S2MM_CHANNELS = 1 generate begin update_curdesc1 <= '0'; update_curdesc2 <= '0'; update_curdesc3 <= '0'; update_curdesc4 <= '0'; update_curdesc5 <= '0'; update_curdesc6 <= '0'; update_curdesc7 <= '0'; update_curdesc8 <= '0'; update_curdesc9 <= '0'; update_curdesc10 <= '0'; update_curdesc11 <= '0'; update_curdesc12 <= '0'; update_curdesc13 <= '0'; update_curdesc14 <= '0'; update_curdesc15 <= '0'; end generate GEN_DESC_UPDATE_FOR_SG; dest0 <= '1' when tdest_in (4 downto 0) = "00000" else '0'; dest1 <= '1' when tdest_in (4 downto 0) = "00001" else '0'; dest2 <= '1' when tdest_in (4 downto 0) = "00010" else '0'; dest3 <= '1' when tdest_in (4 downto 0) = "00011" else '0'; dest4 <= '1' when tdest_in (4 downto 0) = "00100" else '0'; dest5 <= '1' when tdest_in (4 downto 0) = "00101" else '0'; dest6 <= '1' when tdest_in (4 downto 0) = "00110" else '0'; dest7 <= '1' when tdest_in (4 downto 0) = "00111" else '0'; dest8 <= '1' when tdest_in (4 downto 0) = "01000" else '0'; dest9 <= '1' when tdest_in (4 downto 0) = "01001" else '0'; dest10 <= '1' when tdest_in (4 downto 0) = "01010" else '0'; dest11 <= '1' when tdest_in (4 downto 0) = "01011" else '0'; dest12 <= '1' when tdest_in (4 downto 0) = "01100" else '0'; dest13 <= '1' when tdest_in (4 downto 0) = "01101" else '0'; dest14 <= '1' when tdest_in (4 downto 0) = "01110" else '0'; dest15 <= '1' when tdest_in (4 downto 0) = "01111" else '0'; GEN_DESC_UPDATE_FOR_SG_CH : if C_NUM_S2MM_CHANNELS > 1 generate update_curdesc1 <= update_curdesc when tdest_in (4 downto 0) = "00001" else '0'; update_curdesc2 <= update_curdesc when tdest_in (4 downto 0) = "00010" else '0'; update_curdesc3 <= update_curdesc when tdest_in (4 downto 0) = "00011" else '0'; update_curdesc4 <= update_curdesc when tdest_in (4 downto 0) = "00100" else '0'; update_curdesc5 <= update_curdesc when tdest_in (4 downto 0) = "00101" else '0'; update_curdesc6 <= update_curdesc when tdest_in (4 downto 0) = "00110" else '0'; update_curdesc7 <= update_curdesc when tdest_in (4 downto 0) = "00111" else '0'; update_curdesc8 <= update_curdesc when tdest_in (4 downto 0) = "01000" else '0'; update_curdesc9 <= update_curdesc when tdest_in (4 downto 0) = "01001" else '0'; update_curdesc10 <= update_curdesc when tdest_in (4 downto 0) = "01010" else '0'; update_curdesc11 <= update_curdesc when tdest_in (4 downto 0) = "01011" else '0'; update_curdesc12 <= update_curdesc when tdest_in (4 downto 0) = "01100" else '0'; update_curdesc13 <= update_curdesc when tdest_in (4 downto 0) = "01101" else '0'; update_curdesc14 <= update_curdesc when tdest_in (4 downto 0) = "01110" else '0'; update_curdesc15 <= update_curdesc when tdest_in (4 downto 0) = "01111" else '0'; end generate GEN_DESC_UPDATE_FOR_SG_CH; dmacr <= dmacr_i ; dmasr <= dmasr_i ; curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ; curdesc_msb <= curdesc_msb_i ; taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ; taildesc_msb <= taildesc_msb_i ; buffer_address <= buffer_address_i ; buffer_length <= buffer_length_i ; curdesc1_lsb <= curdesc1_lsb_i ; curdesc1_msb <= curdesc1_msb_i ; taildesc1_lsb <= taildesc1_lsb_i ; taildesc1_msb <= taildesc1_msb_i ; curdesc2_lsb <= curdesc2_lsb_i ; curdesc2_msb <= curdesc2_msb_i ; taildesc2_lsb <= taildesc2_lsb_i ; taildesc2_msb <= taildesc2_msb_i ; curdesc3_lsb <= curdesc3_lsb_i ; curdesc3_msb <= curdesc3_msb_i ; taildesc3_lsb <= taildesc3_lsb_i ; taildesc3_msb <= taildesc3_msb_i ; curdesc4_lsb <= curdesc4_lsb_i ; curdesc4_msb <= curdesc4_msb_i ; taildesc4_lsb <= taildesc4_lsb_i ; taildesc4_msb <= taildesc4_msb_i ; curdesc5_lsb <= curdesc5_lsb_i ; curdesc5_msb <= curdesc5_msb_i ; taildesc5_lsb <= taildesc5_lsb_i ; taildesc5_msb <= taildesc5_msb_i ; curdesc6_lsb <= curdesc6_lsb_i ; curdesc6_msb <= curdesc6_msb_i ; taildesc6_lsb <= taildesc6_lsb_i ; taildesc6_msb <= taildesc6_msb_i ; curdesc7_lsb <= curdesc7_lsb_i ; curdesc7_msb <= curdesc7_msb_i ; taildesc7_lsb <= taildesc7_lsb_i ; taildesc7_msb <= taildesc7_msb_i ; curdesc8_lsb <= curdesc8_lsb_i ; curdesc8_msb <= curdesc8_msb_i ; taildesc8_lsb <= taildesc8_lsb_i ; taildesc8_msb <= taildesc8_msb_i ; curdesc9_lsb <= curdesc9_lsb_i ; curdesc9_msb <= curdesc9_msb_i ; taildesc9_lsb <= taildesc9_lsb_i ; taildesc9_msb <= taildesc9_msb_i ; curdesc10_lsb <= curdesc10_lsb_i ; curdesc10_msb <= curdesc10_msb_i ; taildesc10_lsb <= taildesc10_lsb_i ; taildesc10_msb <= taildesc10_msb_i ; curdesc11_lsb <= curdesc11_lsb_i ; curdesc11_msb <= curdesc11_msb_i ; taildesc11_lsb <= taildesc11_lsb_i ; taildesc11_msb <= taildesc11_msb_i ; curdesc12_lsb <= curdesc12_lsb_i ; curdesc12_msb <= curdesc12_msb_i ; taildesc12_lsb <= taildesc12_lsb_i ; taildesc12_msb <= taildesc12_msb_i ; curdesc13_lsb <= curdesc13_lsb_i ; curdesc13_msb <= curdesc13_msb_i ; taildesc13_lsb <= taildesc13_lsb_i ; taildesc13_msb <= taildesc13_msb_i ; curdesc14_lsb <= curdesc14_lsb_i ; curdesc14_msb <= curdesc14_msb_i ; taildesc14_lsb <= taildesc14_lsb_i ; taildesc14_msb <= taildesc14_msb_i ; curdesc15_lsb <= curdesc15_lsb_i ; curdesc15_msb <= curdesc15_msb_i ; taildesc15_lsb <= taildesc15_lsb_i ; taildesc15_msb <= taildesc15_msb_i ; --------------------------------------------------------------------------- -- DMA Control Register --------------------------------------------------------------------------- -- DMACR - Interrupt Delay Value ------------------------------------------------------------------------------- DMACR_DELAY : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0'); elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT); end if; end if; end process DMACR_DELAY; -- If written delay is different than previous value then assert write enable different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) /= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) else '0'; -- delay value different, drive write of delay value to interrupt controller NEW_DELAY_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then irqdelay_wren <= '0'; -- If AXI Lite write to DMACR and delay different than current -- setting then update delay value elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then irqdelay_wren <= '1'; else irqdelay_wren <= '0'; end if; end if; end process NEW_DELAY_WRITE; ------------------------------------------------------------------------------- -- DMACR - Interrupt Threshold Value ------------------------------------------------------------------------------- threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD else '0'; DMACR_THRESH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD; -- On AXI Lite write elsif(axi2ip_wrce(DMACR_INDEX) = '1')then -- If value is 0 then set threshold to 1 if(threshold_is_zero='1')then dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD; -- else set threshold to axi lite wrdata value else dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT); end if; end if; end if; end process DMACR_THRESH; -- If written threshold is different than previous value then assert write enable different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) /= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) else '0'; -- new treshold written therefore drive write of threshold out NEW_THRESH_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then irqthresh_wren <= '0'; -- If AXI Lite write to DMACR and threshold different than current -- setting then update threshold value elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then irqthresh_wren <= '1'; else irqthresh_wren <= '0'; end if; end if; end process NEW_THRESH_WRITE; ------------------------------------------------------------------------------- -- DMACR - Remainder of DMA Control Register, Key Hole write bit (3) ------------------------------------------------------------------------------- DMACR_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 downto DMACR_RESERVED5_BIT) <= (others => '0'); elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15 downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT) -- bit 14 & axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 13 & axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 12 & axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bits 11 downto 3 & ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT); end if; end if; end process DMACR_REGISTER; DMACR_REGISTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then dmacr_i(DMACR_KH_BIT) <= '0'; dmacr_i(CYCLIC_BIT) <= '0'; elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT); dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT); end if; end if; end process DMACR_REGISTER1; ------------------------------------------------------------------------------- -- DMACR - Reset Bit ------------------------------------------------------------------------------- DMACR_RESET : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(soft_reset_clr = '1')then dmacr_i(DMACR_RESET_BIT) <= '0'; -- If soft reset set in other channel then set -- reset bit here too elsif(soft_reset_in = '1')then dmacr_i(DMACR_RESET_BIT) <= '1'; -- If DMACR Write then pass axi lite write bus to DMARC reset bit elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT); end if; end if; end process DMACR_RESET; soft_reset_i <= dmacr_i(DMACR_RESET_BIT); ------------------------------------------------------------------------------- -- Tail Pointer Enable fixed at 1 for this release of axi dma ------------------------------------------------------------------------------- dmacr_i(DMACR_TAILPEN_BIT) <= '1'; ------------------------------------------------------------------------------- -- DMACR - Run/Stop Bit ------------------------------------------------------------------------------- run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error or error_in = '1' -- S2MM Error or stop_dma = '1' -- Stop due to error or soft_reset_i = '1' -- MM2S Soft Reset or soft_reset_in = '1' -- S2MM Soft Reset else '0'; DMACR_RUNSTOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_RS_BIT) <= '0'; -- Clear on sg error (i.e. error) or other channel -- error (i.e. error_in) or dma error or soft reset elsif(run_stop_clr = '1')then dmacr_i(DMACR_RS_BIT) <= '0'; elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT); end if; end if; end process DMACR_RUNSTOP; --------------------------------------------------------------------------- -- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA -- channel is halted. --------------------------------------------------------------------------- DMASR_HALTED : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or halted_set = '1')then halted <= '1'; elsif(halted_clr = '1')then halted <= '0'; end if; end if; end process DMASR_HALTED; --------------------------------------------------------------------------- -- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA -- channel is IDLE waiting at tail pointer. Update of Tail Pointer -- will cause engine to resume. Note: Halted channels return to a -- reset condition. --------------------------------------------------------------------------- DMASR_IDLE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or idle_clr = '1' or halted_set = '1')then idle <= '0'; elsif(idle_set = '1')then idle <= '1'; end if; end if; end process DMASR_IDLE; --------------------------------------------------------------------------- -- DMA Status Error bit (BIT 3) -- Note: any error will cause entire engine to halt --------------------------------------------------------------------------- error <= dma_interr or dma_slverr or dma_decerr or sg_interr or sg_slverr or sg_decerr; -- Scatter Gather Error --sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set; -- SG Update Errors or DMA errors assert flag on descriptor update -- Used to latch current descriptor pointer --sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set -- or dma_interr or dma_slverr or dma_decerr; -- Map out to halt opposing channel error_out <= error; SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_ftch_error <= '0'; sg_updt_error <= '0'; else sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set; sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set or dma_interr or dma_slverr or dma_decerr; end if; end if; end process SG_FTCH_ERROR_PROC; --------------------------------------------------------------------------- -- DMA Status DMA Internal Error bit (BIT 4) --------------------------------------------------------------------------- DMASR_DMAINTERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_interr <= '0'; elsif(dma_interr_set = '1' )then dma_interr <= '1'; end if; end if; end process DMASR_DMAINTERR; --------------------------------------------------------------------------- -- DMA Status DMA Slave Error bit (BIT 5) --------------------------------------------------------------------------- DMASR_DMASLVERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_slverr <= '0'; elsif(dma_slverr_set = '1' )then dma_slverr <= '1'; end if; end if; end process DMASR_DMASLVERR; --------------------------------------------------------------------------- -- DMA Status DMA Decode Error bit (BIT 6) --------------------------------------------------------------------------- DMASR_DMADECERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_decerr <= '0'; elsif(dma_decerr_set = '1' )then dma_decerr <= '1'; end if; end if; end process DMASR_DMADECERR; --------------------------------------------------------------------------- -- DMA Status SG Internal Error bit (BIT 8) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGINTERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_interr <= '0'; elsif(ftch_interr_set = '1' or updt_interr_set = '1')then sg_interr <= '1'; end if; end if; end process DMASR_SGINTERR; --------------------------------------------------------------------------- -- DMA Status SG Slave Error bit (BIT 9) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGSLVERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_slverr <= '0'; elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then sg_slverr <= '1'; end if; end if; end process DMASR_SGSLVERR; --------------------------------------------------------------------------- -- DMA Status SG Decode Error bit (BIT 10) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGDECERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_decerr <= '0'; elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then sg_decerr <= '1'; end if; end if; end process DMASR_SGDECERR; --------------------------------------------------------------------------- -- DMA Status IOC Interrupt status bit (BIT 11) --------------------------------------------------------------------------- DMASR_IOCIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then ioc_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT))) or ioc_irq_set; elsif(ioc_irq_set = '1')then ioc_irq <= '1'; end if; end if; end process DMASR_IOCIRQ; --------------------------------------------------------------------------- -- DMA Status Delay Interrupt status bit (BIT 12) --------------------------------------------------------------------------- DMASR_DLYIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dly_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT))) or dly_irq_set; elsif(dly_irq_set = '1')then dly_irq <= '1'; end if; end if; end process DMASR_DLYIRQ; -- CR605888 Disable delay timer if halted or on delay irq set --dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348 dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348 or dmasr_i(DMASR_DLYIRQ_BIT); --------------------------------------------------------------------------- -- DMA Status Error Interrupt status bit (BIT 12) --------------------------------------------------------------------------- -- Delay error setting for generation of error strobe GEN_ERROR_RE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then error_d1 <= '0'; else error_d1 <= error; end if; end if; end process GEN_ERROR_RE; -- Generate rising edge pulse on error error_re <= error and not error_d1; DMASR_ERRIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then err_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT))) or error_re; elsif(error_re = '1')then err_irq <= '1'; end if; end if; end process DMASR_ERRIRQ; --------------------------------------------------------------------------- -- DMA Interrupt OUT --------------------------------------------------------------------------- REG_INTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then introut <= '0'; else introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT)) or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT)) or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT)); end if; end if; end process; --------------------------------------------------------------------------- -- DMA Status Register --------------------------------------------------------------------------- dmasr_i <= irqdelay_status -- Bits 31 downto 24 & irqthresh_status -- Bits 23 downto 16 & '0' -- Bit 15 & err_irq -- Bit 14 & dly_irq -- Bit 13 & ioc_irq -- Bit 12 & '0' -- Bit 11 & sg_decerr -- Bit 10 & sg_slverr -- Bit 9 & sg_interr -- Bit 8 & '0' -- Bit 7 & dma_decerr -- Bit 6 & dma_slverr -- Bit 5 & dma_interr -- Bit 4 & DMA_CONFIG -- Bit 3 & '0' -- Bit 2 & idle -- Bit 1 & halted; -- Bit 0 -- Generate current descriptor and tail descriptor register for Scatter Gather Mode GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate begin GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate begin MM2S_SGCTL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_cache_info <= "00000011"; --(others => '0'); elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0); else sg_cache_info <= sg_cache_info; end if; end if; end process MM2S_SGCTL; sg_ctl <= sg_cache_info; end generate GEN_SG_CTL_REG; GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate begin sg_ctl <= "00000011"; --(others => '0'); end generate GEN_SG_NO_CTL_REG; -- Signals not used for Scatter Gather Mode, only simple mode buffer_address_i <= (others => '0'); buffer_length_i <= (others => '0'); buffer_length_wren <= '0'; --------------------------------------------------------------------------- -- Current Descriptor LSB Register --------------------------------------------------------------------------- CURDESC_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc_lsb_i <= (others => '0'); error_pointer_set <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6); error_pointer_set <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest0 = '1')then -- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6); error_pointer_set <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and halt_free = '1')then curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT); -- & ZERO_VALUE(CURDESC_RESERVED_BIT5 -- downto CURDESC_RESERVED_BIT0); error_pointer_set <= '0'; end if; end if; end if; end process CURDESC_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT); -- & ZERO_VALUE(TAILDESC_RESERVED_BIT5 -- downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC_LSB_REGISTER; GEN_DESC1_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate CURDESC1_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc1_lsb_i <= (others => '0'); error_pointer_set1 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set1 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then curdesc1_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set1 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest1 = '1')then -- curdesc1_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set1 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then curdesc1_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set1 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC1_LSB_INDEX) = '1' and halt_free = '1')then curdesc1_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set1 <= '0'; end if; end if; end if; end process CURDESC1_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC1_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc1_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC1_LSB_INDEX) = '1')then taildesc1_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC1_LSB_REGISTER; end generate GEN_DESC1_REG_FOR_SG; GEN_DESC2_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate CURDESC2_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc2_lsb_i <= (others => '0'); error_pointer_set2 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set2 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then curdesc2_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set2 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest2 = '1')then -- curdesc2_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set2 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then curdesc2_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set2 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC2_LSB_INDEX) = '1' and halt_free = '1')then curdesc2_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set2 <= '0'; end if; end if; end if; end process CURDESC2_LSB_REGISTER; TAILDESC2_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc2_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC2_LSB_INDEX) = '1')then taildesc2_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC2_LSB_REGISTER; end generate GEN_DESC2_REG_FOR_SG; GEN_DESC3_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate CURDESC3_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc3_lsb_i <= (others => '0'); error_pointer_set3 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set3 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then curdesc3_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set3 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest3 = '1')then -- curdesc3_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set3 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then curdesc3_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set3 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC3_LSB_INDEX) = '1' and halt_free = '1')then curdesc3_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set3 <= '0'; end if; end if; end if; end process CURDESC3_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC3_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc3_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC3_LSB_INDEX) = '1')then taildesc3_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC3_LSB_REGISTER; end generate GEN_DESC3_REG_FOR_SG; GEN_DESC4_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate CURDESC4_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc4_lsb_i <= (others => '0'); error_pointer_set4 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set4 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then curdesc4_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set4 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest4 = '1')then -- curdesc4_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set4 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then curdesc4_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set4 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC4_LSB_INDEX) = '1' and halt_free = '1')then curdesc4_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set4 <= '0'; end if; end if; end if; end process CURDESC4_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC4_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc4_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC4_LSB_INDEX) = '1')then taildesc4_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC4_LSB_REGISTER; end generate GEN_DESC4_REG_FOR_SG; GEN_DESC5_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate CURDESC5_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc5_lsb_i <= (others => '0'); error_pointer_set5 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set5 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then curdesc5_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set5 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest5 = '1')then -- curdesc5_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set5 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then curdesc5_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set5 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC5_LSB_INDEX) = '1' and halt_free = '1')then curdesc5_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set5 <= '0'; end if; end if; end if; end process CURDESC5_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC5_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc5_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC5_LSB_INDEX) = '1')then taildesc5_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC5_LSB_REGISTER; end generate GEN_DESC5_REG_FOR_SG; GEN_DESC6_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate CURDESC6_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc6_lsb_i <= (others => '0'); error_pointer_set6 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set6 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then curdesc6_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set6 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest6 = '1')then -- curdesc6_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set6 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then curdesc6_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set6 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC6_LSB_INDEX) = '1' and halt_free = '1')then curdesc6_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set6 <= '0'; end if; end if; end if; end process CURDESC6_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC6_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc6_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC6_LSB_INDEX) = '1')then taildesc6_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC6_LSB_REGISTER; end generate GEN_DESC6_REG_FOR_SG; GEN_DESC7_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate CURDESC7_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc7_lsb_i <= (others => '0'); error_pointer_set7 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set7 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then curdesc7_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set7 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest7 = '1')then -- curdesc7_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set7 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then curdesc7_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set7 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC7_LSB_INDEX) = '1' and halt_free = '1')then curdesc7_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set7 <= '0'; end if; end if; end if; end process CURDESC7_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC7_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc7_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC7_LSB_INDEX) = '1')then taildesc7_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC7_LSB_REGISTER; end generate GEN_DESC7_REG_FOR_SG; GEN_DESC8_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate CURDESC8_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc8_lsb_i <= (others => '0'); error_pointer_set8 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set8 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then curdesc8_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set8 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest8 = '1')then -- curdesc8_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set8 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then curdesc8_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set8 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC8_LSB_INDEX) = '1' and halt_free = '1')then curdesc8_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set8 <= '0'; end if; end if; end if; end process CURDESC8_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC8_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc8_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC8_LSB_INDEX) = '1')then taildesc8_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC8_LSB_REGISTER; end generate GEN_DESC8_REG_FOR_SG; GEN_DESC9_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate CURDESC9_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc9_lsb_i <= (others => '0'); error_pointer_set9 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set9 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then curdesc9_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set9 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest9 = '1')then -- curdesc9_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set9 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then curdesc9_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set9 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC9_LSB_INDEX) = '1' and halt_free = '1')then curdesc9_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set9 <= '0'; end if; end if; end if; end process CURDESC9_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC9_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc9_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC9_LSB_INDEX) = '1')then taildesc9_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC9_LSB_REGISTER; end generate GEN_DESC9_REG_FOR_SG; GEN_DESC10_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate CURDESC10_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc10_lsb_i <= (others => '0'); error_pointer_set10 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set10 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then curdesc10_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set10 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest10 = '1')then -- curdesc10_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set10 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then curdesc10_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set10 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC10_LSB_INDEX) = '1' and halt_free = '1')then curdesc10_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set10 <= '0'; end if; end if; end if; end process CURDESC10_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC10_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc10_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC10_LSB_INDEX) = '1')then taildesc10_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC10_LSB_REGISTER; end generate GEN_DESC10_REG_FOR_SG; GEN_DESC11_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate CURDESC11_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc11_lsb_i <= (others => '0'); error_pointer_set11 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set11 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then curdesc11_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set11 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest11 = '1')then -- curdesc11_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set11 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then curdesc11_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set11 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC11_LSB_INDEX) = '1' and halt_free = '1')then curdesc11_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set11 <= '0'; end if; end if; end if; end process CURDESC11_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC11_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc11_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC11_LSB_INDEX) = '1')then taildesc11_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC11_LSB_REGISTER; end generate GEN_DESC11_REG_FOR_SG; GEN_DESC12_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate CURDESC12_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc12_lsb_i <= (others => '0'); error_pointer_set12 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set12 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then curdesc12_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set12 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest12 = '1')then -- curdesc12_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set12 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then curdesc12_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set12 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC12_LSB_INDEX) = '1' and halt_free = '1')then curdesc12_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set12 <= '0'; end if; end if; end if; end process CURDESC12_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC12_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc12_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC12_LSB_INDEX) = '1')then taildesc12_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC12_LSB_REGISTER; end generate GEN_DESC12_REG_FOR_SG; GEN_DESC13_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate CURDESC13_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc13_lsb_i <= (others => '0'); error_pointer_set13 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set13 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then curdesc13_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set13 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest13 = '1')then -- curdesc13_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set13 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then curdesc13_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set13 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC13_LSB_INDEX) = '1' and halt_free = '1')then curdesc13_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set13 <= '0'; end if; end if; end if; end process CURDESC13_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC13_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc13_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC13_LSB_INDEX) = '1')then taildesc13_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC13_LSB_REGISTER; end generate GEN_DESC13_REG_FOR_SG; GEN_DESC14_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate CURDESC14_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc14_lsb_i <= (others => '0'); error_pointer_set14 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set14 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then curdesc14_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set14 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest14 = '1')then -- curdesc14_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set14 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then curdesc14_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set14 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC14_LSB_INDEX) = '1' and halt_free = '1')then curdesc14_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set14 <= '0'; end if; end if; end if; end process CURDESC14_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC14_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc14_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC14_LSB_INDEX) = '1')then taildesc14_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC14_LSB_REGISTER; end generate GEN_DESC14_REG_FOR_SG; GEN_DESC15_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate CURDESC15_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc15_lsb_i <= (others => '0'); error_pointer_set15 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set15 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then curdesc15_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set15 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest15 = '1')then -- curdesc15_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set15 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then curdesc15_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set15 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC15_LSB_INDEX) = '1' and halt_free = '1')then curdesc15_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set15 <= '0'; end if; end if; end if; end process CURDESC15_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC15_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc15_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC15_LSB_INDEX) = '1')then taildesc15_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC15_LSB_REGISTER; end generate GEN_DESC15_REG_FOR_SG; --------------------------------------------------------------------------- -- Current Descriptor MSB Register --------------------------------------------------------------------------- -- Scatter Gather Interface configured for 64-Bit SG Addresses GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin CURDESC_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc_msb_i <= (others => '0'); elsif(error_pointer_set = '0')then -- Scatter Gather Fetch Error if(sg_ftch_error = '1' and dest0 = '1')then curdesc_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error elsif(sg_updt_error = '1' and dest0 = '1')then curdesc_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then curdesc_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and halt_free = '1')then curdesc_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then taildesc_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC_MSB_REGISTER; GEN_DESC1_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate CURDESC1_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc1_msb_i <= (others => '0'); elsif(error_pointer_set1 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then curdesc1_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest1 = '1')then -- curdesc1_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then curdesc1_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC1_MSB_INDEX) = '1' and halt_free = '1')then curdesc1_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC1_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC1_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc1_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC1_MSB_INDEX) = '1')then taildesc1_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC1_MSB_REGISTER; end generate GEN_DESC1_MSB_FOR_SG; GEN_DESC2_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate CURDESC2_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc2_msb_i <= (others => '0'); elsif(error_pointer_set2 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then curdesc2_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest2 = '1')then -- curdesc2_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then curdesc2_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC2_MSB_INDEX) = '1' and halt_free = '1')then curdesc2_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC2_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC2_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc2_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC2_MSB_INDEX) = '1')then taildesc2_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC2_MSB_REGISTER; end generate GEN_DESC2_MSB_FOR_SG; GEN_DESC3_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate CURDESC3_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc3_msb_i <= (others => '0'); elsif(error_pointer_set3 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then curdesc3_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest3 = '1')then -- curdesc3_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then curdesc3_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC3_MSB_INDEX) = '1' and halt_free = '1')then curdesc3_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC3_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC3_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc3_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC3_MSB_INDEX) = '1')then taildesc3_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC3_MSB_REGISTER; end generate GEN_DESC3_MSB_FOR_SG; GEN_DESC4_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate CURDESC4_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc4_msb_i <= (others => '0'); elsif(error_pointer_set4 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then curdesc4_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest4 = '1')then -- curdesc4_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then curdesc4_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC4_MSB_INDEX) = '1' and halt_free = '1')then curdesc4_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC4_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC4_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc4_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC4_MSB_INDEX) = '1')then taildesc4_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC4_MSB_REGISTER; end generate GEN_DESC4_MSB_FOR_SG; GEN_DESC5_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate CURDESC5_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc5_msb_i <= (others => '0'); elsif(error_pointer_set5 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then curdesc5_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest5 = '1')then -- curdesc5_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then curdesc5_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC5_MSB_INDEX) = '1' and halt_free = '1')then curdesc5_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC5_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC5_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc5_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC5_MSB_INDEX) = '1')then taildesc5_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC5_MSB_REGISTER; end generate GEN_DESC5_MSB_FOR_SG; GEN_DESC6_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate CURDESC6_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc6_msb_i <= (others => '0'); elsif(error_pointer_set6 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then curdesc6_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest6 = '1')then -- curdesc6_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then curdesc6_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC6_MSB_INDEX) = '1' and halt_free = '1')then curdesc6_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC6_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC6_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc6_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC6_MSB_INDEX) = '1')then taildesc6_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC6_MSB_REGISTER; end generate GEN_DESC6_MSB_FOR_SG; GEN_DESC7_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate CURDESC7_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc7_msb_i <= (others => '0'); elsif(error_pointer_set7 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then curdesc7_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest7 = '1')then -- curdesc7_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then curdesc7_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC7_MSB_INDEX) = '1' and halt_free = '1')then curdesc7_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC7_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC7_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc7_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC7_MSB_INDEX) = '1')then taildesc7_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC7_MSB_REGISTER; end generate GEN_DESC7_MSB_FOR_SG; GEN_DESC8_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate CURDESC8_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc8_msb_i <= (others => '0'); elsif(error_pointer_set8 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then curdesc8_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest8 = '1')then -- curdesc8_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then curdesc8_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC8_MSB_INDEX) = '1' and halt_free = '1')then curdesc8_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC8_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC8_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc8_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC8_MSB_INDEX) = '1')then taildesc8_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC8_MSB_REGISTER; end generate GEN_DESC8_MSB_FOR_SG; GEN_DESC9_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate CURDESC9_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc9_msb_i <= (others => '0'); elsif(error_pointer_set9 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then curdesc9_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest9 = '1')then -- curdesc9_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then curdesc9_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC9_MSB_INDEX) = '1' and halt_free = '1')then curdesc9_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC9_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC9_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc9_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC9_MSB_INDEX) = '1')then taildesc9_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC9_MSB_REGISTER; end generate GEN_DESC9_MSB_FOR_SG; GEN_DESC10_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate CURDESC10_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc10_msb_i <= (others => '0'); elsif(error_pointer_set10 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then curdesc10_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest10 = '1')then -- curdesc10_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then curdesc10_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC10_MSB_INDEX) = '1' and halt_free = '1')then curdesc10_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC10_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC10_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc10_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC10_MSB_INDEX) = '1')then taildesc10_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC10_MSB_REGISTER; end generate GEN_DESC10_MSB_FOR_SG; GEN_DESC11_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate CURDESC11_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc11_msb_i <= (others => '0'); elsif(error_pointer_set11 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then curdesc11_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest11 = '1')then -- curdesc11_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then curdesc11_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC11_MSB_INDEX) = '1' and halt_free = '1')then curdesc11_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC11_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC11_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc11_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC11_MSB_INDEX) = '1')then taildesc11_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC11_MSB_REGISTER; end generate GEN_DESC11_MSB_FOR_SG; GEN_DESC12_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate CURDESC12_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc12_msb_i <= (others => '0'); elsif(error_pointer_set12 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then curdesc12_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest12 = '1')then -- curdesc12_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then curdesc12_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC12_MSB_INDEX) = '1' and halt_free = '1')then curdesc12_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC12_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC12_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc12_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC12_MSB_INDEX) = '1')then taildesc12_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC12_MSB_REGISTER; end generate GEN_DESC12_MSB_FOR_SG; GEN_DESC13_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate CURDESC13_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc13_msb_i <= (others => '0'); elsif(error_pointer_set13 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then curdesc13_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest13 = '1')then -- curdesc13_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then curdesc13_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC13_MSB_INDEX) = '1' and halt_free = '1')then curdesc13_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC13_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC13_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc13_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC13_MSB_INDEX) = '1')then taildesc13_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC13_MSB_REGISTER; end generate GEN_DESC13_MSB_FOR_SG; GEN_DESC14_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate CURDESC14_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc14_msb_i <= (others => '0'); elsif(error_pointer_set14 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then curdesc14_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest14 = '1')then -- curdesc14_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then curdesc14_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC14_MSB_INDEX) = '1' and halt_free = '1')then curdesc14_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC14_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC14_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc14_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC14_MSB_INDEX) = '1')then taildesc14_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC14_MSB_REGISTER; end generate GEN_DESC14_MSB_FOR_SG; GEN_DESC15_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate CURDESC15_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc15_msb_i <= (others => '0'); elsif(error_pointer_set15 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then curdesc15_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest15 = '1')then -- curdesc15_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then curdesc15_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC15_MSB_INDEX) = '1' and halt_free = '1')then curdesc15_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC15_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC15_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc15_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC15_MSB_INDEX) = '1')then taildesc15_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC15_MSB_REGISTER; end generate GEN_DESC15_MSB_FOR_SG; end generate GEN_SG_ADDR_EQL64; -- Scatter Gather Interface configured for 32-Bit SG Addresses GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin curdesc_msb_i <= (others => '0'); taildesc_msb_i <= (others => '0'); -- Extending this to the extra registers curdesc1_msb_i <= (others => '0'); taildesc1_msb_i <= (others => '0'); curdesc2_msb_i <= (others => '0'); taildesc2_msb_i <= (others => '0'); curdesc3_msb_i <= (others => '0'); taildesc3_msb_i <= (others => '0'); curdesc4_msb_i <= (others => '0'); taildesc4_msb_i <= (others => '0'); curdesc5_msb_i <= (others => '0'); taildesc5_msb_i <= (others => '0'); curdesc6_msb_i <= (others => '0'); taildesc6_msb_i <= (others => '0'); curdesc7_msb_i <= (others => '0'); taildesc7_msb_i <= (others => '0'); curdesc8_msb_i <= (others => '0'); taildesc8_msb_i <= (others => '0'); curdesc9_msb_i <= (others => '0'); taildesc9_msb_i <= (others => '0'); curdesc10_msb_i <= (others => '0'); taildesc10_msb_i <= (others => '0'); curdesc11_msb_i <= (others => '0'); taildesc11_msb_i <= (others => '0'); curdesc12_msb_i <= (others => '0'); taildesc12_msb_i <= (others => '0'); curdesc13_msb_i <= (others => '0'); taildesc13_msb_i <= (others => '0'); curdesc14_msb_i <= (others => '0'); taildesc14_msb_i <= (others => '0'); curdesc15_msb_i <= (others => '0'); taildesc15_msb_i <= (others => '0'); end generate GEN_SG_ADDR_EQL32; -- Scatter Gather Interface configured for 32-Bit SG Addresses GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin -- Added dest so that BD can be dynamically updated GENERATE_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0) or (axi2ip_wrce(TAILDESC1_LSB_INDEX) and dest1) or (axi2ip_wrce(TAILDESC2_LSB_INDEX) and dest2) or (axi2ip_wrce(TAILDESC3_LSB_INDEX) and dest3) or (axi2ip_wrce(TAILDESC4_LSB_INDEX) and dest4) or (axi2ip_wrce(TAILDESC5_LSB_INDEX) and dest5) or (axi2ip_wrce(TAILDESC6_LSB_INDEX) and dest6) or (axi2ip_wrce(TAILDESC7_LSB_INDEX) and dest7) or (axi2ip_wrce(TAILDESC8_LSB_INDEX) and dest8) or (axi2ip_wrce(TAILDESC9_LSB_INDEX) and dest9) or (axi2ip_wrce(TAILDESC10_LSB_INDEX) and dest10) or (axi2ip_wrce(TAILDESC11_LSB_INDEX) and dest11) or (axi2ip_wrce(TAILDESC12_LSB_INDEX) and dest12) or (axi2ip_wrce(TAILDESC13_LSB_INDEX) and dest13) or (axi2ip_wrce(TAILDESC14_LSB_INDEX) and dest14) or (axi2ip_wrce(TAILDESC15_LSB_INDEX) and dest15); end generate GENERATE_MULTI_CH; GENERATE_NO_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0); end generate GENERATE_NO_MULTI_CH; TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then tailpntr_updated_d1 <= '0'; elsif (tail_update_lsb = '1' and tdest_in(5) = '0')then tailpntr_updated_d1 <= '1'; else tailpntr_updated_d1 <= '0'; end if; end if; end process TAILPNTR_UPDT_PROCESS; TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tailpntr_updated_d2 <= '0'; else tailpntr_updated_d2 <= tailpntr_updated_d1; end if; end if; end process TAILPNTR_UPDT_PROCESS_DEL; tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2); end generate GEN_TAILUPDATE_EQL32; -- Scatter Gather Interface configured for 64-Bit SG Addresses GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin -- Added dest so that BD can be dynamically updated tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0) or (axi2ip_wrce(TAILDESC1_MSB_INDEX) and dest1) or (axi2ip_wrce(TAILDESC2_MSB_INDEX) and dest2) or (axi2ip_wrce(TAILDESC3_MSB_INDEX) and dest3) or (axi2ip_wrce(TAILDESC4_MSB_INDEX) and dest4) or (axi2ip_wrce(TAILDESC5_MSB_INDEX) and dest5) or (axi2ip_wrce(TAILDESC6_MSB_INDEX) and dest6) or (axi2ip_wrce(TAILDESC7_MSB_INDEX) and dest7) or (axi2ip_wrce(TAILDESC8_MSB_INDEX) and dest8) or (axi2ip_wrce(TAILDESC9_MSB_INDEX) and dest9) or (axi2ip_wrce(TAILDESC10_MSB_INDEX) and dest10) or (axi2ip_wrce(TAILDESC11_MSB_INDEX) and dest11) or (axi2ip_wrce(TAILDESC12_MSB_INDEX) and dest12) or (axi2ip_wrce(TAILDESC13_MSB_INDEX) and dest13) or (axi2ip_wrce(TAILDESC14_MSB_INDEX) and dest14) or (axi2ip_wrce(TAILDESC15_MSB_INDEX) and dest15); -- tail_update_msb <= axi2ip_wrce(TAILDESC_MSB_INDEX) or -- axi2ip_wrce(TAILDESC1_MSB_INDEX) or -- axi2ip_wrce(TAILDESC2_MSB_INDEX) or -- axi2ip_wrce(TAILDESC3_MSB_INDEX) or -- axi2ip_wrce(TAILDESC4_MSB_INDEX) or -- axi2ip_wrce(TAILDESC5_MSB_INDEX) or -- axi2ip_wrce(TAILDESC6_MSB_INDEX) or -- axi2ip_wrce(TAILDESC7_MSB_INDEX) or -- axi2ip_wrce(TAILDESC8_MSB_INDEX) or -- axi2ip_wrce(TAILDESC9_MSB_INDEX) or -- axi2ip_wrce(TAILDESC10_MSB_INDEX) or -- axi2ip_wrce(TAILDESC11_MSB_INDEX) or -- axi2ip_wrce(TAILDESC12_MSB_INDEX) or -- axi2ip_wrce(TAILDESC13_MSB_INDEX) or -- axi2ip_wrce(TAILDESC14_MSB_INDEX) or -- axi2ip_wrce(TAILDESC15_MSB_INDEX); TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then tailpntr_updated_d1 <= '0'; elsif (tail_update_msb = '1' and tdest_in(5) = '0')then tailpntr_updated_d1 <= '1'; else tailpntr_updated_d1 <= '0'; end if; end if; end process TAILPNTR_UPDT_PROCESS; TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tailpntr_updated_d2 <= '0'; else tailpntr_updated_d2 <= tailpntr_updated_d1; end if; end if; end process TAILPNTR_UPDT_PROCESS_DEL; tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2); end generate GEN_TAILUPDATE_EQL64; end generate GEN_DESC_REG_FOR_SG; -- Generate Buffer Address and Length Register for Simple DMA Mode GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate begin -- Signals not used for simple dma mode, only for sg mode curdesc_lsb_i <= (others => '0'); curdesc_msb_i <= (others => '0'); taildesc_lsb_i <= (others => '0'); taildesc_msb_i <= (others => '0'); -- Extending this to new registers curdesc1_msb_i <= (others => '0'); taildesc1_msb_i <= (others => '0'); curdesc2_msb_i <= (others => '0'); taildesc2_msb_i <= (others => '0'); curdesc3_msb_i <= (others => '0'); taildesc3_msb_i <= (others => '0'); curdesc4_msb_i <= (others => '0'); taildesc4_msb_i <= (others => '0'); curdesc5_msb_i <= (others => '0'); taildesc5_msb_i <= (others => '0'); curdesc6_msb_i <= (others => '0'); taildesc6_msb_i <= (others => '0'); curdesc7_msb_i <= (others => '0'); taildesc7_msb_i <= (others => '0'); curdesc8_msb_i <= (others => '0'); taildesc8_msb_i <= (others => '0'); curdesc9_msb_i <= (others => '0'); taildesc9_msb_i <= (others => '0'); curdesc10_msb_i <= (others => '0'); taildesc10_msb_i <= (others => '0'); curdesc11_msb_i <= (others => '0'); taildesc11_msb_i <= (others => '0'); curdesc12_msb_i <= (others => '0'); taildesc12_msb_i <= (others => '0'); curdesc13_msb_i <= (others => '0'); taildesc13_msb_i <= (others => '0'); curdesc14_msb_i <= (others => '0'); taildesc14_msb_i <= (others => '0'); curdesc15_msb_i <= (others => '0'); taildesc15_msb_i <= (others => '0'); curdesc1_lsb_i <= (others => '0'); taildesc1_lsb_i <= (others => '0'); curdesc2_lsb_i <= (others => '0'); taildesc2_lsb_i <= (others => '0'); curdesc3_lsb_i <= (others => '0'); taildesc3_lsb_i <= (others => '0'); curdesc4_lsb_i <= (others => '0'); taildesc4_lsb_i <= (others => '0'); curdesc5_lsb_i <= (others => '0'); taildesc5_lsb_i <= (others => '0'); curdesc6_lsb_i <= (others => '0'); taildesc6_lsb_i <= (others => '0'); curdesc7_lsb_i <= (others => '0'); taildesc7_lsb_i <= (others => '0'); curdesc8_lsb_i <= (others => '0'); taildesc8_lsb_i <= (others => '0'); curdesc9_lsb_i <= (others => '0'); taildesc9_lsb_i <= (others => '0'); curdesc10_lsb_i <= (others => '0'); taildesc10_lsb_i <= (others => '0'); curdesc11_lsb_i <= (others => '0'); taildesc11_lsb_i <= (others => '0'); curdesc12_lsb_i <= (others => '0'); taildesc12_lsb_i <= (others => '0'); curdesc13_lsb_i <= (others => '0'); taildesc13_lsb_i <= (others => '0'); curdesc14_lsb_i <= (others => '0'); taildesc14_lsb_i <= (others => '0'); curdesc15_lsb_i <= (others => '0'); taildesc15_lsb_i <= (others => '0'); tailpntr_updated <= '0'; error_pointer_set <= '0'; -- Buffer Address register. Used for Source Address (SA) if MM2S -- and used for Destination Address (DA) if S2MM BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_address_i <= (others => '0'); elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then buffer_address_i <= axi2ip_wrdata; end if; end if; end process BUFFER_ADDR_REGISTER; -- Buffer Length register. Used for number of bytes to transfer if MM2S -- and used for size of receive buffer is S2MM BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_length_i <= (others => '0'); -- Update with actual bytes received (Only for S2MM channel) elsif(bytes_received_wren = '1' and C_MICRO_DMA = 0)then buffer_length_i <= bytes_received; elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0); end if; end if; end process BUFFER_LNGTH_REGISTER; -- Buffer Length Write Enable control. Assertion of wren will -- begin a transfer if channel is Idle. BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_length_wren <= '0'; -- Non-zero length value written elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1' and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then buffer_length_wren <= '1'; else buffer_length_wren <= '0'; end if; end if; end process BUFFER_LNGTH_WRITE; end generate GEN_REG_FOR_SMPL; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/FIFO_image_filter_dmask_rows_V.vhd

2

4564

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_dmask_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_dmask_rows_V_shiftReg; architecture rtl of FIFO_image_filter_dmask_rows_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_dmask_rows_V is generic ( MEM_STYLE : string := "shiftreg"; DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_dmask_rows_V is component FIFO_image_filter_dmask_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_dmask_rows_V_shiftReg : FIFO_image_filter_dmask_rows_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

mistryalok/Zedboard

learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/ecc_gen.vhd

8

7490

---------------------------------------------------------------------------------------------- -- -- Generated by X-HDL Verilog Translator - Version 4.0.0 Apr. 30, 2006 -- Wed Jun 17 2009 01:03:24 -- -- Input file : /home/samsonn/SandBox_LBranch_11.2/env/Databases/ip/src2/L/mig_v3_2/data/dlib/virtex6/ddr3_sdram/verilog/rtl/ecc/ecc_gen.v -- Component name : ecc_gen -- Author : -- Company : -- -- Description : -- -- ---------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; -- Generate the ecc code. Note that the synthesizer should -- generate this as a static logic. Code in this block should -- never run during simulation phase, or directly impact timing. -- -- The code generated is a single correct, double detect code. -- It is the classic Hamming code. Instead, the code is -- optimized for minimal/balanced tree depth and size. See -- Hsiao IBM Technial Journal 1970. -- -- The code is returned as a single bit vector, h_rows. This was -- the only way to "subroutinize" this with the restrictions of -- disallowed include files and that matrices cannot be passed -- in ports. -- -- Factorial and the combos functions are defined. Combos -- simply computes the number of combinations from the set -- size and elements at a time. -- -- The function next_combo computes the next combination in -- lexicographical order given the "current" combination. Its -- output is undefined if given the last combination in the -- lexicographical order. -- -- next_combo is insensitive to the number of elements in the -- combinations. -- -- An H transpose matrix is generated because that's the easiest -- way to do it. The H transpose matrix is generated by taking -- the one at a time combinations, then the 3 at a time, then -- the 5 at a time. The number combinations used is equal to -- the width of the code (CODE_WIDTH). The boundaries between -- the 1, 3 and 5 groups are hardcoded in the for loop. -- -- At the same time the h_rows vector is generated from the -- H transpose matrix. entity ecc_gen is generic ( CODE_WIDTH : integer := 72; ECC_WIDTH : integer := 8; DATA_WIDTH : integer := 64 ); port ( -- Outputs -- function next_combo -- Given a combination, return the next combo in lexicographical -- order. Scans from right to left. Assumes the first combination -- is k ones all of the way to the left. -- -- Upon entry, initialize seen0, trig1, and ones. "seen0" means -- that a zero has been observed while scanning from right to left. -- "trig1" means that a one have been observed _after_ seen0 is set. -- "ones" counts the number of ones observed while scanning the input. -- -- If trig1 is one, just copy the input bit to the output and increment -- to the next bit. Otherwise set the the output bit to zero, if the -- input is a one, increment ones. If the input bit is a one and seen0 -- is true, dump out the accumulated ones. Set seen0 to the complement -- of the input bit. Note that seen0 is not used subsequent to trig1 -- getting set. -- The stuff above leads to excessive XST execution times. For now, hardwire to 72/64 bit. h_rows : out std_logic_vector(CODE_WIDTH * ECC_WIDTH - 1 downto 0) ); end entity ecc_gen; architecture trans of ecc_gen is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of trans : architecture is "yes"; function factorial (ivar: integer) return integer is variable tmp : integer; begin if (ivar = 1) then return 1; else tmp := 1; for i in ivar downto 2 loop tmp := tmp * i; end loop; end if; return tmp; end function factorial; function combos ( n, k: integer) return integer is begin return factorial(n)/(factorial(k)*factorial(n-k)); end function combos; function next_combo (i: std_logic_vector) return std_logic_vector is variable seen0: std_logic; variable trig1: std_logic; variable ones: std_logic_vector (ECC_WIDTH-1 downto 0); variable tmp: std_logic_vector (ECC_WIDTH-1 downto 0); variable tmp_index : integer; begin seen0 := '0'; trig1 := '0'; ones := (others => '0'); for index in ECC_WIDTH -1 downto 0 loop tmp_index := ECC_WIDTH -1 - index; if (trig1 = '1') then tmp(tmp_index) := i(tmp_index); else tmp(tmp_index) := '0'; ones := ones + i(tmp_index); if ((i(tmp_index) = '1') and (seen0 = '1')) then trig1 := '1'; for dump_index in tmp_index-1 downto 0 loop if (dump_index >= (tmp_index- conv_integer(ones)) ) then tmp(dump_index) := '1'; end if; end loop; end if; seen0 := not(i(tmp_index)); end if; end loop; return tmp; end function next_combo; constant COMBOS_3 : integer := combos(ECC_WIDTH, 3); constant COMBOS_5 : integer := combos(ECC_WIDTH, 5); type twoDarray is array (CODE_WIDTH -1 downto 0) of std_logic_vector (ECC_WIDTH-1 downto 0); signal ht_matrix : twoDarray; begin columns: for n in CODE_WIDTH - 1 downto 0 generate column0: if (n = 0) generate ht_matrix(n) <= "111" & conv_std_logic_vector(0,ECC_WIDTH-3); end generate; column_combos3: if ((n = COMBOS_3) and ( n < DATA_WIDTH) ) generate ht_matrix(n) <= "11111" & conv_std_logic_vector(0,ECC_WIDTH-5); end generate; column_combos5: if ((n = COMBOS_3 + COMBOS_5) and ( n < DATA_WIDTH) ) generate ht_matrix(n) <= "1111111" & conv_std_logic_vector(0,ECC_WIDTH-7); end generate; column_datawidth: if (n = DATA_WIDTH) generate ht_matrix(n) <= "1" & conv_std_logic_vector(0,ECC_WIDTH-1); end generate; column_gen: if ( (n /= 0 ) and ((n /= COMBOS_3) or (n > DATA_WIDTH)) and ((n /= COMBOS_3+COMBOS_5) or (n > DATA_WIDTH)) and (n /= DATA_WIDTH) ) generate ht_matrix(n) <= next_combo(ht_matrix(n-1)); end generate; out_assign: for s in ECC_WIDTH-1 downto 0 generate h_rows(s*CODE_WIDTH+n) <= ht_matrix(n)(s); end generate; end generate; --h_row0 <= "100000000100100011101101001101001000110100100010000110100100010000100000"; --h_row1 <= "010000001010010011011010101010100100101010010001000101010010001000010000"; --h_row2 <= "001000001001001010110110010110010010011001001000100011001001000100001000"; --h_row3 <= "000100000111000101110001110001110001000111000100010000111000100010000100"; --h_row4 <= "000010000000111100001111110000001111000000111100001000000111100001000010"; --h_row5 <= "000001001111111100000000001111111111000000000011111000000000011111000001"; --h_row6 <= "000000101111111100000000000000000000111111111111111000000000000000111111"; --h_row7 <= "000000011111111100000000000000000000000000000000000111111111111111111111"; --h_rows <= (h_row7 & h_row6 & h_row5 & h_row4 & h_row3 & h_row2 & h_row1 & h_row0); end architecture trans;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_s2mm.vhd

3

17013

-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; library lib_fifo_v1_0; use lib_fifo_v1_0.async_fifo_fg; entity axi_dma_s2mm is generic ( C_FAMILY : string := "virtex7" ); port ( clk_in : in std_logic; sg_clk : in std_logic; resetn : in std_logic; reset_sg : in std_logic; s2mm_tvalid : in std_logic; s2mm_tlast : in std_logic; s2mm_tdest : in std_logic_vector (4 downto 0); s2mm_tuser : in std_logic_vector (3 downto 0); s2mm_tid : in std_logic_vector (4 downto 0); s2mm_tready : in std_logic; desc_available : in std_logic; -- s2mm_eof : in std_logic; s2mm_eof_det : in std_logic_vector (1 downto 0); ch2_update_active : in std_logic; tdest_out : out std_logic_vector (6 downto 0); -- to select desc same_tdest : out std_logic; -- to select desc -- to DM s2mm_desc_info : out std_logic_vector (13 downto 0); -- updt_cmpt : out std_logic; s2mm_tvalid_out : out std_logic; s2mm_tlast_out : out std_logic; s2mm_tready_out : out std_logic; s2mm_tdest_out : out std_logic_vector (4 downto 0) ); end entity axi_dma_s2mm; architecture implementation of axi_dma_s2mm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; signal first_data : std_logic; signal first_stream : std_logic; signal first_stream_del : std_logic; signal last_received : std_logic; signal first_received : std_logic; signal first_received1 : std_logic; signal open_window : std_logic; signal tdest_out_int : std_logic_vector (6 downto 0); signal fifo_wr : std_logic; signal last_update_over_int : std_logic; signal last_update_over_int1 : std_logic; signal last_update_over : std_logic; signal ch_updt_over_int : std_logic; signal ch_updt_over_int_cdc_from : std_logic; signal ch_updt_over_int_cdc_to : std_logic; signal ch_updt_over_int_cdc_to1 : std_logic; signal ch_updt_over_int_cdc_to2 : std_logic; -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; --ATTRIBUTE async_reg OF ch_updt_over_int_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF ch_updt_over_int_cdc_to1 : SIGNAL IS "true"; signal fifo_rd : std_logic; signal first_read : std_logic; signal first_rd_en : std_logic; signal fifo_rd_int : std_logic; signal first_read_int : std_logic; signal fifo_empty : std_logic; signal fifo_full : std_logic; signal s2mm_desc_info_int : std_logic_vector (13 downto 0); signal updt_cmpt : std_logic; signal tdest_capture : std_logic_vector (4 downto 0); signal noread : std_logic; signal same_tdest_b2b : std_logic; signal fifo_reset : std_logic; begin process (sg_clk) begin if (sg_clk'event and sg_clk = '1') then if (reset_sg = '0') then ch_updt_over_int_cdc_from <= '0'; else --if (sg_clk'event and sg_clk = '1') then ch_updt_over_int_cdc_from <= ch2_update_active; end if; end if; end process; process (clk_in) begin if (clk_in'event and clk_in = '1') then if (resetn = '0') then ch_updt_over_int_cdc_to <= '0'; ch_updt_over_int_cdc_to1 <= '0'; ch_updt_over_int_cdc_to2 <= '0'; else --if (clk_in'event and clk_in = '1') then ch_updt_over_int_cdc_to <= ch_updt_over_int_cdc_from; ch_updt_over_int_cdc_to1 <= ch_updt_over_int_cdc_to; ch_updt_over_int_cdc_to2 <= ch_updt_over_int_cdc_to1; end if; end if; end process; updt_cmpt <= (not ch_updt_over_int_cdc_to1) and ch_updt_over_int_cdc_to2; -- process (sg_clk) -- begin -- if (resetn = '0') then -- ch_updt_over_int <= '0'; -- elsif (sg_clk'event and sg_clk = '1') then -- ch_updt_over_int <= ch2_update_active; -- end if; -- end process; -- updt_cmpt <= (not ch2_update_active) and ch_updt_over_int; process (sg_clk) begin if (sg_clk'event and sg_clk = '1') then if (reset_sg = '0') then last_update_over_int <= '0'; last_update_over_int1 <= '0'; noread <= '0'; -- else --if (sg_clk'event and sg_clk = '1') then last_update_over_int1 <= last_update_over_int; elsif (s2mm_eof_det(1) = '1' and noread = '0') then last_update_over_int <= '1'; noread <= '1'; elsif (s2mm_eof_det(0) = '1') then noread <= '0'; last_update_over_int <= '0'; elsif (fifo_empty = '0') then -- (updt_cmpt = '1') then last_update_over_int <= '0'; else last_update_over_int <= last_update_over_int; end if; end if; -- end if; end process; last_update_over <= (not last_update_over_int) and last_update_over_int1; process (sg_clk) begin if (sg_clk'event and sg_clk = '1') then if (reset_sg = '0') then fifo_rd_int <= '0'; first_read <= '0'; -- else --if (sg_clk'event and sg_clk = '1') then elsif (last_update_over_int = '1' and fifo_rd_int = '0') then fifo_rd_int <= '1'; else fifo_rd_int <= '0'; end if; end if; end process; process (sg_clk) begin if (sg_clk'event and sg_clk = '1') then if (reset_sg = '0') then first_read_int <= '0'; else --if (sg_clk'event and sg_clk = '1') then first_read_int <= first_read; end if; end if; end process; first_rd_en <= first_read and (not first_read_int); fifo_rd <= last_update_over_int; --(fifo_rd_int or first_rd_en); -- process (clk_in) -- begin -- if (resetn = '0') then -- first_data <= '0'; -- first_stream_del <= '0'; -- elsif (clk_in'event and clk_in = '1') then -- if (s2mm_tvalid = '1' and first_data = '0' and s2mm_tready = '1') then -- no tlast -- first_data <= '1'; -- just after the system comes out of reset -- end if; -- first_stream_del <= first_stream; -- end if; -- end process; first_stream <= (s2mm_tvalid and (not first_data)); -- pulse when first stream comes after reset process (clk_in) begin if (clk_in'event and clk_in = '1') then if (resetn = '0') then first_received1 <= '0'; first_stream_del <= '0'; else --if (clk_in'event and clk_in = '1') then first_received1 <= first_received; --'0'; first_stream_del <= first_stream; end if; end if; end process; process (clk_in) begin if (clk_in'event and clk_in = '1') then if (resetn = '0') then last_received <= '0'; first_received <= '0'; tdest_capture <= (others => '0'); first_data <= '0'; -- else --if (clk_in'event and clk_in = '1') then elsif (s2mm_tvalid = '1' and first_data = '0' and s2mm_tready = '1') then -- first stream afetr reset s2mm_desc_info_int <= s2mm_tuser & s2mm_tid & s2mm_tdest; tdest_capture <= s2mm_tdest; -- latching tdest on first beat first_data <= '1'; -- just after the system comes out of reset elsif (s2mm_tlast = '1' and s2mm_tvalid = '1' and s2mm_tready = '1') then -- catch for last beat last_received <= '1'; first_received <= '0'; s2mm_desc_info_int <= s2mm_desc_info_int; elsif (last_received = '1' and s2mm_tvalid = '1' and s2mm_tready = '1') then -- catch for following first beat last_received <= '0'; first_received <= '1'; tdest_capture <= s2mm_tdest; -- latching tdest on first beat s2mm_desc_info_int <= s2mm_tuser & s2mm_tid & s2mm_tdest; else s2mm_desc_info_int <= s2mm_desc_info_int; last_received <= last_received; if (updt_cmpt = '1') then first_received <= '0'; else first_received <= first_received; -- hold the first received until update comes for previous tlast end if; end if; end if; end process; fifo_wr <= first_stream_del or (first_received and not (first_received1)); -- writing the tdest,tuser,tid into FIFO process (clk_in) begin if (clk_in'event and clk_in = '1') then if (resetn = '0') then tdest_out_int <= "0100000"; same_tdest_b2b <= '0'; -- else --if (clk_in'event and clk_in = '1') then elsif (first_received = '1' or first_stream = '1') then if (first_stream = '1') then -- when first stream is received, capture the tdest tdest_out_int (6) <= not tdest_out_int (6); -- signifies a new stream has come tdest_out_int (5 downto 0) <= '0' & s2mm_tdest; same_tdest_b2b <= '0'; -- elsif (updt_cmpt = '1' or (first_received = '1' and first_received1 = '0')) then -- when subsequent streams are received, pass the latched value of tdest -- elsif (first_received = '1' and first_received1 = '0') then -- when subsequent streams are received, pass the latched value of tdest -- Following change made to allow b2b same channel pkt elsif ((first_received = '1' and first_received1 = '0') and (tdest_out_int (4 downto 0) /= tdest_capture)) then -- when subsequent streams are received, pass the latched value of tdest tdest_out_int (6) <= not tdest_out_int (6); tdest_out_int (5 downto 0) <= '0' & tdest_capture; --s2mm_tdest; elsif (first_received = '1' and first_received1 = '0') then same_tdest_b2b <= not (same_tdest_b2b); end if; else tdest_out_int <= tdest_out_int; end if; end if; end process; tdest_out <= tdest_out_int; same_tdest <= same_tdest_b2b; process (clk_in) begin if (clk_in'event and clk_in = '1') then if (resetn = '0') then open_window <= '0'; -- else --if (clk_in'event and clk_in = '1') then elsif (desc_available = '1') then open_window <= '1'; elsif (s2mm_tlast = '1') then open_window <= '0'; else open_window <= open_window; end if; end if; end process; process (clk_in) begin if (clk_in'event and clk_in = '1') then if (resetn = '0') then s2mm_tvalid_out <= '0'; s2mm_tready_out <= '0'; s2mm_tlast_out <= '0'; s2mm_tdest_out <= "00000"; -- else --if (clk_in'event and clk_in = '1') then elsif (open_window = '1') then s2mm_tvalid_out <= s2mm_tvalid; s2mm_tready_out <= s2mm_tready; s2mm_tlast_out <= s2mm_tlast; s2mm_tdest_out <= s2mm_tdest; else s2mm_tready_out <= '0'; s2mm_tvalid_out <= '0'; s2mm_tlast_out <= '0'; s2mm_tdest_out <= "00000"; end if; end if; end process; fifo_reset <= not (resetn); -- s2mm_desc_info_int <= s2mm_tuser & s2mm_tid & s2mm_tdest; -- Following FIFO is used to store the Tuser, Tid and xCache info I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.async_fifo_fg generic map ( -- C_ALLOW_2N_DEPTH => 1, C_ALLOW_2N_DEPTH => 0, C_FAMILY => C_FAMILY, C_DATA_WIDTH => 14, C_ENABLE_RLOCS => 0, C_FIFO_DEPTH => 31, C_HAS_ALMOST_EMPTY => 1, C_HAS_ALMOST_FULL => 1, C_HAS_RD_ACK => 1, C_HAS_RD_COUNT => 1, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 0, C_HAS_WR_COUNT => 1, C_HAS_WR_ERR => 0, C_RD_ACK_LOW => 0, C_RD_COUNT_WIDTH => 5, C_RD_ERR_LOW => 0, C_USE_BLOCKMEM => 0, C_WR_ACK_LOW => 0, C_WR_COUNT_WIDTH => 5, C_WR_ERR_LOW => 0, C_SYNCHRONIZER_STAGE => C_FIFO_MTBF -- C_USE_EMBEDDED_REG => 1, -- 0 ; -- C_PRELOAD_REGS => 0, -- 0 ; -- C_PRELOAD_LATENCY => 1 -- 1 ; ) port Map ( Din => s2mm_desc_info_int, Wr_en => fifo_wr, Wr_clk => clk_in, Rd_en => fifo_rd, Rd_clk => sg_clk, Ainit => fifo_reset, Dout => s2mm_desc_info, Full => fifo_Full, Empty => fifo_empty, Almost_full => open, Almost_empty => open, Wr_count => open, Rd_count => open, Rd_ack => open, Rd_err => open, -- Not used by axi_dma Wr_ack => open, -- Not used by axi_dma Wr_err => open -- Not used by axi_dma ); end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/lib_srl_fifo_v1_0/292dd5ac/hdl/src/vhdl/srl_fifo_f.vhd

11

9367

-- srl_fifo_f - entity / architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: srl_fifo_f.vhd -- -- Description: A small-to-medium depth FIFO. For -- data storage, the SRL elements native to the -- target FGPA family are used. If the FIFO depth -- exceeds the available depth of the SRL elements, -- then SRLs are cascaded and MUXFN elements are -- used to select the output of the appropriate SRL stage. -- -- Features: -- - Width and depth are arbitrary, but each doubling of -- depth, starting from the native SRL depth, adds -- a level of MUXFN. Generally, in performance-oriented -- applications, the fifo depth may need to be limited to -- not exceed the SRL cascade depth supported by local -- fast interconnect or the number of MUXFN levels. -- However, deeper fifos will correctly build. -- - Commands: read, write. -- - Flags: empty and full. -- - The Addr output is always one less than the current -- occupancy when the FIFO is non-empty, and is all ones -- otherwise. Therefore, the value <FIFO_Empty, Addr>-- -- i.e. FIFO_Empty concatenated on the left to Addr-- -- when taken as a signed value, is one less than the -- current occupancy. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- srl_fifo_f.vhd -- srl_fifo_rbu_f.vhd -- proc_common_pkg.vhd -- ------------------------------------------------------------------------------- -- Author: Farrell Ostler -- -- History: -- FLO 12/13/05 First Version. -- -- FLO 04/27/06 -- ^^^^^^ -- C_FAMILY made to default to "nofamily". -- ~~~~~~ -- FLO 2007-12-12 -- ^^^^^^ -- Using function clog2 now instead of log2 to eliminate superfluous warnings. -- ~~~~~~ -- -- DET 1/17/2008 v5_0 -- ~~~~~~ -- - Changed proc_common library version to v5_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- -- predecessor value by # clks: "*_p#" library ieee; use ieee.std_logic_1164.all; library lib_srl_fifo_v1_0; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.clog2; -- entity srl_fifo_f is generic ( C_DWIDTH : natural; C_DEPTH : positive := 16; C_FAMILY : string := "nofamily" ); port ( Clk : in std_logic; Reset : in std_logic; FIFO_Write : in std_logic; Data_In : in std_logic_vector(0 to C_DWIDTH-1); FIFO_Read : in std_logic; Data_Out : out std_logic_vector(0 to C_DWIDTH-1); FIFO_Empty : out std_logic; FIFO_Full : out std_logic; Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1) ); end entity srl_fifo_f; -- architecture imp of srl_fifo_f is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0'); begin I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0.srl_fifo_rbu_f generic map ( C_DWIDTH => C_DWIDTH, C_DEPTH => C_DEPTH, C_FAMILY => C_FAMILY ) port map ( Clk => Clk, Reset => Reset, FIFO_Write => FIFO_Write, Data_In => Data_In, FIFO_Read => FIFO_Read, Data_Out => Data_Out, FIFO_Full => FIFO_Full, FIFO_Empty => FIFO_Empty, Addr => Addr, Num_To_Reread => ZEROES, Underflow => open, Overflow => open ); end architecture imp;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/axi_lite.vhd

7

95564

------------------------------------------------------------------------------- -- axi_lite.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: axi_lite.vhd -- -- Description: This file is the top level module for the AXI-Lite -- instantiation of the BRAM controller interface. -- -- Responsible for shared address pipelining between the -- write address (AW) and read address (AR) channels. -- Controls (seperately) the data flows for the write data -- (W), write response (B), and read data (R) channels. -- -- Creates a shared port to BRAM (for all read and write -- transactions) or dual BRAM port utilization based on a -- generic parameter setting. -- -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- ecc_gen.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/22/2011 v1.03a -- ~~~~~~ -- Update BRAM address mapping to lite_ecc_reg module. Corrected -- signal size for XST detected unused bits in vector. -- Plus minor code cleanup. -- -- Add top level parameter, C_ECC_TYPE for Hsiao ECC algorithm. -- ^^^^^^ -- JLJ 2/23/2011 v1.03a -- ~~~~~~ -- Add Hsiao ECC algorithm logic (similar to full_axi module HDL). -- ^^^^^^ -- JLJ 2/24/2011 v1.03a -- ~~~~~~ -- Move REG_RDATA register process out from C_ECC_TYPE generate block -- to C_ECC generate block. -- ^^^^^^ -- JLJ 3/22/2011 v1.03a -- ~~~~~~ -- Add LUT level with reset signal to combinatorial outputs, AWREADY -- and WREADY. This will ensure that the output remains LOW during reset, -- regardless of AWVALID or WVALID input signals. -- ^^^^^^ -- JLJ 3/28/2011 v1.03a -- ~~~~~~ -- Remove combinatorial output paths on AWREADY and WREADY. -- Combine AWREADY and WREADY registers. -- Remove combinatorial output path on ARREADY. Can pre-assert ARREADY -- (but only for non ECC configurations). -- Create 3-bit counter for BVALID response, seperate from AW/W channels. -- -- Delay assertion of WREADY in ECC configurations to minimize register -- resource utilization. -- No pre-assertion of ARREADY in ECC configurations (due to write latency -- with ECC enabled). -- -- ^^^^^^ -- JLJ 3/30/2011 v1.03a -- ~~~~~~ -- Update Sl_CE and Sl_UE flag assertions to a single clock cycle. -- Clean up comments. -- ^^^^^^ -- JLJ 4/19/2011 v1.03a -- ~~~~~~ -- Update BVALID assertion when ECC is enabled to match the implementation -- when C_ECC = 0. Optimize back to back write performance when C_ECC = 1. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Modify FaultInjectClr signal assertion. With BVALID counter, delay -- when fault inject register gets cleared. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Code clean up. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove usage of C_FAMILY. -- Hard code C_USE_LUT6 constant. -- ^^^^^^ -- JLJ 7/7/2011 v1.03a -- ~~~~~~ -- Fix DV regression failure with reset. -- Hold off BRAM enable output with active reset signal. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.lite_ecc_reg; use work.parity; use work.checkbit_handler; use work.correct_one_bit; use work.ecc_gen; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity axi_lite is generic ( C_S_AXI_PROTOCOL : string := "AXI4LITE"; -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_SINGLE_PORT_BRAM : integer := 1; -- Enable single port usage of BRAM -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_TYPE : integer := 0; -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Interface Signals -- AXI Clock and Reset S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; ECC_Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- *** AXI Write Address Channel Signals (AW) *** AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); AXI_AWVALID : in std_logic; AXI_AWREADY : out std_logic; -- Unused AW AXI-Lite Signals -- AXI_AWID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); -- AXI_AWLEN : in std_logic_vector(7 downto 0); -- AXI_AWSIZE : in std_logic_vector(2 downto 0); -- AXI_AWBURST : in std_logic_vector(1 downto 0); -- AXI_AWLOCK : in std_logic; -- Currently unused -- AXI_AWCACHE : in std_logic_vector(3 downto 0); -- Currently unused -- AXI_AWPROT : in std_logic_vector(2 downto 0); -- Currently unused -- *** AXI Write Data Channel Signals (W) *** AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0); AXI_WVALID : in std_logic; AXI_WREADY : out std_logic; -- Unused W AXI-Lite Signals -- AXI_WLAST : in std_logic; -- *** AXI Write Data Response Channel Signals (B) *** AXI_BRESP : out std_logic_vector(1 downto 0); AXI_BVALID : out std_logic; AXI_BREADY : in std_logic; -- Unused B AXI-Lite Signals -- AXI_BID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); -- *** AXI Read Address Channel Signals (AR) *** AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); AXI_ARVALID : in std_logic; AXI_ARREADY : out std_logic; -- *** AXI Read Data Channel Signals (R) *** AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); AXI_RRESP : out std_logic_vector(1 downto 0); AXI_RLAST : out std_logic; AXI_RVALID : out std_logic; AXI_RREADY : in std_logic; -- *** AXI-Lite ECC Register Interface Signals *** -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk : in std_logic; -- S_AXI_CTRL_AResetn : in std_logic; -- AXI-Lite Write Address Channel Signals (AW) AXI_CTRL_AWVALID : in std_logic; AXI_CTRL_AWREADY : out std_logic; AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_WVALID : in std_logic; AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); AXI_CTRL_BVALID : out std_logic; AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); AXI_CTRL_ARVALID : in std_logic; AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); AXI_CTRL_RVALID : out std_logic; AXI_CTRL_RREADY : in std_logic; -- *** BRAM Port A Interface Signals *** -- Note: Clock handled at top level (axi_bram_ctrl module) BRAM_En_A : out std_logic; BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0); BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC -- Note: Remove BRAM_RdData_A port (unused in dual port mode) -- Platgen will keep port open on BRAM block -- *** BRAM Port B Interface Signals *** -- Note: Clock handled at top level (axi_bram_ctrl module) BRAM_En_B : out std_logic; BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0); BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) -- @ port level = 8-bits wide ECC ); end entity axi_lite; ------------------------------------------------------------------------------- architecture implementation of axi_lite is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- All functions defined in axi_bram_ctrl_funcs package. ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_RESET_ACTIVE : std_logic := '0'; constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error -- For future implementation. -- constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response -- constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error -- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width -- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00" -- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000" -- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000" -- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000" constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8); constant C_BRAM_ADDR_ADJUST : integer := C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR; constant C_AXI_DATA_WIDTH_BYTES : integer := C_S_AXI_DATA_WIDTH/8; -- Internal data width based on C_S_AXI_DATA_WIDTH. constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH); -- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6; -- Remove usage of C_FAMILY. -- All architectures supporting AXI will support a LUT6. -- Hard code this internal constant used in ECC algorithm. -- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6; constant C_USE_LUT6 : boolean := TRUE; ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal axi_aresetn_d1 : std_logic := '0'; signal axi_aresetn_re : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Write & Read Address Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type LITE_SM_TYPE is ( IDLE, SNG_WR_DATA, RD_DATA, RMW_RD_DATA, RMW_MOD_DATA, RMW_WR_DATA ); signal lite_sm_cs, lite_sm_ns : LITE_SM_TYPE; signal axi_arready_cmb : std_logic := '0'; signal axi_arready_reg : std_logic := '0'; signal axi_arready_int : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Write Data Channel Signals ------------------------------------------------------------------------------- signal axi_wready_cmb : std_logic := '0'; signal axi_wready_int : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Write Response Channel Signals ------------------------------------------------------------------------------- signal axi_bresp_int : std_logic_vector (1 downto 0) := (others => '0'); signal axi_bvalid_int : std_logic := '0'; signal bvalid_cnt_inc : std_logic := '0'; signal bvalid_cnt_inc_d1 : std_logic := '0'; signal bvalid_cnt_dec : std_logic := '0'; signal bvalid_cnt : std_logic_vector (2 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- AXI Read Data Channel Signals ------------------------------------------------------------------------------- signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0'); signal axi_rvalid_set : std_logic := '0'; signal axi_rvalid_set_r : std_logic := '0'; signal axi_rvalid_int : std_logic := '0'; signal axi_rlast_set : std_logic := '0'; signal axi_rlast_set_r : std_logic := '0'; signal axi_rlast_int : std_logic := '0'; signal axi_rdata_int : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal axi_rdata_int_corr : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Internal BRAM Signals ------------------------------------------------------------------------------- signal bram_we_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0) := (others => '0'); signal bram_en_a_cmb : std_logic := '0'; signal bram_en_b_cmb : std_logic := '0'; signal bram_en_a_int : std_logic := '0'; signal bram_en_b_int : std_logic := '0'; signal bram_addr_a_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_a_int_q : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_b_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal bram_wrdata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Port level signal, 8-bits ECC ------------------------------------------------------------------------------- -- Internal ECC Signals ------------------------------------------------------------------------------- signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register signal Sl_CE : std_logic := '0'; -- Correctable Error Flag signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag signal Sl_CE_i : std_logic := '0'; signal Sl_UE_i : std_logic := '0'; signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal FaultInjectECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width signal CorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal UnCorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal CE_Q : std_logic := '0'; signal UE_Q : std_logic := '0'; signal Enable_ECC : std_logic := '0'; signal RdModifyWr_Read : std_logic := '0'; -- Read cycle in read modify write sequence signal RdModifyWr_Check : std_logic := '0'; -- Read cycle in read modify write sequence signal RdModifyWr_Modify : std_logic := '0'; -- Modify cycle in read modify write sequence signal RdModifyWr_Write : std_logic := '0'; -- Write cycle in read modify write sequence signal WrData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal WrData_cmb : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal Active_Wr : std_logic := '0'; signal BRAM_Addr_En : std_logic := '0'; signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Specific to 32-bit ECC signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to 32-bit ECC signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Specific for 32-bit ECC signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- *** AXI-Lite ECC Register Output Signals *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NO_REGS -- Purpose: Generate default values if ECC registers are disabled (or when -- ECC is disabled). -- Include both AXI-Lite default signal values & internal -- core signal values. --------------------------------------------------------------------------- -- For future implementation. -- GEN_NO_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) or (C_ECC = 0) generate GEN_NO_REGS: if (C_ECC = 0) generate begin AXI_CTRL_AWREADY <= '0'; AXI_CTRL_WREADY <= '0'; AXI_CTRL_BRESP <= (others => '0'); AXI_CTRL_BVALID <= '0'; AXI_CTRL_ARREADY <= '0'; AXI_CTRL_RDATA <= (others => '0'); AXI_CTRL_RRESP <= (others => '0'); AXI_CTRL_RVALID <= '0'; -- No fault injection FaultInjectData <= (others => '0'); FaultInjectECC <= (others => '0'); -- Interrupt only enabled when ECC status/interrupt registers enabled ECC_Interrupt <= '0'; ECC_UE <= '0'; BRAM_Addr_En <= '0'; ----------------------------------------------------------------------- -- Generate: GEN_DIS_ECC -- Purpose: Disable ECC in read path when ECC is disabled in core. ----------------------------------------------------------------------- GEN_DIS_ECC: if C_ECC = 0 generate Enable_ECC <= '0'; end generate GEN_DIS_ECC; -- For future implementation. -- -- ----------------------------------------------------------------------- -- -- Generate: GEN_EN_ECC -- -- Purpose: Enable ECC when C_ECC = 1 and no ECC registers are available. -- -- ECC on/off control register is not accessible (so ECC is always -- -- enabled in this configuraiton). -- ----------------------------------------------------------------------- -- GEN_EN_ECC: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) generate -- Enable_ECC <= '1'; -- ECC ON/OFF register can not be enabled (as no ECC -- -- ECC registers are available. Therefore, ECC -- -- is always enabled. -- end generate GEN_EN_ECC; end generate GEN_NO_REGS; --------------------------------------------------------------------------- -- Generate: GEN_REGS -- Purpose: Generate ECC register module when ECC is enabled and -- ECC registers are enabled. --------------------------------------------------------------------------- -- For future implementation. -- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate GEN_REGS: if (C_ECC = 1) generate begin --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- Description: This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. --------------------------------------------------------------------------- I_LITE_ECC_REG : entity work.lite_ecc_reg generic map ( C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width C_FAULT_INJECT => C_FAULT_INJECT , C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS , C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS , C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS , C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER , C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE , C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH ) port map ( S_AXI_AClk => S_AXI_AClk , -- AXI clock S_AXI_AResetn => S_AXI_AResetn , -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock -- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn , Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , AXI_CTRL_AWVALID => AXI_CTRL_AWVALID , AXI_CTRL_AWREADY => AXI_CTRL_AWREADY , AXI_CTRL_AWADDR => AXI_CTRL_AWADDR , AXI_CTRL_WDATA => AXI_CTRL_WDATA , AXI_CTRL_WVALID => AXI_CTRL_WVALID , AXI_CTRL_WREADY => AXI_CTRL_WREADY , AXI_CTRL_BRESP => AXI_CTRL_BRESP , AXI_CTRL_BVALID => AXI_CTRL_BVALID , AXI_CTRL_BREADY => AXI_CTRL_BREADY , AXI_CTRL_ARADDR => AXI_CTRL_ARADDR , AXI_CTRL_ARVALID => AXI_CTRL_ARVALID , AXI_CTRL_ARREADY => AXI_CTRL_ARREADY , AXI_CTRL_RDATA => AXI_CTRL_RDATA , AXI_CTRL_RRESP => AXI_CTRL_RRESP , AXI_CTRL_RVALID => AXI_CTRL_RVALID , AXI_CTRL_RREADY => AXI_CTRL_RREADY , Enable_ECC => Enable_ECC , FaultInjectClr => FaultInjectClr , CE_Failing_We => CE_Failing_We , CE_CounterReg_Inc => CE_Failing_We , Sl_CE => Sl_CE , Sl_UE => Sl_UE , BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a BRAM_Addr_En => BRAM_Addr_En , Active_Wr => Active_Wr , FaultInjectData => FaultInjectData , FaultInjectECC => FaultInjectECC ); FaultInjectClr <= '1' when (bvalid_cnt_inc_d1 = '1') else '0'; CE_Failing_We <= '1' when Enable_ECC = '1' and CE_Q = '1' else '0'; Active_Wr <= '1' when (RdModifyWr_Read = '1' or RdModifyWr_Check = '1' or RdModifyWr_Modify = '1' or RdModifyWr_Write = '1') else '0'; ----------------------------------------------------------------------- -- Add register delay on BVALID counter increment -- Used to clear fault inject register. REG_BVALID_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then bvalid_cnt_inc_d1 <= '0'; else bvalid_cnt_inc_d1 <= bvalid_cnt_inc; end if; end if; end process REG_BVALID_CNT; ----------------------------------------------------------------------- end generate GEN_REGS; --------------------------------------------------------------------------- -- *** AXI Output Signals *** --------------------------------------------------------------------------- -- AXI Write Address Channel Output Signals -- AXI_AWREADY <= axi_awready_cmb; -- AXI_AWREADY <= '0' when (S_AXI_AResetn = '0') else axi_awready_cmb; -- v1.03a AXI_AWREADY <= axi_wready_int; -- v1.03a -- AXI Write Data Channel Output Signals -- AXI_WREADY <= axi_wready_cmb; -- AXI_WREADY <= '0' when (S_AXI_AResetn = '0') else axi_wready_cmb; -- v1.03a AXI_WREADY <= axi_wready_int; -- v1.03a -- AXI Write Response Channel Output Signals AXI_BRESP <= axi_bresp_int; AXI_BVALID <= axi_bvalid_int; -- AXI Read Address Channel Output Signals -- AXI_ARREADY <= axi_arready_cmb; -- v1.03a AXI_ARREADY <= axi_arready_int; -- v1.03a -- AXI Read Data Channel Output Signals -- AXI_RRESP <= axi_rresp_int; AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int; -- AXI_RDATA <= axi_rdata_int; -- Move assignment of RDATA to generate statements based on C_ECC. AXI_RVALID <= axi_rvalid_int; AXI_RLAST <= axi_rlast_int; ---------------------------------------------------------------------------- -- Need to detect end of reset cycle to assert AWREADY on AXI bus REG_ARESETN: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then axi_aresetn_d1 <= S_AXI_AResetn; end if; end process REG_ARESETN; -- Create combinatorial RE detect of S_AXI_AResetn axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0'; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- *** AXI Write Address Channel Interface *** --------------------------------------------------------------------------- -- Notes: -- No address pipelining for AXI-Lite. -- PDR feedback. -- Remove address register stage to BRAM. -- Rely on registers in AXI Interconnect. --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Generate all valid bits in the address(es) to BRAM. -- If dual port, generate Port B address signal. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin --------------------------------------------------------------------------- -- Generate: GEN_ADDR_SNG_PORT -- Purpose: Generate BRAM address when a single port to BRAM. -- Mux read and write addresses from AXI AW and AR channels. --------------------------------------------------------------------------- GEN_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate begin -- Read takes priority over AWADDR -- bram_addr_a_int (i) <= AXI_ARADDR (i) when (AXI_ARVALID = '1') else AXI_AWADDR (i); -- ISE should optimize away this mux when connected to the AXI Interconnect -- as the AXI Interconnect duplicates the write or read address on both channels. -- v1.03a -- ARVALID may get asserted while handling ECC read-modify-write. -- With the delay in assertion of AWREADY/WREADY, must add some logic to the -- control on this mux select. bram_addr_a_int (i) <= AXI_ARADDR (i) when ((AXI_ARVALID = '1' and (lite_sm_cs = IDLE or lite_sm_cs = SNG_WR_DATA)) or (lite_sm_cs = RD_DATA)) else AXI_AWADDR (i); end generate GEN_ADDR_SNG_PORT; --------------------------------------------------------------------------- -- Generate: GEN_ADDR_DUAL_PORT -- Purpose: Generate BRAM address when a single port to BRAM. -- Mux read and write addresses from AXI AW and AR channels. --------------------------------------------------------------------------- GEN_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate begin bram_addr_a_int (i) <= AXI_AWADDR (i); bram_addr_b_int (i) <= AXI_ARADDR (i); end generate GEN_ADDR_DUAL_PORT; end generate GEN_ADDR; --------------------------------------------------------------------------- -- *** AXI Read Address Channel Interface *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_ARREADY -- Purpose: Only pre-assert ARREADY for non ECC designs. -- With ECC, a write requires a read-modify-write and -- will miss the address associated with the ARVALID -- (due to the # of clock cycles). --------------------------------------------------------------------------- GEN_ARREADY: if (C_ECC = 0) generate begin REG_ARREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- ARREADY is asserted until we detect the ARVALID. -- Check for back-to-back ARREADY assertions (add axi_arready_int). if (S_AXI_AResetn = C_RESET_ACTIVE) or (AXI_ARVALID = '1' and axi_arready_int = '1') then axi_arready_int <= '0'; -- Then ARREADY is asserted again when the read operation completes. elsif (axi_aresetn_re = '1') or (axi_rlast_int = '1' and AXI_RREADY = '1') then axi_arready_int <= '1'; else axi_arready_int <= axi_arready_int; end if; end if; end process REG_ARREADY; end generate GEN_ARREADY; --------------------------------------------------------------------------- -- Generate: GEN_ARREADY_ECC -- Purpose: Generate ARREADY from SM logic. ARREADY is not pre-asserted -- as in the non ECC configuration. --------------------------------------------------------------------------- GEN_ARREADY_ECC: if (C_ECC = 1) generate begin axi_arready_int <= axi_arready_reg; end generate GEN_ARREADY_ECC; --------------------------------------------------------------------------- -- *** AXI Write Data Channel Interface *** --------------------------------------------------------------------------- -- No AXI_WLAST --------------------------------------------------------------------------- -- Generate: GEN_WRDATA -- Purpose: Generate BRAM port A write data. For AXI-Lite, pass -- through from AXI bus. If ECC is enabled, merge with fault -- inject vector. -- Write data bits are in lower order bit lanes. -- (31:0) or (63:0) --------------------------------------------------------------------------- GEN_WRDATA: for i in C_S_AXI_DATA_WIDTH-1 downto 0 generate begin --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Generate output write data when ECC is disabled. -- Remove write data path register to BRAM --------------------------------------------------------------------------- GEN_NO_ECC : if C_ECC = 0 generate begin bram_wrdata_a_int (i) <= AXI_WDATA (i); end generate GEN_NO_ECC; --------------------------------------------------------------------------- -- Generate: GEN_W_ECC -- Purpose: Generate output write data when ECC is enable -- (use fault vector). -- (N:0) --------------------------------------------------------------------------- GEN_W_ECC : if C_ECC = 1 generate begin bram_wrdata_a_int (i) <= WrData (i) xor FaultInjectData (i); end generate GEN_W_ECC; end generate GEN_WRDATA; --------------------------------------------------------------------------- -- *** AXI Write Response Channel Interface *** --------------------------------------------------------------------------- -- No BID support (wrap around in Interconnect) -- In AXI-Lite, no WLAST assertion -- Drive constant value out on BRESP -- axi_bresp_int <= RESP_OKAY; axi_bresp_int <= RESP_SLVERR when (C_ECC = 1 and UE_Q = '1') else RESP_OKAY; --------------------------------------------------------------------------- -- Implement BVALID with counter regardless of IP configuration. -- -- BVALID counter to track the # of required BVALID/BREADY handshakes -- needed to occur on the AXI interface. Based on early and seperate -- AWVALID/AWREADY and WVALID/WREADY handshake exchanges. REG_BVALID_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then bvalid_cnt <= (others => '0'); -- Ensure we only increment counter wyhen BREADY is not asserted elsif (bvalid_cnt_inc = '1') and (bvalid_cnt_dec = '0') then bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) + 1); -- Ensure that we only decrement when SM is not incrementing elsif (bvalid_cnt_dec = '1') and (bvalid_cnt_inc = '0') then bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) - 1); else bvalid_cnt <= bvalid_cnt; end if; end if; end process REG_BVALID_CNT; bvalid_cnt_dec <= '1' when (AXI_BREADY = '1' and axi_bvalid_int = '1' and bvalid_cnt /= "000") else '0'; -- Replace BVALID output register -- Assert BVALID as long as BVALID counter /= zero REG_BVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (bvalid_cnt = "001" and bvalid_cnt_dec = '1') then axi_bvalid_int <= '0'; elsif (bvalid_cnt /= "000") then axi_bvalid_int <= '1'; else axi_bvalid_int <= '0'; end if; end if; end process REG_BVALID; --------------------------------------------------------------------------- -- *** AXI Read Data Channel Interface *** --------------------------------------------------------------------------- -- For reductions on AXI-Lite, drive constant value on RESP axi_rresp_int <= RESP_OKAY; --------------------------------------------------------------------------- -- Generate: GEN_R -- Purpose: Generate AXI R channel outputs when ECC is disabled. -- No register delay on AXI_RVALID and AXI_RLAST. --------------------------------------------------------------------------- GEN_R: if C_ECC = 0 generate begin --------------------------------------------------------------------------- -- AXI_RVALID Output Register -- -- Set AXI_RVALID when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then -- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1' -- May be able to remove from this if clause (and simplify logic) axi_rvalid_int <= '0'; elsif (axi_rvalid_set = '1') then axi_rvalid_int <= '1'; else axi_rvalid_int <= axi_rvalid_int; end if; end if; end process REG_RVALID; --------------------------------------------------------------------------- -- AXI_RLAST Output Register -- -- Set AXI_RLAST when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RLAST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then -- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1' -- May be able to remove from this if clause (and simplify logic) axi_rlast_int <= '0'; elsif (axi_rlast_set = '1') then axi_rlast_int <= '1'; else axi_rlast_int <= axi_rlast_int; end if; end if; end process REG_RLAST; end generate GEN_R; --------------------------------------------------------------------------- -- Generate: GEN_R_ECC -- Purpose: Generate AXI R channel outputs when ECC is enabled. -- Must use registered delayed control signals for RLAST -- and RVALID to align with register inclusion for corrected -- read data in ECC logic. --------------------------------------------------------------------------- GEN_R_ECC: if C_ECC = 1 generate begin --------------------------------------------------------------------------- -- AXI_RVALID Output Register -- -- Set AXI_RVALID when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then -- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1' -- May be able to remove from this if clause (and simplify logic) axi_rvalid_int <= '0'; elsif (axi_rvalid_set_r = '1') then axi_rvalid_int <= '1'; else axi_rvalid_int <= axi_rvalid_int; end if; end if; end process REG_RVALID; --------------------------------------------------------------------------- -- AXI_RLAST Output Register -- -- Set AXI_RLAST when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RLAST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then -- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1' -- May be able to remove from this if clause (and simplify logic) axi_rlast_int <= '0'; elsif (axi_rlast_set_r = '1') then axi_rlast_int <= '1'; else axi_rlast_int <= axi_rlast_int; end if; end if; end process REG_RLAST; end generate GEN_R_ECC; --------------------------------------------------------------------------- -- -- Generate AXI bus read data. No register. Pass through -- read data from BRAM. Determine source on single port -- vs. dual port configuration. -- --------------------------------------------------------------------------- ----------------------------------------------------------------------- -- Generate: RDATA_NO_ECC -- Purpose: Define port A/B from BRAM on AXI_RDATA when ECC disabled. ----------------------------------------------------------------------- RDATA_NO_ECC: if (C_ECC = 0) generate begin AXI_RDATA <= axi_rdata_int; ----------------------------------------------------------------------- -- Generate: GEN_RDATA_SNG_PORT -- Purpose: Source of read data: Port A in single port configuration. ----------------------------------------------------------------------- GEN_RDATA_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate begin axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_A(C_S_AXI_DATA_WIDTH-1 downto 0); end generate GEN_RDATA_SNG_PORT; ----------------------------------------------------------------------- -- Generate: GEN_RDATA_DUAL_PORT -- Purpose: Source of read data: Port B in dual port configuration. ----------------------------------------------------------------------- GEN_RDATA_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate begin axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0); end generate GEN_RDATA_DUAL_PORT; end generate RDATA_NO_ECC; ----------------------------------------------------------------------- -- Generate: RDATA_W_ECC -- Purpose: Connect AXI_RDATA from ECC module when ECC enabled. ----------------------------------------------------------------------- RDATA_W_ECC: if (C_ECC = 1) generate subtype syndrome_bits is std_logic_vector (0 to 6); type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits; constant correct_data_table : correct_data_table_type := ( 0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001", 4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001", 8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101", 12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101", 16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101", 20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101", 24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011", 28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011" ); begin -- Logic common to either type of ECC encoding/decoding -- Renove bit reversal on AXI_RDATA output. AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr; CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0); -- Remove GEN_RDATA that was doing bit reversal. -- Read back data is registered prior to any single bit error correction. REG_RDATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rdata_int <= (others => '0'); else axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1); end if; end if; end process REG_RDATA; --------------------------------------------------------------------------- -- Generate: RDATA_W_HAMMING -- Purpose: Add generate statement for Hamming Code ECC algorithm -- specific logic. --------------------------------------------------------------------------- RDATA_W_HAMMING: if C_ECC_TYPE = 0 generate begin -- Move correct_one_bit logic to output side of AXI_RDATA output register. -- Improves timing by balancing logic on both sides of pipeline stage. -- Utilizing registers in AXI interconnect makes this feasible. --------------------------------------------------------------------------- -- Register ECC syndrome value to correct any single bit errors -- post-register on AXI read data. REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_reg <= Syndrome; syndrome_4_reg <= Syndrome_4; syndrome_6_reg <= Syndrome_6; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Do last XOR on select syndrome bits outside of checkbit_handler (to match rd_chnl -- w/ balanced pipeline stage) before correct_one_bit module. syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3); PARITY_CHK4: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2) port map ( InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (4) ); -- [out std_logic] syndrome_reg_i (5) <= syndrome_reg (5); PARITY_CHK6: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (6) ); -- [out std_logic] --------------------------------------------------------------------------- -- Generate: GEN_CORR_32 -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_32: for i in 0 to C_S_AXI_DATA_WIDTH-1 generate begin --------------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_32 -- Description: Generate ECC bits for checking data read from BRAM. --------------------------------------------------------------------------- CORR_ONE_BIT_32: entity work.correct_one_bit generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table (i)) port map ( DIn => axi_rdata_int (31-i), Syndrome => syndrome_reg_i, DCorr => axi_rdata_int_corr (31-i)); end generate GEN_CORR_32; end generate RDATA_W_HAMMING; -- Hsiao ECC done in seperate generate statement (GEN_HSIAO_ECC) end generate RDATA_W_ECC; --------------------------------------------------------------------------- -- Main AXI-Lite State Machine -- -- Description: Central processing unit for AXI-Lite write and read address -- channel interface handling and handshaking. -- Handles all arbitration between write and read channels -- to utilize single port to BRAM -- -- Outputs: axi_wready_int Registered -- axi_arready_reg Registered (used in ECC configurations) -- bvalid_cnt_inc Combinatorial -- axi_rvalid_set Combinatorial -- axi_rlast_set Combinatorial -- bram_en_a_cmb Combinatorial -- bram_en_b_cmb Combinatorial -- bram_we_a_int Combinatorial -- -- -- LITE_SM_CMB_PROCESS: Combinational process to determine next state. -- LITE_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- LITE_SM_CMB_PROCESS: process ( AXI_AWVALID, AXI_WVALID, AXI_WSTRB, AXI_ARVALID, AXI_RREADY, bvalid_cnt, axi_rvalid_int, lite_sm_cs ) begin -- assign default values for state machine outputs lite_sm_ns <= lite_sm_cs; axi_wready_cmb <= '0'; axi_arready_cmb <= '0'; bvalid_cnt_inc <= '0'; axi_rvalid_set <= '0'; axi_rlast_set <= '0'; bram_en_a_cmb <= '0'; bram_en_b_cmb <= '0'; bram_we_a_int <= (others => '0'); case lite_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- AXI Interconnect will only issue AWVALID OR ARVALID -- at a time. In the case when the core is attached -- to another AXI master IP, arbitrate between read -- and write operation. Read operation will always win. if (AXI_ARVALID = '1') then lite_sm_ns <= RD_DATA; -- Initiate BRAM read transfer -- For single port BRAM, use Port A -- For dual port BRAM, use Port B if (C_SINGLE_PORT_BRAM = 1) then bram_en_a_cmb <= '1'; else bram_en_b_cmb <= '1'; end if; bram_we_a_int <= (others => '0'); -- RVALID to be asserted in next clock cycle -- Only 1 clock cycle latency on reading data from BRAM axi_rvalid_set <= '1'; -- Due to single data beat with AXI-Lite -- Assert RLAST on AXI axi_rlast_set <= '1'; -- Only in ECC configurations -- Must assert ARREADY here (no pre-assertion) if (C_ECC = 1) then axi_arready_cmb <= '1'; end if; -- Write operations are lower priority than reads -- when an AXI master asserted both operations simultaneously. elsif (AXI_AWVALID = '1') and (AXI_WVALID = '1') and (bvalid_cnt /= "111") then -- Initiate BRAM write transfer bram_en_a_cmb <= '1'; -- Always perform a read-modify-write sequence with ECC is enabled. if (C_ECC = 1) then lite_sm_ns <= RMW_RD_DATA; -- Disable Port A write enables bram_we_a_int <= (others => '0'); else -- Non ECC operation or an ECC full 32-bit word write -- Assert acknowledge of data & address on AXI. -- Wait to assert AWREADY and WREADY in ECC designs. axi_wready_cmb <= '1'; -- Increment counter to track # of required BVALID responses. bvalid_cnt_inc <= '1'; lite_sm_ns <= SNG_WR_DATA; bram_we_a_int <= AXI_WSTRB; end if; end if; ------------------------- SNG_WR_DATA State ------------------------- when SNG_WR_DATA => -- With early assertion of ARREADY, the SM -- must be able to accept a read address at any clock cycle. -- Check here for active ARVALID and directly handle read -- and do not proceed back to IDLE (no empty clock cycle in which -- read address may be missed). if (AXI_ARVALID = '1') and (C_ECC = 0) then lite_sm_ns <= RD_DATA; -- Initiate BRAM read transfer -- For single port BRAM, use Port A -- For dual port BRAM, use Port B if (C_SINGLE_PORT_BRAM = 1) then bram_en_a_cmb <= '1'; else bram_en_b_cmb <= '1'; end if; bram_we_a_int <= (others => '0'); -- RVALID to be asserted in next clock cycle -- Only 1 clock cycle latency on reading data from BRAM axi_rvalid_set <= '1'; -- Due to single data beat with AXI-Lite -- Assert RLAST on AXI axi_rlast_set <= '1'; -- Only in ECC configurations -- Must assert ARREADY here (no pre-assertion) -- Pre-assertion of ARREADY is only for non ECC configurations. if (C_ECC = 1) then axi_arready_cmb <= '1'; end if; else lite_sm_ns <= IDLE; end if; ---------------------------- RD_DATA State --------------------------- when RD_DATA => -- Data is presented to AXI bus -- Wait for acknowledgment to process any next transfers -- RVALID may not be asserted as we transition into this state. if (AXI_RREADY = '1') and (axi_rvalid_int = '1') then lite_sm_ns <= IDLE; end if; ------------------------- RMW_RD_DATA State ------------------------- when RMW_RD_DATA => lite_sm_ns <= RMW_MOD_DATA; ------------------------- RMW_MOD_DATA State ------------------------- when RMW_MOD_DATA => lite_sm_ns <= RMW_WR_DATA; -- Hold off on assertion of WREADY and AWREADY until -- here, so no pipeline registers necessary. -- Assert acknowledge of data & address on AXI axi_wready_cmb <= '1'; -- Increment counter to track # of required BVALID responses. -- Able to assert this signal early, then BVALID counter -- will get incremented in the next clock cycle when WREADY -- is asserted. bvalid_cnt_inc <= '1'; ------------------------- RMW_WR_DATA State ------------------------- when RMW_WR_DATA => -- Initiate BRAM write transfer bram_en_a_cmb <= '1'; -- Enable all WEs to BRAM bram_we_a_int <= (others => '1'); -- Complete write operation lite_sm_ns <= IDLE; --coverage off ------------------------------ Default ---------------------------- when others => lite_sm_ns <= IDLE; --coverage on end case; end process LITE_SM_CMB_PROCESS; --------------------------------------------------------------------------- LITE_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then lite_sm_cs <= IDLE; axi_wready_int <= '0'; axi_arready_reg <= '0'; axi_rvalid_set_r <= '0'; axi_rlast_set_r <= '0'; else lite_sm_cs <= lite_sm_ns; axi_wready_int <= axi_wready_cmb; axi_arready_reg <= axi_arready_cmb; axi_rvalid_set_r <= axi_rvalid_set; axi_rlast_set_r <= axi_rlast_set; end if; end if; end process LITE_SM_REG_PROCESS; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- *** ECC Logic *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_ECC -- Purpose: Generate BRAM ECC write data and check ECC on read operations. -- Create signals to update ECC registers (lite_ecc_reg module interface). -- --------------------------------------------------------------------------- GEN_ECC: if C_ECC = 1 generate constant null7 : std_logic_vector(0 to 6) := "0000000"; -- Specific to 32-bit data width (AXI-Lite) signal WrECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0); -- Specific to BRAM data width signal WrECC_i : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0'); signal wrdata_i : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0); signal AXI_WDATA_Q : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0); signal AXI_WSTRB_Q : std_logic_vector ((C_S_AXI_DATA_WIDTH/8 - 1) downto 0); signal bram_din_a_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width signal bram_rddata_in : std_logic_vector (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); subtype syndrome_bits is std_logic_vector (0 to 6); type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits; constant correct_data_table : correct_data_table_type := ( 0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001", 4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001", 8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101", 12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101", 16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101", 20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101", 24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011", 28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011" ); type bool_array is array (natural range 0 to 6) of boolean; constant inverted_bit : bool_array := (false,false,true,false,true,false,false); begin -- Read on Port A -- or any operation on Port B (it will be read only). BRAM_Addr_En <= '1' when (bram_en_a_int = '1' and bram_we_a_int = "00000") or (bram_en_b_int = '1') else '0'; -- BRAM_WE generated from SM -- Remember byte write enables one clock cycle to properly mux bytes to write, -- with read data in read/modify write operation -- Write in Read/Write always 1 cycle after Read REG_RMW_SIGS : process (S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Add reset values if (S_AXI_AResetn = C_RESET_ACTIVE) then RdModifyWr_Check <= '0'; RdModifyWr_Modify <= '0'; RdModifyWr_Write <= '0'; else RdModifyWr_Check <= RdModifyWr_Read; RdModifyWr_Modify <= RdModifyWr_Check; RdModifyWr_Write <= RdModifyWr_Modify; end if; end if; end process REG_RMW_SIGS; -- v1.03a -- Delay assertion of WREADY to minimize registers in core. -- Use SM transition to RMW "read" to assert this signal. RdModifyWr_Read <= '1' when (lite_sm_ns = RMW_RD_DATA) else '0'; -- Remember write data one cycle to be available after read has been completed in a -- read/modify write operation STORE_WRITE_DBUS : process (S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then AXI_WDATA_Q <= (others => '0'); AXI_WSTRB_Q <= (others => '0'); -- v1.03a -- With the delay assertion of WREADY, use WVALID -- to register in WDATA and WSTRB signals. elsif (AXI_WVALID = '1') then AXI_WDATA_Q <= AXI_WDATA; AXI_WSTRB_Q <= AXI_WSTRB; end if; end if; end process STORE_WRITE_DBUS; wrdata_i <= AXI_WDATA_Q when RdModifyWr_Modify = '1' else AXI_WDATA; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_WRDATA_CMB -- Purpose: Replace manual signal assignment for WrData_cmb with -- generate funtion. -- -- Ensure correct byte swapping occurs with -- CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) assignment -- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0). -- -- AXI_WSTRB_Q (C_S_AXI_DATA_WIDTH_BYTES-1 downto 0) matches -- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0). -- ------------------------------------------------------------------------ GEN_WRDATA_CMB: for i in C_AXI_DATA_WIDTH_BYTES-1 downto 0 generate begin WrData_cmb ( (((i+1)*8)-1) downto i*8 ) <= wrdata_i ((((i+1)*8)-1) downto i*8) when (RdModifyWr_Modify = '1' and AXI_WSTRB_Q(i) = '1') else CorrectedRdData ( (C_S_AXI_DATA_WIDTH - ((i+1)*8)) to (C_S_AXI_DATA_WIDTH - (i*8) - 1) ); end generate GEN_WRDATA_CMB; REG_WRDATA : process (S_AXI_AClk) is begin -- Remove reset value to minimize resources & improve timing if (S_AXI_AClk'event and S_AXI_AClk = '1') then WrData <= WrData_cmb; end if; end process REG_WRDATA; ------------------------------------------------------------------------ -- New assignment of ECC bits to BRAM write data outside generate -- blocks. Same signal assignment regardless of ECC type. bram_wrdata_a_int (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) <= '0'; bram_wrdata_a_int ((C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH - 1) downto C_S_AXI_DATA_WIDTH) <= WrECC xor FaultInjectECC; ------------------------------------------------------------------------ -- No need to use RdModifyWr_Write in the data path. -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HAMMING_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. ------------------------------------------------------------------------ GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate begin --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_WR_32 -- Description: Generate ECC bits for writing into BRAM. -- WrData (N:0) --------------------------------------------------------------------------- CHK_HANDLER_WR_32: entity work.checkbit_handler generic map ( C_ENCODE => true, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( DataIn => WrData, -- [in std_logic_vector(0 to 31)] CheckIn => null7, -- [in std_logic_vector(0 to 6)] CheckOut => WrECC, -- [out std_logic_vector(0 to 6)] Syndrome_4 => open, -- [out std_logic_vector(0 to 1)] Syndrome_6 => open, -- [out std_logic_vector(0 to 5)] Syndrome => open, -- [out std_logic_vector(0 to 6)] Enable_ECC => '1', -- [in std_logic] Syndrome_Chk => null7, -- [in std_logic_vector(0 to 6)] UE_Q => '0', -- [in std_logic] CE_Q => '0', -- [in std_logic] UE => open, -- [out std_logic] CE => open ); -- [out std_logic] --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_RD_32 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) --------------------------------------------------------------------------- CHK_HANDLER_RD_32: entity work.checkbit_handler generic map ( C_ENCODE => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( -- DataIn (8:39) -- CheckIn (1:7) -- Bit swapping done at port level on checkbit_handler (31:0) & (6:0) DataIn => bram_din_a_i (C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_S_AXI_DATA_WIDTH), -- [in std_logic_vector(8 to 39)] CheckIn => bram_din_a_i (1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(1 to 7)] CheckOut => open, -- [out std_logic_vector(0 to 6)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)] Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)] Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)] Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 6)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] -- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate -- of AXI RDATA output register logic to use registered syndrome value. end generate GEN_HAMMING_ECC; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HSIAO_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Derived from MIG v3.7 Hsiao HDL. ------------------------------------------------------------------------ GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate constant CODE_WIDTH : integer := C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH; constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; type type_int0 is array (C_S_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0); signal syndrome_ns : std_logic_vector(ECC_WIDTH - 1 downto 0); signal syndrome_r : std_logic_vector(ECC_WIDTH - 1 downto 0); signal ecc_rddata_r : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); signal h_matrix : type_int0; signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0); signal flip_bits : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); begin ---------------------- Hsiao ECC Write Logic ---------------------- -- Instantiate ecc_gen module, generated from MIG ECC_GEN_HSIAO: entity work.ecc_gen generic map ( code_width => CODE_WIDTH, ecc_width => ECC_WIDTH, data_width => C_S_AXI_DATA_WIDTH ) port map ( -- Output h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0) ); -- Merge muxed rd/write data to gen HSIAO_ECC: process (h_rows, WrData) constant DQ_WIDTH : integer := CODE_WIDTH; variable ecc_wrdata_tmp : std_logic_vector(DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH); begin -- Loop to generate all ECC bits for k in 0 to ECC_WIDTH - 1 loop ecc_wrdata_tmp (CODE_WIDTH - k - 1) := REDUCTION_XOR ( (WrData (C_S_AXI_DATA_WIDTH - 1 downto 0) and h_rows (k * CODE_WIDTH + C_S_AXI_DATA_WIDTH - 1 downto k * CODE_WIDTH))); end loop; WrECC (C_INT_ECC_WIDTH-1 downto 0) <= ecc_wrdata_tmp (DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH); end process HSIAO_ECC; ---------------------- Hsiao ECC Read Logic ----------------------- GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate begin syndrome_ns (m) <= REDUCTION_XOR ( bram_rddata_in (CODE_WIDTH-1 downto 0) and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH))); end generate GEN_RD_ECC; -- Insert register stage for syndrome REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_r <= syndrome_ns; -- Replicate BRAM read back data register for Hamming ECC ecc_rddata_r <= bram_rddata_in (C_S_AXI_DATA_WIDTH-1 downto 0); end if; end process REG_SYNDROME; -- Reconstruct H-matrix H_COL: for n in 0 to C_S_AXI_DATA_WIDTH - 1 generate begin H_BIT: for p in 0 to ECC_WIDTH - 1 generate begin h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n); end generate H_BIT; end generate H_COL; GEN_FLIP_BIT: for r in 0 to C_S_AXI_DATA_WIDTH - 1 generate begin flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r); end generate GEN_FLIP_BIT; axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0) <= ecc_rddata_r (C_S_AXI_DATA_WIDTH-1 downto 0) xor flip_bits (C_S_AXI_DATA_WIDTH-1 downto 0); Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); end generate GEN_HSIAO_ECC; -- Capture correctable/uncorrectable error from BRAM read. -- Either during RMW of write operation or during BRAM read. CORR_REG: process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if RdModifyWr_Modify = '1' or ((Enable_ECC = '1') and (axi_rvalid_int = '1' and AXI_RREADY = '1')) then -- Capture error signals CE_Q <= Sl_CE_i; UE_Q <= Sl_UE_i; else CE_Q <= '0'; UE_Q <= '0'; end if; end if; end process CORR_REG; -- Register CE and UE flags to register block. Sl_CE <= CE_Q; Sl_UE <= UE_Q; --------------------------------------------------------------------------- -- Generate: GEN_DIN_A -- Purpose: Generate BRAM read data vector assignment to always be from Port A -- in a single port BRAM configuration. -- Map BRAM_RdData_A (N:0) to bram_din_a_i (0:N) -- Including read back ECC bits. --------------------------------------------------------------------------- GEN_DIN_A: if C_SINGLE_PORT_BRAM = 1 generate begin --------------------------------------------------------------------------- -- Generate: GEN_DIN_A_HAMMING -- Purpose: Standard input for Hamming ECC code generation. -- MSB '0' is removed in port mapping to checkbit_handler module. --------------------------------------------------------------------------- GEN_DIN_A_HAMMING: if C_ECC_TYPE = 0 generate begin bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); end generate GEN_DIN_A_HAMMING; --------------------------------------------------------------------------- -- Generate: GEN_DIN_A_HSIAO -- Purpose: For Hsiao ECC implementation configurations. -- Remove MSB '0' on 32-bit implementation with fixed -- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix). --------------------------------------------------------------------------- GEN_DIN_A_HSIAO: if C_ECC_TYPE = 1 generate begin bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0); end generate GEN_DIN_A_HSIAO; end generate GEN_DIN_A; --------------------------------------------------------------------------- -- Generate: GEN_DIN_B -- Purpose: Generate BRAM read data vector assignment in a dual port -- configuration to be either from Port B, or from Port A in a -- read-modify-write sequence. -- Map BRAM_RdData_A/B (N:0) to bram_din_a_i (0:N) -- Including read back ECC bits. --------------------------------------------------------------------------- GEN_DIN_B: if C_SINGLE_PORT_BRAM = 0 generate begin --------------------------------------------------------------------------- -- Generate: GEN_DIN_B_HAMMING -- Purpose: Standard input for Hamming ECC code generation. -- MSB '0' is removed in port mapping to checkbit_handler module. --------------------------------------------------------------------------- GEN_DIN_B_HAMMING: if C_ECC_TYPE = 0 generate begin bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) when (RdModifyWr_Check = '1') else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); end generate GEN_DIN_B_HAMMING; --------------------------------------------------------------------------- -- Generate: GEN_DIN_B_HSIAO -- Purpose: For Hsiao ECC implementation configurations. -- Remove MSB '0' on 32-bit implementation with fixed -- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix). --------------------------------------------------------------------------- GEN_DIN_B_HSIAO: if C_ECC_TYPE = 1 generate begin bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0) when (RdModifyWr_Check = '1') else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0); end generate GEN_DIN_B_HSIAO; end generate GEN_DIN_B; -- Map data vector from BRAM to use in correct_one_bit module with -- register syndrome (post AXI RDATA register). UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_S_AXI_DATA_WIDTH-1) when (C_ECC_TYPE = 0) else bram_rddata_in(C_S_AXI_DATA_WIDTH-1 downto 0); end generate GEN_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- *** BRAM Interface Signals *** --------------------------------------------------------------------------- -- With AXI-LITE no narrow operations are allowed. -- AXI_WSTRB is ignored and all byte lanes are written. bram_en_a_int <= bram_en_a_cmb; -- BRAM_En_A <= bram_en_a_int; -- DV regression failure with reset -- 7/7/11 BRAM_En_A <= '0' when (S_AXI_AResetn = C_RESET_ACTIVE) else bram_en_a_int; ----------------------------------------------------------------------- -- Generate: GEN_BRAM_EN_DUAL_PORT -- Purpose: Only generate Port B BRAM enable signal when -- configured for dual port BRAM. ----------------------------------------------------------------------- GEN_BRAM_EN_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate begin bram_en_b_int <= bram_en_b_cmb; BRAM_En_B <= bram_en_b_int; end generate GEN_BRAM_EN_DUAL_PORT; ----------------------------------------------------------------------- -- Generate: GEN_BRAM_EN_SNG_PORT -- Purpose: Drive default for unused BRAM Port B in single -- port BRAM configuration. ----------------------------------------------------------------------- GEN_BRAM_EN_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate begin BRAM_En_B <= '0'; end generate GEN_BRAM_EN_SNG_PORT; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_WE -- Purpose: BRAM WE generate process -- One WE per 8-bits of BRAM data. --------------------------------------------------------------------------- GEN_BRAM_WE: for i in (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH)/8-1 downto 0 generate begin BRAM_WE_A (i) <= bram_we_a_int (i); end generate GEN_BRAM_WE; --------------------------------------------------------------------------- BRAM_Addr_A <= BRAM_Addr_A_i; BRAM_Addr_B <= BRAM_Addr_B_i; --------------------------------------------------------------------------- -- Generate: GEN_L_BRAM_ADDR -- Purpose: Generate zeros on lower order address bits adjustable -- based on BRAM data width. --------------------------------------------------------------------------- GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin BRAM_Addr_A_i (i) <= '0'; BRAM_Addr_B_i (i) <= '0'; end generate GEN_L_BRAM_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_ADDR -- Purpose: Assign BRAM address output from address counter. --------------------------------------------------------------------------- GEN_U_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin BRAM_Addr_A_i (i) <= bram_addr_a_int (i); ----------------------------------------------------------------------- -- Generate: GEN_BRAM_ADDR_DUAL_PORT -- Purpose: Only generate Port B BRAM address when -- configured for dual port BRAM. ----------------------------------------------------------------------- GEN_BRAM_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate begin BRAM_Addr_B_i (i) <= bram_addr_b_int (i); end generate GEN_BRAM_ADDR_DUAL_PORT; ----------------------------------------------------------------------- -- Generate: GEN_BRAM_ADDR_SNG_PORT -- Purpose: Drive default for unused BRAM Port B in single -- port BRAM configuration. ----------------------------------------------------------------------- GEN_BRAM_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate begin BRAM_Addr_B_i (i) <= '0'; end generate GEN_BRAM_ADDR_SNG_PORT; end generate GEN_U_BRAM_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_WRDATA -- Purpose: Generate BRAM Write Data for Port A. --------------------------------------------------------------------------- -- When C_ECC = 0, C_ECC_WIDTH = 0 (at top level HDL) GEN_BRAM_WRDATA: for i in (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) downto 0 generate begin BRAM_WrData_A (i) <= bram_wrdata_a_int (i); end generate GEN_BRAM_WRDATA; BRAM_WrData_B <= (others => '0'); BRAM_WE_B <= (others => '0'); --------------------------------------------------------------------------- end architecture implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/FIFO_image_filter_p_src_data_stream_2_V.vhd

2

4629

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_p_src_data_stream_2_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_p_src_data_stream_2_V_shiftReg; architecture rtl of FIFO_image_filter_p_src_data_stream_2_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_p_src_data_stream_2_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_p_src_data_stream_2_V is component FIFO_image_filter_p_src_data_stream_2_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_p_src_data_stream_2_V_shiftReg : FIFO_image_filter_p_src_data_stream_2_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_p_src_data_stream_2_V.vhd

2

4629

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_p_src_data_stream_2_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_p_src_data_stream_2_V_shiftReg; architecture rtl of FIFO_image_filter_p_src_data_stream_2_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_p_src_data_stream_2_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_p_src_data_stream_2_V is component FIFO_image_filter_p_src_data_stream_2_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_p_src_data_stream_2_V_shiftReg : FIFO_image_filter_p_src_data_stream_2_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_slice.vhd

19

4781

-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; entity axi_datamover_slice is generic ( C_DATA_WIDTH : Integer range 1 to 200 := 64 ); port ( ACLK : in std_logic; ARESET : in std_logic; -- Slave side S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0); S_VALID : in std_logic; S_READY : out std_logic; -- Master side M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0); M_VALID : out std_logic; M_READY : in std_logic ); end entity axi_datamover_slice; architecture working of axi_datamover_slice is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes"; signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0); signal s_ready_i : std_logic; signal m_valid_i : std_logic; signal areset_d : std_logic_vector (1 downto 0); begin -- assign local signal to its output signal S_READY <= s_ready_i; M_VALID <= m_valid_i; process (ACLK) begin if (ACLK'event and ACLK = '1') then areset_d(0) <= ARESET; areset_d(1) <= areset_d(0); end if; end process; -- Save payload data whenever we have a transaction on the slave side process (ACLK) begin if (ACLK'event and ACLK = '1') then if (S_VALID = '1' and s_ready_i = '1') then storage_data <= S_PAYLOAD_DATA; else storage_data <= storage_data; end if; end if; end process; M_PAYLOAD_DATA <= storage_data; -- M_Valid set to high when we have a completed transfer on slave side -- Is removed on a M_READY except if we have a new transfer on the slave side process (ACLK) begin if (ACLK'event and ACLK = '1') then if (areset_d (1) = '1') then m_valid_i <= '0'; elsif (S_VALID = '1') then m_valid_i <= '1'; elsif (M_READY = '1') then m_valid_i <= '0'; else m_valid_i <= m_valid_i; end if; end if; end process; -- Slave Ready is either when Master side drives M_Ready or we have space in our storage data s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0)); end working;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_updt_noqueue.vhd

3

30514

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_noqueue.vhd -- Description: This entity provides the descriptor update for the No Queue mode -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_noqueue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 -- 1 IOC bit + 32 Update Status Bits ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Channel 1 Control -- updt_curdesc_wren : out std_logic ; -- updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_active : in std_logic ; -- updt_queue_empty : out std_logic ; -- updt_ioc : out std_logic ; -- updt_ioc_irq_set : in std_logic ; -- -- dma_interr : out std_logic ; -- dma_slverr : out std_logic ; -- dma_decerr : out std_logic ; -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- updt2_active : in std_logic ; -- updt2_queue_empty : out std_logic ; -- updt2_ioc : out std_logic ; -- updt2_ioc_irq_set : in std_logic ; -- -- dma2_interr : out std_logic ; -- dma2_slverr : out std_logic ; -- dma2_decerr : out std_logic ; -- dma2_interr_set : in std_logic ; -- dma2_slverr_set : in std_logic ; -- dma2_decerr_set : in std_logic ; -- -- --*********************************-- -- --** Channel Update Interface In **-- -- --*********************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis_updtptr_tvalid : in std_logic ; -- s_axis_updtptr_tready : out std_logic ; -- s_axis_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_updtsts_tvalid : in std_logic ; -- s_axis_updtsts_tready : out std_logic ; -- s_axis_updtsts_tlast : in std_logic ; -- -- Update Pointer Stream -- s_axis2_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis2_updtptr_tvalid : in std_logic ; -- s_axis2_updtptr_tready : out std_logic ; -- s_axis2_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis2_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis2_updtsts_tvalid : in std_logic ; -- s_axis2_updtsts_tready : out std_logic ; -- s_axis2_updtsts_tlast : in std_logic ; -- -- --*********************************-- -- --** Channel Update Interface Out**-- -- --*********************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata : out std_logic_vector -- (C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); -- m_axis_updt_tlast : out std_logic ; -- m_axis_updt_tvalid : out std_logic ; -- m_axis_updt_tready : in std_logic -- ); end axi_sg_updt_noqueue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_noqueue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Contstants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel signals signal writing_curdesc : std_logic := '0'; signal write_curdesc_lsb : std_logic := '0'; signal write_curdesc_msb : std_logic := '0'; signal updt_active_d1 : std_logic := '0'; signal updt_active_re : std_logic := '0'; type PNTR_STATE_TYPE is (IDLE, READ_CURDESC_LSB, READ_CURDESC_MSB, WRITE_STATUS ); signal pntr_cs : PNTR_STATE_TYPE; signal pntr_ns : PNTR_STATE_TYPE; signal writing_status : std_logic := '0'; signal curdesc_tready : std_logic := '0'; signal writing_status_d1 : std_logic := '0'; signal writing_status_re : std_logic := '0'; signal writing_status_re_ch1 : std_logic := '0'; signal writing_status_re_ch2 : std_logic := '0'; signal updt_active_int : std_logic := '0'; signal s_axis_updtptr_tvalid_int : std_logic := '0'; signal s_axis_updtsts_tvalid_int : std_logic := '0'; signal s_axis_updtsts_tlast_int : std_logic := '0'; signal s_axis_updtptr_tdata_int : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); signal s_axis_qual : std_logic := '0'; signal s_axis2_qual : std_logic := '0'; signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); -- signal m_axis_updt_tlast_mm2s : std_logic ; -- signal m_axis_updt_tvalid_mm2s : std_logic ; signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); -- signal m_axis_updt_tlast_s2mm : std_logic ; -- signal m_axis_updt_tvalid_s2mm : std_logic ; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else m_axis_updt_tdata_s2mm; m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else m_axis_updt_tvalid_s2mm; m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else m_axis_updt_tlast_s2mm; updt_active_int <= updt_active or updt2_active; s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid; s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid; s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast; s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active; s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active; -- Asset active strobe on rising edge of update active -- asertion. This kicks off the update process for -- the channel REG_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_active_d1 <= '0'; else updt_active_d1 <= updt_active or updt2_active; end if; end if; end process REG_ACTIVE; updt_active_re <= (updt_active or updt2_active) and not updt_active_d1; -- Current Descriptor Pointer Fetch. This state machine controls -- reading out the current pointer from the Queue or channel port -- and writing it to the update manager for use in command -- generation to the DataMover for Descriptor update. CURDESC_PNTR_STATE : process(pntr_cs, updt_active_int, s_axis_updtptr_tvalid_int, updt_active, updt2_active, s_axis_qual, s_axis2_qual, s_axis_updtptr_tvalid, s_axis2_updtptr_tvalid, s_axis_updtsts_tvalid_int, m_axis_updt_tready) begin write_curdesc_lsb <= '0'; write_curdesc_msb <= '0'; writing_status <= '0'; writing_curdesc <= '0'; curdesc_tready <= '0'; pntr_ns <= pntr_cs; case pntr_cs is when IDLE => if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or (s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then writing_curdesc <= '1'; pntr_ns <= READ_CURDESC_LSB; else pntr_ns <= IDLE; end if; --------------------------------------------------------------- -- Get lower current descriptor when READ_CURDESC_LSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- on tvalid from Queue or channel port then register -- lsb curdesc and setup to register msb curdesc if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then write_curdesc_lsb <= '1'; -- pntr_ns <= READ_CURDESC_MSB; pntr_ns <= WRITE_STATUS; else -- coverage off pntr_ns <= READ_CURDESC_LSB; -- coverage on end if; -- coverage off --------------------------------------------------------------- -- Get upper current descriptor when READ_CURDESC_MSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- On tvalid from Queue or channel port then register -- msb. This will also write curdesc out to update -- manager. if(s_axis_updtptr_tvalid_int = '1')then write_curdesc_msb <= '1'; pntr_ns <= WRITE_STATUS; else pntr_ns <= READ_CURDESC_MSB; end if; -- coverage on --------------------------------------------------------------- -- Hold in this state until remainder of descriptor is -- written out. when WRITE_STATUS => writing_status <= '1'; --s_axis_updtsts_tvalid_int; if((s_axis_qual = '1' and m_axis_updt_tready = '1') or (s_axis2_qual = '1' and m_axis_updt_tready = '1')) then pntr_ns <= IDLE; else pntr_ns <= WRITE_STATUS; end if; -- coverage off when others => pntr_ns <= IDLE; -- coverage on end case; end process CURDESC_PNTR_STATE; --------------------------------------------------------------------------- -- Register for CURDESC Pointer state machine --------------------------------------------------------------------------- REG_PNTR_STATES : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then pntr_cs <= IDLE; else pntr_cs <= pntr_ns; end if; end if; end process REG_PNTR_STATES; -- Status stream signals m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0); m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status; m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status; s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active; -- Pointer stream signals s_axis_updtptr_tready <= curdesc_tready and updt_active; -- Indicate need for channel service for update state machine updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status); m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0); m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status; m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status; s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active; -- Pointer stream signals s_axis2_updtptr_tready <= curdesc_tready and updt2_active; -- Indicate need for channel service for update state machine updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status); --********************************************************************* --** POINTER CAPTURE LOGIC --********************************************************************* s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else s_axis2_updtptr_tdata; --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_LSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(31 downto 0) <= (others => '0'); -- Capture lower pointer from FIFO or channel port elsif(write_curdesc_lsb = '1')then updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); end if; end if; end process REG_LSB_CURPNTR; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(63 downto 32) <= (others => '0'); updt_curdesc_wren <= '0'; -- Capture upper pointer from FIFO or channel port -- and also write curdesc out elsif(write_curdesc_msb = '1')then updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); updt_curdesc_wren <= '1'; -- Assert tready/wren for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_UPPER_MSB_CURDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc_wren <= '0'; -- Throw away second word, only write curdesc out with msb -- set to zero elsif(write_curdesc_lsb = '1')then -- elsif(write_curdesc_msb = '1')then updt_curdesc_wren <= '1'; -- Assert for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_NO_UPR_MSB_CURDESC; --********************************************************************* --** ERROR CAPTURE LOGIC --********************************************************************* ----------------------------------------------------------------------- -- Generate rising edge pulse on writing status signal. This will -- assert at the beginning of the status write. Coupled with status -- fifo set to first word fall through status will be on dout -- regardless of target ready. ----------------------------------------------------------------------- REG_WRITE_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then writing_status_d1 <= '0'; else writing_status_d1 <= writing_status; end if; end if; end process REG_WRITE_STATUS; writing_status_re <= writing_status and not writing_status_d1; writing_status_re_ch1 <= writing_status_re and updt_active; writing_status_re_ch2 <= writing_status_re and updt2_active; --------------------------------------------------------------------------- -- Caputure IOC begin set --------------------------------------------------------------------------- REG_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then updt_ioc <= '0'; elsif(writing_status_re_ch1 = '1')then updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then dma_interr <= '0'; elsif(writing_status_re_ch1 = '1')then dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then dma_slverr <= '0'; elsif(writing_status_re_ch1 = '1')then dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then dma_decerr <= '0'; elsif(writing_status_re_ch1 = '1')then dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC_ERROR; --------------------------------------------------------------------------- -- Caputure IOC begin set --------------------------------------------------------------------------- REG2_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then updt2_ioc <= '0'; elsif(writing_status_re_ch2 = '1')then updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT); end if; end if; end process REG2_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then dma2_interr <= '0'; elsif(writing_status_re_ch2 = '1')then dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE2_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then dma2_slverr <= '0'; elsif(writing_status_re_ch2 = '1')then dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE2_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then dma2_decerr <= '0'; elsif(writing_status_re_ch2 = '1')then dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE2_DMADEC_ERROR; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_dre_mux2_1_x_n.vhd

18

5142

------------------------------------------------------------------------------- -- axi_datamover_dre_mux2_1_x_n.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_dre_mux2_1_x_n.vhd -- -- Description: -- -- This VHDL file provides a 2 to 1 xn bit wide mux for the AXI Data Realignment -- Engine (DRE). -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use ieee.STD_LOGIC_UNSIGNED.all; use ieee.std_logic_arith.all; ------------------------------------------------------------------------------- -- Start 2 to 1 xN Mux ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- Entity axi_datamover_dre_mux2_1_x_n is generic ( C_WIDTH : Integer := 8 -- Sets the bit width of the 2x Mux slice ); port ( Sel : In std_logic; -- Mux select control I0 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 0 input I1 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 1 inputl Y : Out std_logic_vector(C_WIDTH-1 downto 0) -- Mux output value ); end entity axi_datamover_dre_mux2_1_x_n; -- Architecture implementation of axi_datamover_dre_mux2_1_x_n is begin ------------------------------------------------------------- -- Combinational Process -- -- Label: SELECT2_1 -- -- Process Description: -- This process implements an 2 to 1 mux. -- ------------------------------------------------------------- SELECT2_1 : process (Sel, I0, I1) begin case Sel is when '0' => Y <= I0; when '1' => Y <= I1; when others => Y <= I0; end case; end process SELECT2_1; end implementation; -- axi_datamover_dre_mux2_1_x_n ------------------------------------------------------------------------------- -- End 2 to 1 xN Mux -------------------------------------------------------------------------------

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/impl/vhdl/FIFO_image_filter_img_0_data_stream_0_V.vhd

4

4629

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_img_0_data_stream_0_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_img_0_data_stream_0_V_shiftReg; architecture rtl of FIFO_image_filter_img_0_data_stream_0_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_img_0_data_stream_0_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_img_0_data_stream_0_V is component FIFO_image_filter_img_0_data_stream_0_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_img_0_data_stream_0_V_shiftReg : FIFO_image_filter_img_0_data_stream_0_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/rd_chnl.vhd

5

207533

------------------------------------------------------------------------------- -- rd_chnl.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: rd_chnl.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller read channel interfaces. Controls all -- handshaking and data flow on the AXI read address (AR) -- and read data (R) channels. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- ------------------------------------------------------------------------------- -- -- History: -- -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/3/2011 v1.03a -- ~~~~~~ -- Edits for scalability and support of 512 and 1024-bit data widths. -- ^^^^^^ -- JLJ 2/14/2011 v1.03a -- ~~~~~~ -- Initial integration of Hsiao ECC algorithm. -- Add C_ECC_TYPE top level parameter. -- Similar edits as wr_chnl on Hsiao ECC code. -- ^^^^^^ -- JLJ 2/18/2011 v1.03a -- ~~~~~~ -- Update for usage of ecc_gen.vhd module directly from MIG. -- Clean-up XST warnings. -- ^^^^^^ -- JLJ 2/22/2011 v1.03a -- ~~~~~~ -- Found issue with ECC decoding on read path. Remove MSB '0' usage -- in syndrome calculation, since h_matrix is based on 32 + 7 = 39 bits. -- Modify read data signal used in single bit error correction. -- ^^^^^^ -- JLJ 2/23/2011 v1.03a -- ~~~~~~ -- Move all MIG functions to package body. -- ^^^^^^ -- JLJ 3/2/2011 v1.03a -- ~~~~~~ -- Fix XST handling for DIV functions. Create seperate process when -- divisor is not constant and a power of two. -- ^^^^^^ -- JLJ 3/15/2011 v1.03a -- ~~~~~~ -- Clean-up unused signal, narrow_addr_inc. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Add comments as noted in Spyglass runs. And general code clean-up. -- ^^^^^^ -- JLJ 4/21/2011 v1.03a -- ~~~~~~ -- Code clean up. -- Add defaults to araddr_pipe_sel & axi_arready_int when in single port mode. -- Remove use of IF_IS_AXI4 constant. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Code clean up. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove usage of C_FAMILY. -- Hard code C_USE_LUT6 constant. -- ^^^^^^ -- JLJ 5/26/2011 v1.03a -- ~~~~~~ -- With CR # 609695, update else clause for narrow_burst_cnt_ld to -- remove simulation warnings when axi_byte_div_curr_arsize = zero. -- ^^^^^^ -- -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.wrap_brst; use work.ua_narrow; use work.checkbit_handler; use work.checkbit_handler_64; use work.correct_one_bit; use work.correct_one_bit_64; use work.ecc_gen; use work.parity; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity rd_chnl is generic ( -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type C_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) C_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_AXI_ID_WIDTH : integer := 4; -- AXI ID vector width C_S_AXI_SUPPORTS_NARROW : integer := 1; -- Support for narrow burst operations C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to "AXI4LITE" to optimize out burst transaction support C_SINGLE_PORT_BRAM : integer := 0; -- Enable single port usage of BRAM C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_ECC_TYPE : integer := 0 -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code ); port ( -- AXI Global Signals S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI Read Address Channel Signals (AR) AXI_ARID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); AXI_ARADDR : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0); AXI_ARLEN : in std_logic_vector(7 downto 0); -- Specifies the number of data transfers in the burst -- "0000 0000" 1 data transfer -- "0000 0001" 2 data transfers -- ... -- "1111 1111" 256 data transfers AXI_ARSIZE : in std_logic_vector(2 downto 0); -- Specifies the max number of data bytes to transfer in each data beat -- "000" 1 byte to transfer -- "001" 2 bytes to transfer -- "010" 3 bytes to transfer -- ... AXI_ARBURST : in std_logic_vector(1 downto 0); -- Specifies burst type -- "00" FIXED = Fixed burst address (handled as INCR) -- "01" INCR = Increment burst address -- "10" WRAP = Incrementing address burst that wraps to lower order address at boundary -- "11" Reserved (not checked) AXI_ARLOCK : in std_logic; AXI_ARCACHE : in std_logic_vector(3 downto 0); AXI_ARPROT : in std_logic_vector(2 downto 0); AXI_ARVALID : in std_logic; AXI_ARREADY : out std_logic; -- AXI Read Data Channel Signals (R) AXI_RID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); AXI_RDATA : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0); AXI_RRESP : out std_logic_vector(1 downto 0); AXI_RLAST : out std_logic; AXI_RVALID : out std_logic; AXI_RREADY : in std_logic; -- ECC Register Interface Signals Enable_ECC : in std_logic; BRAM_Addr_En : out std_logic; CE_Failing_We : out std_logic := '0'; Sl_CE : out std_logic := '0'; Sl_UE : out std_logic := '0'; -- Single Port Arbitration Signals Arb2AR_Active : in std_logic; AR2Arb_Active_Clr : out std_logic := '0'; Sng_BRAM_Addr_Ld_En : out std_logic := '0'; Sng_BRAM_Addr_Ld : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); Sng_BRAM_Addr_Inc : out std_logic := '0'; Sng_BRAM_Addr : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- BRAM Read Port Interface Signals BRAM_En : out std_logic; BRAM_Addr : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0); BRAM_RdData : in std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) ); end entity rd_chnl; ------------------------------------------------------------------------------- architecture implementation of rd_chnl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- All functions defined in axi_bram_ctrl_funcs package. ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- -- Reset active level (common through core) constant C_RESET_ACTIVE : std_logic := '0'; constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error -- For future support. constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response -- For future support. constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error -- Set constants for ARLEN equal to a count of one or two beats. constant AXI_ARLEN_ONE : std_logic_vector(7 downto 0) := (others => '0'); constant AXI_ARLEN_TWO : std_logic_vector(7 downto 0) := "00000001"; -- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width -- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00" -- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000" -- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000" -- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000" -- Move to full_axi module -- constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_AXI_DATA_WIDTH/8); -- Not used -- constant C_BRAM_ADDR_ADJUST : integer := C_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR; -- Determine maximum size for narrow burst length counter -- When C_AXI_DATA_WIDTH = 32, minimum narrow width burst is 8 bits -- resulting in a count 3 downto 0 => so minimum counter width = 2 bits. -- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst is 8 bits -- resulting in a count 31 downto 0 => so minimum counter width = 5 bits. constant C_NARROW_BURST_CNT_LEN : integer := log2 (C_AXI_DATA_WIDTH/8); constant NARROW_CNT_MAX : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); -- Max length burst count AXI4 specification constant C_MAX_BRST_CNT : integer := 256; constant C_BRST_CNT_SIZE : integer := log2 (C_MAX_BRST_CNT); -- When the burst count = 0 constant C_BRST_CNT_ZERO : std_logic_vector(C_BRST_CNT_SIZE-1 downto 0) := (others => '0'); -- Burst count = 1 constant C_BRST_CNT_ONE : std_logic_vector(7 downto 0) := "00000001"; -- Burst count = 2 constant C_BRST_CNT_TWO : std_logic_vector(7 downto 0) := "00000010"; -- Read data mux select constants (for signal rddata_mux_sel) -- '0' selects BRAM -- '1' selects read skid buffer constant C_RDDATA_MUX_BRAM : std_logic := '0'; constant C_RDDATA_MUX_SKID_BUF : std_logic := '1'; -- Determine the number of bytes based on the AXI data width. constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8; -- AXI Burst Types -- AXI Spec 4.4 constant C_AXI_BURST_WRAP : std_logic_vector (1 downto 0) := "10"; constant C_AXI_BURST_INCR : std_logic_vector (1 downto 0) := "01"; constant C_AXI_BURST_FIXED : std_logic_vector (1 downto 0) := "00"; -- AXI Size Constants -- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte -- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes -- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM -- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM -- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM -- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM -- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM -- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM -- Determine max value of ARSIZE based on the AXI data width. -- Use function in axi_bram_ctrl_funcs package. constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH); -- Internal ECC data width size. constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_AXI_DATA_WIDTH); -- For use with ECC functions (to use LUT6 components or let synthesis infer the optimal implementation). -- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6; -- Remove usage of C_FAMILY. -- All architectures supporting AXI will support a LUT6. -- Hard code this internal constant used in ECC algorithm. constant C_USE_LUT6 : boolean := TRUE; ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Read Address Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type RD_ADDR_SM_TYPE is ( IDLE, LD_ARADDR ); signal rd_addr_sm_cs, rd_addr_sm_ns : RD_ADDR_SM_TYPE; signal ar_active_set : std_logic := '0'; signal ar_active_set_i : std_logic := '0'; signal ar_active_clr : std_logic := '0'; signal ar_active : std_logic := '0'; signal ar_active_d1 : std_logic := '0'; signal ar_active_re : std_logic := '0'; signal axi_araddr_pipe : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal curr_araddr_lsb : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0'); signal araddr_pipe_ld : std_logic := '0'; signal araddr_pipe_ld_i : std_logic := '0'; signal araddr_pipe_sel : std_logic := '0'; -- '0' indicates mux select from AXI -- '1' indicates mux select from AR Addr Register signal axi_araddr_full : std_logic := '0'; signal axi_arready_int : std_logic := '0'; signal axi_early_arready_int : std_logic := '0'; signal axi_aresetn_d1 : std_logic := '0'; signal axi_aresetn_d2 : std_logic := '0'; signal axi_aresetn_re : std_logic := '0'; signal axi_aresetn_re_reg : std_logic := '0'; signal no_ar_ack_cmb : std_logic := '0'; signal no_ar_ack : std_logic := '0'; signal pend_rd_op_cmb : std_logic := '0'; signal pend_rd_op : std_logic := '0'; signal axi_arid_pipe : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_arsize_pipe : std_logic_vector (2 downto 0) := (others => '0'); signal axi_arsize_pipe_4byte : std_logic := '0'; signal axi_arsize_pipe_8byte : std_logic := '0'; signal axi_arsize_pipe_16byte : std_logic := '0'; signal axi_arsize_pipe_32byte : std_logic := '0'; -- v1.03a signal axi_arsize_pipe_max : std_logic := '0'; signal curr_arsize : std_logic_vector (2 downto 0) := (others => '0'); signal curr_arsize_reg : std_logic_vector (2 downto 0) := (others => '0'); signal axi_arlen_pipe : std_logic_vector(7 downto 0) := (others => '0'); signal axi_arlen_pipe_1_or_2 : std_logic := '0'; signal curr_arlen : std_logic_vector(7 downto 0) := (others => '0'); signal curr_arlen_reg : std_logic_vector(7 downto 0) := (others => '0'); signal axi_arburst_pipe : std_logic_vector(1 downto 0) := (others => '0'); signal axi_arburst_pipe_fixed : std_logic := '0'; signal curr_arburst : std_logic_vector(1 downto 0) := (others => '0'); signal curr_wrap_burst : std_logic := '0'; signal curr_wrap_burst_reg : std_logic := '0'; signal max_wrap_burst : std_logic := '0'; signal curr_incr_burst : std_logic := '0'; signal curr_fixed_burst : std_logic := '0'; signal curr_fixed_burst_reg : std_logic := '0'; -- BRAM Address Counter signal bram_addr_ld_en : std_logic := '0'; signal bram_addr_ld_en_i : std_logic := '0'; signal bram_addr_ld_en_mod : std_logic := '0'; signal bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_ld_wrap : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_inc : std_logic := '0'; signal bram_addr_inc_mod : std_logic := '0'; signal bram_addr_inc_wrap_mod : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Read Data Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type RD_DATA_SM_TYPE is ( IDLE, SNG_ADDR, SEC_ADDR, FULL_PIPE, FULL_THROTTLE, LAST_ADDR, LAST_THROTTLE, LAST_DATA, LAST_DATA_AR_PEND ); signal rd_data_sm_cs, rd_data_sm_ns : RD_DATA_SM_TYPE; signal rd_adv_buf : std_logic := '0'; signal axi_rd_burst : std_logic := '0'; signal axi_rd_burst_two : std_logic := '0'; signal act_rd_burst : std_logic := '0'; signal act_rd_burst_set : std_logic := '0'; signal act_rd_burst_clr : std_logic := '0'; signal act_rd_burst_two : std_logic := '0'; -- Rd Data Buffer/Register signal rd_skid_buf_ld_cmb : std_logic := '0'; signal rd_skid_buf_ld_reg : std_logic := '0'; signal rd_skid_buf_ld : std_logic := '0'; signal rd_skid_buf_ld_imm : std_logic := '0'; signal rd_skid_buf : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal rddata_mux_sel_cmb : std_logic := '0'; signal rddata_mux_sel : std_logic := '0'; signal axi_rdata_en : std_logic := '0'; signal axi_rdata_mux : std_logic_vector (C_AXI_DATA_WIDTH+8*C_ECC-1 downto 0) := (others => '0'); -- Read Burst Counter signal brst_cnt_max : std_logic := '0'; signal brst_cnt_max_d1 : std_logic := '0'; signal brst_cnt_max_re : std_logic := '0'; signal end_brst_rd_clr_cmb : std_logic := '0'; signal end_brst_rd_clr : std_logic := '0'; signal end_brst_rd : std_logic := '0'; signal brst_zero : std_logic := '0'; signal brst_one : std_logic := '0'; signal brst_cnt_ld : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0'); signal brst_cnt_rst : std_logic := '0'; signal brst_cnt_ld_en : std_logic := '0'; signal brst_cnt_ld_en_i : std_logic := '0'; signal brst_cnt_dec : std_logic := '0'; signal brst_cnt : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0'); -- AXI Read Response Signals signal axi_rid_temp : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_rid_temp_full : std_logic := '0'; signal axi_rid_temp_full_d1 : std_logic := '0'; signal axi_rid_temp_full_fe : std_logic := '0'; signal axi_rid_temp2 : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_rid_temp2_full : std_logic := '0'; signal axi_b2b_rid_adv : std_logic := '0'; signal axi_rid_int : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0'); signal axi_rvalid_clr_ok : std_logic := '0'; signal axi_rvalid_set_cmb : std_logic := '0'; signal axi_rvalid_set : std_logic := '0'; signal axi_rvalid_int : std_logic := '0'; signal axi_rlast_int : std_logic := '0'; signal axi_rlast_set : std_logic := '0'; -- Internal BRAM Signals signal bram_en_cmb : std_logic := '0'; signal bram_en_int : std_logic := '0'; signal bram_addr_int : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- Narrow Burst Signals signal curr_narrow_burst_cmb : std_logic := '0'; signal curr_narrow_burst : std_logic := '0'; signal narrow_burst_cnt_ld : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_burst_cnt_ld_reg : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_burst_cnt_ld_mod : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_addr_rst : std_logic := '0'; signal narrow_addr_ld_en : std_logic := '0'; signal narrow_addr_dec : std_logic := '0'; signal narrow_bram_addr_inc : std_logic := '0'; signal narrow_bram_addr_inc_d1 : std_logic := '0'; signal narrow_bram_addr_inc_re : std_logic := '0'; signal narrow_addr_int : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal curr_ua_narrow_wrap : std_logic := '0'; signal curr_ua_narrow_incr : std_logic := '0'; signal ua_narrow_load : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); -- State machine type declarations type RLAST_SM_TYPE is ( IDLE, W8_THROTTLE, W8_2ND_LAST_DATA, W8_LAST_DATA, -- W8_LAST_DATA_B2, W8_THROTTLE_B2 ); signal rlast_sm_cs, rlast_sm_ns : RLAST_SM_TYPE; signal last_bram_addr : std_logic := '0'; signal set_last_bram_addr : std_logic := '0'; signal alast_bram_addr : std_logic := '0'; signal rd_b2b_elgible : std_logic := '0'; signal rd_b2b_elgible_no_thr_check : std_logic := '0'; signal throttle_last_data : std_logic := '0'; signal disable_b2b_brst_cmb : std_logic := '0'; signal disable_b2b_brst : std_logic := '0'; signal axi_b2b_brst_cmb : std_logic := '0'; signal axi_b2b_brst : std_logic := '0'; signal do_cmplt_burst_cmb : std_logic := '0'; signal do_cmplt_burst : std_logic := '0'; signal do_cmplt_burst_clr : std_logic := '0'; ------------------------------------------------------------------------------- -- ECC Signals ------------------------------------------------------------------------------- signal UnCorrectedRdData : std_logic_vector (0 to C_AXI_DATA_WIDTH-1) := (others => '0'); -- Move vector from core ECC module to use in AXI RDATA register output signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to ECC @ 32-bit data width signal Syndrome_7 : std_logic_vector (0 to 11) := (others => '0'); -- Specific to ECC @ 64-bit data width signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal Sl_UE_i : std_logic := '0'; signal UE_Q : std_logic := '0'; -- v1.03a -- Hsiao ECC signal syndrome_r : std_logic_vector (C_INT_ECC_WIDTH - 1 downto 0) := (others => '0'); constant CODE_WIDTH : integer := C_AXI_DATA_WIDTH + C_INT_ECC_WIDTH; constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- AXI Read Address Channel Output Signals --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_ARREADY_DUAL -- Purpose: Generate AXI_ARREADY when in dual port mode. --------------------------------------------------------------------------- GEN_ARREADY_DUAL: if C_SINGLE_PORT_BRAM = 0 generate begin -- Ensure ARREADY only gets asserted early when acknowledge recognized -- on AXI read data channel. AXI_ARREADY <= axi_arready_int or (axi_early_arready_int and rd_adv_buf); end generate GEN_ARREADY_DUAL; --------------------------------------------------------------------------- -- Generate: GEN_ARREADY_SNG -- Purpose: Generate AXI_ARREADY when in single port mode. --------------------------------------------------------------------------- GEN_ARREADY_SNG: if C_SINGLE_PORT_BRAM = 1 generate begin -- ARREADY generated by sng_port_arb module AXI_ARREADY <= '0'; axi_arready_int <= '0'; end generate GEN_ARREADY_SNG; --------------------------------------------------------------------------- -- AXI Read Data Channel Output Signals --------------------------------------------------------------------------- -- UE flag is detected is same clock cycle that read data is presented on -- the AXI bus. Must drive SLVERR combinatorially to align with corrupted -- detected data word. AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int; AXI_RVALID <= axi_rvalid_int; AXI_RID <= axi_rid_int; AXI_RLAST <= axi_rlast_int; --------------------------------------------------------------------------- -- -- *** AXI Read Address Channel Interface *** -- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_AR_PIPE_SNG -- Purpose: Only generate pipeline registers when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AR_PIPE_SNG: if C_SINGLE_PORT_BRAM = 1 generate begin -- Unused AW pipeline (set default values) araddr_pipe_ld <= '0'; axi_araddr_pipe <= AXI_ARADDR; axi_arid_pipe <= AXI_ARID; axi_arsize_pipe <= AXI_ARSIZE; axi_arlen_pipe <= AXI_ARLEN; axi_arburst_pipe <= AXI_ARBURST; axi_arlen_pipe_1_or_2 <= '0'; axi_arburst_pipe_fixed <= '0'; axi_araddr_full <= '0'; end generate GEN_AR_PIPE_SNG; --------------------------------------------------------------------------- -- Generate: GEN_AR_PIPE_DUAL -- Purpose: Only generate pipeline registers when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AR_PIPE_DUAL: if C_SINGLE_PORT_BRAM = 0 generate begin ----------------------------------------------------------------------- -- AXI Read Address Buffer/Register -- (mimic behavior of address pipeline for AXI_ARID) ----------------------------------------------------------------------- GEN_ARADDR: for i in C_AXI_ADDR_WIDTH-1 downto 0 generate begin REG_ARADDR: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- No reset condition to save resources/timing if (araddr_pipe_ld = '1') then axi_araddr_pipe (i) <= AXI_ARADDR (i); else axi_araddr_pipe (i) <= axi_araddr_pipe (i); end if; end if; end process REG_ARADDR; end generate GEN_ARADDR; ------------------------------------------------------------------- -- Register ARID -- No reset condition to save resources/timing ------------------------------------------------------------------- REG_ARID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (araddr_pipe_ld = '1') then axi_arid_pipe <= AXI_ARID; else axi_arid_pipe <= axi_arid_pipe; end if; end if; end process REG_ARID; --------------------------------------------------------------------------- -- In parallel to ARADDR pipeline and ARID -- Use same control signals to capture AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST. -- Register AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST -- No reset condition to save resources/timing REG_ARCTRL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (araddr_pipe_ld = '1') then axi_arsize_pipe <= AXI_ARSIZE; axi_arlen_pipe <= AXI_ARLEN; axi_arburst_pipe <= AXI_ARBURST; else axi_arsize_pipe <= axi_arsize_pipe; axi_arlen_pipe <= axi_arlen_pipe; axi_arburst_pipe <= axi_arburst_pipe; end if; end if; end process REG_ARCTRL; --------------------------------------------------------------------------- -- Create signals that indicate value of AXI_ARLEN in pipeline stage -- Used to decode length of burst when BRAM address can be loaded early -- when pipeline is full. -- -- Add early decode of ARBURST in pipeline. -- Copy logic from WR_CHNL module (similar logic). -- Add early decode of ARSIZE = 4 bytes in pipeline. REG_ARLEN_PIPE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- No reset condition to save resources/timing if (araddr_pipe_ld = '1') then -- Create merge to decode ARLEN of ONE or TWO if (AXI_ARLEN = AXI_ARLEN_ONE) or (AXI_ARLEN = AXI_ARLEN_TWO) then axi_arlen_pipe_1_or_2 <= '1'; else axi_arlen_pipe_1_or_2 <= '0'; end if; -- Early decode on value in pipeline of ARBURST if (AXI_ARBURST = C_AXI_BURST_FIXED) then axi_arburst_pipe_fixed <= '1'; else axi_arburst_pipe_fixed <= '0'; end if; else axi_arlen_pipe_1_or_2 <= axi_arlen_pipe_1_or_2; axi_arburst_pipe_fixed <= axi_arburst_pipe_fixed; end if; end if; end process REG_ARLEN_PIPE; --------------------------------------------------------------------------- -- Create full flag for ARADDR pipeline -- Set when read address register is loaded. -- Cleared when read address stored in register is loaded into BRAM -- address counter. REG_RDADDR_FULL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- (bram_addr_ld_en = '1' and araddr_pipe_sel = '1') then (bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and araddr_pipe_ld = '0') then axi_araddr_full <= '0'; elsif (araddr_pipe_ld = '1') then axi_araddr_full <= '1'; else axi_araddr_full <= axi_araddr_full; end if; end if; end process REG_RDADDR_FULL; --------------------------------------------------------------------------- end generate GEN_AR_PIPE_DUAL; --------------------------------------------------------------------------- -- v1.03a -- Add early decode of ARSIZE = max size in pipeline based on AXI data -- bus width (use constant, C_AXI_SIZE_MAX) REG_ARSIZE_PIPE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_arsize_pipe_max <= '0'; elsif (araddr_pipe_ld = '1') then -- Early decode of ARSIZE in pipeline equal to max # of bytes -- based on AXI data bus width if (AXI_ARSIZE = C_AXI_SIZE_MAX) then axi_arsize_pipe_max <= '1'; else axi_arsize_pipe_max <= '0'; end if; else axi_arsize_pipe_max <= axi_arsize_pipe_max; end if; end if; end process REG_ARSIZE_PIPE; --------------------------------------------------------------------------- -- Generate: GE_ARREADY -- Purpose: ARREADY is only created here when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_ARREADY: if (C_SINGLE_PORT_BRAM = 0) generate begin ---------------------------------------------------------------------------- -- AXI_ARREADY Output Register -- Description: Keep AXI_ARREADY output asserted until ARADDR pipeline -- is full. When a full condition is reached, negate -- ARREADY as another AR address can not be accepted. -- Add condition to keep ARReady asserted if loading current --- ARADDR pipeline value into the BRAM address counter. -- Indicated by assertion of bram_addr_ld_en & araddr_pipe_sel. -- ---------------------------------------------------------------------------- REG_ARREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_arready_int <= '0'; -- Detect end of S_AXI_AResetn to assert AWREADY and accept -- new AWADDR values elsif (axi_aresetn_re_reg = '1') or -- Add condition for early ARREADY to keep pipeline full (bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and axi_early_arready_int = '0') then axi_arready_int <= '1'; -- Add conditional check if ARREADY is asserted (with ARVALID) (one clock cycle later) -- when the address pipeline is full. elsif (araddr_pipe_ld = '1') or (AXI_ARVALID = '1' and axi_arready_int = '1' and axi_araddr_full = '1') then axi_arready_int <= '0'; else axi_arready_int <= axi_arready_int; end if; end if; end process REG_ARREADY; ---------------------------------------------------------------------------- REG_EARLY_ARREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_early_arready_int <= '0'; -- Pending ARADDR and ARREADY is not yet asserted to accept -- operation (due to ARADDR being full) elsif (AXI_ARVALID = '1' and axi_arready_int = '0' and axi_araddr_full = '1') and (alast_bram_addr = '1') and -- Add check for elgible back-to-back BRAM load (rd_b2b_elgible = '1') then axi_early_arready_int <= '1'; else axi_early_arready_int <= '0'; end if; end if; end process REG_EARLY_ARREADY; --------------------------------------------------------------------------- -- Need to detect end of reset cycle to assert ARREADY on AXI bus REG_ARESETN: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then axi_aresetn_d1 <= S_AXI_AResetn; axi_aresetn_d2 <= axi_aresetn_d1; axi_aresetn_re_reg <= axi_aresetn_re; end if; end process REG_ARESETN; -- Create combinatorial RE detect of S_AXI_AResetn axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0'; ---------------------------------------------------------------------------- end generate GEN_ARREADY; --------------------------------------------------------------------------- -- Generate: GEN_DUAL_ADDR_CNT -- Purpose: Instantiate BRAM address counter unique for wr_chnl logic -- only when controller configured in dual port mode. --------------------------------------------------------------------------- GEN_DUAL_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 0) generate begin --------------------------------------------------------------------------- -- Replace I_ADDR_CNT module usage of pf_counter in proc_common library. -- Only need to use lower 12-bits of address due to max AXI burst size -- Since AXI guarantees bursts do not cross 4KB boundary, the counting part -- of I_ADDR_CNT can be reduced to max 4KB. -- -- No reset on bram_addr_int. -- Increment ONLY. REG_ADDR_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (bram_addr_ld_en_mod = '1') then bram_addr_int <= bram_addr_ld; elsif (bram_addr_inc_mod = '1') then bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12) <= bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12); bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <= std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1); end if; end if; end process REG_ADDR_CNT; --------------------------------------------------------------------------- -- Set defaults to shared address counter -- Only used in single port configurations Sng_BRAM_Addr_Ld_En <= '0'; Sng_BRAM_Addr_Ld <= (others => '0'); Sng_BRAM_Addr_Inc <= '0'; end generate GEN_DUAL_ADDR_CNT; --------------------------------------------------------------------------- -- Generate: GEN_SNG_ADDR_CNT -- Purpose: When configured in single port BRAM mode, address counter -- is shared with rd_chnl module. Assign output signals here -- to counter instantiation at full_axi module level. --------------------------------------------------------------------------- GEN_SNG_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 1) generate begin Sng_BRAM_Addr_Ld_En <= bram_addr_ld_en_mod; Sng_BRAM_Addr_Ld <= bram_addr_ld; Sng_BRAM_Addr_Inc <= bram_addr_inc_mod; bram_addr_int <= Sng_BRAM_Addr; end generate GEN_SNG_ADDR_CNT; --------------------------------------------------------------------------- -- BRAM address load mux. -- Either load BRAM counter directly from AXI bus or from stored registered value -- Use registered signal to indicate current operation is a WRAP burst -- -- Match bram_addr_ld to what asserts bram_addr_ld_en_mod -- Include bram_addr_inc_mod when asserted to use bram_addr_ld_wrap value -- (otherwise use pipelined or AXI bus value to load BRAM address counter) bram_addr_ld <= bram_addr_ld_wrap when (max_wrap_burst = '1' and curr_wrap_burst_reg = '1' and bram_addr_inc_wrap_mod = '1') else axi_araddr_pipe (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) when (araddr_pipe_sel = '1') else AXI_ARADDR (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); --------------------------------------------------------------------------- -- On wrap burst max loads (simultaneous BRAM address increment is asserted). -- Ensure that load has higher priority over increment. -- Use registered signal to indicate current operation is a WRAP burst bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or (max_wrap_burst = '1' and curr_wrap_burst_reg = '1' and bram_addr_inc_wrap_mod = '1')) else '0'; -- Create a special bram_addr_inc_mod for use in the bram_addr_ld_en_mod signal -- logic. No need for the check if the current operation is NOT a fixed AND a wrap -- burst. The transfer will be one or the other. -- Found issue when narrow FIXED length burst is incorrectly -- incrementing BRAM address counter bram_addr_inc_wrap_mod <= bram_addr_inc when (curr_narrow_burst = '0') else narrow_bram_addr_inc_re; ---------------------------------------------------------------------------- -- Narrow bursting -- -- Handle read burst addressing on narrow burst operations -- Intercept BRAM address increment flag, bram_addr_inc and only -- increment address when the number of BRAM reads match the width of the -- AXI data bus. -- For a 32-bit BRAM, byte burst will increment the BRAM address -- after four reads from BRAM. -- For a 256-bit BRAM, a byte burst will increment the BRAM address -- after 32 reads from BRAM. -- Based on current operation being a narrow burst, hold off BRAM -- address increment until narrow burst fits BRAM data width. -- For non narrow burst operations, use bram_addr_inc from data SM. -- -- Add in check that burst type is not FIXED, curr_fixed_burst_reg -- bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else -- narrow_bram_addr_inc_re; -- -- -- Replace w/ below generate statements based on supporting narrow transfers or not. -- Create generate statement around the signal assignment for bram_addr_inc_mod. --------------------------------------------------------------------------- -- Generate: GEN_BRAM_INC_MOD_W_NARROW -- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers -- are supported in design instantiation. --------------------------------------------------------------------------- GEN_BRAM_INC_MOD_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin -- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else (narrow_bram_addr_inc_re and not (curr_fixed_burst_reg)); end generate GEN_BRAM_INC_MOD_W_NARROW; --------------------------------------------------------------------------- -- Generate: GEN_WO_NARROW -- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers -- are not supported in the design instantiation. -- Drive default values for narrow counter and logic when -- narrow operation support is disabled. --------------------------------------------------------------------------- GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate begin -- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter bram_addr_inc_mod <= bram_addr_inc and not (curr_fixed_burst_reg); narrow_addr_rst <= '0'; narrow_burst_cnt_ld_mod <= (others => '0'); narrow_addr_dec <= '0'; narrow_addr_ld_en <= '0'; narrow_bram_addr_inc <= '0'; narrow_bram_addr_inc_d1 <= '0'; narrow_bram_addr_inc_re <= '0'; narrow_addr_int <= (others => '0'); curr_narrow_burst <= '0'; end generate GEN_WO_NARROW; --------------------------------------------------------------------------- -- -- Only instantiate NARROW_CNT and supporting logic when narrow transfers -- are supported and utilized by masters in the AXI system. -- The design parameter, C_S_AXI_SUPPORTS_NARROW will indicate this. -- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NARROW_CNT -- Purpose: Instantiate narrow counter and logic when narrow -- operation support is enabled. --------------------------------------------------------------------------- GEN_NARROW_CNT: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin --------------------------------------------------------------------------- -- -- Generate seperate smaller counter for narrow burst operations -- Replace I_NARROW_CNT module usage of pf_counter_top from proc_common library. -- -- Counter size is adjusted based on size of data burst. -- -- For example, 32-bit data width BRAM, minimum narrow width -- burst is 8 bits resulting in a count 3 downto 0. So the -- minimum counter width = 2 bits. -- -- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst -- is 8 bits resulting in a count 31 downto 0. So the -- minimum counter width = 5 bits. -- -- Size of counter = C_NARROW_BURST_CNT_LEN -- --------------------------------------------------------------------------- REG_NARROW_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (narrow_addr_rst = '1') then narrow_addr_int <= (others => '0'); -- Load enable elsif (narrow_addr_ld_en = '1') then narrow_addr_int <= narrow_burst_cnt_ld_mod; -- Decrement ONLY (no increment functionality) elsif (narrow_addr_dec = '1') then narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0) <= std_logic_vector (unsigned (narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0)) - 1); end if; end if; end process REG_NARROW_CNT; --------------------------------------------------------------------------- narrow_addr_rst <= not (S_AXI_AResetn); -- Modify narrow burst count load value based on -- unalignment of AXI address value narrow_burst_cnt_ld_mod <= ua_narrow_load when (curr_ua_narrow_wrap = '1' or curr_ua_narrow_incr = '1') else narrow_burst_cnt_ld when (bram_addr_ld_en = '1') else narrow_burst_cnt_ld_reg; narrow_addr_dec <= bram_addr_inc when (curr_narrow_burst = '1') else '0'; narrow_addr_ld_en <= (curr_narrow_burst_cmb and bram_addr_ld_en) or narrow_bram_addr_inc_re; narrow_bram_addr_inc <= '1' when (narrow_addr_int = NARROW_CNT_MAX) and (curr_narrow_burst = '1') -- Ensure that narrow address counter doesn't -- flag max or get loaded to -- reset narrow counter until AXI read data -- bus has acknowledged current -- data on the AXI bus. Use rd_adv_buf signal -- to indicate the non throttle -- condition on the AXI bus. and (bram_addr_inc = '1') else '0'; ---------------------------------------------------------------------------- -- Detect rising edge of narrow_bram_addr_inc REG_NARROW_BRAM_ADDR_INC: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then narrow_bram_addr_inc_d1 <= '0'; else narrow_bram_addr_inc_d1 <= narrow_bram_addr_inc; end if; end if; end process REG_NARROW_BRAM_ADDR_INC; narrow_bram_addr_inc_re <= '1' when (narrow_bram_addr_inc = '1') and (narrow_bram_addr_inc_d1 = '0') else '0'; --------------------------------------------------------------------------- end generate GEN_NARROW_CNT; ---------------------------------------------------------------------------- -- Specify current ARSIZE signal -- Address pipeline MUX curr_arsize <= axi_arsize_pipe when (araddr_pipe_sel = '1') else AXI_ARSIZE; REG_ARSIZE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then curr_arsize_reg <= (others => '0'); -- Register curr_arsize when bram_addr_ld_en = '1' elsif (bram_addr_ld_en = '1') then curr_arsize_reg <= curr_arsize; else curr_arsize_reg <= curr_arsize_reg; end if; end if; end process REG_ARSIZE; --------------------------------------------------------------------------- -- Generate: GEN_NARROW_EN -- Purpose: Only instantiate logic to determine if current burst -- is a narrow burst when narrow bursting logic is supported. --------------------------------------------------------------------------- GEN_NARROW_EN: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin ----------------------------------------------------------------------- -- Determine "narrow" burst transfers -- Compare the ARSIZE to the BRAM data width ----------------------------------------------------------------------- -- v1.03a -- Detect if current burst operation is of size /= to the full -- AXI data bus width. If not, then the current operation is a -- "narrow" burst. curr_narrow_burst_cmb <= '1' when (curr_arsize /= C_AXI_SIZE_MAX) else '0'; --------------------------------------------------------------------------- -- Register flag indicating the current operation -- is a narrow read burst NARROW_BURST_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Need to reset this flag at end of narrow burst operation -- Ensure if curr_narrow_burst got set during previous transaction, axi_rlast_set -- doesn't clear the flag (add check for pend_rd_op negated). if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_set = '1' and pend_rd_op = '0' and bram_addr_ld_en = '0') then curr_narrow_burst <= '0'; -- Add check for burst operation using ARLEN value -- Ensure that narrow burst flag does not get set during FIXED burst types elsif (bram_addr_ld_en = '1') and (curr_arlen /= AXI_ARLEN_ONE) and (curr_fixed_burst = '0') then curr_narrow_burst <= curr_narrow_burst_cmb; end if; end if; end process NARROW_BURST_REG; end generate GEN_NARROW_EN; --------------------------------------------------------------------------- -- Generate: GEN_NARROW_CNT_LD -- Purpose: Only instantiate logic to determine narrow burst counter -- load value when narrow bursts are enabled. --------------------------------------------------------------------------- GEN_NARROW_CNT_LD: if (C_S_AXI_SUPPORTS_NARROW = 1) generate signal curr_arsize_unsigned : unsigned (2 downto 0) := (others => '0'); signal axi_byte_div_curr_arsize : integer := 1; begin -- v1.03a -- Create narrow burst counter load value based on current operation -- "narrow" data width (indicated by value of AWSIZE). curr_arsize_unsigned <= unsigned (curr_arsize); -- XST does not support divisors that are not constants and powers of 2. -- Create process to create a fixed value for divisor. -- Replace this statement: -- narrow_burst_cnt_ld <= std_logic_vector ( -- to_unsigned ( -- (C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_arsize_unsigned))) ) - 1, -- C_NARROW_BURST_CNT_LEN)); -- -- With this new process and subsequent signal assignment: -- DIV_AWSIZE: process (curr_arsize_unsigned) -- begin -- -- case (to_integer (curr_arsize_unsigned)) is -- when 0 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1; -- when 1 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2; -- when 2 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4; -- when 3 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8; -- when 4 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16; -- when 5 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32; -- when 6 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64; -- when 7 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128; -- --coverage off -- when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES; -- --coverage on -- end case; -- -- end process DIV_AWSIZE; -- w/ CR # 609695 -- With this new process and subsequent signal assignment: DIV_AWSIZE: process (curr_arsize_unsigned) begin case (curr_arsize_unsigned) is when "000" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1; when "001" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2; when "010" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4; when "011" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8; when "100" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16; when "101" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32; when "110" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64; when "111" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128; --coverage off when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES; --coverage on end case; end process DIV_AWSIZE; -- v1.03a -- Replace with new signal assignment. -- For synthesis to support only divisors that are constant and powers of two. -- Updated else clause for simulation warnings w/ CR # 609695 narrow_burst_cnt_ld <= std_logic_vector ( to_unsigned ( (axi_byte_div_curr_arsize) - 1, C_NARROW_BURST_CNT_LEN)) when (axi_byte_div_curr_arsize > 0) else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN)); --------------------------------------------------------------------------- -- Register narrow burst count load indicator REG_NAR_BRST_CNT_LD: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then narrow_burst_cnt_ld_reg <= (others => '0'); elsif (bram_addr_ld_en = '1') then narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld; else narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld_reg; end if; end if; end process REG_NAR_BRST_CNT_LD; --------------------------------------------------------------------------- end generate GEN_NARROW_CNT_LD; ---------------------------------------------------------------------------- -- Handling for WRAP burst types -- -- For WRAP burst types, the counter value will roll over when the burst -- boundary is reached. -- Boundary is reached based on ARSIZE and ARLEN. -- -- Goal is to minimize muxing on initial load of counter value. -- On WRAP burst types, detect when the max address is reached. -- When the max address is reached, re-load counter with lower -- address value set to '0'. ---------------------------------------------------------------------------- -- Detect valid WRAP burst types curr_wrap_burst <= '1' when (curr_arburst = C_AXI_BURST_WRAP) else '0'; curr_incr_burst <= '1' when (curr_arburst = C_AXI_BURST_INCR) else '0'; curr_fixed_burst <= '1' when (curr_arburst = C_AXI_BURST_FIXED) else '0'; ---------------------------------------------------------------------------- -- Register curr_wrap_burst & curr_fixed_burst signals when BRAM -- address counter is initially loaded REG_CURR_BRST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then curr_wrap_burst_reg <= '0'; curr_fixed_burst_reg <= '0'; elsif (bram_addr_ld_en = '1') then curr_wrap_burst_reg <= curr_wrap_burst; curr_fixed_burst_reg <= curr_fixed_burst; else curr_wrap_burst_reg <= curr_wrap_burst_reg; curr_fixed_burst_reg <= curr_fixed_burst_reg; end if; end if; end process REG_CURR_BRST; --------------------------------------------------------------------------- -- Instance: I_WRAP_BRST -- -- Description: -- -- Instantiate WRAP_BRST module -- Logic to generate the wrap around value to load into the BRAM address -- counter on WRAP burst transactions. -- WRAP value is based on current ARLEN, ARSIZE (for narrows) and -- data width of BRAM module. -- --------------------------------------------------------------------------- I_WRAP_BRST : entity work.wrap_brst generic map ( C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , curr_axlen => curr_arlen , curr_axsize => curr_arsize , curr_narrow_burst => curr_narrow_burst , narrow_bram_addr_inc_re => narrow_bram_addr_inc_re , bram_addr_ld_en => bram_addr_ld_en , bram_addr_ld => bram_addr_ld , bram_addr_int => bram_addr_int , bram_addr_ld_wrap => bram_addr_ld_wrap , max_wrap_burst_mod => max_wrap_burst ); ---------------------------------------------------------------------------- -- Specify current ARBURST signal -- Input address pipeline MUX curr_arburst <= axi_arburst_pipe when (araddr_pipe_sel = '1') else AXI_ARBURST; ---------------------------------------------------------------------------- -- Specify current AWBURST signal -- Input address pipeline MUX curr_arlen <= axi_arlen_pipe when (araddr_pipe_sel = '1') else AXI_ARLEN; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_UA_NARROW -- Purpose: Only instantiate logic for burst narrow WRAP operations when -- AXI bus protocol is not set for AXI-LITE and narrow -- burst operations are supported. -- --------------------------------------------------------------------------- GEN_UA_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin --------------------------------------------------------------------------- -- -- New logic to detect unaligned address on a narrow WRAP burst transaction. -- If this condition is met, then the narrow burst counter will be -- initially loaded with an offset value corresponding to the unalignment -- in the ARADDR value. -- -- -- Create a sub module for all logic to determine the narrow burst counter -- offset value on unaligned WRAP burst operations. -- -- Module generates the following signals: -- -- => curr_ua_narrow_wrap, to indicate the current -- operation is an unaligned narrow WRAP burst. -- -- => curr_ua_narrow_incr, to load narrow burst counter -- for unaligned INCR burst operations. -- -- => ua_narrow_load, narrow counter load value. -- Sized, (C_NARROW_BURST_CNT_LEN-1 downto 0) -- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Instance: I_UA_NARROW -- -- Description: -- -- Creates a narrow burst count load value when an operation -- is an unaligned narrow WRAP or INCR burst type. Used by -- I_NARROW_CNT module. -- -- Logic is customized for each C_AXI_DATA_WIDTH. -- --------------------------------------------------------------------------- I_UA_NARROW : entity work.ua_narrow generic map ( C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_NARROW_BURST_CNT_LEN => C_NARROW_BURST_CNT_LEN ) port map ( curr_wrap_burst => curr_wrap_burst , -- in curr_incr_burst => curr_incr_burst , -- in bram_addr_ld_en => bram_addr_ld_en , -- in curr_axlen => curr_arlen , -- in curr_axsize => curr_arsize , -- in curr_axaddr_lsb => curr_araddr_lsb , -- in curr_ua_narrow_wrap => curr_ua_narrow_wrap , -- out curr_ua_narrow_incr => curr_ua_narrow_incr , -- out ua_narrow_load => ua_narrow_load -- out ); -- Use in all C_AXI_DATA_WIDTH generate statements -- Only probe least significant BRAM address bits -- C_BRAM_ADDR_ADJUST_FACTOR offset down to 0. curr_araddr_lsb <= axi_araddr_pipe (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) when (araddr_pipe_sel = '1') else AXI_ARADDR (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0); end generate GEN_UA_NARROW; ---------------------------------------------------------------------------- -- -- New logic to detect if pending operation in ARADDR pipeline is -- elgible for back-to-back no "bubble" performance. And BRAM address -- counter can be loaded upon last BRAM address presented for the current -- operation. -- This condition exists when the ARADDR pipeline is full and the pending -- operation is a burst >= length of two data beats. -- And not a FIXED burst type (must be INCR or WRAP type). -- The DATA SM handles detecting a throttle condition and will void -- the capability to be a back-to-back in performance transaction. -- -- Add check if new operation is a narrow burst (to be loaded into BRAM -- counter) -- Add check for throttling condition on after last BRAM address is -- presented -- ---------------------------------------------------------------------------- -- v1.03a rd_b2b_elgible_no_thr_check <= '1' when (axi_araddr_full = '1') and (axi_arlen_pipe_1_or_2 /= '1') and (axi_arburst_pipe_fixed /= '1') and (disable_b2b_brst = '0') and (axi_arsize_pipe_max = '1') else '0'; rd_b2b_elgible <= '1' when (rd_b2b_elgible_no_thr_check = '1') and (throttle_last_data = '0') else '0'; -- Check if SM is in LAST_THROTTLE state which also indicates we are throttling at -- the last data beat in the read burst. Ensures that the bursts are not implemented -- as back-to-back bursts and RVALID will negate upon recognition of RLAST and RID -- pipeline will be advanced properly. -- Fix timing path on araddr_pipe_sel generated in RDADDR SM -- SM uses rd_b2b_elgible signal which checks throttle condition on -- last data beat to hold off loading new BRAM address counter for next -- back-to-back operation. -- Attempt to modify logic in generation of throttle_last_data signal. throttle_last_data <= '1' when ((brst_zero = '1') and (rd_adv_buf = '0')) or (rd_data_sm_cs = LAST_THROTTLE) else '0'; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_AR_SNG -- Purpose: If single port BRAM configuration, set all AR flags from -- logic generated in sng_port_arb module. -- --------------------------------------------------------------------------- GEN_AR_SNG: if (C_SINGLE_PORT_BRAM = 1) generate begin araddr_pipe_sel <= '0'; -- Unused in single port configuration ar_active <= Arb2AR_Active; bram_addr_ld_en <= ar_active_re; brst_cnt_ld_en <= ar_active_re; AR2Arb_Active_Clr <= axi_rlast_int and AXI_RREADY; -- Rising edge detect of Arb2AR_Active RE_AR_ACT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Clear ar_active_d1 early w/ ar_active -- So back to back ar_active assertions see the new transaction -- and initiate the read transfer. if (S_AXI_AResetn = C_RESET_ACTIVE) or ((axi_rlast_int and AXI_RREADY) = '1') then ar_active_d1 <= '0'; else ar_active_d1 <= ar_active; end if; end if; end process RE_AR_ACT; ar_active_re <= '1' when (ar_active = '1' and ar_active_d1 = '0') else '0'; end generate GEN_AR_SNG; --------------------------------------------------------------------------- -- -- Generate: GEN_AW_DUAL -- Purpose: Generate AW control state machine logic only when AXI4 -- controller is configured for dual port mode. In dual port -- mode, wr_chnl has full access over AW & port A of BRAM. -- --------------------------------------------------------------------------- GEN_AR_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate begin AR2Arb_Active_Clr <= '0'; -- Only used in single port case --------------------------------------------------------------------------- -- RD ADDR State Machine -- -- Description: Central processing unit for AXI write address -- channel interface handling and handshaking. -- -- Outputs: araddr_pipe_ld Not Registered -- araddr_pipe_sel Not Registered -- bram_addr_ld_en Not Registered -- brst_cnt_ld_en Not Registered -- ar_active_set Not Registered -- -- WR_ADDR_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_ADDR_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- RD_ADDR_SM_CMB_PROCESS: process ( AXI_ARVALID, axi_araddr_full, ar_active, no_ar_ack, pend_rd_op, last_bram_addr, rd_b2b_elgible, rd_addr_sm_cs ) begin -- assign default values for state machine outputs rd_addr_sm_ns <= rd_addr_sm_cs; araddr_pipe_ld_i <= '0'; bram_addr_ld_en_i <= '0'; brst_cnt_ld_en_i <= '0'; ar_active_set_i <= '0'; case rd_addr_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Reload BRAM address counter on last BRAM address of current burst -- if a new address is pending in the AR pipeline and is elgible to -- be loaded for subsequent back-to-back performance. if (last_bram_addr = '1' and rd_b2b_elgible = '1') then -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; brst_cnt_ld_en_i <= '1'; ar_active_set_i <= '1'; -- If loading BRAM counter for subsequent operation -- AND ARVALID is pending on the bus, go ahead and respond -- and fill ARADDR pipeline with next operation. -- -- Asserting the signal to load the ARADDR pipeline here -- allows the full bandwidth utilization to BRAM on -- back to back bursts of two data beats. if (AXI_ARVALID = '1') then araddr_pipe_ld_i <= '1'; rd_addr_sm_ns <= LD_ARADDR; else rd_addr_sm_ns <= IDLE; end if; elsif (AXI_ARVALID = '1') then -- If address pipeline is full -- ARReady output is negated -- Remain in this state -- -- Add check for already pending read operation -- in data SM, but waiting on throttle (even though ar_active is -- already set to '0'). if (ar_active = '0') and (no_ar_ack = '0') and (pend_rd_op = '0') then rd_addr_sm_ns <= IDLE; bram_addr_ld_en_i <= '1'; brst_cnt_ld_en_i <= '1'; ar_active_set_i <= '1'; -- Address counter is currently busy else -- Check if ARADDR pipeline is not full and can be loaded if (axi_araddr_full = '0') then rd_addr_sm_ns <= LD_ARADDR; araddr_pipe_ld_i <= '1'; end if; end if; -- ar_active -- Pending operation in pipeline that is waiting -- until current operation is complete (ar_active = '0') elsif (axi_araddr_full = '1') and (ar_active = '0') and (no_ar_ack = '0') and (pend_rd_op = '0') then rd_addr_sm_ns <= IDLE; -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; brst_cnt_ld_en_i <= '1'; ar_active_set_i <= '1'; end if; -- ARVALID ---------------------------- LD_ARADDR State --------------------------- when LD_ARADDR => -- Check here for subsequent BRAM address load when ARADDR pipe is loaded -- in previous clock cycle. -- -- Reload BRAM address counter on last BRAM address of current burst -- if a new address is pending in the AR pipeline and is elgible to -- be loaded for subsequent back-to-back performance. if (last_bram_addr = '1' and rd_b2b_elgible = '1') then -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; brst_cnt_ld_en_i <= '1'; ar_active_set_i <= '1'; -- If loading BRAM counter for subsequent operation -- AND ARVALID is pending on the bus, go ahead and respond -- and fill ARADDR pipeline with next operation. -- -- Asserting the signal to load the ARADDR pipeline here -- allows the full bandwidth utilization to BRAM on -- back to back bursts of two data beats. if (AXI_ARVALID = '1') then araddr_pipe_ld_i <= '1'; rd_addr_sm_ns <= LD_ARADDR; -- Stay in this state another clock cycle else rd_addr_sm_ns <= IDLE; end if; else rd_addr_sm_ns <= IDLE; end if; --coverage off ------------------------------ Default ---------------------------- when others => rd_addr_sm_ns <= IDLE; --coverage on end case; end process RD_ADDR_SM_CMB_PROCESS; --------------------------------------------------------------------------- -- CR # 582705 -- Ensure combinatorial SM output signals do not get set before -- the end of the reset (and ARREAADY can be set). bram_addr_ld_en <= bram_addr_ld_en_i and axi_aresetn_d2; brst_cnt_ld_en <= brst_cnt_ld_en_i and axi_aresetn_d2; ar_active_set <= ar_active_set_i and axi_aresetn_d2; araddr_pipe_ld <= araddr_pipe_ld_i and axi_aresetn_d2; RD_ADDR_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- if (S_AXI_AResetn = C_RESET_ACTIVE) then -- CR # 582705 -- Ensure that ar_active does not get asserted (from SM) before -- the end of reset and the ARREADY flag is set. if (axi_aresetn_d2 = C_RESET_ACTIVE) then rd_addr_sm_cs <= IDLE; else rd_addr_sm_cs <= rd_addr_sm_ns; end if; end if; end process RD_ADDR_SM_REG_PROCESS; --------------------------------------------------------------------------- -- Assert araddr_pipe_sel outside of SM logic -- The BRAM address counter will get loaded with value in ARADDR pipeline -- when data is stored in the ARADDR pipeline. araddr_pipe_sel <= '1' when (axi_araddr_full = '1') else '0'; --------------------------------------------------------------------------- -- Register for ar_active REG_AR_ACT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- if (S_AXI_AResetn = C_RESET_ACTIVE) then -- CR # 582705 if (axi_aresetn_d2 = C_RESET_ACTIVE) then ar_active <= '0'; elsif (ar_active_set = '1') then ar_active <= '1'; -- For code coverage closure, ensure priority encoding in if/else clause -- to prevent checking ar_active_set in reset clause. elsif (ar_active_clr = '1') then ar_active <= '0'; else ar_active <= ar_active; end if; end if; end process REG_AR_ACT; end generate GEN_AR_DUAL; --------------------------------------------------------------------------- -- -- REG_BRST_CNT. -- Read Burst Counter. -- No need to decrement burst counter. -- Able to load with fixed burst length value. -- Replace usage of proc_common_v4_0 library with direct HDL. -- -- Size of counter = C_BRST_CNT_SIZE -- Max size of burst transfer = 256 data beats -- --------------------------------------------------------------------------- REG_BRST_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (brst_cnt_rst = '1') then brst_cnt <= (others => '0'); -- Load burst counter elsif (brst_cnt_ld_en = '1') then brst_cnt <= brst_cnt_ld; -- Decrement ONLY (no increment functionality) elsif (brst_cnt_dec = '1') then brst_cnt (C_BRST_CNT_SIZE-1 downto 0) <= std_logic_vector (unsigned (brst_cnt (C_BRST_CNT_SIZE-1 downto 0)) - 1); end if; end if; end process REG_BRST_CNT; --------------------------------------------------------------------------- brst_cnt_rst <= not (S_AXI_AResetn); -- Determine burst count load value -- Either load BRAM counter directly from AXI bus or from stored registered value. -- Use mux signal for ARLEN BRST_CNT_LD_PROCESS : process (curr_arlen) variable brst_cnt_ld_int : integer := 0; begin brst_cnt_ld_int := to_integer (unsigned (curr_arlen (7 downto 0))); brst_cnt_ld <= std_logic_vector (to_unsigned (brst_cnt_ld_int, 8)); end process BRST_CNT_LD_PROCESS; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_BRST_MAX_W_NARROW -- Purpose: Generate registered logic for brst_cnt_max when the -- design instantiation supports narrow operations. -- --------------------------------------------------------------------------- GEN_BRST_MAX_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin REG_BRST_MAX: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1') -- Added with single port (13.1 release) or (end_brst_rd_clr = '1') then brst_cnt_max <= '0'; -- Replace usage of brst_cnt in this logic. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then -- Hold off assertion of brst_cnt_max on narrow burst transfers -- Must wait until narrow burst count = 0. if (curr_narrow_burst = '1') then if (narrow_bram_addr_inc = '1') then brst_cnt_max <= '1'; end if; else brst_cnt_max <= '1'; end if; else brst_cnt_max <= brst_cnt_max; end if; end if; end process REG_BRST_MAX; end generate GEN_BRST_MAX_W_NARROW; --------------------------------------------------------------------------- -- -- Generate: GEN_BRST_MAX_WO_NARROW -- Purpose: Generate registered logic for brst_cnt_max when the -- design instantiation does not support narrow operations. -- --------------------------------------------------------------------------- GEN_BRST_MAX_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate begin REG_BRST_MAX: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1') then brst_cnt_max <= '0'; -- Replace usage of brst_cnt in this logic. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then -- When narrow operations are not supported in the core -- configuration, no check for curr_narrow_burst on assertion. brst_cnt_max <= '1'; else brst_cnt_max <= brst_cnt_max; end if; end if; end process REG_BRST_MAX; end generate GEN_BRST_MAX_WO_NARROW; --------------------------------------------------------------------------- REG_BRST_MAX_D1: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then brst_cnt_max_d1 <= '0'; else brst_cnt_max_d1 <= brst_cnt_max; end if; end if; end process REG_BRST_MAX_D1; brst_cnt_max_re <= '1' when (brst_cnt_max = '1') and (brst_cnt_max_d1 = '0') else '0'; -- Set flag that end of burst is reached -- Need to capture this condition as the burst -- counter may get reloaded for a subsequent read burst REG_END_BURST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- SM may assert clear flag early (in case of narrow bursts) -- Wait until the end_brst_rd flag is asserted to clear the flag. if (S_AXI_AResetn = C_RESET_ACTIVE) or (end_brst_rd_clr = '1' and end_brst_rd = '1') then end_brst_rd <= '0'; elsif (brst_cnt_max_re = '1') then end_brst_rd <= '1'; end if; end if; end process REG_END_BURST; --------------------------------------------------------------------------- -- Create flag that indicates burst counter is reaching ZEROs (max of burst -- length) REG_BURST_ZERO: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or ((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ZERO)) then brst_zero <= '0'; elsif (brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE) then brst_zero <= '1'; else brst_zero <= brst_zero; end if; end if; end process REG_BURST_ZERO; --------------------------------------------------------------------------- -- Create additional flag that indicates burst counter is reaching ONEs -- (near end of burst length). Used to disable back-to-back condition in SM. REG_BURST_ONE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or ((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ONE)) or ((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE)) then brst_one <= '0'; elsif ((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_TWO)) or ((brst_cnt_ld_en = '1') and (brst_cnt_ld = C_BRST_CNT_ONE)) then brst_one <= '1'; else brst_one <= brst_one; end if; end if; end process REG_BURST_ONE; --------------------------------------------------------------------------- -- Register flags for read burst operation REG_RD_BURST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Clear axi_rd_burst flags when burst count gets to zeros (unless the burst -- counter is getting subsequently loaded for the new burst operation) -- -- Replace usage of brst_cnt in this logic. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_zero = '1' and brst_cnt_ld_en = '0') then axi_rd_burst <= '0'; axi_rd_burst_two <= '0'; elsif (brst_cnt_ld_en = '1') then if (curr_arlen /= AXI_ARLEN_ONE and curr_arlen /= AXI_ARLEN_TWO) then axi_rd_burst <= '1'; else axi_rd_burst <= '0'; end if; if (curr_arlen = AXI_ARLEN_TWO) then axi_rd_burst_two <= '1'; else axi_rd_burst_two <= '0'; end if; else axi_rd_burst <= axi_rd_burst; axi_rd_burst_two <= axi_rd_burst_two; end if; end if; end process REG_RD_BURST; --------------------------------------------------------------------------- -- Seeing issue with axi_rd_burst getting cleared too soon -- on subsquent brst_cnt_ld_en early assertion and pend_rd_op is asserted. -- Create flag for currently active read burst operation -- Gets asserted when burst counter is loaded, but does not -- get cleared until the RD_DATA_SM has completed the read -- burst operation REG_ACT_RD_BURST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (act_rd_burst_clr = '1') then act_rd_burst <= '0'; act_rd_burst_two <= '0'; elsif (act_rd_burst_set = '1') then -- If not loading the burst counter for a B2B operation -- Then act_rd_burst follows axi_rd_burst and -- act_rd_burst_two follows axi_rd_burst_two. -- Get registered value of axi_* signal. if (brst_cnt_ld_en = '0') then act_rd_burst <= axi_rd_burst; act_rd_burst_two <= axi_rd_burst_two; else -- Otherwise, duplicate logic for axi_* signals if burst counter -- is getting loaded. -- For improved code coverage here -- The act_rd_burst_set signal will never get asserted if the burst -- size is less than two data beats. So, the conditional check -- for (curr_arlen /= AXI_ARLEN_ONE) is never evaluated. Removed -- from this if clause. if (curr_arlen /= AXI_ARLEN_TWO) then act_rd_burst <= '1'; else act_rd_burst <= '0'; end if; if (curr_arlen = AXI_ARLEN_TWO) then act_rd_burst_two <= '1'; else act_rd_burst_two <= '0'; end if; -- Note: re-code this if/else clause. end if; else act_rd_burst <= act_rd_burst; act_rd_burst_two <= act_rd_burst_two; end if; end if; end process REG_ACT_RD_BURST; --------------------------------------------------------------------------- rd_adv_buf <= axi_rvalid_int and AXI_RREADY; --------------------------------------------------------------------------- -- RD DATA State Machine -- -- Description: Central processing unit for AXI write data -- channel interface handling and AXI write data response -- handshaking. -- -- Outputs: Name Type -- -- bram_en_int Registered -- bram_addr_inc Not Registered -- brst_cnt_dec Not Registered -- rddata_mux_sel Registered -- axi_rdata_en Not Registered -- axi_rvalid_set Registered -- -- -- RD_DATA_SM_CMB_PROCESS: Combinational process to determine next state. -- RD_DATA_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- RD_DATA_SM_CMB_PROCESS: process ( bram_addr_ld_en, rd_adv_buf, ar_active, axi_araddr_full, rd_b2b_elgible_no_thr_check, disable_b2b_brst, curr_arlen, axi_rd_burst, axi_rd_burst_two, act_rd_burst, act_rd_burst_two, end_brst_rd, brst_zero, brst_one, axi_b2b_brst, bram_en_int, rddata_mux_sel, end_brst_rd_clr, no_ar_ack, pend_rd_op, axi_rlast_int, rd_data_sm_cs ) begin -- assign default values for state machine outputs rd_data_sm_ns <= rd_data_sm_cs; bram_en_cmb <= bram_en_int; bram_addr_inc <= '0'; brst_cnt_dec <= '0'; rd_skid_buf_ld_cmb <= '0'; rd_skid_buf_ld_imm <= '0'; rddata_mux_sel_cmb <= rddata_mux_sel; -- Change axi_rdata_en generated from SM to be a combinatorial signal -- Can't afford the latency when throttling on the AXI bus. axi_rdata_en <= '0'; axi_rvalid_set_cmb <= '0'; end_brst_rd_clr_cmb <= end_brst_rd_clr; no_ar_ack_cmb <= no_ar_ack; pend_rd_op_cmb <= pend_rd_op; act_rd_burst_set <= '0'; act_rd_burst_clr <= '0'; set_last_bram_addr <= '0'; alast_bram_addr <= '0'; axi_b2b_brst_cmb <= axi_b2b_brst; disable_b2b_brst_cmb <= disable_b2b_brst; ar_active_clr <= '0'; case rd_data_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Initiate BRAM read when address is available in controller -- Indicated by load of BRAM address counter -- Remove use of pend_rd_op signal. -- Never asserted as we transition back to IDLE -- Detected in code coverage if (bram_addr_ld_en = '1') then -- At start of new read, clear end burst signal end_brst_rd_clr_cmb <= '0'; -- Initiate BRAM read transfer bram_en_cmb <= '1'; -- Only count addresses & burst length for read -- burst operations -- If currently loading BRAM address counter -- Must check curr_arlen (mux output from pipe or AXI bus) -- to determine length of next operation. -- If ARLEN = 1 data beat, then set last_bram_addr signal -- Otherwise, increment BRAM address counter. if (curr_arlen /= AXI_ARLEN_ONE) then -- Start of new operation, update act_rd_burst and -- act_rd_burst_two signals act_rd_burst_set <= '1'; else -- Set flag for last_bram_addr on transition -- to SNG_ADDR on single operations. set_last_bram_addr <= '1'; end if; -- Go to single active read address state rd_data_sm_ns <= SNG_ADDR; end if; ------------------------- SNG_ADDR State -------------------------- when SNG_ADDR => -- Clear flag once pending read is recognized -- Duplicate logic here in case combinatorial flag was getting -- set as the SM transitioned into this state. if (pend_rd_op = '1') then pend_rd_op_cmb <= '0'; end if; -- At start of new read, clear end burst signal end_brst_rd_clr_cmb <= '0'; -- Reach this state on first BRAM address & enable assertion -- For burst operation, create next BRAM address and keep enable -- asserted -- Note: -- No ability to throttle yet as RVALID has not yet been -- asserted on the AXI bus -- Reset data mux select between skid buffer and BRAM -- Ensure read data mux is set for BRAM data rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM; -- Assert RVALID on AXI when 1st data beat available -- from BRAM axi_rvalid_set_cmb <= '1'; -- Reach this state when BRAM address counter is loaded -- Use axi_rd_burst and axi_rd_burst_two to indicate if -- operation is a single data beat burst. if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then -- Proceed directly to get BRAM read data rd_data_sm_ns <= LAST_ADDR; -- End of active current read address ar_active_clr <= '1'; -- Negate BRAM enable bram_en_cmb <= '0'; -- Load read data skid buffer for BRAM capture -- in next clock cycle rd_skid_buf_ld_cmb <= '1'; -- Assert new flag to disable back-to-back bursts -- due to throttling disable_b2b_brst_cmb <= '1'; -- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM -- address is loaded) and we are waiting for the current read burst to complete. if (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; end if; -- Read burst else -- Increment BRAM address counter (2nd data beat) bram_addr_inc <= '1'; -- Decrement BRAM burst counter (2nd data beat) brst_cnt_dec <= '1'; -- Keep BRAM enable asserted bram_en_cmb <= '1'; rd_data_sm_ns <= SEC_ADDR; -- Load read data skid buffer for BRAM capture -- in next clock cycle rd_skid_buf_ld_cmb <= '1'; -- Start of new operation, update act_rd_burst and -- act_rd_burst_two signals act_rd_burst_set <= '1'; -- If new burst is 2 data beats -- Then disable capability on back-to-back bursts if (axi_rd_burst_two = '1') then -- Assert new flag to disable back-to-back bursts -- due to throttling disable_b2b_brst_cmb <= '1'; else -- Support back-to-back for all other burst lengths disable_b2b_brst_cmb <= '0'; end if; end if; ------------------------- SEC_ADDR State -------------------------- when SEC_ADDR => -- Reach this state when the 2nd incremented address of the burst -- is presented to the BRAM. -- Only reach this state when axi_rd_burst = '1', -- an active read burst. -- Note: -- No ability to throttle yet as RVALID has not yet been -- asserted on the AXI bus -- Enable AXI read data register axi_rdata_en <= '1'; -- Only in dual port mode can the address counter get loaded early if C_SINGLE_PORT_BRAM = 0 then -- If we see the next address get loaded into the BRAM counter -- then set flag for pending operation if (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; end if; end if; -- Check here for burst length of two data transfers -- If so, then the SM will NOT hit the condition of a full -- pipeline: -- Operation A) 1st BRAM address data on AXI bus -- Operation B) 2nd BRAm address data read from BRAM -- Operation C) 3rd BRAM address presented to BRAM -- -- Full pipeline condition is hit for any read burst -- length greater than 2 data beats. if (axi_rd_burst_two = '1') then -- No increment of BRAM address -- or decrement of burst counter -- Burst counter should be = zero rd_data_sm_ns <= LAST_ADDR; -- End of active current read address ar_active_clr <= '1'; -- Ensure read data mux is set for BRAM data rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM; -- Negate BRAM enable bram_en_cmb <= '0'; -- Load read data skid buffer for BRAM capture -- in next clock cycle. -- This signal will negate in the next state -- if the data is not accepted on the AXI bus. -- So that no new data from BRAM is registered into the -- read channel controller. rd_skid_buf_ld_cmb <= '1'; else -- Burst length will hit full pipeline condition -- Increment BRAM address counter (3rd data beat) bram_addr_inc <= '1'; -- Decrement BRAM burst counter (3rd data beat) brst_cnt_dec <= '1'; -- Keep BRAM enable asserted bram_en_cmb <= '1'; rd_data_sm_ns <= FULL_PIPE; -- Assert almost last BRAM address flag -- so that ARVALID logic output can remain registered -- -- Replace usage of brst_cnt with signal, brst_one. if (brst_one = '1') then alast_bram_addr <= '1'; end if; -- Load read data skid buffer for BRAM capture -- in next clock cycle rd_skid_buf_ld_cmb <= '1'; end if; -- ARLEN = "0000 0001" ------------------------- FULL_PIPE State ------------------------- when FULL_PIPE => -- Reach this state when all three data beats in the burst -- are active -- -- Operation A) 1st BRAM address data on AXI bus -- Operation B) 2nd BRAM address data read from BRAM -- Operation C) 3rd BRAM address presented to BRAM -- Ensure read data mux is set for BRAM data rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM; -- With new pipelining capability BRAM address counter may be -- loaded in this state. This only occurs on back-to-back -- bursts (when enabled). -- No flag set for pending operation. -- Modify the if clause here to check for back-to-back burst operations -- If we load the BRAM address in this state for a subsequent burst, then -- this condition indicates a back-to-back burst and no need to assert -- the pending read operation flag. -- Seeing corner case when pend_rd_op needs to be asserted and cleared -- in this state. If the BRAM address counter is loaded early, but -- axi_rlast_set is delayed in getting asserted (all while in this state). -- The signal, curr_narrow_burst can not get cleared. -- Only in dual port mode can the address counter get loaded early if C_SINGLE_PORT_BRAM = 0 then -- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM -- address is loaded) and we are waiting for the current read burst to complete. if (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; -- Clear flag once pending read is recognized and -- earlier read data phase is complete. elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then pend_rd_op_cmb <= '0'; end if; end if; -- Check AXI throttling condition -- If AXI bus advances and accepts read data, SM can -- proceed with next data beat of burst. -- If not, then go to FULL_THROTTLE state to wait for -- AXI_RREADY = '1'. if (rd_adv_buf = '1') then -- Assert AXI read data enable for BRAM capture axi_rdata_en <= '1'; -- Load read data skid buffer for BRAM capture in next clock cycle rd_skid_buf_ld_cmb <= '1'; -- Assert almost last BRAM address flag -- so that ARVALID logic output can remain registered -- -- Replace usage of brst_cnt with signal, brst_one. if (brst_one = '1') then alast_bram_addr <= '1'; end if; -- Check burst counter for max -- If max burst count is reached, no new addresses -- presented to BRAM, advance to last capture data states. -- -- For timing, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (brst_zero = '1') or (end_brst_rd = '1' and axi_b2b_brst = '0') then -- Check for elgible pending read operation to support back-to-back performance. -- If so, load BRAM address counter. -- -- Replace rd_b2b_elgible signal check to remove path from -- arlen_pipe through rd_b2b_elgible -- (with data throttle check) if (rd_b2b_elgible_no_thr_check = '1') then rd_data_sm_ns <= FULL_PIPE; -- Set flag to indicate back-to-back read burst -- RVALID will not clear in this case and remain asserted axi_b2b_brst_cmb <= '1'; -- Set flag to update active read burst or -- read burst of two flag act_rd_burst_set <= '1'; -- Otherwise, complete current transaction else -- No increment of BRAM address -- or decrement of burst counter -- Burst counter should be = zero bram_addr_inc <= '0'; brst_cnt_dec <= '0'; rd_data_sm_ns <= LAST_ADDR; -- Negate BRAM enable bram_en_cmb <= '0'; -- End of active current read address ar_active_clr <= '1'; end if; else -- Remain in this state until burst count reaches zero -- Increment BRAM address counter (Nth data beat) bram_addr_inc <= '1'; -- Decrement BRAM burst counter (Nth data beat) brst_cnt_dec <= '1'; -- Keep BRAM enable asserted bram_en_cmb <= '1'; -- Skid buffer load will remain asserted -- AXI read data register is asserted end if; else -- Throttling condition detected rd_data_sm_ns <= FULL_THROTTLE; -- Ensure that AXI read data output register is disabled -- due to throttle condition. axi_rdata_en <= '0'; -- Skid buffer gets loaded from BRAM read data in next clock -- cycle ONLY. -- Only on transition to THROTTLE state does skid buffer get loaded. -- Negate load of read data skid buffer for BRAM capture -- in next clock cycle due to detection of Throttle condition rd_skid_buf_ld_cmb <= '0'; -- BRAM address is NOT getting incremented -- (same for burst counter) bram_addr_inc <= '0'; brst_cnt_dec <= '0'; -- If transitioning to throttle state -- Then next register enable assertion of the AXI read data -- output register needs to come from the skid buffer -- Set read data mux select here for SKID_BUFFER data rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; -- Detect if at end of burst read as we transition to FULL_THROTTLE -- If so, negate the BRAM enable even if prior to throttle condition -- on AXI bus. Read skid buffer will hold last beat of data in burst. -- -- For timing purposes, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (brst_zero = '1') or (end_brst_rd = '1') then -- No back to back "non bubble" support when AXI master -- is throttling on current burst. -- Seperate signal throttle_last_data will be asserted outside SM. -- End of burst read, negate BRAM enable bram_en_cmb <= '0'; -- Assert new flag to disable back-to-back bursts -- due to throttling disable_b2b_brst_cmb <= '1'; -- Disable B2B capability if throttling detected when -- burst count is equal to one. -- -- For timing purposes, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_one, indicating the -- brst_cnt to be one when decrement. elsif (brst_one = '1') then -- Assert new flag to disable back-to-back bursts -- due to throttling disable_b2b_brst_cmb <= '1'; -- Throttle, but not end of burst else bram_en_cmb <= '1'; end if; end if; -- rd_adv_buf (RREADY throttle) ------------------------- FULL_THROTTLE State --------------------- when FULL_THROTTLE => -- Reach this state when the AXI bus throttles on the AXI data -- beat read from BRAM (when the read pipeline is fully active) -- Flag disable_b2b_brst_cmb should be asserted as we transition -- to this state. Flag is asserted near the end of a read burst -- to prevent the back-to-back performance pipelining in the BRAM -- address counter. -- Detect if at end of burst read -- If so, negate the BRAM enable even if prior to throttle condition -- on AXI bus. Read skid buffer will hold last beat of data in burst. -- -- For timing, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (brst_zero = '1') or (end_brst_rd = '1') then bram_en_cmb <= '0'; end if; -- Set new flag for pending operation if bram_addr_ld_en is asserted (BRAM -- address is loaded) and we are waiting for the current read burst to complete. if (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; -- Clear flag once pending read is recognized and -- earlier read data phase is complete. elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then pend_rd_op_cmb <= '0'; end if; -- Wait for RREADY to be asserted w/ RVALID on AXI bus if (rd_adv_buf = '1') then -- Ensure read data mux is set for skid buffer data rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; -- Ensure that AXI read data output register is enabled axi_rdata_en <= '1'; -- Must reload skid buffer here from BRAM data -- so if needed can be presented to AXI bus on the following clock cycle rd_skid_buf_ld_imm <= '1'; -- When detecting end of throttle condition -- Check first if burst count is complete -- Check burst counter for max -- If max burst count is reached, no new addresses -- presented to BRAM, advance to last capture data states. -- -- For timing, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (brst_zero = '1') or (end_brst_rd = '1') then -- No back-to-back performance when AXI master throttles -- If we reach the end of the burst, proceed to LAST_ADDR state. -- No increment of BRAM address -- or decrement of burst counter -- Burst counter should be = zero bram_addr_inc <= '0'; brst_cnt_dec <= '0'; rd_data_sm_ns <= LAST_ADDR; -- Negate BRAM enable bram_en_cmb <= '0'; -- End of active current read address ar_active_clr <= '1'; -- Not end of current burst w/ throttle condition else -- Go back to FULL_PIPE rd_data_sm_ns <= FULL_PIPE; -- Assert almost last BRAM address flag -- so that ARVALID logic output can remain registered -- -- For timing purposes, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_one, indicating the -- brst_cnt to be one when decrement. if (brst_one = '1') then alast_bram_addr <= '1'; end if; -- Increment BRAM address counter (Nth data beat) bram_addr_inc <= '1'; -- Decrement BRAM burst counter (Nth data beat) brst_cnt_dec <= '1'; -- Keep BRAM enable asserted bram_en_cmb <= '1'; end if; -- Burst Max else -- Stay in this state -- Ensure that AXI read data output register is disabled -- due to throttle condition. axi_rdata_en <= '0'; -- Ensure that skid buffer is not getting loaded with -- current read data from BRAM rd_skid_buf_ld_cmb <= '0'; -- BRAM address is NOT getting incremented -- (same for burst counter) bram_addr_inc <= '0'; brst_cnt_dec <= '0'; end if; -- rd_adv_buf (RREADY throttle) ------------------------- LAST_ADDR State ------------------------- when LAST_ADDR => -- Reach this state in the clock cycle following the last address -- presented to the BRAM. Capture the last BRAM data beat in the -- next clock cycle. -- -- Data is presented to AXI bus (if no throttling detected) and -- loaded into the skid buffer. -- If we reach this state after back to back burst transfers -- then clear the flag to ensure that RVALID will clear when RLAST -- is recognized if (axi_b2b_brst = '1') then axi_b2b_brst_cmb <= '0'; end if; -- Clear flag that indicates end of read burst -- Once we reach this state, we have recognized the burst complete. -- -- It is getting asserted too early -- and recognition of the end of the burst is missed when throttling -- on the last two data beats in the read. end_brst_rd_clr_cmb <= '1'; -- Set new flag for pending operation if ar_active is asserted (BRAM -- address has already been loaded) and we are waiting for the current -- read burst to complete. If those two conditions apply, set this flag. -- For dual port, support checking for early writes into BRAM address counter if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then -- Support back-to-backs for single AND dual port modes. -- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then -- if (ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; end if; -- Load read data skid buffer for BRAM is asserted on transition -- into this state. Only gets negated if done with operation -- as detected in below if clause. -- Check flag for no subsequent operations -- Clear that now, with current operation completing if (no_ar_ack = '1') then no_ar_ack_cmb <= '0'; end if; -- Check for single AXI read operations -- If so, wait for RREADY to be asserted -- Check for burst and bursts of two as seperate signals. if (act_rd_burst = '0') and (act_rd_burst_two = '0') then -- Create rvalid_set to only be asserted for a single clock -- cycle. -- Will get set as transitioning to LAST_ADDR on single read operations -- Only assert RVALID here on single operations -- Enable AXI read data register axi_rdata_en <= '1'; -- Data will not yet be acknowledged on AXI -- in this state. -- Go to wait for last data beat rd_data_sm_ns <= LAST_DATA; -- Set read data mux select for SKID BUF rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; else -- Only check throttling on AXI during read data burst operations -- Check AXI throttling condition -- If AXI bus advances and accepts read data, SM can -- proceed with next data beat. -- If not, then go to LAST_THROTTLE state to wait for -- AXI_RREADY = '1'. if (rd_adv_buf = '1') then -- Assert AXI read data enable for BRAM capture -- in next clock cycle -- Enable AXI read data register axi_rdata_en <= '1'; -- Ensure read data mux is set for BRAM data rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM; -- Burst counter already at zero. Reached this state due to NO -- pending ARADDR in the read address pipeline. However, check -- here for any new read addresses. -- New ARADDR detected and loaded into BRAM address counter -- Add check here for previously loaded BRAM address -- ar_active will be asserted (and qualify that with the -- condition that the read burst is complete, for narrow reads). if (bram_addr_ld_en = '1') then -- Initiate BRAM read transfer bram_en_cmb <= '1'; -- Instead of transitioning to SNG_ADDR -- go to wait for last data beat. rd_data_sm_ns <= LAST_DATA_AR_PEND; else -- No pending read address to initiate next read burst -- Go to capture last data beat from BRAM and present on AXI bus. rd_data_sm_ns <= LAST_DATA; end if; -- bram_addr_ld_en (New read burst) else -- Throttling condition detected rd_data_sm_ns <= LAST_THROTTLE; -- Ensure that AXI read data output register is disabled -- due to throttle condition. axi_rdata_en <= '0'; -- Skid buffer gets loaded from BRAM read data in next clock -- cycle ONLY. -- Only on transition to THROTTLE state does skid buffer get loaded. -- Set read data mux select for SKID BUF rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; end if; -- rd_adv_buf (RREADY throttle) end if; -- AXI read burst ------------------------- LAST_THROTTLE State --------------------- when LAST_THROTTLE => -- Reach this state when the AXI bus throttles on the last data -- beat read from BRAM -- Data to be sourced from read skid buffer -- Add check in LAST_THROTTLE as well as LAST_ADDR -- as we may miss the setting of this flag for a subsequent operation. -- For dual port, support checking for early writes into BRAM address counter if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then -- Support back-to-back for single AND dual port modes. -- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then pend_rd_op_cmb <= '1'; end if; -- Wait for RREADY to be asserted w/ RVALID on AXI bus if (rd_adv_buf = '1') then -- Assert AXI read data enable for BRAM capture axi_rdata_en <= '1'; -- Set read data mux select for SKID BUF rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; -- No pending read address to initiate next read burst -- Go to capture last data beat from BRAM and present on AXI bus. rd_data_sm_ns <= LAST_DATA; -- Load read data skid buffer for BRAM capture in next clock cycle -- of last data read -- Read Skid buffer already loaded with last data beat from BRAM -- Does not need to be asserted again in this state else -- Stay in this state -- Ensure that AXI read data output register is disabled axi_rdata_en <= '0'; -- Ensure that skid buffer is not getting loaded with -- current read data from BRAM rd_skid_buf_ld_cmb <= '0'; -- BRAM address is NOT getting incremented -- (same for burst counter) bram_addr_inc <= '0'; brst_cnt_dec <= '0'; -- Keep RVALID asserted on AXI -- No need to assert RVALID again end if; -- rd_adv_buf (RREADY throttle) ------------------------- LAST_DATA State ------------------------- when LAST_DATA => -- Reach this state when last BRAM data beat is -- presented on AXI bus. -- For a read burst, RLAST is not asserted until SM reaches -- this state. -- Ok to accept new operation if throttling detected -- during current operation (and flag was previously set -- to disable the back-to-back performance). disable_b2b_brst_cmb <= '0'; -- Stay in this state until RREADY is asserted on AXI bus -- Indicated by assertion of rd_adv_buf if (rd_adv_buf = '1') then -- Last data beat acknowledged on AXI bus -- Check for new read burst or proceed back to IDLE -- New ARADDR detected and loaded into BRAM address counter -- Note: this condition may occur when C_SINGLE_PORT_BRAM = 0 or 1 if (bram_addr_ld_en = '1') or (pend_rd_op = '1') then -- Clear flag once pending read is recognized if (pend_rd_op = '1') then pend_rd_op_cmb <= '0'; end if; -- Initiate BRAM read transfer bram_en_cmb <= '1'; -- Only count addresses & burst length for read -- burst operations -- Go to SNG_ADDR state rd_data_sm_ns <= SNG_ADDR; -- If current operation was a burst, clear the active -- burst flag if (act_rd_burst = '1') or (act_rd_burst_two = '1') then act_rd_burst_clr <= '1'; end if; -- If we are loading the BRAM, then we have to view the curr_arlen -- signal to determine if the next operation is a single transfer. -- Or if the BRAM address counter is already loaded (and we reach -- this if clause due to pend_rd_op then the axi_* signals will indicate -- if the next operation is a burst or not. -- If the operation is a single transaction, then set the last_bram_addr -- signal when we reach SNG_ADDR. if (bram_addr_ld_en = '1') then if (curr_arlen = AXI_ARLEN_ONE) then -- Set flag for last_bram_addr on transition -- to SNG_ADDR on single operations. set_last_bram_addr <= '1'; end if; elsif (pend_rd_op = '1') then if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then set_last_bram_addr <= '1'; end if; end if; else -- No pending read address to initiate next read burst. -- Go to IDLE rd_data_sm_ns <= IDLE; -- If current operation was a burst, clear the active -- burst flag if (act_rd_burst = '1') or (act_rd_burst_two = '1') then act_rd_burst_clr <= '1'; end if; end if; else -- Throttling condition detected -- Ensure that AXI read data output register is disabled -- due to throttle condition. axi_rdata_en <= '0'; -- If new ARADDR detected and loaded into BRAM address counter if (bram_addr_ld_en = '1') then -- Initiate BRAM read transfer bram_en_cmb <= '1'; -- Only count addresses & burst length for read -- burst operations -- Instead of transitioning to SNG_ADDR -- to wait for last data beat. rd_data_sm_ns <= LAST_DATA_AR_PEND; -- For singles, block any subsequent loads into BRAM address -- counter from AR SM no_ar_ack_cmb <= '1'; end if; end if; -- rd_adv_buf (RREADY throttle) ------------------------ LAST_DATA_AR_PEND -------------------- when LAST_DATA_AR_PEND => -- Ok to accept new operation if throttling detected -- during current operation (and flag was previously set -- to disable the back-to-back performance). disable_b2b_brst_cmb <= '0'; -- Reach this state when new BRAM address is loaded into -- BRAM address counter -- But waiting for last RREADY/RVALID/RLAST to be asserted -- Once this occurs, continue with pending AR operation if (rd_adv_buf = '1') then -- Go to SNG_ADDR state rd_data_sm_ns <= SNG_ADDR; -- If current operation was a burst, clear the active -- burst flag if (act_rd_burst = '1') or (act_rd_burst_two = '1') then act_rd_burst_clr <= '1'; end if; -- In this state, the BRAM address counter is already loaded, -- the axi_rd_burst and axi_rd_burst_two signals will indicate -- if the next operation is a burst or not. -- If the operation is a single transaction, then set the last_bram_addr -- signal when we reach SNG_ADDR. if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then set_last_bram_addr <= '1'; end if; -- Code coverage tests are reporting that reaching this state -- always when axi_rd_burst = '0' and axi_rd_burst_two = '0', -- so no bursting operations. end if; --coverage off ------------------------------ Default ---------------------------- when others => rd_data_sm_ns <= IDLE; --coverage on end case; end process RD_DATA_SM_CMB_PROCESS; --------------------------------------------------------------------------- RD_DATA_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then rd_data_sm_cs <= IDLE; bram_en_int <= '0'; rd_skid_buf_ld_reg <= '0'; rddata_mux_sel <= C_RDDATA_MUX_BRAM; axi_rvalid_set <= '0'; end_brst_rd_clr <= '0'; no_ar_ack <= '0'; pend_rd_op <= '0'; axi_b2b_brst <= '0'; disable_b2b_brst <= '0'; else rd_data_sm_cs <= rd_data_sm_ns; bram_en_int <= bram_en_cmb; rd_skid_buf_ld_reg <= rd_skid_buf_ld_cmb; rddata_mux_sel <= rddata_mux_sel_cmb; axi_rvalid_set <= axi_rvalid_set_cmb; end_brst_rd_clr <= end_brst_rd_clr_cmb; no_ar_ack <= no_ar_ack_cmb; pend_rd_op <= pend_rd_op_cmb; axi_b2b_brst <= axi_b2b_brst_cmb; disable_b2b_brst <= disable_b2b_brst_cmb; end if; end if; end process RD_DATA_SM_REG_PROCESS; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Create seperate registered process for last_bram_addr signal. -- Only asserted for a single clock cycle -- Gets set when the burst counter is loaded with 0's (for a single data beat operation) -- (indicated by set_last_bram_addr from DATA SM) -- or when the burst counter is decrement and the current value = 1 REG_LAST_BRAM_ADDR: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then last_bram_addr <= '0'; -- The signal, set_last_bram_addr, is asserted when the DATA SM transitions to SNG_ADDR -- on a single data beat burst. Can not use condition of loading burst counter -- with the value of 0's (as the burst counter may be loaded during prior single operation -- when waiting on last throttle/data beat, ie. rd_adv_buf not yet asserted). elsif (set_last_bram_addr = '1') or -- On burst operations at the last BRAM address presented to BRAM (brst_cnt_dec = '1' and brst_cnt = C_BRST_CNT_ONE) then last_bram_addr <= '1'; else last_bram_addr <= '0'; end if; end if; end process REG_LAST_BRAM_ADDR; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- *** AXI Read Data Channel Interface *** -- --------------------------------------------------------------------------- rd_skid_buf_ld <= rd_skid_buf_ld_reg or rd_skid_buf_ld_imm; --------------------------------------------------------------------------- -- Generate: GEN_RDATA_NO_ECC -- Purpose: Generation of AXI_RDATA output register without ECC -- logic (C_ECC = 0 parameterization in design) --------------------------------------------------------------------------- GEN_RDATA_NO_ECC: if C_ECC = 0 generate signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); begin --------------------------------------------------------------------------- -- AXI RdData Skid Buffer/Register -- Sized according to size of AXI/BRAM data width --------------------------------------------------------------------------- REG_RD_BUF: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then rd_skid_buf <= (others => '0'); -- Add immediate load of read skid buffer -- Occurs in the case when at full throttle and RREADY/RVALID are asserted elsif (rd_skid_buf_ld = '1') then rd_skid_buf <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0); else rd_skid_buf <= rd_skid_buf; end if; end if; end process REG_RD_BUF; -- Rd Data Mux (selects between skid buffer and BRAM read data) -- Select control signal from SM determines register load value axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else rd_skid_buf; --------------------------------------------------------------------------- -- Generate: GEN_RDATA -- Purpose: Generate each bit of AXI_RDATA. --------------------------------------------------------------------------- GEN_RDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate begin REG_RDATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Clear output after last data beat accepted by requesting AXI master if (S_AXI_AResetn = C_RESET_ACTIVE) or -- Don't clear RDDATA when a back to back burst is occuring on RLAST & RVALID assertion -- For improved code coverage, can remove the signal, axi_rvalid_int from this if clause. -- It will always be asserted in this case. (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then axi_rdata_int (i) <= '0'; elsif (axi_rdata_en = '1') then axi_rdata_int (i) <= axi_rdata_mux (i); else axi_rdata_int (i) <= axi_rdata_int (i); end if; end if; end process REG_RDATA; end generate GEN_RDATA; -- If C_ECC = 0, direct output assignment to AXI_RDATA AXI_RDATA <= axi_rdata_int; end generate GEN_RDATA_NO_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_RDATA_ECC -- Purpose: Generation of AXI_RDATA output register when ECC -- logic is enabled (C_ECC = 1 parameterization in design) --------------------------------------------------------------------------- GEN_RDATA_ECC: if C_ECC = 1 generate subtype syndrome_bits is std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- 0:6 for 32-bit ECC -- 0:7 for 64-bit ECC type correct_data_table_type is array (natural range 0 to C_AXI_DATA_WIDTH-1) of syndrome_bits; signal rd_skid_buf_i : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal axi_rdata_int_corr : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); begin -- Remove GEN_RD_BUF that was doing bit reversal. -- Replace with direct register assignments. Sized according to AXI data width. REG_RD_BUF: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then rd_skid_buf_i <= (others => '0'); -- Add immediate load of read skid buffer -- Occurs in the case when at full throttle and RREADY/RVALID are asserted elsif (rd_skid_buf_ld = '1') then rd_skid_buf_i (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1); else rd_skid_buf_i <= rd_skid_buf_i; end if; end if; end process REG_RD_BUF; -- Rd Data Mux (selects between skid buffer and BRAM read data) -- Select control signal from SM determines register load value -- axi_rdata_mux holds data + ECC bits. -- Previous mux on input to checkbit_handler logic. -- Removed now (mux inserted after checkbit_handler logic before register stage) -- -- axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else -- rd_skid_buf_i; -- Remove GEN_RDATA that was doing bit reversal. REG_RDATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then axi_rdata_int <= (others => '0'); elsif (axi_rdata_en = '1') then -- Track uncorrected data vector with AXI RDATA output pipeline -- Mimic mux logic here (from previous post checkbit XOR logic register) if (rddata_mux_sel = C_RDDATA_MUX_BRAM) then axi_rdata_int (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1); else axi_rdata_int <= rd_skid_buf_i; end if; else axi_rdata_int <= axi_rdata_int; end if; end if; end process REG_RDATA; -- When C_ECC = 1, correct any single bit errors on output read data. -- Post register stage to improve timing on ECC logic data path. -- Use registers in AXI Interconnect IP core. -- Perform bit swapping on output of correct_one_bit -- module (axi_rdata_int_corr signal). -- AXI_RDATA (i) <= axi_rdata_int (i) when (Enable_ECC = '0') -- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i); -- Found in HW debug -- axi_rdata_int is reversed to be returned on AXI bus. -- AXI_RDATA (i) <= axi_rdata_int (C_AXI_DATA_WIDTH-1-i) when (Enable_ECC = '0') -- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i); -- Remove bit reversal on AXI_RDATA output. AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HAMMING_ECC_CORR -- -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Generate statements to correct BRAM read data -- dependent on ECC type. ------------------------------------------------------------------------ GEN_HAMMING_ECC_CORR: if C_ECC_TYPE = 0 generate begin ------------------------------------------------------------------------ -- Generate: CHK_ECC_32 -- Purpose: Check ECC data unique for 32-bit BRAM. ------------------------------------------------------------------------ CHK_ECC_32: if C_AXI_DATA_WIDTH = 32 generate constant correct_data_table_32 : correct_data_table_type := ( 0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001", 4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001", 8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101", 12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101", 16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101", 20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101", 24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011", 28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011" ); signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC begin --------------------------------------------------------------------------- -- Register ECC syndrome value to correct any single bit errors -- post-register on AXI read data. REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then syndrome_reg <= (others => '0'); syndrome_4_reg <= (others => '0'); syndrome_6_reg <= (others => '0'); -- Align register stage of syndrome with AXI read data pipeline elsif (axi_rdata_en = '1') then syndrome_reg <= Syndrome; syndrome_4_reg <= Syndrome_4; syndrome_6_reg <= Syndrome_6; else syndrome_reg <= syndrome_reg; syndrome_4_reg <= syndrome_4_reg; syndrome_6_reg <= syndrome_6_reg; end if; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Do last XOR on specific syndrome bits after pipeline stage before -- correct_one_bit module. syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3); PARITY_CHK4: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2) port map ( InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (4) ); -- [out std_logic] syndrome_reg_i (5) <= syndrome_reg (5); PARITY_CHK6: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (6) ); -- [out std_logic] --------------------------------------------------------------------------- -- Generate: GEN_CORR_32 -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_32: for i in 0 to C_AXI_DATA_WIDTH-1 generate begin ----------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_32 -- Description: Correct output read data based on syndrome vector. -- A single error can be corrected by decoding the -- syndrome value. -- Input signal is declared (N:0). -- Output signal is (N:0). -- In order to reuse correct_one_bit module, -- the single data bit correction is done LSB to MSB -- in generate statement loop. ----------------------------------------------------------------------- CORR_ONE_BIT_32: entity work.correct_one_bit generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table_32 (i)) port map ( DIn => axi_rdata_int (31-i), -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal) Syndrome => syndrome_reg_i, DCorr => axi_rdata_int_corr (31-i)); -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal) end generate GEN_CORR_32; end generate CHK_ECC_32; ------------------------------------------------------------------------ -- Generate: CHK_ECC_64 -- Purpose: Check ECC data unique for 64-bit BRAM. ------------------------------------------------------------------------ CHK_ECC_64: if C_AXI_DATA_WIDTH = 64 generate constant correct_data_table_64 : correct_data_table_type := ( 0 => "11000001", 1 => "10100001", 2 => "01100001", 3 => "11100001", 4 => "10010001", 5 => "01010001", 6 => "11010001", 7 => "00110001", 8 => "10110001", 9 => "01110001", 10 => "11110001", 11 => "10001001", 12 => "01001001", 13 => "11001001", 14 => "00101001", 15 => "10101001", 16 => "01101001", 17 => "11101001", 18 => "00011001", 19 => "10011001", 20 => "01011001", 21 => "11011001", 22 => "00111001", 23 => "10111001", 24 => "01111001", 25 => "11111001", 26 => "10000101", 27 => "01000101", 28 => "11000101", 29 => "00100101", 30 => "10100101", 31 => "01100101", 32 => "11100101", 33 => "00010101", 34 => "10010101", 35 => "01010101", 36 => "11010101", 37 => "00110101", 38 => "10110101", 39 => "01110101", 40 => "11110101", 41 => "00001101", 42 => "10001101", 43 => "01001101", 44 => "11001101", 45 => "00101101", 46 => "10101101", 47 => "01101101", 48 => "11101101", 49 => "00011101", 50 => "10011101", 51 => "01011101", 52 => "11011101", 53 => "00111101", 54 => "10111101", 55 => "01111101", 56 => "11111101", 57 => "10000011", 58 => "01000011", 59 => "11000011", 60 => "00100011", 61 => "10100011", 62 => "01100011", 63 => "11100011" ); signal syndrome_7_reg : std_logic_vector (0 to 11) := (others => '0'); -- Specific for 64-bit ECC signal syndrome_7_a : std_logic; signal syndrome_7_b : std_logic; begin --------------------------------------------------------------------------- -- Register ECC syndrome value to correct any single bit errors -- post-register on AXI read data. REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Align register stage of syndrome with AXI read data pipeline if (axi_rdata_en = '1') then syndrome_reg <= Syndrome; syndrome_7_reg <= Syndrome_7; else syndrome_reg <= syndrome_reg; syndrome_7_reg <= syndrome_7_reg; end if; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Do last XOR on select syndrome bits after pipeline stage -- before correct_one_bit_64 module. PARITY_CHK7_A: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_7_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_7_a ); -- [out std_logic] PARITY_CHK7_B: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_7_reg (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_7_b ); -- [out std_logic] -- Do last XOR on Syndrome MSB after pipeline stage before correct_one_bit module -- PASSES: syndrome_reg_i (7) <= syndrome_reg (7) xor syndrome_7_b_reg; syndrome_reg_i (7) <= syndrome_7_a xor syndrome_7_b; syndrome_reg_i (0 to 6) <= syndrome_reg (0 to 6); --------------------------------------------------------------------------- -- Generate: GEN_CORR_64 -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_64: for i in 0 to C_AXI_DATA_WIDTH-1 generate begin ----------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_64 -- Description: Correct output read data based on syndrome vector. -- A single error can be corrected by decoding the -- syndrome value. ----------------------------------------------------------------------- CORR_ONE_BIT_64: entity work.correct_one_bit_64 generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table_64 (i)) port map ( DIn => axi_rdata_int (i), Syndrome => syndrome_reg_i, DCorr => axi_rdata_int_corr (i)); end generate GEN_CORR_64; end generate CHK_ECC_64; end generate GEN_HAMMING_ECC_CORR; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HSIAO_ECC_CORR -- -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Derived from MIG v3.7 Hsiao HDL. -- Generate statements to correct BRAM read data -- dependent on ECC type. ------------------------------------------------------------------------ GEN_HSIAO_ECC_CORR: if C_ECC_TYPE = 1 generate type type_int0 is array (C_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0); signal h_matrix : type_int0; signal flip_bits : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0); signal ecc_rddata_r : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0); begin -- Reconstruct H-matrix H_COL: for n in 0 to C_AXI_DATA_WIDTH - 1 generate begin H_BIT: for p in 0 to ECC_WIDTH - 1 generate begin h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n); end generate H_BIT; end generate H_COL; -- Based on syndrome value, determine bits to flip in BRAM read data. GEN_FLIP_BIT: for r in 0 to C_AXI_DATA_WIDTH - 1 generate begin flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r); end generate GEN_FLIP_BIT; ecc_rddata_r <= axi_rdata_int; axi_rdata_int_corr (C_AXI_DATA_WIDTH-1 downto 0) <= -- UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) xor ecc_rddata_r (C_AXI_DATA_WIDTH-1 downto 0) xor flip_bits (C_AXI_DATA_WIDTH-1 downto 0); end generate GEN_HSIAO_ECC_CORR; end generate GEN_RDATA_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_RID_SNG -- Purpose: Generate RID output pipeline when the core is configured -- in a single port mode. --------------------------------------------------------------------------- GEN_RID_SNG: if (C_SINGLE_PORT_BRAM = 1) generate begin REG_RID_TEMP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rid_temp <= (others => '0'); elsif (bram_addr_ld_en = '1') then axi_rid_temp <= AXI_ARID; else axi_rid_temp <= axi_rid_temp; end if; end if; end process REG_RID_TEMP; REG_RID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then axi_rid_int <= (others => '0'); elsif (bram_addr_ld_en = '1') then axi_rid_int <= AXI_ARID; elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then axi_rid_int <= axi_rid_temp; else axi_rid_int <= axi_rid_int; end if; end if; end process REG_RID; -- Advance RID pipeline values axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '1') else '0'; end generate GEN_RID_SNG; --------------------------------------------------------------------------- -- Generate: GEN_RID -- Purpose: Generate RID in dual port mode (with read address pipeline). --------------------------------------------------------------------------- GEN_RID: if (C_SINGLE_PORT_BRAM = 0) generate begin --------------------------------------------------------------------------- -- RID Output Register -- -- Output RID value either comes from pipelined value or directly wrapped -- ARID value. Determined by address pipeline usage. --------------------------------------------------------------------------- -- Create intermediate temporary RID output register REG_RID_TEMP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rid_temp <= (others => '0'); -- When BRAM address counter gets loaded -- Set output RID value based on address source elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '0') then -- If BRAM address counter gets loaded directly from -- AXI bus, then save ARID value for wrapping to RID if (araddr_pipe_sel = '0') then axi_rid_temp <= AXI_ARID; else -- Use pipelined AWID value axi_rid_temp <= axi_arid_pipe; end if; -- Add condition to check for temp utilized (temp_full now = '0'), but a -- pending RID is stored in temp2. Must advance the pipeline. elsif ((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or (axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then axi_rid_temp <= axi_rid_temp2; else axi_rid_temp <= axi_rid_temp; end if; end if; end process REG_RID_TEMP; -- Create flag that indicates if axi_rid_temp is full REG_RID_TEMP_FULL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rid_temp_full = '1' and (axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and axi_rid_temp2_full = '0') then axi_rid_temp_full <= '0'; elsif (bram_addr_ld_en = '1') or ((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or (axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then axi_rid_temp_full <= '1'; else axi_rid_temp_full <= axi_rid_temp_full; end if; end if; end process REG_RID_TEMP_FULL; -- Create flag to detect falling edge of axi_rid_temp_full flag REG_RID_TEMP_FULL_D1: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rid_temp_full_d1 <= '0'; else axi_rid_temp_full_d1 <= axi_rid_temp_full; end if; end if; end process REG_RID_TEMP_FULL_D1; axi_rid_temp_full_fe <= '1' when (axi_rid_temp_full = '0' and axi_rid_temp_full_d1 = '1') else '0'; --------------------------------------------------------------------------- -- Create intermediate temporary RID output register REG_RID_TEMP2: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rid_temp2 <= (others => '0'); -- When BRAM address counter gets loaded -- Set output RID value based on address source elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then -- If BRAM address counter gets loaded directly from -- AXI bus, then save ARID value for wrapping to RID if (araddr_pipe_sel = '0') then axi_rid_temp2 <= AXI_ARID; else -- Use pipelined AWID value axi_rid_temp2 <= axi_arid_pipe; end if; else axi_rid_temp2 <= axi_rid_temp2; end if; end if; end process REG_RID_TEMP2; -- Create flag that indicates if axi_rid_temp2 is full REG_RID_TEMP2_FULL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rid_temp2_full = '1' and (axi_rvalid_set = '1' or axi_b2b_rid_adv = '1')) or (axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then axi_rid_temp2_full <= '0'; elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then axi_rid_temp2_full <= '1'; else axi_rid_temp2_full <= axi_rid_temp2_full; end if; end if; end process REG_RID_TEMP2_FULL; --------------------------------------------------------------------------- -- Output RID register is enabeld when RVALID is asserted on the AXI bus -- Clear RID when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. REG_RID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- For improved code coverage, can remove the signal, axi_rvalid_int from statement. (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then axi_rid_int <= (others => '0'); -- Add back to back case to advance RID elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then axi_rid_int <= axi_rid_temp; else axi_rid_int <= axi_rid_int; end if; end if; end process REG_RID; -- Advance RID pipeline values axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '1') else '0'; end generate GEN_RID; --------------------------------------------------------------------------- -- Generate: GEN_RRESP -- Purpose: Create register output unique when ECC is disabled. -- Only possible output value = OKAY response. --------------------------------------------------------------------------- GEN_RRESP: if C_ECC = 0 generate begin ----------------------------------------------------------------------- -- AXI_RRESP Output Register -- -- Set when RVALID is asserted on AXI bus. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking -- sequence and recognized by AXI requesting master. ----------------------------------------------------------------------- REG_RRESP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted. (axi_rlast_int = '1' and AXI_RREADY = '1') then axi_rresp_int <= (others => '0'); elsif (axi_rvalid_set = '1') then -- AXI BRAM only supports OK response for normal operations -- Exclusive operations not yet supported axi_rresp_int <= RESP_OKAY; else axi_rresp_int <= axi_rresp_int; end if; end if; end process REG_RRESP; end generate GEN_RRESP; --------------------------------------------------------------------------- -- Generate: GEN_RRESP_ECC -- Purpose: Create register output unique when ECC is disabled. -- Only possible output value = OKAY response. --------------------------------------------------------------------------- GEN_RRESP_ECC: if C_ECC = 1 generate begin ----------------------------------------------------------------------- -- AXI_RRESP Output Register -- -- Set when RVALID is asserted on AXI bus. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking -- sequence and recognized by AXI requesting master. ----------------------------------------------------------------------- REG_RRESP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted. (axi_rlast_int = '1' and AXI_RREADY = '1') then axi_rresp_int <= (others => '0'); elsif (axi_rvalid_set = '1') then -- AXI BRAM only supports OK response for normal operations -- Exclusive operations not yet supported -- For ECC implementation -- Check that an uncorrectable error has not occured. -- If so, then respond with RESP_SLVERR on AXI. -- Ok to use combinatorial signal here. The Sl_UE_i -- flag is generated based on the registered syndrome value. -- if (Sl_UE_i = '1') then -- axi_rresp_int <= RESP_SLVERR; -- else axi_rresp_int <= RESP_OKAY; -- end if; else axi_rresp_int <= axi_rresp_int; end if; end if; end process REG_RRESP; end generate GEN_RRESP_ECC; --------------------------------------------------------------------------- -- AXI_RVALID Output Register -- -- Set AXI_RVALID when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- Clear AXI_RVALID at the end of tranfer when able to clear -- (axi_rlast_int = '1' and axi_rvalid_int = '1' and AXI_RREADY = '1' and -- For improved code coverage, remove signal axi_rvalid_int. (axi_rlast_int = '1' and AXI_RREADY = '1' and -- Added axi_rvalid_clr_ok to check if during a back-to-back burst -- and the back-to-back is elgible for streaming performance axi_rvalid_clr_ok = '1') then axi_rvalid_int <= '0'; elsif (axi_rvalid_set = '1') then axi_rvalid_int <= '1'; else axi_rvalid_int <= axi_rvalid_int; end if; end if; end process REG_RVALID; -- Create flag that gets set when we load BRAM address early in a B2B scenario -- This will prevent the RVALID from getting cleared at the end of the current burst -- Otherwise, the RVALID gets cleared after RLAST/RREADY dual assertion REG_RVALID_CLR: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rvalid_clr_ok <= '0'; -- When the new address loaded into the BRAM counter is for a back-to-back operation -- Do not clear the RVALID elsif (rd_b2b_elgible = '1' and bram_addr_ld_en = '1') then axi_rvalid_clr_ok <= '0'; -- Else when we start a new transaction (that is not back-to-back) -- Then enable the RVALID to get cleared upon RLAST/RREADY elsif (bram_addr_ld_en = '1') or (axi_rvalid_clr_ok = '0' and (disable_b2b_brst = '1' or disable_b2b_brst_cmb = '1') and last_bram_addr = '1') or -- Add check for current SM state -- If LAST_ADDR state reached, no longer performing back-to-back -- transfers and keeping data streaming on AXI bus. (rd_data_sm_cs = LAST_ADDR) then axi_rvalid_clr_ok <= '1'; else axi_rvalid_clr_ok <= axi_rvalid_clr_ok; end if; end if; end process REG_RVALID_CLR; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- AXI_RLAST Output Register -- -- Set AXI_RLAST when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RLAST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- To improve code coverage, remove -- use of axi_rvalid_int (it will always be asserted with RLAST). if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_rlast_set = '0') then axi_rlast_int <= '0'; elsif (axi_rlast_set = '1') then axi_rlast_int <= '1'; else axi_rlast_int <= axi_rlast_int; end if; end if; end process REG_RLAST; --------------------------------------------------------------------------- -- Generate complete flag do_cmplt_burst_cmb <= '1' when (last_bram_addr = '1' and axi_rd_burst = '1' and axi_rd_burst_two = '0') else '0'; -- Register complete flags REG_CMPLT_BURST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (do_cmplt_burst_clr = '1') then do_cmplt_burst <= '0'; elsif (do_cmplt_burst_cmb = '1') then do_cmplt_burst <= '1'; else do_cmplt_burst <= do_cmplt_burst; end if; end if; end process REG_CMPLT_BURST; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- RLAST State Machine -- -- Description: SM to generate axi_rlast_set signal. -- Created based on IR # 555346 to track when RLAST needs -- to be asserted for back to back transfers -- Uses the indication when last BRAM address is presented -- and then counts the handshaking cycles on the AXI bus -- (RVALID and RREADY both asserted). -- Uses rd_adv_buf to perform this operation. -- -- Output: Name Type -- axi_rlast_set Not Registered -- do_cmplt_burst_clr Not Registered -- -- -- RLAST_SM_CMB_PROCESS: Combinational process to determine next state. -- RLAST_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- RLAST_SM_CMB_PROCESS: process ( do_cmplt_burst, last_bram_addr, rd_adv_buf, act_rd_burst, axi_rd_burst, act_rd_burst_two, axi_rd_burst_two, axi_rlast_int, rlast_sm_cs ) begin -- assign default values for state machine outputs rlast_sm_ns <= rlast_sm_cs; axi_rlast_set <= '0'; do_cmplt_burst_clr <= '0'; case rlast_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- If last read address is presented to BRAM if (last_bram_addr = '1') then -- If the operation is a single read operation if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then -- Go to wait for last data beat rlast_sm_ns <= W8_LAST_DATA; -- Else the transaction is a burst else -- Throttle condition on 3rd to last data beat if (rd_adv_buf = '0') then -- If AXI read burst = 2 (only two data beats to capture) if (axi_rd_burst_two = '1' or act_rd_burst_two = '1') then rlast_sm_ns <= W8_THROTTLE_B2; else rlast_sm_ns <= W8_THROTTLE; end if; -- No throttle on 3rd to last data beat else -- Only back-to-back support when burst size is greater -- than two data beats. We will never toggle on a burst > 2 -- when last_bram_addr is asserted (as this is no toggle -- condition) -- Go to wait for 2nd to last data beat rlast_sm_ns <= W8_2ND_LAST_DATA; do_cmplt_burst_clr <= '1'; end if; end if; end if; ------------------------- W8_THROTTLE State ----------------------- when W8_THROTTLE => if (rd_adv_buf = '1') then -- Go to wait for 2nd to last data beat rlast_sm_ns <= W8_2ND_LAST_DATA; -- If do_cmplt_burst flag is set, then clear it if (do_cmplt_burst = '1') then do_cmplt_burst_clr <= '1'; end if; end if; ---------------------- W8_2ND_LAST_DATA State --------------------- when W8_2ND_LAST_DATA => if (rd_adv_buf = '1') then -- Assert RLAST on AXI axi_rlast_set <= '1'; rlast_sm_ns <= W8_LAST_DATA; end if; ------------------------- W8_LAST_DATA State ---------------------- when W8_LAST_DATA => -- If pending single to complete, keep RLAST asserted -- Added to only assert axi_rlast_set for a single clock cycle -- when we enter this state and are here waiting for the -- throttle on the AXI bus. if (axi_rlast_int = '1') then axi_rlast_set <= '0'; else axi_rlast_set <= '1'; end if; -- Wait for last data beat to transition back to IDLE if (rd_adv_buf = '1') then rlast_sm_ns <= IDLE; end if; -------------------------- W8_THROTTLE_B2 ------------------------ when W8_THROTTLE_B2 => -- Wait for last data beat to transition back to IDLE -- and set RLAST if (rd_adv_buf = '1') then rlast_sm_ns <= IDLE; axi_rlast_set <= '1'; end if; --coverage off ------------------------------ Default ---------------------------- when others => rlast_sm_ns <= IDLE; --coverage on end case; end process RLAST_SM_CMB_PROCESS; --------------------------------------------------------------------------- RLAST_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then rlast_sm_cs <= IDLE; else rlast_sm_cs <= rlast_sm_ns; end if; end if; end process RLAST_SM_REG_PROCESS; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- *** ECC Logic *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_ECC -- Purpose: Generate BRAM ECC write data and check ECC on read operations. -- Create signals to update ECC registers (lite_ecc_reg module interface). -- --------------------------------------------------------------------------- GEN_ECC: if C_ECC = 1 generate signal bram_din_a_i : std_logic_vector(0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width signal CE_Q : std_logic := '0'; signal Sl_CE_i : std_logic := '0'; signal bram_en_int_d1 : std_logic := '0'; signal bram_en_int_d2 : std_logic := '0'; begin -- Generate signal to advance BRAM read address pipeline to -- capture address for ECC error conditions (in lite_ecc_reg module). -- BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or -- ((bram_en_int or bram_en_int_reg) and not (axi_rd_burst) and not (axi_rd_burst_two)); BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or rd_adv_buf or ((bram_en_int or bram_en_int_d1 or bram_en_int_d2) and not (axi_rd_burst) and not (axi_rd_burst_two)); -- Enable 2nd & 3rd pipeline stage for BRAM address storage with single read transfers. BRAM_EN_REG: process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then bram_en_int_d1 <= bram_en_int; bram_en_int_d2 <= bram_en_int_d1; end if; end process BRAM_EN_REG; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HAMMING_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. ------------------------------------------------------------------------ GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate begin ------------------------------------------------------------------------ -- Generate: GEN_ECC_32 -- Purpose: Check ECC data unique for 32-bit BRAM. -- Add extra '0' at MSB of ECC vector for data2mem alignment -- w/ 32-bit BRAM data widths. -- ECC bits are in upper order bits. ------------------------------------------------------------------------ GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate signal bram_din_a_rev : std_logic_vector(31 downto 0) := (others => '0'); -- Specific to BRAM data width signal bram_din_ecc_a_rev : std_logic_vector(6 downto 0) := (others => '0'); -- Specific to BRAM data width begin --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_32 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) --------------------------------------------------------------------------- -- process (bram_din_a_i) begin -- for k in 0 to 31 loop -- bram_din_a_rev(k) <= bram_din_a_i(39-k); -- end loop; -- for k in 0 to 6 loop -- bram_din_ecc_a_rev(0) <= bram_din_a_i(6-k); -- end loop; -- end process; CHK_HANDLER_32: entity work.checkbit_handler generic map ( C_ENCODE => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( -- In 32-bit BRAM use case: DataIn (8:39) -- CheckIn (1:7) DataIn => bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH), -- [in std_logic_vector(0 to 31)] CheckIn => bram_din_a_i(1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(0 to 6)] --DataIn => bram_din_a_rev, -- [in std_logic_vector(0 to 31)] --CheckIn => bram_din_ecc_a_rev, -- [in std_logic_vector(0 to 6)] CheckOut => open, -- [out std_logic_vector(0 to 6)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)] Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)] Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)] Syndrome_Chk => syndrome_reg_i, -- [out std_logic_vector(0 to 6)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] -- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate -- of AXI RDATA output register logic. end generate GEN_ECC_32; ------------------------------------------------------------------------ -- Generate: GEN_ECC_64 -- Purpose: Check ECC data unique for 64-bit BRAM. -- No extra '0' at MSB of ECC vector for data2mem alignment -- w/ 64-bit BRAM data widths. -- ECC bits are in upper order bits. ------------------------------------------------------------------------ GEN_ECC_64: if C_AXI_DATA_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_64 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) --------------------------------------------------------------------------- CHK_HANDLER_64: entity work.checkbit_handler_64 generic map ( C_ENCODE => false, -- [boolean] C_REG => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( Clk => S_AXI_AClk, -- [in std_logic] -- In 64-bit BRAM use case: DataIn (8:71) -- CheckIn (0:7) DataIn => bram_din_a_i (C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1), -- [in std_logic_vector(0 to 63)] CheckIn => bram_din_a_i (0 to C_INT_ECC_WIDTH-1), -- [in std_logic_vector(0 to 7)] CheckOut => open, -- [out std_logic_vector(0 to 7)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 7)] Syndrome_7 => Syndrome_7, Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 7)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] -- GEN_CORR_64 generate & correct_one_bit instantiation moved to generate -- of AXI RDATA output register logic. end generate GEN_ECC_64; end generate GEN_HAMMING_ECC; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HSIAO_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Derived from MIG v3.7 Hsiao HDL. ------------------------------------------------------------------------ GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; signal syndrome_ns : std_logic_vector (ECC_WIDTH - 1 downto 0) := (others => '0'); begin -- Generate ECC check bits and syndrome values based on -- BRAM read data. -- Generate appropriate single or double bit error flags. -- Instantiate ecc_gen_hsiao module, generated from MIG I_ECC_GEN_HSIAO: entity work.ecc_gen generic map ( code_width => CODE_WIDTH, ecc_width => ECC_WIDTH, data_width => C_AXI_DATA_WIDTH ) port map ( -- Output h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0) ); GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate begin syndrome_ns (m) <= REDUCTION_XOR ( -- bram_din_a_i (0 to CODE_WIDTH-1) BRAM_RdData (CODE_WIDTH-1 downto 0) and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH))); end generate GEN_RD_ECC; -- Insert register stage for syndrome. -- Same as Hamming ECC code. Syndrome value is registered. REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_r <= syndrome_ns; end if; end process REG_SYNDROME; Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not(REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); end generate GEN_HSIAO_ECC; -- Capture correctable/uncorrectable error from BRAM read CORR_REG: process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (Enable_ECC = '1') and (axi_rvalid_int = '1' and AXI_RREADY = '1') then -- Capture error flags CE_Q <= Sl_CE_i; UE_Q <= Sl_UE_i; else CE_Q <= '0'; UE_Q <= '0'; end if; end if; end process CORR_REG; -- The signal, axi_rdata_en loads the syndrome_reg. -- Use the AXI RVALID/READY signals to capture state of UE and CE. -- Since flag generation uses the registered syndrome value. -- ECC register block gets registered UE or CE conditions to update -- ECC registers/interrupt/flag outputs. Sl_CE <= CE_Q; Sl_UE <= UE_Q; -- CE_Failing_We <= Sl_CE_i and Enable_ECC and axi_rvalid_set; CE_Failing_We <= CE_Q; --------------------------------------------------------------------------- -- Generate BRAM read data vector assignment to always be from Port A -- in a single port BRAM configuration. -- Map BRAM_RdData (Port A) (N:0) to bram_din_a_i (0:N) -- Including read back ECC bits. -- -- Port A or Port B sourcing done at full_axi module level --------------------------------------------------------------------------- -- Original design with mux (BRAM vs. Skid Buffer) on input side of checkbit_handler logic. -- Move mux to enable on AXI RDATA register. bram_din_a_i (0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- Map data vector from BRAM to use in correct_one_bit module with -- register syndrome (post AXI RDATA register). UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_AXI_DATA_WIDTH-1); end generate GEN_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Drive default output signals when ECC is diabled. --------------------------------------------------------------------------- GEN_NO_ECC: if C_ECC = 0 generate begin BRAM_Addr_En <= '0'; CE_Failing_We <= '0'; Sl_CE <= '0'; Sl_UE <= '0'; end generate GEN_NO_ECC; --------------------------------------------------------------------------- -- -- *** BRAM Interface Signals *** -- --------------------------------------------------------------------------- BRAM_En <= bram_en_int; --------------------------------------------------------------------------- -- BRAM Address Generate --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_L_BRAM_ADDR -- Purpose: Generate zeros on lower order address bits adjustable -- based on BRAM data width. -- --------------------------------------------------------------------------- GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin BRAM_Addr (i) <= '0'; end generate GEN_L_BRAM_ADDR; --------------------------------------------------------------------------- -- -- Generate: GEN_BRAM_ADDR -- Purpose: Assign BRAM address output from address counter. -- --------------------------------------------------------------------------- GEN_BRAM_ADDR: for i in C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin BRAM_Addr (i) <= bram_addr_int (i); end generate GEN_BRAM_ADDR; --------------------------------------------------------------------------- end architecture implementation;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/zpu/vhdl_source/zpu_8bit_ok.vhd

5

28212

------------------------------------------------------------------------------ ---- ---- ---- ZPU 8-bit version ---- ---- ---- ---- http://www.opencores.org/ ---- ---- ---- ---- Description: ---- ---- ZPU is a 32 bits small stack cpu. This is a modified version of ---- ---- the zpu_small implementation. This one has a third (8-bit) port for ---- ---- fetching instructions. This modification reduces the LUT size by ---- ---- approximately 10% and increases the performance with 21%. ---- ---- Needs external dual ported memory, plus single cycle external ---- ---- program memory. It also requires a different linker script to ---- ---- place the text segment on a logically different address to stick to ---- ---- the single-, flat memory model programming paradigm. ---- ---- ---- ---- To Do: ---- ---- Add a 'ready' for the external code memory ---- ---- More thorough testing, cleanup code a bit more ---- ---- ---- ---- Author: ---- ---- - Øyvind Harboe, oyvind.harboe zylin.com ---- ---- - Salvador E. Tropea, salvador inti.gob.ar ---- ---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ---- ---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- ---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- ---- ---- ---- Distributed under the BSD license ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Design unit: zpu_8bit(Behave) (Entity and architecture) ---- ---- File name: zpu_8bit.vhdl ---- ---- Note: None ---- ---- Limitations: None known ---- ---- Errors: None known ---- ---- Library: work ---- ---- Dependencies: ieee.std_logic_1164 ---- ---- ieee.numeric_std ---- ---- work.zpupkg ---- ---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ---- ---- Language: VHDL ---- ---- Wishbone: No ---- ---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ---- ---- Simulation tools: Modelsim ---- ---- Text editor: UltraEdit 11.00a+ ---- ---- ---- ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.zpupkg.all; entity zpu_8bit is generic( g_addr_size : integer := 16; -- Total address space width (incl. I/O) g_stack_size : integer := 12; -- Memory (stack+data) width g_prog_size : integer := 14; -- Program size g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0' port( clk_i : in std_logic; -- System Clock reset_i : in std_logic; -- Synchronous Reset interrupt_i : in std_logic; -- Interrupt break_o : out std_logic; -- Breakpoint opcode executed -- synthesis translate_off dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) -- synthesis translate_on -- BRAM (stack ONLY) a_en_o : out std_logic; a_we_o : out std_logic; -- BRAM A port Write Enable a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port a_i : in unsigned(31 downto 0); -- Data from BRAM A port b_en_o : out std_logic; b_we_o : out std_logic; -- BRAM B port Write Enable b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port b_i : in unsigned(31 downto 0); -- Data from BRAM B port -- memory port for text, bss, data c_i : in unsigned(c_opcode_width-1 downto 0); c_valid_i : in std_logic; c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0'); c_o : out unsigned(c_opcode_width-1 downto 0); c_en_o : out std_logic; c_we_o : out std_logic ); end entity zpu_8bit; architecture Behave of zpu_8bit is constant c_max_addr_bit : integer:=g_addr_size-1; -- Stack Pointer initial value: BRAM size-8 constant SP_START_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size); constant SP_START : unsigned(g_stack_size-1 downto 2):= SP_START_1(g_stack_size-1 downto 2); -- constant IO_BIT : integer:=g_addr_size-1; -- Address bit to determine this is an I/O -- Program counter signal pc_r : unsigned(c_max_addr_bit downto 0):=(others => '0'); -- Stack pointer signal sp_r : unsigned(g_stack_size-1 downto 2):=SP_START; signal idim_r : std_logic:='0'; -- BRAM (text, some data, bss and stack) -- a_r is a register for the top of the stack [SP] -- Note: as this is a stack CPU this is a very important register. signal a_we_r : std_logic:='0'; signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0'); signal a_r : unsigned(31 downto 0):=(others => '0'); -- b_r is a register for the next value in the stack [SP+1] signal b_we_r : std_logic:='0'; signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0'); signal b_r : unsigned(31 downto 0):=(others => '0'); signal c_we_r : std_logic := '0'; signal c_en_r : std_logic := '0'; signal c_mux_r : std_logic := '0'; signal c_mux_d : std_logic := '0'; signal first : std_logic := '0'; signal byte_cnt : unsigned(1 downto 0) := "00"; signal byte_cnt_d : unsigned(1 downto 0) := "00"; signal posted_wr_a : std_logic := '0'; -- State machine. type state_t is (st_fetch, st_execute, st_add, st_or, st_and, st_store, st_read_mem, st_write_mem, st_add_sp, st_decode, st_resync); signal state : state_t:=st_resync; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "one-hot"; -- Decoded Opcode type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp, dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add, dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store, dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb); signal dec_valid : std_logic; signal d_opcode_r : decode_t; signal d_opcode : decode_t; signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered -- IRQ flag signal in_irq_r : std_logic:='0'; -- I/O space address signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0'); begin a_en_o <= '1'; b_en_o <= '1'; c_en_o <= '1' when state = st_fetch else c_en_r; -- Dual ported memory interface a_we_o <= a_we_r; a_addr_o <= a_addr_r(g_stack_size-1 downto 2); a_o <= a_r; b_we_o <= b_we_r; b_addr_o <= b_addr_r(g_stack_size-1 downto 2); b_o <= b_r; opcode <= c_i; c_addr_o <= resize(pc_r(g_prog_size-1 downto 0), g_addr_size) when c_mux_r = '0' else addr_r; c_we_o <= c_we_r; ------------------------- -- Instruction Decoder -- ------------------------- -- Note: We use a separate memory port to fetch opcodes. decode_control: process(opcode) begin if (opcode(7 downto 7)=OPCODE_IM) then d_opcode <= dec_im; elsif (opcode(7 downto 5)=OPCODE_STORESP) then d_opcode <= dec_store_sp; elsif (opcode(7 downto 5)=OPCODE_LOADSP) then d_opcode <= dec_load_sp; elsif (opcode(7 downto 5)=OPCODE_EMULATE) then -- if opcode(5 downto 0) = OPCODE_LOADB then -- d_opcode <= dec_loadb; -- elsif opcode(5 downto 0) = OPCODE_STOREB then -- d_opcode <= dec_storeb; -- else d_opcode <= dec_emulate; -- end if; elsif (opcode(7 downto 4)=OPCODE_ADDSP) then d_opcode <= dec_add_sp; else -- OPCODE_SHORT case opcode(3 downto 0) is when OPCODE_BREAK => d_opcode <= dec_break; when OPCODE_PUSHSP => d_opcode <= dec_push_sp; when OPCODE_POPPC => d_opcode <= dec_pop_pc; when OPCODE_ADD => d_opcode <= dec_add; when OPCODE_OR => d_opcode <= dec_or; when OPCODE_AND => d_opcode <= dec_and; when OPCODE_LOAD => d_opcode <= dec_load; when OPCODE_NOT => d_opcode <= dec_not; when OPCODE_FLIP => d_opcode <= dec_flip; when OPCODE_STORE => d_opcode <= dec_store; when OPCODE_POPSP => d_opcode <= dec_pop_sp; when others => -- OPCODE_NOP and others d_opcode <= dec_nop; end case; end if; end process decode_control; opcode_control: process (clk_i) variable sp_offset : unsigned(4 downto 0); begin if rising_edge(clk_i) then break_o <= '0'; -- synthesis translate_off dbg_o.b_inst <= '0'; -- synthesis translate_on posted_wr_a <= '0'; c_we_r <= '0'; byte_cnt_d <= byte_cnt; c_mux_d <= c_mux_r; d_opcode_r <= d_opcode; dec_valid <= not c_mux_d and c_valid_i; opcode_r <= opcode; a_we_r <= '0'; b_we_r <= '0'; -- a_r <= (others => g_dont_care); b_r <= (others => g_dont_care); sp_offset:=(others => g_dont_care); a_addr_r <= (others => g_dont_care); -- b_addr_r <= (others => g_dont_care); -- addr_r <= a_i(g_addr_size-1 downto 0); if interrupt_i='0' then in_irq_r <= '0'; -- no longer in an interrupt end if; case state is when st_execute => if dec_valid = '1' then state <= st_fetch; -- At this point: -- b_i contains opcode word -- a_i contains top of stack pc_r <= pc_r+1; -- synthesis translate_off -- Debug info (Trace) dbg_o.b_inst <= '1'; dbg_o.pc <= (others => '0'); dbg_o.pc(g_addr_size-1 downto 0) <= pc_r; dbg_o.opcode <= opcode_r; dbg_o.sp <= (others => '0'); dbg_o.sp(g_stack_size-1 downto 2) <= sp_r; dbg_o.stk_a <= a_i; dbg_o.stk_b <= b_i; -- synthesis translate_on -- During the next cycle we'll be reading the next opcode sp_offset(4):=not opcode_r(4); sp_offset(3 downto 0):=opcode_r(3 downto 0); idim_r <= '0'; -------------------- -- Execution Unit -- -------------------- case d_opcode_r is when dec_interrupt => -- Not a real instruction, but an interrupt -- Push(PC); PC=32 sp_r <= sp_r-1; a_addr_r <= sp_r-1; a_we_r <= '1'; a_r <= (others => g_dont_care); a_r(c_max_addr_bit downto 0) <= pc_r; -- Jump to ISR pc_r <= to_unsigned(32, c_max_addr_bit+1); -- interrupt address --report "ZPU jumped to interrupt!" severity note; when dec_im => idim_r <= '1'; a_we_r <= '1'; if idim_r='0' then -- First IM -- Push the 7 bits (extending the sign) sp_r <= sp_r-1; a_addr_r <= sp_r-1; a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32)); else -- Next IMs, shift the word and put the new value in the lower -- bits a_addr_r <= sp_r; a_r(31 downto 7) <= a_i(24 downto 0); a_r(6 downto 0) <= opcode_r(6 downto 0); end if; when dec_store_sp => -- [SP+Offset]=Pop() b_we_r <= '1'; b_addr_r <= sp_r+sp_offset; b_r <= a_i; sp_r <= sp_r+1; state <= st_resync; when dec_load_sp => -- Push([SP+Offset]) sp_r <= sp_r-1; a_addr_r <= sp_r+sp_offset; posted_wr_a <= '1'; state <= st_resync; when dec_emulate => -- Push(PC+1), PC=Opcode[4:0]*32 sp_r <= sp_r-1; a_we_r <= '1'; a_addr_r <= sp_r-1; a_r <= (others => g_dont_care); a_r(c_max_addr_bit downto 0) <= pc_r+1; -- Jump to NUM*32 -- The emulate address is: -- 98 7654 3210 -- 0000 00aa aaa0 0000 pc_r <= (others => '0'); pc_r(9 downto 5) <= opcode_r(4 downto 0); when dec_add_sp => -- Push(Pop()+[SP+Offset]) a_addr_r <= sp_r; b_addr_r <= sp_r+sp_offset; state <= st_add_sp; when dec_break => --report "Break instruction encountered" severity failure; break_o <= '1'; when dec_push_sp => -- Push(SP) sp_r <= sp_r-1; a_we_r <= '1'; a_addr_r <= sp_r-1; a_r <= (others => '0'); a_r(sp_r'range) <= sp_r; a_r(31) <= '1'; -- DEBUG when dec_pop_pc => -- Pop(PC) pc_r <= a_i(pc_r'range); sp_r <= sp_r+1; state <= st_resync; when dec_add => -- Push(Pop()+Pop()) sp_r <= sp_r+1; state <= st_add; when dec_or => -- Push(Pop() or Pop()) sp_r <= sp_r+1; state <= st_or; when dec_and => -- Push(Pop() and Pop()) sp_r <= sp_r+1; state <= st_and; -- when dec_loadb => -- addr_r <= a_i(g_addr_size-1 downto 0); -- -- assert a_i(31)='0' -- report "LoadB only works from external memory!" -- severity error; -- -- c_en_r <= '1'; -- c_mux_r <= '1'; -- byte_cnt <= "00"; -- 1 byte -- byte_cnt_d <= "11"; -- state <= st_read_mem; when dec_load => -- Push([Pop()]) addr_r <= a_i(g_addr_size-1 downto 0); if a_i(31)='1' then -- stack a_addr_r <= a_i(a_addr_r'range); posted_wr_a <= '1'; state <= st_resync; else c_en_r <= '1'; c_mux_r <= '1'; state <= st_read_mem; byte_cnt <= "11"; -- 4 bytes byte_cnt_d <= "11"; end if; when dec_not => -- Push(not(Pop())) a_addr_r <= sp_r; a_we_r <= '1'; a_r <= not a_i; when dec_flip => -- Push(flip(Pop())) a_addr_r <= sp_r; a_we_r <= '1'; for i in 0 to 31 loop a_r(i) <= a_i(31-i); end loop; when dec_store => -- a=Pop(), b=Pop(), [a]=b sp_r <= sp_r+1; b_addr_r <= sp_r+1; -- added from store/io_store if a_i(31) = '1' then state <= st_store; b_addr_r <= sp_r+1; else state <= st_write_mem; byte_cnt <= "11"; -- 4 bytes first <= '1'; c_mux_r <= '1'; end if; when dec_pop_sp => -- SP=Pop() sp_r <= a_i(g_stack_size-1 downto 2); state <= st_resync; when dec_nop => -- Default, keep addressing to of the stack (A) a_addr_r <= sp_r; when others => null; end case; end if; -- decode valid when st_store => sp_r <= sp_r+1; a_we_r <= '1'; a_addr_r <= a_i(g_stack_size-1 downto 2); a_r <= b_i; state <= st_resync; when st_read_mem => -- BIG ENDIAN if c_valid_i = '1' then case byte_cnt_d is when "00" => a_r(7 downto 0) <= c_i; when "01" => a_r(15 downto 8) <= c_i; when "10" => a_r(23 downto 16) <= c_i; when others => -- 11 a_r(31 downto 24) <= c_i; end case; addr_r(1 downto 0) <= addr_r(1 downto 0) + 1; byte_cnt <= byte_cnt - 1; if byte_cnt_d = "00" then a_addr_r <= sp_r; a_we_r <= '1'; state <= st_fetch; end if; if byte_cnt = "00" then c_mux_r <= '0'; c_en_r <= '0'; end if; end if; when st_write_mem => case byte_cnt is when "00" => c_o <= b_i(7 downto 0); when "01" => c_o <= b_i(15 downto 8); when "10" => c_o <= b_i(23 downto 16); when others => -- 11 c_o <= b_i(31 downto 24); end case; if first='1' then first <= '0'; addr_r <= a_i(g_addr_size-1 downto 0); else addr_r(1 downto 0) <= addr_r(1 downto 0) + 1; end if; c_en_r <= '1'; c_we_r <= '1'; byte_cnt <= byte_cnt - 1; if byte_cnt = "00" then sp_r <= sp_r+1; state <= st_resync; end if; when st_fetch => -- We need to resync. During this cycle -- we'll fetch the opcode @ pc and thus it will -- be available for st_execute in the next cycle -- At this point a_i contains the value that is from the top of the stack -- or that was fetched from the stack with an offset (loadsp) a_we_r <= posted_wr_a; a_r <= a_i; a_addr_r <= sp_r; b_addr_r <= sp_r+1; state <= st_decode; when st_decode => if interrupt_i='1' and in_irq_r='0' and idim_r='0' then -- We got an interrupt, execute interrupt instead of next instruction in_irq_r <= '1'; d_opcode_r <= dec_interrupt; end if; -- during the st_execute cycle we'll be fetching SP+1 a_addr_r <= sp_r; b_addr_r <= sp_r+1; state <= st_execute; when st_add_sp => state <= st_add; when st_add => a_addr_r <= sp_r; a_we_r <= '1'; a_r <= a_i+b_i; state <= st_fetch; when st_or => a_addr_r <= sp_r; a_we_r <= '1'; a_r <= a_i or b_i; state <= st_fetch; when st_and => a_addr_r <= sp_r; a_we_r <= '1'; a_r <= a_i and b_i; state <= st_fetch; when st_resync => c_en_r <= '0'; c_mux_r <= '0'; a_addr_r <= sp_r; state <= st_fetch; posted_wr_a <= posted_wr_a; -- keep when others => null; end case; if reset_i='1' then state <= st_resync; sp_r <= SP_START; pc_r <= (others => '0'); idim_r <= '0'; in_irq_r <= '0'; c_mux_r <= '0'; first <= '0'; end if; end if; -- rising_edge(clk_i) end process opcode_control; end architecture Behave; -- Entity: zpu_8bit

gpl-3.0

Netzpfuscher/stmbl

hw/kicad/bob/firmware/PIN_stmbl_bob_001_34.vhd

2

9826

library IEEE; use IEEE.std_logic_1164.all; -- defines std_logic types use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics -- http://www.mesanet.com -- -- This program is is licensed under a disjunctive dual license giving you -- the choice of one of the two following sets of free software/open source -- licensing terms: -- -- * GNU General Public License (GPL), version 2.0 or later -- * 3-clause BSD License -- -- -- The GNU GPL License: -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -- -- -- The 3-clause BSD License: -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- * Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- * Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- * Neither the name of Mesa Electronics nor the names of its -- contributors may be used to endorse or promote products -- derived from this software without specific prior written -- permission. -- -- -- Disclaimer: -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- use work.IDROMConst.all; package PIN_stmbl_bob_001_34 is constant ModuleID : ModuleIDType :=( (WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask), (IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask), (SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask), (LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000") ); constant PinDesc : PinDescType :=( -- Base func sec unit sec func sec pin external DB25 IOPortTag & x"00" & NullTag & x"00", -- I/O 00 PIN 1 LED IOPortTag & x"00" & NullTag & x"00", -- I/O 01 PIN 14 in0 IOPortTag & x"00" & NullTag & x"00", -- I/O 02 PIN 2 out0 IOPortTag & x"00" & NullTag & x"00", -- I/O 03 PIN 15 in1 IOPortTag & x"00" & NullTag & x"00", -- I/O 04 PIN 3 out1 IOPortTag & x"00" & NullTag & x"00", -- I/O 05 PIN 16 in2 IOPortTag & x"00" & NullTag & x"00", -- I/O 06 PIN 4 out2 IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, -- I/O 07 PIN 17 5. port(top right) IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, -- I/O 08 PIN 5 IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 09 PIN 6 4. port IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 10 PIN 7 IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 11 PIN 8 3. port IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 12 PIN 9 IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 13 PIN 10 2. port IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 14 PIN 11 IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 15 PIN 12 1. port(top left) IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 16 PIN 13 -- 26 HDR IDC DB25 IOPortTag & x"00" & NullTag & x"00", -- I/O 17 PIN 1 PIN 1 IOPortTag & x"00" & NullTag & x"00", -- I/O 18 PIN 2 PIN 14 IOPortTag & x"00" & NullTag & x"00", -- I/O 19 PIN 3 PIN 2 IOPortTag & x"00" & NullTag & x"00", -- I/O 20 PIN 4 PIN 15 IOPortTag & x"00" & NullTag & x"00", -- I/O 21 PIN 5 PIN 3 IOPortTag & x"00" & NullTag & x"00", -- I/O 22 PIN 6 PIN 16 IOPortTag & x"00" & NullTag & x"00", -- I/O 23 PIN 7 PIN 4 IOPortTag & x"00" & NullTag & x"00", -- I/O 24 PIN 8 PIN 17 IOPortTag & x"00" & NullTag & x"00", -- I/O 25 PIN 9 PIN 5 IOPortTag & x"00" & NullTag & x"00", -- I/O 26 PIN 11 PIN 6 IOPortTag & x"00" & NullTag & x"00", -- I/O 27 PIN 13 PIN 7 IOPortTag & x"00" & NullTag & x"00", -- I/O 28 PIN 15 PIN 8 IOPortTag & x"00" & NullTag & x"00", -- I/O 29 PIN 17 PIN 9 IOPortTag & x"00" & NullTag & x"00", -- I/O 30 PIN 19 PIN 10 IOPortTag & x"00" & NullTag & x"00", -- I/O 31 PIN 21 PIN 11 IOPortTag & x"00" & NullTag & x"00", -- I/O 32 PIN 23 PIN 12 IOPortTag & x"00" & NullTag & x"00", -- I/O 33 PIN 25 PIN 13 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin); end package PIN_stmbl_bob_001_34;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/sid6581/vhdl_source/sid_regs.vhd

4

11455

------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 Gideon's Logic Architectures' -- ------------------------------------------------------------------------------- -- -- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) -- -- Note that this file is copyrighted, and is not supposed to be used in other -- projects without written permission from the author. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity sid_regs is port ( clock : in std_logic; reset : in std_logic; addr : in unsigned(7 downto 0); wren : in std_logic; wdata : in std_logic_vector(7 downto 0); rdata : out std_logic_vector(7 downto 0); --- comb_wave_l : in std_logic; comb_wave_r : in std_logic; --- voice_osc : in unsigned(3 downto 0); voice_wave : in unsigned(3 downto 0); voice_adsr : in unsigned(3 downto 0); voice_mul : in unsigned(3 downto 0); -- Oscillator parameters freq : out unsigned(15 downto 0); test : out std_logic; sync : out std_logic; -- Wave map parameters comb_mode : out std_logic; ring_mod : out std_logic; wave_sel : out std_logic_vector(3 downto 0); sq_width : out unsigned(11 downto 0); -- ADSR parameters gate : out std_logic; attack : out std_logic_vector(3 downto 0); decay : out std_logic_vector(3 downto 0); sustain : out std_logic_vector(3 downto 0); release : out std_logic_vector(3 downto 0); -- mixer 1 parameters filter_en : out std_logic; -- globals volume_l : out unsigned(3 downto 0) := (others => '0'); filter_co_l : out unsigned(10 downto 0) := (others => '0'); filter_res_l : out unsigned(3 downto 0) := (others => '0'); filter_ex_l : out std_logic := '0'; filter_hp_l : out std_logic := '0'; filter_bp_l : out std_logic := '0'; filter_lp_l : out std_logic := '0'; voice3_off_l : out std_logic := '0'; volume_r : out unsigned(3 downto 0) := (others => '0'); filter_co_r : out unsigned(10 downto 0) := (others => '0'); filter_res_r : out unsigned(3 downto 0) := (others => '0'); filter_ex_r : out std_logic := '0'; filter_hp_r : out std_logic := '0'; filter_bp_r : out std_logic := '0'; filter_lp_r : out std_logic := '0'; voice3_off_r : out std_logic := '0'; -- readback osc3 : in std_logic_vector(7 downto 0); env3 : in std_logic_vector(7 downto 0) ); attribute keep_hierarchy : string; attribute keep_hierarchy of sid_regs : entity is "yes"; end sid_regs; architecture gideon of sid_regs is type byte_array_t is array(natural range <>) of std_logic_vector(7 downto 0); type nibble_array_t is array(natural range <>) of std_logic_vector(3 downto 0); signal freq_lo : byte_array_t(0 to 15) := (others => (others => '0')); signal freq_hi : byte_array_t(0 to 15) := (others => (others => '0')); signal phase_lo : byte_array_t(0 to 15) := (others => (others => '0')); signal phase_hi : nibble_array_t(0 to 15):= (others => (others => '0')); signal control : byte_array_t(0 to 15) := (others => (others => '0')); signal att_dec : byte_array_t(0 to 15) := (others => (others => '0')); signal sust_rel : byte_array_t(0 to 15) := (others => (others => '0')); signal do_write : std_logic; signal wdata_d : std_logic_vector(7 downto 0); signal filt_en_i: std_logic_vector(15 downto 0) := (others => '0'); constant address_remap : byte_array_t(0 to 255) := ( X"00", X"01", X"02", X"03", X"04", X"05", X"06", -- 00 Voice 1 X"10", X"11", X"12", X"13", X"14", X"15", X"16", -- 07 Voice 2 X"20", X"21", X"22", X"23", X"24", X"25", X"26", -- 0E Voice 3 X"08", X"09", X"0A", X"0B", -- 15 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 19 X"30", X"31", X"32", X"33", X"34", X"35", X"36", -- 20 Voice 4 X"40", X"41", X"42", X"43", X"44", X"45", X"46", -- 27 Voice 5 X"50", X"51", X"52", X"53", X"54", X"55", X"56", -- 2E Voice 6 X"60", X"61", X"62", X"63", X"64", X"65", X"66", -- 35 Voice 7 X"70", X"71", X"72", X"73", X"74", X"75", X"76", -- 3C Voice 8 X"0C", X"0D", X"0E", -- 43 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 46 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 4D X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 54 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 5B X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 62 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 69 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 70 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 77 X"FF", X"FF", -- 7E X"80", X"81", X"82", X"83", X"84", X"85", X"86", -- 80 Voice 9 X"90", X"91", X"92", X"93", X"94", X"95", X"96", -- 87 Voice 10 X"A0", X"A1", X"A2", X"A3", X"A4", X"A5", X"A6", -- 8E Voice 11 X"88", X"89", X"8A", X"8B", -- 95 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 99 X"B0", X"B1", X"B2", X"B3", X"B4", X"B5", X"B6", -- A0 Voice 12 X"C0", X"C1", X"C2", X"C3", X"C4", X"C5", X"C6", -- A7 Voice 13 X"D0", X"D1", X"D2", X"D3", X"D4", X"D5", X"D6", -- AE Voice 14 X"E0", X"E1", X"E2", X"E3", X"E4", X"E5", X"E6", -- B5 Voice 15 X"F0", X"F1", X"F2", X"F3", X"F4", X"F5", X"F6", -- BC Voice 16 X"8C", X"8D", X"8E", -- C3 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- C6 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- CD X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- D4 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- DB X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E2 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E9 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F0 X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F7 X"FF", X"FF" ); -- FE signal address : unsigned(7 downto 0); begin process(clock) begin if rising_edge(clock) then address <= unsigned(address_remap(to_integer(addr))); do_write <= wren; wdata_d <= wdata; if do_write='1' then if address(3)='0' then -- Voice register case address(2 downto 0) is when "000" => freq_lo(to_integer(address(7 downto 4))) <= wdata_d; when "001" => freq_hi(to_integer(address(7 downto 4))) <= wdata_d; when "010" => phase_lo(to_integer(address(7 downto 4))) <= wdata_d; when "011" => phase_hi(to_integer(address(7 downto 4))) <= wdata_d(3 downto 0); when "100" => control(to_integer(address(7 downto 4))) <= wdata_d; when "101" => att_dec(to_integer(address(7 downto 4))) <= wdata_d; when "110" => sust_rel(to_integer(address(7 downto 4))) <= wdata_d; when others => null; end case; elsif address(7)='0' then -- Global register for left case address(2 downto 0) is when "000" => filter_co_l(2 downto 0) <= unsigned(wdata_d(2 downto 0)); when "001" => filter_co_l(10 downto 3) <= unsigned(wdata_d); when "010" => filter_res_l <= unsigned(wdata_d(7 downto 4)); filter_ex_l <= wdata_d(3); filt_en_i(2 downto 0) <= wdata_d(2 downto 0); when "011" => voice3_off_l <= wdata_d(7); filter_hp_l <= wdata_d(6); filter_bp_l <= wdata_d(5); filter_lp_l <= wdata_d(4); volume_l <= unsigned(wdata_d(3 downto 0)); when "100" => filt_en_i(7 downto 0) <= wdata_d; when others => null; end case; else -- Global register for right case address(2 downto 0) is when "000" => filter_co_r(2 downto 0) <= unsigned(wdata_d(2 downto 0)); when "001" => filter_co_r(10 downto 3) <= unsigned(wdata_d); when "010" => filter_res_r <= unsigned(wdata_d(7 downto 4)); filter_ex_r <= wdata_d(3); filt_en_i(10 downto 8) <= wdata_d(2 downto 0); when "011" => voice3_off_r <= wdata_d(7); filter_hp_r <= wdata_d(6); filter_bp_r <= wdata_d(5); filter_lp_r <= wdata_d(4); volume_r <= unsigned(wdata_d(3 downto 0)); when "100" => filt_en_i(15 downto 8) <= wdata_d; when others => null; end case; end if; end if; -- Readback (unmapped address) case addr is when "00011011" => rdata <= osc3; when "00011100" => rdata <= env3; when others => rdata <= (others => '0'); end case; if reset='1' then filt_en_i <= (others => '0'); voice3_off_l <= '0'; voice3_off_r <= '0'; volume_l <= X"0"; volume_r <= X"0"; end if; end if; end process; freq <= unsigned(freq_hi(to_integer(voice_osc))) & unsigned(freq_lo(to_integer(voice_osc))); test <= control(to_integer(voice_osc))(3); sync <= control(to_integer(voice_osc))(1); -- Wave map parameters ring_mod <= control(to_integer(voice_wave))(2); wave_sel <= control(to_integer(voice_wave))(7 downto 4); sq_width <= unsigned(phase_hi(to_integer(voice_wave))) & unsigned(phase_lo(to_integer(voice_wave))); comb_mode <= (voice_wave(3) and comb_wave_r) or (not voice_wave(3) and comb_wave_l); -- ADSR parameters gate <= control(to_integer(voice_adsr))(0); attack <= att_dec(to_integer(voice_adsr))(7 downto 4); decay <= att_dec(to_integer(voice_adsr))(3 downto 0); sustain <= sust_rel(to_integer(voice_adsr))(7 downto 4); release <= sust_rel(to_integer(voice_adsr))(3 downto 0); -- Mixer 1 parameters filter_en <= filt_en_i(to_integer(voice_mul)); end gideon;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v4b.vhd

3

12673

------------------------------------------------------------------------------- -- Title : External Memory controller for SDRAM (burst capable) ------------------------------------------------------------------------------- -- Description: This module implements a simple, single access memory controller. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; library work; use work.mem_bus_pkg.all; entity ext_mem_ctrl_v4b is generic ( g_simulation : boolean := false; A_Width : integer := 15; SDRAM_WakeupTime : integer := 40; -- refresh periods SDRAM_Refr_period : integer := 375 ); port ( clock : in std_logic := '0'; clk_shifted : in std_logic := '0'; reset : in std_logic := '0'; inhibit : in std_logic; is_idle : out std_logic; req : in t_mem_req; resp : out t_mem_resp; SDRAM_CLK : out std_logic; SDRAM_CKE : out std_logic; SDRAM_CSn : out std_logic := '1'; SDRAM_RASn : out std_logic := '1'; SDRAM_CASn : out std_logic := '1'; SDRAM_WEn : out std_logic := '1'; SDRAM_DQM : out std_logic := '0'; MEM_A : out std_logic_vector(A_Width-1 downto 0); MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z')); end ext_mem_ctrl_v4b; -- ADDR: 25 24 23 ... -- 0 X X ... SDRAM (32MB) architecture Gideon of ext_mem_ctrl_v4b is -- SRCW constant c_cmd_inactive : std_logic_vector(3 downto 0) := "1111"; constant c_cmd_nop : std_logic_vector(3 downto 0) := "0111"; constant c_cmd_active : std_logic_vector(3 downto 0) := "0011"; constant c_cmd_read : std_logic_vector(3 downto 0) := "0101"; constant c_cmd_write : std_logic_vector(3 downto 0) := "0100"; constant c_cmd_bterm : std_logic_vector(3 downto 0) := "0110"; constant c_cmd_precharge : std_logic_vector(3 downto 0) := "0010"; constant c_cmd_refresh : std_logic_vector(3 downto 0) := "0001"; constant c_cmd_mode_reg : std_logic_vector(3 downto 0) := "0000"; type t_init is record addr : std_logic_vector(15 downto 0); cmd : std_logic_vector(3 downto 0); end record; type t_init_array is array(natural range <>) of t_init; constant c_init_array : t_init_array(0 to 7) := ( ( X"0400", c_cmd_precharge ), ( X"0222", c_cmd_mode_reg ), -- mode register, burstlen=4, writelen=1, CAS lat = 2 ( X"0000", c_cmd_refresh ), ( X"0000", c_cmd_refresh ), ( X"0000", c_cmd_refresh ), ( X"0000", c_cmd_refresh ), ( X"0000", c_cmd_refresh ), ( X"0000", c_cmd_refresh ) ); type t_state is (boot, init, idle, sd_read, read_single, read_single_end, sd_write, wait_for_precharge, delay_to_terminate); signal state : t_state; signal sdram_cmd : std_logic_vector(3 downto 0) := "1111"; signal sdram_d_o : std_logic_vector(MEM_D'range) := (others => '1'); signal sdram_d_t : std_logic := '0'; signal delay : integer range 0 to 15; signal inhibit_d : std_logic; signal rwn_i : std_logic; signal tag : std_logic_vector(req.tag'range); signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0'); signal col_addr : std_logic_vector(9 downto 0) := (others => '0'); signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1; signal do_refresh : std_logic := '0'; signal refresh_inhibit: std_logic := '0'; signal not_clock : std_logic; signal reg_out : integer range 0 to 3 := 0; signal rdata_i : std_logic_vector(7 downto 0) := (others => '0'); signal dout_sel : std_logic := '0'; signal refr_delay : integer range 0 to 3; signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1; signal init_cnt : integer range 0 to c_init_array'high; signal enable_sdram : std_logic := '1'; signal req_i : std_logic; signal dack_count : unsigned(1 downto 0) := "00"; signal count_out : unsigned(1 downto 0) := "00"; signal dack : std_logic := '0'; signal dack_pre : std_logic := '0'; signal rack : std_logic := '0'; signal dack_tag_pre : std_logic_vector(req.tag'range) := (others => '0'); signal rack_tag : std_logic_vector(req.tag'range) := (others => '0'); signal dack_tag : std_logic_vector(req.tag'range) := (others => '0'); -- attribute fsm_encoding : string; -- attribute fsm_encoding of state : signal is "sequential"; -- attribute register_duplication : string; -- attribute register_duplication of mem_a_i : signal is "no"; attribute iob : string; attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB attribute iob of sdram_cmd : signal is "true"; attribute iob of mem_a_i : signal is "true"; attribute iob of SDRAM_CKE : signal is "false"; begin is_idle <= '1' when state = idle else '0'; req_i <= req.request; resp.data <= rdata_i; resp.rack <= rack; resp.rack_tag <= rack_tag; resp.dack_tag <= dack_tag; resp.count <= count_out; process(clock) procedure send_refresh_cmd is begin do_refresh <= '0'; sdram_cmd <= c_cmd_refresh; refr_delay <= 3; end procedure; procedure accept_req is begin rack <= '1'; rack_tag <= req.tag; tag <= req.tag; rwn_i <= req.read_writen; dack_count <= req.size; sdram_d_o <= req.data; mem_a_i(12 downto 0) <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits mem_a_i(14 downto 13) <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits sdram_cmd <= c_cmd_active; end procedure; begin if rising_edge(clock) then rack <= '0'; rack_tag <= (others => '0'); dack_pre <= '0'; dack_tag_pre <= (others => '0'); dack <= dack_pre; dack_tag <= dack_tag_pre; if dack='1' then count_out <= count_out + 1; else count_out <= "00"; end if; dout_sel <= '0'; inhibit_d <= inhibit; rdata_i <= MEM_D; -- clock in sdram_cmd <= c_cmd_inactive; SDRAM_CKE <= enable_sdram; sdram_d_t <= '0'; if refr_delay /= 0 then refr_delay <= refr_delay - 1; end if; if delay /= 0 then delay <= delay - 1; end if; if inhibit='1' then refresh_inhibit <= '1'; end if; case state is when boot => refresh_inhibit <= '0'; enable_sdram <= '1'; if refresh_cnt = 0 then boot_cnt <= boot_cnt - 1; if boot_cnt = 1 then state <= init; end if; elsif g_simulation then state <= idle; end if; when init => mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range); sdram_cmd(3) <= '1'; sdram_cmd(2 downto 0) <= c_init_array(init_cnt).cmd(2 downto 0); if delay = 0 then delay <= 7; sdram_cmd(3) <= '0'; if init_cnt = c_init_array'high then state <= idle; else init_cnt <= init_cnt + 1; end if; end if; when idle => -- first cycle after inhibit goes 1, should not be a refresh -- this enables putting cartridge images in sdram, because we guarantee the first access after inhibit to be a cart cycle if do_refresh='1' and refresh_inhibit='0' then send_refresh_cmd; elsif inhibit='0' then -- make sure we are allowed to start a new cycle if req_i='1' and refr_delay = 0 then accept_req; refresh_inhibit <= '0'; if req.read_writen = '1' then state <= sd_read; else state <= sd_write; end if; end if; end if; when sd_read => mem_a_i(10) <= '0'; -- no auto precharge mem_a_i(9 downto 0) <= col_addr; sdram_cmd <= c_cmd_read; if dack_count = "00" then state <= read_single; else state <= delay_to_terminate; end if; when read_single => dack_pre <= '1'; dack_tag_pre <= tag; sdram_cmd <= c_cmd_bterm; state <= read_single_end; when read_single_end => sdram_cmd <= c_cmd_precharge; state <= idle; when delay_to_terminate => dack_pre <= '1'; dack_tag_pre <= tag; dack_count <= dack_count - 1; delay <= 2; if dack_count = "00" then sdram_cmd <= c_cmd_precharge; state <= idle; end if; when sd_write => if delay = 0 then mem_a_i(10) <= '1'; -- auto precharge mem_a_i(9 downto 0) <= col_addr; sdram_cmd <= c_cmd_write; sdram_d_t <= '1'; delay <= 2; state <= wait_for_precharge; end if; when wait_for_precharge => if delay = 0 then state <= idle; end if; when others => null; end case; if refresh_cnt = SDRAM_Refr_period-1 then do_refresh <= '1'; refresh_cnt <= 0; else refresh_cnt <= refresh_cnt + 1; end if; if reset='1' then state <= boot; sdram_d_t <= '0'; delay <= 0; tag <= (others => '0'); do_refresh <= '0'; boot_cnt <= SDRAM_WakeupTime-1; init_cnt <= 0; enable_sdram <= '1'; refresh_inhibit <= '0'; end if; end if; end process; MEM_D <= sdram_d_o when sdram_d_t='1' else (others => 'Z'); MEM_A <= mem_a_i; SDRAM_CSn <= sdram_cmd(3); SDRAM_RASn <= sdram_cmd(2); SDRAM_CASn <= sdram_cmd(1); SDRAM_WEn <= sdram_cmd(0); not_clock <= not clk_shifted; clkout: FDDRRSE port map ( CE => '1', C0 => clk_shifted, C1 => not_clock, D0 => '0', D1 => enable_sdram, Q => SDRAM_CLK, R => '0', S => '0' ); end Gideon; -- ACT to READ: tRCD = 20 ns ( = 1 CLK) -- ACT to PRCH: tRAS = 44 ns ( = 3 CLKs) -- ACT to ACT: tRC = 66 ns ( = 4 CLKs) -- ACT to ACTb: tRRD = 15 ns ( = 1 CLK) -- PRCH time; tRP = 20 ns ( = 1 CLK) -- wr. recov. tWR=8ns+1clk ( = 2 CLKs) (starting from last data word) -- CL=2 -- 0 1 2 3 4 5 6 7 8 9 -- BL1 A R P + -- - - - D -- +: ONLY if same bank, otherwise we don't meet tRC. -- BL2 A R - P -- - - - D D -- BL3 A R - - P -- - - - D D D -- BL4 A r - - - p -- - - - D D D D -- BL1W A(W)= = p -- - D - - - -- BL4 A r - - - p - A -- - - - D D D D -- BL1W A(W)= = p -- - D - - -

gpl-3.0

davidhorrocks/1541UltimateII

fpga/ip/busses/vhdl_bfm/dma_bus_slave_bfm.vhd

5

1680

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.dma_bus_pkg.all; use work.tl_flat_memory_model_pkg.all; entity dma_bus_slave_bfm is generic ( g_name : string; g_latency : positive := 2 ); port ( clock : in std_logic; req : in t_dma_req; resp : out t_dma_resp ); end dma_bus_slave_bfm; architecture bfm of dma_bus_slave_bfm is shared variable mem : h_mem_object; signal bound : boolean := false; signal pipe : t_dma_req_array(0 to g_latency-1) := (others => c_dma_req_init); signal resp_i : t_dma_resp; begin -- this process registers this instance of the bfm to the server package bind: process begin register_mem_model(dma_bus_slave_bfm'path_name, g_name, mem); bound <= true; wait; end process; resp <= resp_i; process(clock) begin if rising_edge(clock) then pipe(0 to g_latency-2) <= pipe(1 to g_latency-1); pipe(g_latency-1) <= req; if resp_i.rack='1' then pipe(g_latency-1).request <= '0'; end if; resp_i.data <= (others => '0'); resp_i.dack <= '0'; resp_i.rack <= '0'; if bound then resp_i.rack <= req.request and not resp_i.rack; if pipe(0).request='1' then if pipe(0).read_writen='1' then resp_i.data <= read_memory_8(mem, X"0000" & std_logic_vector(pipe(0).address)); resp_i.dack <= '1'; else write_memory_8(mem, X"0000" & std_logic_vector(pipe(0).address), pipe(0).data); end if; end if; end if; end if; end process; end bfm;

gpl-3.0

davidhorrocks/1541UltimateII

target/simulation/packages/vhdl_source/tl_math_pkg.vhd

5

12297

------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 - Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : Miscelaneous mathematic operations ------------------------------------------------------------------------------- -- Description: This file contains math functions ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package tl_math_pkg is --------------------------------------------------------------------------- -- increment/decrement functions --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- wrapping decrement/increment --------------------------------------------------------------------------- -- Description: These functions give an increment/decrement that wraps when -- the maximal vector range is reached. --------------------------------------------------------------------------- function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector; function incr(old_value: unsigned; increment: natural := 1) return unsigned; function incr(old_value: signed; increment: natural := 1) return signed; function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector; function decr(old_value: unsigned; decrement: natural := 1) return unsigned; function decr(old_value: signed; decrement: natural := 1) return signed; --------------------------------------------------------------------------- -- clipping decrement/increment --------------------------------------------------------------------------- -- Description: These functions give an increment/decrement that clips when -- the maximal vector range is reached. --------------------------------------------------------------------------- function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector; function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned; function incr_clip(old_value: signed; increment: natural := 1) return signed; function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector; function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned; function decr_clip(old_value: signed; decrement: natural := 1) return signed; --------------------------------------------------------------------------- -- log functions --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- log2 --------------------------------------------------------------------------- -- Description: This functions returns the log2 value of a number. The -- result is in the natural range and rounded depended on the -- selected mode. -- NOTE: use an argument of type unsigned when using this function for -- synthesis --------------------------------------------------------------------------- type log2mode is (ceil, floor); function log2(arg: integer) return natural; function log2(arg: integer; mode: log2mode) return natural; function log2_floor(arg: integer) return natural; function log2_ceil(arg: integer) return natural; function log2(arg: unsigned) return natural; function log2(arg: unsigned; mode: log2mode) return natural; function log2_floor(arg: unsigned) return natural; function log2_ceil(arg: unsigned) return natural; --------------------------------------------------------------------------- -- min/max --------------------------------------------------------------------------- -- Description: These functions return the minimum/maximum of two values --------------------------------------------------------------------------- function max(a, b: integer) return integer; function max(a, b: unsigned) return unsigned; function min(a, b: integer) return integer; function min(a, b: unsigned) return unsigned; end tl_math_pkg; library work; use work.tl_vector_pkg.all; package body tl_math_pkg is --------------------------------------------------------------------------- -- increment/decrement functions --------------------------------------------------------------------------- function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is begin return std_logic_vector(incr(unsigned(old_value), increment)); end function; function incr(old_value: unsigned; increment: natural := 1) return unsigned is variable v_result : unsigned(old_value'range); begin v_result := (old_value + increment) mod 2**old_value'length; return v_result; end function; function incr(old_value: signed; increment: natural := 1) return signed is begin return signed(incr(unsigned(old_value), increment)); end function; function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is begin return std_logic_vector(decr(unsigned(old_value), decrement)); end function; function decr(old_value: unsigned; decrement: natural := 1) return unsigned is constant c_norm_decrement : integer := decrement mod 2**old_value'length; variable v_result : unsigned(old_value'range); begin v_result := (2**old_value'length + (old_value - c_norm_decrement)) mod 2**old_value'length; return v_result; end function; function decr(old_value: signed; decrement: natural := 1) return signed is begin return signed(decr(unsigned(old_value), decrement)); end function; --------------------------------------------------------------------------- -- clipping decrement/increment --------------------------------------------------------------------------- -- Description: These functions give an increment/decrement that clips when -- the maximal vector range is reached. --------------------------------------------------------------------------- function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is begin return std_logic_vector(incr_clip(unsigned(old_value), increment)); end function; function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned is constant c_max_value : unsigned(old_value'range) := (others => '1'); variable v_result : unsigned(old_value'range); begin assert increment < 2**old_value'length report "ERROR: Increment value is larger than vector range" severity error; if old_value <= (c_max_value - increment) then v_result := old_value + increment; else v_result := c_max_value; end if; return v_result; end function; function incr_clip(old_value: signed; increment: natural := 1) return signed is variable c_max_value : signed(old_value'range) := to_signed(2**old_value'length / 2 - 1, old_value'length); variable v_result : signed(old_value'range); begin if old_value <= (c_max_value - increment) then v_result := old_value + increment; else v_result := c_max_value; end if; return v_result; end function; function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is begin return std_logic_vector(decr_clip(unsigned(old_value), decrement)); end function; function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned is constant c_min_value : unsigned(old_value'range) := (others => '0'); variable v_result : unsigned(old_value'range); begin if old_value >= (c_min_value + decrement) then v_result := old_value - decrement; else v_result := c_min_value; end if; return v_result; end function; function decr_clip(old_value: signed; decrement: natural := 1) return signed is constant c_min_value : signed(old_value'range) := to_signed(2**old_value'length / 2, old_value'length); variable v_result : signed(old_value'range); begin if old_value >= (c_min_value + decrement) then v_result := old_value - decrement; else v_result := c_min_value; end if; return v_result; end function; --------------------------------------------------------------------------- -- log functions --------------------------------------------------------------------------- function log2(arg: integer) return natural is begin return log2_ceil(arg); end function; function log2(arg: integer; mode: log2mode) return natural is begin if mode = floor then return log2_floor(arg); else return log2_ceil(arg); end if; end; function log2_ceil(arg: integer) return natural is variable v_temp : integer; variable v_result : natural; begin v_result := log2_floor(arg); if 2**v_result < arg then return v_result + 1; else return v_result; end if; end function; function log2_floor(arg: integer) return natural is variable v_temp : integer; variable v_result : natural; begin v_result := 0; v_temp := arg / 2; while v_temp /= 0 loop v_temp := v_temp / 2; v_result := v_result + 1; end loop; return v_result; end function; function log2(arg: unsigned) return natural is begin return log2_ceil(arg); end function; function log2(arg: unsigned; mode: log2mode) return natural is begin if mode = ceil then return log2_ceil(arg); else return log2_floor(arg); end if; end function; function log2_floor(arg: unsigned) return natural is alias w : unsigned(arg'length - 1 downto 0) is arg; begin return highest_bit(w); end function; function log2_ceil(arg: unsigned) return natural is alias w : unsigned(arg'length - 1 downto 0) is arg; begin if ones(arg) > 1 then return highest_bit(w) + 1; else return highest_bit(w); end if; end function; --------------------------------------------------------------------------- -- min/max --------------------------------------------------------------------------- -- Description: These functions return the minimum/maximum of two values --------------------------------------------------------------------------- function max(a, b: integer) return integer is begin if a > b then return a; else return b; end if; end function; function max(a, b: unsigned) return unsigned is begin if a > b then return a; else return b; end if; end function; function min(a, b: integer) return integer is begin if a < b then return a; else return b; end if; end function; function min(a, b: unsigned) return unsigned is begin if a < b then return a; else return b; end if; end function; end tl_math_pkg;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/ip/nano_cpu/vhdl_sim/nano_tb.vhd

5

807

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nano_tb is end entity; architecture tb of nano_tb is signal clock : std_logic := '0'; signal reset : std_logic; signal io_addr : unsigned(7 downto 0); signal io_write : std_logic; signal io_wdata : std_logic_vector(15 downto 0); signal io_rdata : std_logic_vector(15 downto 0); begin clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; i_cpu: entity work.nano port map ( clock => clock, reset => reset, -- i/o interface io_addr => io_addr, io_write => io_write, io_wdata => io_wdata, io_rdata => io_rdata ); end architecture;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/1541/vhdl_sim/tb_hardware_gcr.vhd

5

3010

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity tb_hardware_gcr is end tb_hardware_gcr; architecture tb of tb_hardware_gcr is signal clock : std_logic := '0'; signal reset : std_logic; signal cpu_clock_en: std_logic := '1'; signal cpu_addr : std_logic_vector(2 downto 0) := "000"; signal cpu_access : std_logic := '0'; signal cpu_write : std_logic := '0'; signal cpu_wdata : std_logic_vector(7 downto 0) := X"00"; signal cpu_rdata : std_logic_vector(7 downto 0) := X"00"; signal busy : std_logic; signal mem_req : std_logic; signal mem_ack : std_logic := '1'; signal mem_addr : std_logic_vector(23 downto 0); signal mem_rwn : std_logic; signal mem_wdata : std_logic_vector(7 downto 0); signal mem_rdata : std_logic_vector(7 downto 0) := X"00"; begin clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; hw: entity work.hardware_gcr port map ( clock => clock, reset => reset, cpu_clock_en => cpu_clock_en, cpu_addr => cpu_addr, cpu_access => cpu_access, cpu_write => cpu_write, cpu_wdata => cpu_wdata, cpu_rdata => cpu_rdata, busy => busy, --- mem_req => mem_req, mem_ack => mem_ack, mem_addr => mem_addr, mem_rwn => mem_rwn, mem_wdata => mem_wdata, mem_rdata => mem_rdata ); process procedure do_write(a: std_logic_vector(2 downto 0); d: std_logic_vector(7 downto 0)) is begin wait until clock='1'; cpu_access <= '1'; cpu_write <= '1'; cpu_addr <= a; cpu_wdata <= d; wait until clock='1'; cpu_access <= '0'; cpu_write <= '0'; for i in 0 to 9 loop wait until clock='1'; end loop; end procedure do_write; begin wait until reset='0'; do_write("000", X"56"); do_write("001", X"34"); do_write("010", X"12"); do_write("100", X"47"); do_write("100", X"47"); do_write("100", X"47"); do_write("100", X"47"); do_write("101", X"00"); do_write("101", X"00"); do_write("101", X"00"); do_write("101", X"00"); do_write("101", X"00"); do_write("101", X"00"); do_write("101", X"00"); do_write("100", X"47"); do_write("100", X"47"); do_write("100", X"47"); do_write("100", X"47"); wait; end process; end tb;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/ip/memory/vhdl_source/spram.vhd

5

1660

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity spram is generic ( g_width_bits : positive := 16; g_depth_bits : positive := 9; g_read_first : boolean := false; g_storage : string := "auto" -- can also be "block" or "distributed" ); port ( clock : in std_logic; address : in unsigned(g_depth_bits-1 downto 0); rdata : out std_logic_vector(g_width_bits-1 downto 0); wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); en : in std_logic := '1'; we : in std_logic ); attribute keep_hierarchy : string; attribute keep_hierarchy of spram : entity is "yes"; end entity; architecture xilinx of spram is type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0); shared variable ram : t_ram := (others => (others => '0')); -- Xilinx and Altera attributes attribute ram_style : string; attribute ram_style of ram : variable is g_storage; begin p_port: process(clock) begin if rising_edge(clock) then if en = '1' then if g_read_first then rdata <= ram(to_integer(address)); end if; if we = '1' then ram(to_integer(address)) := wdata; end if; if not g_read_first then rdata <= ram(to_integer(address)); end if; end if; end if; end process; end architecture;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/sid6581/vhdl_source/adsr_multi.vhd

5

8478

------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 Gideon's Logic Architectures' -- ------------------------------------------------------------------------------- -- -- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) -- -- Note that this file is copyrighted, and is not supposed to be used in other -- projects without written permission from the author. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.sid_debug_pkg.all; -- LUT: 195, FF:68 entity adsr_multi is generic ( g_num_voices : integer := 8 ); port ( clock : in std_logic; reset : in std_logic; voice_i : in unsigned(3 downto 0); enable_i : in std_logic; voice_o : out unsigned(3 downto 0); enable_o : out std_logic; gate : in std_logic; attack : in std_logic_vector(3 downto 0); decay : in std_logic_vector(3 downto 0); sustain : in std_logic_vector(3 downto 0); release : in std_logic_vector(3 downto 0); env_state: out std_logic_vector(1 downto 0); -- for testing only env_out : out unsigned(7 downto 0) ); end adsr_multi; -- 158 1 62 .. FF -- 45 2 35 .. 61 -- 26 4 1C .. 34 -- 13 8 0D .. 1B -- 6 16 07 .. 0C -- 7 30 00 .. 06 architecture gideon of adsr_multi is type presc_array_t is array(natural range <>) of unsigned(15 downto 0); constant prescalers : presc_array_t(0 to 15) := ( X"0008", X"001F", X"003E", X"005E", X"0094", X"00DB", X"010A", X"0138", X"0187", X"03D0", X"07A1", X"0C35", X"0F42", X"2DC7", X"4C4B", X"7A12" ); signal enveloppe : unsigned(7 downto 0) := (others => '0'); signal state : unsigned(1 downto 0) := (others => '0'); constant st_release : unsigned(1 downto 0) := "00"; constant st_attack : unsigned(1 downto 0) := "01"; constant st_decay : unsigned(1 downto 0) := "11"; type state_array_t is array(natural range <>) of unsigned(29 downto 0); signal state_array : state_array_t(0 to g_num_voices-1) := (others => (others => '0')); signal voice_dbg : t_voice_debug_array(0 to g_num_voices-1); begin env_out <= enveloppe; env_state <= std_logic_vector(state); -- FF-5E 01 -- 5D-37 02 -- 36-1B 04 -- 1A-0F 08 -- 0E-07 10 -- 06-01 1E process(clock) function logarithmic(lev: unsigned(7 downto 0)) return unsigned is variable res : unsigned(4 downto 0); begin if lev = X"00" then res := "00000"; -- prescaler off elsif lev < X"07" then res := "11101"; -- 1E-1 elsif lev < X"0F" then res := "01111"; -- 10-1 elsif lev < X"1B" then res := "00111"; -- 08-1 elsif lev < X"37" then res := "00011"; -- 04-1 elsif lev < X"5E" then res := "00001"; -- 02-1 else res := "00000"; -- 01-1 end if; return res; end function logarithmic; variable presc_select : integer range 0 to 15; variable cur_state : unsigned(1 downto 0); variable cur_env : unsigned(7 downto 0); variable cur_pre15 : unsigned(14 downto 0); variable cur_pre5 : unsigned(4 downto 0); variable next_state : unsigned(1 downto 0); variable next_env : unsigned(7 downto 0); variable next_pre15 : unsigned(14 downto 0); variable next_pre5 : unsigned(4 downto 0); variable presc_val : unsigned(14 downto 0); variable log_div : unsigned(4 downto 0); variable do_count_15 : std_logic; variable do_count_5 : std_logic; variable voice_x : integer; begin if rising_edge(clock) then cur_state := state_array(0)(1 downto 0); cur_env := state_array(0)(9 downto 2); cur_pre15 := state_array(0)(24 downto 10); cur_pre5 := state_array(0)(29 downto 25); voice_o <= voice_i; enable_o <= enable_i; next_state := cur_state; next_env := cur_env; next_pre15 := cur_pre15; next_pre5 := cur_pre5; -- PRESCALER LOGIC, output: do_count -- -- 15 bit prescaler select -- case cur_state is when st_attack => presc_select := to_integer(unsigned(attack)); when st_decay => presc_select := to_integer(unsigned(decay)); when others => -- includes release and idle presc_select := to_integer(unsigned(release)); end case; presc_val := prescalers(presc_select)(14 downto 0); -- 15 bit prescaler counter -- do_count_15 := '0'; if cur_pre15 = presc_val then next_pre15 := (others => '0'); do_count_15 := '1'; else next_pre15 := cur_pre15 + 1; end if; -- 5 bit prescaler -- log_div := logarithmic(cur_env); do_count_5 := '0'; if do_count_15='1' then if (cur_state = st_attack) or cur_pre5 = log_div then next_pre5 := "00000"; do_count_5 := '1'; else next_pre5 := cur_pre5 + 1; end if; end if; -- END PRESCALER LOGIC -- case cur_state is when st_attack => if gate = '0' then next_state := st_release; elsif cur_env = X"FF" then next_state := st_decay; end if; if do_count_15='1' then next_env := cur_env + 1; -- if cur_env = X"FE" or cur_env = X"FF" then -- result could be FF, but also 00!! -- next_state := st_decay; -- end if; end if; when st_decay => if gate = '0' then next_state := st_release; end if; if do_count_15='1' and do_count_5='1' and std_logic_vector(cur_env) /= (sustain & sustain) and cur_env /= X"00" then next_env := cur_env - 1; end if; when st_release => if gate = '1' then next_state := st_attack; end if; if do_count_15='1' and do_count_5='1' and cur_env /= X"00" then next_env := cur_env - 1; end if; when others => next_state := st_release; end case; if enable_i='1' then state_array(0 to g_num_voices-2) <= state_array(1 to g_num_voices-1); state_array(g_num_voices-1) <= next_pre5 & next_pre15 & next_env & next_state; enveloppe <= next_env; state <= next_state; voice_x := to_integer(voice_i); voice_dbg(voice_x).state <= next_state; voice_dbg(voice_x).enveloppe <= next_env; voice_dbg(voice_x).pre15 <= next_pre15; voice_dbg(voice_x).pre5 <= next_pre5; voice_dbg(voice_x).presc <= presc_val; voice_dbg(voice_x).gate <= gate; voice_dbg(voice_x).attack <= attack; voice_dbg(voice_x).decay <= decay; voice_dbg(voice_x).sustain <= sustain; voice_dbg(voice_x).release <= release; end if; if reset='1' then state <= "00"; enveloppe <= (others => '0'); enable_o <= '0'; end if; end if; end process; end gideon;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/ip/busses/vhdl_bfm/slot_bus_master_bfm_pkg.vhd

5

5996

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library std; use std.textio.all; library work; use work.slot_bus_pkg.all; package slot_bus_master_bfm_pkg is type t_slot_bus_master_bfm_object; type p_slot_bus_master_bfm_object is access t_slot_bus_master_bfm_object; type t_slot_bus_bfm_command is ( e_slot_none, e_slot_io_read, e_slot_bus_read, e_slot_io_write, e_slot_bus_write ); type t_slot_bus_master_bfm_object is record next_bfm : p_slot_bus_master_bfm_object; name : string(1 to 256); command : t_slot_bus_bfm_command; poll_time : time; address : unsigned(15 downto 0); data : std_logic_vector(7 downto 0); irq_pending : boolean; end record; ------------------------------------------------------------------------------------ shared variable slot_bus_master_bfms : p_slot_bus_master_bfm_object := null; ------------------------------------------------------------------------------------ procedure register_slot_bus_master_bfm(named : string; variable pntr: inout p_slot_bus_master_bfm_object); procedure bind_slot_bus_master_bfm(named : string; variable pntr: inout p_slot_bus_master_bfm_object); ------------------------------------------------------------------------------------ procedure slot_io_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0)); procedure slot_io_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0)); procedure slot_bus_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0)); procedure slot_bus_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0)); procedure slot_wait_irq(variable m : inout p_slot_bus_master_bfm_object); end slot_bus_master_bfm_pkg; package body slot_bus_master_bfm_pkg is procedure register_slot_bus_master_bfm(named : string; variable pntr : inout p_slot_bus_master_bfm_object) is begin -- Allocate a new BFM object in memory pntr := new t_slot_bus_master_bfm_object; -- Initialize object pntr.next_bfm := null; pntr.name(named'range) := named; -- add this pointer to the head of the linked list if slot_bus_master_bfms = null then -- first entry slot_bus_master_bfms := pntr; else -- insert new entry pntr.next_bfm := slot_bus_master_bfms; slot_bus_master_bfms := pntr; end if; pntr.irq_pending := false; pntr.poll_time := 10 ns; end register_slot_bus_master_bfm; procedure bind_slot_bus_master_bfm(named : string; variable pntr : inout p_slot_bus_master_bfm_object) is variable p : p_slot_bus_master_bfm_object; begin pntr := null; wait for 1 ns; -- needed to make sure that binding takes place after registration p := slot_bus_master_bfms; -- start at the root L1: while p /= null loop if p.name(named'range) = named then pntr := p; exit L1; else p := p.next_bfm; end if; end loop; end bind_slot_bus_master_bfm; ------------------------------------------------------------------------------ procedure slot_bus_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0)) is variable a_i : unsigned(15 downto 0); begin a_i := (others => '0'); a_i(addr'length-1 downto 0) := addr; m.address := a_i; m.command := e_slot_bus_read; while m.command /= e_slot_none loop wait for m.poll_time; end loop; data := m.data; end procedure; procedure slot_io_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0)) is variable a_i : unsigned(15 downto 0); begin a_i := (others => '0'); a_i(addr'length-1 downto 0) := addr; m.address := a_i; m.command := e_slot_io_read; while m.command /= e_slot_none loop wait for m.poll_time; end loop; data := m.data; end procedure; procedure slot_bus_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0)) is variable a_i : unsigned(15 downto 0); begin a_i := (others => '0'); a_i(addr'length-1 downto 0) := addr; m.address := a_i; m.command := e_slot_bus_write; m.data := data; while m.command /= e_slot_none loop wait for m.poll_time; end loop; end procedure; procedure slot_io_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0)) is variable a_i : unsigned(15 downto 0); begin a_i := (others => '0'); a_i(addr'length-1 downto 0) := addr; m.address := a_i; m.command := e_slot_io_write; m.data := data; while m.command /= e_slot_none loop wait for m.poll_time; end loop; end procedure; procedure slot_wait_irq(variable m : inout p_slot_bus_master_bfm_object) is begin while not m.irq_pending loop wait for m.poll_time; end loop; end procedure; end; ------------------------------------------------------------------------------

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/sampler/vhdl_sim/sampler_tb.vhd

4

4560

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.io_bus_pkg.all; use work.mem_bus_pkg.all; use work.sampler_pkg.all; use work.io_bus_bfm_pkg.all; use work.tl_flat_memory_model_pkg.all; entity sampler_tb is end entity; architecture tb of sampler_tb is signal clock : std_logic := '0'; signal reset : std_logic; signal io_req : t_io_req; signal io_resp : t_io_resp; signal mem_req : t_mem_req; signal mem_resp : t_mem_resp; signal sample_L : signed(17 downto 0); signal sample_R : signed(17 downto 0); signal new_sample : std_logic; begin clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; i_dut: entity work.sampler generic map ( g_num_voices => 8 ) port map ( clock => clock, reset => reset, io_req => io_req, io_resp => io_resp, mem_req => mem_req, mem_resp => mem_resp, sample_L => sample_L, sample_R => sample_R, new_sample => new_sample ); i_io_bfm: entity work.io_bus_bfm generic map ( g_name => "io_bfm" ) port map ( clock => clock, req => io_req, resp => io_resp ); i_mem_bfm: entity work.mem_bus_slave_bfm generic map ( g_name => "mem_bfm", g_latency => 2 ) port map ( clock => clock, req => mem_req, resp => mem_resp ); test: process variable io : p_io_bus_bfm_object; variable mem : h_mem_object; variable d : std_logic_vector(7 downto 0); begin wait until reset='0'; bind_io_bus_bfm("io_bfm", io); bind_mem_model("mem_bfm", mem); for i in 0 to 255 loop d := std_logic_vector(to_signed(integer(127.0*sin(real(i) / 40.58451048843)), 8)); write_memory_8(mem, std_logic_vector(to_unsigned(16#1234500#+i, 32)), d); end loop; io_write(io, X"00" + c_sample_volume , X"3F"); io_write(io, X"00" + c_sample_pan , X"07"); io_write(io, X"00" + c_sample_start_addr_h , X"01"); io_write(io, X"00" + c_sample_start_addr_mh , X"23"); io_write(io, X"00" + c_sample_start_addr_ml , X"45"); io_write(io, X"00" + c_sample_start_addr_l , X"00"); io_write(io, X"00" + c_sample_length_h , X"00"); io_write(io, X"00" + c_sample_length_m , X"01"); io_write(io, X"00" + c_sample_length_l , X"00"); io_write(io, X"00" + c_sample_rate_h , X"00"); io_write(io, X"00" + c_sample_rate_l , X"18"); io_write(io, X"00" + c_sample_control , X"01"); io_write(io, X"10" + c_sample_volume , X"28"); io_write(io, X"10" + c_sample_pan , X"0F"); io_write(io, X"10" + c_sample_start_addr_h , X"01"); io_write(io, X"10" + c_sample_start_addr_mh , X"23"); io_write(io, X"10" + c_sample_start_addr_ml , X"45"); io_write(io, X"10" + c_sample_start_addr_l , X"00"); io_write(io, X"10" + c_sample_length_h , X"00"); io_write(io, X"10" + c_sample_length_m , X"01"); io_write(io, X"10" + c_sample_length_l , X"00"); io_write(io, X"10" + c_sample_rate_h , X"00"); io_write(io, X"10" + c_sample_rate_l , X"05"); io_write(io, X"10" + c_sample_control , X"03"); -- repeat on io_write(io, X"20" + c_sample_volume , X"38"); io_write(io, X"20" + c_sample_pan , X"04"); io_write(io, X"20" + c_sample_start_addr_h , X"01"); io_write(io, X"20" + c_sample_start_addr_mh , X"23"); io_write(io, X"20" + c_sample_start_addr_ml , X"45"); io_write(io, X"20" + c_sample_start_addr_l , X"00"); io_write(io, X"20" + c_sample_length_h , X"00"); io_write(io, X"20" + c_sample_length_m , X"00"); io_write(io, X"20" + c_sample_length_l , X"80"); io_write(io, X"20" + c_sample_rate_h , X"00"); io_write(io, X"20" + c_sample_rate_l , X"09"); io_write(io, X"20" + c_sample_control , X"13"); -- repeat on, 16 bit wait; end process; end architecture;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/ip/sync_fifo/vhdl_source/sync_fifo.vhd

4

5506

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sync_fifo is generic ( g_depth : integer := 512; -- Actual depth. g_data_width : integer := 32; g_threshold : integer := 13; g_storage : string := "auto"; -- can also be "blockram" or "distributed" g_fall_through : boolean := false); port ( clock : in std_logic; reset : in std_logic; rd_en : in std_logic; wr_en : in std_logic; din : in std_logic_vector(g_data_width-1 downto 0); dout : out std_logic_vector(g_data_width-1 downto 0); flush : in std_logic; full : out std_logic; almost_full : out std_logic; empty : out std_logic; count : out integer range 0 to g_depth ); end sync_fifo; architecture rtl of sync_fifo is subtype t_data_element is std_logic_vector(g_data_width-1 downto 0); type t_data_array is array (0 to g_depth-1) of t_data_element; signal data_array : t_data_array; attribute ram_style : string; attribute ram_style of data_array : signal is g_storage; signal rd_data : std_logic_vector(g_data_width-1 downto 0); signal din_reg : std_logic_vector(g_data_width-1 downto 0); signal rd_inhibit : std_logic; signal rd_inhibit_d : std_logic; signal rd_en_flt : std_logic; signal rd_enable : std_logic; signal rd_pnt : integer range 0 to g_depth-1; signal rd_pnt_next : integer range 0 to g_depth-1; signal rd_index : integer range 0 to g_depth-1; signal wr_en_flt : std_logic; signal wr_pnt : integer range 0 to g_depth-1; signal num_el : integer range 0 to g_depth; begin -- Check generic values (also for synthesis) assert(g_threshold <= g_depth) report "Invalid parameter 'g_threshold'" severity failure; -- Filter fifo read/write enables for full/empty conditions rd_en_flt <= '1' when (num_el /= 0) and (rd_en='1') else '0'; wr_en_flt <= '1' when (num_el /= g_depth) and (wr_en='1') else '0'; -- Read enable depends on 'fall through' mode. In case fall through: prevent -- read & write at same address (when fifo is empty) rd_enable <= rd_en_flt when not(g_fall_through) else '0' when rd_inhibit = '1' else '1'; rd_inhibit <= '1' when rd_index = wr_pnt and wr_en_flt = '1' and g_fall_through else '0'; rd_index <= rd_pnt_next when g_fall_through and rd_en_flt = '1' and num_el /= 0 else rd_pnt; -- FIFO output data. Combinatoric switch to fix simultaneous read/write issues. dout <= din_reg when rd_inhibit_d = '1' else rd_data; p_dpram: process(clock) begin if rising_edge(clock) then if (wr_en_flt = '1') then data_array(wr_pnt) <= din; end if; if (rd_enable = '1') then rd_data <= data_array(rd_index); end if; end if; end process; rd_pnt_next <= 0 when (rd_pnt=g_depth-1) else rd_pnt + 1; process(clock) variable v_new_cnt : integer range 0 to g_depth; begin if (clock'event and clock='1') then rd_inhibit_d <= rd_inhibit; -- Modify read/write pointers if (rd_en_flt='1') then rd_pnt <= rd_pnt_next; end if; if (wr_en_flt='1') then -- Registered din is needed for BlockRAM based 'fall through' FIFO din_reg <= din; if (wr_pnt=g_depth-1) then wr_pnt <= 0; else wr_pnt <= wr_pnt + 1; end if; end if; -- Update number of elements in fifo for next clock cycle if (rd_en_flt = '1') and (wr_en_flt = '0') then v_new_cnt := num_el - 1; elsif (rd_en_flt = '0') and (wr_en_flt = '1') then v_new_cnt := num_el + 1; elsif (flush='1') then v_new_cnt := 0; else v_new_cnt := num_el; end if; num_el <= v_new_cnt; -- update (almost)full and empty indications almost_full <= '0'; if (v_new_cnt >= g_threshold) then almost_full <= '1'; end if; empty <= '0'; if (v_new_cnt = 0) then empty <= '1'; end if; full <= '0'; if (v_new_cnt = g_depth) then full <= '1'; end if; if (flush='1') or (reset='1') then rd_pnt <= 0; wr_pnt <= 0; num_el <= 0; rd_inhibit_d <= '0'; if (reset='1') then full <= '0'; empty <= '1'; almost_full <= '0'; end if; end if; end if; end process; count <= num_el; end rtl;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/mem_ctrl/vhdl_source/fpga_mem_test_v7.vhd

5

2933

------------------------------------------------------------------------------- -- Title : External Memory controller for SDRAM ------------------------------------------------------------------------------- -- Description: This module implements a simple, single burst memory controller. -- User interface is 16 bit (burst of 4), externally 8x 8 bit. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.mem_bus_pkg.all; entity fpga_mem_test_v7 is port ( CLOCK_50 : in std_logic; SDRAM_CLK : out std_logic; SDRAM_CKE : out std_logic; SDRAM_CSn : out std_logic := '1'; SDRAM_RASn : out std_logic := '1'; SDRAM_CASn : out std_logic := '1'; SDRAM_WEn : out std_logic := '1'; SDRAM_DQM : out std_logic := '0'; SDRAM_A : out std_logic_vector(14 downto 0); SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z'); MOTOR_LEDn : out std_logic; ACT_LEDn : out std_logic ); end fpga_mem_test_v7; architecture tb of fpga_mem_test_v7 is signal clock : std_logic := '1'; signal clk_2x : std_logic := '1'; signal reset : std_logic := '0'; signal inhibit : std_logic := '0'; signal is_idle : std_logic := '0'; signal req : t_mem_burst_32_req := c_mem_burst_32_req_init; signal resp : t_mem_burst_32_resp; signal okay : std_logic; begin i_clk: entity work.s3a_clockgen port map ( clk_50 => CLOCK_50, reset_in => '0', dcm_lock => open, sys_clock => clock, -- 50 MHz sys_reset => reset, sys_clock_2x => clk_2x ); i_checker: entity work.ext_mem_test_32 port map ( clock => clock, reset => reset, req => req, resp => resp, okay => ACT_LEDn ); i_mem_ctrl: entity work.ext_mem_ctrl_v7 generic map ( q_tcko_data => 5 ns, g_simulation => false ) port map ( clock => clock, clk_2x => clk_2x, reset => reset, inhibit => inhibit, is_idle => is_idle, req => req, resp => resp, SDRAM_CLK => SDRAM_CLK, SDRAM_CKE => SDRAM_CKE, SDRAM_CSn => SDRAM_CSn, SDRAM_RASn => SDRAM_RASn, SDRAM_CASn => SDRAM_CASn, SDRAM_WEn => SDRAM_WEn, SDRAM_DQM => SDRAM_DQM, SDRAM_BA => SDRAM_A(14 downto 13), SDRAM_A => SDRAM_A(12 downto 0), SDRAM_DQ => SDRAM_DQ ); MOTOR_LEDn <= 'Z'; end;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/usb2/vhdl_source/bridge_to_mem_ctrl.vhd

4

2777

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity bridge_to_mem_ctrl is port ( ulpi_clock : in std_logic; ulpi_reset : in std_logic; nano_addr : in unsigned(7 downto 0); nano_write : in std_logic; nano_wdata : in std_logic_vector(15 downto 0); -- cmd interface sys_clock : in std_logic; sys_reset : in std_logic; cmd_addr : out std_logic_vector(3 downto 0); cmd_valid : out std_logic; cmd_write : out std_logic; cmd_wdata : out std_logic_vector(15 downto 0); cmd_ack : in std_logic ); end entity; architecture gideon of bridge_to_mem_ctrl is signal fifo_data_in : std_logic_vector(19 downto 0); signal fifo_data_out : std_logic_vector(19 downto 0); signal fifo_get : std_logic; signal fifo_empty : std_logic; signal fifo_write : std_logic; signal cmd_data_out : std_logic_vector(19 downto 0); begin fifo_data_in <= std_logic_vector(nano_addr(3 downto 0)) & nano_wdata; fifo_write <= '1' when (nano_addr(7 downto 4)=X"7" and nano_write='1') else '0'; i_cmd_fifo: entity work.async_fifo generic map ( g_data_width => 20, g_depth_bits => 3, g_count_bits => 3, g_threshold => 3, g_storage => "distributed" ) port map ( -- write port signals (synchronized to write clock) wr_clock => ulpi_clock, wr_reset => ulpi_reset, wr_en => fifo_write, wr_din => fifo_data_in, wr_flush => '0', wr_count => open, wr_full => open, wr_almost_full => open, wr_error => open, wr_inhibit => open, -- read port signals (synchronized to read clock) rd_clock => sys_clock, rd_reset => sys_reset, rd_en => fifo_get, rd_dout => fifo_data_out, rd_count => open, rd_empty => fifo_empty, rd_almost_empty => open, rd_error => open ); i_ft: entity work.fall_through_add_on generic map ( g_data_width => 20) port map ( clock => sys_clock, reset => sys_reset, -- fifo side rd_dout => fifo_data_out, rd_empty => fifo_empty, rd_en => fifo_get, -- consumer side data_out => cmd_data_out, data_valid => cmd_valid, data_next => cmd_ack ); cmd_addr <= cmd_data_out(19 downto 16); cmd_wdata <= cmd_data_out(15 downto 0); cmd_write <= '1'; -- we don't support reads yet end architecture;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v4.vhd

5

9586

------------------------------------------------------------------------------- -- Title : External Memory controller for SDRAM (no burst) ------------------------------------------------------------------------------- -- Description: This module implements a simple, single access memory controller. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; library work; use work.mem_bus_pkg.all; entity ext_mem_ctrl_v4 is generic ( g_simulation : boolean := false; A_Width : integer := 15; SDRAM_WakeupTime : integer := 40; -- refresh periods SDRAM_Refr_period : integer := 375 ); port ( clock : in std_logic := '0'; clk_shifted : in std_logic := '0'; reset : in std_logic := '0'; inhibit : in std_logic; is_idle : out std_logic; req : in t_mem_req; resp : out t_mem_resp; SDRAM_CLK : out std_logic; SDRAM_CKE : out std_logic; SDRAM_CSn : out std_logic := '1'; SDRAM_RASn : out std_logic := '1'; SDRAM_CASn : out std_logic := '1'; SDRAM_WEn : out std_logic := '1'; SDRAM_DQM : out std_logic := '0'; MEM_A : out std_logic_vector(A_Width-1 downto 0); MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z')); end ext_mem_ctrl_v4; -- ADDR: 25 24 23 ... -- 0 X X ... SDRAM (32MB) architecture Gideon of ext_mem_ctrl_v4 is type t_init is record addr : std_logic_vector(15 downto 0); cmd : std_logic_vector(2 downto 0); -- we-cas-ras end record; type t_init_array is array(natural range <>) of t_init; constant c_init_array : t_init_array(0 to 7) := ( ( X"0400", "010" ), -- auto precharge ( X"0220", "000" ), -- mode register, burstlen=1, writelen=1, CAS lat = 2 ( X"0000", "001" ), -- auto refresh ( X"0000", "001" ), -- auto refresh ( X"0000", "001" ), -- auto refresh ( X"0000", "001" ), -- auto refresh ( X"0000", "001" ), -- auto refresh ( X"0000", "001" ) ); type t_state is (boot, init, idle, sd_cas, sd_wait); signal state : t_state; signal sram_d_o : std_logic_vector(MEM_D'range) := (others => '1'); signal sram_d_t : std_logic := '0'; signal delay : integer range 0 to 15; signal inhibit_d : std_logic; signal rwn_i : std_logic; signal tag : std_logic_vector(req.tag'range); signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0'); signal col_addr : std_logic_vector(9 downto 0) := (others => '0'); signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1; signal do_refresh : std_logic := '0'; signal not_clock : std_logic; signal reg_out : integer range 0 to 3 := 0; signal rdata_i : std_logic_vector(7 downto 0) := (others => '0'); signal dout_sel : std_logic := '0'; signal refr_delay : integer range 0 to 3; signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1; signal init_cnt : integer range 0 to c_init_array'high; signal enable_sdram : std_logic := '1'; signal req_i : std_logic; signal dack : std_logic; signal rack : std_logic; signal rack_tag : std_logic_vector(req.tag'range); signal dack_tag : std_logic_vector(req.tag'range); -- attribute fsm_encoding : string; -- attribute fsm_encoding of state : signal is "sequential"; -- attribute register_duplication : string; -- attribute register_duplication of mem_a_i : signal is "no"; attribute iob : string; attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB attribute iob of SDRAM_CKE : signal is "false"; begin is_idle <= '1' when state = idle else '0'; req_i <= req.request; resp.data <= rdata_i; resp.rack <= rack; resp.rack_tag <= rack_tag; resp.dack_tag <= dack_tag; process(clock) procedure send_refresh_cmd is begin do_refresh <= '0'; SDRAM_CSn <= '0'; SDRAM_RASn <= '0'; SDRAM_CASn <= '0'; SDRAM_WEn <= '1'; -- Auto Refresh refr_delay <= 3; end procedure; procedure accept_req is begin rack <= '1'; rack_tag <= req.tag; tag <= req.tag; rwn_i <= req.read_writen; sram_d_t <= '0'; --not req.read_writen; sram_d_o <= req.data; mem_a_i(12 downto 0) <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits mem_a_i(14 downto 13) <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits SDRAM_CSn <= '0'; SDRAM_RASn <= '0'; SDRAM_CASn <= '1'; SDRAM_WEn <= '1'; -- Command = ACTIVE sram_d_t <= '0'; -- no data yet delay <= 1; state <= sd_cas; end procedure; begin if rising_edge(clock) then rack <= '0'; dack <= '0'; rack_tag <= (others => '0'); dack_tag <= (others => '0'); dout_sel <= '0'; inhibit_d <= inhibit; rdata_i <= MEM_D; -- clock in SDRAM_CSn <= '1'; SDRAM_CKE <= enable_sdram; if refr_delay /= 0 then refr_delay <= refr_delay - 1; end if; case state is when boot => enable_sdram <= '1'; if refresh_cnt = 0 then boot_cnt <= boot_cnt - 1; if boot_cnt = 1 then state <= init; end if; elsif g_simulation then state <= idle; end if; when init => mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range); SDRAM_RASn <= c_init_array(init_cnt).cmd(0); SDRAM_CASn <= c_init_array(init_cnt).cmd(1); SDRAM_WEn <= c_init_array(init_cnt).cmd(2); if delay = 0 then delay <= 7; SDRAM_CSn <= '0'; if init_cnt = c_init_array'high then state <= idle; else init_cnt <= init_cnt + 1; end if; else delay <= delay - 1; end if; when idle => -- first cycle after inhibit goes 0, do not do refresh -- this enables putting cartridge images in sdram if do_refresh='1' and not (inhibit_d='1' or inhibit='1') then send_refresh_cmd; elsif inhibit='0' then if req_i='1' and refr_delay = 0 then accept_req; end if; end if; when sd_cas => mem_a_i(10) <= '1'; -- auto precharge mem_a_i(9 downto 0) <= col_addr; sram_d_t <= not rwn_i; -- enable for writes if delay = 0 then -- read or write with auto precharge SDRAM_CSn <= '0'; SDRAM_RASn <= '1'; SDRAM_CASn <= '0'; SDRAM_WEn <= rwn_i; if rwn_i='0' then -- write delay <= 2; else delay <= 2; end if; state <= sd_wait; else delay <= delay - 1; end if; when sd_wait => sram_d_t <= '0'; if delay=0 then if rwn_i = '1' then -- read dack <= '1'; dack_tag <= tag; end if; state <= idle; else delay <= delay - 1; end if; when others => null; end case; if refresh_cnt = SDRAM_Refr_period-1 then do_refresh <= '1'; refresh_cnt <= 0; else refresh_cnt <= refresh_cnt + 1; end if; if reset='1' then state <= boot; sram_d_t <= '0'; delay <= 0; tag <= (others => '0'); do_refresh <= '0'; boot_cnt <= SDRAM_WakeupTime-1; init_cnt <= 0; enable_sdram <= '1'; end if; end if; end process; MEM_D <= sram_d_o when sram_d_t='1' else (others => 'Z'); MEM_A <= mem_a_i; not_clock <= not clk_shifted; clkout: FDDRRSE port map ( CE => '1', C0 => clk_shifted, C1 => not_clock, D0 => '0', D1 => enable_sdram, Q => SDRAM_CLK, R => '0', S => '0' ); end Gideon;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/mem_ctrl/vhdl_sim/ext_mem_ctrl_v7_tb.vhd

5

10543

------------------------------------------------------------------------------- -- Title : External Memory controller for SDRAM ------------------------------------------------------------------------------- -- Description: This module implements a simple, single burst memory controller. -- User interface is 16 bit (burst of 4), externally 8x 8 bit. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.vital_timing.all; library work; use work.mem_bus_pkg.all; entity ext_mem_ctrl_v7_tb is end ext_mem_ctrl_v7_tb; architecture tb of ext_mem_ctrl_v7_tb is signal clock : std_logic := '1'; signal clk_2x : std_logic := '1'; signal reset : std_logic := '0'; signal inhibit : std_logic := '0'; signal is_idle : std_logic; signal req : t_mem_burst_32_req := c_mem_burst_32_req_init; signal resp : t_mem_burst_32_resp; signal SDRAM_CLK : std_logic; signal SDRAM_CKE : std_logic; signal SDRAM_CSn : std_logic := '1'; signal SDRAM_RASn : std_logic := '1'; signal SDRAM_CASn : std_logic := '1'; signal SDRAM_WEn : std_logic := '1'; signal SDRAM_DQM : std_logic := '0'; signal SDRAM_A : std_logic_vector(12 downto 0); signal SDRAM_BA : std_logic_vector(1 downto 0); signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z'); signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H'); signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H'); constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns ); begin clock <= not clock after 12 ns; clk_2x <= not clk_2x after 6 ns; reset <= '1', '0' after 100 ns; i_mut: entity work.ext_mem_ctrl_v7 generic map ( q_tcko_data => 5 ns, g_simulation => true ) port map ( clock => clock, clk_2x => clk_2x, reset => reset, inhibit => inhibit, is_idle => is_idle, req => req, resp => resp, SDRAM_CLK => SDRAM_CLK, SDRAM_CKE => SDRAM_CKE, SDRAM_CSn => SDRAM_CSn, SDRAM_RASn => SDRAM_RASn, SDRAM_CASn => SDRAM_CASn, SDRAM_WEn => SDRAM_WEn, SDRAM_DQM => SDRAM_DQM, SDRAM_BA => SDRAM_BA, SDRAM_A => SDRAM_A, SDRAM_DQ => SDRAM_DQ ); p_test: process procedure queue_req(rw : std_logic; bank : integer; row : integer; col : integer) is begin req.request <= '1'; req.read_writen <= rw; req.address <= to_unsigned(bank*8192 + col*8 + row*32768, req.address'length); wait for 2 ns; while resp.ready='0' loop wait until clock='1'; end loop; wait until clock='1'; req.request <= '0'; end procedure; begin req.read_writen <= '1'; -- read req.request <= '0'; req.address <= unsigned(to_signed(-32, req.address'length)); req.data_pop <= '0'; wait until reset='0'; wait until clock='1'; -- simple write / readback test queue_req('0', 0, 0, 0); queue_req('1', 0, 0, 0); while true loop -- read-read, other row, other bank queue_req('1', 0, 16, 127); queue_req('1', 1, 17, 0); -- read-read, other row, same bank queue_req('1', 1, 18, 1); -- read-read, same row, other bank queue_req('1', 2, 18, 2); -- read-read, same row, same bank queue_req('1', 2, 18, 3); -- read-write, other row, other bank queue_req('0', 0, 16, 4); -- read-write, other row, same bank queue_req('1', 0, 16, 127); queue_req('0', 0, 17, 5); -- read-write, same row, other bank queue_req('1', 0, 18, 127); queue_req('0', 1, 18, 6); -- read-write, same row, same bank queue_req('1', 2, 19, 127); queue_req('0', 2, 19, 7); -- write-read, other row, other bank queue_req('1', 3, 20, 8); -- write-read, other row, same bank queue_req('0', 0, 16, 127); queue_req('1', 0, 17, 9); -- write-read, same row, other bank queue_req('0', 1, 18, 127); queue_req('1', 2, 18, 10); -- write-read, same row, same bank queue_req('0', 3, 19, 127); queue_req('1', 3, 19, 11); -- write-write, other row, other bank queue_req('0', 0, 20, 127); queue_req('0', 1, 21, 12); -- write-write, other row, same bank queue_req('0', 1, 22, 13); -- write-write, same row, other bank queue_req('0', 2, 22, 14); -- write-write, same row, same bank queue_req('0', 2, 22, 15); -- read write toggle performance tests.. for i in 1 to 10 loop queue_req('1', 0, 0, i); queue_req('0', 1, 0, i); end loop; for i in 1 to 10 loop queue_req('1', 0, 0, i); queue_req('0', 0, 0, i); end loop; for i in 1 to 10 loop queue_req('1', 0, 0, i); queue_req('0', 0, 1, i); end loop; for i in 1 to 1000 loop queue_req('1', 0, 0, i); end loop; end loop; wait; end process; p_write: process(clock) variable v_data : unsigned(31 downto 0) := X"DEAD4001"; begin if rising_edge(clock) then if resp.wdata_full='0' and reset='0' then req.data_push <= '1'; req.data <= std_logic_vector(v_data); req.byte_en <= "0111"; v_data := v_data + 1; else req.data_push <= '0'; end if; end if; end process; i_sdram : entity work.mt48lc16m16a2 generic map( tipd_BA0 => c_wire_delay, tipd_BA1 => c_wire_delay, tipd_DQMH => c_wire_delay, tipd_DQML => c_wire_delay, tipd_DQ0 => c_wire_delay, tipd_DQ1 => c_wire_delay, tipd_DQ2 => c_wire_delay, tipd_DQ3 => c_wire_delay, tipd_DQ4 => c_wire_delay, tipd_DQ5 => c_wire_delay, tipd_DQ6 => c_wire_delay, tipd_DQ7 => c_wire_delay, tipd_DQ8 => c_wire_delay, tipd_DQ9 => c_wire_delay, tipd_DQ10 => c_wire_delay, tipd_DQ11 => c_wire_delay, tipd_DQ12 => c_wire_delay, tipd_DQ13 => c_wire_delay, tipd_DQ14 => c_wire_delay, tipd_DQ15 => c_wire_delay, tipd_CLK => c_wire_delay, tipd_CKE => c_wire_delay, tipd_A0 => c_wire_delay, tipd_A1 => c_wire_delay, tipd_A2 => c_wire_delay, tipd_A3 => c_wire_delay, tipd_A4 => c_wire_delay, tipd_A5 => c_wire_delay, tipd_A6 => c_wire_delay, tipd_A7 => c_wire_delay, tipd_A8 => c_wire_delay, tipd_A9 => c_wire_delay, tipd_A10 => c_wire_delay, tipd_A11 => c_wire_delay, tipd_A12 => c_wire_delay, tipd_WENeg => c_wire_delay, tipd_RASNeg => c_wire_delay, tipd_CSNeg => c_wire_delay, tipd_CASNeg => c_wire_delay, -- tpd delays tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ), tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ), -- -- tpw values: pulse widths -- tpw_CLK_posedge : VitalDelayType := UnitDelay; -- tpw_CLK_negedge : VitalDelayType := UnitDelay; -- -- tsetup values: setup times -- tsetup_DQ0_CLK : VitalDelayType := UnitDelay; -- -- thold values: hold times -- thold_DQ0_CLK : VitalDelayType := UnitDelay; -- -- tperiod_min: minimum clock period = 1/max freq -- tperiod_CLK_posedge : VitalDelayType := UnitDelay; -- mem_file_name => "none", tpowerup => 100 ns ) port map( BA0 => SDRAM_BA(0), BA1 => SDRAM_BA(1), DQMH => dummy_dqm(1), DQML => SDRAM_DQM, DQ0 => SDRAM_DQ(0), DQ1 => SDRAM_DQ(1), DQ2 => SDRAM_DQ(2), DQ3 => SDRAM_DQ(3), DQ4 => SDRAM_DQ(4), DQ5 => SDRAM_DQ(5), DQ6 => SDRAM_DQ(6), DQ7 => SDRAM_DQ(7), DQ8 => dummy_data(8), DQ9 => dummy_data(9), DQ10 => dummy_data(10), DQ11 => dummy_data(11), DQ12 => dummy_data(12), DQ13 => dummy_data(13), DQ14 => dummy_data(14), DQ15 => dummy_data(15), CLK => SDRAM_CLK, CKE => SDRAM_CKE, A0 => SDRAM_A(0), A1 => SDRAM_A(1), A2 => SDRAM_A(2), A3 => SDRAM_A(3), A4 => SDRAM_A(4), A5 => SDRAM_A(5), A6 => SDRAM_A(6), A7 => SDRAM_A(7), A8 => SDRAM_A(8), A9 => SDRAM_A(9), A10 => SDRAM_A(10), A11 => SDRAM_A(11), A12 => SDRAM_A(12), WENeg => SDRAM_WEn, RASNeg => SDRAM_RASn, CSNeg => SDRAM_CSn, CASNeg => SDRAM_CASn ); end;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/ip/memory/vhdl_source/dpram.vhd

5

3149

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity dpram is generic ( g_width_bits : positive := 16; g_depth_bits : positive := 9; g_read_first_a : boolean := false; g_read_first_b : boolean := false; g_storage : string := "auto" -- can also be "block" or "distributed" ); port ( a_clock : in std_logic; a_address : in unsigned(g_depth_bits-1 downto 0); a_rdata : out std_logic_vector(g_width_bits-1 downto 0); a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); a_en : in std_logic := '1'; a_we : in std_logic := '0'; b_clock : in std_logic := '0'; b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0'); b_rdata : out std_logic_vector(g_width_bits-1 downto 0); b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); b_en : in std_logic := '1'; b_we : in std_logic := '0' ); attribute keep_hierarchy : string; attribute keep_hierarchy of dpram : entity is "yes"; end entity; architecture xilinx of dpram is type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0); shared variable ram : t_ram := (others => (others => '0')); -- Xilinx and Altera attributes attribute ram_style : string; attribute ram_style of ram : variable is g_storage; begin ----------------------------------------------------------------------- -- PORT A ----------------------------------------------------------------------- p_port_a: process(a_clock) begin if rising_edge(a_clock) then if a_en = '1' then if g_read_first_a then a_rdata <= ram(to_integer(a_address)); end if; if a_we = '1' then ram(to_integer(a_address)) := a_wdata; end if; if not g_read_first_a then a_rdata <= ram(to_integer(a_address)); end if; end if; end if; end process; ----------------------------------------------------------------------- -- PORT B ----------------------------------------------------------------------- p_port_b: process(b_clock) begin if rising_edge(b_clock) then if b_en = '1' then if g_read_first_b then b_rdata <= ram(to_integer(b_address)); end if; if b_we = '1' then ram(to_integer(b_address)) := b_wdata; end if; if not g_read_first_b then b_rdata <= ram(to_integer(b_address)); end if; end if; end if; end process; end architecture;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/icap/vhdl_source/icap_pkg.vhd

5

312

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package icap_pkg is constant c_icap_fpga_type : unsigned(3 downto 0) := X"0"; constant c_icap_write : unsigned(3 downto 0) := X"4"; constant c_icap_pulse : unsigned(3 downto 0) := X"8"; end package;

gpl-3.0

JamesHyunKim/myhdl

tests/counter/testbench/counter_tb/vhdl/counter_tb.vhd

2

1403

---------------------------------------------------------- -- Design : Simple testbench for an 8-bit VHDL counter -- Author : Javier D. Garcia-Lasheras ---------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity counter_tb is -- entity declaration end counter_tb; ----------------------------------------------------------------------- architecture testbench of counter_tb is component counter port( clock: in std_logic; clear: in std_logic; count: in std_logic; Q: out std_logic_vector(7 downto 0) ); end component; signal t_clock: std_logic; signal t_clear: std_logic; signal t_count: std_logic; signal t_Q: std_logic_vector(7 downto 0); begin U_counter: counter port map (t_clock, t_clear, t_count, t_Q); process begin t_clock <= '0'; -- clock cycle is 10 ns wait for 5 ns; t_clock <= '1'; wait for 5 ns; end process; process begin t_clear <= '1'; -- start counting t_count <= '1'; wait for 50 ns; t_clear <= '0'; -- clear output wait for 1000 ns; report "Testbench of Adder completed successfully!" severity note; wait; end process; end testbench; ----------------------------------------------------------------

gpl-3.0

davidhorrocks/1541UltimateII

fpga/1541/vhdl_source/c1541_timing.vhd

4

2249

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity c1541_timing is port ( clock : in std_logic; reset : in std_logic; use_c64_reset : in std_logic; c64_reset_n : in std_logic; iec_reset_n : in std_logic; iec_reset_o : out std_logic; drive_stop : in std_logic; drv_clock_en : out std_logic; -- 1/12.5 (4 MHz) cpu_clock_en : out std_logic ); -- 1/50 (1 MHz) end c1541_timing; architecture Gideon of c1541_timing is signal div_cnt : unsigned(3 downto 0) := "0000"; signal pre_cnt : unsigned(1 downto 0) := "00"; signal cpu_clock_en_i : std_logic := '0'; signal toggle : std_logic := '0'; signal iec_reset_sh : std_logic_vector(0 to 2) := "000"; signal c64_reset_sh : std_logic_vector(0 to 2) := "000"; begin process(clock) begin if rising_edge(clock) then drv_clock_en <= '0'; cpu_clock_en_i <= '0'; if drive_stop='0' then if (div_cnt = X"B" and toggle='0') or (div_cnt = X"C" and toggle='1') then div_cnt <= X"0"; drv_clock_en <= '1'; toggle <= not toggle; pre_cnt <= pre_cnt + 1; if pre_cnt = "11" then cpu_clock_en_i <= '1'; end if; else div_cnt <= div_cnt + 1; end if; end if; if cpu_clock_en_i = '1' then iec_reset_sh(0) <= not iec_reset_n; iec_reset_sh(1 to 2) <= iec_reset_sh(0 to 1); c64_reset_sh(0) <= use_c64_reset and not c64_reset_n; c64_reset_sh(1 to 2) <= c64_reset_sh(0 to 1); end if; if reset='1' then toggle <= '0'; pre_cnt <= (others => '0'); div_cnt <= (others => '0'); end if; end if; end process; cpu_clock_en <= cpu_clock_en_i; iec_reset_o <= '1' when (iec_reset_sh="111") or (c64_reset_sh="111") else '0'; end Gideon;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/ip/busses/vhdl_bfm/slot_bus_master_bfm.vhd

5

2373

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.slot_bus_pkg.all; use work.slot_bus_master_bfm_pkg.all; entity slot_bus_master_bfm is generic ( g_name : string ); port ( clock : in std_logic; req : out t_slot_req; resp : in t_slot_resp ); end slot_bus_master_bfm; architecture bfm of slot_bus_master_bfm is shared variable this : p_slot_bus_master_bfm_object := null; signal bound : boolean := false; type t_state is (idle, exec); signal state : t_state := idle; signal delay : integer := 0; begin -- this process registers this instance of the bfm to the server package bind: process begin register_slot_bus_master_bfm(g_name, this); bound <= true; wait; end process; process(clock) begin if rising_edge(clock) then req.bus_write <= '0'; req.io_read <= '0'; req.io_write <= '0'; this.irq_pending := (resp.irq = '1'); case state is when idle => req <= c_slot_req_init; if bound then delay <= 3; if this.command /= e_slot_none then req.io_address <= this.address; req.bus_address <= this.address; req.data <= this.data; end if; case this.command is when e_slot_io_read => state <= exec; when e_slot_io_write => state <= exec; when e_slot_bus_read => state <= exec; when e_slot_bus_write => req.bus_write <= '1'; state <= exec; when others => null; end case; end if; when exec => if delay=0 then case this.command is when e_slot_io_read => req.io_read <= '1'; when e_slot_io_write => req.io_write <= '1'; when others => null; end case; if resp.reg_output='1' then this.data := resp.data; else this.data := (others => 'X'); end if; this.command := e_slot_none; state <= idle; else delay <= delay - 1; end if; when others => null; end case; end if; end process; end bfm;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/sigma_delta_dac/vhdl_sim/sine_osc_tb.vhd

5

931

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity sine_osc_tb is end sine_osc_tb; architecture tb of sine_osc_tb is signal clock : std_logic := '0'; signal reset : std_logic; signal sine : signed(15 downto 0); signal cosine : signed(15 downto 0); begin clock <= not clock after 10 ns; reset <= '1', '0' after 100 ns; osc: entity work.sine_osc port map ( clock => clock, reset => reset, sine => sine, cosine => cosine ); process variable n: time; variable p: integer; begin wait until reset='0'; n := now; while true loop wait until sine(15)='1'; p := (now - n) / 20 ns; n := now; report "Period: " & integer'image(p) & " samples" severity note; end loop; end process; end tb;

gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_status_flags_as.vhd

9

15251

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block kS5RyUqA0GEmQjNgWngWZVAacB7b+BQQcD6vmZxeLh0UFKV8v4e0wPlb9UEnetDuLG1UOtRsoWM+ JpY3jji2PQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block B7zNu769eR7bKWAGHj9/0eNDSGvXiqMj82G0EY6o/uh/SIFwA1KhTmzWtWnLu0Jp7RP5GNPk6sLY pX0/g+4u3yb3eGFjoMEUR7Xuyx+NxR236QDSWH4PQ8KaiWgTsqL4LXAaH8NNqk0FYEvapaZB1sh2 oBKwlNZSL5S4Jgt6Nnk= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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gpl-3.0

Project-Bonfire/EHA

RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/ParityChecker_for_LBDR.vhd

9

681

--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; entity parity_checker_for_LBDR is generic(DATA_WIDTH : integer := 32); port( RX: in std_logic_vector(DATA_WIDTH-1 downto 0); empty: in std_logic; faulty: out std_logic ); end parity_checker_for_LBDR; architecture behavior of parity_checker_for_LBDR is signal xor_all: std_logic; begin process(empty, RX) begin if empty = '0' then xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1)); else xor_all <= '0'; end if; end process; process(RX, xor_all)begin faulty <= '0'; if xor_all /= RX(0) then faulty <= '1'; end if; end process; end;

gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_axi_write_wrapper.vhd

9

65399

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Ay7yUo344MX/HpMjaa/BfEnxojenX57nfZN9+kMuLNQKkNFQNMwwKXWYirwn8AeviwFh8Ye8bBwr 07jpMsc3Ww== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block GtKHFr1bTEO3BDZPZ8B11z5mN8Sou0TY2F19SmGWFzX1kEzsWibDjneI2l/UloaSNmCpkBvA5It+ 3v5N0cX3jTFQb6WArjXcGBdkY+96yJsuL/xjolKd2zK29DYDPjWDcqAAYun1mT7vy+P/RlE+qcEV 8d59OQmsYNVgHec5WPI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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gpl-3.0

julioamerico/prj_crc_ip

src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@f2@d@s@s_@a@c@e_@p@p@e_@d@p@r@a@m/_primary.vhd

3

1382

library verilog; use verilog.vl_types.all; entity F2DSS_ACE_PPE_DPRAM is port( CLKA : in vl_logic; CSBA : in vl_logic; RWBA : in vl_logic; AA : in vl_logic_vector(8 downto 0); DIA : in vl_logic_vector(31 downto 0); DOA : out vl_logic_vector(31 downto 0); CLKB : in vl_logic; CSBB : in vl_logic; RWBB : in vl_logic; AB : in vl_logic_vector(8 downto 0); DIB : in vl_logic_vector(31 downto 0); DOB : out vl_logic_vector(31 downto 0); TEST_MODE : in vl_logic; RB_TEST : in vl_logic; RB_CSBA : in vl_logic; RB_CSBB : in vl_logic; RB_RWBA : in vl_logic; RB_RWBB : in vl_logic; RB_ADA : in vl_logic_vector(8 downto 0); RB_ADB : in vl_logic_vector(8 downto 0); RB_WDA : in vl_logic_vector(31 downto 0); RB_WDB : in vl_logic_vector(31 downto 0); RB_RDA : out vl_logic_vector(31 downto 0); RB_RDB : out vl_logic_vector(31 downto 0) ); end F2DSS_ACE_PPE_DPRAM;

gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo16_patch/input_block_fifo16_patch.vhd

9

15036

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block a72d+j/QkZDkv8eDO5pA9BEngzdbQGQHhuxY2nDNAEhnIoRf0SgDQdLQUGAjqTT/LgQ/F0Cs+16w c1P7TVYYIQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block l/1IXczTwKQBVElHEsh+Zvo7KblkXaJxo8UlygCcRw3ZY3tWBi5BiOQVA9yqXhof3R4G5ULkurKn 46GuEoIAY3OUXtbKoFE/fg9ET9kDVkPf1jISgRyi7rAeyld9i/Cbc18E0R0zSIcXYm0KkBSXRMxF 9wuwdCtkYN244/gGxpo= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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gpl-3.0

meaepeppe/FIR_ISA

VHDL/FIR_filter.vhd

1

4881

LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE ieee.math_real.all; USE work.FIR_constants.all; ENTITY FIR_filter IS PORT( CLK, RST_n: IN STD_LOGIC; VIN: IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); Coeffs: IN STD_LOGIC_VECTOR(((Ord+1)*Nb)-1 DOWNTO 0); --# of coeffs IS Ord+1 VOUT: OUT STD_LOGIC; DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0) ); END ENTITY; ARCHITECTURE beh_fir OF FIR_filter IS TYPE sum_array IS ARRAY (Ord DOWNTO 0) OF STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0); TYPE sig_array IS ARRAY (Ord DOWNTO 0) OF STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); SIGNAL Bi: sig_array; -- there IS Ord instead of Ord-1 becaUSE the coeffs are Ord+1 SIGNAL REG_OUT_array: sig_array; SIGNAL SUM_OUT_array: sum_array; SIGNAL VIN_delay_line: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL Coeffs_delayed: STD_LOGIC_VECTOR(((Ord+1)*Nb)-1 DOWNTO 0); SIGNAL DIN_mult: STD_LOGIC_VECTOR(2*Nb-1 DOWNTO 0); SIGNAL mult_ext: STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0); COMPONENT Cell IS PORT( CLK, RST_n, EN : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); SUM_IN: IN STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0); Bi: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); REG_OUT : OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); ADD_OUT: OUT STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0) -- aggiunti 9 bit di guardia ); END COMPONENT; COMPONENT Reg_n IS GENERIC(Nb: INTEGER :=9); PORT( CLK, RST_n, EN: IN STD_LOGIC; DIN: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0) ); END COMPONENT; COMPONENT mult_n IS GENERIC( Nb: INTEGER := 9 ); PORT( in_a: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); in_b: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); mult_out: OUT STD_LOGIC_VECTOR(2*Nb-1 DOWNTO 0) ); END COMPONENT; BEGIN ----------------------------------------------------------- ------------------------ Input Buffers -------------------- In_buffers_1: IF IO_buffers GENERATE VIN_delay_line(0) <= VIN; data_in_reg: Reg_n GENERIC MAP (Nb => Nb) PORT MAP ( CLK => CLK, RST_n => RST_n, EN => VIN, DIN => DIN, DOUT => REG_OUT_array(0) ); Coeffs_in_reg: Reg_n GENERIC MAP (Nb => ((Ord+1)*Nb)) PORT MAP ( CLK => CLK, RST_n => RST_n, EN => VIN, DIN => Coeffs, DOUT => Coeffs_delayed ); VIN_in_reg: Reg_n GENERIC MAP (Nb => 1) PORT MAP ( CLK => CLK, RST_n => RST_n, EN => '1', DIN => VIN_delay_line(0 DOWNTO 0), DOUT => VIN_delay_line(1 DOWNTO 1) ); END GENERATE; In_buffers_0: IF NOT(IO_buffers) GENERATE Coeffs_delayed <= Coeffs; REG_OUT_array(0) <= DIN; VIN_delay_line(1) <= VIN; END GENERATE; -------------------------------------------------------------- ------------------------ First Multiplier -------------------- Coeff_gen: FOR i IN 0 to Ord GENERATE Bi(i) <= Coeffs_delayed(((i+1)*Nb)-1 DOWNTO (i*Nb)); END GENERATE; DIN_mult_gen: mult_n GENERIC MAP(Nb => Nb) PORT MAP ( in_a => REG_OUT_array(0), in_b => Bi(0), mult_out => DIN_mult ); DIN_mult_extension_0: IF (Nbadder <= Nbmult) GENERATE mult_ext <= DIN_mult((DIN_mult'LENGTH - (Nbmult - Nbadder) -1) DOWNTO (DIN_mult'LENGTH)-1-(Nbmult-1)); END GENERATE; DIN_mult_extension_1: IF (Nbadder > Nbmult) GENERATE mult_ext(Nbmult-1 DOWNTO 0)<= DIN_mult((DIN_mult'LENGTH -1) DOWNTO ((DIN_mult'LENGTH)-1-(Nbmult-1)) ); mult_ext(Nbadder-1 DOWNTO Nbmult) <= (OTHERS => mult_ext(Nbmult-1)); END GENERATE; SUM_OUT_array(0) <= mult_ext; ------------------------------------------------------------- ------------------------ Matrix of Cells -------------------- Cells_gen: FOR j IN 0 to Ord-1 GENERATE Single_cell: Cell PORT MAP ( CLK => CLK, RST_n => RST_n, EN => VIN_delay_line(1), DIN => REG_OUT_array(j), SUM_IN => SUM_OUT_array(j), Bi => Bi(j+1), REG_OUT => REG_OUT_array(j+1), ADD_OUT => SUM_OUT_array(j+1) ); END GENERATE; ----------------------------------------------------------- ----------------------- Output Buffers -------------------- Out_buffers_1: IF IO_buffers GENERATE data_out_reg: Reg_n GENERIC MAP (Nb => Nb) PORT MAP ( CLK => CLK, RST_n => RST_n, EN => VIN_delay_line(1), DIN => SUM_OUT_array(Ord)(Nb-1 DOWNTO 0), DOUT => DOUT ); VIN_out_reg: Reg_n GENERIC MAP (Nb => 1) PORT MAP ( CLK => CLK, RST_n => RST_n, EN => '1', DIN => VIN_delay_line(1 DOWNTO 1), DOUT => VIN_delay_line(2 DOWNTO 2) ); VOUT <= VIN_delay_line(2); END GENERATE; Out_buffers_0: IF NOT(IO_buffers) GENERATE DOUT <= SUM_OUT_array(Ord)(Nb-1 DOWNTO 0); VOUT <= VIN; END GENERATE; END beh_fir;

gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_status_flags_ss.vhd

9

17955

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gpl-3.0