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// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33
// Digital model of a traffic light
// By Dan Hyde August 10, 1995
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red = off; amber = off; green = off;
$display(" Time green amber red");
$monitor("%3d %b %b %b", $time, green, amber, red);
end
// task to wait for 'tics' positive edge clocks
// before turning light off
task light;
output color;
input [31:0] tics;
begin
repeat(tics) // wait to detect tics positive edges on clock
@(posedge clock);
color = off;
end
endtask
// waveform for clock period of 2 time units
always begin: clock_wave
#1 clock = 0;
#1 clock = 1;
end
always begin: main_process
red = on;
light(red, red_tics); // call task to wait
green = on;
light(green, green_tics);
amber = on;
light(amber, amber_tics);
end
endmodule
|
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33
// Digital model of a traffic light
// By Dan Hyde August 10, 1995
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red = off; amber = off; green = off;
$display(" Time green amber red");
$monitor("%3d %b %b %b", $time, green, amber, red);
end
// task to wait for 'tics' positive edge clocks
// before turning light off
task light;
output color;
input [31:0] tics;
begin
repeat(tics) // wait to detect tics positive edges on clock
@(posedge clock);
color = off;
end
endtask
// waveform for clock period of 2 time units
always begin: clock_wave
#1 clock = 0;
#1 clock = 1;
end
always begin: main_process
red = on;
light(red, red_tics); // call task to wait
green = on;
light(green, green_tics);
amber = on;
light(amber, amber_tics);
end
endmodule
|
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33
// Digital model of a traffic light
// By Dan Hyde August 10, 1995
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red = off; amber = off; green = off;
$display(" Time green amber red");
$monitor("%3d %b %b %b", $time, green, amber, red);
end
// task to wait for 'tics' positive edge clocks
// before turning light off
task light;
output color;
input [31:0] tics;
begin
repeat(tics) // wait to detect tics positive edges on clock
@(posedge clock);
color = off;
end
endtask
// waveform for clock period of 2 time units
always begin: clock_wave
#1 clock = 0;
#1 clock = 1;
end
always begin: main_process
red = on;
light(red, red_tics); // call task to wait
green = on;
light(green, green_tics);
amber = on;
light(amber, amber_tics);
end
endmodule
|
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33
// Digital model of a traffic light
// By Dan Hyde August 10, 1995
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red = off; amber = off; green = off;
$display(" Time green amber red");
$monitor("%3d %b %b %b", $time, green, amber, red);
end
// task to wait for 'tics' positive edge clocks
// before turning light off
task light;
output color;
input [31:0] tics;
begin
repeat(tics) // wait to detect tics positive edges on clock
@(posedge clock);
color = off;
end
endtask
// waveform for clock period of 2 time units
always begin: clock_wave
#1 clock = 0;
#1 clock = 1;
end
always begin: main_process
red = on;
light(red, red_tics); // call task to wait
green = on;
light(green, green_tics);
amber = on;
light(amber, amber_tics);
end
endmodule
|
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33
// Digital model of a traffic light
// By Dan Hyde August 10, 1995
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red = off; amber = off; green = off;
$display(" Time green amber red");
$monitor("%3d %b %b %b", $time, green, amber, red);
end
// task to wait for 'tics' positive edge clocks
// before turning light off
task light;
output color;
input [31:0] tics;
begin
repeat(tics) // wait to detect tics positive edges on clock
@(posedge clock);
color = off;
end
endtask
// waveform for clock period of 2 time units
always begin: clock_wave
#1 clock = 0;
#1 clock = 1;
end
always begin: main_process
red = on;
light(red, red_tics); // call task to wait
green = on;
light(green, green_tics);
amber = on;
light(amber, amber_tics);
end
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: decerr_slave.v
//
// Description:
// Phantom slave interface used to complete W, R and B channel transfers when an
// erroneous transaction is trapped in the crossbar.
//--------------------------------------------------------------------------
//
// Structure:
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_decerr_slave #
(
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_RESP = 2'b11,
parameter integer C_IGNORE_ID = 0
)
(
input wire ACLK,
input wire ARESETN,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
output wire [1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] S_AXI_ARLEN,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
reg s_axi_awready_i;
reg s_axi_wready_i;
reg s_axi_bvalid_i;
reg s_axi_arready_i;
reg s_axi_rvalid_i;
localparam P_WRITE_IDLE = 2'b00;
localparam P_WRITE_DATA = 2'b01;
localparam P_WRITE_RESP = 2'b10;
localparam P_READ_IDLE = 2'b00;
localparam P_READ_START = 2'b01;
localparam P_READ_DATA = 2'b10;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
assign S_AXI_BRESP = C_RESP;
assign S_AXI_RRESP = C_RESP;
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign S_AXI_AWREADY = s_axi_awready_i;
assign S_AXI_WREADY = s_axi_wready_i;
assign S_AXI_BVALID = s_axi_bvalid_i;
assign S_AXI_ARREADY = s_axi_arready_i;
assign S_AXI_RVALID = s_axi_rvalid_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
reg s_axi_rvalid_en;
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BID = 0;
assign S_AXI_RID = 0;
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
end else begin
if (s_axi_bvalid_i) begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
end
end else if (S_AXI_WVALID & s_axi_wready_i) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
end else if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1;
end
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rvalid_en <= 1'b0;
end else begin
if (s_axi_rvalid_i) begin
if (S_AXI_RREADY) begin
s_axi_rvalid_i <= 1'b0;
s_axi_arready_i <= 1'b1;
end
end else if (s_axi_rvalid_en) begin
s_axi_rvalid_en <= 1'b0;
s_axi_rvalid_i <= 1'b1;
end else if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_en <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1;
end
end
end
end else begin : gen_axi
reg s_axi_rlast_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt;
reg [1:0] write_cs;
reg [1:0] read_cs;
assign S_AXI_RLAST = s_axi_rlast_i;
assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i;
assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i;
always @(posedge ACLK) begin
if (~ARESETN) begin
write_cs <= P_WRITE_IDLE;
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
s_axi_bid_i <= 0;
end else begin
case (write_cs)
P_WRITE_IDLE:
begin
if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID;
s_axi_wready_i <= 1'b1;
write_cs <= P_WRITE_DATA;
end else begin
s_axi_awready_i <= 1'b1;
end
end
P_WRITE_DATA:
begin
if (S_AXI_WVALID & S_AXI_WLAST) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
write_cs <= P_WRITE_RESP;
end
end
P_WRITE_RESP:
begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
write_cs <= P_WRITE_IDLE;
end
end
endcase
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
read_cs <= P_READ_IDLE;
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_rid_i <= 0;
read_cnt <= 0;
end else begin
case (read_cs)
P_READ_IDLE:
begin
if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID;
read_cnt <= S_AXI_ARLEN;
s_axi_rlast_i <= (S_AXI_ARLEN == 0);
read_cs <= P_READ_START;
end else begin
s_axi_arready_i <= 1'b1;
end
end
P_READ_START:
begin
s_axi_rvalid_i <= 1'b1;
read_cs <= P_READ_DATA;
end
P_READ_DATA:
begin
if (S_AXI_RREADY) begin
if (read_cnt == 0) begin
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_arready_i <= 1'b1;
read_cs <= P_READ_IDLE;
end else begin
if (read_cnt == 1) begin
s_axi_rlast_i <= 1'b1;
end
read_cnt <= read_cnt - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule
`default_nettype wire
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: decerr_slave.v
//
// Description:
// Phantom slave interface used to complete W, R and B channel transfers when an
// erroneous transaction is trapped in the crossbar.
//--------------------------------------------------------------------------
//
// Structure:
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_decerr_slave #
(
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_RESP = 2'b11,
parameter integer C_IGNORE_ID = 0
)
(
input wire ACLK,
input wire ARESETN,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
output wire [1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] S_AXI_ARLEN,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
reg s_axi_awready_i;
reg s_axi_wready_i;
reg s_axi_bvalid_i;
reg s_axi_arready_i;
reg s_axi_rvalid_i;
localparam P_WRITE_IDLE = 2'b00;
localparam P_WRITE_DATA = 2'b01;
localparam P_WRITE_RESP = 2'b10;
localparam P_READ_IDLE = 2'b00;
localparam P_READ_START = 2'b01;
localparam P_READ_DATA = 2'b10;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
assign S_AXI_BRESP = C_RESP;
assign S_AXI_RRESP = C_RESP;
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign S_AXI_AWREADY = s_axi_awready_i;
assign S_AXI_WREADY = s_axi_wready_i;
assign S_AXI_BVALID = s_axi_bvalid_i;
assign S_AXI_ARREADY = s_axi_arready_i;
assign S_AXI_RVALID = s_axi_rvalid_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
reg s_axi_rvalid_en;
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BID = 0;
assign S_AXI_RID = 0;
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
end else begin
if (s_axi_bvalid_i) begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
end
end else if (S_AXI_WVALID & s_axi_wready_i) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
end else if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1;
end
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rvalid_en <= 1'b0;
end else begin
if (s_axi_rvalid_i) begin
if (S_AXI_RREADY) begin
s_axi_rvalid_i <= 1'b0;
s_axi_arready_i <= 1'b1;
end
end else if (s_axi_rvalid_en) begin
s_axi_rvalid_en <= 1'b0;
s_axi_rvalid_i <= 1'b1;
end else if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_en <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1;
end
end
end
end else begin : gen_axi
reg s_axi_rlast_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt;
reg [1:0] write_cs;
reg [1:0] read_cs;
assign S_AXI_RLAST = s_axi_rlast_i;
assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i;
assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i;
always @(posedge ACLK) begin
if (~ARESETN) begin
write_cs <= P_WRITE_IDLE;
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
s_axi_bid_i <= 0;
end else begin
case (write_cs)
P_WRITE_IDLE:
begin
if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID;
s_axi_wready_i <= 1'b1;
write_cs <= P_WRITE_DATA;
end else begin
s_axi_awready_i <= 1'b1;
end
end
P_WRITE_DATA:
begin
if (S_AXI_WVALID & S_AXI_WLAST) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
write_cs <= P_WRITE_RESP;
end
end
P_WRITE_RESP:
begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
write_cs <= P_WRITE_IDLE;
end
end
endcase
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
read_cs <= P_READ_IDLE;
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_rid_i <= 0;
read_cnt <= 0;
end else begin
case (read_cs)
P_READ_IDLE:
begin
if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID;
read_cnt <= S_AXI_ARLEN;
s_axi_rlast_i <= (S_AXI_ARLEN == 0);
read_cs <= P_READ_START;
end else begin
s_axi_arready_i <= 1'b1;
end
end
P_READ_START:
begin
s_axi_rvalid_i <= 1'b1;
read_cs <= P_READ_DATA;
end
P_READ_DATA:
begin
if (S_AXI_RREADY) begin
if (read_cnt == 0) begin
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_arready_i <= 1'b1;
read_cs <= P_READ_IDLE;
end else begin
if (read_cnt == 1) begin
s_axi_rlast_i <= 1'b1;
end
read_cnt <= read_cnt - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule
`default_nettype wire
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: decerr_slave.v
//
// Description:
// Phantom slave interface used to complete W, R and B channel transfers when an
// erroneous transaction is trapped in the crossbar.
//--------------------------------------------------------------------------
//
// Structure:
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_decerr_slave #
(
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_RESP = 2'b11,
parameter integer C_IGNORE_ID = 0
)
(
input wire ACLK,
input wire ARESETN,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
output wire [1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] S_AXI_ARLEN,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
reg s_axi_awready_i;
reg s_axi_wready_i;
reg s_axi_bvalid_i;
reg s_axi_arready_i;
reg s_axi_rvalid_i;
localparam P_WRITE_IDLE = 2'b00;
localparam P_WRITE_DATA = 2'b01;
localparam P_WRITE_RESP = 2'b10;
localparam P_READ_IDLE = 2'b00;
localparam P_READ_START = 2'b01;
localparam P_READ_DATA = 2'b10;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
assign S_AXI_BRESP = C_RESP;
assign S_AXI_RRESP = C_RESP;
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign S_AXI_AWREADY = s_axi_awready_i;
assign S_AXI_WREADY = s_axi_wready_i;
assign S_AXI_BVALID = s_axi_bvalid_i;
assign S_AXI_ARREADY = s_axi_arready_i;
assign S_AXI_RVALID = s_axi_rvalid_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
reg s_axi_rvalid_en;
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BID = 0;
assign S_AXI_RID = 0;
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
end else begin
if (s_axi_bvalid_i) begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
end
end else if (S_AXI_WVALID & s_axi_wready_i) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
end else if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1;
end
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rvalid_en <= 1'b0;
end else begin
if (s_axi_rvalid_i) begin
if (S_AXI_RREADY) begin
s_axi_rvalid_i <= 1'b0;
s_axi_arready_i <= 1'b1;
end
end else if (s_axi_rvalid_en) begin
s_axi_rvalid_en <= 1'b0;
s_axi_rvalid_i <= 1'b1;
end else if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_en <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1;
end
end
end
end else begin : gen_axi
reg s_axi_rlast_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt;
reg [1:0] write_cs;
reg [1:0] read_cs;
assign S_AXI_RLAST = s_axi_rlast_i;
assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i;
assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i;
always @(posedge ACLK) begin
if (~ARESETN) begin
write_cs <= P_WRITE_IDLE;
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
s_axi_bid_i <= 0;
end else begin
case (write_cs)
P_WRITE_IDLE:
begin
if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID;
s_axi_wready_i <= 1'b1;
write_cs <= P_WRITE_DATA;
end else begin
s_axi_awready_i <= 1'b1;
end
end
P_WRITE_DATA:
begin
if (S_AXI_WVALID & S_AXI_WLAST) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
write_cs <= P_WRITE_RESP;
end
end
P_WRITE_RESP:
begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
write_cs <= P_WRITE_IDLE;
end
end
endcase
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
read_cs <= P_READ_IDLE;
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_rid_i <= 0;
read_cnt <= 0;
end else begin
case (read_cs)
P_READ_IDLE:
begin
if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID;
read_cnt <= S_AXI_ARLEN;
s_axi_rlast_i <= (S_AXI_ARLEN == 0);
read_cs <= P_READ_START;
end else begin
s_axi_arready_i <= 1'b1;
end
end
P_READ_START:
begin
s_axi_rvalid_i <= 1'b1;
read_cs <= P_READ_DATA;
end
P_READ_DATA:
begin
if (S_AXI_RREADY) begin
if (read_cnt == 0) begin
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_arready_i <= 1'b1;
read_cs <= P_READ_IDLE;
end else begin
if (read_cnt == 1) begin
s_axi_rlast_i <= 1'b1;
end
read_cnt <= read_cnt - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule
`default_nettype wire
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: decerr_slave.v
//
// Description:
// Phantom slave interface used to complete W, R and B channel transfers when an
// erroneous transaction is trapped in the crossbar.
//--------------------------------------------------------------------------
//
// Structure:
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_decerr_slave #
(
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_RESP = 2'b11,
parameter integer C_IGNORE_ID = 0
)
(
input wire ACLK,
input wire ARESETN,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
output wire [1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] S_AXI_ARLEN,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
reg s_axi_awready_i;
reg s_axi_wready_i;
reg s_axi_bvalid_i;
reg s_axi_arready_i;
reg s_axi_rvalid_i;
localparam P_WRITE_IDLE = 2'b00;
localparam P_WRITE_DATA = 2'b01;
localparam P_WRITE_RESP = 2'b10;
localparam P_READ_IDLE = 2'b00;
localparam P_READ_START = 2'b01;
localparam P_READ_DATA = 2'b10;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
assign S_AXI_BRESP = C_RESP;
assign S_AXI_RRESP = C_RESP;
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign S_AXI_AWREADY = s_axi_awready_i;
assign S_AXI_WREADY = s_axi_wready_i;
assign S_AXI_BVALID = s_axi_bvalid_i;
assign S_AXI_ARREADY = s_axi_arready_i;
assign S_AXI_RVALID = s_axi_rvalid_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
reg s_axi_rvalid_en;
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BID = 0;
assign S_AXI_RID = 0;
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
end else begin
if (s_axi_bvalid_i) begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
end
end else if (S_AXI_WVALID & s_axi_wready_i) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
end else if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1;
end
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rvalid_en <= 1'b0;
end else begin
if (s_axi_rvalid_i) begin
if (S_AXI_RREADY) begin
s_axi_rvalid_i <= 1'b0;
s_axi_arready_i <= 1'b1;
end
end else if (s_axi_rvalid_en) begin
s_axi_rvalid_en <= 1'b0;
s_axi_rvalid_i <= 1'b1;
end else if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_en <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1;
end
end
end
end else begin : gen_axi
reg s_axi_rlast_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt;
reg [1:0] write_cs;
reg [1:0] read_cs;
assign S_AXI_RLAST = s_axi_rlast_i;
assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i;
assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i;
always @(posedge ACLK) begin
if (~ARESETN) begin
write_cs <= P_WRITE_IDLE;
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
s_axi_bid_i <= 0;
end else begin
case (write_cs)
P_WRITE_IDLE:
begin
if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID;
s_axi_wready_i <= 1'b1;
write_cs <= P_WRITE_DATA;
end else begin
s_axi_awready_i <= 1'b1;
end
end
P_WRITE_DATA:
begin
if (S_AXI_WVALID & S_AXI_WLAST) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
write_cs <= P_WRITE_RESP;
end
end
P_WRITE_RESP:
begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
write_cs <= P_WRITE_IDLE;
end
end
endcase
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
read_cs <= P_READ_IDLE;
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_rid_i <= 0;
read_cnt <= 0;
end else begin
case (read_cs)
P_READ_IDLE:
begin
if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID;
read_cnt <= S_AXI_ARLEN;
s_axi_rlast_i <= (S_AXI_ARLEN == 0);
read_cs <= P_READ_START;
end else begin
s_axi_arready_i <= 1'b1;
end
end
P_READ_START:
begin
s_axi_rvalid_i <= 1'b1;
read_cs <= P_READ_DATA;
end
P_READ_DATA:
begin
if (S_AXI_RREADY) begin
if (read_cnt == 0) begin
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_arready_i <= 1'b1;
read_cs <= P_READ_IDLE;
end else begin
if (read_cnt == 1) begin
s_axi_rlast_i <= 1'b1;
end
read_cnt <= read_cnt - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule
`default_nettype wire
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data AXI3 Slave Converter
// Forward and split transactions as required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_w_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
input wire [4-1:0] cmd_length,
output wire cmd_ready,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Burst length handling.
reg first_mi_word;
reg [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
wire last_beat;
wire last_word;
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Internal SI side control signals.
wire S_AXI_WREADY_I;
// Internal signals for MI-side.
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID_I;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I;
wire M_AXI_WLAST_I;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I;
wire M_AXI_WVALID_I;
wire M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from SI-Side to MI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling;
assign S_AXI_WREADY = S_AXI_WREADY_I;
// Indicate when there is data available @ MI-side.
assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid;
// Get MI-side data.
assign pop_mi_data = M_AXI_WVALID_I & M_AXI_WREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = M_AXI_WVALID_I & ~M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data forwarding:
//
// On the first cycle of the transaction is the length taken from the Command
// FIFO. The length is decreased until 0 is reached which indicates last data
// word.
//
// If bursts are unsupported will all data words be the last word, each one
// from a separate transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word <= 1'b1;
length_counter_1 <= 4'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_WLAST_I ) begin
first_mi_word <= 1'b1;
end else begin
first_mi_word <= 1'b0;
end
length_counter_1 <= next_length_counter;
end
end
end
// Detect last beat in a burst.
assign last_beat = ( length_counter == 4'b0 );
// Determine if this last word that shall be extracted from this SI-side word.
assign last_word = ( last_beat ) |
( C_SUPPORT_BURSTS == 0 );
/////////////////////////////////////////////////////////////////////////////
// Select the SI-side word to write.
//
// Most information can be reused directly (DATA, STRB, ID and USER).
// ID is taken from the Command FIFO.
//
// Split transactions needs to insert new LAST transactions. So to simplify
// is the LAST signal always generated.
//
/////////////////////////////////////////////////////////////////////////////
// ID and USER is copied from the SI word to all MI word transactions.
assign M_AXI_WUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1'b0}};
// Data has to be multiplexed.
assign M_AXI_WDATA_I = S_AXI_WDATA;
assign M_AXI_WSTRB_I = S_AXI_WSTRB;
// ID is taken directly from the command queue.
assign M_AXI_WID_I = cmd_id;
// Handle last flag, i.e. set for MI-side last word.
assign M_AXI_WLAST_I = last_word;
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign M_AXI_WID = M_AXI_WID_I;
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_I;
assign M_AXI_WUSER = M_AXI_WUSER_I;
assign M_AXI_WVALID = M_AXI_WVALID_I;
assign M_AXI_WREADY_I = M_AXI_WREADY;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data AXI3 Slave Converter
// Forward and split transactions as required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_w_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
input wire [4-1:0] cmd_length,
output wire cmd_ready,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Burst length handling.
reg first_mi_word;
reg [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
wire last_beat;
wire last_word;
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Internal SI side control signals.
wire S_AXI_WREADY_I;
// Internal signals for MI-side.
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID_I;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I;
wire M_AXI_WLAST_I;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I;
wire M_AXI_WVALID_I;
wire M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from SI-Side to MI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling;
assign S_AXI_WREADY = S_AXI_WREADY_I;
// Indicate when there is data available @ MI-side.
assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid;
// Get MI-side data.
assign pop_mi_data = M_AXI_WVALID_I & M_AXI_WREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = M_AXI_WVALID_I & ~M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data forwarding:
//
// On the first cycle of the transaction is the length taken from the Command
// FIFO. The length is decreased until 0 is reached which indicates last data
// word.
//
// If bursts are unsupported will all data words be the last word, each one
// from a separate transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word <= 1'b1;
length_counter_1 <= 4'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_WLAST_I ) begin
first_mi_word <= 1'b1;
end else begin
first_mi_word <= 1'b0;
end
length_counter_1 <= next_length_counter;
end
end
end
// Detect last beat in a burst.
assign last_beat = ( length_counter == 4'b0 );
// Determine if this last word that shall be extracted from this SI-side word.
assign last_word = ( last_beat ) |
( C_SUPPORT_BURSTS == 0 );
/////////////////////////////////////////////////////////////////////////////
// Select the SI-side word to write.
//
// Most information can be reused directly (DATA, STRB, ID and USER).
// ID is taken from the Command FIFO.
//
// Split transactions needs to insert new LAST transactions. So to simplify
// is the LAST signal always generated.
//
/////////////////////////////////////////////////////////////////////////////
// ID and USER is copied from the SI word to all MI word transactions.
assign M_AXI_WUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1'b0}};
// Data has to be multiplexed.
assign M_AXI_WDATA_I = S_AXI_WDATA;
assign M_AXI_WSTRB_I = S_AXI_WSTRB;
// ID is taken directly from the command queue.
assign M_AXI_WID_I = cmd_id;
// Handle last flag, i.e. set for MI-side last word.
assign M_AXI_WLAST_I = last_word;
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign M_AXI_WID = M_AXI_WID_I;
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_I;
assign M_AXI_WUSER = M_AXI_WUSER_I;
assign M_AXI_WVALID = M_AXI_WVALID_I;
assign M_AXI_WREADY_I = M_AXI_WREADY;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data AXI3 Slave Converter
// Forward and split transactions as required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_w_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
input wire [4-1:0] cmd_length,
output wire cmd_ready,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Burst length handling.
reg first_mi_word;
reg [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
wire last_beat;
wire last_word;
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Internal SI side control signals.
wire S_AXI_WREADY_I;
// Internal signals for MI-side.
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID_I;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I;
wire M_AXI_WLAST_I;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I;
wire M_AXI_WVALID_I;
wire M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from SI-Side to MI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling;
assign S_AXI_WREADY = S_AXI_WREADY_I;
// Indicate when there is data available @ MI-side.
assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid;
// Get MI-side data.
assign pop_mi_data = M_AXI_WVALID_I & M_AXI_WREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = M_AXI_WVALID_I & ~M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data forwarding:
//
// On the first cycle of the transaction is the length taken from the Command
// FIFO. The length is decreased until 0 is reached which indicates last data
// word.
//
// If bursts are unsupported will all data words be the last word, each one
// from a separate transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word <= 1'b1;
length_counter_1 <= 4'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_WLAST_I ) begin
first_mi_word <= 1'b1;
end else begin
first_mi_word <= 1'b0;
end
length_counter_1 <= next_length_counter;
end
end
end
// Detect last beat in a burst.
assign last_beat = ( length_counter == 4'b0 );
// Determine if this last word that shall be extracted from this SI-side word.
assign last_word = ( last_beat ) |
( C_SUPPORT_BURSTS == 0 );
/////////////////////////////////////////////////////////////////////////////
// Select the SI-side word to write.
//
// Most information can be reused directly (DATA, STRB, ID and USER).
// ID is taken from the Command FIFO.
//
// Split transactions needs to insert new LAST transactions. So to simplify
// is the LAST signal always generated.
//
/////////////////////////////////////////////////////////////////////////////
// ID and USER is copied from the SI word to all MI word transactions.
assign M_AXI_WUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1'b0}};
// Data has to be multiplexed.
assign M_AXI_WDATA_I = S_AXI_WDATA;
assign M_AXI_WSTRB_I = S_AXI_WSTRB;
// ID is taken directly from the command queue.
assign M_AXI_WID_I = cmd_id;
// Handle last flag, i.e. set for MI-side last word.
assign M_AXI_WLAST_I = last_word;
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign M_AXI_WID = M_AXI_WID_I;
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_I;
assign M_AXI_WUSER = M_AXI_WUSER_I;
assign M_AXI_WVALID = M_AXI_WVALID_I;
assign M_AXI_WREADY_I = M_AXI_WREADY;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data AXI3 Slave Converter
// Forward and split transactions as required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_w_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
input wire [4-1:0] cmd_length,
output wire cmd_ready,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Burst length handling.
reg first_mi_word;
reg [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
wire last_beat;
wire last_word;
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Internal SI side control signals.
wire S_AXI_WREADY_I;
// Internal signals for MI-side.
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID_I;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I;
wire M_AXI_WLAST_I;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I;
wire M_AXI_WVALID_I;
wire M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from SI-Side to MI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling;
assign S_AXI_WREADY = S_AXI_WREADY_I;
// Indicate when there is data available @ MI-side.
assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid;
// Get MI-side data.
assign pop_mi_data = M_AXI_WVALID_I & M_AXI_WREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = M_AXI_WVALID_I & ~M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data forwarding:
//
// On the first cycle of the transaction is the length taken from the Command
// FIFO. The length is decreased until 0 is reached which indicates last data
// word.
//
// If bursts are unsupported will all data words be the last word, each one
// from a separate transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word <= 1'b1;
length_counter_1 <= 4'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_WLAST_I ) begin
first_mi_word <= 1'b1;
end else begin
first_mi_word <= 1'b0;
end
length_counter_1 <= next_length_counter;
end
end
end
// Detect last beat in a burst.
assign last_beat = ( length_counter == 4'b0 );
// Determine if this last word that shall be extracted from this SI-side word.
assign last_word = ( last_beat ) |
( C_SUPPORT_BURSTS == 0 );
/////////////////////////////////////////////////////////////////////////////
// Select the SI-side word to write.
//
// Most information can be reused directly (DATA, STRB, ID and USER).
// ID is taken from the Command FIFO.
//
// Split transactions needs to insert new LAST transactions. So to simplify
// is the LAST signal always generated.
//
/////////////////////////////////////////////////////////////////////////////
// ID and USER is copied from the SI word to all MI word transactions.
assign M_AXI_WUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1'b0}};
// Data has to be multiplexed.
assign M_AXI_WDATA_I = S_AXI_WDATA;
assign M_AXI_WSTRB_I = S_AXI_WSTRB;
// ID is taken directly from the command queue.
assign M_AXI_WID_I = cmd_id;
// Handle last flag, i.e. set for MI-side last word.
assign M_AXI_WLAST_I = last_word;
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign M_AXI_WID = M_AXI_WID_I;
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_I;
assign M_AXI_WUSER = M_AXI_WUSER_I;
assign M_AXI_WVALID = M_AXI_WVALID_I;
assign M_AXI_WREADY_I = M_AXI_WREADY;
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes switch and button inputs with a slow sampled shift register
*/
module debounce_switch #(
parameter WIDTH=1, // width of the input and output signals
parameter N=3, // length of shift register
parameter RATE=125000 // clock division factor
)(
input wire clk,
input wire rst,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [23:0] cnt_reg = 24'd0;
reg [N-1:0] debounce_reg[WIDTH-1:0];
reg [WIDTH-1:0] state;
/*
* The synchronized output is the state register
*/
assign out = state;
integer k;
always @(posedge clk or posedge rst) begin
if (rst) begin
cnt_reg <= 0;
state <= 0;
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= 0;
end
end else begin
if (cnt_reg < RATE) begin
cnt_reg <= cnt_reg + 24'd1;
end else begin
cnt_reg <= 24'd0;
end
if (cnt_reg == 24'd0) begin
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
end
end
for (k = 0; k < WIDTH; k = k + 1) begin
if (|debounce_reg[k] == 0) begin
state[k] <= 0;
end else if (&debounce_reg[k] == 1) begin
state[k] <= 1;
end else begin
state[k] <= state[k];
end
end
end
end
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes switch and button inputs with a slow sampled shift register
*/
module debounce_switch #(
parameter WIDTH=1, // width of the input and output signals
parameter N=3, // length of shift register
parameter RATE=125000 // clock division factor
)(
input wire clk,
input wire rst,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [23:0] cnt_reg = 24'd0;
reg [N-1:0] debounce_reg[WIDTH-1:0];
reg [WIDTH-1:0] state;
/*
* The synchronized output is the state register
*/
assign out = state;
integer k;
always @(posedge clk or posedge rst) begin
if (rst) begin
cnt_reg <= 0;
state <= 0;
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= 0;
end
end else begin
if (cnt_reg < RATE) begin
cnt_reg <= cnt_reg + 24'd1;
end else begin
cnt_reg <= 24'd0;
end
if (cnt_reg == 24'd0) begin
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
end
end
for (k = 0; k < WIDTH; k = k + 1) begin
if (|debounce_reg[k] == 0) begin
state[k] <= 0;
end else if (&debounce_reg[k] == 1) begin
state[k] <= 1;
end else begin
state[k] <= state[k];
end
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/12/2016 06:26:54 PM
// Design Name:
// Module Name: shift_mux_array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shift_mux_array
#(parameter SWR=26, parameter LEVEL=5)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
genvar j;
generate for (j=0; j<=SWR-1 ; j=j+1) begin
localparam sh=(2**LEVEL)+j; //value for second mux input. It changes in exponentation by 2 for each level
case (sh>SWR-1)
1'b1:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (bit_shift_i),
.S (Data_o[j])
);
end
1'b0:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (Data_i[sh]),
.S (Data_o[j])
);
end
endcase
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/12/2016 06:26:54 PM
// Design Name:
// Module Name: shift_mux_array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shift_mux_array
#(parameter SWR=26, parameter LEVEL=5)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
genvar j;
generate for (j=0; j<=SWR-1 ; j=j+1) begin
localparam sh=(2**LEVEL)+j; //value for second mux input. It changes in exponentation by 2 for each level
case (sh>SWR-1)
1'b1:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (bit_shift_i),
.S (Data_o[j])
);
end
1'b0:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (Data_i[sh]),
.S (Data_o[j])
);
end
endcase
end
endgenerate
endmodule
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, quadA, quadB, quadZ, up, down);
parameter QW=14;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
wire do_tristate;
reg[9:0] real_dout; output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout;
input [7:0] din;
input [3:0] quadA;
input [3:0] quadB;
input [3:0] quadZ;
wire[3:0] real_up; output [3:0] up = do_tristate ? 4'bZZZZ : real_up;
wire[3:0] real_down; output [3:0] down = do_tristate ? 4'bZZZZ : real_down;
reg Zpolarity;
wire [2*QW:0] quad0, quad1, quad2, quad3;
wire do_enable_wdt;
wire pwm_at_top;
wdt w(clk, do_enable_wdt, pwm_at_top, do_tristate);
// PWM stuff
// PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt
reg [10:0] pwmcnt;
wire [10:0] top = 11'd2046;
assign pwm_at_top = (pwmcnt == top);
reg [15:0] pwm0, pwm1, pwm2, pwm3;
always @(posedge clk) begin
if(pwm_at_top) pwmcnt <= 0;
else pwmcnt <= pwmcnt + 11'd1;
end
wire [10:0] pwmrev = {
pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9],
pwmcnt[10], pwmcnt[3:0]};
wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt;
wire pwmact0 = pwm0[10:0] > pwmcmp0;
wire pwmact1 = pwm1[10:0] > pwmcmp0;
wire pwmact2 = pwm2[10:0] > pwmcmp0;
wire pwmact3 = pwm3[10:0] > pwmcmp0;
assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0);
assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1);
assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2);
assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3);
assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0);
assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1);
assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2);
assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3);
// Quadrature stuff
// Quadrature is digitized at 40MHz into 14-bit counters
// Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period
reg qtest;
wire qr0, qr1, qr2, qr3;
quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0);
quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1);
quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2);
quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3);
// EPP stuff
wire EPP_write = ~nWrite;
wire EPP_read = nWrite;
wire EPP_addr_strobe = ~nAddrStr;
wire EPP_data_strobe = ~nDataStr;
wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe;
wire EPP_wait; assign nWait = ~EPP_wait;
wire [7:0] EPP_datain = pport_data;
wire [7:0] EPP_dataout; assign pport_data = EPP_dataout;
reg [4:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe};
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
// reg led;
assign EPP_wait = EPP_strobe_reg[4];
reg[4:0] addr_reg;
reg[7:0] lowbyte;
always @(posedge clk)
if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin
addr_reg <= EPP_datain[4:0];
end
else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin
if(addr_reg[3:0] == 4'd1) pwm0 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd3) pwm1 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd5) pwm2 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd7) pwm3 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd9) begin
real_dout <= { EPP_datain[1:0], lowbyte };
Zpolarity <= EPP_datain[7];
qtest <= EPP_datain[5];
end
else lowbyte <= EPP_datain;
end
end
reg [31:0] data_buf;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin
if(addr_reg[4:2] == 3'd0) data_buf <= quad0;
else if(addr_reg[4:2] == 3'd1) data_buf <= quad1;
else if(addr_reg[4:2] == 3'd2) data_buf <= quad2;
else if(addr_reg[4:2] == 3'd3) data_buf <= quad3;
else if(addr_reg[4:2] == 3'd4)
data_buf <= {quadA, quadB, quadZ, din};
end
end
// the addr_reg test looks funny because it is auto-incremented in an always
// block so "1" reads the low byte, "2 and "3" read middle bytes, and "0"
// reads the high byte I have a feeling that I'm doing this in the wrong way.
wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] :
(addr_reg[1:0] == 2'd2 ? data_buf[15:8] :
(addr_reg[1:0] == 2'd3 ? data_buf[23:16] :
data_buf[31:24]));
wire [7:0] EPP_data_mux = data_reg;
assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ;
assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
assign qr0 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd0);
assign qr1 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd1);
assign qr2 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd2);
assign qr3 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd3);
assign led = do_tristate ? 1'BZ : (real_up[0] ^ real_down[0]);
assign nConfig = epp_nReset; // 1'b1;
endmodule
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, quadA, quadB, quadZ, up, down);
parameter QW=14;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
wire do_tristate;
reg[9:0] real_dout; output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout;
input [7:0] din;
input [3:0] quadA;
input [3:0] quadB;
input [3:0] quadZ;
wire[3:0] real_up; output [3:0] up = do_tristate ? 4'bZZZZ : real_up;
wire[3:0] real_down; output [3:0] down = do_tristate ? 4'bZZZZ : real_down;
reg Zpolarity;
wire [2*QW:0] quad0, quad1, quad2, quad3;
wire do_enable_wdt;
wire pwm_at_top;
wdt w(clk, do_enable_wdt, pwm_at_top, do_tristate);
// PWM stuff
// PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt
reg [10:0] pwmcnt;
wire [10:0] top = 11'd2046;
assign pwm_at_top = (pwmcnt == top);
reg [15:0] pwm0, pwm1, pwm2, pwm3;
always @(posedge clk) begin
if(pwm_at_top) pwmcnt <= 0;
else pwmcnt <= pwmcnt + 11'd1;
end
wire [10:0] pwmrev = {
pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9],
pwmcnt[10], pwmcnt[3:0]};
wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt;
wire pwmact0 = pwm0[10:0] > pwmcmp0;
wire pwmact1 = pwm1[10:0] > pwmcmp0;
wire pwmact2 = pwm2[10:0] > pwmcmp0;
wire pwmact3 = pwm3[10:0] > pwmcmp0;
assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0);
assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1);
assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2);
assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3);
assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0);
assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1);
assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2);
assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3);
// Quadrature stuff
// Quadrature is digitized at 40MHz into 14-bit counters
// Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period
reg qtest;
wire qr0, qr1, qr2, qr3;
quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0);
quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1);
quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2);
quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3);
// EPP stuff
wire EPP_write = ~nWrite;
wire EPP_read = nWrite;
wire EPP_addr_strobe = ~nAddrStr;
wire EPP_data_strobe = ~nDataStr;
wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe;
wire EPP_wait; assign nWait = ~EPP_wait;
wire [7:0] EPP_datain = pport_data;
wire [7:0] EPP_dataout; assign pport_data = EPP_dataout;
reg [4:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe};
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
// reg led;
assign EPP_wait = EPP_strobe_reg[4];
reg[4:0] addr_reg;
reg[7:0] lowbyte;
always @(posedge clk)
if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin
addr_reg <= EPP_datain[4:0];
end
else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin
if(addr_reg[3:0] == 4'd1) pwm0 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd3) pwm1 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd5) pwm2 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd7) pwm3 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd9) begin
real_dout <= { EPP_datain[1:0], lowbyte };
Zpolarity <= EPP_datain[7];
qtest <= EPP_datain[5];
end
else lowbyte <= EPP_datain;
end
end
reg [31:0] data_buf;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin
if(addr_reg[4:2] == 3'd0) data_buf <= quad0;
else if(addr_reg[4:2] == 3'd1) data_buf <= quad1;
else if(addr_reg[4:2] == 3'd2) data_buf <= quad2;
else if(addr_reg[4:2] == 3'd3) data_buf <= quad3;
else if(addr_reg[4:2] == 3'd4)
data_buf <= {quadA, quadB, quadZ, din};
end
end
// the addr_reg test looks funny because it is auto-incremented in an always
// block so "1" reads the low byte, "2 and "3" read middle bytes, and "0"
// reads the high byte I have a feeling that I'm doing this in the wrong way.
wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] :
(addr_reg[1:0] == 2'd2 ? data_buf[15:8] :
(addr_reg[1:0] == 2'd3 ? data_buf[23:16] :
data_buf[31:24]));
wire [7:0] EPP_data_mux = data_reg;
assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ;
assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
assign qr0 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd0);
assign qr1 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd1);
assign qr2 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd2);
assign qr3 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd3);
assign led = do_tristate ? 1'BZ : (real_up[0] ^ real_down[0]);
assign nConfig = epp_nReset; // 1'b1;
endmodule
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, quadA, quadB, quadZ, up, down);
parameter QW=14;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
wire do_tristate;
reg[9:0] real_dout; output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout;
input [7:0] din;
input [3:0] quadA;
input [3:0] quadB;
input [3:0] quadZ;
wire[3:0] real_up; output [3:0] up = do_tristate ? 4'bZZZZ : real_up;
wire[3:0] real_down; output [3:0] down = do_tristate ? 4'bZZZZ : real_down;
reg Zpolarity;
wire [2*QW:0] quad0, quad1, quad2, quad3;
wire do_enable_wdt;
wire pwm_at_top;
wdt w(clk, do_enable_wdt, pwm_at_top, do_tristate);
// PWM stuff
// PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt
reg [10:0] pwmcnt;
wire [10:0] top = 11'd2046;
assign pwm_at_top = (pwmcnt == top);
reg [15:0] pwm0, pwm1, pwm2, pwm3;
always @(posedge clk) begin
if(pwm_at_top) pwmcnt <= 0;
else pwmcnt <= pwmcnt + 11'd1;
end
wire [10:0] pwmrev = {
pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9],
pwmcnt[10], pwmcnt[3:0]};
wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt;
wire pwmact0 = pwm0[10:0] > pwmcmp0;
wire pwmact1 = pwm1[10:0] > pwmcmp0;
wire pwmact2 = pwm2[10:0] > pwmcmp0;
wire pwmact3 = pwm3[10:0] > pwmcmp0;
assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0);
assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1);
assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2);
assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3);
assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0);
assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1);
assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2);
assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3);
// Quadrature stuff
// Quadrature is digitized at 40MHz into 14-bit counters
// Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period
reg qtest;
wire qr0, qr1, qr2, qr3;
quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0);
quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1);
quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2);
quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3);
// EPP stuff
wire EPP_write = ~nWrite;
wire EPP_read = nWrite;
wire EPP_addr_strobe = ~nAddrStr;
wire EPP_data_strobe = ~nDataStr;
wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe;
wire EPP_wait; assign nWait = ~EPP_wait;
wire [7:0] EPP_datain = pport_data;
wire [7:0] EPP_dataout; assign pport_data = EPP_dataout;
reg [4:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe};
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
// reg led;
assign EPP_wait = EPP_strobe_reg[4];
reg[4:0] addr_reg;
reg[7:0] lowbyte;
always @(posedge clk)
if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin
addr_reg <= EPP_datain[4:0];
end
else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin
if(addr_reg[3:0] == 4'd1) pwm0 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd3) pwm1 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd5) pwm2 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd7) pwm3 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd9) begin
real_dout <= { EPP_datain[1:0], lowbyte };
Zpolarity <= EPP_datain[7];
qtest <= EPP_datain[5];
end
else lowbyte <= EPP_datain;
end
end
reg [31:0] data_buf;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin
if(addr_reg[4:2] == 3'd0) data_buf <= quad0;
else if(addr_reg[4:2] == 3'd1) data_buf <= quad1;
else if(addr_reg[4:2] == 3'd2) data_buf <= quad2;
else if(addr_reg[4:2] == 3'd3) data_buf <= quad3;
else if(addr_reg[4:2] == 3'd4)
data_buf <= {quadA, quadB, quadZ, din};
end
end
// the addr_reg test looks funny because it is auto-incremented in an always
// block so "1" reads the low byte, "2 and "3" read middle bytes, and "0"
// reads the high byte I have a feeling that I'm doing this in the wrong way.
wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] :
(addr_reg[1:0] == 2'd2 ? data_buf[15:8] :
(addr_reg[1:0] == 2'd3 ? data_buf[23:16] :
data_buf[31:24]));
wire [7:0] EPP_data_mux = data_reg;
assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ;
assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
assign qr0 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd0);
assign qr1 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd1);
assign qr2 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd2);
assign qr3 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd3);
assign led = do_tristate ? 1'BZ : (real_up[0] ^ real_down[0]);
assign nConfig = epp_nReset; // 1'b1;
endmodule
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, quadA, quadB, quadZ, up, down);
parameter QW=14;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
wire do_tristate;
reg[9:0] real_dout; output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout;
input [7:0] din;
input [3:0] quadA;
input [3:0] quadB;
input [3:0] quadZ;
wire[3:0] real_up; output [3:0] up = do_tristate ? 4'bZZZZ : real_up;
wire[3:0] real_down; output [3:0] down = do_tristate ? 4'bZZZZ : real_down;
reg Zpolarity;
wire [2*QW:0] quad0, quad1, quad2, quad3;
wire do_enable_wdt;
wire pwm_at_top;
wdt w(clk, do_enable_wdt, pwm_at_top, do_tristate);
// PWM stuff
// PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt
reg [10:0] pwmcnt;
wire [10:0] top = 11'd2046;
assign pwm_at_top = (pwmcnt == top);
reg [15:0] pwm0, pwm1, pwm2, pwm3;
always @(posedge clk) begin
if(pwm_at_top) pwmcnt <= 0;
else pwmcnt <= pwmcnt + 11'd1;
end
wire [10:0] pwmrev = {
pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9],
pwmcnt[10], pwmcnt[3:0]};
wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt;
wire pwmact0 = pwm0[10:0] > pwmcmp0;
wire pwmact1 = pwm1[10:0] > pwmcmp0;
wire pwmact2 = pwm2[10:0] > pwmcmp0;
wire pwmact3 = pwm3[10:0] > pwmcmp0;
assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0);
assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1);
assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2);
assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3);
assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0);
assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1);
assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2);
assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3);
// Quadrature stuff
// Quadrature is digitized at 40MHz into 14-bit counters
// Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period
reg qtest;
wire qr0, qr1, qr2, qr3;
quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0);
quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1);
quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2);
quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3);
// EPP stuff
wire EPP_write = ~nWrite;
wire EPP_read = nWrite;
wire EPP_addr_strobe = ~nAddrStr;
wire EPP_data_strobe = ~nDataStr;
wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe;
wire EPP_wait; assign nWait = ~EPP_wait;
wire [7:0] EPP_datain = pport_data;
wire [7:0] EPP_dataout; assign pport_data = EPP_dataout;
reg [4:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe};
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
// reg led;
assign EPP_wait = EPP_strobe_reg[4];
reg[4:0] addr_reg;
reg[7:0] lowbyte;
always @(posedge clk)
if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin
addr_reg <= EPP_datain[4:0];
end
else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin
if(addr_reg[3:0] == 4'd1) pwm0 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd3) pwm1 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd5) pwm2 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd7) pwm3 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd9) begin
real_dout <= { EPP_datain[1:0], lowbyte };
Zpolarity <= EPP_datain[7];
qtest <= EPP_datain[5];
end
else lowbyte <= EPP_datain;
end
end
reg [31:0] data_buf;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin
if(addr_reg[4:2] == 3'd0) data_buf <= quad0;
else if(addr_reg[4:2] == 3'd1) data_buf <= quad1;
else if(addr_reg[4:2] == 3'd2) data_buf <= quad2;
else if(addr_reg[4:2] == 3'd3) data_buf <= quad3;
else if(addr_reg[4:2] == 3'd4)
data_buf <= {quadA, quadB, quadZ, din};
end
end
// the addr_reg test looks funny because it is auto-incremented in an always
// block so "1" reads the low byte, "2 and "3" read middle bytes, and "0"
// reads the high byte I have a feeling that I'm doing this in the wrong way.
wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] :
(addr_reg[1:0] == 2'd2 ? data_buf[15:8] :
(addr_reg[1:0] == 2'd3 ? data_buf[23:16] :
data_buf[31:24]));
wire [7:0] EPP_data_mux = data_reg;
assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ;
assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
assign qr0 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd0);
assign qr1 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd1);
assign qr2 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd2);
assign qr3 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd3);
assign led = do_tristate ? 1'BZ : (real_up[0] ^ real_down[0]);
assign nConfig = epp_nReset; // 1'b1;
endmodule
|
// This is a component of pluto_step, a hardware step waveform generator
// Copyright 2007 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// install ubuntu package "verilog" from universe
// Compile with: iverilog -DTESTING test_stepgen.v stepgen.v
// run with "./a.out | less" and look at output for problems
module test_stepgen();
reg clk;
reg [4:0] vel;
wire [19:0] pos;
wire step, dir;
stepgen #(16,4,16) s(clk, 1, pos, vel, 1, 0, step, dir, 3);
integer q;
reg ost;
initial begin
vel = 5'h8; // two useful test cases:
// vel=5'h8 (max step speed)
// vel=5'h2 (~1 step per repeat)
q = 0;
repeat(50) begin
repeat(50) begin
#20 clk<=1;
#20 clk<=0;
if(step && !ost) begin
if(dir) q = q+1;
else q = q - 1;
end
ost <= step;
$display("%d %d %x %x %d %d %d %d %d",
step, dir, vel, pos, s.state, s.ones, s.pbit, s.timer, q);
end
vel = 6'h20 - vel;
end
end
endmodule
|
// This is a component of pluto_step, a hardware step waveform generator
// Copyright 2007 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// install ubuntu package "verilog" from universe
// Compile with: iverilog -DTESTING test_stepgen.v stepgen.v
// run with "./a.out | less" and look at output for problems
module test_stepgen();
reg clk;
reg [4:0] vel;
wire [19:0] pos;
wire step, dir;
stepgen #(16,4,16) s(clk, 1, pos, vel, 1, 0, step, dir, 3);
integer q;
reg ost;
initial begin
vel = 5'h8; // two useful test cases:
// vel=5'h8 (max step speed)
// vel=5'h2 (~1 step per repeat)
q = 0;
repeat(50) begin
repeat(50) begin
#20 clk<=1;
#20 clk<=0;
if(step && !ost) begin
if(dir) q = q+1;
else q = q - 1;
end
ost <= step;
$display("%d %d %x %x %d %d %d %d %d",
step, dir, vel, pos, s.state, s.ones, s.pbit, s.timer, q);
end
vel = 6'h20 - vel;
end
end
endmodule
|
// This is a component of pluto_step, a hardware step waveform generator
// Copyright 2007 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// install ubuntu package "verilog" from universe
// Compile with: iverilog -DTESTING test_stepgen.v stepgen.v
// run with "./a.out | less" and look at output for problems
module test_stepgen();
reg clk;
reg [4:0] vel;
wire [19:0] pos;
wire step, dir;
stepgen #(16,4,16) s(clk, 1, pos, vel, 1, 0, step, dir, 3);
integer q;
reg ost;
initial begin
vel = 5'h8; // two useful test cases:
// vel=5'h8 (max step speed)
// vel=5'h2 (~1 step per repeat)
q = 0;
repeat(50) begin
repeat(50) begin
#20 clk<=1;
#20 clk<=0;
if(step && !ost) begin
if(dir) q = q+1;
else q = q - 1;
end
ost <= step;
$display("%d %d %x %x %d %d %d %d %d",
step, dir, vel, pos, s.state, s.ones, s.pbit, s.timer, q);
end
vel = 6'h20 - vel;
end
end
endmodule
|
// This is a component of pluto_step, a hardware step waveform generator
// Copyright 2007 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// install ubuntu package "verilog" from universe
// Compile with: iverilog -DTESTING test_stepgen.v stepgen.v
// run with "./a.out | less" and look at output for problems
module test_stepgen();
reg clk;
reg [4:0] vel;
wire [19:0] pos;
wire step, dir;
stepgen #(16,4,16) s(clk, 1, pos, vel, 1, 0, step, dir, 3);
integer q;
reg ost;
initial begin
vel = 5'h8; // two useful test cases:
// vel=5'h8 (max step speed)
// vel=5'h2 (~1 step per repeat)
q = 0;
repeat(50) begin
repeat(50) begin
#20 clk<=1;
#20 clk<=0;
if(step && !ost) begin
if(dir) q = q+1;
else q = q - 1;
end
ost <= step;
$display("%d %d %x %x %d %d %d %d %d",
step, dir, vel, pos, s.state, s.ones, s.pbit, s.timer, q);
end
vel = 6'h20 - vel;
end
end
endmodule
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_1_3_bhv_ver_as
* |
* +-fifo_generator_v13_1_3_bhv_ver_ss
* |
* +-fifo_generator_v13_1_3_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_3_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_3_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_1_3
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_1_3_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy_o,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
wire rst_asreg_d1;
wire rst_asreg_d2;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire fifo_empty_fb;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire safety_ckt_wr_rst;
wire safety_ckt_rd_rst;
reg sckt_wr_rst_i_q = 1'b0;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
always @ (posedge clk_i)
sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy};
end endgenerate
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v13_1_3_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_1_3_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= 1;
ALMOSTEMPTY_P0_OUT_Q <= 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
(C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};
reg [1:0] wrst_cc = {2{1'b0}};
reg [1:0] rrst_cc = {2{1'b0}};
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
reg safety_ckt_wr_rst_i = 1'b0;
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
// end : gnrst_sync
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
reg fifo_wrst_done = 1'b0;
reg fifo_rrst_done = 1'b0;
reg sckt_wrst_i = 1'b0;
reg sckt_wrst_i_q = 1'b0;
reg rd_rst_active = 1'b0;
reg rd_rst_middle = 1'b0;
reg sckt_rd_rst_d1 = 1'b0;
reg [1:0] rst_delayed_ic_w = 2'h0;
wire rst_delayed_ic_w_i;
reg [1:0] rst_delayed_ic_r = 2'h0;
wire rst_delayed_ic_r_i;
wire arst_sync_rst;
wire fifo_rst_done;
wire fifo_rst_active;
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed_ic_w_i;
assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;
assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;
assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_w <= 2'b11;
else
rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};
end
assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_r <= 2'b11;
else
rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};
end
assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
always @(posedge WR_CLK) begin
sckt_wrst_i_q <= #`TCQ sckt_wrst_i;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
if (arst_sync_rst && ~fifo_rst_active)
sckt_wrst_i <= #`TCQ 1'b1;
else if (sckt_wrst_i && fifo_rst_done)
sckt_wrst_i <= #`TCQ 1'b0;
else
sckt_wrst_i <= #`TCQ sckt_wrst_i;
if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
fifo_rrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_rrst_done <= #`TCQ 1'b0;
else
fifo_rrst_done <= #`TCQ fifo_rrst_done;
if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
fifo_wrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_wrst_done <= #`TCQ 1'b0;
else
fifo_wrst_done <= #`TCQ fifo_wrst_done;
end
always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
if (rst_delayed_ic_w_i == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
end
assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
if (rst_delayed_ic_r_i == 1'b1) begin
rd_rst_asreg <= 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;
if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
rd_rst_active <= #`TCQ 1'b1;
rd_rst_middle <= #`TCQ 1'b1;
end else if (safety_ckt_rd_rst)
rd_rst_active <= #`TCQ 1'b0;
else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
rd_rst_middle <= #`TCQ 1'b0;
end
assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_ic_rst
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
reg [1:0] rst_delayed_cc = 2'h0;
wire rst_delayed_cc_i;
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed_cc_i;
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
rst_delayed_cc <= 2'b11;
else
rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};
end
assign rst_delayed_cc_i = rst_delayed_cc[1];
always @(posedge CLK or posedge rst_delayed_cc_i) begin
if (rst_delayed_cc_i == 1'b1) begin
rst_asreg <= 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
end
assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_cc_rst
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
// end : g8s_cc_rst
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
assign safety_ckt_wr_rst = 1'b0;
assign safety_ckt_rd_rst = 1'b0;
end
endgenerate
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d3;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule //fifo_generator_v13_1_3_conv_ver
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_1_3_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input SAFETY_CKT_WR_RST,
input SAFETY_CKT_RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg EMPTY_FB = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
EMPTY_FB <= #`TCQ 1'b1;
else if (empty_int)
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ 1'b0;
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= 0;
stage2_valid <= 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule // fifo_generator_v13_1_3_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input SAFETY_CKT_WR_RST,
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output reg EMPTY_FB = 1'b1,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_1_3_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_1_3_bhv_ver_as
* |
* +-fifo_generator_v13_1_3_bhv_ver_ss
* |
* +-fifo_generator_v13_1_3_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_3_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_3_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_1_3
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_1_3_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy_o,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
wire rst_asreg_d1;
wire rst_asreg_d2;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire fifo_empty_fb;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire safety_ckt_wr_rst;
wire safety_ckt_rd_rst;
reg sckt_wr_rst_i_q = 1'b0;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
always @ (posedge clk_i)
sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy};
end endgenerate
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v13_1_3_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_1_3_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= 1;
ALMOSTEMPTY_P0_OUT_Q <= 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
(C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};
reg [1:0] wrst_cc = {2{1'b0}};
reg [1:0] rrst_cc = {2{1'b0}};
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
reg safety_ckt_wr_rst_i = 1'b0;
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
// end : gnrst_sync
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
reg fifo_wrst_done = 1'b0;
reg fifo_rrst_done = 1'b0;
reg sckt_wrst_i = 1'b0;
reg sckt_wrst_i_q = 1'b0;
reg rd_rst_active = 1'b0;
reg rd_rst_middle = 1'b0;
reg sckt_rd_rst_d1 = 1'b0;
reg [1:0] rst_delayed_ic_w = 2'h0;
wire rst_delayed_ic_w_i;
reg [1:0] rst_delayed_ic_r = 2'h0;
wire rst_delayed_ic_r_i;
wire arst_sync_rst;
wire fifo_rst_done;
wire fifo_rst_active;
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed_ic_w_i;
assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;
assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;
assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_w <= 2'b11;
else
rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};
end
assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_r <= 2'b11;
else
rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};
end
assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
always @(posedge WR_CLK) begin
sckt_wrst_i_q <= #`TCQ sckt_wrst_i;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
if (arst_sync_rst && ~fifo_rst_active)
sckt_wrst_i <= #`TCQ 1'b1;
else if (sckt_wrst_i && fifo_rst_done)
sckt_wrst_i <= #`TCQ 1'b0;
else
sckt_wrst_i <= #`TCQ sckt_wrst_i;
if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
fifo_rrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_rrst_done <= #`TCQ 1'b0;
else
fifo_rrst_done <= #`TCQ fifo_rrst_done;
if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
fifo_wrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_wrst_done <= #`TCQ 1'b0;
else
fifo_wrst_done <= #`TCQ fifo_wrst_done;
end
always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
if (rst_delayed_ic_w_i == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
end
assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
if (rst_delayed_ic_r_i == 1'b1) begin
rd_rst_asreg <= 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;
if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
rd_rst_active <= #`TCQ 1'b1;
rd_rst_middle <= #`TCQ 1'b1;
end else if (safety_ckt_rd_rst)
rd_rst_active <= #`TCQ 1'b0;
else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
rd_rst_middle <= #`TCQ 1'b0;
end
assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_ic_rst
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
reg [1:0] rst_delayed_cc = 2'h0;
wire rst_delayed_cc_i;
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed_cc_i;
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
rst_delayed_cc <= 2'b11;
else
rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};
end
assign rst_delayed_cc_i = rst_delayed_cc[1];
always @(posedge CLK or posedge rst_delayed_cc_i) begin
if (rst_delayed_cc_i == 1'b1) begin
rst_asreg <= 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
end
assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_cc_rst
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
// end : g8s_cc_rst
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
assign safety_ckt_wr_rst = 1'b0;
assign safety_ckt_rd_rst = 1'b0;
end
endgenerate
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d3;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule //fifo_generator_v13_1_3_conv_ver
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_1_3_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input SAFETY_CKT_WR_RST,
input SAFETY_CKT_RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg EMPTY_FB = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
EMPTY_FB <= #`TCQ 1'b1;
else if (empty_int)
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ 1'b0;
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= 0;
stage2_valid <= 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule // fifo_generator_v13_1_3_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input SAFETY_CKT_WR_RST,
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output reg EMPTY_FB = 1'b1,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_1_3_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// DUC block
module duc(input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_interp_out, q_interp_out;
wire [31:0] phase;
wire strobe1, strobe2;
reg [3:0] strobe_ctr1,strobe_ctr2;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr2 <= #1 4'd0;
else if(strobe2)
strobe_ctr2 <= #1 4'd0;
else
strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr1 <= #1 4'd0;
else if(strobe1)
strobe_ctr1 <= #1 4'd0;
else if(strobe2)
strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
assign strobe2 = enable & ( strobe_ctr2 == rate2 );
assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
assign strobe = strobe1;
function [2:0] log_ceil;
input [3:0] val;
log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
endfunction
wire [2:0] shift1 = log_ceil(rate1);
wire [2:0] shift2 = log_ceil(rate2);
cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
cordic(.clock(clock), .reset(reset), .enable(enable),
.xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]),
.xo(i_out), .yo(q_out), .zo() );
cic_interp_2stage #(.bw(bw),.N(4))
interp_i(.clock(clock),.reset(reset),.enable(enable),
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
.signal_in(i_in),.signal_out(i_interp_out));
cic_interp_2stage #(.bw(bw),.N(4))
interp_q(.clock(clock),.reset(reset),.enable(enable),
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
.signal_in(q_in),.signal_out(q_interp_out));
phase_acc #(.resolution(32))
nco (.clk(clock),.reset(reset),.enable(enable),
.freq(freq),.phase(phase));
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// DUC block
module duc(input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_interp_out, q_interp_out;
wire [31:0] phase;
wire strobe1, strobe2;
reg [3:0] strobe_ctr1,strobe_ctr2;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr2 <= #1 4'd0;
else if(strobe2)
strobe_ctr2 <= #1 4'd0;
else
strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr1 <= #1 4'd0;
else if(strobe1)
strobe_ctr1 <= #1 4'd0;
else if(strobe2)
strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
assign strobe2 = enable & ( strobe_ctr2 == rate2 );
assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
assign strobe = strobe1;
function [2:0] log_ceil;
input [3:0] val;
log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
endfunction
wire [2:0] shift1 = log_ceil(rate1);
wire [2:0] shift2 = log_ceil(rate2);
cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
cordic(.clock(clock), .reset(reset), .enable(enable),
.xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]),
.xo(i_out), .yo(q_out), .zo() );
cic_interp_2stage #(.bw(bw),.N(4))
interp_i(.clock(clock),.reset(reset),.enable(enable),
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
.signal_in(i_in),.signal_out(i_interp_out));
cic_interp_2stage #(.bw(bw),.N(4))
interp_q(.clock(clock),.reset(reset),.enable(enable),
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
.signal_in(q_in),.signal_out(q_interp_out));
phase_acc #(.resolution(32))
nco (.clk(clock),.reset(reset),.enable(enable),
.freq(freq),.phase(phase));
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// DUC block
module duc(input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_interp_out, q_interp_out;
wire [31:0] phase;
wire strobe1, strobe2;
reg [3:0] strobe_ctr1,strobe_ctr2;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr2 <= #1 4'd0;
else if(strobe2)
strobe_ctr2 <= #1 4'd0;
else
strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr1 <= #1 4'd0;
else if(strobe1)
strobe_ctr1 <= #1 4'd0;
else if(strobe2)
strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
assign strobe2 = enable & ( strobe_ctr2 == rate2 );
assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
assign strobe = strobe1;
function [2:0] log_ceil;
input [3:0] val;
log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
endfunction
wire [2:0] shift1 = log_ceil(rate1);
wire [2:0] shift2 = log_ceil(rate2);
cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
cordic(.clock(clock), .reset(reset), .enable(enable),
.xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]),
.xo(i_out), .yo(q_out), .zo() );
cic_interp_2stage #(.bw(bw),.N(4))
interp_i(.clock(clock),.reset(reset),.enable(enable),
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
.signal_in(i_in),.signal_out(i_interp_out));
cic_interp_2stage #(.bw(bw),.N(4))
interp_q(.clock(clock),.reset(reset),.enable(enable),
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
.signal_in(q_in),.signal_out(q_interp_out));
phase_acc #(.resolution(32))
nco (.clk(clock),.reset(reset),.enable(enable),
.freq(freq),.phase(phase));
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Addr Decoder
// Each received address is compared to base and high address pairs for each
// of a set of decode targets.
// The matching target's index (if any) is output combinatorially.
// If the decode is successful (matches any target), the MATCH output is asserted.
// For each target, a set of alternative address ranges may be specified.
// The base and high address pairs are formatted as a pair of 2-dimensional arrays,
// alternative address ranges iterate within each target.
// The alternative range which matches the address is also output as REGION.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// addr_decoder
// comparator_static
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_addr_decoder #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16]
parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS)
parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that
// can match each target [1:16]
parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of
// each base and high address [2:64]
parameter integer C_TARGET_ENC = 0, // Enable encoded target output
parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output
parameter integer C_REGION_ENC = 0, // Enable REGION output
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}},
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}},
parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}},
// Indicates whether each target has connectivity.
// Format: C_NUM_TARGETS{Bit1}.
parameter integer C_RESOLUTION = 0,
// Number of low-order ADDR bits that can be ignored when decoding.
parameter integer C_COMPARATOR_THRESHOLD = 6
// Number of decoded ADDR bits above which will implement comparator_static.
)
(
input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand
output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot)
output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded)
output wire MATCH, // Decode successful
output wire [3:0] REGION // Range within target matching address (encoded)
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
genvar target_cnt;
genvar region_cnt;
/////////////////////////////////////////////////////////////////////////////
// Function to detect addrs is in the addressable range.
// Only compare 4KB page address (ignore low-order 12 bits)
function decode_address;
input [C_ADDR_WIDTH-1:0] base, high, addr;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;
begin
addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin
decode_address = 1'b0;
end else begin
mask = base_page ^ high_page;
if ( (base_page & ~mask) == (addr_page & ~mask) ) begin
decode_address = 1'b1;
end else begin
decode_address = 1'b0;
end
end
end
endfunction
// Generates a binary coded from onehotone encoded
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot).
wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot).
wire [3:0] TARGET_ENC_I; // Internal version of encoded hit.
/////////////////////////////////////////////////////////////////////////////
// Generate detection per region per target.
generate
for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region
// Detect if this is an address hit (including used region decoding).
if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static
if (C_TARGET_QUAL[target_cnt] &&
((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||
(C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range
generic_baseblocks_v2_1_comparator_static #
(
.C_FAMILY("rtl"),
.C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),
.C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)
) addr_decode_comparator
(
.CIN(1'b1),
.A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &
~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),
.COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])
);
end else begin : gen_null_range
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;
end
end else begin : gen_no_comparator_static
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ?
decode_address(
C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
ADDR)
: 1'b0;
end // gen_comparator_static
assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];
assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];
end // gen_region
// All regions are non-overlapping
// => Or all the region detections for this target to determine if it is a hit.
assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];
end // gen_target
endgenerate
/////////////////////////////////////////////////////////////////////////////
// All regions are non-overlapping
// => Or all the target hit detections if it is a match.
assign MATCH = | TARGET_HOT_I;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
generate
if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT
assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;
end else begin : NO_TARGET_ONEHOT
assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED
assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);
assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];
end else begin : NO_TARGET_ENCODED
assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded region output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED
assign REGION = f_hot2enc(REGION_HOT);
end else begin : NO_REGION_ENCODED
assign REGION = 4'b0;
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Addr Decoder
// Each received address is compared to base and high address pairs for each
// of a set of decode targets.
// The matching target's index (if any) is output combinatorially.
// If the decode is successful (matches any target), the MATCH output is asserted.
// For each target, a set of alternative address ranges may be specified.
// The base and high address pairs are formatted as a pair of 2-dimensional arrays,
// alternative address ranges iterate within each target.
// The alternative range which matches the address is also output as REGION.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// addr_decoder
// comparator_static
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_addr_decoder #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16]
parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS)
parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that
// can match each target [1:16]
parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of
// each base and high address [2:64]
parameter integer C_TARGET_ENC = 0, // Enable encoded target output
parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output
parameter integer C_REGION_ENC = 0, // Enable REGION output
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}},
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}},
parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}},
// Indicates whether each target has connectivity.
// Format: C_NUM_TARGETS{Bit1}.
parameter integer C_RESOLUTION = 0,
// Number of low-order ADDR bits that can be ignored when decoding.
parameter integer C_COMPARATOR_THRESHOLD = 6
// Number of decoded ADDR bits above which will implement comparator_static.
)
(
input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand
output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot)
output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded)
output wire MATCH, // Decode successful
output wire [3:0] REGION // Range within target matching address (encoded)
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
genvar target_cnt;
genvar region_cnt;
/////////////////////////////////////////////////////////////////////////////
// Function to detect addrs is in the addressable range.
// Only compare 4KB page address (ignore low-order 12 bits)
function decode_address;
input [C_ADDR_WIDTH-1:0] base, high, addr;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;
begin
addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin
decode_address = 1'b0;
end else begin
mask = base_page ^ high_page;
if ( (base_page & ~mask) == (addr_page & ~mask) ) begin
decode_address = 1'b1;
end else begin
decode_address = 1'b0;
end
end
end
endfunction
// Generates a binary coded from onehotone encoded
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot).
wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot).
wire [3:0] TARGET_ENC_I; // Internal version of encoded hit.
/////////////////////////////////////////////////////////////////////////////
// Generate detection per region per target.
generate
for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region
// Detect if this is an address hit (including used region decoding).
if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static
if (C_TARGET_QUAL[target_cnt] &&
((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||
(C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range
generic_baseblocks_v2_1_comparator_static #
(
.C_FAMILY("rtl"),
.C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),
.C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)
) addr_decode_comparator
(
.CIN(1'b1),
.A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &
~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),
.COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])
);
end else begin : gen_null_range
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;
end
end else begin : gen_no_comparator_static
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ?
decode_address(
C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
ADDR)
: 1'b0;
end // gen_comparator_static
assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];
assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];
end // gen_region
// All regions are non-overlapping
// => Or all the region detections for this target to determine if it is a hit.
assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];
end // gen_target
endgenerate
/////////////////////////////////////////////////////////////////////////////
// All regions are non-overlapping
// => Or all the target hit detections if it is a match.
assign MATCH = | TARGET_HOT_I;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
generate
if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT
assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;
end else begin : NO_TARGET_ONEHOT
assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED
assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);
assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];
end else begin : NO_TARGET_ENCODED
assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded region output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED
assign REGION = f_hot2enc(REGION_HOT);
end else begin : NO_REGION_ENCODED
assign REGION = 4'b0;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:15:08 08/27/2015
// Design Name:
// Module Name: Tenth_Phase
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock Signal
input wire rst, //Reset Signal
input wire load_i,
input wire sel_a_i, //Overflow/add/subt result's mux's selector
input wire sel_b_i, //underflow/add/subt result's mux's selector
input wire sign_i, //Sign of the largest Operand
input wire [EW-1:0] exp_ieee_i, //Final Exponent
input wire [SW-1:0] sgf_ieee_i,//Final Significand
//OUTPUTS
output wire [W-1:0] final_result_ieee_o //Final Result
);
//Wire Connection signals
wire [SW-1:0] Sgf_S_mux;
wire [EW-1:0] Exp_S_mux;
wire Sign_S_mux;
wire [W-1:0] final_result_reg;
wire overunder;
wire [EW-1:0] exp_mux_D1;
wire [SW-1:0] sgf_mux_D1;
//////////////////////////////////////////////////////////
assign overunder = sel_a_i | sel_b_i;
Mux_3x1 #(.W(1)) Sign_Mux (
.ctrl({sel_a_i,sel_b_i}),
.D0(sign_i),
.D1(1'b1),
.D2(1'b0),
.S(Sign_S_mux)
);
Multiplexer_AC #(.W(EW)) Exp_Mux (
.ctrl(overunder),
.D0(exp_ieee_i),
.D1(exp_mux_D1),
.S(Exp_S_mux)
);
Multiplexer_AC #(.W(SW)) Sgf_Mux (
.ctrl(overunder),
.D0(sgf_ieee_i),
.D1(sgf_mux_D1),
.S(Sgf_S_mux)
);
/////////////////////////////////////////////////////////
generate
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
endgenerate
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) Final_Result_IEEE (
.clk(clk),
.rst(rst),
.load(load_i),
.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:15:08 08/27/2015
// Design Name:
// Module Name: Tenth_Phase
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock Signal
input wire rst, //Reset Signal
input wire load_i,
input wire sel_a_i, //Overflow/add/subt result's mux's selector
input wire sel_b_i, //underflow/add/subt result's mux's selector
input wire sign_i, //Sign of the largest Operand
input wire [EW-1:0] exp_ieee_i, //Final Exponent
input wire [SW-1:0] sgf_ieee_i,//Final Significand
//OUTPUTS
output wire [W-1:0] final_result_ieee_o //Final Result
);
//Wire Connection signals
wire [SW-1:0] Sgf_S_mux;
wire [EW-1:0] Exp_S_mux;
wire Sign_S_mux;
wire [W-1:0] final_result_reg;
wire overunder;
wire [EW-1:0] exp_mux_D1;
wire [SW-1:0] sgf_mux_D1;
//////////////////////////////////////////////////////////
assign overunder = sel_a_i | sel_b_i;
Mux_3x1 #(.W(1)) Sign_Mux (
.ctrl({sel_a_i,sel_b_i}),
.D0(sign_i),
.D1(1'b1),
.D2(1'b0),
.S(Sign_S_mux)
);
Multiplexer_AC #(.W(EW)) Exp_Mux (
.ctrl(overunder),
.D0(exp_ieee_i),
.D1(exp_mux_D1),
.S(Exp_S_mux)
);
Multiplexer_AC #(.W(SW)) Sgf_Mux (
.ctrl(overunder),
.D0(sgf_ieee_i),
.D1(sgf_mux_D1),
.S(Sgf_S_mux)
);
/////////////////////////////////////////////////////////
generate
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
endgenerate
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) Final_Result_IEEE (
.clk(clk),
.rst(rst),
.load(load_i),
.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:15:08 08/27/2015
// Design Name:
// Module Name: Tenth_Phase
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock Signal
input wire rst, //Reset Signal
input wire load_i,
input wire sel_a_i, //Overflow/add/subt result's mux's selector
input wire sel_b_i, //underflow/add/subt result's mux's selector
input wire sign_i, //Sign of the largest Operand
input wire [EW-1:0] exp_ieee_i, //Final Exponent
input wire [SW-1:0] sgf_ieee_i,//Final Significand
//OUTPUTS
output wire [W-1:0] final_result_ieee_o //Final Result
);
//Wire Connection signals
wire [SW-1:0] Sgf_S_mux;
wire [EW-1:0] Exp_S_mux;
wire Sign_S_mux;
wire [W-1:0] final_result_reg;
wire overunder;
wire [EW-1:0] exp_mux_D1;
wire [SW-1:0] sgf_mux_D1;
//////////////////////////////////////////////////////////
assign overunder = sel_a_i | sel_b_i;
Mux_3x1 #(.W(1)) Sign_Mux (
.ctrl({sel_a_i,sel_b_i}),
.D0(sign_i),
.D1(1'b1),
.D2(1'b0),
.S(Sign_S_mux)
);
Multiplexer_AC #(.W(EW)) Exp_Mux (
.ctrl(overunder),
.D0(exp_ieee_i),
.D1(exp_mux_D1),
.S(Exp_S_mux)
);
Multiplexer_AC #(.W(SW)) Sgf_Mux (
.ctrl(overunder),
.D0(sgf_ieee_i),
.D1(sgf_mux_D1),
.S(Sgf_S_mux)
);
/////////////////////////////////////////////////////////
generate
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
endgenerate
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) Final_Result_IEEE (
.clk(clk),
.rst(rst),
.load(load_i),
.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:15:08 08/27/2015
// Design Name:
// Module Name: Tenth_Phase
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock Signal
input wire rst, //Reset Signal
input wire load_i,
input wire sel_a_i, //Overflow/add/subt result's mux's selector
input wire sel_b_i, //underflow/add/subt result's mux's selector
input wire sign_i, //Sign of the largest Operand
input wire [EW-1:0] exp_ieee_i, //Final Exponent
input wire [SW-1:0] sgf_ieee_i,//Final Significand
//OUTPUTS
output wire [W-1:0] final_result_ieee_o //Final Result
);
//Wire Connection signals
wire [SW-1:0] Sgf_S_mux;
wire [EW-1:0] Exp_S_mux;
wire Sign_S_mux;
wire [W-1:0] final_result_reg;
wire overunder;
wire [EW-1:0] exp_mux_D1;
wire [SW-1:0] sgf_mux_D1;
//////////////////////////////////////////////////////////
assign overunder = sel_a_i | sel_b_i;
Mux_3x1 #(.W(1)) Sign_Mux (
.ctrl({sel_a_i,sel_b_i}),
.D0(sign_i),
.D1(1'b1),
.D2(1'b0),
.S(Sign_S_mux)
);
Multiplexer_AC #(.W(EW)) Exp_Mux (
.ctrl(overunder),
.D0(exp_ieee_i),
.D1(exp_mux_D1),
.S(Exp_S_mux)
);
Multiplexer_AC #(.W(SW)) Sgf_Mux (
.ctrl(overunder),
.D0(sgf_ieee_i),
.D1(sgf_mux_D1),
.S(Sgf_S_mux)
);
/////////////////////////////////////////////////////////
generate
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
endgenerate
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) Final_Result_IEEE (
.clk(clk),
.rst(rst),
.load(load_i),
.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:15:08 08/27/2015
// Design Name:
// Module Name: Tenth_Phase
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock Signal
input wire rst, //Reset Signal
input wire load_i,
input wire sel_a_i, //Overflow/add/subt result's mux's selector
input wire sel_b_i, //underflow/add/subt result's mux's selector
input wire sign_i, //Sign of the largest Operand
input wire [EW-1:0] exp_ieee_i, //Final Exponent
input wire [SW-1:0] sgf_ieee_i,//Final Significand
//OUTPUTS
output wire [W-1:0] final_result_ieee_o //Final Result
);
//Wire Connection signals
wire [SW-1:0] Sgf_S_mux;
wire [EW-1:0] Exp_S_mux;
wire Sign_S_mux;
wire [W-1:0] final_result_reg;
wire overunder;
wire [EW-1:0] exp_mux_D1;
wire [SW-1:0] sgf_mux_D1;
//////////////////////////////////////////////////////////
assign overunder = sel_a_i | sel_b_i;
Mux_3x1 #(.W(1)) Sign_Mux (
.ctrl({sel_a_i,sel_b_i}),
.D0(sign_i),
.D1(1'b1),
.D2(1'b0),
.S(Sign_S_mux)
);
Multiplexer_AC #(.W(EW)) Exp_Mux (
.ctrl(overunder),
.D0(exp_ieee_i),
.D1(exp_mux_D1),
.S(Exp_S_mux)
);
Multiplexer_AC #(.W(SW)) Sgf_Mux (
.ctrl(overunder),
.D0(sgf_ieee_i),
.D1(sgf_mux_D1),
.S(Sgf_S_mux)
);
/////////////////////////////////////////////////////////
generate
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
endgenerate
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) Final_Result_IEEE (
.clk(clk),
.rst(rst),
.load(load_i),
.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_cmd_translator.v
//
// Description:
// INCR and WRAP burst modes are decoded in parallel and then the output is
// chosen based on the AxBURST value. FIXED burst mode is not supported and
// is mapped to the INCR command instead.
//
// Specifications:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_cmd_translator #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axaddr ,
input wire [7:0] s_axlen ,
input wire [2:0] s_axsize ,
input wire [1:0] s_axburst ,
input wire s_axhandshake ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr ,
output wire incr_burst ,
// Connections to/from fsm module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXBURST decodes
localparam P_AXBURST_FIXED = 2'b00;
localparam P_AXBURST_INCR = 2'b01;
localparam P_AXBURST_WRAP = 2'b10;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_AXI_ADDR_WIDTH-1:0] incr_cmd_byte_addr;
wire incr_next_pending;
wire [C_AXI_ADDR_WIDTH-1:0] wrap_cmd_byte_addr;
wire wrap_next_pending;
reg sel_first;
reg s_axburst_eq1;
reg s_axburst_eq0;
reg sel_first_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// INCR and WRAP translations are calcuated in independently, select the one
// for our transactions
// right shift by the UI width to the DRAM width ratio
assign m_axaddr = (s_axburst == P_AXBURST_FIXED) ? s_axaddr :
(s_axburst == P_AXBURST_INCR) ? incr_cmd_byte_addr :
wrap_cmd_byte_addr;
assign incr_burst = (s_axburst[1]) ? 1'b0 : 1'b1;
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | s_axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
always @( * ) begin
if (reset | s_axhandshake) begin
sel_first_i = 1'b1;
end else if (next) begin
sel_first_i = 1'b0;
end else begin
sel_first_i = sel_first;
end
end
assign next_pending = s_axburst[1] ? s_axburst_eq1 : s_axburst_eq0;
always @(posedge clk) begin
if (sel_first_i || s_axburst[1]) begin
s_axburst_eq1 <= wrap_next_pending;
end else begin
s_axburst_eq1 <= incr_next_pending;
end
if (sel_first_i || !s_axburst[1]) begin
s_axburst_eq0 <= incr_next_pending;
end else begin
s_axburst_eq0 <= wrap_next_pending;
end
end
axi_protocol_converter_v2_1_b2s_incr_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
incr_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( incr_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( incr_next_pending )
);
axi_protocol_converter_v2_1_b2s_wrap_cmd #(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH)
)
wrap_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( s_axaddr ) ,
.axlen ( s_axlen ) ,
.axsize ( s_axsize ) ,
.axhandshake ( s_axhandshake ) ,
.cmd_byte_addr ( wrap_cmd_byte_addr ) ,
.next ( next ) ,
.next_pending ( wrap_next_pending )
);
endmodule
`default_nettype wire
|
`include "lo_read.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:46 12/20/2010
// Design Name:
// Module Name: clk_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311OI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A311OI_PP_SYMBOL_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a311oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311OI_PP_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : wiredly.v
// /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7Series
// Design Name : DDR2 SDRAM
// Purpose :
// This module provide the definition of a zero ohm component (A, B).
//
// The applications of this component include:
// . Normal operation of a jumper wire (data flowing in both directions)
// This can corrupt data from DRAM to FPGA useful for verifying ECC function.
//
// The component consists of 2 ports:
// . Port A: One side of the pass-through switch
// . Port B: The other side of the pass-through switch
// The model is sensitive to transactions on all ports. Once a transaction
// is detected, all other transactions are ignored for that simulation time
// (i.e. further transactions in that delta time are ignored).
// Model Limitations and Restrictions:
// Signals asserted on the ports of the error injector should not have
// transactions occuring in multiple delta times because the model
// is sensitive to transactions on port A, B ONLY ONCE during
// a simulation time. Thus, once fired, a process will
// not refire if there are multiple transactions occuring in delta times.
// This condition may occur in gate level simulations with
// ZERO delays because transactions may occur in multiple delta times.
//
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ns / 1ps
module WireDelay # (
parameter Delay_g = 0,
parameter Delay_rd = 0,
parameter ERR_INSERT = "OFF"
)
(
inout A,
inout B,
input reset,
input phy_init_done
);
reg A_r;
reg B_r;
reg B_inv ;
reg line_en;
reg B_nonX;
assign A = A_r;
assign B = B_r;
always @ (*)
begin
if (B === 1'bx)
B_nonX <= $random;
else
B_nonX <= B;
end
always@(*)
begin
if((B_nonX == 'b1) || (B_nonX == 'b0))
B_inv <= #0 ~B_nonX ;
else
B_inv <= #0 'bz ;
end
always @(*) begin
if (!reset) begin
A_r <= 1'bz;
B_r <= 1'bz;
line_en <= 1'b0;
end else begin
if (line_en) begin
B_r <= 1'bz;
if ((ERR_INSERT == "ON") & (phy_init_done))
A_r <= #Delay_rd B_inv;
else
A_r <= #Delay_rd B_nonX;
end else begin
B_r <= #Delay_g A;
A_r <= 1'bz;
end
end
end
always @(A or B) begin
if (!reset) begin
line_en <= 1'b0;
end else if (A !== A_r) begin
line_en <= 1'b0;
end else if (B_r !== B) begin
line_en <= 1'b1;
end else begin
line_en <= line_en;
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: router_op_lut_regs_non_cntr.v
// Project: NF2.1
// Description: Demultiplexes, stores and serves register requests
//
// Contains the non-counter registers.
//
///////////////////////////////////////////////////////////////////////////////
module router_op_lut_regs_non_cntr
#( parameter NUM_QUEUES = 5,
parameter ARP_LUT_DEPTH_BITS = 4,
parameter LPM_LUT_DEPTH_BITS = 4,
parameter FILTER_DEPTH_BITS = 4,
parameter UDP_REG_SRC_WIDTH = 2
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
// --- interface to ip_lpm
output reg [LPM_LUT_DEPTH_BITS-1:0 ] lpm_rd_addr, // address in table to read
output reg lpm_rd_req, // request a read
input [31:0] lpm_rd_ip, // ip to match in the CAM
input [31:0] lpm_rd_mask, // subnet mask
input [NUM_QUEUES-1:0] lpm_rd_oq, // input queue
input [31:0] lpm_rd_next_hop_ip, // ip addr of next hop
input lpm_rd_ack, // pulses high
output reg [LPM_LUT_DEPTH_BITS-1:0] lpm_wr_addr,
output reg lpm_wr_req,
output [NUM_QUEUES-1:0] lpm_wr_oq,
output [31:0] lpm_wr_next_hop_ip, // ip addr of next hop
output [31:0] lpm_wr_ip, // data to match in the CAM
output [31:0] lpm_wr_mask,
input lpm_wr_ack,
// --- ip_arp
output reg [ARP_LUT_DEPTH_BITS-1:0] arp_rd_addr, // address in table to read
output reg arp_rd_req, // request a read
input [47:0] arp_rd_mac, // data read from the LUT at rd_addr
input [31:0] arp_rd_ip, // ip to match in the CAM
input arp_rd_ack, // pulses high
output reg [ARP_LUT_DEPTH_BITS-1:0] arp_wr_addr,
output reg arp_wr_req,
output [47:0] arp_wr_mac,
output [31:0] arp_wr_ip, // data to match in the CAM
input arp_wr_ack,
// --- interface to dest_ip_filter
output reg [FILTER_DEPTH_BITS-1:0] dest_ip_filter_rd_addr, // address in table to read
output reg dest_ip_filter_rd_req, // request a read
input [31:0] dest_ip_filter_rd_ip, // ip to match in the CAM
input dest_ip_filter_rd_ack, // pulses high
output reg [FILTER_DEPTH_BITS-1:0] dest_ip_filter_wr_addr,
output reg dest_ip_filter_wr_req,
output [31:0] dest_ip_filter_wr_ip, // data to match in the CAM
input dest_ip_filter_wr_ack,
// --- eth_parser
output reg [47:0] mac_0, // address of rx queue 0
output reg [47:0] mac_1, // address of rx queue 1
output reg [47:0] mac_2, // address of rx queue 2
output reg [47:0] mac_3, // address of rx queue 3
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Internal parameters --------------
localparam NUM_REGS_USED = 32;
localparam ADDR_WIDTH = log2(NUM_REGS_USED);
localparam WAIT_FOR_REQ = 1;
localparam WRITE_TO_ARP_LUT = 2;
localparam READ_FROM_ARP_LUT = 4;
localparam WRITE_TO_RT_LUT = 8;
localparam READ_FROM_RT_LUT = 16;
localparam WRITE_TO_DEST_IP_FILTER = 32;
localparam READ_FROM_DEST_IP_FILTER = 64;
localparam DONE = 128;
// ------------- Wires/reg ------------------
wire [ADDR_WIDTH-1:0] addr;
wire [`ROUTER_OP_LUT_REG_ADDR_WIDTH- 1:0] reg_addr;
wire [`UDP_REG_ADDR_WIDTH-`ROUTER_OP_LUT_REG_ADDR_WIDTH- 1:0] tag_addr;
wire addr_good;
wire tag_hit;
reg [7:0] state;
reg reg_rd_wr_L_held;
reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_held;
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_held;
reg [UDP_REG_SRC_WIDTH-1:0] reg_src_held;
reg [NUM_QUEUES-1:0] lpm_oq;
reg [31:0] lpm_next_hop_ip;
reg [31:0] lpm_ip;
reg [31:0] lpm_mask;
reg [47:0] arp_mac;
reg [31:0] arp_ip;
reg [31:0] dest_ip_filter_ip;
// -------------- Logic --------------------
assign addr = reg_addr_in[ADDR_WIDTH-1:0];
assign reg_addr = reg_addr_in[`ROUTER_OP_LUT_REG_ADDR_WIDTH-1:0];
assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:`ROUTER_OP_LUT_REG_ADDR_WIDTH];
//assign addr_good = reg_addr < NUM_REGS_USED;
assign addr_good = reg_addr >= `ROUTER_OP_LUT_MAC_0_HI &&
reg_addr <= `ROUTER_OP_LUT_DST_IP_FILTER_TABLE_WR_ADDR;
assign tag_hit = tag_addr == `ROUTER_OP_LUT_BLOCK_ADDR;
assign lpm_wr_oq = lpm_oq;
assign lpm_wr_next_hop_ip = lpm_next_hop_ip;
assign lpm_wr_ip = lpm_ip;
assign lpm_wr_mask = lpm_mask;
assign dest_ip_filter_wr_ip = dest_ip_filter_ip;
assign arp_wr_ip = arp_ip;
assign arp_wr_mac = arp_mac;
// The following resets have been moved here to enable optimization by
// pushing some registers into RAMs
// synthesis translate_off
initial
begin
arp_rd_addr = 'h0;
arp_wr_addr = 'h0;
lpm_rd_addr = 'h0;
lpm_wr_addr = 'h0;
dest_ip_filter_rd_addr = 'h0;
dest_ip_filter_wr_addr = 'h0;
end
// synthesis translate_on
/* run the counters and mux between write and update */
always @(posedge clk) begin
if(reset) begin
arp_mac <= 48'h0;
arp_ip <= 32'h0;
lpm_ip <= 'h0;
lpm_mask <= 'h0;
lpm_next_hop_ip <= 'h0;
lpm_oq <= 'h0;
mac_0 <= {`ROUTER_OP_LUT_DEFAULT_MAC_0_HI, `ROUTER_OP_LUT_DEFAULT_MAC_0_LO};
mac_1 <= {`ROUTER_OP_LUT_DEFAULT_MAC_1_HI, `ROUTER_OP_LUT_DEFAULT_MAC_1_LO};
mac_2 <= {`ROUTER_OP_LUT_DEFAULT_MAC_2_HI, `ROUTER_OP_LUT_DEFAULT_MAC_2_LO};
mac_3 <= {`ROUTER_OP_LUT_DEFAULT_MAC_3_HI, `ROUTER_OP_LUT_DEFAULT_MAC_3_LO};
dest_ip_filter_ip <= 'h0;
reg_req_out <= 0;
reg_ack_out <= 0;
reg_rd_wr_L_out <= 0;
reg_addr_out <= 0;
reg_data_out <= 0;
reg_src_out <= 0;
reg_rd_wr_L_held <= 0;
reg_addr_held <= 0;
reg_data_held <= 0;
reg_src_held <= 0;
state <= WAIT_FOR_REQ;
lpm_rd_req <= 0;
lpm_wr_req <= 0;
arp_rd_req <= 0;
arp_wr_req <= 0;
dest_ip_filter_wr_req <= 0;
dest_ip_filter_rd_req <= 0;
end // if (reset)
else begin
case(state)
WAIT_FOR_REQ: begin
if (reg_req_in && tag_hit) begin
if (!reg_rd_wr_L_in && addr_good) begin // write
// Update the appropriate register
case (addr)
`ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_HI : arp_mac[47:32] <= reg_data_in;
`ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_LO : arp_mac[31:0] <= reg_data_in;
`ROUTER_OP_LUT_ARP_TABLE_ENTRY_NEXT_HOP_IP : arp_ip <= reg_data_in;
`ROUTER_OP_LUT_ARP_TABLE_RD_ADDR : arp_rd_addr <= reg_data_in;
`ROUTER_OP_LUT_ARP_TABLE_WR_ADDR : arp_wr_addr <= reg_data_in;
`ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_IP : lpm_ip <= reg_data_in;
`ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_MASK : lpm_mask <= reg_data_in;
`ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_NEXT_HOP_IP : lpm_next_hop_ip <= reg_data_in;
`ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_OUTPUT_PORT : lpm_oq <= reg_data_in;
`ROUTER_OP_LUT_ROUTE_TABLE_RD_ADDR : lpm_rd_addr <= reg_data_in;
`ROUTER_OP_LUT_ROUTE_TABLE_WR_ADDR : lpm_wr_addr <= reg_data_in;
`ROUTER_OP_LUT_MAC_0_HI : mac_0[47:32] <= reg_data_in;
`ROUTER_OP_LUT_MAC_0_LO : mac_0[31:0] <= reg_data_in;
`ROUTER_OP_LUT_MAC_1_HI : mac_1[47:32] <= reg_data_in;
`ROUTER_OP_LUT_MAC_1_LO : mac_1[31:0] <= reg_data_in;
`ROUTER_OP_LUT_MAC_2_HI : mac_2[47:32] <= reg_data_in;
`ROUTER_OP_LUT_MAC_2_LO : mac_2[31:0] <= reg_data_in;
`ROUTER_OP_LUT_MAC_3_HI : mac_3[47:32] <= reg_data_in;
`ROUTER_OP_LUT_MAC_3_LO : mac_3[31:0] <= reg_data_in;
`ROUTER_OP_LUT_DST_IP_FILTER_TABLE_ENTRY_IP : dest_ip_filter_ip<= reg_data_in;
`ROUTER_OP_LUT_DST_IP_FILTER_TABLE_RD_ADDR : dest_ip_filter_rd_addr <= reg_data_in;
`ROUTER_OP_LUT_DST_IP_FILTER_TABLE_WR_ADDR : dest_ip_filter_wr_addr <= reg_data_in;
endcase
// Perform the correct post processing
case(addr)
`ROUTER_OP_LUT_ARP_TABLE_WR_ADDR : state <= WRITE_TO_ARP_LUT;
`ROUTER_OP_LUT_ARP_TABLE_RD_ADDR : state <= READ_FROM_ARP_LUT;
`ROUTER_OP_LUT_ROUTE_TABLE_WR_ADDR : state <= WRITE_TO_RT_LUT;
`ROUTER_OP_LUT_ROUTE_TABLE_RD_ADDR : state <= READ_FROM_RT_LUT;
`ROUTER_OP_LUT_DST_IP_FILTER_TABLE_WR_ADDR : state <= WRITE_TO_DEST_IP_FILTER;
`ROUTER_OP_LUT_DST_IP_FILTER_TABLE_RD_ADDR : state <= READ_FROM_DEST_IP_FILTER;
default : state <= DONE;
endcase // case(addr)
reg_req_out <= 0;
reg_ack_out <= 0;
reg_rd_wr_L_out <= 0;
reg_addr_out <= 0;
reg_data_out <= 0;
reg_src_out <= 0;
reg_rd_wr_L_held <= reg_rd_wr_L_in;
reg_addr_held <= reg_addr_in;
reg_data_held <= reg_data_in;
reg_src_held <= reg_src_in;
end
else begin
reg_req_out <= 1'b 1;
reg_rd_wr_L_out <= reg_rd_wr_L_in;
reg_addr_out <= reg_addr_in;
if (addr_good) begin
reg_ack_out <= 1'b 1;
case (addr)
`ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_HI : reg_data_out <= arp_mac[47:32];
`ROUTER_OP_LUT_ARP_TABLE_ENTRY_MAC_LO : reg_data_out <= arp_mac[31:0];
`ROUTER_OP_LUT_ARP_TABLE_ENTRY_NEXT_HOP_IP : reg_data_out <= arp_ip;
`ROUTER_OP_LUT_ARP_TABLE_RD_ADDR : reg_data_out <= arp_rd_addr;
`ROUTER_OP_LUT_ARP_TABLE_WR_ADDR : reg_data_out <= arp_wr_addr;
`ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_IP : reg_data_out <= lpm_ip;
`ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_MASK : reg_data_out <= lpm_mask;
`ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_NEXT_HOP_IP : reg_data_out <= lpm_next_hop_ip;
`ROUTER_OP_LUT_ROUTE_TABLE_ENTRY_OUTPUT_PORT : reg_data_out <= lpm_oq;
`ROUTER_OP_LUT_ROUTE_TABLE_RD_ADDR : reg_data_out <= lpm_rd_addr;
`ROUTER_OP_LUT_ROUTE_TABLE_WR_ADDR : reg_data_out <= lpm_wr_addr;
`ROUTER_OP_LUT_MAC_0_HI : reg_data_out <= mac_0[47:32];
`ROUTER_OP_LUT_MAC_0_LO : reg_data_out <= mac_0[31:0];
`ROUTER_OP_LUT_MAC_1_HI : reg_data_out <= mac_1[47:32];
`ROUTER_OP_LUT_MAC_1_LO : reg_data_out <= mac_1[31:0];
`ROUTER_OP_LUT_MAC_2_HI : reg_data_out <= mac_2[47:32];
`ROUTER_OP_LUT_MAC_2_LO : reg_data_out <= mac_2[31:0];
`ROUTER_OP_LUT_MAC_3_HI : reg_data_out <= mac_3[47:32];
`ROUTER_OP_LUT_MAC_3_LO : reg_data_out <= mac_3[31:0];
`ROUTER_OP_LUT_DST_IP_FILTER_TABLE_ENTRY_IP : reg_data_out <= dest_ip_filter_ip;
`ROUTER_OP_LUT_DST_IP_FILTER_TABLE_RD_ADDR : reg_data_out <= dest_ip_filter_rd_addr;
`ROUTER_OP_LUT_DST_IP_FILTER_TABLE_WR_ADDR : reg_data_out <= dest_ip_filter_wr_addr;
default : reg_data_out <= 32'h DEAD_BEEF;
endcase
end
else
begin
reg_ack_out <= 1'b 0;
reg_data_out <= reg_data_in;
end
reg_src_out <= reg_src_in;
end
end
else begin
reg_req_out <= reg_req_in;
reg_ack_out <= reg_ack_in;
reg_rd_wr_L_out <= reg_rd_wr_L_in;
reg_addr_out <= reg_addr_in;
reg_data_out <= reg_data_in;
reg_src_out <= reg_src_in;
end
end // case: WAIT_FOR_REQ
WRITE_TO_ARP_LUT: begin
if(arp_wr_ack) begin
state <= DONE;
arp_wr_req <= 0;
end
else begin
arp_wr_req <= 1;
end
end
READ_FROM_ARP_LUT: begin
if(arp_rd_ack) begin
arp_mac[47:32] <= arp_rd_mac[47:32];
arp_mac[31:0] <= arp_rd_mac[31:0];
arp_ip <= arp_rd_ip;
state <= DONE;
arp_rd_req <= 0;
end // if (rd_ack)
else begin
arp_rd_req <= 1;
end
end // case: READ_FROM_MAC_LUT
WRITE_TO_RT_LUT: begin
if(lpm_wr_ack) begin
state <= DONE;
lpm_wr_req <= 0;
end
else begin
lpm_wr_req <= 1;
end
end
READ_FROM_RT_LUT: begin
if(lpm_rd_ack) begin
lpm_ip <= lpm_rd_ip;
lpm_mask <= lpm_rd_mask;
lpm_next_hop_ip <= lpm_rd_next_hop_ip;
lpm_oq <= lpm_rd_oq;
state <= DONE;
lpm_rd_req <= 0;
end // if (rd_ack)
else begin
lpm_rd_req <= 1;
end
end // case: READ_FROM_MAC_LUT
WRITE_TO_DEST_IP_FILTER: begin
if(dest_ip_filter_wr_ack) begin
state <= DONE;
dest_ip_filter_wr_req <= 0;
end
else begin
dest_ip_filter_wr_req <= 1;
end
end // case: WRITE_TO_DEST_IP_FILTER
READ_FROM_DEST_IP_FILTER: begin
if(dest_ip_filter_rd_ack) begin
dest_ip_filter_ip <= dest_ip_filter_rd_ip;
state <= DONE;
dest_ip_filter_rd_req <= 0;
end // if (rd_ack)
else begin
dest_ip_filter_rd_req <= 1;
end
end // case: READ_FROM_DEST_IP_FILTER
DONE: begin
state <= WAIT_FOR_REQ;
reg_req_out <= 1'b 1;
reg_ack_out <= 1'b 1;
reg_rd_wr_L_out <= reg_rd_wr_L_held;
reg_addr_out <= reg_addr_held;
reg_data_out <= reg_data_held;
reg_src_out <= reg_src_held;
end
endcase // case(state)
end // else: !if(reset)
end // always @ (posedge clk)
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_PP_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_PP_V |
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_no_underflow (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter min = 0;
parameter max = ((1<<width)-1);
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_NO_UNDERFLOW";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_no_underflow_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_no_underflow_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_no_underflow_psl_logic.v"
`else
`endmodule // ovl_no_underflow
`endif
|
// TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_015.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 222
`timescale 1 ps / 1 ps
module TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_015 #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_015_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__FILL_FUNCTIONAL_PP_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__fill (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_SN_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_SN_BLACKBOX_V
/**
* udp_dlatch$PR_pp$sN: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$PR_pp$sN (
Q ,
D ,
GATE ,
RESET ,
SLEEP_B ,
NOTIFIER
);
output Q ;
input D ;
input GATE ;
input RESET ;
input SLEEP_B ;
input NOTIFIER;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_SN_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDFSTP_PP_BLACKBOX_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSTP_PP_BLACKBOX_V
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_sys.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.0.0 Build 614 04/24/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
module pll_sys (
inclk0,
c0,
c1,
c2,
locked);
input inclk0;
output c0;
output c1;
output c2;
output locked;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "7.372800"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "1.843200"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "7.37280000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "1.84320000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_sys.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2304"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "576"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: upd77c25_datrom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module upd77c25_datrom (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [15:0] data;
input [10:0] rdaddress;
input [10:0] wraddress;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({16{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 11,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL "rdaddress[10..0]"
// Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL "wraddress[10..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 11 0 wraddress 0 0 11 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datrom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datrom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datrom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datrom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datrom_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_datrom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_15x16.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1.191 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_15x16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [14:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [14:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [14:0] sub_wire3;
wire sub_wire4;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [14:0] q = sub_wire3[14:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = 12,
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 15,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "12"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "15"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "15"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "15"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 15 0 INPUT NODEFVAL "data[14..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 15 0 OUTPUT NODEFVAL "q[14..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 15 0 data 0 0 15 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 15 0 @q 0 0 15 0
// Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_15x16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_15x16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_15x16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_15x16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_15x16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_15x16_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module axis2buffer #(
parameter DWIDTH = 32,
parameter WIDTH = 8
)(
// Control signals
clk,
rstn,
// Color conversion signals
alive_color,
dead_color,
// AXIS Connection
S_AXIS_TDATA,
S_AXIS_TVALID,
S_AXIS_TREADY,
S_AXIS_TLAST,
// Output to conware computation
out_data,
out_valid,
out_ready,
num_reads,
counter
);
// Port descriptions
input clk;
input rstn;
input [DWIDTH-1:0] alive_color;
input [DWIDTH-1:0] dead_color;
input [DWIDTH-1:0] S_AXIS_TDATA;
input S_AXIS_TVALID;
input S_AXIS_TLAST;
output reg S_AXIS_TREADY;
output reg [WIDTH-1:0] out_data;
output reg out_valid;
input out_ready;
output reg [31:0] num_reads;
reg next_num_reads;
// State params
reg state;
reg next_state;
localparam Wait = 0;
localparam Read = 1;
// Internal values
reg in_state;
output reg [7:0] counter;
reg [7:0] next_counter;
initial begin
state <= Read;
out_data <= 0;
counter <= 0;
num_reads <= 0;
end
// Combinational Logic
always @* begin
next_num_reads <= num_reads;
if ((state == Read) && (S_AXIS_TVALID == 1)) begin
in_state <= (S_AXIS_TDATA == alive_color)? 1'b1 : 1'b0;
end else begin
in_state <= out_data[counter];
end
case (state)
Wait: begin
next_counter <= 0;
S_AXIS_TREADY <= 0;
out_valid <= 1;
if (out_ready) begin
next_state <= Read;
end else begin
next_state <= Wait;
end
end
Read: begin
S_AXIS_TREADY <= 1;
next_state <= Read;
out_valid <= 0;
if (S_AXIS_TVALID == 1) begin
if (counter == WIDTH-1) begin
next_counter <= 0;
next_state <= Wait;
next_num_reads <= num_reads + 1;
end else begin
next_counter <= counter + 1;
end
end else begin
// Data source stalled
next_counter <= counter;
end
end
endcase
end
// Clocked Logic
always @(posedge clk) begin
if (!rstn) begin
counter <= 8'h00;
state <= Read;
num_reads <= 0;
end else begin
out_data[counter] <= in_state;
state <= next_state;
counter <= next_counter;
num_reads <= next_num_reads;
end
end
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:55:30 03/10/2014
// Design Name:
// Module Name: Frequency
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Frequency(
input wire clk,
input wire rst,
input wire rand,
output reg pass
);
parameter N = 20000, U = 10182, L = 9818;
reg [14:0] count_bits0, count_bits1, count_ones;
always @(posedge clk)
if (rst) begin
count_bits0 <= 15'H7FFF;
count_bits1 <= 0;
count_ones <= 0;
pass <= 0;
end
else begin
count_bits0 <= count_bits0 + 1;
count_bits1 <= count_bits0;
if (count_bits0 == (N-1)) begin
count_bits0 <= 0;
end
if (rand) count_ones <= count_ones + 1;
if (count_bits1 == (N-1)) begin
count_ones <= rand;
if ((count_ones <= U) && (count_ones >= L)) pass <= 1;
else pass <= 0;
end
end
endmodule
|
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
Require Export CoRN.algebra.CPoly_NthCoeff.
Require Export CoRN.algebra.CFields.
Require Export CoRN.tactics.Rational.
Require Import Lia.
Import CRing_Homomorphisms.coercions.
Set Automatic Introduction.
(**
* Degrees of Polynomials
** Degrees of polynomials over a ring
%\begin{convention}%
Let [R] be a ring and write [RX] for the ring of polynomials
over [R].
%\end{convention}%
*)
Section Degree_def.
Variable R : CRing.
(* begin hide *)
Notation RX := (cpoly_cring R).
(* end hide *)
(**
The length of a polynomial is the number of its coefficients. This is
a syntactical property, as the highest coefficient may be [0]. Note that
the `zero' polynomial [cpoly_zero] has length [0],
a constant polynomial has length [1] and so forth. So the length
is always [1] higher than the `degree' (assuming that the highest
coefficient is [[#][0]])!
*)
Arguments cpoly_zero {CR}.
Arguments cpoly_linear [CR].
Fixpoint lth_of_poly (p : RX) : nat :=
match p with
| cpoly_zero => 0
| cpoly_linear d q => S (lth_of_poly q)
end.
(**
When dealing with constructive polynomials, notably over the reals or
complex numbers, the degree may be unknown, as we can not decide
whether the highest coefficient is [[#][0]]. Hence,
degree is a relation between polynomials and natural numbers; if the
degree is unknown for polynomial [p], degree(n,p) doesn't hold for
any [n]. If we don't know the degree of [p], we may still
know it to be below or above a certain number. E.g. for the polynomial
$p_0 +p_1 X +\cdots + p_{n-1} X^{n-1}$#p0 +p1 X + ... + p(n-1)
X^(n-1)#, if $p_i \mathrel{\#}0$#pi apart from 0#, we can say that the
`degree is at least [i]' and if $p_{j+1} = \ldots =p_n =0$#p(j+1)
= ... =pn =0# (with [n] the length of the polynomial), we can say
that the `degree is at most [j]'.
*)
Definition degree_le n (p : RX) : Prop := forall m, n < m -> nth_coeff m p [=] [0].
Definition degree n (p : RX) : CProp := nth_coeff n p [#] [0] and degree_le n p.
Definition monic n (p : RX) : Prop := nth_coeff n p [=] [1] /\ degree_le n p.
Definition odd_cpoly (p : RX) : CProp := {n : nat | Codd n | degree n p}.
Definition even_cpoly (p : RX) : CProp := {n : nat | Ceven n | degree n p}.
Definition regular (p : RX) : CProp := {n : nat | degree n p}.
End Degree_def.
Arguments degree_le [R].
Arguments degree [R].
Arguments monic [R].
Arguments lth_of_poly [R].
Section Degree_props.
Variable R : CRing.
Add Ring R: (CRing_Ring R).
(* begin hide *)
Notation RX := (cpoly_cring R).
(* end hide *)
Lemma degree_le_wd : forall (p p' : RX) n,
p [=] p' -> degree_le n p -> degree_le n p'.
Proof.
unfold degree_le in |- *. intros.
Step_final (nth_coeff m p).
Qed.
Lemma degree_wd : forall (p p' : RX) n, p [=] p' -> degree n p -> degree n p'.
Proof.
unfold degree in |- *. intros p p' n H H0.
elim H0. clear H0. intros. split.
astepl (nth_coeff n p). auto.
apply degree_le_wd with p; auto.
Qed.
Lemma monic_wd : forall (p p' : RX) n, p [=] p' -> monic n p -> monic n p'.
Proof.
unfold monic in |- *. intros.
elim H0. clear H0. intros. split.
Step_final (nth_coeff n p).
apply degree_le_wd with p; auto.
Qed.
Lemma degree_imp_degree_le : forall (p : RX) n, degree n p -> degree_le n p.
Proof.
unfold degree in |- *. intros p n H. elim H. auto.
Qed.
Lemma degree_le_cpoly_zero n: degree_le n (cpoly_zero R).
Proof. intro. reflexivity. Qed.
Lemma degree_le_c_ : forall c : R, degree_le 0 (_C_ c).
Proof.
unfold degree_le in |- *. intros c m. elim m; intros.
elim (lt_irrefl _ H).
simpl in |- *. algebra.
Qed.
Lemma degree_c_ : forall c : R, c [#] [0] -> degree 0 (_C_ c).
Proof.
unfold degree in |- *. intros. split. simpl in |- *. auto. apply degree_le_c_.
Qed.
Lemma monic_c_one : monic 0 (_C_ ([1]:R)).
Proof.
unfold monic in |- *. intros. split. simpl in |- *. algebra. apply degree_le_c_.
Qed.
Lemma degree_le_x_ : degree_le 1 (_X_:RX).
Proof.
unfold degree_le in |- *.
intro. elim m. intros. elim (lt_n_O _ H).
intro. elim n. intros. elim (lt_irrefl _ H0).
intros. simpl in |- *. algebra.
Qed.
Lemma degree_x_ : degree 1 (_X_:RX).
Proof.
unfold degree in |- *. split. simpl in |- *. algebra. exact degree_le_x_.
Qed.
Lemma monic_x_ : monic 1 (_X_:RX).
Proof.
unfold monic in |- *. split. simpl in |- *. algebra. exact degree_le_x_.
Qed.
Lemma degree_le_mon : forall (p : RX) m n,
m <= n -> degree_le m p -> degree_le n p.
Proof.
unfold degree_le in |- *. intros. apply H0.
apply le_lt_trans with n; auto with arith.
Qed.
Lemma degree_le_inv : forall (p : RX) n, degree_le n p -> degree_le n [--]p.
Proof.
unfold degree_le in |- *. intros.
astepl ( [--] (nth_coeff m p)).
Step_final ( [--] ([0]:R)).
Qed.
Lemma degree_le_plus : forall (p q : RX) n,
degree_le n p -> degree_le n q -> degree_le n (p[+]q).
Proof.
unfold degree_le in |- *. intros.
astepl (nth_coeff m p[+]nth_coeff m q).
Step_final ([0][+] ([0]:R)).
Qed.
Lemma degree_le_minus : forall (p q : RX) n,
degree_le n p -> degree_le n q -> degree_le n (p[-]q).
Proof.
unfold degree_le in |- *. intros.
astepl (nth_coeff m p[-]nth_coeff m q).
Step_final ([0][-] ([0]:R)).
Qed.
Lemma Sum_degree_le : forall (f : nat -> RX) (n k l : nat), k <= S l ->
(forall i, k <= i -> i <= l -> degree_le n (f i)) -> degree_le n (Sum k l f).
Proof.
unfold degree_le in |- *. intros. induction l as [| l Hrecl]; intros.
generalize (toCle _ _ H); clear H; intro H.
inversion H as [|m0 X].
unfold Sum in |- *. unfold Sum1 in |- *. simpl in |- *.
apply eq_transitive with (nth_coeff m ([0]:RX)).
apply nth_coeff_wd. algebra. algebra.
inversion X. rename H3 into kis0. unfold Sum in |- *. unfold Sum1 in |- *. simpl in |- *.
apply eq_transitive with (nth_coeff m (f 0)).
apply nth_coeff_wd. cut (f 0[-][0] [=] f 0). auto. algebra.
apply H0; try auto. rewrite kis0; auto.
elim (le_lt_eq_dec _ _ H); intro y.
apply eq_transitive_unfolded with (nth_coeff m (Sum k l f[+]f (S l))).
apply nth_coeff_wd. algebra.
astepl (nth_coeff m (Sum k l f) [+]nth_coeff m (f (S l))).
astepr ([0][+] ([0]:R)). apply bin_op_wd_unfolded.
apply Hrecl. auto with arith. intros.
apply H0. auto. auto. auto.
apply H0. auto with arith. auto. auto.
rewrite y. unfold Sum in |- *. unfold Sum1 in |- *. simpl in |- *.
apply eq_transitive_unfolded with (nth_coeff m ([0]:RX)).
apply nth_coeff_wd. algebra. algebra.
Qed.
Lemma degree_le_Sum (l: list (cpoly R)) n:
(forall p, In p l -> degree_le n p) -> degree_le n (cm_Sum l).
Proof.
induction l; intros.
apply degree_le_cpoly_zero.
change (degree_le n (a [+] cm_Sum l)).
apply degree_le_plus; intuition.
Qed.
Lemma degree_inv : forall (p : RX) (n : nat), degree n p -> degree n [--]p.
Proof.
unfold degree in |- *. intros p n H.
elim H. clear H. intros. split.
astepl ( [--] (nth_coeff n p)). algebra.
apply degree_le_inv; auto.
Qed.
Lemma degree_plus_rht : forall (p q : RX) m n,
degree_le m p -> degree n q -> m < n -> degree n (p[+]q).
Proof.
unfold degree in |- *. unfold degree_le in |- *. intros.
elim X. clear X. intros.
split.
astepl (nth_coeff n p[+]nth_coeff n q).
astepl ([0][+]nth_coeff n q).
astepl (nth_coeff n q). auto.
intros.
astepl (nth_coeff m0 p[+]nth_coeff m0 q).
cut (m < m0). intro.
Step_final ([0][+] ([0]:R)).
apply lt_trans with n; auto.
Qed.
Lemma degree_minus_lft : forall (p q : RX) m n,
degree_le m p -> degree n q -> m < n -> degree n (q[-]p).
Proof.
intros.
apply degree_wd with ( [--]p[+]q).
Step_final (q[+][--]p).
apply degree_plus_rht with m.
apply degree_le_inv. auto. auto. auto.
Qed.
Lemma monic_plus : forall (p q : RX) m n,
degree_le m p -> monic n q -> m < n -> monic n (p[+]q).
Proof.
unfold monic in |- *. unfold degree_le in |- *. intros.
elim H0. clear H0. intros.
split.
astepl (nth_coeff n p[+]nth_coeff n q).
astepl ([0][+]nth_coeff n q).
Step_final (nth_coeff n q).
intros.
astepl (nth_coeff m0 p[+]nth_coeff m0 q).
cut (m < m0). intro.
Step_final ([0][+] ([0]:R)).
apply lt_trans with n; auto.
Qed.
Lemma monic_minus : forall (p q : RX) m n,
degree_le m p -> monic n q -> m < n -> monic n (q[-]p).
Proof.
intros.
apply monic_wd with ( [--]p[+]q).
Step_final (q[+][--]p).
apply monic_plus with m.
apply degree_le_inv. auto. auto. auto.
Qed.
Lemma degree_le_mult : forall (p q : RX) m n,
degree_le m p -> degree_le n q -> degree_le (m + n) (p[*]q).
Proof.
unfold degree_le in |- *. intros.
astepl (Sum 0 m0 (fun i : nat => nth_coeff i p[*]nth_coeff (m0 - i) q)).
apply Sum_zero. auto with arith.
intros.
cut ({m < i} + {n < m0 - i}). intro.
elim H4; clear H4; intros.
Step_final ([0][*]nth_coeff (m0 - i) q).
Step_final (nth_coeff i p[*][0]).
elim (lt_eq_lt_dec m i); intro.
elim a; intro.
auto.
right.
lia.
right.
lia.
Qed.
Lemma degree_le_Product (l: list (cpoly R)) n:
(forall p, In p l -> degree_le n p) ->
degree_le (length l * n) (cr_Product l).
Proof.
induction l; intros.
apply (degree_le_c_ [1]).
change (degree_le (n + length l * n) (a [*] cr_Product l)).
apply degree_le_mult; intuition.
Qed.
Lemma degree_le_mult_constant_l (p: cpoly R) (x: R) (n: nat):
degree_le n p -> degree_le n (_C_ x [*] p).
Proof with auto.
intros.
replace n with (0 + n)%nat...
apply degree_le_mult...
apply degree_le_c_.
Qed.
Lemma degree_le_mult_constant_r (p: cpoly R) (x: R) (n: nat):
degree_le n p -> degree_le n (p [*] _C_ x).
Proof with auto.
intros.
replace n with (n + 0)%nat...
apply degree_le_mult...
apply degree_le_c_.
Qed.
Lemma degree_mult_aux : forall (p q : RX) m n, degree_le m p -> degree_le n q ->
nth_coeff (m + n) (p[*]q) [=] nth_coeff m p[*]nth_coeff n q.
Proof.
unfold degree_le in |- *. intros.
astepl (Sum 0 (m + n) (fun i : nat => nth_coeff i p[*]nth_coeff (m + n - i) q)).
astepl (Sum 0 m (fun i : nat => nth_coeff i p[*]nth_coeff (m + n - i) q) [+]
Sum (S m) (m + n) (fun i : nat => nth_coeff i p[*]nth_coeff (m + n - i) q)).
astepr (nth_coeff m p[*]nth_coeff n q[+][0]).
apply bin_op_wd_unfolded.
elim (O_or_S m); intro y.
elim y. clear y. intros x y. rewrite <- y in H. rewrite <- y.
apply eq_transitive_unfolded with
(Sum 0 x (fun i : nat => nth_coeff i p[*]nth_coeff (S x + n - i) q) [+]
nth_coeff (S x) p[*]nth_coeff (S x + n - S x) q).
apply Sum_last with (f := fun i : nat => nth_coeff i p[*]nth_coeff (S x + n - i) q).
astepr ([0][+]nth_coeff (S x) p[*]nth_coeff n q).
apply bin_op_wd_unfolded.
apply Sum_zero. auto with arith. intros.
cut (n < S x + n - i). intro.
Step_final (nth_coeff i p[*][0]).
lia.
replace (S x + n - S x) with n. algebra. auto with arith.
rewrite <- y in H. rewrite <- y.
pattern n at 2 in |- *. replace n with (0 + n - 0).
apply Sum_one with (f := fun i : nat => nth_coeff i p[*]nth_coeff (0 + n - i) q).
auto with arith.
apply Sum_zero. auto with arith. intros.
cut (m < i). intro.
Step_final ([0][*]nth_coeff (m + n - i) q).
auto.
Qed.
Lemma lead_coeff_product_1 (n: nat) (l: list (cpoly R)):
(forall p, In p l -> (nth_coeff n p [=] [1] /\ degree_le n p)) ->
nth_coeff (length l * n) (cr_Product l) [=] [1].
Proof with auto.
intro H.
induction l.
simpl. reflexivity.
change (nth_coeff (n + length l * n) (a [*] cr_Product l)[=][1]).
rewrite degree_mult_aux.
setoid_replace (nth_coeff n a) with ([1]:R).
rewrite IHl.
apply mult_one.
intros. apply H...
apply H...
apply H...
apply degree_le_Product.
intros. apply H...
Qed.
Hint Resolve degree_mult_aux: algebra.
Lemma monic_mult : forall (p q : RX) m n,
monic m p -> monic n q -> monic (m + n) (p[*]q).
Proof.
unfold monic in |- *. intros.
elim H. clear H. intros. elim H0. clear H0. intros. split.
astepl (nth_coeff m p[*]nth_coeff n q).
Step_final ([1][*] ([1]:R)).
apply degree_le_mult; auto.
Qed.
Lemma degree_le_nexp : forall (p : RX) m n,
degree_le m p -> degree_le (m * n) (p[^]n).
Proof.
intros. induction n as [| n Hrecn]; intros.
replace (m * 0) with 0.
apply degree_le_wd with (_C_ ([1]:R)). algebra.
apply degree_le_c_.
auto.
replace (m * S n) with (m * n + m).
apply degree_le_wd with (p[^]n[*]p). algebra.
apply degree_le_mult; auto.
auto.
Qed.
Lemma monic_nexp : forall (p : RX) m n, monic m p -> monic (m * n) (p[^]n).
Proof.
intros. induction n as [| n Hrecn]; intros.
replace (m * 0) with 0.
apply monic_wd with (_C_ ([1]:R)). algebra.
apply monic_c_one.
auto.
replace (m * S n) with (m * n + m).
apply monic_wd with (p[^]n[*]p). algebra.
apply monic_mult; auto.
auto.
Qed.
Lemma lt_i_lth_of_poly : forall i (p : RX),
nth_coeff i p [#] [0] -> i < lth_of_poly p.
Proof.
intros i. induction i as [| i Hreci]; intros; rename X into H.
induction p as [| s p Hrecp]; intros.
simpl in H. elim (ap_irreflexive_unfolded _ _ H).
simpl in |- *. auto with arith.
induction p as [| s p Hrecp]; intros.
simpl in H. elim (ap_irreflexive_unfolded _ _ H).
simpl in |- *. simpl in H. apply lt_n_S. auto.
Qed.
Lemma poly_degree_lth : forall p : RX, degree_le (lth_of_poly p) p.
Proof.
unfold degree_le in |- *. intros. apply not_ap_imp_eq. intro.
elim (lt_not_le _ _ H). apply lt_le_weak.
apply lt_i_lth_of_poly. auto.
Qed.
Lemma Cpoly_ex_degree : forall p : RX, {n : nat | degree_le n p}.
Proof.
intros. exists (lth_of_poly p). apply poly_degree_lth.
Qed.
Lemma poly_as_sum'' : forall (p : RX) n,
degree_le n p -> p [=] Sum 0 n (fun i => _C_ (nth_coeff i p) [*]_X_[^]i).
Proof.
unfold degree_le in |- *. intros. apply all_nth_coeff_eq_imp. intros.
apply eq_symmetric_unfolded.
apply eq_transitive_unfolded with
(Sum 0 n (fun i0 : nat => nth_coeff i (_C_ (nth_coeff i0 p) [*]_X_[^]i0))).
apply nth_coeff_sum with (p_ := fun i : nat => _C_ (nth_coeff i p) [*]_X_[^]i).
apply eq_transitive_unfolded
with (Sum 0 n (fun i0 : nat => nth_coeff i0 p[*]nth_coeff i (_X_[^]i0))).
apply Sum_wd. intros. algebra.
elim (le_lt_dec i n); intros.
astepr (nth_coeff i p[*][1]).
astepr (nth_coeff i p[*]nth_coeff i (_X_[^]i)).
apply Sum_term with (i := i) (f := fun i0 : nat => nth_coeff i0 p[*]nth_coeff i (_X_[^]i0)).
auto with arith. auto.
intros.
Step_final (nth_coeff j p[*][0]).
astepr ([0]:R).
apply Sum_zero. auto with arith. intros.
cut (i <> i0). intro.
Step_final (nth_coeff i0 p[*][0]).
intro; rewrite <- H2 in H1.
apply (le_not_lt i n); auto.
Qed.
Hint Resolve poly_as_sum'': algebra.
Lemma poly_as_sum' : forall p : RX,
p [=] Sum 0 (lth_of_poly p) (fun i => _C_ (nth_coeff i p) [*]_X_[^]i).
Proof.
intros. apply poly_as_sum''. apply poly_degree_lth.
Qed.
Lemma poly_as_sum : forall (p : RX) n, degree_le n p ->
forall x, p ! x [=] Sum 0 n (fun i => nth_coeff i p[*]x[^]i).
Proof.
intros.
astepl (Sum 0 n (fun i : nat => _C_ (nth_coeff i p) [*]_X_[^]i)) ! x.
apply eq_transitive_unfolded with (Sum 0 n (fun i : nat => (_C_ (nth_coeff i p) [*]_X_[^]i) ! x)).
apply Sum_cpoly_ap with (f := fun i : nat => _C_ (nth_coeff i p) [*]_X_[^]i).
apply Sum_wd. intros.
astepl ((_C_ (nth_coeff i p)) ! x[*] (_X_[^]i) ! x).
Step_final (nth_coeff i p[*]_X_ ! x[^]i).
Qed.
Lemma degree_le_zero : forall p : RX, degree_le 0 p -> {a : R | p [=] _C_ a}.
Proof.
unfold degree_le in |- *. intros.
exists (nth_coeff 0 p).
apply all_nth_coeff_eq_imp. intros.
elim (O_or_S i); intro y.
elim y. clear y. intros x y. rewrite <- y.
cut (0 < S x). intro. Step_final ([0]:R). auto with arith.
rewrite <- y. algebra.
Qed.
Lemma degree_le_1_imp : forall p : RX,
degree_le 1 p -> {a : R | {b : R | p [=] _C_ a[*]_X_[+]_C_ b}}.
Proof.
unfold degree_le in |- *. intros.
exists (nth_coeff 1 p). exists (nth_coeff 0 p).
apply all_nth_coeff_eq_imp. intros.
elim i; intros. simpl in |- *. ring.
elim n; intros.
simpl in |- *. algebra.
simpl in |- *. apply H. auto with arith.
Qed.
Lemma degree_le_cpoly_linear : forall (p : cpoly R) c n,
degree_le (S n) (c[+X*]p) -> degree_le n p.
Proof.
unfold degree_le in |- *. intros.
change (nth_coeff (S m) (cpoly_linear _ c p) [=] [0]) in |- *.
apply H. auto with arith.
Qed.
Lemma degree_le_cpoly_linear_inv (p: cpoly R) (c: R) (n: nat):
degree_le n p -> degree_le (S n) (c[+X*]p).
Proof. intros H [|m] E. inversion E. apply (H m). auto with arith. Qed.
Lemma monic_cpoly_linear : forall (p : cpoly R) c n, monic (S n) (c[+X*]p) -> monic n p.
Proof.
unfold monic in |- *. intros. elim H. clear H. intros. split. auto.
apply degree_le_cpoly_linear with c. auto.
Qed.
Lemma monic_one : forall (p : cpoly R) c, monic 1 (c[+X*]p) -> forall x, p ! x [=] [1].
Proof.
intros. cut (monic 0 p). unfold monic in |- *. intros. elim H0. clear H0.
intros H0 H1.
elim (degree_le_zero _ H1). intro d. intros.
astepl (_C_ d) ! x.
astepl d.
astepl (nth_coeff 0 (_C_ d)).
Step_final (nth_coeff 0 p).
apply monic_cpoly_linear with c. auto.
Qed.
Lemma monic_apzero : forall (p : RX) n, monic n p -> p [#] [0].
Proof.
unfold monic in |- *. intros.
elim H. clear H. intros.
apply nth_coeff_ap_zero_imp with n.
astepl ([1]:R). apply one_ap_zero.
Qed.
End Degree_props.
Hint Resolve poly_as_sum'' poly_as_sum' poly_as_sum: algebra.
Hint Resolve degree_mult_aux: algebra.
Section degree_props_Field.
(**
** Degrees of polynomials over a field
%\begin{convention}% Let [F] be a field and write [FX] for the ring of
polynomials over [F].
%\end{convention}%
*)
Variable F : CField.
(* begin hide *)
Notation FX := (cpoly_cring F).
(* end hide *)
Lemma degree_mult : forall (p q : FX) m n,
degree m p -> degree n q -> degree (m + n) (p[*]q).
Proof.
unfold degree in |- *. intros. rename X into H. rename X0 into H0.
elim H. clear H. intros H1 H2. elim H0. clear H0. intros H3 H4.
split.
astepl (nth_coeff m p[*]nth_coeff n q). algebra.
apply degree_le_mult; auto.
Qed.
Lemma degree_nexp : forall (p : FX) m n, degree m p -> degree (m * n) (p[^]n).
Proof.
intros. induction n as [| n Hrecn]; intros.
replace (m * 0) with 0.
apply degree_wd with (_C_ ([1]:F)). algebra.
apply degree_c_. algebra.
auto.
replace (m * S n) with (m * n + m).
apply degree_wd with (p[^]n[*]p). algebra.
apply degree_mult; auto.
auto.
Qed.
Lemma degree_le_mult_imp : forall (p q : FX) m n,
degree m p -> degree_le (m + n) (p[*]q) -> degree_le n q.
Proof.
unfold degree in |- *. unfold degree_le in |- *. intros. rename H0 into H1. rename H into H0. rename X into H. elim H. clear H. intros H2 H3.
elim (Cpoly_ex_degree _ q). unfold degree_le in |- *. intro N. intro H4.
(* Set_ not necessary *)
cut (forall k i : nat, n < i -> N - k < i -> nth_coeff i q [=] [0]). intro H5.
elim (le_lt_dec m0 N); intros H6.
replace m0 with (N - (N - m0)). apply H5 with (N - n).
lia. lia. lia.
apply H4; auto.
intro. induction k as [| k Hreck]; intros.
apply H4. rewrite <- minus_n_O in H5; auto.
elim (le_lt_eq_dec (N - k) i); try intro y. auto. rewrite y in Hreck.
apply mult_cancel_lft with (nth_coeff m p). auto. astepr ([0]:F).
apply eq_transitive_unfolded with
(Sum 0 (m + i) (fun j : nat => nth_coeff j p[*]nth_coeff (m + i - j) q)).
pattern i at 1 in |- *. replace i with (m + i - m).
apply eq_symmetric_unfolded.
apply Sum_term with (f := fun j : nat => nth_coeff j p[*]nth_coeff (m + i - j) q).
auto with arith. auto with arith.
intros. elim (le_lt_dec j m); intros.
cut (i < m + i - j). intro.
cut (n < m + i - j). intro.
Step_final (nth_coeff j p[*][0]).
lia. lia.
Step_final ([0][*]nth_coeff (m + i - j) q).
auto with arith.
astepl (nth_coeff (m + i) (p[*]q)).
cut (m + n < m + i). intro.
auto.
auto with arith.
lia.
Qed.
Lemma degree_mult_imp : forall (p q : FX) m n,
degree m p -> degree (m + n) (p[*]q) -> degree n q.
Proof.
unfold degree in |- *. intros. rename X into H. rename X0 into H0.
elim H. clear H. intros H H1.
elim H0. clear H0. intros H0 H2.
cut (degree_le n q). intro H3. split.
apply mult_cancel_ap_zero_rht with (nth_coeff m p).
astepl (nth_coeff (m + n) (p[*]q)). auto.
assumption.
apply degree_le_mult_imp with p m; auto.
unfold degree in |- *. split. auto.
assumption.
Qed.
End degree_props_Field.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__EINVP_FUNCTIONAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVP_FUNCTIONAL_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
`define STRINGIFY(x) `"x`"
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
//======================================================================
module t;
integer file;
integer r_i;
byte r_upb[20:10];
byte r_dnb[20:10];
reg [13:0] r_ups[20:10];
reg [13:0] r_dns[10:20];
reg [30:0] r_upi[20:10];
reg [30:0] r_dni[10:20];
reg [61:0] r_upq[20:10];
reg [61:0] r_dnq[10:20];
reg [71:0] r_upw[20:10];
reg [71:0] r_dnw[10:20];
task clear;
// Initialize memories to zero,
// avoid differences between 2-state and 4-state.
r_i = ~0;
foreach (r_upb[i]) r_upb[i] = ~0;
foreach (r_dnb[i]) r_dnb[i] = ~0;
foreach (r_ups[i]) r_ups[i] = ~0;
foreach (r_dns[i]) r_dns[i] = ~0;
foreach (r_upi[i]) r_upi[i] = ~0;
foreach (r_dni[i]) r_dni[i] = ~0;
foreach (r_upq[i]) r_upq[i] = ~0;
foreach (r_dnq[i]) r_dnq[i] = ~0;
foreach (r_upw[i]) r_upw[i] = ~0;
foreach (r_dnw[i]) r_dnw[i] = ~0;
// Open file
$fclose(file);
file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_fread.mem"}, "r");
if ($feof(file)) $stop;
endtask
task dump;
$write("Dump:");
$write("\n r_i:"); $write(" %x",r_i);
$write("\n r_upb:"); foreach (r_upb[i]) $write(" %x", r_upb[i]);
$write("\n r_dnb:"); foreach (r_dnb[i]) $write(" %x", r_dnb[i]);
$write("\n r_ups:"); foreach (r_ups[i]) $write(" %x", r_ups[i]);
$write("\n r_dns:"); foreach (r_dns[i]) $write(" %x", r_dns[i]);
$write("\n r_upi:"); foreach (r_upi[i]) $write(" %x", r_upi[i]);
$write("\n r_dni:"); foreach (r_dni[i]) $write(" %x", r_dni[i]);
$write("\n r_upq:"); foreach (r_upq[i]) $write(" %x", r_upq[i]);
$write("\n r_dnq:"); foreach (r_dnq[i]) $write(" %x", r_dnq[i]);
$write("\n r_upw:"); foreach (r_upw[i]) $write(" %x", r_upw[i]);
$write("\n r_dnw:"); foreach (r_dnw[i]) $write(" %x", r_dnw[i]);
$write("\n\n");
endtask
integer code;
initial begin
clear;
code = $fread(r_i, file); `checkd(code, 4);
code = $fread(r_upb, file); `checkd(code, 11);
code = $fread(r_dnb, file); `checkd(code, 11);
code = $fread(r_ups, file); `checkd(code, 22);
code = $fread(r_dns, file); `checkd(code, 22);
code = $fread(r_upi, file); `checkd(code, 44);
code = $fread(r_dni, file); `checkd(code, 44);
code = $fread(r_upq, file); `checkd(code, 88);
code = $fread(r_dnq, file); `checkd(code, 88);
code = $fread(r_upw, file); `checkd(code, 99);
code = $fread(r_dnw, file); `checkd(code, 99);
dump;
clear;
code = $fread(r_upb, file, 15); `checkd(code, 6);
code = $fread(r_ups, file, 15, 2); `checkd(code, 4);
dump;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: ff_40x32_fwft.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ff_40x32_fwft (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [39:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [39:0] q;
output [4:0] usedw;
wire [4:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [39:0] sub_wire3;
wire [4:0] usedw = sub_wire0[4:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [39:0] q = sub_wire3[39:0];
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_empty (),
.almost_full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Cyclone V",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 40,
scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "40"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "40"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=MLAB"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "40"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 40 0 INPUT NODEFVAL "data[39..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 40 0 OUTPUT NODEFVAL "q[39..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 5 0 OUTPUT NODEFVAL "usedw[4..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 40 0 data 0 0 40 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 40 0 @q 0 0 40 0
// Retrieval info: CONNECT: usedw 0 0 5 0 @usedw 0 0 5 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ff_40x32_fwft_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22A_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O22A_PP_SYMBOL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o22a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22A_PP_SYMBOL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_pipe_lane.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_pipe_lane.v //
// Description : Implements the PIPE interface PIPELINE for all per lane //
// interface signals //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_pipe_lane.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_pipe_lane #
(
parameter TCQ = 100,
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
) (
output wire [ 1:0] pipe_rx_char_is_k_o ,// Pipelined PIPE Rx Char Is K
output wire [31:0] pipe_rx_data_o ,// Pipelined PIPE Rx Data
output wire pipe_rx_valid_o ,// Pipelined PIPE Rx Valid
output wire pipe_rx_data_valid_o ,// Pipelined PIPE Rx Data Valid
output wire [ 2:0] pipe_rx_status_o ,// Pipelined PIPE Rx Status
output wire pipe_rx_phy_status_o ,// Pipelined PIPE Rx Phy Status
output wire pipe_rx_elec_idle_o ,// Pipelined PIPE Rx Electrical Idle
output wire pipe_rx_eqdone_o ,// Pipelined PIPE Rx Eq
output wire pipe_rx_eqlpadaptdone_o ,// Pipelined PIPE Rx Eq
output wire pipe_rx_eqlplffssel_o ,// Pipelined PIPE Rx Eq
output wire [17:0] pipe_rx_eqlpnewtxcoefforpreset_o,// Pipelined PIPE Rx Eq
output wire pipe_rx_startblock_o ,// Pipelined PIPE Rx Start Block
output wire [ 1:0] pipe_rx_syncheader_o ,// Pipelined PIPE Rx Sync Header
output wire pipe_rx_slide_o ,// Pipelined PIPE Rx Slide
output wire pipe_rx_syncdone_o ,// Pipelined PIPE Rx Sync done
input wire pipe_rx_polarity_i ,// PIPE Rx Polarity
input wire [ 1:0] pipe_rx_eqcontrol_i ,// PIPE Rx Eq control
input wire [ 5:0] pipe_rx_eqlplffs_i ,// PIPE Rx Eq
input wire [ 3:0] pipe_rx_eqlptxpreset_i ,// PIPE Rx Eq
input wire [ 2:0] pipe_rx_eqpreset_i ,// PIPE Rx Eq
output wire [17:0] pipe_tx_eqcoeff_o ,// Pipelined Tx Eq Coefficient
output wire pipe_tx_eqdone_o ,// Pipelined Tx Eq Done
input wire pipe_tx_compliance_i ,// PIPE Tx Compliance
input wire [ 1:0] pipe_tx_char_is_k_i ,// PIPE Tx Char Is K
input wire [31:0] pipe_tx_data_i ,// PIPE Tx Data
input wire pipe_tx_elec_idle_i ,// PIPE Tx Electrical Idle
input wire [ 1:0] pipe_tx_powerdown_i ,// PIPE Tx Powerdown
input wire pipe_tx_datavalid_i ,// PIPE Tx Data Valid
input wire pipe_tx_startblock_i ,// PIPE Tx Start Block
input wire [ 1:0] pipe_tx_syncheader_i ,// PIPE Tx Sync Header
input wire [ 1:0] pipe_tx_eqcontrol_i ,// PIPE Tx Eq Control
input wire [ 5:0] pipe_tx_eqdeemph_i ,// PIPE Tx Eq Deemphesis
input wire [ 3:0] pipe_tx_eqpreset_i ,// PIPE Tx Preset
input wire [ 1:0] pipe_rx_char_is_k_i ,// PIPE Rx Char Is K
input wire [31:0] pipe_rx_data_i ,// PIPE Rx Data
input wire pipe_rx_valid_i ,// PIPE Rx Valid
input wire pipe_rx_data_valid_i ,// PIPE Rx Data Valid
input wire [ 2:0] pipe_rx_status_i ,// PIPE Rx Status
input wire pipe_rx_phy_status_i ,// PIPE Rx Phy Status
input wire pipe_rx_elec_idle_i ,// PIPE Rx Electrical Idle
input wire pipe_rx_eqdone_i ,// PIPE Rx Eq
input wire pipe_rx_eqlpadaptdone_i ,// PIPE Rx Eq
input wire pipe_rx_eqlplffssel_i ,// PIPE Rx Eq
input wire [17:0] pipe_rx_eqlpnewtxcoefforpreset_i,// PIPE Rx Eq
input wire pipe_rx_startblock_i ,// PIPE Rx Start Block
input wire [ 1:0] pipe_rx_syncheader_i ,// PIPE Rx Sync Header
input wire pipe_rx_slide_i ,// PIPE Rx Slide
input wire pipe_rx_syncdone_i ,// PIPE Rx Sync done
output wire pipe_rx_polarity_o ,// Pipelined PIPE Rx Polarity
output wire [ 1:0] pipe_rx_eqcontrol_o ,// Pipelined PIPE Rx Eq control
output wire [ 5:0] pipe_rx_eqlplffs_o ,// Pipelined PIPE Rx Eq
output wire [ 3:0] pipe_rx_eqlptxpreset_o ,// Pipelined PIPE Rx Eq
output wire [ 2:0] pipe_rx_eqpreset_o ,// Pipelined PIPE Rx Eq
input wire [17:0] pipe_tx_eqcoeff_i ,// PIPE Tx Eq Coefficient
input wire pipe_tx_eqdone_i ,// PIPE Tx Eq Done
output wire pipe_tx_compliance_o ,// Pipelined PIPE Tx Compliance
output wire [ 1:0] pipe_tx_char_is_k_o ,// Pipelined PIPE Tx Char Is K
output wire [31:0] pipe_tx_data_o ,// Pipelined PIPE Tx Data
output wire pipe_tx_elec_idle_o ,// Pipelined PIPE Tx Electrical Idle
output wire [ 1:0] pipe_tx_powerdown_o ,// Pipelined PIPE Tx Powerdown
output wire pipe_tx_datavalid_o ,// Pipelined PIPE Tx Data Valid
output wire pipe_tx_startblock_o ,// Pipelined PIPE Tx Start Block
output wire [ 1:0] pipe_tx_syncheader_o ,// Pipelined PIPE Tx Sync Header
output wire [ 1:0] pipe_tx_eqcontrol_o ,// Pipelined PIPE Tx Eq Control
output wire [ 5:0] pipe_tx_eqdeemph_o ,// Pipelined PIPE Tx Eq Deemphesis
output wire [ 3:0] pipe_tx_eqpreset_o ,// Pipelined PIPE Tx Preset
input wire pipe_clk ,// PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
reg [ 1:0] pipe_rx_char_is_k_q ;
reg [31:0] pipe_rx_data_q ;
reg pipe_rx_valid_q ;
reg pipe_rx_data_valid_q ;
reg [ 2:0] pipe_rx_status_q ;
reg pipe_rx_phy_status_q ;
reg pipe_rx_elec_idle_q ;
reg pipe_rx_eqdone_q ;
reg pipe_rx_eqlpadaptdone_q ;
reg pipe_rx_eqlplffssel_q ;
reg [17:0] pipe_rx_eqlpnewtxcoefforpreset_q ;
reg pipe_rx_startblock_q ;
reg [ 1:0] pipe_rx_syncheader_q ;
reg pipe_rx_slide_q ;
reg pipe_rx_syncdone_q ;
reg pipe_rx_polarity_q ;
reg [ 1:0] pipe_rx_eqcontrol_q ;
reg [ 5:0] pipe_rx_eqlplffs_q ;
reg [ 3:0] pipe_rx_eqlptxpreset_q ;
reg [ 2:0] pipe_rx_eqpreset_q ;
reg [17:0] pipe_tx_eqcoeff_q ;
reg pipe_tx_eqdone_q ;
reg pipe_tx_compliance_q ;
reg [ 1:0] pipe_tx_char_is_k_q ;
reg [31:0] pipe_tx_data_q ;
reg pipe_tx_elec_idle_q ;
reg [ 1:0] pipe_tx_powerdown_q ;
reg pipe_tx_datavalid_q ;
reg pipe_tx_startblock_q ;
reg [ 1:0] pipe_tx_syncheader_q ;
reg [ 1:0] pipe_tx_eqcontrol_q ;
reg [ 5:0] pipe_tx_eqdeemph_q ;
reg [ 3:0] pipe_tx_eqpreset_q ;
reg [ 1:0] pipe_rx_char_is_k_qq ;
reg [31:0] pipe_rx_data_qq ;
reg pipe_rx_valid_qq ;
reg pipe_rx_data_valid_qq ;
reg [ 2:0] pipe_rx_status_qq ;
reg pipe_rx_phy_status_qq ;
reg pipe_rx_elec_idle_qq ;
reg pipe_rx_eqdone_qq ;
reg pipe_rx_eqlpadaptdone_qq ;
reg pipe_rx_eqlplffssel_qq ;
reg [17:0] pipe_rx_eqlpnewtxcoefforpreset_qq ;
reg pipe_rx_startblock_qq ;
reg [ 1:0] pipe_rx_syncheader_qq ;
reg pipe_rx_slide_qq ;
reg pipe_rx_syncdone_qq ;
reg pipe_rx_polarity_qq ;
reg [ 1:0] pipe_rx_eqcontrol_qq ;
reg [ 5:0] pipe_rx_eqlplffs_qq ;
reg [ 3:0] pipe_rx_eqlptxpreset_qq ;
reg [ 2:0] pipe_rx_eqpreset_qq ;
reg [17:0] pipe_tx_eqcoeff_qq ;
reg pipe_tx_eqdone_qq ;
reg pipe_tx_compliance_qq ;
reg [ 1:0] pipe_tx_char_is_k_qq ;
reg [31:0] pipe_tx_data_qq ;
reg pipe_tx_elec_idle_qq ;
reg [ 1:0] pipe_tx_powerdown_qq ;
reg pipe_tx_datavalid_qq ;
reg pipe_tx_startblock_qq ;
reg [ 1:0] pipe_tx_syncheader_qq ;
reg [ 1:0] pipe_tx_eqcontrol_qq ;
reg [ 5:0] pipe_tx_eqdeemph_qq ;
reg [ 3:0] pipe_tx_eqpreset_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i ;
assign pipe_rx_data_o = pipe_rx_data_i ;
assign pipe_rx_valid_o = pipe_rx_valid_i ;
assign pipe_rx_data_valid_o = pipe_rx_data_valid_i ;
assign pipe_rx_status_o = pipe_rx_status_i ;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_i ;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i ;
assign pipe_rx_eqdone_o = pipe_rx_eqdone_i ;
assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_i ;
assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_i ;
assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_i ;
assign pipe_rx_startblock_o = pipe_rx_startblock_i ;
assign pipe_rx_syncheader_o = pipe_rx_syncheader_i ;
assign pipe_rx_slide_o = pipe_rx_slide_i ;
assign pipe_rx_syncdone_o = pipe_rx_syncdone_i ;
assign pipe_rx_polarity_o = pipe_rx_polarity_i ;
assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_i ;
assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_i ;
assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_i ;
assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_i ;
assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_i ;
assign pipe_tx_eqdone_o = pipe_tx_eqdone_i ;
assign pipe_tx_compliance_o = pipe_tx_compliance_i ;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i ;
assign pipe_tx_data_o = pipe_tx_data_i ;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i ;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_i ;
assign pipe_tx_datavalid_o = pipe_tx_datavalid_i ;
assign pipe_tx_startblock_o = pipe_tx_startblock_i ;
assign pipe_tx_syncheader_o = pipe_tx_syncheader_i ;
assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_i ;
assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_i ;
assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_i ;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
always @(posedge pipe_clk) begin
if (!rst_n)
begin
pipe_rx_char_is_k_q <= #TCQ 2'b00;
pipe_rx_data_q <= #TCQ 32'h00000000;
pipe_rx_valid_q <= #TCQ 1'b0;
pipe_rx_data_valid_q <= #TCQ 1'b0;
pipe_rx_status_q <= #TCQ 2'b00;
pipe_rx_phy_status_q <= #TCQ 1'b0;
pipe_rx_elec_idle_q <= #TCQ 1'b1;
pipe_rx_eqdone_q <= #TCQ 1'b0;
pipe_rx_eqlpadaptdone_q <= #TCQ 1'b0;
pipe_rx_eqlplffssel_q <= #TCQ 1'b0;
pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ 17'b00000000000000000;
pipe_rx_startblock_q <= #TCQ 1'b0;
pipe_rx_syncheader_q <= #TCQ 2'b00;
pipe_rx_slide_q <= #TCQ 1'b0;
pipe_rx_syncdone_q <= #TCQ 1'b0;
pipe_rx_polarity_q <= #TCQ 17'b00000000000000000;
pipe_rx_eqcontrol_q <= #TCQ 1'b0;
pipe_rx_eqlplffs_q <= #TCQ 1'b0;
pipe_rx_eqlptxpreset_q <= #TCQ 2'b00;
pipe_rx_eqpreset_q <= #TCQ 6'b000000;
pipe_tx_eqcoeff_q <= #TCQ 4'h0;
pipe_tx_eqdone_q <= #TCQ 3'b000;
pipe_tx_compliance_q <= #TCQ 1'b0;
pipe_tx_char_is_k_q <= #TCQ 2'b00;
pipe_tx_data_q <= #TCQ 32'h00000000;
pipe_tx_elec_idle_q <= #TCQ 1'b1;
pipe_tx_powerdown_q <= #TCQ 2'b00;
pipe_tx_datavalid_q <= #TCQ 1'b0;
pipe_tx_startblock_q <= #TCQ 1'b0;
pipe_tx_syncheader_q <= #TCQ 2'b00;
pipe_tx_eqcontrol_q <= #TCQ 2'b00;
pipe_tx_eqdeemph_q <= #TCQ 6'b000000;
pipe_tx_eqpreset_q <= #TCQ 4'h0;
end
else
begin
pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i ;
pipe_rx_data_q <= #TCQ pipe_rx_data_i ;
pipe_rx_valid_q <= #TCQ pipe_rx_valid_i ;
pipe_rx_data_valid_q <= #TCQ pipe_rx_data_valid_i ;
pipe_rx_status_q <= #TCQ pipe_rx_status_i ;
pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i ;
pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i ;
pipe_rx_eqdone_q <= #TCQ pipe_rx_eqdone_i ;
pipe_rx_eqlpadaptdone_q <= #TCQ pipe_rx_eqlpadaptdone_i ;
pipe_rx_eqlplffssel_q <= #TCQ pipe_rx_eqlplffssel_i ;
pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ pipe_rx_eqlpnewtxcoefforpreset_i ;
pipe_rx_startblock_q <= #TCQ pipe_rx_startblock_i ;
pipe_rx_syncheader_q <= #TCQ pipe_rx_syncheader_i ;
pipe_rx_slide_q <= #TCQ pipe_rx_slide_i ;
pipe_rx_syncdone_q <= #TCQ pipe_rx_syncdone_i ;
pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i ;
pipe_rx_eqcontrol_q <= #TCQ pipe_rx_eqcontrol_i ;
pipe_rx_eqlplffs_q <= #TCQ pipe_rx_eqlplffs_i ;
pipe_rx_eqlptxpreset_q <= #TCQ pipe_rx_eqlptxpreset_i ;
pipe_rx_eqpreset_q <= #TCQ pipe_rx_eqpreset_i ;
pipe_tx_eqcoeff_q <= #TCQ pipe_tx_eqcoeff_i ;
pipe_tx_eqdone_q <= #TCQ pipe_tx_eqdone_i ;
pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i ;
pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i ;
pipe_tx_data_q <= #TCQ pipe_tx_data_i ;
pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i ;
pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i ;
pipe_tx_datavalid_q <= #TCQ pipe_tx_datavalid_i ;
pipe_tx_startblock_q <= #TCQ pipe_tx_startblock_i ;
pipe_tx_syncheader_q <= #TCQ pipe_tx_syncheader_i ;
pipe_tx_eqcontrol_q <= #TCQ pipe_tx_eqcontrol_i ;
pipe_tx_eqdeemph_q <= #TCQ pipe_tx_eqdeemph_i ;
pipe_tx_eqpreset_q <= #TCQ pipe_tx_eqpreset_i ;
end
end
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_q ;
assign pipe_rx_data_o = pipe_rx_data_q ;
assign pipe_rx_valid_o = pipe_rx_valid_q ;
assign pipe_rx_data_valid_o = pipe_rx_data_valid_q ;
assign pipe_rx_status_o = pipe_rx_status_q ;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_q ;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_q ;
assign pipe_rx_eqdone_o = pipe_rx_eqdone_q ;
assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_q ;
assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_q ;
assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_q ;
assign pipe_rx_startblock_o = pipe_rx_startblock_q ;
assign pipe_rx_syncheader_o = pipe_rx_syncheader_q ;
assign pipe_rx_slide_o = pipe_rx_slide_q ;
assign pipe_rx_syncdone_o = pipe_rx_syncdone_q ;
assign pipe_rx_polarity_o = pipe_rx_polarity_q ;
assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_q ;
assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_q ;
assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_q ;
assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_q ;
assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_q ;
assign pipe_tx_eqdone_o = pipe_tx_eqdone_q ;
assign pipe_tx_compliance_o = pipe_tx_compliance_q ;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_q ;
assign pipe_tx_data_o = pipe_tx_data_q ;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_q ;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_q ;
assign pipe_tx_datavalid_o = pipe_tx_datavalid_q ;
assign pipe_tx_startblock_o = pipe_tx_startblock_q ;
assign pipe_tx_syncheader_o = pipe_tx_syncheader_q ;
assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_q ;
assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_q ;
assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_q ;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
always @(posedge pipe_clk) begin
if (!rst_n)
begin
pipe_rx_char_is_k_q <= #TCQ 2'b00;
pipe_rx_data_q <= #TCQ 32'h00000000;
pipe_rx_valid_q <= #TCQ 1'b0;
pipe_rx_data_valid_q <= #TCQ 1'b0;
pipe_rx_status_q <= #TCQ 2'b00;
pipe_rx_phy_status_q <= #TCQ 1'b0;
pipe_rx_elec_idle_q <= #TCQ 1'b1;
pipe_rx_eqdone_q <= #TCQ 1'b0;
pipe_rx_eqlpadaptdone_q <= #TCQ 1'b0;
pipe_rx_eqlplffssel_q <= #TCQ 1'b0;
pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ 17'b00000000000000000;
pipe_rx_startblock_q <= #TCQ 1'b0;
pipe_rx_syncheader_q <= #TCQ 2'b00;
pipe_rx_slide_q <= #TCQ 1'b0;
pipe_rx_syncdone_q <= #TCQ 1'b0;
pipe_rx_polarity_q <= #TCQ 17'b00000000000000000;
pipe_rx_eqcontrol_q <= #TCQ 1'b0;
pipe_rx_eqlplffs_q <= #TCQ 1'b0;
pipe_rx_eqlptxpreset_q <= #TCQ 2'b00;
pipe_rx_eqpreset_q <= #TCQ 6'b000000;
pipe_tx_eqcoeff_q <= #TCQ 4'h0;
pipe_tx_eqdone_q <= #TCQ 3'b000;
pipe_tx_compliance_q <= #TCQ 1'b0;
pipe_tx_char_is_k_q <= #TCQ 2'b00;
pipe_tx_data_q <= #TCQ 32'h00000000;
pipe_tx_elec_idle_q <= #TCQ 1'b1;
pipe_tx_powerdown_q <= #TCQ 2'b00;
pipe_tx_datavalid_q <= #TCQ 1'b0;
pipe_tx_startblock_q <= #TCQ 1'b0;
pipe_tx_syncheader_q <= #TCQ 2'b00;
pipe_tx_eqcontrol_q <= #TCQ 2'b00;
pipe_tx_eqdeemph_q <= #TCQ 6'b000000;
pipe_tx_eqpreset_q <= #TCQ 4'h0;
pipe_rx_char_is_k_qq <= #TCQ 2'b00;
pipe_rx_data_qq <= #TCQ 32'h00000000;
pipe_rx_valid_qq <= #TCQ 1'b0;
pipe_rx_data_valid_qq <= #TCQ 1'b0;
pipe_rx_status_qq <= #TCQ 2'b00;
pipe_rx_phy_status_qq <= #TCQ 1'b0;
pipe_rx_elec_idle_qq <= #TCQ 1'b1;
pipe_rx_eqdone_qq <= #TCQ 1'b0;
pipe_rx_eqlpadaptdone_qq <= #TCQ 1'b0;
pipe_rx_eqlplffssel_qq <= #TCQ 1'b0;
pipe_rx_eqlpnewtxcoefforpreset_qq<= #TCQ 17'b00000000000000000;
pipe_rx_startblock_qq <= #TCQ 1'b0;
pipe_rx_syncheader_qq <= #TCQ 2'b00;
pipe_rx_slide_qq <= #TCQ 1'b0;
pipe_rx_syncdone_qq <= #TCQ 1'b0;
pipe_rx_polarity_qq <= #TCQ 17'b00000000000000000;
pipe_rx_eqcontrol_qq <= #TCQ 1'b0;
pipe_rx_eqlplffs_qq <= #TCQ 1'b0;
pipe_rx_eqlptxpreset_qq <= #TCQ 2'b00;
pipe_rx_eqpreset_qq <= #TCQ 6'b000000;
pipe_tx_eqcoeff_qq <= #TCQ 4'h0;
pipe_tx_eqdone_qq <= #TCQ 3'b000;
pipe_tx_compliance_qq <= #TCQ 1'b0;
pipe_tx_char_is_k_qq <= #TCQ 2'b00;
pipe_tx_data_qq <= #TCQ 32'h00000000;
pipe_tx_elec_idle_qq <= #TCQ 1'b1;
pipe_tx_powerdown_qq <= #TCQ 2'b00;
pipe_tx_datavalid_qq <= #TCQ 1'b0;
pipe_tx_startblock_qq <= #TCQ 1'b0;
pipe_tx_syncheader_qq <= #TCQ 2'b00;
pipe_tx_eqcontrol_qq <= #TCQ 2'b00;
pipe_tx_eqdeemph_qq <= #TCQ 6'b000000;
pipe_tx_eqpreset_qq <= #TCQ 4'h0;
end
else
begin
pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i ;
pipe_rx_data_q <= #TCQ pipe_rx_data_i ;
pipe_rx_valid_q <= #TCQ pipe_rx_valid_i ;
pipe_rx_data_valid_q <= #TCQ pipe_rx_data_valid_i ;
pipe_rx_status_q <= #TCQ pipe_rx_status_i ;
pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i ;
pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i ;
pipe_rx_eqdone_q <= #TCQ pipe_rx_eqdone_i ;
pipe_rx_eqlpadaptdone_q <= #TCQ pipe_rx_eqlpadaptdone_i ;
pipe_rx_eqlplffssel_q <= #TCQ pipe_rx_eqlplffssel_i ;
pipe_rx_eqlpnewtxcoefforpreset_q <= #TCQ pipe_rx_eqlpnewtxcoefforpreset_i ;
pipe_rx_startblock_q <= #TCQ pipe_rx_startblock_i ;
pipe_rx_syncheader_q <= #TCQ pipe_rx_syncheader_i ;
pipe_rx_slide_q <= #TCQ pipe_rx_slide_i ;
pipe_rx_syncdone_q <= #TCQ pipe_rx_syncdone_i ;
pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i ;
pipe_rx_eqcontrol_q <= #TCQ pipe_rx_eqcontrol_i ;
pipe_rx_eqlplffs_q <= #TCQ pipe_rx_eqlplffs_i ;
pipe_rx_eqlptxpreset_q <= #TCQ pipe_rx_eqlptxpreset_i ;
pipe_rx_eqpreset_q <= #TCQ pipe_rx_eqpreset_i ;
pipe_tx_eqcoeff_q <= #TCQ pipe_tx_eqcoeff_i ;
pipe_tx_eqdone_q <= #TCQ pipe_tx_eqdone_i ;
pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i ;
pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i ;
pipe_tx_data_q <= #TCQ pipe_tx_data_i ;
pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i ;
pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i ;
pipe_tx_datavalid_q <= #TCQ pipe_tx_datavalid_i ;
pipe_tx_startblock_q <= #TCQ pipe_tx_startblock_i ;
pipe_tx_syncheader_q <= #TCQ pipe_tx_syncheader_i ;
pipe_tx_eqcontrol_q <= #TCQ pipe_tx_eqcontrol_i ;
pipe_tx_eqdeemph_q <= #TCQ pipe_tx_eqdeemph_i ;
pipe_tx_eqpreset_q <= #TCQ pipe_tx_eqpreset_i ;
pipe_rx_char_is_k_qq <= #TCQ pipe_rx_char_is_k_q ;
pipe_rx_data_qq <= #TCQ pipe_rx_data_q ;
pipe_rx_valid_qq <= #TCQ pipe_rx_valid_q ;
pipe_rx_data_valid_qq <= #TCQ pipe_rx_data_valid_q ;
pipe_rx_status_qq <= #TCQ pipe_rx_status_q ;
pipe_rx_phy_status_qq <= #TCQ pipe_rx_phy_status_q ;
pipe_rx_elec_idle_qq <= #TCQ pipe_rx_elec_idle_q ;
pipe_rx_eqdone_qq <= #TCQ pipe_rx_eqdone_q ;
pipe_rx_eqlpadaptdone_qq <= #TCQ pipe_rx_eqlpadaptdone_q ;
pipe_rx_eqlplffssel_qq <= #TCQ pipe_rx_eqlplffssel_q ;
pipe_rx_eqlpnewtxcoefforpreset_qq<= #TCQ pipe_rx_eqlpnewtxcoefforpreset_q ;
pipe_rx_startblock_qq <= #TCQ pipe_rx_startblock_q ;
pipe_rx_syncheader_qq <= #TCQ pipe_rx_syncheader_q ;
pipe_rx_slide_qq <= #TCQ pipe_rx_slide_q ;
pipe_rx_syncdone_qq <= #TCQ pipe_rx_syncdone_q ;
pipe_rx_polarity_qq <= #TCQ pipe_rx_polarity_q ;
pipe_rx_eqcontrol_qq <= #TCQ pipe_rx_eqcontrol_q ;
pipe_rx_eqlplffs_qq <= #TCQ pipe_rx_eqlplffs_q ;
pipe_rx_eqlptxpreset_qq <= #TCQ pipe_rx_eqlptxpreset_q ;
pipe_rx_eqpreset_qq <= #TCQ pipe_rx_eqpreset_q ;
pipe_tx_eqcoeff_qq <= #TCQ pipe_tx_eqcoeff_q ;
pipe_tx_eqdone_qq <= #TCQ pipe_tx_eqdone_q ;
pipe_tx_compliance_qq <= #TCQ pipe_tx_compliance_q ;
pipe_tx_char_is_k_qq <= #TCQ pipe_tx_char_is_k_q ;
pipe_tx_data_qq <= #TCQ pipe_tx_data_q ;
pipe_tx_elec_idle_qq <= #TCQ pipe_tx_elec_idle_q ;
pipe_tx_powerdown_qq <= #TCQ pipe_tx_powerdown_q ;
pipe_tx_datavalid_qq <= #TCQ pipe_tx_datavalid_q ;
pipe_tx_startblock_qq <= #TCQ pipe_tx_startblock_q ;
pipe_tx_syncheader_qq <= #TCQ pipe_tx_syncheader_q ;
pipe_tx_eqcontrol_qq <= #TCQ pipe_tx_eqcontrol_q ;
pipe_tx_eqdeemph_qq <= #TCQ pipe_tx_eqdeemph_q ;
pipe_tx_eqpreset_qq <= #TCQ pipe_tx_eqpreset_q ;
end
end
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_qq ;
assign pipe_rx_data_o = pipe_rx_data_qq ;
assign pipe_rx_valid_o = pipe_rx_valid_qq ;
assign pipe_rx_data_valid_o = pipe_rx_data_valid_qq ;
assign pipe_rx_status_o = pipe_rx_status_qq ;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_qq ;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_qq ;
assign pipe_rx_eqdone_o = pipe_rx_eqdone_qq ;
assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_qq ;
assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_qq ;
assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_qq ;
assign pipe_rx_startblock_o = pipe_rx_startblock_qq ;
assign pipe_rx_syncheader_o = pipe_rx_syncheader_qq ;
assign pipe_rx_slide_o = pipe_rx_slide_qq ;
assign pipe_rx_syncdone_o = pipe_rx_syncdone_qq ;
assign pipe_rx_polarity_o = pipe_rx_polarity_qq ;
assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_qq ;
assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_qq ;
assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_qq ;
assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_qq ;
assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_qq ;
assign pipe_tx_eqdone_o = pipe_tx_eqdone_qq ;
assign pipe_tx_compliance_o = pipe_tx_compliance_qq ;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_qq ;
assign pipe_tx_data_o = pipe_tx_data_qq ;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_qq ;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_qq ;
assign pipe_tx_datavalid_o = pipe_tx_datavalid_qq ;
assign pipe_tx_startblock_o = pipe_tx_startblock_qq ;
assign pipe_tx_syncheader_o = pipe_tx_syncheader_qq ;
assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_qq ;
assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_qq ;
assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_qq ;
end // if (PIPE_PIPELINE_STAGES == 2)
// Default to zero pipeline stages if PIPE_PIPELINE_STAGES != 0,1,2
else begin
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i ;
assign pipe_rx_data_o = pipe_rx_data_i ;
assign pipe_rx_valid_o = pipe_rx_valid_i ;
assign pipe_rx_data_valid_o = pipe_rx_data_valid_i ;
assign pipe_rx_status_o = pipe_rx_status_i ;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_i ;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i ;
assign pipe_rx_eqdone_o = pipe_rx_eqdone_i ;
assign pipe_rx_eqlpadaptdone_o = pipe_rx_eqlpadaptdone_i ;
assign pipe_rx_eqlplffssel_o = pipe_rx_eqlplffssel_i ;
assign pipe_rx_eqlpnewtxcoefforpreset_o = pipe_rx_eqlpnewtxcoefforpreset_i ;
assign pipe_rx_startblock_o = pipe_rx_startblock_i ;
assign pipe_rx_syncheader_o = pipe_rx_syncheader_i ;
assign pipe_rx_slide_o = pipe_rx_slide_i ;
assign pipe_rx_syncdone_o = pipe_rx_syncdone_i ;
assign pipe_rx_polarity_o = pipe_rx_polarity_i ;
assign pipe_rx_eqcontrol_o = pipe_rx_eqcontrol_i ;
assign pipe_rx_eqlplffs_o = pipe_rx_eqlplffs_i ;
assign pipe_rx_eqlptxpreset_o = pipe_rx_eqlptxpreset_i ;
assign pipe_rx_eqpreset_o = pipe_rx_eqpreset_i ;
assign pipe_tx_eqcoeff_o = pipe_tx_eqcoeff_i ;
assign pipe_tx_eqdone_o = pipe_tx_eqdone_i ;
assign pipe_tx_compliance_o = pipe_tx_compliance_i ;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i ;
assign pipe_tx_data_o = pipe_tx_data_i ;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i ;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_i ;
assign pipe_tx_datavalid_o = pipe_tx_datavalid_i ;
assign pipe_tx_startblock_o = pipe_tx_startblock_i ;
assign pipe_tx_syncheader_o = pipe_tx_syncheader_i ;
assign pipe_tx_eqcontrol_o = pipe_tx_eqcontrol_i ;
assign pipe_tx_eqdeemph_o = pipe_tx_eqdeemph_i ;
assign pipe_tx_eqpreset_o = pipe_tx_eqpreset_i ;
end
endgenerate
endmodule
|
// usb_system.v
// Generated using ACDS version 14.0 200 at 2015.04.28.18:24:52
`timescale 1 ps / 1 ps
module usb_system (
input wire clk_clk, // clk.clk
output wire [7:0] keycode_export, // keycode.export
input wire reset_reset_n, // reset.reset_n
output wire sdram_out_clk_clk, // sdram_out_clk.clk
output wire [12:0] sdram_wire_addr, // sdram_wire.addr
output wire [1:0] sdram_wire_ba, // .ba
output wire sdram_wire_cas_n, // .cas_n
output wire sdram_wire_cke, // .cke
output wire sdram_wire_cs_n, // .cs_n
inout wire [31:0] sdram_wire_dq, // .dq
output wire [3:0] sdram_wire_dqm, // .dqm
output wire sdram_wire_ras_n, // .ras_n
output wire sdram_wire_we_n, // .we_n
inout wire [15:0] usb_DATA, // usb.DATA
output wire [1:0] usb_ADDR, // .ADDR
output wire usb_RD_N, // .RD_N
output wire usb_WR_N, // .WR_N
output wire usb_CS_N, // .CS_N
output wire usb_RST_N, // .RST_N
input wire usb_INT, // .INT
output wire usb_out_clk_clk // usb_out_clk.clk
);
wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest
wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata
wire [28:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write
wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read
wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata
wire cpu_data_master_debugaccess; // cpu:jtag_debug_module_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess
wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable
wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest
wire [28:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read
wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
wire mm_interconnect_0_cpu_jtag_debug_module_waitrequest; // cpu:jtag_debug_module_waitrequest -> mm_interconnect_0:cpu_jtag_debug_module_waitrequest
wire [31:0] mm_interconnect_0_cpu_jtag_debug_module_writedata; // mm_interconnect_0:cpu_jtag_debug_module_writedata -> cpu:jtag_debug_module_writedata
wire [8:0] mm_interconnect_0_cpu_jtag_debug_module_address; // mm_interconnect_0:cpu_jtag_debug_module_address -> cpu:jtag_debug_module_address
wire mm_interconnect_0_cpu_jtag_debug_module_write; // mm_interconnect_0:cpu_jtag_debug_module_write -> cpu:jtag_debug_module_write
wire mm_interconnect_0_cpu_jtag_debug_module_read; // mm_interconnect_0:cpu_jtag_debug_module_read -> cpu:jtag_debug_module_read
wire [31:0] mm_interconnect_0_cpu_jtag_debug_module_readdata; // cpu:jtag_debug_module_readdata -> mm_interconnect_0:cpu_jtag_debug_module_readdata
wire mm_interconnect_0_cpu_jtag_debug_module_debugaccess; // mm_interconnect_0:cpu_jtag_debug_module_debugaccess -> cpu:jtag_debug_module_debugaccess
wire [3:0] mm_interconnect_0_cpu_jtag_debug_module_byteenable; // mm_interconnect_0:cpu_jtag_debug_module_byteenable -> cpu:jtag_debug_module_byteenable
wire [31:0] mm_interconnect_0_clocks_pll_slave_writedata; // mm_interconnect_0:clocks_pll_slave_writedata -> clocks:writedata
wire [1:0] mm_interconnect_0_clocks_pll_slave_address; // mm_interconnect_0:clocks_pll_slave_address -> clocks:address
wire mm_interconnect_0_clocks_pll_slave_write; // mm_interconnect_0:clocks_pll_slave_write -> clocks:write
wire mm_interconnect_0_clocks_pll_slave_read; // mm_interconnect_0:clocks_pll_slave_read -> clocks:read
wire [31:0] mm_interconnect_0_clocks_pll_slave_readdata; // clocks:readdata -> mm_interconnect_0:clocks_pll_slave_readdata
wire mm_interconnect_0_clock_crossing_io_s0_waitrequest; // clock_crossing_io:s0_waitrequest -> mm_interconnect_0:clock_crossing_io_s0_waitrequest
wire [0:0] mm_interconnect_0_clock_crossing_io_s0_burstcount; // mm_interconnect_0:clock_crossing_io_s0_burstcount -> clock_crossing_io:s0_burstcount
wire [31:0] mm_interconnect_0_clock_crossing_io_s0_writedata; // mm_interconnect_0:clock_crossing_io_s0_writedata -> clock_crossing_io:s0_writedata
wire [21:0] mm_interconnect_0_clock_crossing_io_s0_address; // mm_interconnect_0:clock_crossing_io_s0_address -> clock_crossing_io:s0_address
wire mm_interconnect_0_clock_crossing_io_s0_write; // mm_interconnect_0:clock_crossing_io_s0_write -> clock_crossing_io:s0_write
wire mm_interconnect_0_clock_crossing_io_s0_read; // mm_interconnect_0:clock_crossing_io_s0_read -> clock_crossing_io:s0_read
wire [31:0] mm_interconnect_0_clock_crossing_io_s0_readdata; // clock_crossing_io:s0_readdata -> mm_interconnect_0:clock_crossing_io_s0_readdata
wire mm_interconnect_0_clock_crossing_io_s0_debugaccess; // mm_interconnect_0:clock_crossing_io_s0_debugaccess -> clock_crossing_io:s0_debugaccess
wire mm_interconnect_0_clock_crossing_io_s0_readdatavalid; // clock_crossing_io:s0_readdatavalid -> mm_interconnect_0:clock_crossing_io_s0_readdatavalid
wire [3:0] mm_interconnect_0_clock_crossing_io_s0_byteenable; // mm_interconnect_0:clock_crossing_io_s0_byteenable -> clock_crossing_io:s0_byteenable
wire [31:0] mm_interconnect_0_keycode_s1_writedata; // mm_interconnect_0:keycode_s1_writedata -> keycode:writedata
wire [1:0] mm_interconnect_0_keycode_s1_address; // mm_interconnect_0:keycode_s1_address -> keycode:address
wire mm_interconnect_0_keycode_s1_chipselect; // mm_interconnect_0:keycode_s1_chipselect -> keycode:chipselect
wire mm_interconnect_0_keycode_s1_write; // mm_interconnect_0:keycode_s1_write -> keycode:write_n
wire [31:0] mm_interconnect_0_keycode_s1_readdata; // keycode:readdata -> mm_interconnect_0:keycode_s1_readdata
wire mm_interconnect_0_sdram_s1_waitrequest; // sdram:za_waitrequest -> mm_interconnect_0:sdram_s1_waitrequest
wire [31:0] mm_interconnect_0_sdram_s1_writedata; // mm_interconnect_0:sdram_s1_writedata -> sdram:az_data
wire [24:0] mm_interconnect_0_sdram_s1_address; // mm_interconnect_0:sdram_s1_address -> sdram:az_addr
wire mm_interconnect_0_sdram_s1_chipselect; // mm_interconnect_0:sdram_s1_chipselect -> sdram:az_cs
wire mm_interconnect_0_sdram_s1_write; // mm_interconnect_0:sdram_s1_write -> sdram:az_wr_n
wire mm_interconnect_0_sdram_s1_read; // mm_interconnect_0:sdram_s1_read -> sdram:az_rd_n
wire [31:0] mm_interconnect_0_sdram_s1_readdata; // sdram:za_data -> mm_interconnect_0:sdram_s1_readdata
wire mm_interconnect_0_sdram_s1_readdatavalid; // sdram:za_valid -> mm_interconnect_0:sdram_s1_readdatavalid
wire [3:0] mm_interconnect_0_sdram_s1_byteenable; // mm_interconnect_0:sdram_s1_byteenable -> sdram:az_be_n
wire [0:0] clock_crossing_io_m0_burstcount; // clock_crossing_io:m0_burstcount -> mm_interconnect_1:clock_crossing_io_m0_burstcount
wire clock_crossing_io_m0_waitrequest; // mm_interconnect_1:clock_crossing_io_m0_waitrequest -> clock_crossing_io:m0_waitrequest
wire [21:0] clock_crossing_io_m0_address; // clock_crossing_io:m0_address -> mm_interconnect_1:clock_crossing_io_m0_address
wire [31:0] clock_crossing_io_m0_writedata; // clock_crossing_io:m0_writedata -> mm_interconnect_1:clock_crossing_io_m0_writedata
wire clock_crossing_io_m0_write; // clock_crossing_io:m0_write -> mm_interconnect_1:clock_crossing_io_m0_write
wire clock_crossing_io_m0_read; // clock_crossing_io:m0_read -> mm_interconnect_1:clock_crossing_io_m0_read
wire [31:0] clock_crossing_io_m0_readdata; // mm_interconnect_1:clock_crossing_io_m0_readdata -> clock_crossing_io:m0_readdata
wire clock_crossing_io_m0_debugaccess; // clock_crossing_io:m0_debugaccess -> mm_interconnect_1:clock_crossing_io_m0_debugaccess
wire [3:0] clock_crossing_io_m0_byteenable; // clock_crossing_io:m0_byteenable -> mm_interconnect_1:clock_crossing_io_m0_byteenable
wire clock_crossing_io_m0_readdatavalid; // mm_interconnect_1:clock_crossing_io_m0_readdatavalid -> clock_crossing_io:m0_readdatavalid
wire [31:0] mm_interconnect_1_cy7c67200_if_0_hpi_writedata; // mm_interconnect_1:CY7C67200_IF_0_hpi_writedata -> CY7C67200_IF_0:iDATA
wire [1:0] mm_interconnect_1_cy7c67200_if_0_hpi_address; // mm_interconnect_1:CY7C67200_IF_0_hpi_address -> CY7C67200_IF_0:iADDR
wire mm_interconnect_1_cy7c67200_if_0_hpi_chipselect; // mm_interconnect_1:CY7C67200_IF_0_hpi_chipselect -> CY7C67200_IF_0:iCS_N
wire mm_interconnect_1_cy7c67200_if_0_hpi_write; // mm_interconnect_1:CY7C67200_IF_0_hpi_write -> CY7C67200_IF_0:iWR_N
wire mm_interconnect_1_cy7c67200_if_0_hpi_read; // mm_interconnect_1:CY7C67200_IF_0_hpi_read -> CY7C67200_IF_0:iRD_N
wire [31:0] mm_interconnect_1_cy7c67200_if_0_hpi_readdata; // CY7C67200_IF_0:oDATA -> mm_interconnect_1:CY7C67200_IF_0_hpi_readdata
wire irq_mapper_receiver1_irq; // jtag_uart:av_irq -> irq_mapper:receiver1_irq
wire [31:0] cpu_d_irq_irq; // irq_mapper:sender_irq -> cpu:d_irq
wire irq_mapper_receiver0_irq; // irq_synchronizer:sender_irq -> irq_mapper:receiver0_irq
wire [0:0] irq_synchronizer_receiver_irq; // CY7C67200_IF_0:oINT -> irq_synchronizer:receiver_irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [CY7C67200_IF_0:iRST_N, clock_crossing_io:m0_reset, irq_synchronizer:receiver_reset, mm_interconnect_1:clock_crossing_io_m0_reset_reset_bridge_in_reset_reset]
wire cpu_jtag_debug_module_reset_reset; // cpu:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1, rst_controller_002:reset_in1]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [clock_crossing_io:s0_reset, clocks:reset, cpu:reset_n, irq_mapper:reset, irq_synchronizer:sender_reset, jtag_uart:rst_n, keycode:reset_n, mm_interconnect_0:cpu_reset_n_reset_bridge_in_reset_reset, rst_translator:in_reset]
wire rst_controller_001_reset_out_reset_req; // rst_controller_001:reset_req -> [cpu:reset_req, rst_translator:reset_req_in]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [mm_interconnect_0:sdram_reset_reset_bridge_in_reset_reset, sdram:reset_n]
CY7C67200_IF cy7c67200_if_0 (
.oDATA (mm_interconnect_1_cy7c67200_if_0_hpi_readdata), // hpi.readdata
.iADDR (mm_interconnect_1_cy7c67200_if_0_hpi_address), // .address
.iRD_N (~mm_interconnect_1_cy7c67200_if_0_hpi_read), // .read_n
.iWR_N (~mm_interconnect_1_cy7c67200_if_0_hpi_write), // .write_n
.iCS_N (~mm_interconnect_1_cy7c67200_if_0_hpi_chipselect), // .chipselect_n
.iDATA (mm_interconnect_1_cy7c67200_if_0_hpi_writedata), // .writedata
.iCLK (usb_out_clk_clk), // clock_sink.clk
.iRST_N (~rst_controller_reset_out_reset), // clock_sink_reset.reset_n
.oINT (irq_synchronizer_receiver_irq), // interrupt_sender.irq
.HPI_DATA (usb_DATA), // conduit_end.export
.HPI_ADDR (usb_ADDR), // .export
.HPI_RD_N (usb_RD_N), // .export
.HPI_WR_N (usb_WR_N), // .export
.HPI_CS_N (usb_CS_N), // .export
.HPI_RST_N (usb_RST_N), // .export
.HPI_INT (usb_INT) // .export
);
altera_avalon_mm_clock_crossing_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (22),
.BURSTCOUNT_WIDTH (1),
.COMMAND_FIFO_DEPTH (32),
.RESPONSE_FIFO_DEPTH (256),
.MASTER_SYNC_DEPTH (3),
.SLAVE_SYNC_DEPTH (3)
) clock_crossing_io (
.m0_clk (usb_out_clk_clk), // m0_clk.clk
.m0_reset (rst_controller_reset_out_reset), // m0_reset.reset
.s0_clk (clk_clk), // s0_clk.clk
.s0_reset (rst_controller_001_reset_out_reset), // s0_reset.reset
.s0_waitrequest (mm_interconnect_0_clock_crossing_io_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_0_clock_crossing_io_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_0_clock_crossing_io_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_0_clock_crossing_io_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_0_clock_crossing_io_s0_writedata), // .writedata
.s0_address (mm_interconnect_0_clock_crossing_io_s0_address), // .address
.s0_write (mm_interconnect_0_clock_crossing_io_s0_write), // .write
.s0_read (mm_interconnect_0_clock_crossing_io_s0_read), // .read
.s0_byteenable (mm_interconnect_0_clock_crossing_io_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_0_clock_crossing_io_s0_debugaccess), // .debugaccess
.m0_waitrequest (clock_crossing_io_m0_waitrequest), // m0.waitrequest
.m0_readdata (clock_crossing_io_m0_readdata), // .readdata
.m0_readdatavalid (clock_crossing_io_m0_readdatavalid), // .readdatavalid
.m0_burstcount (clock_crossing_io_m0_burstcount), // .burstcount
.m0_writedata (clock_crossing_io_m0_writedata), // .writedata
.m0_address (clock_crossing_io_m0_address), // .address
.m0_write (clock_crossing_io_m0_write), // .write
.m0_read (clock_crossing_io_m0_read), // .read
.m0_byteenable (clock_crossing_io_m0_byteenable), // .byteenable
.m0_debugaccess (clock_crossing_io_m0_debugaccess) // .debugaccess
);
usb_system_clocks clocks (
.clk (clk_clk), // inclk_interface.clk
.reset (rst_controller_001_reset_out_reset), // inclk_interface_reset.reset
.read (mm_interconnect_0_clocks_pll_slave_read), // pll_slave.read
.write (mm_interconnect_0_clocks_pll_slave_write), // .write
.address (mm_interconnect_0_clocks_pll_slave_address), // .address
.readdata (mm_interconnect_0_clocks_pll_slave_readdata), // .readdata
.writedata (mm_interconnect_0_clocks_pll_slave_writedata), // .writedata
.c0 (sdram_out_clk_clk), // c0.clk
.c1 (usb_out_clk_clk), // c1.clk
.areset (), // areset_conduit.export
.locked (), // locked_conduit.export
.phasedone () // phasedone_conduit.export
);
usb_system_cpu cpu (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset_n.reset_n
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.d_address (cpu_data_master_address), // data_master.address
.d_byteenable (cpu_data_master_byteenable), // .byteenable
.d_read (cpu_data_master_read), // .read
.d_readdata (cpu_data_master_readdata), // .readdata
.d_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.d_write (cpu_data_master_write), // .write
.d_writedata (cpu_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess), // .debugaccess
.i_address (cpu_instruction_master_address), // instruction_master.address
.i_read (cpu_instruction_master_read), // .read
.i_readdata (cpu_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.d_irq (cpu_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (cpu_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset
.jtag_debug_module_address (mm_interconnect_0_cpu_jtag_debug_module_address), // jtag_debug_module.address
.jtag_debug_module_byteenable (mm_interconnect_0_cpu_jtag_debug_module_byteenable), // .byteenable
.jtag_debug_module_debugaccess (mm_interconnect_0_cpu_jtag_debug_module_debugaccess), // .debugaccess
.jtag_debug_module_read (mm_interconnect_0_cpu_jtag_debug_module_read), // .read
.jtag_debug_module_readdata (mm_interconnect_0_cpu_jtag_debug_module_readdata), // .readdata
.jtag_debug_module_waitrequest (mm_interconnect_0_cpu_jtag_debug_module_waitrequest), // .waitrequest
.jtag_debug_module_write (mm_interconnect_0_cpu_jtag_debug_module_write), // .write
.jtag_debug_module_writedata (mm_interconnect_0_cpu_jtag_debug_module_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
usb_system_jtag_uart jtag_uart (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver1_irq) // irq.irq
);
usb_system_keycode keycode (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_keycode_s1_address), // s1.address
.write_n (~mm_interconnect_0_keycode_s1_write), // .write_n
.writedata (mm_interconnect_0_keycode_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_keycode_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_keycode_s1_readdata), // .readdata
.out_port (keycode_export) // external_connection.export
);
usb_system_sdram sdram (
.clk (sdram_out_clk_clk), // clk.clk
.reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_0_sdram_s1_address), // s1.address
.az_be_n (~mm_interconnect_0_sdram_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.az_data (mm_interconnect_0_sdram_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_0_sdram_s1_read), // .read_n
.az_wr_n (~mm_interconnect_0_sdram_s1_write), // .write_n
.za_data (mm_interconnect_0_sdram_s1_readdata), // .readdata
.za_valid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.zs_addr (sdram_wire_addr), // wire.export
.zs_ba (sdram_wire_ba), // .export
.zs_cas_n (sdram_wire_cas_n), // .export
.zs_cke (sdram_wire_cke), // .export
.zs_cs_n (sdram_wire_cs_n), // .export
.zs_dq (sdram_wire_dq), // .export
.zs_dqm (sdram_wire_dqm), // .export
.zs_ras_n (sdram_wire_ras_n), // .export
.zs_we_n (sdram_wire_we_n) // .export
);
usb_system_mm_interconnect_0 mm_interconnect_0 (
.clk_clk_clk (clk_clk), // clk_clk.clk
.clocks_c0_clk (sdram_out_clk_clk), // clocks_c0.clk
.cpu_reset_n_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // cpu_reset_n_reset_bridge_in_reset.reset
.sdram_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // sdram_reset_reset_bridge_in_reset.reset
.cpu_data_master_address (cpu_data_master_address), // cpu_data_master.address
.cpu_data_master_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.cpu_data_master_byteenable (cpu_data_master_byteenable), // .byteenable
.cpu_data_master_read (cpu_data_master_read), // .read
.cpu_data_master_readdata (cpu_data_master_readdata), // .readdata
.cpu_data_master_write (cpu_data_master_write), // .write
.cpu_data_master_writedata (cpu_data_master_writedata), // .writedata
.cpu_data_master_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.cpu_instruction_master_address (cpu_instruction_master_address), // cpu_instruction_master.address
.cpu_instruction_master_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.cpu_instruction_master_read (cpu_instruction_master_read), // .read
.cpu_instruction_master_readdata (cpu_instruction_master_readdata), // .readdata
.clock_crossing_io_s0_address (mm_interconnect_0_clock_crossing_io_s0_address), // clock_crossing_io_s0.address
.clock_crossing_io_s0_write (mm_interconnect_0_clock_crossing_io_s0_write), // .write
.clock_crossing_io_s0_read (mm_interconnect_0_clock_crossing_io_s0_read), // .read
.clock_crossing_io_s0_readdata (mm_interconnect_0_clock_crossing_io_s0_readdata), // .readdata
.clock_crossing_io_s0_writedata (mm_interconnect_0_clock_crossing_io_s0_writedata), // .writedata
.clock_crossing_io_s0_burstcount (mm_interconnect_0_clock_crossing_io_s0_burstcount), // .burstcount
.clock_crossing_io_s0_byteenable (mm_interconnect_0_clock_crossing_io_s0_byteenable), // .byteenable
.clock_crossing_io_s0_readdatavalid (mm_interconnect_0_clock_crossing_io_s0_readdatavalid), // .readdatavalid
.clock_crossing_io_s0_waitrequest (mm_interconnect_0_clock_crossing_io_s0_waitrequest), // .waitrequest
.clock_crossing_io_s0_debugaccess (mm_interconnect_0_clock_crossing_io_s0_debugaccess), // .debugaccess
.clocks_pll_slave_address (mm_interconnect_0_clocks_pll_slave_address), // clocks_pll_slave.address
.clocks_pll_slave_write (mm_interconnect_0_clocks_pll_slave_write), // .write
.clocks_pll_slave_read (mm_interconnect_0_clocks_pll_slave_read), // .read
.clocks_pll_slave_readdata (mm_interconnect_0_clocks_pll_slave_readdata), // .readdata
.clocks_pll_slave_writedata (mm_interconnect_0_clocks_pll_slave_writedata), // .writedata
.cpu_jtag_debug_module_address (mm_interconnect_0_cpu_jtag_debug_module_address), // cpu_jtag_debug_module.address
.cpu_jtag_debug_module_write (mm_interconnect_0_cpu_jtag_debug_module_write), // .write
.cpu_jtag_debug_module_read (mm_interconnect_0_cpu_jtag_debug_module_read), // .read
.cpu_jtag_debug_module_readdata (mm_interconnect_0_cpu_jtag_debug_module_readdata), // .readdata
.cpu_jtag_debug_module_writedata (mm_interconnect_0_cpu_jtag_debug_module_writedata), // .writedata
.cpu_jtag_debug_module_byteenable (mm_interconnect_0_cpu_jtag_debug_module_byteenable), // .byteenable
.cpu_jtag_debug_module_waitrequest (mm_interconnect_0_cpu_jtag_debug_module_waitrequest), // .waitrequest
.cpu_jtag_debug_module_debugaccess (mm_interconnect_0_cpu_jtag_debug_module_debugaccess), // .debugaccess
.jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
.jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write
.jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read
.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.keycode_s1_address (mm_interconnect_0_keycode_s1_address), // keycode_s1.address
.keycode_s1_write (mm_interconnect_0_keycode_s1_write), // .write
.keycode_s1_readdata (mm_interconnect_0_keycode_s1_readdata), // .readdata
.keycode_s1_writedata (mm_interconnect_0_keycode_s1_writedata), // .writedata
.keycode_s1_chipselect (mm_interconnect_0_keycode_s1_chipselect), // .chipselect
.sdram_s1_address (mm_interconnect_0_sdram_s1_address), // sdram_s1.address
.sdram_s1_write (mm_interconnect_0_sdram_s1_write), // .write
.sdram_s1_read (mm_interconnect_0_sdram_s1_read), // .read
.sdram_s1_readdata (mm_interconnect_0_sdram_s1_readdata), // .readdata
.sdram_s1_writedata (mm_interconnect_0_sdram_s1_writedata), // .writedata
.sdram_s1_byteenable (mm_interconnect_0_sdram_s1_byteenable), // .byteenable
.sdram_s1_readdatavalid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.sdram_s1_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.sdram_s1_chipselect (mm_interconnect_0_sdram_s1_chipselect) // .chipselect
);
usb_system_mm_interconnect_1 mm_interconnect_1 (
.clocks_c1_clk (usb_out_clk_clk), // clocks_c1.clk
.clock_crossing_io_m0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // clock_crossing_io_m0_reset_reset_bridge_in_reset.reset
.clock_crossing_io_m0_address (clock_crossing_io_m0_address), // clock_crossing_io_m0.address
.clock_crossing_io_m0_waitrequest (clock_crossing_io_m0_waitrequest), // .waitrequest
.clock_crossing_io_m0_burstcount (clock_crossing_io_m0_burstcount), // .burstcount
.clock_crossing_io_m0_byteenable (clock_crossing_io_m0_byteenable), // .byteenable
.clock_crossing_io_m0_read (clock_crossing_io_m0_read), // .read
.clock_crossing_io_m0_readdata (clock_crossing_io_m0_readdata), // .readdata
.clock_crossing_io_m0_readdatavalid (clock_crossing_io_m0_readdatavalid), // .readdatavalid
.clock_crossing_io_m0_write (clock_crossing_io_m0_write), // .write
.clock_crossing_io_m0_writedata (clock_crossing_io_m0_writedata), // .writedata
.clock_crossing_io_m0_debugaccess (clock_crossing_io_m0_debugaccess), // .debugaccess
.CY7C67200_IF_0_hpi_address (mm_interconnect_1_cy7c67200_if_0_hpi_address), // CY7C67200_IF_0_hpi.address
.CY7C67200_IF_0_hpi_write (mm_interconnect_1_cy7c67200_if_0_hpi_write), // .write
.CY7C67200_IF_0_hpi_read (mm_interconnect_1_cy7c67200_if_0_hpi_read), // .read
.CY7C67200_IF_0_hpi_readdata (mm_interconnect_1_cy7c67200_if_0_hpi_readdata), // .readdata
.CY7C67200_IF_0_hpi_writedata (mm_interconnect_1_cy7c67200_if_0_hpi_writedata), // .writedata
.CY7C67200_IF_0_hpi_chipselect (mm_interconnect_1_cy7c67200_if_0_hpi_chipselect) // .chipselect
);
usb_system_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.sender_irq (cpu_d_irq_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer (
.receiver_clk (usb_out_clk_clk), // receiver_clk.clk
.sender_clk (clk_clk), // sender_clk.clk
.receiver_reset (rst_controller_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_001_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver0_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (usb_out_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (sdram_out_clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A211O_BEHAVIORAL_PP_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a211o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
// Local signals
wire C1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211O_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// RCN bus RAM
//
module rcn_ram
(
input clk,
input rst,
input [68:0] rcn_in,
output [68:0] rcn_out
);
parameter ADDR_BASE = 0;
wire cs;
wire wr;
wire [3:0] mask;
wire [23:0] addr;
wire [31:0] wdata;
wire [31:0] rdata;
rcn_slave #(.ADDR_MASK(24'hFF0000), .ADDR_BASE(ADDR_BASE)) rcn_slave
(
.rst(rst),
.clk(clk),
.rcn_in(rcn_in),
.rcn_out(rcn_out),
.cs(cs),
.wr(wr),
.mask(mask),
.addr(addr),
.wdata(wdata),
.rdata(rdata)
);
reg [7:0] byte_0[(1024 * 16)-1:0];
reg [7:0] byte_1[(1024 * 16)-1:0];
reg [7:0] byte_2[(1024 * 16)-1:0];
reg [7:0] byte_3[(1024 * 16)-1:0];
reg [31:0] data_out;
always @ (posedge clk)
if (cs && wr)
begin
if (mask[0])
byte_0[addr[15:2]] <= wdata[7:0];
if (mask[1])
byte_1[addr[15:2]] <= wdata[15:8];
if (mask[2])
byte_2[addr[15:2]] <= wdata[23:16];
if (mask[3])
byte_3[addr[15:2]] <= wdata[31:24];
end
always @ (posedge clk)
if (cs)
data_out <= {byte_3[addr[15:2]], byte_2[addr[15:2]],
byte_1[addr[15:2]], byte_0[addr[15:2]]};
assign rdata = data_out;
endmodule
|
`timescale 1ns / 1ps
module DataMemory(
output reg [31:0] ReadData,
output reg [31:0] DATO1,
output reg [31:0] DATO2,
output reg [31:0] RESULTADO,
input [31:0] Address,
input [31:0] WriteData,
input [31:0] MouseData,
input MouseEnable,
input WriteEnable,
input CLK
);
reg [31:0] block [0:9];
always @ (*) begin
DATO1 = block[4];
DATO2 = block[5];
RESULTADO = block[7];
if (CLK) begin
case (Address)
32'h00000000: ReadData = block[0];
32'h00000004: ReadData = block[1];
32'h00000008: ReadData = block[2];
32'h0000000c: ReadData = block[3];
32'h00000010: ReadData = block[4];
32'h00000014: ReadData = block[5];
32'h00000018: ReadData = block[6];
32'h0000001c: ReadData = block[7];
32'h00000020: ReadData = block[8];
32'h00000024: ReadData = block[9];
default: ReadData = 32'b0;
endcase
end
else begin
if (MouseEnable) begin
block[1] = MouseData;
end
if (WriteEnable)
case (Address)
32'h00000000: block[0] = WriteData;
32'h00000004: block[1] = WriteData;
32'h00000008: block[2] = WriteData;
32'h0000000c: block[3] = WriteData;
32'h00000010: block[4] = WriteData;
32'h00000014: block[5] = WriteData;
32'h00000018: block[6] = WriteData;
32'h0000001c: block[7] = WriteData;
32'h00000020: block[8] = WriteData;
32'h00000024: block[9] = WriteData;
endcase
end
end
integer i = 0;
initial begin
for (i=0;i<10;i=i+1)
block[i] = 32'b0;
block[1] = 2;
block[4] = 2;
end
endmodule
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "encoder_pl.v"
`include "decoder_pl.v"
`include "pipelinedec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [13:0] c;
// Output of stage 2
wire [13:0] cx;
// Output of stage 3
wire [3:0] q;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [3:0] b;
reg [3:0] r_b;
reg [13:0] e;
reg [13:0] r_e;
// 2nd stage
reg [13:0] r_c;
reg [13:0] rr_e;
reg [3:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [14:0] cx;
//reg [10:0] qx;
reg [13:0] r_qx;
reg [3:0] rb;
reg clk,reset;
reg [13:0] e2;
encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,rr_e,cx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
e2<=rr_e;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = 14'b00000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000100000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000001000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000100000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 14'b00000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 288K-bit High-Density Memory Building Block
// /___/ /\ Filename : URAM288.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 10/31/2014 - Initial functional version
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module URAM288 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer AUTO_SLEEP_LATENCY = 8,
parameter integer AVG_CONS_INACTIVE_CYCLES = 10,
parameter BWE_MODE_A = "PARITY_INTERLEAVED",
parameter BWE_MODE_B = "PARITY_INTERLEAVED",
parameter CASCADE_ORDER_A = "NONE",
parameter CASCADE_ORDER_B = "NONE",
parameter EN_AUTO_SLEEP_MODE = "FALSE",
parameter EN_ECC_RD_A = "FALSE",
parameter EN_ECC_RD_B = "FALSE",
parameter EN_ECC_WR_A = "FALSE",
parameter EN_ECC_WR_B = "FALSE",
parameter IREG_PRE_A = "FALSE",
parameter IREG_PRE_B = "FALSE",
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_EN_A_INVERTED = 1'b0,
parameter [0:0] IS_EN_B_INVERTED = 1'b0,
parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0,
parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0,
parameter [0:0] IS_RST_A_INVERTED = 1'b0,
parameter [0:0] IS_RST_B_INVERTED = 1'b0,
parameter MATRIX_ID = "NONE",
parameter integer NUM_UNIQUE_SELF_ADDR_A = 1,
parameter integer NUM_UNIQUE_SELF_ADDR_B = 1,
parameter integer NUM_URAM_IN_MATRIX = 1,
parameter OREG_A = "FALSE",
parameter OREG_B = "FALSE",
parameter OREG_ECC_A = "FALSE",
parameter OREG_ECC_B = "FALSE",
parameter REG_CAS_A = "FALSE",
parameter REG_CAS_B = "FALSE",
parameter RST_MODE_A = "SYNC",
parameter RST_MODE_B = "SYNC",
parameter [10:0] SELF_ADDR_A = 11'h000,
parameter [10:0] SELF_ADDR_B = 11'h000,
parameter [10:0] SELF_MASK_A = 11'h7FF,
parameter [10:0] SELF_MASK_B = 11'h7FF,
parameter USE_EXT_CE_A = "FALSE",
parameter USE_EXT_CE_B = "FALSE"
)(
output [22:0] CAS_OUT_ADDR_A,
output [22:0] CAS_OUT_ADDR_B,
output [8:0] CAS_OUT_BWE_A,
output [8:0] CAS_OUT_BWE_B,
output CAS_OUT_DBITERR_A,
output CAS_OUT_DBITERR_B,
output [71:0] CAS_OUT_DIN_A,
output [71:0] CAS_OUT_DIN_B,
output [71:0] CAS_OUT_DOUT_A,
output [71:0] CAS_OUT_DOUT_B,
output CAS_OUT_EN_A,
output CAS_OUT_EN_B,
output CAS_OUT_RDACCESS_A,
output CAS_OUT_RDACCESS_B,
output CAS_OUT_RDB_WR_A,
output CAS_OUT_RDB_WR_B,
output CAS_OUT_SBITERR_A,
output CAS_OUT_SBITERR_B,
output DBITERR_A,
output DBITERR_B,
output [71:0] DOUT_A,
output [71:0] DOUT_B,
output RDACCESS_A,
output RDACCESS_B,
output SBITERR_A,
output SBITERR_B,
input [22:0] ADDR_A,
input [22:0] ADDR_B,
input [8:0] BWE_A,
input [8:0] BWE_B,
input [22:0] CAS_IN_ADDR_A,
input [22:0] CAS_IN_ADDR_B,
input [8:0] CAS_IN_BWE_A,
input [8:0] CAS_IN_BWE_B,
input CAS_IN_DBITERR_A,
input CAS_IN_DBITERR_B,
input [71:0] CAS_IN_DIN_A,
input [71:0] CAS_IN_DIN_B,
input [71:0] CAS_IN_DOUT_A,
input [71:0] CAS_IN_DOUT_B,
input CAS_IN_EN_A,
input CAS_IN_EN_B,
input CAS_IN_RDACCESS_A,
input CAS_IN_RDACCESS_B,
input CAS_IN_RDB_WR_A,
input CAS_IN_RDB_WR_B,
input CAS_IN_SBITERR_A,
input CAS_IN_SBITERR_B,
input CLK,
input [71:0] DIN_A,
input [71:0] DIN_B,
input EN_A,
input EN_B,
input INJECT_DBITERR_A,
input INJECT_DBITERR_B,
input INJECT_SBITERR_A,
input INJECT_SBITERR_B,
input OREG_CE_A,
input OREG_CE_B,
input OREG_ECC_CE_A,
input OREG_ECC_CE_B,
input RDB_WR_A,
input RDB_WR_B,
input RST_A,
input RST_B,
input SLEEP
);
// define constants
localparam MODULE_NAME = "URAM288";
// Parameter encodings and registers
localparam BWE_MODE_A_PARITY_INDEPENDENT = 1;
localparam BWE_MODE_A_PARITY_INTERLEAVED = 0;
localparam BWE_MODE_B_PARITY_INDEPENDENT = 1;
localparam BWE_MODE_B_PARITY_INTERLEAVED = 0;
localparam CASCADE_ORDER_A_FIRST = 1;
localparam CASCADE_ORDER_A_LAST = 2;
localparam CASCADE_ORDER_A_MIDDLE = 3;
localparam CASCADE_ORDER_A_NONE = 0;
localparam CASCADE_ORDER_B_FIRST = 1;
localparam CASCADE_ORDER_B_LAST = 2;
localparam CASCADE_ORDER_B_MIDDLE = 3;
localparam CASCADE_ORDER_B_NONE = 0;
localparam EN_AUTO_SLEEP_MODE_FALSE = 0;
localparam EN_AUTO_SLEEP_MODE_TRUE = 1;
localparam EN_ECC_RD_A_FALSE = 0;
localparam EN_ECC_RD_A_TRUE = 1;
localparam EN_ECC_RD_B_FALSE = 0;
localparam EN_ECC_RD_B_TRUE = 1;
localparam EN_ECC_WR_A_FALSE = 0;
localparam EN_ECC_WR_A_TRUE = 1;
localparam EN_ECC_WR_B_FALSE = 0;
localparam EN_ECC_WR_B_TRUE = 1;
localparam IREG_PRE_A_FALSE = 0;
localparam IREG_PRE_A_TRUE = 1;
localparam IREG_PRE_B_FALSE = 0;
localparam IREG_PRE_B_TRUE = 1;
localparam OREG_A_FALSE = 0;
localparam OREG_A_TRUE = 1;
localparam OREG_B_FALSE = 0;
localparam OREG_B_TRUE = 1;
localparam OREG_ECC_A_FALSE = 0;
localparam OREG_ECC_A_TRUE = 1;
localparam OREG_ECC_B_FALSE = 0;
localparam OREG_ECC_B_TRUE = 1;
localparam REG_CAS_A_FALSE = 0;
localparam REG_CAS_A_TRUE = 1;
localparam REG_CAS_B_FALSE = 0;
localparam REG_CAS_B_TRUE = 1;
localparam RST_MODE_A_ASYNC = 1;
localparam RST_MODE_A_SYNC = 0;
localparam RST_MODE_B_ASYNC = 1;
localparam RST_MODE_B_SYNC = 0;
localparam USE_EXT_CE_A_FALSE = 0;
localparam USE_EXT_CE_A_TRUE = 1;
localparam USE_EXT_CE_B_FALSE = 0;
localparam USE_EXT_CE_B_TRUE = 1;
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "URAM288_dr.v"
`else
reg [31:0] AUTO_SLEEP_LATENCY_REG = AUTO_SLEEP_LATENCY;
reg [31:0] AVG_CONS_INACTIVE_CYCLES_REG = AVG_CONS_INACTIVE_CYCLES;
reg [144:1] BWE_MODE_A_REG = BWE_MODE_A;
reg [144:1] BWE_MODE_B_REG = BWE_MODE_B;
reg [48:1] CASCADE_ORDER_A_REG = CASCADE_ORDER_A;
reg [48:1] CASCADE_ORDER_B_REG = CASCADE_ORDER_B;
reg [40:1] EN_AUTO_SLEEP_MODE_REG = EN_AUTO_SLEEP_MODE;
reg [40:1] EN_ECC_RD_A_REG = EN_ECC_RD_A;
reg [40:1] EN_ECC_RD_B_REG = EN_ECC_RD_B;
reg [40:1] EN_ECC_WR_A_REG = EN_ECC_WR_A;
reg [40:1] EN_ECC_WR_B_REG = EN_ECC_WR_B;
reg [40:1] IREG_PRE_A_REG = IREG_PRE_A;
reg [40:1] IREG_PRE_B_REG = IREG_PRE_B;
reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
reg [0:0] IS_EN_A_INVERTED_REG = IS_EN_A_INVERTED;
reg [0:0] IS_EN_B_INVERTED_REG = IS_EN_B_INVERTED;
reg [0:0] IS_RDB_WR_A_INVERTED_REG = IS_RDB_WR_A_INVERTED;
reg [0:0] IS_RDB_WR_B_INVERTED_REG = IS_RDB_WR_B_INVERTED;
reg [0:0] IS_RST_A_INVERTED_REG = IS_RST_A_INVERTED;
reg [0:0] IS_RST_B_INVERTED_REG = IS_RST_B_INVERTED;
reg [32:1] MATRIX_ID_REG = MATRIX_ID;
reg [31:0] NUM_UNIQUE_SELF_ADDR_A_REG = NUM_UNIQUE_SELF_ADDR_A;
reg [31:0] NUM_UNIQUE_SELF_ADDR_B_REG = NUM_UNIQUE_SELF_ADDR_B;
reg [31:0] NUM_URAM_IN_MATRIX_REG = NUM_URAM_IN_MATRIX;
reg [40:1] OREG_A_REG = OREG_A;
reg [40:1] OREG_B_REG = OREG_B;
reg [40:1] OREG_ECC_A_REG = OREG_ECC_A;
reg [40:1] OREG_ECC_B_REG = OREG_ECC_B;
reg [40:1] REG_CAS_A_REG = REG_CAS_A;
reg [40:1] REG_CAS_B_REG = REG_CAS_B;
reg [40:1] RST_MODE_A_REG = RST_MODE_A;
reg [40:1] RST_MODE_B_REG = RST_MODE_B;
reg [10:0] SELF_ADDR_A_REG = SELF_ADDR_A;
reg [10:0] SELF_ADDR_B_REG = SELF_ADDR_B;
reg [10:0] SELF_MASK_A_REG = SELF_MASK_A;
reg [10:0] SELF_MASK_B_REG = SELF_MASK_B;
reg [40:1] USE_EXT_CE_A_REG = USE_EXT_CE_A;
reg [40:1] USE_EXT_CE_B_REG = USE_EXT_CE_B;
`endif
`ifdef XIL_XECLIB
wire [3:0] AUTO_SLEEP_LATENCY_BIN;
wire [16:0] AVG_CONS_INACTIVE_CYCLES_BIN;
wire BWE_MODE_A_BIN;
wire BWE_MODE_B_BIN;
wire [1:0] CASCADE_ORDER_A_BIN;
wire [1:0] CASCADE_ORDER_B_BIN;
wire EN_AUTO_SLEEP_MODE_BIN;
wire EN_ECC_RD_A_BIN;
wire EN_ECC_RD_B_BIN;
wire EN_ECC_WR_A_BIN;
wire EN_ECC_WR_B_BIN;
wire IREG_PRE_A_BIN;
wire IREG_PRE_B_BIN;
wire [11:0] NUM_UNIQUE_SELF_ADDR_A_BIN;
wire [11:0] NUM_UNIQUE_SELF_ADDR_B_BIN;
wire [11:0] NUM_URAM_IN_MATRIX_BIN;
wire OREG_A_BIN;
wire OREG_B_BIN;
wire OREG_ECC_A_BIN;
wire OREG_ECC_B_BIN;
wire REG_CAS_A_BIN;
wire REG_CAS_B_BIN;
wire RST_MODE_A_BIN;
wire RST_MODE_B_BIN;
wire USE_EXT_CE_A_BIN;
wire USE_EXT_CE_B_BIN;
`else
reg [3:0] AUTO_SLEEP_LATENCY_BIN;
reg [16:0] AVG_CONS_INACTIVE_CYCLES_BIN;
reg BWE_MODE_A_BIN;
reg BWE_MODE_B_BIN;
reg [1:0] CASCADE_ORDER_A_BIN;
reg [1:0] CASCADE_ORDER_B_BIN;
reg EN_AUTO_SLEEP_MODE_BIN;
reg EN_ECC_RD_A_BIN;
reg EN_ECC_RD_B_BIN;
reg EN_ECC_WR_A_BIN;
reg EN_ECC_WR_B_BIN;
reg IREG_PRE_A_BIN;
reg IREG_PRE_B_BIN;
reg [11:0] NUM_UNIQUE_SELF_ADDR_A_BIN;
reg [11:0] NUM_UNIQUE_SELF_ADDR_B_BIN;
reg [11:0] NUM_URAM_IN_MATRIX_BIN;
reg OREG_A_BIN;
reg OREG_B_BIN;
reg OREG_ECC_A_BIN;
reg OREG_ECC_B_BIN;
reg REG_CAS_A_BIN;
reg REG_CAS_B_BIN;
reg RST_MODE_A_BIN;
reg RST_MODE_B_BIN;
reg USE_EXT_CE_A_BIN;
reg USE_EXT_CE_B_BIN;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
wire CAS_IN_DBITERR_A_in;
wire CAS_IN_DBITERR_B_in;
wire CAS_IN_EN_A_in;
wire CAS_IN_EN_B_in;
wire CAS_IN_RDACCESS_A_in;
wire CAS_IN_RDACCESS_B_in;
wire CAS_IN_RDB_WR_A_in;
wire CAS_IN_RDB_WR_B_in;
wire CAS_IN_SBITERR_A_in;
wire CAS_IN_SBITERR_B_in;
wire CLK_in;
wire EN_A_in;
wire EN_B_in;
wire INJECT_DBITERR_A_in;
wire INJECT_DBITERR_B_in;
wire INJECT_SBITERR_A_in;
wire INJECT_SBITERR_B_in;
wire OREG_CE_A_in;
wire OREG_CE_B_in;
wire OREG_ECC_CE_A_in;
wire OREG_ECC_CE_B_in;
wire RDB_WR_A_in;
wire RDB_WR_B_in;
wire RST_A_in;
wire RST_B_in;
wire SLEEP_in;
wire [22:0] ADDR_A_in;
wire [22:0] ADDR_B_in;
wire [22:0] CAS_IN_ADDR_A_in;
wire [22:0] CAS_IN_ADDR_B_in;
wire [71:0] CAS_IN_DIN_A_in;
wire [71:0] CAS_IN_DIN_B_in;
wire [71:0] CAS_IN_DOUT_A_in;
wire [71:0] CAS_IN_DOUT_B_in;
wire [71:0] DIN_A_in;
wire [71:0] DIN_B_in;
wire [8:0] BWE_A_in;
wire [8:0] BWE_B_in;
wire [8:0] CAS_IN_BWE_A_in;
wire [8:0] CAS_IN_BWE_B_in;
`ifdef XIL_TIMING
wire CAS_IN_DBITERR_A_delay;
wire CAS_IN_DBITERR_B_delay;
wire CAS_IN_EN_A_delay;
wire CAS_IN_EN_B_delay;
wire CAS_IN_RDACCESS_A_delay;
wire CAS_IN_RDACCESS_B_delay;
wire CAS_IN_RDB_WR_A_delay;
wire CAS_IN_RDB_WR_B_delay;
wire CAS_IN_SBITERR_A_delay;
wire CAS_IN_SBITERR_B_delay;
wire CLK_delay;
wire EN_A_delay;
wire EN_B_delay;
wire INJECT_DBITERR_A_delay;
wire INJECT_DBITERR_B_delay;
wire INJECT_SBITERR_A_delay;
wire INJECT_SBITERR_B_delay;
wire OREG_CE_A_delay;
wire OREG_CE_B_delay;
wire OREG_ECC_CE_A_delay;
wire OREG_ECC_CE_B_delay;
wire RDB_WR_A_delay;
wire RDB_WR_B_delay;
wire RST_A_delay;
wire RST_B_delay;
wire SLEEP_delay;
wire [22:0] ADDR_A_delay;
wire [22:0] ADDR_B_delay;
wire [22:0] CAS_IN_ADDR_A_delay;
wire [22:0] CAS_IN_ADDR_B_delay;
wire [71:0] CAS_IN_DIN_A_delay;
wire [71:0] CAS_IN_DIN_B_delay;
wire [71:0] CAS_IN_DOUT_A_delay;
wire [71:0] CAS_IN_DOUT_B_delay;
wire [71:0] DIN_A_delay;
wire [71:0] DIN_B_delay;
wire [8:0] BWE_A_delay;
wire [8:0] BWE_B_delay;
wire [8:0] CAS_IN_BWE_A_delay;
wire [8:0] CAS_IN_BWE_B_delay;
`endif
`ifdef XIL_TIMING
assign ADDR_A_in = ADDR_A_delay;
assign ADDR_B_in = ADDR_B_delay;
assign BWE_A_in = BWE_A_delay;
assign BWE_B_in = BWE_B_delay;
assign CAS_IN_ADDR_A_in[0] = (CAS_IN_ADDR_A[0] !== 1'bz) && CAS_IN_ADDR_A_delay[0]; // rv 0
assign CAS_IN_ADDR_A_in[10] = (CAS_IN_ADDR_A[10] !== 1'bz) && CAS_IN_ADDR_A_delay[10]; // rv 0
assign CAS_IN_ADDR_A_in[11] = (CAS_IN_ADDR_A[11] !== 1'bz) && CAS_IN_ADDR_A_delay[11]; // rv 0
assign CAS_IN_ADDR_A_in[12] = (CAS_IN_ADDR_A[12] !== 1'bz) && CAS_IN_ADDR_A_delay[12]; // rv 0
assign CAS_IN_ADDR_A_in[13] = (CAS_IN_ADDR_A[13] !== 1'bz) && CAS_IN_ADDR_A_delay[13]; // rv 0
assign CAS_IN_ADDR_A_in[14] = (CAS_IN_ADDR_A[14] !== 1'bz) && CAS_IN_ADDR_A_delay[14]; // rv 0
assign CAS_IN_ADDR_A_in[15] = (CAS_IN_ADDR_A[15] !== 1'bz) && CAS_IN_ADDR_A_delay[15]; // rv 0
assign CAS_IN_ADDR_A_in[16] = (CAS_IN_ADDR_A[16] !== 1'bz) && CAS_IN_ADDR_A_delay[16]; // rv 0
assign CAS_IN_ADDR_A_in[17] = (CAS_IN_ADDR_A[17] !== 1'bz) && CAS_IN_ADDR_A_delay[17]; // rv 0
assign CAS_IN_ADDR_A_in[18] = (CAS_IN_ADDR_A[18] !== 1'bz) && CAS_IN_ADDR_A_delay[18]; // rv 0
assign CAS_IN_ADDR_A_in[19] = (CAS_IN_ADDR_A[19] !== 1'bz) && CAS_IN_ADDR_A_delay[19]; // rv 0
assign CAS_IN_ADDR_A_in[1] = (CAS_IN_ADDR_A[1] !== 1'bz) && CAS_IN_ADDR_A_delay[1]; // rv 0
assign CAS_IN_ADDR_A_in[20] = (CAS_IN_ADDR_A[20] !== 1'bz) && CAS_IN_ADDR_A_delay[20]; // rv 0
assign CAS_IN_ADDR_A_in[21] = (CAS_IN_ADDR_A[21] !== 1'bz) && CAS_IN_ADDR_A_delay[21]; // rv 0
assign CAS_IN_ADDR_A_in[22] = (CAS_IN_ADDR_A[22] !== 1'bz) && CAS_IN_ADDR_A_delay[22]; // rv 0
assign CAS_IN_ADDR_A_in[2] = (CAS_IN_ADDR_A[2] !== 1'bz) && CAS_IN_ADDR_A_delay[2]; // rv 0
assign CAS_IN_ADDR_A_in[3] = (CAS_IN_ADDR_A[3] !== 1'bz) && CAS_IN_ADDR_A_delay[3]; // rv 0
assign CAS_IN_ADDR_A_in[4] = (CAS_IN_ADDR_A[4] !== 1'bz) && CAS_IN_ADDR_A_delay[4]; // rv 0
assign CAS_IN_ADDR_A_in[5] = (CAS_IN_ADDR_A[5] !== 1'bz) && CAS_IN_ADDR_A_delay[5]; // rv 0
assign CAS_IN_ADDR_A_in[6] = (CAS_IN_ADDR_A[6] !== 1'bz) && CAS_IN_ADDR_A_delay[6]; // rv 0
assign CAS_IN_ADDR_A_in[7] = (CAS_IN_ADDR_A[7] !== 1'bz) && CAS_IN_ADDR_A_delay[7]; // rv 0
assign CAS_IN_ADDR_A_in[8] = (CAS_IN_ADDR_A[8] !== 1'bz) && CAS_IN_ADDR_A_delay[8]; // rv 0
assign CAS_IN_ADDR_A_in[9] = (CAS_IN_ADDR_A[9] !== 1'bz) && CAS_IN_ADDR_A_delay[9]; // rv 0
assign CAS_IN_ADDR_B_in[0] = (CAS_IN_ADDR_B[0] !== 1'bz) && CAS_IN_ADDR_B_delay[0]; // rv 0
assign CAS_IN_ADDR_B_in[10] = (CAS_IN_ADDR_B[10] !== 1'bz) && CAS_IN_ADDR_B_delay[10]; // rv 0
assign CAS_IN_ADDR_B_in[11] = (CAS_IN_ADDR_B[11] !== 1'bz) && CAS_IN_ADDR_B_delay[11]; // rv 0
assign CAS_IN_ADDR_B_in[12] = (CAS_IN_ADDR_B[12] !== 1'bz) && CAS_IN_ADDR_B_delay[12]; // rv 0
assign CAS_IN_ADDR_B_in[13] = (CAS_IN_ADDR_B[13] !== 1'bz) && CAS_IN_ADDR_B_delay[13]; // rv 0
assign CAS_IN_ADDR_B_in[14] = (CAS_IN_ADDR_B[14] !== 1'bz) && CAS_IN_ADDR_B_delay[14]; // rv 0
assign CAS_IN_ADDR_B_in[15] = (CAS_IN_ADDR_B[15] !== 1'bz) && CAS_IN_ADDR_B_delay[15]; // rv 0
assign CAS_IN_ADDR_B_in[16] = (CAS_IN_ADDR_B[16] !== 1'bz) && CAS_IN_ADDR_B_delay[16]; // rv 0
assign CAS_IN_ADDR_B_in[17] = (CAS_IN_ADDR_B[17] !== 1'bz) && CAS_IN_ADDR_B_delay[17]; // rv 0
assign CAS_IN_ADDR_B_in[18] = (CAS_IN_ADDR_B[18] !== 1'bz) && CAS_IN_ADDR_B_delay[18]; // rv 0
assign CAS_IN_ADDR_B_in[19] = (CAS_IN_ADDR_B[19] !== 1'bz) && CAS_IN_ADDR_B_delay[19]; // rv 0
assign CAS_IN_ADDR_B_in[1] = (CAS_IN_ADDR_B[1] !== 1'bz) && CAS_IN_ADDR_B_delay[1]; // rv 0
assign CAS_IN_ADDR_B_in[20] = (CAS_IN_ADDR_B[20] !== 1'bz) && CAS_IN_ADDR_B_delay[20]; // rv 0
assign CAS_IN_ADDR_B_in[21] = (CAS_IN_ADDR_B[21] !== 1'bz) && CAS_IN_ADDR_B_delay[21]; // rv 0
assign CAS_IN_ADDR_B_in[22] = (CAS_IN_ADDR_B[22] !== 1'bz) && CAS_IN_ADDR_B_delay[22]; // rv 0
assign CAS_IN_ADDR_B_in[2] = (CAS_IN_ADDR_B[2] !== 1'bz) && CAS_IN_ADDR_B_delay[2]; // rv 0
assign CAS_IN_ADDR_B_in[3] = (CAS_IN_ADDR_B[3] !== 1'bz) && CAS_IN_ADDR_B_delay[3]; // rv 0
assign CAS_IN_ADDR_B_in[4] = (CAS_IN_ADDR_B[4] !== 1'bz) && CAS_IN_ADDR_B_delay[4]; // rv 0
assign CAS_IN_ADDR_B_in[5] = (CAS_IN_ADDR_B[5] !== 1'bz) && CAS_IN_ADDR_B_delay[5]; // rv 0
assign CAS_IN_ADDR_B_in[6] = (CAS_IN_ADDR_B[6] !== 1'bz) && CAS_IN_ADDR_B_delay[6]; // rv 0
assign CAS_IN_ADDR_B_in[7] = (CAS_IN_ADDR_B[7] !== 1'bz) && CAS_IN_ADDR_B_delay[7]; // rv 0
assign CAS_IN_ADDR_B_in[8] = (CAS_IN_ADDR_B[8] !== 1'bz) && CAS_IN_ADDR_B_delay[8]; // rv 0
assign CAS_IN_ADDR_B_in[9] = (CAS_IN_ADDR_B[9] !== 1'bz) && CAS_IN_ADDR_B_delay[9]; // rv 0
assign CAS_IN_BWE_A_in[0] = (CAS_IN_BWE_A[0] !== 1'bz) && CAS_IN_BWE_A_delay[0]; // rv 0
assign CAS_IN_BWE_A_in[1] = (CAS_IN_BWE_A[1] !== 1'bz) && CAS_IN_BWE_A_delay[1]; // rv 0
assign CAS_IN_BWE_A_in[2] = (CAS_IN_BWE_A[2] !== 1'bz) && CAS_IN_BWE_A_delay[2]; // rv 0
assign CAS_IN_BWE_A_in[3] = (CAS_IN_BWE_A[3] !== 1'bz) && CAS_IN_BWE_A_delay[3]; // rv 0
assign CAS_IN_BWE_A_in[4] = (CAS_IN_BWE_A[4] !== 1'bz) && CAS_IN_BWE_A_delay[4]; // rv 0
assign CAS_IN_BWE_A_in[5] = (CAS_IN_BWE_A[5] !== 1'bz) && CAS_IN_BWE_A_delay[5]; // rv 0
assign CAS_IN_BWE_A_in[6] = (CAS_IN_BWE_A[6] !== 1'bz) && CAS_IN_BWE_A_delay[6]; // rv 0
assign CAS_IN_BWE_A_in[7] = (CAS_IN_BWE_A[7] !== 1'bz) && CAS_IN_BWE_A_delay[7]; // rv 0
assign CAS_IN_BWE_A_in[8] = (CAS_IN_BWE_A[8] !== 1'bz) && CAS_IN_BWE_A_delay[8]; // rv 0
assign CAS_IN_BWE_B_in[0] = (CAS_IN_BWE_B[0] !== 1'bz) && CAS_IN_BWE_B_delay[0]; // rv 0
assign CAS_IN_BWE_B_in[1] = (CAS_IN_BWE_B[1] !== 1'bz) && CAS_IN_BWE_B_delay[1]; // rv 0
assign CAS_IN_BWE_B_in[2] = (CAS_IN_BWE_B[2] !== 1'bz) && CAS_IN_BWE_B_delay[2]; // rv 0
assign CAS_IN_BWE_B_in[3] = (CAS_IN_BWE_B[3] !== 1'bz) && CAS_IN_BWE_B_delay[3]; // rv 0
assign CAS_IN_BWE_B_in[4] = (CAS_IN_BWE_B[4] !== 1'bz) && CAS_IN_BWE_B_delay[4]; // rv 0
assign CAS_IN_BWE_B_in[5] = (CAS_IN_BWE_B[5] !== 1'bz) && CAS_IN_BWE_B_delay[5]; // rv 0
assign CAS_IN_BWE_B_in[6] = (CAS_IN_BWE_B[6] !== 1'bz) && CAS_IN_BWE_B_delay[6]; // rv 0
assign CAS_IN_BWE_B_in[7] = (CAS_IN_BWE_B[7] !== 1'bz) && CAS_IN_BWE_B_delay[7]; // rv 0
assign CAS_IN_BWE_B_in[8] = (CAS_IN_BWE_B[8] !== 1'bz) && CAS_IN_BWE_B_delay[8]; // rv 0
assign CAS_IN_DBITERR_A_in = (CAS_IN_DBITERR_A !== 1'bz) && CAS_IN_DBITERR_A_delay; // rv 0
assign CAS_IN_DBITERR_B_in = (CAS_IN_DBITERR_B !== 1'bz) && CAS_IN_DBITERR_B_delay; // rv 0
assign CAS_IN_DIN_A_in[0] = (CAS_IN_DIN_A[0] !== 1'bz) && CAS_IN_DIN_A_delay[0]; // rv 0
assign CAS_IN_DIN_A_in[10] = (CAS_IN_DIN_A[10] !== 1'bz) && CAS_IN_DIN_A_delay[10]; // rv 0
assign CAS_IN_DIN_A_in[11] = (CAS_IN_DIN_A[11] !== 1'bz) && CAS_IN_DIN_A_delay[11]; // rv 0
assign CAS_IN_DIN_A_in[12] = (CAS_IN_DIN_A[12] !== 1'bz) && CAS_IN_DIN_A_delay[12]; // rv 0
assign CAS_IN_DIN_A_in[13] = (CAS_IN_DIN_A[13] !== 1'bz) && CAS_IN_DIN_A_delay[13]; // rv 0
assign CAS_IN_DIN_A_in[14] = (CAS_IN_DIN_A[14] !== 1'bz) && CAS_IN_DIN_A_delay[14]; // rv 0
assign CAS_IN_DIN_A_in[15] = (CAS_IN_DIN_A[15] !== 1'bz) && CAS_IN_DIN_A_delay[15]; // rv 0
assign CAS_IN_DIN_A_in[16] = (CAS_IN_DIN_A[16] !== 1'bz) && CAS_IN_DIN_A_delay[16]; // rv 0
assign CAS_IN_DIN_A_in[17] = (CAS_IN_DIN_A[17] !== 1'bz) && CAS_IN_DIN_A_delay[17]; // rv 0
assign CAS_IN_DIN_A_in[18] = (CAS_IN_DIN_A[18] !== 1'bz) && CAS_IN_DIN_A_delay[18]; // rv 0
assign CAS_IN_DIN_A_in[19] = (CAS_IN_DIN_A[19] !== 1'bz) && CAS_IN_DIN_A_delay[19]; // rv 0
assign CAS_IN_DIN_A_in[1] = (CAS_IN_DIN_A[1] !== 1'bz) && CAS_IN_DIN_A_delay[1]; // rv 0
assign CAS_IN_DIN_A_in[20] = (CAS_IN_DIN_A[20] !== 1'bz) && CAS_IN_DIN_A_delay[20]; // rv 0
assign CAS_IN_DIN_A_in[21] = (CAS_IN_DIN_A[21] !== 1'bz) && CAS_IN_DIN_A_delay[21]; // rv 0
assign CAS_IN_DIN_A_in[22] = (CAS_IN_DIN_A[22] !== 1'bz) && CAS_IN_DIN_A_delay[22]; // rv 0
assign CAS_IN_DIN_A_in[23] = (CAS_IN_DIN_A[23] !== 1'bz) && CAS_IN_DIN_A_delay[23]; // rv 0
assign CAS_IN_DIN_A_in[24] = (CAS_IN_DIN_A[24] !== 1'bz) && CAS_IN_DIN_A_delay[24]; // rv 0
assign CAS_IN_DIN_A_in[25] = (CAS_IN_DIN_A[25] !== 1'bz) && CAS_IN_DIN_A_delay[25]; // rv 0
assign CAS_IN_DIN_A_in[26] = (CAS_IN_DIN_A[26] !== 1'bz) && CAS_IN_DIN_A_delay[26]; // rv 0
assign CAS_IN_DIN_A_in[27] = (CAS_IN_DIN_A[27] !== 1'bz) && CAS_IN_DIN_A_delay[27]; // rv 0
assign CAS_IN_DIN_A_in[28] = (CAS_IN_DIN_A[28] !== 1'bz) && CAS_IN_DIN_A_delay[28]; // rv 0
assign CAS_IN_DIN_A_in[29] = (CAS_IN_DIN_A[29] !== 1'bz) && CAS_IN_DIN_A_delay[29]; // rv 0
assign CAS_IN_DIN_A_in[2] = (CAS_IN_DIN_A[2] !== 1'bz) && CAS_IN_DIN_A_delay[2]; // rv 0
assign CAS_IN_DIN_A_in[30] = (CAS_IN_DIN_A[30] !== 1'bz) && CAS_IN_DIN_A_delay[30]; // rv 0
assign CAS_IN_DIN_A_in[31] = (CAS_IN_DIN_A[31] !== 1'bz) && CAS_IN_DIN_A_delay[31]; // rv 0
assign CAS_IN_DIN_A_in[32] = (CAS_IN_DIN_A[32] !== 1'bz) && CAS_IN_DIN_A_delay[32]; // rv 0
assign CAS_IN_DIN_A_in[33] = (CAS_IN_DIN_A[33] !== 1'bz) && CAS_IN_DIN_A_delay[33]; // rv 0
assign CAS_IN_DIN_A_in[34] = (CAS_IN_DIN_A[34] !== 1'bz) && CAS_IN_DIN_A_delay[34]; // rv 0
assign CAS_IN_DIN_A_in[35] = (CAS_IN_DIN_A[35] !== 1'bz) && CAS_IN_DIN_A_delay[35]; // rv 0
assign CAS_IN_DIN_A_in[36] = (CAS_IN_DIN_A[36] !== 1'bz) && CAS_IN_DIN_A_delay[36]; // rv 0
assign CAS_IN_DIN_A_in[37] = (CAS_IN_DIN_A[37] !== 1'bz) && CAS_IN_DIN_A_delay[37]; // rv 0
assign CAS_IN_DIN_A_in[38] = (CAS_IN_DIN_A[38] !== 1'bz) && CAS_IN_DIN_A_delay[38]; // rv 0
assign CAS_IN_DIN_A_in[39] = (CAS_IN_DIN_A[39] !== 1'bz) && CAS_IN_DIN_A_delay[39]; // rv 0
assign CAS_IN_DIN_A_in[3] = (CAS_IN_DIN_A[3] !== 1'bz) && CAS_IN_DIN_A_delay[3]; // rv 0
assign CAS_IN_DIN_A_in[40] = (CAS_IN_DIN_A[40] !== 1'bz) && CAS_IN_DIN_A_delay[40]; // rv 0
assign CAS_IN_DIN_A_in[41] = (CAS_IN_DIN_A[41] !== 1'bz) && CAS_IN_DIN_A_delay[41]; // rv 0
assign CAS_IN_DIN_A_in[42] = (CAS_IN_DIN_A[42] !== 1'bz) && CAS_IN_DIN_A_delay[42]; // rv 0
assign CAS_IN_DIN_A_in[43] = (CAS_IN_DIN_A[43] !== 1'bz) && CAS_IN_DIN_A_delay[43]; // rv 0
assign CAS_IN_DIN_A_in[44] = (CAS_IN_DIN_A[44] !== 1'bz) && CAS_IN_DIN_A_delay[44]; // rv 0
assign CAS_IN_DIN_A_in[45] = (CAS_IN_DIN_A[45] !== 1'bz) && CAS_IN_DIN_A_delay[45]; // rv 0
assign CAS_IN_DIN_A_in[46] = (CAS_IN_DIN_A[46] !== 1'bz) && CAS_IN_DIN_A_delay[46]; // rv 0
assign CAS_IN_DIN_A_in[47] = (CAS_IN_DIN_A[47] !== 1'bz) && CAS_IN_DIN_A_delay[47]; // rv 0
assign CAS_IN_DIN_A_in[48] = (CAS_IN_DIN_A[48] !== 1'bz) && CAS_IN_DIN_A_delay[48]; // rv 0
assign CAS_IN_DIN_A_in[49] = (CAS_IN_DIN_A[49] !== 1'bz) && CAS_IN_DIN_A_delay[49]; // rv 0
assign CAS_IN_DIN_A_in[4] = (CAS_IN_DIN_A[4] !== 1'bz) && CAS_IN_DIN_A_delay[4]; // rv 0
assign CAS_IN_DIN_A_in[50] = (CAS_IN_DIN_A[50] !== 1'bz) && CAS_IN_DIN_A_delay[50]; // rv 0
assign CAS_IN_DIN_A_in[51] = (CAS_IN_DIN_A[51] !== 1'bz) && CAS_IN_DIN_A_delay[51]; // rv 0
assign CAS_IN_DIN_A_in[52] = (CAS_IN_DIN_A[52] !== 1'bz) && CAS_IN_DIN_A_delay[52]; // rv 0
assign CAS_IN_DIN_A_in[53] = (CAS_IN_DIN_A[53] !== 1'bz) && CAS_IN_DIN_A_delay[53]; // rv 0
assign CAS_IN_DIN_A_in[54] = (CAS_IN_DIN_A[54] !== 1'bz) && CAS_IN_DIN_A_delay[54]; // rv 0
assign CAS_IN_DIN_A_in[55] = (CAS_IN_DIN_A[55] !== 1'bz) && CAS_IN_DIN_A_delay[55]; // rv 0
assign CAS_IN_DIN_A_in[56] = (CAS_IN_DIN_A[56] !== 1'bz) && CAS_IN_DIN_A_delay[56]; // rv 0
assign CAS_IN_DIN_A_in[57] = (CAS_IN_DIN_A[57] !== 1'bz) && CAS_IN_DIN_A_delay[57]; // rv 0
assign CAS_IN_DIN_A_in[58] = (CAS_IN_DIN_A[58] !== 1'bz) && CAS_IN_DIN_A_delay[58]; // rv 0
assign CAS_IN_DIN_A_in[59] = (CAS_IN_DIN_A[59] !== 1'bz) && CAS_IN_DIN_A_delay[59]; // rv 0
assign CAS_IN_DIN_A_in[5] = (CAS_IN_DIN_A[5] !== 1'bz) && CAS_IN_DIN_A_delay[5]; // rv 0
assign CAS_IN_DIN_A_in[60] = (CAS_IN_DIN_A[60] !== 1'bz) && CAS_IN_DIN_A_delay[60]; // rv 0
assign CAS_IN_DIN_A_in[61] = (CAS_IN_DIN_A[61] !== 1'bz) && CAS_IN_DIN_A_delay[61]; // rv 0
assign CAS_IN_DIN_A_in[62] = (CAS_IN_DIN_A[62] !== 1'bz) && CAS_IN_DIN_A_delay[62]; // rv 0
assign CAS_IN_DIN_A_in[63] = (CAS_IN_DIN_A[63] !== 1'bz) && CAS_IN_DIN_A_delay[63]; // rv 0
assign CAS_IN_DIN_A_in[64] = (CAS_IN_DIN_A[64] !== 1'bz) && CAS_IN_DIN_A_delay[64]; // rv 0
assign CAS_IN_DIN_A_in[65] = (CAS_IN_DIN_A[65] !== 1'bz) && CAS_IN_DIN_A_delay[65]; // rv 0
assign CAS_IN_DIN_A_in[66] = (CAS_IN_DIN_A[66] !== 1'bz) && CAS_IN_DIN_A_delay[66]; // rv 0
assign CAS_IN_DIN_A_in[67] = (CAS_IN_DIN_A[67] !== 1'bz) && CAS_IN_DIN_A_delay[67]; // rv 0
assign CAS_IN_DIN_A_in[68] = (CAS_IN_DIN_A[68] !== 1'bz) && CAS_IN_DIN_A_delay[68]; // rv 0
assign CAS_IN_DIN_A_in[69] = (CAS_IN_DIN_A[69] !== 1'bz) && CAS_IN_DIN_A_delay[69]; // rv 0
assign CAS_IN_DIN_A_in[6] = (CAS_IN_DIN_A[6] !== 1'bz) && CAS_IN_DIN_A_delay[6]; // rv 0
assign CAS_IN_DIN_A_in[70] = (CAS_IN_DIN_A[70] !== 1'bz) && CAS_IN_DIN_A_delay[70]; // rv 0
assign CAS_IN_DIN_A_in[71] = (CAS_IN_DIN_A[71] !== 1'bz) && CAS_IN_DIN_A_delay[71]; // rv 0
assign CAS_IN_DIN_A_in[7] = (CAS_IN_DIN_A[7] !== 1'bz) && CAS_IN_DIN_A_delay[7]; // rv 0
assign CAS_IN_DIN_A_in[8] = (CAS_IN_DIN_A[8] !== 1'bz) && CAS_IN_DIN_A_delay[8]; // rv 0
assign CAS_IN_DIN_A_in[9] = (CAS_IN_DIN_A[9] !== 1'bz) && CAS_IN_DIN_A_delay[9]; // rv 0
assign CAS_IN_DIN_B_in[0] = (CAS_IN_DIN_B[0] !== 1'bz) && CAS_IN_DIN_B_delay[0]; // rv 0
assign CAS_IN_DIN_B_in[10] = (CAS_IN_DIN_B[10] !== 1'bz) && CAS_IN_DIN_B_delay[10]; // rv 0
assign CAS_IN_DIN_B_in[11] = (CAS_IN_DIN_B[11] !== 1'bz) && CAS_IN_DIN_B_delay[11]; // rv 0
assign CAS_IN_DIN_B_in[12] = (CAS_IN_DIN_B[12] !== 1'bz) && CAS_IN_DIN_B_delay[12]; // rv 0
assign CAS_IN_DIN_B_in[13] = (CAS_IN_DIN_B[13] !== 1'bz) && CAS_IN_DIN_B_delay[13]; // rv 0
assign CAS_IN_DIN_B_in[14] = (CAS_IN_DIN_B[14] !== 1'bz) && CAS_IN_DIN_B_delay[14]; // rv 0
assign CAS_IN_DIN_B_in[15] = (CAS_IN_DIN_B[15] !== 1'bz) && CAS_IN_DIN_B_delay[15]; // rv 0
assign CAS_IN_DIN_B_in[16] = (CAS_IN_DIN_B[16] !== 1'bz) && CAS_IN_DIN_B_delay[16]; // rv 0
assign CAS_IN_DIN_B_in[17] = (CAS_IN_DIN_B[17] !== 1'bz) && CAS_IN_DIN_B_delay[17]; // rv 0
assign CAS_IN_DIN_B_in[18] = (CAS_IN_DIN_B[18] !== 1'bz) && CAS_IN_DIN_B_delay[18]; // rv 0
assign CAS_IN_DIN_B_in[19] = (CAS_IN_DIN_B[19] !== 1'bz) && CAS_IN_DIN_B_delay[19]; // rv 0
assign CAS_IN_DIN_B_in[1] = (CAS_IN_DIN_B[1] !== 1'bz) && CAS_IN_DIN_B_delay[1]; // rv 0
assign CAS_IN_DIN_B_in[20] = (CAS_IN_DIN_B[20] !== 1'bz) && CAS_IN_DIN_B_delay[20]; // rv 0
assign CAS_IN_DIN_B_in[21] = (CAS_IN_DIN_B[21] !== 1'bz) && CAS_IN_DIN_B_delay[21]; // rv 0
assign CAS_IN_DIN_B_in[22] = (CAS_IN_DIN_B[22] !== 1'bz) && CAS_IN_DIN_B_delay[22]; // rv 0
assign CAS_IN_DIN_B_in[23] = (CAS_IN_DIN_B[23] !== 1'bz) && CAS_IN_DIN_B_delay[23]; // rv 0
assign CAS_IN_DIN_B_in[24] = (CAS_IN_DIN_B[24] !== 1'bz) && CAS_IN_DIN_B_delay[24]; // rv 0
assign CAS_IN_DIN_B_in[25] = (CAS_IN_DIN_B[25] !== 1'bz) && CAS_IN_DIN_B_delay[25]; // rv 0
assign CAS_IN_DIN_B_in[26] = (CAS_IN_DIN_B[26] !== 1'bz) && CAS_IN_DIN_B_delay[26]; // rv 0
assign CAS_IN_DIN_B_in[27] = (CAS_IN_DIN_B[27] !== 1'bz) && CAS_IN_DIN_B_delay[27]; // rv 0
assign CAS_IN_DIN_B_in[28] = (CAS_IN_DIN_B[28] !== 1'bz) && CAS_IN_DIN_B_delay[28]; // rv 0
assign CAS_IN_DIN_B_in[29] = (CAS_IN_DIN_B[29] !== 1'bz) && CAS_IN_DIN_B_delay[29]; // rv 0
assign CAS_IN_DIN_B_in[2] = (CAS_IN_DIN_B[2] !== 1'bz) && CAS_IN_DIN_B_delay[2]; // rv 0
assign CAS_IN_DIN_B_in[30] = (CAS_IN_DIN_B[30] !== 1'bz) && CAS_IN_DIN_B_delay[30]; // rv 0
assign CAS_IN_DIN_B_in[31] = (CAS_IN_DIN_B[31] !== 1'bz) && CAS_IN_DIN_B_delay[31]; // rv 0
assign CAS_IN_DIN_B_in[32] = (CAS_IN_DIN_B[32] !== 1'bz) && CAS_IN_DIN_B_delay[32]; // rv 0
assign CAS_IN_DIN_B_in[33] = (CAS_IN_DIN_B[33] !== 1'bz) && CAS_IN_DIN_B_delay[33]; // rv 0
assign CAS_IN_DIN_B_in[34] = (CAS_IN_DIN_B[34] !== 1'bz) && CAS_IN_DIN_B_delay[34]; // rv 0
assign CAS_IN_DIN_B_in[35] = (CAS_IN_DIN_B[35] !== 1'bz) && CAS_IN_DIN_B_delay[35]; // rv 0
assign CAS_IN_DIN_B_in[36] = (CAS_IN_DIN_B[36] !== 1'bz) && CAS_IN_DIN_B_delay[36]; // rv 0
assign CAS_IN_DIN_B_in[37] = (CAS_IN_DIN_B[37] !== 1'bz) && CAS_IN_DIN_B_delay[37]; // rv 0
assign CAS_IN_DIN_B_in[38] = (CAS_IN_DIN_B[38] !== 1'bz) && CAS_IN_DIN_B_delay[38]; // rv 0
assign CAS_IN_DIN_B_in[39] = (CAS_IN_DIN_B[39] !== 1'bz) && CAS_IN_DIN_B_delay[39]; // rv 0
assign CAS_IN_DIN_B_in[3] = (CAS_IN_DIN_B[3] !== 1'bz) && CAS_IN_DIN_B_delay[3]; // rv 0
assign CAS_IN_DIN_B_in[40] = (CAS_IN_DIN_B[40] !== 1'bz) && CAS_IN_DIN_B_delay[40]; // rv 0
assign CAS_IN_DIN_B_in[41] = (CAS_IN_DIN_B[41] !== 1'bz) && CAS_IN_DIN_B_delay[41]; // rv 0
assign CAS_IN_DIN_B_in[42] = (CAS_IN_DIN_B[42] !== 1'bz) && CAS_IN_DIN_B_delay[42]; // rv 0
assign CAS_IN_DIN_B_in[43] = (CAS_IN_DIN_B[43] !== 1'bz) && CAS_IN_DIN_B_delay[43]; // rv 0
assign CAS_IN_DIN_B_in[44] = (CAS_IN_DIN_B[44] !== 1'bz) && CAS_IN_DIN_B_delay[44]; // rv 0
assign CAS_IN_DIN_B_in[45] = (CAS_IN_DIN_B[45] !== 1'bz) && CAS_IN_DIN_B_delay[45]; // rv 0
assign CAS_IN_DIN_B_in[46] = (CAS_IN_DIN_B[46] !== 1'bz) && CAS_IN_DIN_B_delay[46]; // rv 0
assign CAS_IN_DIN_B_in[47] = (CAS_IN_DIN_B[47] !== 1'bz) && CAS_IN_DIN_B_delay[47]; // rv 0
assign CAS_IN_DIN_B_in[48] = (CAS_IN_DIN_B[48] !== 1'bz) && CAS_IN_DIN_B_delay[48]; // rv 0
assign CAS_IN_DIN_B_in[49] = (CAS_IN_DIN_B[49] !== 1'bz) && CAS_IN_DIN_B_delay[49]; // rv 0
assign CAS_IN_DIN_B_in[4] = (CAS_IN_DIN_B[4] !== 1'bz) && CAS_IN_DIN_B_delay[4]; // rv 0
assign CAS_IN_DIN_B_in[50] = (CAS_IN_DIN_B[50] !== 1'bz) && CAS_IN_DIN_B_delay[50]; // rv 0
assign CAS_IN_DIN_B_in[51] = (CAS_IN_DIN_B[51] !== 1'bz) && CAS_IN_DIN_B_delay[51]; // rv 0
assign CAS_IN_DIN_B_in[52] = (CAS_IN_DIN_B[52] !== 1'bz) && CAS_IN_DIN_B_delay[52]; // rv 0
assign CAS_IN_DIN_B_in[53] = (CAS_IN_DIN_B[53] !== 1'bz) && CAS_IN_DIN_B_delay[53]; // rv 0
assign CAS_IN_DIN_B_in[54] = (CAS_IN_DIN_B[54] !== 1'bz) && CAS_IN_DIN_B_delay[54]; // rv 0
assign CAS_IN_DIN_B_in[55] = (CAS_IN_DIN_B[55] !== 1'bz) && CAS_IN_DIN_B_delay[55]; // rv 0
assign CAS_IN_DIN_B_in[56] = (CAS_IN_DIN_B[56] !== 1'bz) && CAS_IN_DIN_B_delay[56]; // rv 0
assign CAS_IN_DIN_B_in[57] = (CAS_IN_DIN_B[57] !== 1'bz) && CAS_IN_DIN_B_delay[57]; // rv 0
assign CAS_IN_DIN_B_in[58] = (CAS_IN_DIN_B[58] !== 1'bz) && CAS_IN_DIN_B_delay[58]; // rv 0
assign CAS_IN_DIN_B_in[59] = (CAS_IN_DIN_B[59] !== 1'bz) && CAS_IN_DIN_B_delay[59]; // rv 0
assign CAS_IN_DIN_B_in[5] = (CAS_IN_DIN_B[5] !== 1'bz) && CAS_IN_DIN_B_delay[5]; // rv 0
assign CAS_IN_DIN_B_in[60] = (CAS_IN_DIN_B[60] !== 1'bz) && CAS_IN_DIN_B_delay[60]; // rv 0
assign CAS_IN_DIN_B_in[61] = (CAS_IN_DIN_B[61] !== 1'bz) && CAS_IN_DIN_B_delay[61]; // rv 0
assign CAS_IN_DIN_B_in[62] = (CAS_IN_DIN_B[62] !== 1'bz) && CAS_IN_DIN_B_delay[62]; // rv 0
assign CAS_IN_DIN_B_in[63] = (CAS_IN_DIN_B[63] !== 1'bz) && CAS_IN_DIN_B_delay[63]; // rv 0
assign CAS_IN_DIN_B_in[64] = (CAS_IN_DIN_B[64] !== 1'bz) && CAS_IN_DIN_B_delay[64]; // rv 0
assign CAS_IN_DIN_B_in[65] = (CAS_IN_DIN_B[65] !== 1'bz) && CAS_IN_DIN_B_delay[65]; // rv 0
assign CAS_IN_DIN_B_in[66] = (CAS_IN_DIN_B[66] !== 1'bz) && CAS_IN_DIN_B_delay[66]; // rv 0
assign CAS_IN_DIN_B_in[67] = (CAS_IN_DIN_B[67] !== 1'bz) && CAS_IN_DIN_B_delay[67]; // rv 0
assign CAS_IN_DIN_B_in[68] = (CAS_IN_DIN_B[68] !== 1'bz) && CAS_IN_DIN_B_delay[68]; // rv 0
assign CAS_IN_DIN_B_in[69] = (CAS_IN_DIN_B[69] !== 1'bz) && CAS_IN_DIN_B_delay[69]; // rv 0
assign CAS_IN_DIN_B_in[6] = (CAS_IN_DIN_B[6] !== 1'bz) && CAS_IN_DIN_B_delay[6]; // rv 0
assign CAS_IN_DIN_B_in[70] = (CAS_IN_DIN_B[70] !== 1'bz) && CAS_IN_DIN_B_delay[70]; // rv 0
assign CAS_IN_DIN_B_in[71] = (CAS_IN_DIN_B[71] !== 1'bz) && CAS_IN_DIN_B_delay[71]; // rv 0
assign CAS_IN_DIN_B_in[7] = (CAS_IN_DIN_B[7] !== 1'bz) && CAS_IN_DIN_B_delay[7]; // rv 0
assign CAS_IN_DIN_B_in[8] = (CAS_IN_DIN_B[8] !== 1'bz) && CAS_IN_DIN_B_delay[8]; // rv 0
assign CAS_IN_DIN_B_in[9] = (CAS_IN_DIN_B[9] !== 1'bz) && CAS_IN_DIN_B_delay[9]; // rv 0
assign CAS_IN_DOUT_A_in[0] = (CAS_IN_DOUT_A[0] !== 1'bz) && CAS_IN_DOUT_A_delay[0]; // rv 0
assign CAS_IN_DOUT_A_in[10] = (CAS_IN_DOUT_A[10] !== 1'bz) && CAS_IN_DOUT_A_delay[10]; // rv 0
assign CAS_IN_DOUT_A_in[11] = (CAS_IN_DOUT_A[11] !== 1'bz) && CAS_IN_DOUT_A_delay[11]; // rv 0
assign CAS_IN_DOUT_A_in[12] = (CAS_IN_DOUT_A[12] !== 1'bz) && CAS_IN_DOUT_A_delay[12]; // rv 0
assign CAS_IN_DOUT_A_in[13] = (CAS_IN_DOUT_A[13] !== 1'bz) && CAS_IN_DOUT_A_delay[13]; // rv 0
assign CAS_IN_DOUT_A_in[14] = (CAS_IN_DOUT_A[14] !== 1'bz) && CAS_IN_DOUT_A_delay[14]; // rv 0
assign CAS_IN_DOUT_A_in[15] = (CAS_IN_DOUT_A[15] !== 1'bz) && CAS_IN_DOUT_A_delay[15]; // rv 0
assign CAS_IN_DOUT_A_in[16] = (CAS_IN_DOUT_A[16] !== 1'bz) && CAS_IN_DOUT_A_delay[16]; // rv 0
assign CAS_IN_DOUT_A_in[17] = (CAS_IN_DOUT_A[17] !== 1'bz) && CAS_IN_DOUT_A_delay[17]; // rv 0
assign CAS_IN_DOUT_A_in[18] = (CAS_IN_DOUT_A[18] !== 1'bz) && CAS_IN_DOUT_A_delay[18]; // rv 0
assign CAS_IN_DOUT_A_in[19] = (CAS_IN_DOUT_A[19] !== 1'bz) && CAS_IN_DOUT_A_delay[19]; // rv 0
assign CAS_IN_DOUT_A_in[1] = (CAS_IN_DOUT_A[1] !== 1'bz) && CAS_IN_DOUT_A_delay[1]; // rv 0
assign CAS_IN_DOUT_A_in[20] = (CAS_IN_DOUT_A[20] !== 1'bz) && CAS_IN_DOUT_A_delay[20]; // rv 0
assign CAS_IN_DOUT_A_in[21] = (CAS_IN_DOUT_A[21] !== 1'bz) && CAS_IN_DOUT_A_delay[21]; // rv 0
assign CAS_IN_DOUT_A_in[22] = (CAS_IN_DOUT_A[22] !== 1'bz) && CAS_IN_DOUT_A_delay[22]; // rv 0
assign CAS_IN_DOUT_A_in[23] = (CAS_IN_DOUT_A[23] !== 1'bz) && CAS_IN_DOUT_A_delay[23]; // rv 0
assign CAS_IN_DOUT_A_in[24] = (CAS_IN_DOUT_A[24] !== 1'bz) && CAS_IN_DOUT_A_delay[24]; // rv 0
assign CAS_IN_DOUT_A_in[25] = (CAS_IN_DOUT_A[25] !== 1'bz) && CAS_IN_DOUT_A_delay[25]; // rv 0
assign CAS_IN_DOUT_A_in[26] = (CAS_IN_DOUT_A[26] !== 1'bz) && CAS_IN_DOUT_A_delay[26]; // rv 0
assign CAS_IN_DOUT_A_in[27] = (CAS_IN_DOUT_A[27] !== 1'bz) && CAS_IN_DOUT_A_delay[27]; // rv 0
assign CAS_IN_DOUT_A_in[28] = (CAS_IN_DOUT_A[28] !== 1'bz) && CAS_IN_DOUT_A_delay[28]; // rv 0
assign CAS_IN_DOUT_A_in[29] = (CAS_IN_DOUT_A[29] !== 1'bz) && CAS_IN_DOUT_A_delay[29]; // rv 0
assign CAS_IN_DOUT_A_in[2] = (CAS_IN_DOUT_A[2] !== 1'bz) && CAS_IN_DOUT_A_delay[2]; // rv 0
assign CAS_IN_DOUT_A_in[30] = (CAS_IN_DOUT_A[30] !== 1'bz) && CAS_IN_DOUT_A_delay[30]; // rv 0
assign CAS_IN_DOUT_A_in[31] = (CAS_IN_DOUT_A[31] !== 1'bz) && CAS_IN_DOUT_A_delay[31]; // rv 0
assign CAS_IN_DOUT_A_in[32] = (CAS_IN_DOUT_A[32] !== 1'bz) && CAS_IN_DOUT_A_delay[32]; // rv 0
assign CAS_IN_DOUT_A_in[33] = (CAS_IN_DOUT_A[33] !== 1'bz) && CAS_IN_DOUT_A_delay[33]; // rv 0
assign CAS_IN_DOUT_A_in[34] = (CAS_IN_DOUT_A[34] !== 1'bz) && CAS_IN_DOUT_A_delay[34]; // rv 0
assign CAS_IN_DOUT_A_in[35] = (CAS_IN_DOUT_A[35] !== 1'bz) && CAS_IN_DOUT_A_delay[35]; // rv 0
assign CAS_IN_DOUT_A_in[36] = (CAS_IN_DOUT_A[36] !== 1'bz) && CAS_IN_DOUT_A_delay[36]; // rv 0
assign CAS_IN_DOUT_A_in[37] = (CAS_IN_DOUT_A[37] !== 1'bz) && CAS_IN_DOUT_A_delay[37]; // rv 0
assign CAS_IN_DOUT_A_in[38] = (CAS_IN_DOUT_A[38] !== 1'bz) && CAS_IN_DOUT_A_delay[38]; // rv 0
assign CAS_IN_DOUT_A_in[39] = (CAS_IN_DOUT_A[39] !== 1'bz) && CAS_IN_DOUT_A_delay[39]; // rv 0
assign CAS_IN_DOUT_A_in[3] = (CAS_IN_DOUT_A[3] !== 1'bz) && CAS_IN_DOUT_A_delay[3]; // rv 0
assign CAS_IN_DOUT_A_in[40] = (CAS_IN_DOUT_A[40] !== 1'bz) && CAS_IN_DOUT_A_delay[40]; // rv 0
assign CAS_IN_DOUT_A_in[41] = (CAS_IN_DOUT_A[41] !== 1'bz) && CAS_IN_DOUT_A_delay[41]; // rv 0
assign CAS_IN_DOUT_A_in[42] = (CAS_IN_DOUT_A[42] !== 1'bz) && CAS_IN_DOUT_A_delay[42]; // rv 0
assign CAS_IN_DOUT_A_in[43] = (CAS_IN_DOUT_A[43] !== 1'bz) && CAS_IN_DOUT_A_delay[43]; // rv 0
assign CAS_IN_DOUT_A_in[44] = (CAS_IN_DOUT_A[44] !== 1'bz) && CAS_IN_DOUT_A_delay[44]; // rv 0
assign CAS_IN_DOUT_A_in[45] = (CAS_IN_DOUT_A[45] !== 1'bz) && CAS_IN_DOUT_A_delay[45]; // rv 0
assign CAS_IN_DOUT_A_in[46] = (CAS_IN_DOUT_A[46] !== 1'bz) && CAS_IN_DOUT_A_delay[46]; // rv 0
assign CAS_IN_DOUT_A_in[47] = (CAS_IN_DOUT_A[47] !== 1'bz) && CAS_IN_DOUT_A_delay[47]; // rv 0
assign CAS_IN_DOUT_A_in[48] = (CAS_IN_DOUT_A[48] !== 1'bz) && CAS_IN_DOUT_A_delay[48]; // rv 0
assign CAS_IN_DOUT_A_in[49] = (CAS_IN_DOUT_A[49] !== 1'bz) && CAS_IN_DOUT_A_delay[49]; // rv 0
assign CAS_IN_DOUT_A_in[4] = (CAS_IN_DOUT_A[4] !== 1'bz) && CAS_IN_DOUT_A_delay[4]; // rv 0
assign CAS_IN_DOUT_A_in[50] = (CAS_IN_DOUT_A[50] !== 1'bz) && CAS_IN_DOUT_A_delay[50]; // rv 0
assign CAS_IN_DOUT_A_in[51] = (CAS_IN_DOUT_A[51] !== 1'bz) && CAS_IN_DOUT_A_delay[51]; // rv 0
assign CAS_IN_DOUT_A_in[52] = (CAS_IN_DOUT_A[52] !== 1'bz) && CAS_IN_DOUT_A_delay[52]; // rv 0
assign CAS_IN_DOUT_A_in[53] = (CAS_IN_DOUT_A[53] !== 1'bz) && CAS_IN_DOUT_A_delay[53]; // rv 0
assign CAS_IN_DOUT_A_in[54] = (CAS_IN_DOUT_A[54] !== 1'bz) && CAS_IN_DOUT_A_delay[54]; // rv 0
assign CAS_IN_DOUT_A_in[55] = (CAS_IN_DOUT_A[55] !== 1'bz) && CAS_IN_DOUT_A_delay[55]; // rv 0
assign CAS_IN_DOUT_A_in[56] = (CAS_IN_DOUT_A[56] !== 1'bz) && CAS_IN_DOUT_A_delay[56]; // rv 0
assign CAS_IN_DOUT_A_in[57] = (CAS_IN_DOUT_A[57] !== 1'bz) && CAS_IN_DOUT_A_delay[57]; // rv 0
assign CAS_IN_DOUT_A_in[58] = (CAS_IN_DOUT_A[58] !== 1'bz) && CAS_IN_DOUT_A_delay[58]; // rv 0
assign CAS_IN_DOUT_A_in[59] = (CAS_IN_DOUT_A[59] !== 1'bz) && CAS_IN_DOUT_A_delay[59]; // rv 0
assign CAS_IN_DOUT_A_in[5] = (CAS_IN_DOUT_A[5] !== 1'bz) && CAS_IN_DOUT_A_delay[5]; // rv 0
assign CAS_IN_DOUT_A_in[60] = (CAS_IN_DOUT_A[60] !== 1'bz) && CAS_IN_DOUT_A_delay[60]; // rv 0
assign CAS_IN_DOUT_A_in[61] = (CAS_IN_DOUT_A[61] !== 1'bz) && CAS_IN_DOUT_A_delay[61]; // rv 0
assign CAS_IN_DOUT_A_in[62] = (CAS_IN_DOUT_A[62] !== 1'bz) && CAS_IN_DOUT_A_delay[62]; // rv 0
assign CAS_IN_DOUT_A_in[63] = (CAS_IN_DOUT_A[63] !== 1'bz) && CAS_IN_DOUT_A_delay[63]; // rv 0
assign CAS_IN_DOUT_A_in[64] = (CAS_IN_DOUT_A[64] !== 1'bz) && CAS_IN_DOUT_A_delay[64]; // rv 0
assign CAS_IN_DOUT_A_in[65] = (CAS_IN_DOUT_A[65] !== 1'bz) && CAS_IN_DOUT_A_delay[65]; // rv 0
assign CAS_IN_DOUT_A_in[66] = (CAS_IN_DOUT_A[66] !== 1'bz) && CAS_IN_DOUT_A_delay[66]; // rv 0
assign CAS_IN_DOUT_A_in[67] = (CAS_IN_DOUT_A[67] !== 1'bz) && CAS_IN_DOUT_A_delay[67]; // rv 0
assign CAS_IN_DOUT_A_in[68] = (CAS_IN_DOUT_A[68] !== 1'bz) && CAS_IN_DOUT_A_delay[68]; // rv 0
assign CAS_IN_DOUT_A_in[69] = (CAS_IN_DOUT_A[69] !== 1'bz) && CAS_IN_DOUT_A_delay[69]; // rv 0
assign CAS_IN_DOUT_A_in[6] = (CAS_IN_DOUT_A[6] !== 1'bz) && CAS_IN_DOUT_A_delay[6]; // rv 0
assign CAS_IN_DOUT_A_in[70] = (CAS_IN_DOUT_A[70] !== 1'bz) && CAS_IN_DOUT_A_delay[70]; // rv 0
assign CAS_IN_DOUT_A_in[71] = (CAS_IN_DOUT_A[71] !== 1'bz) && CAS_IN_DOUT_A_delay[71]; // rv 0
assign CAS_IN_DOUT_A_in[7] = (CAS_IN_DOUT_A[7] !== 1'bz) && CAS_IN_DOUT_A_delay[7]; // rv 0
assign CAS_IN_DOUT_A_in[8] = (CAS_IN_DOUT_A[8] !== 1'bz) && CAS_IN_DOUT_A_delay[8]; // rv 0
assign CAS_IN_DOUT_A_in[9] = (CAS_IN_DOUT_A[9] !== 1'bz) && CAS_IN_DOUT_A_delay[9]; // rv 0
assign CAS_IN_DOUT_B_in[0] = (CAS_IN_DOUT_B[0] !== 1'bz) && CAS_IN_DOUT_B_delay[0]; // rv 0
assign CAS_IN_DOUT_B_in[10] = (CAS_IN_DOUT_B[10] !== 1'bz) && CAS_IN_DOUT_B_delay[10]; // rv 0
assign CAS_IN_DOUT_B_in[11] = (CAS_IN_DOUT_B[11] !== 1'bz) && CAS_IN_DOUT_B_delay[11]; // rv 0
assign CAS_IN_DOUT_B_in[12] = (CAS_IN_DOUT_B[12] !== 1'bz) && CAS_IN_DOUT_B_delay[12]; // rv 0
assign CAS_IN_DOUT_B_in[13] = (CAS_IN_DOUT_B[13] !== 1'bz) && CAS_IN_DOUT_B_delay[13]; // rv 0
assign CAS_IN_DOUT_B_in[14] = (CAS_IN_DOUT_B[14] !== 1'bz) && CAS_IN_DOUT_B_delay[14]; // rv 0
assign CAS_IN_DOUT_B_in[15] = (CAS_IN_DOUT_B[15] !== 1'bz) && CAS_IN_DOUT_B_delay[15]; // rv 0
assign CAS_IN_DOUT_B_in[16] = (CAS_IN_DOUT_B[16] !== 1'bz) && CAS_IN_DOUT_B_delay[16]; // rv 0
assign CAS_IN_DOUT_B_in[17] = (CAS_IN_DOUT_B[17] !== 1'bz) && CAS_IN_DOUT_B_delay[17]; // rv 0
assign CAS_IN_DOUT_B_in[18] = (CAS_IN_DOUT_B[18] !== 1'bz) && CAS_IN_DOUT_B_delay[18]; // rv 0
assign CAS_IN_DOUT_B_in[19] = (CAS_IN_DOUT_B[19] !== 1'bz) && CAS_IN_DOUT_B_delay[19]; // rv 0
assign CAS_IN_DOUT_B_in[1] = (CAS_IN_DOUT_B[1] !== 1'bz) && CAS_IN_DOUT_B_delay[1]; // rv 0
assign CAS_IN_DOUT_B_in[20] = (CAS_IN_DOUT_B[20] !== 1'bz) && CAS_IN_DOUT_B_delay[20]; // rv 0
assign CAS_IN_DOUT_B_in[21] = (CAS_IN_DOUT_B[21] !== 1'bz) && CAS_IN_DOUT_B_delay[21]; // rv 0
assign CAS_IN_DOUT_B_in[22] = (CAS_IN_DOUT_B[22] !== 1'bz) && CAS_IN_DOUT_B_delay[22]; // rv 0
assign CAS_IN_DOUT_B_in[23] = (CAS_IN_DOUT_B[23] !== 1'bz) && CAS_IN_DOUT_B_delay[23]; // rv 0
assign CAS_IN_DOUT_B_in[24] = (CAS_IN_DOUT_B[24] !== 1'bz) && CAS_IN_DOUT_B_delay[24]; // rv 0
assign CAS_IN_DOUT_B_in[25] = (CAS_IN_DOUT_B[25] !== 1'bz) && CAS_IN_DOUT_B_delay[25]; // rv 0
assign CAS_IN_DOUT_B_in[26] = (CAS_IN_DOUT_B[26] !== 1'bz) && CAS_IN_DOUT_B_delay[26]; // rv 0
assign CAS_IN_DOUT_B_in[27] = (CAS_IN_DOUT_B[27] !== 1'bz) && CAS_IN_DOUT_B_delay[27]; // rv 0
assign CAS_IN_DOUT_B_in[28] = (CAS_IN_DOUT_B[28] !== 1'bz) && CAS_IN_DOUT_B_delay[28]; // rv 0
assign CAS_IN_DOUT_B_in[29] = (CAS_IN_DOUT_B[29] !== 1'bz) && CAS_IN_DOUT_B_delay[29]; // rv 0
assign CAS_IN_DOUT_B_in[2] = (CAS_IN_DOUT_B[2] !== 1'bz) && CAS_IN_DOUT_B_delay[2]; // rv 0
assign CAS_IN_DOUT_B_in[30] = (CAS_IN_DOUT_B[30] !== 1'bz) && CAS_IN_DOUT_B_delay[30]; // rv 0
assign CAS_IN_DOUT_B_in[31] = (CAS_IN_DOUT_B[31] !== 1'bz) && CAS_IN_DOUT_B_delay[31]; // rv 0
assign CAS_IN_DOUT_B_in[32] = (CAS_IN_DOUT_B[32] !== 1'bz) && CAS_IN_DOUT_B_delay[32]; // rv 0
assign CAS_IN_DOUT_B_in[33] = (CAS_IN_DOUT_B[33] !== 1'bz) && CAS_IN_DOUT_B_delay[33]; // rv 0
assign CAS_IN_DOUT_B_in[34] = (CAS_IN_DOUT_B[34] !== 1'bz) && CAS_IN_DOUT_B_delay[34]; // rv 0
assign CAS_IN_DOUT_B_in[35] = (CAS_IN_DOUT_B[35] !== 1'bz) && CAS_IN_DOUT_B_delay[35]; // rv 0
assign CAS_IN_DOUT_B_in[36] = (CAS_IN_DOUT_B[36] !== 1'bz) && CAS_IN_DOUT_B_delay[36]; // rv 0
assign CAS_IN_DOUT_B_in[37] = (CAS_IN_DOUT_B[37] !== 1'bz) && CAS_IN_DOUT_B_delay[37]; // rv 0
assign CAS_IN_DOUT_B_in[38] = (CAS_IN_DOUT_B[38] !== 1'bz) && CAS_IN_DOUT_B_delay[38]; // rv 0
assign CAS_IN_DOUT_B_in[39] = (CAS_IN_DOUT_B[39] !== 1'bz) && CAS_IN_DOUT_B_delay[39]; // rv 0
assign CAS_IN_DOUT_B_in[3] = (CAS_IN_DOUT_B[3] !== 1'bz) && CAS_IN_DOUT_B_delay[3]; // rv 0
assign CAS_IN_DOUT_B_in[40] = (CAS_IN_DOUT_B[40] !== 1'bz) && CAS_IN_DOUT_B_delay[40]; // rv 0
assign CAS_IN_DOUT_B_in[41] = (CAS_IN_DOUT_B[41] !== 1'bz) && CAS_IN_DOUT_B_delay[41]; // rv 0
assign CAS_IN_DOUT_B_in[42] = (CAS_IN_DOUT_B[42] !== 1'bz) && CAS_IN_DOUT_B_delay[42]; // rv 0
assign CAS_IN_DOUT_B_in[43] = (CAS_IN_DOUT_B[43] !== 1'bz) && CAS_IN_DOUT_B_delay[43]; // rv 0
assign CAS_IN_DOUT_B_in[44] = (CAS_IN_DOUT_B[44] !== 1'bz) && CAS_IN_DOUT_B_delay[44]; // rv 0
assign CAS_IN_DOUT_B_in[45] = (CAS_IN_DOUT_B[45] !== 1'bz) && CAS_IN_DOUT_B_delay[45]; // rv 0
assign CAS_IN_DOUT_B_in[46] = (CAS_IN_DOUT_B[46] !== 1'bz) && CAS_IN_DOUT_B_delay[46]; // rv 0
assign CAS_IN_DOUT_B_in[47] = (CAS_IN_DOUT_B[47] !== 1'bz) && CAS_IN_DOUT_B_delay[47]; // rv 0
assign CAS_IN_DOUT_B_in[48] = (CAS_IN_DOUT_B[48] !== 1'bz) && CAS_IN_DOUT_B_delay[48]; // rv 0
assign CAS_IN_DOUT_B_in[49] = (CAS_IN_DOUT_B[49] !== 1'bz) && CAS_IN_DOUT_B_delay[49]; // rv 0
assign CAS_IN_DOUT_B_in[4] = (CAS_IN_DOUT_B[4] !== 1'bz) && CAS_IN_DOUT_B_delay[4]; // rv 0
assign CAS_IN_DOUT_B_in[50] = (CAS_IN_DOUT_B[50] !== 1'bz) && CAS_IN_DOUT_B_delay[50]; // rv 0
assign CAS_IN_DOUT_B_in[51] = (CAS_IN_DOUT_B[51] !== 1'bz) && CAS_IN_DOUT_B_delay[51]; // rv 0
assign CAS_IN_DOUT_B_in[52] = (CAS_IN_DOUT_B[52] !== 1'bz) && CAS_IN_DOUT_B_delay[52]; // rv 0
assign CAS_IN_DOUT_B_in[53] = (CAS_IN_DOUT_B[53] !== 1'bz) && CAS_IN_DOUT_B_delay[53]; // rv 0
assign CAS_IN_DOUT_B_in[54] = (CAS_IN_DOUT_B[54] !== 1'bz) && CAS_IN_DOUT_B_delay[54]; // rv 0
assign CAS_IN_DOUT_B_in[55] = (CAS_IN_DOUT_B[55] !== 1'bz) && CAS_IN_DOUT_B_delay[55]; // rv 0
assign CAS_IN_DOUT_B_in[56] = (CAS_IN_DOUT_B[56] !== 1'bz) && CAS_IN_DOUT_B_delay[56]; // rv 0
assign CAS_IN_DOUT_B_in[57] = (CAS_IN_DOUT_B[57] !== 1'bz) && CAS_IN_DOUT_B_delay[57]; // rv 0
assign CAS_IN_DOUT_B_in[58] = (CAS_IN_DOUT_B[58] !== 1'bz) && CAS_IN_DOUT_B_delay[58]; // rv 0
assign CAS_IN_DOUT_B_in[59] = (CAS_IN_DOUT_B[59] !== 1'bz) && CAS_IN_DOUT_B_delay[59]; // rv 0
assign CAS_IN_DOUT_B_in[5] = (CAS_IN_DOUT_B[5] !== 1'bz) && CAS_IN_DOUT_B_delay[5]; // rv 0
assign CAS_IN_DOUT_B_in[60] = (CAS_IN_DOUT_B[60] !== 1'bz) && CAS_IN_DOUT_B_delay[60]; // rv 0
assign CAS_IN_DOUT_B_in[61] = (CAS_IN_DOUT_B[61] !== 1'bz) && CAS_IN_DOUT_B_delay[61]; // rv 0
assign CAS_IN_DOUT_B_in[62] = (CAS_IN_DOUT_B[62] !== 1'bz) && CAS_IN_DOUT_B_delay[62]; // rv 0
assign CAS_IN_DOUT_B_in[63] = (CAS_IN_DOUT_B[63] !== 1'bz) && CAS_IN_DOUT_B_delay[63]; // rv 0
assign CAS_IN_DOUT_B_in[64] = (CAS_IN_DOUT_B[64] !== 1'bz) && CAS_IN_DOUT_B_delay[64]; // rv 0
assign CAS_IN_DOUT_B_in[65] = (CAS_IN_DOUT_B[65] !== 1'bz) && CAS_IN_DOUT_B_delay[65]; // rv 0
assign CAS_IN_DOUT_B_in[66] = (CAS_IN_DOUT_B[66] !== 1'bz) && CAS_IN_DOUT_B_delay[66]; // rv 0
assign CAS_IN_DOUT_B_in[67] = (CAS_IN_DOUT_B[67] !== 1'bz) && CAS_IN_DOUT_B_delay[67]; // rv 0
assign CAS_IN_DOUT_B_in[68] = (CAS_IN_DOUT_B[68] !== 1'bz) && CAS_IN_DOUT_B_delay[68]; // rv 0
assign CAS_IN_DOUT_B_in[69] = (CAS_IN_DOUT_B[69] !== 1'bz) && CAS_IN_DOUT_B_delay[69]; // rv 0
assign CAS_IN_DOUT_B_in[6] = (CAS_IN_DOUT_B[6] !== 1'bz) && CAS_IN_DOUT_B_delay[6]; // rv 0
assign CAS_IN_DOUT_B_in[70] = (CAS_IN_DOUT_B[70] !== 1'bz) && CAS_IN_DOUT_B_delay[70]; // rv 0
assign CAS_IN_DOUT_B_in[71] = (CAS_IN_DOUT_B[71] !== 1'bz) && CAS_IN_DOUT_B_delay[71]; // rv 0
assign CAS_IN_DOUT_B_in[7] = (CAS_IN_DOUT_B[7] !== 1'bz) && CAS_IN_DOUT_B_delay[7]; // rv 0
assign CAS_IN_DOUT_B_in[8] = (CAS_IN_DOUT_B[8] !== 1'bz) && CAS_IN_DOUT_B_delay[8]; // rv 0
assign CAS_IN_DOUT_B_in[9] = (CAS_IN_DOUT_B[9] !== 1'bz) && CAS_IN_DOUT_B_delay[9]; // rv 0
assign CAS_IN_EN_A_in = (CAS_IN_EN_A !== 1'bz) && CAS_IN_EN_A_delay; // rv 0
assign CAS_IN_EN_B_in = (CAS_IN_EN_B !== 1'bz) && CAS_IN_EN_B_delay; // rv 0
assign CAS_IN_RDACCESS_A_in = (CAS_IN_RDACCESS_A !== 1'bz) && CAS_IN_RDACCESS_A_delay; // rv 0
assign CAS_IN_RDACCESS_B_in = (CAS_IN_RDACCESS_B !== 1'bz) && CAS_IN_RDACCESS_B_delay; // rv 0
assign CAS_IN_RDB_WR_A_in = (CAS_IN_RDB_WR_A !== 1'bz) && CAS_IN_RDB_WR_A_delay; // rv 0
assign CAS_IN_RDB_WR_B_in = (CAS_IN_RDB_WR_B !== 1'bz) && CAS_IN_RDB_WR_B_delay; // rv 0
assign CAS_IN_SBITERR_A_in = (CAS_IN_SBITERR_A !== 1'bz) && CAS_IN_SBITERR_A_delay; // rv 0
assign CAS_IN_SBITERR_B_in = (CAS_IN_SBITERR_B !== 1'bz) && CAS_IN_SBITERR_B_delay; // rv 0
assign CLK_in = (CLK !== 1'bz) && (CLK_delay ^ IS_CLK_INVERTED_REG); // rv 0
assign DIN_A_in = DIN_A_delay;
assign DIN_B_in = DIN_B_delay;
assign EN_A_in = (EN_A !== 1'bz) && (EN_A_delay ^ IS_EN_A_INVERTED_REG); // rv 0
assign EN_B_in = (EN_B !== 1'bz) && (EN_B_delay ^ IS_EN_B_INVERTED_REG); // rv 0
assign INJECT_DBITERR_A_in = (INJECT_DBITERR_A !== 1'bz) && INJECT_DBITERR_A_delay; // rv 0
assign INJECT_DBITERR_B_in = (INJECT_DBITERR_B !== 1'bz) && INJECT_DBITERR_B_delay; // rv 0
assign INJECT_SBITERR_A_in = (INJECT_SBITERR_A !== 1'bz) && INJECT_SBITERR_A_delay; // rv 0
assign INJECT_SBITERR_B_in = (INJECT_SBITERR_B !== 1'bz) && INJECT_SBITERR_B_delay; // rv 0
assign OREG_CE_A_in = (OREG_CE_A === 1'bz) || OREG_CE_A_delay; // rv 1
assign OREG_CE_B_in = (OREG_CE_B === 1'bz) || OREG_CE_B_delay; // rv 1
assign OREG_ECC_CE_A_in = (OREG_ECC_CE_A === 1'bz) || OREG_ECC_CE_A_delay; // rv 1
assign OREG_ECC_CE_B_in = (OREG_ECC_CE_B === 1'bz) || OREG_ECC_CE_B_delay; // rv 1
assign RDB_WR_A_in = (RDB_WR_A !== 1'bz) && (RDB_WR_A_delay ^ IS_RDB_WR_A_INVERTED_REG); // rv 0
assign RDB_WR_B_in = (RDB_WR_B !== 1'bz) && (RDB_WR_B_delay ^ IS_RDB_WR_B_INVERTED_REG); // rv 0
assign RST_A_in = (RST_A !== 1'bz) && (RST_A_delay ^ IS_RST_A_INVERTED_REG); // rv 0
assign RST_B_in = (RST_B !== 1'bz) && (RST_B_delay ^ IS_RST_B_INVERTED_REG); // rv 0
assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP_delay; // rv 0
`else
assign ADDR_A_in = ADDR_A;
assign ADDR_B_in = ADDR_B;
assign BWE_A_in[0] = (BWE_A[0] === 1'bz) || BWE_A[0]; // rv 1
assign BWE_A_in[1] = (BWE_A[1] === 1'bz) || BWE_A[1]; // rv 1
assign BWE_A_in[2] = (BWE_A[2] === 1'bz) || BWE_A[2]; // rv 1
assign BWE_A_in[3] = (BWE_A[3] === 1'bz) || BWE_A[3]; // rv 1
assign BWE_A_in[4] = (BWE_A[4] === 1'bz) || BWE_A[4]; // rv 1
assign BWE_A_in[5] = (BWE_A[5] === 1'bz) || BWE_A[5]; // rv 1
assign BWE_A_in[6] = (BWE_A[6] === 1'bz) || BWE_A[6]; // rv 1
assign BWE_A_in[7] = (BWE_A[7] === 1'bz) || BWE_A[7]; // rv 1
assign BWE_A_in[8] = (BWE_A[8] === 1'bz) || BWE_A[8]; // rv 1
assign BWE_B_in[0] = (BWE_B[0] === 1'bz) || BWE_B[0]; // rv 1
assign BWE_B_in[1] = (BWE_B[1] === 1'bz) || BWE_B[1]; // rv 1
assign BWE_B_in[2] = (BWE_B[2] === 1'bz) || BWE_B[2]; // rv 1
assign BWE_B_in[3] = (BWE_B[3] === 1'bz) || BWE_B[3]; // rv 1
assign BWE_B_in[4] = (BWE_B[4] === 1'bz) || BWE_B[4]; // rv 1
assign BWE_B_in[5] = (BWE_B[5] === 1'bz) || BWE_B[5]; // rv 1
assign BWE_B_in[6] = (BWE_B[6] === 1'bz) || BWE_B[6]; // rv 1
assign BWE_B_in[7] = (BWE_B[7] === 1'bz) || BWE_B[7]; // rv 1
assign BWE_B_in[8] = (BWE_B[8] === 1'bz) || BWE_B[8]; // rv 1
assign CAS_IN_ADDR_A_in[0] = (CAS_IN_ADDR_A[0] !== 1'bz) && CAS_IN_ADDR_A[0]; // rv 0
assign CAS_IN_ADDR_A_in[10] = (CAS_IN_ADDR_A[10] !== 1'bz) && CAS_IN_ADDR_A[10]; // rv 0
assign CAS_IN_ADDR_A_in[11] = (CAS_IN_ADDR_A[11] !== 1'bz) && CAS_IN_ADDR_A[11]; // rv 0
assign CAS_IN_ADDR_A_in[12] = (CAS_IN_ADDR_A[12] !== 1'bz) && CAS_IN_ADDR_A[12]; // rv 0
assign CAS_IN_ADDR_A_in[13] = (CAS_IN_ADDR_A[13] !== 1'bz) && CAS_IN_ADDR_A[13]; // rv 0
assign CAS_IN_ADDR_A_in[14] = (CAS_IN_ADDR_A[14] !== 1'bz) && CAS_IN_ADDR_A[14]; // rv 0
assign CAS_IN_ADDR_A_in[15] = (CAS_IN_ADDR_A[15] !== 1'bz) && CAS_IN_ADDR_A[15]; // rv 0
assign CAS_IN_ADDR_A_in[16] = (CAS_IN_ADDR_A[16] !== 1'bz) && CAS_IN_ADDR_A[16]; // rv 0
assign CAS_IN_ADDR_A_in[17] = (CAS_IN_ADDR_A[17] !== 1'bz) && CAS_IN_ADDR_A[17]; // rv 0
assign CAS_IN_ADDR_A_in[18] = (CAS_IN_ADDR_A[18] !== 1'bz) && CAS_IN_ADDR_A[18]; // rv 0
assign CAS_IN_ADDR_A_in[19] = (CAS_IN_ADDR_A[19] !== 1'bz) && CAS_IN_ADDR_A[19]; // rv 0
assign CAS_IN_ADDR_A_in[1] = (CAS_IN_ADDR_A[1] !== 1'bz) && CAS_IN_ADDR_A[1]; // rv 0
assign CAS_IN_ADDR_A_in[20] = (CAS_IN_ADDR_A[20] !== 1'bz) && CAS_IN_ADDR_A[20]; // rv 0
assign CAS_IN_ADDR_A_in[21] = (CAS_IN_ADDR_A[21] !== 1'bz) && CAS_IN_ADDR_A[21]; // rv 0
assign CAS_IN_ADDR_A_in[22] = (CAS_IN_ADDR_A[22] !== 1'bz) && CAS_IN_ADDR_A[22]; // rv 0
assign CAS_IN_ADDR_A_in[2] = (CAS_IN_ADDR_A[2] !== 1'bz) && CAS_IN_ADDR_A[2]; // rv 0
assign CAS_IN_ADDR_A_in[3] = (CAS_IN_ADDR_A[3] !== 1'bz) && CAS_IN_ADDR_A[3]; // rv 0
assign CAS_IN_ADDR_A_in[4] = (CAS_IN_ADDR_A[4] !== 1'bz) && CAS_IN_ADDR_A[4]; // rv 0
assign CAS_IN_ADDR_A_in[5] = (CAS_IN_ADDR_A[5] !== 1'bz) && CAS_IN_ADDR_A[5]; // rv 0
assign CAS_IN_ADDR_A_in[6] = (CAS_IN_ADDR_A[6] !== 1'bz) && CAS_IN_ADDR_A[6]; // rv 0
assign CAS_IN_ADDR_A_in[7] = (CAS_IN_ADDR_A[7] !== 1'bz) && CAS_IN_ADDR_A[7]; // rv 0
assign CAS_IN_ADDR_A_in[8] = (CAS_IN_ADDR_A[8] !== 1'bz) && CAS_IN_ADDR_A[8]; // rv 0
assign CAS_IN_ADDR_A_in[9] = (CAS_IN_ADDR_A[9] !== 1'bz) && CAS_IN_ADDR_A[9]; // rv 0
assign CAS_IN_ADDR_B_in[0] = (CAS_IN_ADDR_B[0] !== 1'bz) && CAS_IN_ADDR_B[0]; // rv 0
assign CAS_IN_ADDR_B_in[10] = (CAS_IN_ADDR_B[10] !== 1'bz) && CAS_IN_ADDR_B[10]; // rv 0
assign CAS_IN_ADDR_B_in[11] = (CAS_IN_ADDR_B[11] !== 1'bz) && CAS_IN_ADDR_B[11]; // rv 0
assign CAS_IN_ADDR_B_in[12] = (CAS_IN_ADDR_B[12] !== 1'bz) && CAS_IN_ADDR_B[12]; // rv 0
assign CAS_IN_ADDR_B_in[13] = (CAS_IN_ADDR_B[13] !== 1'bz) && CAS_IN_ADDR_B[13]; // rv 0
assign CAS_IN_ADDR_B_in[14] = (CAS_IN_ADDR_B[14] !== 1'bz) && CAS_IN_ADDR_B[14]; // rv 0
assign CAS_IN_ADDR_B_in[15] = (CAS_IN_ADDR_B[15] !== 1'bz) && CAS_IN_ADDR_B[15]; // rv 0
assign CAS_IN_ADDR_B_in[16] = (CAS_IN_ADDR_B[16] !== 1'bz) && CAS_IN_ADDR_B[16]; // rv 0
assign CAS_IN_ADDR_B_in[17] = (CAS_IN_ADDR_B[17] !== 1'bz) && CAS_IN_ADDR_B[17]; // rv 0
assign CAS_IN_ADDR_B_in[18] = (CAS_IN_ADDR_B[18] !== 1'bz) && CAS_IN_ADDR_B[18]; // rv 0
assign CAS_IN_ADDR_B_in[19] = (CAS_IN_ADDR_B[19] !== 1'bz) && CAS_IN_ADDR_B[19]; // rv 0
assign CAS_IN_ADDR_B_in[1] = (CAS_IN_ADDR_B[1] !== 1'bz) && CAS_IN_ADDR_B[1]; // rv 0
assign CAS_IN_ADDR_B_in[20] = (CAS_IN_ADDR_B[20] !== 1'bz) && CAS_IN_ADDR_B[20]; // rv 0
assign CAS_IN_ADDR_B_in[21] = (CAS_IN_ADDR_B[21] !== 1'bz) && CAS_IN_ADDR_B[21]; // rv 0
assign CAS_IN_ADDR_B_in[22] = (CAS_IN_ADDR_B[22] !== 1'bz) && CAS_IN_ADDR_B[22]; // rv 0
assign CAS_IN_ADDR_B_in[2] = (CAS_IN_ADDR_B[2] !== 1'bz) && CAS_IN_ADDR_B[2]; // rv 0
assign CAS_IN_ADDR_B_in[3] = (CAS_IN_ADDR_B[3] !== 1'bz) && CAS_IN_ADDR_B[3]; // rv 0
assign CAS_IN_ADDR_B_in[4] = (CAS_IN_ADDR_B[4] !== 1'bz) && CAS_IN_ADDR_B[4]; // rv 0
assign CAS_IN_ADDR_B_in[5] = (CAS_IN_ADDR_B[5] !== 1'bz) && CAS_IN_ADDR_B[5]; // rv 0
assign CAS_IN_ADDR_B_in[6] = (CAS_IN_ADDR_B[6] !== 1'bz) && CAS_IN_ADDR_B[6]; // rv 0
assign CAS_IN_ADDR_B_in[7] = (CAS_IN_ADDR_B[7] !== 1'bz) && CAS_IN_ADDR_B[7]; // rv 0
assign CAS_IN_ADDR_B_in[8] = (CAS_IN_ADDR_B[8] !== 1'bz) && CAS_IN_ADDR_B[8]; // rv 0
assign CAS_IN_ADDR_B_in[9] = (CAS_IN_ADDR_B[9] !== 1'bz) && CAS_IN_ADDR_B[9]; // rv 0
assign CAS_IN_BWE_A_in[0] = (CAS_IN_BWE_A[0] !== 1'bz) && CAS_IN_BWE_A[0]; // rv 0
assign CAS_IN_BWE_A_in[1] = (CAS_IN_BWE_A[1] !== 1'bz) && CAS_IN_BWE_A[1]; // rv 0
assign CAS_IN_BWE_A_in[2] = (CAS_IN_BWE_A[2] !== 1'bz) && CAS_IN_BWE_A[2]; // rv 0
assign CAS_IN_BWE_A_in[3] = (CAS_IN_BWE_A[3] !== 1'bz) && CAS_IN_BWE_A[3]; // rv 0
assign CAS_IN_BWE_A_in[4] = (CAS_IN_BWE_A[4] !== 1'bz) && CAS_IN_BWE_A[4]; // rv 0
assign CAS_IN_BWE_A_in[5] = (CAS_IN_BWE_A[5] !== 1'bz) && CAS_IN_BWE_A[5]; // rv 0
assign CAS_IN_BWE_A_in[6] = (CAS_IN_BWE_A[6] !== 1'bz) && CAS_IN_BWE_A[6]; // rv 0
assign CAS_IN_BWE_A_in[7] = (CAS_IN_BWE_A[7] !== 1'bz) && CAS_IN_BWE_A[7]; // rv 0
assign CAS_IN_BWE_A_in[8] = (CAS_IN_BWE_A[8] !== 1'bz) && CAS_IN_BWE_A[8]; // rv 0
assign CAS_IN_BWE_B_in[0] = (CAS_IN_BWE_B[0] !== 1'bz) && CAS_IN_BWE_B[0]; // rv 0
assign CAS_IN_BWE_B_in[1] = (CAS_IN_BWE_B[1] !== 1'bz) && CAS_IN_BWE_B[1]; // rv 0
assign CAS_IN_BWE_B_in[2] = (CAS_IN_BWE_B[2] !== 1'bz) && CAS_IN_BWE_B[2]; // rv 0
assign CAS_IN_BWE_B_in[3] = (CAS_IN_BWE_B[3] !== 1'bz) && CAS_IN_BWE_B[3]; // rv 0
assign CAS_IN_BWE_B_in[4] = (CAS_IN_BWE_B[4] !== 1'bz) && CAS_IN_BWE_B[4]; // rv 0
assign CAS_IN_BWE_B_in[5] = (CAS_IN_BWE_B[5] !== 1'bz) && CAS_IN_BWE_B[5]; // rv 0
assign CAS_IN_BWE_B_in[6] = (CAS_IN_BWE_B[6] !== 1'bz) && CAS_IN_BWE_B[6]; // rv 0
assign CAS_IN_BWE_B_in[7] = (CAS_IN_BWE_B[7] !== 1'bz) && CAS_IN_BWE_B[7]; // rv 0
assign CAS_IN_BWE_B_in[8] = (CAS_IN_BWE_B[8] !== 1'bz) && CAS_IN_BWE_B[8]; // rv 0
assign CAS_IN_DBITERR_A_in = (CAS_IN_DBITERR_A !== 1'bz) && CAS_IN_DBITERR_A; // rv 0
assign CAS_IN_DBITERR_B_in = (CAS_IN_DBITERR_B !== 1'bz) && CAS_IN_DBITERR_B; // rv 0
assign CAS_IN_DIN_A_in[0] = (CAS_IN_DIN_A[0] !== 1'bz) && CAS_IN_DIN_A[0]; // rv 0
assign CAS_IN_DIN_A_in[10] = (CAS_IN_DIN_A[10] !== 1'bz) && CAS_IN_DIN_A[10]; // rv 0
assign CAS_IN_DIN_A_in[11] = (CAS_IN_DIN_A[11] !== 1'bz) && CAS_IN_DIN_A[11]; // rv 0
assign CAS_IN_DIN_A_in[12] = (CAS_IN_DIN_A[12] !== 1'bz) && CAS_IN_DIN_A[12]; // rv 0
assign CAS_IN_DIN_A_in[13] = (CAS_IN_DIN_A[13] !== 1'bz) && CAS_IN_DIN_A[13]; // rv 0
assign CAS_IN_DIN_A_in[14] = (CAS_IN_DIN_A[14] !== 1'bz) && CAS_IN_DIN_A[14]; // rv 0
assign CAS_IN_DIN_A_in[15] = (CAS_IN_DIN_A[15] !== 1'bz) && CAS_IN_DIN_A[15]; // rv 0
assign CAS_IN_DIN_A_in[16] = (CAS_IN_DIN_A[16] !== 1'bz) && CAS_IN_DIN_A[16]; // rv 0
assign CAS_IN_DIN_A_in[17] = (CAS_IN_DIN_A[17] !== 1'bz) && CAS_IN_DIN_A[17]; // rv 0
assign CAS_IN_DIN_A_in[18] = (CAS_IN_DIN_A[18] !== 1'bz) && CAS_IN_DIN_A[18]; // rv 0
assign CAS_IN_DIN_A_in[19] = (CAS_IN_DIN_A[19] !== 1'bz) && CAS_IN_DIN_A[19]; // rv 0
assign CAS_IN_DIN_A_in[1] = (CAS_IN_DIN_A[1] !== 1'bz) && CAS_IN_DIN_A[1]; // rv 0
assign CAS_IN_DIN_A_in[20] = (CAS_IN_DIN_A[20] !== 1'bz) && CAS_IN_DIN_A[20]; // rv 0
assign CAS_IN_DIN_A_in[21] = (CAS_IN_DIN_A[21] !== 1'bz) && CAS_IN_DIN_A[21]; // rv 0
assign CAS_IN_DIN_A_in[22] = (CAS_IN_DIN_A[22] !== 1'bz) && CAS_IN_DIN_A[22]; // rv 0
assign CAS_IN_DIN_A_in[23] = (CAS_IN_DIN_A[23] !== 1'bz) && CAS_IN_DIN_A[23]; // rv 0
assign CAS_IN_DIN_A_in[24] = (CAS_IN_DIN_A[24] !== 1'bz) && CAS_IN_DIN_A[24]; // rv 0
assign CAS_IN_DIN_A_in[25] = (CAS_IN_DIN_A[25] !== 1'bz) && CAS_IN_DIN_A[25]; // rv 0
assign CAS_IN_DIN_A_in[26] = (CAS_IN_DIN_A[26] !== 1'bz) && CAS_IN_DIN_A[26]; // rv 0
assign CAS_IN_DIN_A_in[27] = (CAS_IN_DIN_A[27] !== 1'bz) && CAS_IN_DIN_A[27]; // rv 0
assign CAS_IN_DIN_A_in[28] = (CAS_IN_DIN_A[28] !== 1'bz) && CAS_IN_DIN_A[28]; // rv 0
assign CAS_IN_DIN_A_in[29] = (CAS_IN_DIN_A[29] !== 1'bz) && CAS_IN_DIN_A[29]; // rv 0
assign CAS_IN_DIN_A_in[2] = (CAS_IN_DIN_A[2] !== 1'bz) && CAS_IN_DIN_A[2]; // rv 0
assign CAS_IN_DIN_A_in[30] = (CAS_IN_DIN_A[30] !== 1'bz) && CAS_IN_DIN_A[30]; // rv 0
assign CAS_IN_DIN_A_in[31] = (CAS_IN_DIN_A[31] !== 1'bz) && CAS_IN_DIN_A[31]; // rv 0
assign CAS_IN_DIN_A_in[32] = (CAS_IN_DIN_A[32] !== 1'bz) && CAS_IN_DIN_A[32]; // rv 0
assign CAS_IN_DIN_A_in[33] = (CAS_IN_DIN_A[33] !== 1'bz) && CAS_IN_DIN_A[33]; // rv 0
assign CAS_IN_DIN_A_in[34] = (CAS_IN_DIN_A[34] !== 1'bz) && CAS_IN_DIN_A[34]; // rv 0
assign CAS_IN_DIN_A_in[35] = (CAS_IN_DIN_A[35] !== 1'bz) && CAS_IN_DIN_A[35]; // rv 0
assign CAS_IN_DIN_A_in[36] = (CAS_IN_DIN_A[36] !== 1'bz) && CAS_IN_DIN_A[36]; // rv 0
assign CAS_IN_DIN_A_in[37] = (CAS_IN_DIN_A[37] !== 1'bz) && CAS_IN_DIN_A[37]; // rv 0
assign CAS_IN_DIN_A_in[38] = (CAS_IN_DIN_A[38] !== 1'bz) && CAS_IN_DIN_A[38]; // rv 0
assign CAS_IN_DIN_A_in[39] = (CAS_IN_DIN_A[39] !== 1'bz) && CAS_IN_DIN_A[39]; // rv 0
assign CAS_IN_DIN_A_in[3] = (CAS_IN_DIN_A[3] !== 1'bz) && CAS_IN_DIN_A[3]; // rv 0
assign CAS_IN_DIN_A_in[40] = (CAS_IN_DIN_A[40] !== 1'bz) && CAS_IN_DIN_A[40]; // rv 0
assign CAS_IN_DIN_A_in[41] = (CAS_IN_DIN_A[41] !== 1'bz) && CAS_IN_DIN_A[41]; // rv 0
assign CAS_IN_DIN_A_in[42] = (CAS_IN_DIN_A[42] !== 1'bz) && CAS_IN_DIN_A[42]; // rv 0
assign CAS_IN_DIN_A_in[43] = (CAS_IN_DIN_A[43] !== 1'bz) && CAS_IN_DIN_A[43]; // rv 0
assign CAS_IN_DIN_A_in[44] = (CAS_IN_DIN_A[44] !== 1'bz) && CAS_IN_DIN_A[44]; // rv 0
assign CAS_IN_DIN_A_in[45] = (CAS_IN_DIN_A[45] !== 1'bz) && CAS_IN_DIN_A[45]; // rv 0
assign CAS_IN_DIN_A_in[46] = (CAS_IN_DIN_A[46] !== 1'bz) && CAS_IN_DIN_A[46]; // rv 0
assign CAS_IN_DIN_A_in[47] = (CAS_IN_DIN_A[47] !== 1'bz) && CAS_IN_DIN_A[47]; // rv 0
assign CAS_IN_DIN_A_in[48] = (CAS_IN_DIN_A[48] !== 1'bz) && CAS_IN_DIN_A[48]; // rv 0
assign CAS_IN_DIN_A_in[49] = (CAS_IN_DIN_A[49] !== 1'bz) && CAS_IN_DIN_A[49]; // rv 0
assign CAS_IN_DIN_A_in[4] = (CAS_IN_DIN_A[4] !== 1'bz) && CAS_IN_DIN_A[4]; // rv 0
assign CAS_IN_DIN_A_in[50] = (CAS_IN_DIN_A[50] !== 1'bz) && CAS_IN_DIN_A[50]; // rv 0
assign CAS_IN_DIN_A_in[51] = (CAS_IN_DIN_A[51] !== 1'bz) && CAS_IN_DIN_A[51]; // rv 0
assign CAS_IN_DIN_A_in[52] = (CAS_IN_DIN_A[52] !== 1'bz) && CAS_IN_DIN_A[52]; // rv 0
assign CAS_IN_DIN_A_in[53] = (CAS_IN_DIN_A[53] !== 1'bz) && CAS_IN_DIN_A[53]; // rv 0
assign CAS_IN_DIN_A_in[54] = (CAS_IN_DIN_A[54] !== 1'bz) && CAS_IN_DIN_A[54]; // rv 0
assign CAS_IN_DIN_A_in[55] = (CAS_IN_DIN_A[55] !== 1'bz) && CAS_IN_DIN_A[55]; // rv 0
assign CAS_IN_DIN_A_in[56] = (CAS_IN_DIN_A[56] !== 1'bz) && CAS_IN_DIN_A[56]; // rv 0
assign CAS_IN_DIN_A_in[57] = (CAS_IN_DIN_A[57] !== 1'bz) && CAS_IN_DIN_A[57]; // rv 0
assign CAS_IN_DIN_A_in[58] = (CAS_IN_DIN_A[58] !== 1'bz) && CAS_IN_DIN_A[58]; // rv 0
assign CAS_IN_DIN_A_in[59] = (CAS_IN_DIN_A[59] !== 1'bz) && CAS_IN_DIN_A[59]; // rv 0
assign CAS_IN_DIN_A_in[5] = (CAS_IN_DIN_A[5] !== 1'bz) && CAS_IN_DIN_A[5]; // rv 0
assign CAS_IN_DIN_A_in[60] = (CAS_IN_DIN_A[60] !== 1'bz) && CAS_IN_DIN_A[60]; // rv 0
assign CAS_IN_DIN_A_in[61] = (CAS_IN_DIN_A[61] !== 1'bz) && CAS_IN_DIN_A[61]; // rv 0
assign CAS_IN_DIN_A_in[62] = (CAS_IN_DIN_A[62] !== 1'bz) && CAS_IN_DIN_A[62]; // rv 0
assign CAS_IN_DIN_A_in[63] = (CAS_IN_DIN_A[63] !== 1'bz) && CAS_IN_DIN_A[63]; // rv 0
assign CAS_IN_DIN_A_in[64] = (CAS_IN_DIN_A[64] !== 1'bz) && CAS_IN_DIN_A[64]; // rv 0
assign CAS_IN_DIN_A_in[65] = (CAS_IN_DIN_A[65] !== 1'bz) && CAS_IN_DIN_A[65]; // rv 0
assign CAS_IN_DIN_A_in[66] = (CAS_IN_DIN_A[66] !== 1'bz) && CAS_IN_DIN_A[66]; // rv 0
assign CAS_IN_DIN_A_in[67] = (CAS_IN_DIN_A[67] !== 1'bz) && CAS_IN_DIN_A[67]; // rv 0
assign CAS_IN_DIN_A_in[68] = (CAS_IN_DIN_A[68] !== 1'bz) && CAS_IN_DIN_A[68]; // rv 0
assign CAS_IN_DIN_A_in[69] = (CAS_IN_DIN_A[69] !== 1'bz) && CAS_IN_DIN_A[69]; // rv 0
assign CAS_IN_DIN_A_in[6] = (CAS_IN_DIN_A[6] !== 1'bz) && CAS_IN_DIN_A[6]; // rv 0
assign CAS_IN_DIN_A_in[70] = (CAS_IN_DIN_A[70] !== 1'bz) && CAS_IN_DIN_A[70]; // rv 0
assign CAS_IN_DIN_A_in[71] = (CAS_IN_DIN_A[71] !== 1'bz) && CAS_IN_DIN_A[71]; // rv 0
assign CAS_IN_DIN_A_in[7] = (CAS_IN_DIN_A[7] !== 1'bz) && CAS_IN_DIN_A[7]; // rv 0
assign CAS_IN_DIN_A_in[8] = (CAS_IN_DIN_A[8] !== 1'bz) && CAS_IN_DIN_A[8]; // rv 0
assign CAS_IN_DIN_A_in[9] = (CAS_IN_DIN_A[9] !== 1'bz) && CAS_IN_DIN_A[9]; // rv 0
assign CAS_IN_DIN_B_in[0] = (CAS_IN_DIN_B[0] !== 1'bz) && CAS_IN_DIN_B[0]; // rv 0
assign CAS_IN_DIN_B_in[10] = (CAS_IN_DIN_B[10] !== 1'bz) && CAS_IN_DIN_B[10]; // rv 0
assign CAS_IN_DIN_B_in[11] = (CAS_IN_DIN_B[11] !== 1'bz) && CAS_IN_DIN_B[11]; // rv 0
assign CAS_IN_DIN_B_in[12] = (CAS_IN_DIN_B[12] !== 1'bz) && CAS_IN_DIN_B[12]; // rv 0
assign CAS_IN_DIN_B_in[13] = (CAS_IN_DIN_B[13] !== 1'bz) && CAS_IN_DIN_B[13]; // rv 0
assign CAS_IN_DIN_B_in[14] = (CAS_IN_DIN_B[14] !== 1'bz) && CAS_IN_DIN_B[14]; // rv 0
assign CAS_IN_DIN_B_in[15] = (CAS_IN_DIN_B[15] !== 1'bz) && CAS_IN_DIN_B[15]; // rv 0
assign CAS_IN_DIN_B_in[16] = (CAS_IN_DIN_B[16] !== 1'bz) && CAS_IN_DIN_B[16]; // rv 0
assign CAS_IN_DIN_B_in[17] = (CAS_IN_DIN_B[17] !== 1'bz) && CAS_IN_DIN_B[17]; // rv 0
assign CAS_IN_DIN_B_in[18] = (CAS_IN_DIN_B[18] !== 1'bz) && CAS_IN_DIN_B[18]; // rv 0
assign CAS_IN_DIN_B_in[19] = (CAS_IN_DIN_B[19] !== 1'bz) && CAS_IN_DIN_B[19]; // rv 0
assign CAS_IN_DIN_B_in[1] = (CAS_IN_DIN_B[1] !== 1'bz) && CAS_IN_DIN_B[1]; // rv 0
assign CAS_IN_DIN_B_in[20] = (CAS_IN_DIN_B[20] !== 1'bz) && CAS_IN_DIN_B[20]; // rv 0
assign CAS_IN_DIN_B_in[21] = (CAS_IN_DIN_B[21] !== 1'bz) && CAS_IN_DIN_B[21]; // rv 0
assign CAS_IN_DIN_B_in[22] = (CAS_IN_DIN_B[22] !== 1'bz) && CAS_IN_DIN_B[22]; // rv 0
assign CAS_IN_DIN_B_in[23] = (CAS_IN_DIN_B[23] !== 1'bz) && CAS_IN_DIN_B[23]; // rv 0
assign CAS_IN_DIN_B_in[24] = (CAS_IN_DIN_B[24] !== 1'bz) && CAS_IN_DIN_B[24]; // rv 0
assign CAS_IN_DIN_B_in[25] = (CAS_IN_DIN_B[25] !== 1'bz) && CAS_IN_DIN_B[25]; // rv 0
assign CAS_IN_DIN_B_in[26] = (CAS_IN_DIN_B[26] !== 1'bz) && CAS_IN_DIN_B[26]; // rv 0
assign CAS_IN_DIN_B_in[27] = (CAS_IN_DIN_B[27] !== 1'bz) && CAS_IN_DIN_B[27]; // rv 0
assign CAS_IN_DIN_B_in[28] = (CAS_IN_DIN_B[28] !== 1'bz) && CAS_IN_DIN_B[28]; // rv 0
assign CAS_IN_DIN_B_in[29] = (CAS_IN_DIN_B[29] !== 1'bz) && CAS_IN_DIN_B[29]; // rv 0
assign CAS_IN_DIN_B_in[2] = (CAS_IN_DIN_B[2] !== 1'bz) && CAS_IN_DIN_B[2]; // rv 0
assign CAS_IN_DIN_B_in[30] = (CAS_IN_DIN_B[30] !== 1'bz) && CAS_IN_DIN_B[30]; // rv 0
assign CAS_IN_DIN_B_in[31] = (CAS_IN_DIN_B[31] !== 1'bz) && CAS_IN_DIN_B[31]; // rv 0
assign CAS_IN_DIN_B_in[32] = (CAS_IN_DIN_B[32] !== 1'bz) && CAS_IN_DIN_B[32]; // rv 0
assign CAS_IN_DIN_B_in[33] = (CAS_IN_DIN_B[33] !== 1'bz) && CAS_IN_DIN_B[33]; // rv 0
assign CAS_IN_DIN_B_in[34] = (CAS_IN_DIN_B[34] !== 1'bz) && CAS_IN_DIN_B[34]; // rv 0
assign CAS_IN_DIN_B_in[35] = (CAS_IN_DIN_B[35] !== 1'bz) && CAS_IN_DIN_B[35]; // rv 0
assign CAS_IN_DIN_B_in[36] = (CAS_IN_DIN_B[36] !== 1'bz) && CAS_IN_DIN_B[36]; // rv 0
assign CAS_IN_DIN_B_in[37] = (CAS_IN_DIN_B[37] !== 1'bz) && CAS_IN_DIN_B[37]; // rv 0
assign CAS_IN_DIN_B_in[38] = (CAS_IN_DIN_B[38] !== 1'bz) && CAS_IN_DIN_B[38]; // rv 0
assign CAS_IN_DIN_B_in[39] = (CAS_IN_DIN_B[39] !== 1'bz) && CAS_IN_DIN_B[39]; // rv 0
assign CAS_IN_DIN_B_in[3] = (CAS_IN_DIN_B[3] !== 1'bz) && CAS_IN_DIN_B[3]; // rv 0
assign CAS_IN_DIN_B_in[40] = (CAS_IN_DIN_B[40] !== 1'bz) && CAS_IN_DIN_B[40]; // rv 0
assign CAS_IN_DIN_B_in[41] = (CAS_IN_DIN_B[41] !== 1'bz) && CAS_IN_DIN_B[41]; // rv 0
assign CAS_IN_DIN_B_in[42] = (CAS_IN_DIN_B[42] !== 1'bz) && CAS_IN_DIN_B[42]; // rv 0
assign CAS_IN_DIN_B_in[43] = (CAS_IN_DIN_B[43] !== 1'bz) && CAS_IN_DIN_B[43]; // rv 0
assign CAS_IN_DIN_B_in[44] = (CAS_IN_DIN_B[44] !== 1'bz) && CAS_IN_DIN_B[44]; // rv 0
assign CAS_IN_DIN_B_in[45] = (CAS_IN_DIN_B[45] !== 1'bz) && CAS_IN_DIN_B[45]; // rv 0
assign CAS_IN_DIN_B_in[46] = (CAS_IN_DIN_B[46] !== 1'bz) && CAS_IN_DIN_B[46]; // rv 0
assign CAS_IN_DIN_B_in[47] = (CAS_IN_DIN_B[47] !== 1'bz) && CAS_IN_DIN_B[47]; // rv 0
assign CAS_IN_DIN_B_in[48] = (CAS_IN_DIN_B[48] !== 1'bz) && CAS_IN_DIN_B[48]; // rv 0
assign CAS_IN_DIN_B_in[49] = (CAS_IN_DIN_B[49] !== 1'bz) && CAS_IN_DIN_B[49]; // rv 0
assign CAS_IN_DIN_B_in[4] = (CAS_IN_DIN_B[4] !== 1'bz) && CAS_IN_DIN_B[4]; // rv 0
assign CAS_IN_DIN_B_in[50] = (CAS_IN_DIN_B[50] !== 1'bz) && CAS_IN_DIN_B[50]; // rv 0
assign CAS_IN_DIN_B_in[51] = (CAS_IN_DIN_B[51] !== 1'bz) && CAS_IN_DIN_B[51]; // rv 0
assign CAS_IN_DIN_B_in[52] = (CAS_IN_DIN_B[52] !== 1'bz) && CAS_IN_DIN_B[52]; // rv 0
assign CAS_IN_DIN_B_in[53] = (CAS_IN_DIN_B[53] !== 1'bz) && CAS_IN_DIN_B[53]; // rv 0
assign CAS_IN_DIN_B_in[54] = (CAS_IN_DIN_B[54] !== 1'bz) && CAS_IN_DIN_B[54]; // rv 0
assign CAS_IN_DIN_B_in[55] = (CAS_IN_DIN_B[55] !== 1'bz) && CAS_IN_DIN_B[55]; // rv 0
assign CAS_IN_DIN_B_in[56] = (CAS_IN_DIN_B[56] !== 1'bz) && CAS_IN_DIN_B[56]; // rv 0
assign CAS_IN_DIN_B_in[57] = (CAS_IN_DIN_B[57] !== 1'bz) && CAS_IN_DIN_B[57]; // rv 0
assign CAS_IN_DIN_B_in[58] = (CAS_IN_DIN_B[58] !== 1'bz) && CAS_IN_DIN_B[58]; // rv 0
assign CAS_IN_DIN_B_in[59] = (CAS_IN_DIN_B[59] !== 1'bz) && CAS_IN_DIN_B[59]; // rv 0
assign CAS_IN_DIN_B_in[5] = (CAS_IN_DIN_B[5] !== 1'bz) && CAS_IN_DIN_B[5]; // rv 0
assign CAS_IN_DIN_B_in[60] = (CAS_IN_DIN_B[60] !== 1'bz) && CAS_IN_DIN_B[60]; // rv 0
assign CAS_IN_DIN_B_in[61] = (CAS_IN_DIN_B[61] !== 1'bz) && CAS_IN_DIN_B[61]; // rv 0
assign CAS_IN_DIN_B_in[62] = (CAS_IN_DIN_B[62] !== 1'bz) && CAS_IN_DIN_B[62]; // rv 0
assign CAS_IN_DIN_B_in[63] = (CAS_IN_DIN_B[63] !== 1'bz) && CAS_IN_DIN_B[63]; // rv 0
assign CAS_IN_DIN_B_in[64] = (CAS_IN_DIN_B[64] !== 1'bz) && CAS_IN_DIN_B[64]; // rv 0
assign CAS_IN_DIN_B_in[65] = (CAS_IN_DIN_B[65] !== 1'bz) && CAS_IN_DIN_B[65]; // rv 0
assign CAS_IN_DIN_B_in[66] = (CAS_IN_DIN_B[66] !== 1'bz) && CAS_IN_DIN_B[66]; // rv 0
assign CAS_IN_DIN_B_in[67] = (CAS_IN_DIN_B[67] !== 1'bz) && CAS_IN_DIN_B[67]; // rv 0
assign CAS_IN_DIN_B_in[68] = (CAS_IN_DIN_B[68] !== 1'bz) && CAS_IN_DIN_B[68]; // rv 0
assign CAS_IN_DIN_B_in[69] = (CAS_IN_DIN_B[69] !== 1'bz) && CAS_IN_DIN_B[69]; // rv 0
assign CAS_IN_DIN_B_in[6] = (CAS_IN_DIN_B[6] !== 1'bz) && CAS_IN_DIN_B[6]; // rv 0
assign CAS_IN_DIN_B_in[70] = (CAS_IN_DIN_B[70] !== 1'bz) && CAS_IN_DIN_B[70]; // rv 0
assign CAS_IN_DIN_B_in[71] = (CAS_IN_DIN_B[71] !== 1'bz) && CAS_IN_DIN_B[71]; // rv 0
assign CAS_IN_DIN_B_in[7] = (CAS_IN_DIN_B[7] !== 1'bz) && CAS_IN_DIN_B[7]; // rv 0
assign CAS_IN_DIN_B_in[8] = (CAS_IN_DIN_B[8] !== 1'bz) && CAS_IN_DIN_B[8]; // rv 0
assign CAS_IN_DIN_B_in[9] = (CAS_IN_DIN_B[9] !== 1'bz) && CAS_IN_DIN_B[9]; // rv 0
assign CAS_IN_DOUT_A_in[0] = (CAS_IN_DOUT_A[0] !== 1'bz) && CAS_IN_DOUT_A[0]; // rv 0
assign CAS_IN_DOUT_A_in[10] = (CAS_IN_DOUT_A[10] !== 1'bz) && CAS_IN_DOUT_A[10]; // rv 0
assign CAS_IN_DOUT_A_in[11] = (CAS_IN_DOUT_A[11] !== 1'bz) && CAS_IN_DOUT_A[11]; // rv 0
assign CAS_IN_DOUT_A_in[12] = (CAS_IN_DOUT_A[12] !== 1'bz) && CAS_IN_DOUT_A[12]; // rv 0
assign CAS_IN_DOUT_A_in[13] = (CAS_IN_DOUT_A[13] !== 1'bz) && CAS_IN_DOUT_A[13]; // rv 0
assign CAS_IN_DOUT_A_in[14] = (CAS_IN_DOUT_A[14] !== 1'bz) && CAS_IN_DOUT_A[14]; // rv 0
assign CAS_IN_DOUT_A_in[15] = (CAS_IN_DOUT_A[15] !== 1'bz) && CAS_IN_DOUT_A[15]; // rv 0
assign CAS_IN_DOUT_A_in[16] = (CAS_IN_DOUT_A[16] !== 1'bz) && CAS_IN_DOUT_A[16]; // rv 0
assign CAS_IN_DOUT_A_in[17] = (CAS_IN_DOUT_A[17] !== 1'bz) && CAS_IN_DOUT_A[17]; // rv 0
assign CAS_IN_DOUT_A_in[18] = (CAS_IN_DOUT_A[18] !== 1'bz) && CAS_IN_DOUT_A[18]; // rv 0
assign CAS_IN_DOUT_A_in[19] = (CAS_IN_DOUT_A[19] !== 1'bz) && CAS_IN_DOUT_A[19]; // rv 0
assign CAS_IN_DOUT_A_in[1] = (CAS_IN_DOUT_A[1] !== 1'bz) && CAS_IN_DOUT_A[1]; // rv 0
assign CAS_IN_DOUT_A_in[20] = (CAS_IN_DOUT_A[20] !== 1'bz) && CAS_IN_DOUT_A[20]; // rv 0
assign CAS_IN_DOUT_A_in[21] = (CAS_IN_DOUT_A[21] !== 1'bz) && CAS_IN_DOUT_A[21]; // rv 0
assign CAS_IN_DOUT_A_in[22] = (CAS_IN_DOUT_A[22] !== 1'bz) && CAS_IN_DOUT_A[22]; // rv 0
assign CAS_IN_DOUT_A_in[23] = (CAS_IN_DOUT_A[23] !== 1'bz) && CAS_IN_DOUT_A[23]; // rv 0
assign CAS_IN_DOUT_A_in[24] = (CAS_IN_DOUT_A[24] !== 1'bz) && CAS_IN_DOUT_A[24]; // rv 0
assign CAS_IN_DOUT_A_in[25] = (CAS_IN_DOUT_A[25] !== 1'bz) && CAS_IN_DOUT_A[25]; // rv 0
assign CAS_IN_DOUT_A_in[26] = (CAS_IN_DOUT_A[26] !== 1'bz) && CAS_IN_DOUT_A[26]; // rv 0
assign CAS_IN_DOUT_A_in[27] = (CAS_IN_DOUT_A[27] !== 1'bz) && CAS_IN_DOUT_A[27]; // rv 0
assign CAS_IN_DOUT_A_in[28] = (CAS_IN_DOUT_A[28] !== 1'bz) && CAS_IN_DOUT_A[28]; // rv 0
assign CAS_IN_DOUT_A_in[29] = (CAS_IN_DOUT_A[29] !== 1'bz) && CAS_IN_DOUT_A[29]; // rv 0
assign CAS_IN_DOUT_A_in[2] = (CAS_IN_DOUT_A[2] !== 1'bz) && CAS_IN_DOUT_A[2]; // rv 0
assign CAS_IN_DOUT_A_in[30] = (CAS_IN_DOUT_A[30] !== 1'bz) && CAS_IN_DOUT_A[30]; // rv 0
assign CAS_IN_DOUT_A_in[31] = (CAS_IN_DOUT_A[31] !== 1'bz) && CAS_IN_DOUT_A[31]; // rv 0
assign CAS_IN_DOUT_A_in[32] = (CAS_IN_DOUT_A[32] !== 1'bz) && CAS_IN_DOUT_A[32]; // rv 0
assign CAS_IN_DOUT_A_in[33] = (CAS_IN_DOUT_A[33] !== 1'bz) && CAS_IN_DOUT_A[33]; // rv 0
assign CAS_IN_DOUT_A_in[34] = (CAS_IN_DOUT_A[34] !== 1'bz) && CAS_IN_DOUT_A[34]; // rv 0
assign CAS_IN_DOUT_A_in[35] = (CAS_IN_DOUT_A[35] !== 1'bz) && CAS_IN_DOUT_A[35]; // rv 0
assign CAS_IN_DOUT_A_in[36] = (CAS_IN_DOUT_A[36] !== 1'bz) && CAS_IN_DOUT_A[36]; // rv 0
assign CAS_IN_DOUT_A_in[37] = (CAS_IN_DOUT_A[37] !== 1'bz) && CAS_IN_DOUT_A[37]; // rv 0
assign CAS_IN_DOUT_A_in[38] = (CAS_IN_DOUT_A[38] !== 1'bz) && CAS_IN_DOUT_A[38]; // rv 0
assign CAS_IN_DOUT_A_in[39] = (CAS_IN_DOUT_A[39] !== 1'bz) && CAS_IN_DOUT_A[39]; // rv 0
assign CAS_IN_DOUT_A_in[3] = (CAS_IN_DOUT_A[3] !== 1'bz) && CAS_IN_DOUT_A[3]; // rv 0
assign CAS_IN_DOUT_A_in[40] = (CAS_IN_DOUT_A[40] !== 1'bz) && CAS_IN_DOUT_A[40]; // rv 0
assign CAS_IN_DOUT_A_in[41] = (CAS_IN_DOUT_A[41] !== 1'bz) && CAS_IN_DOUT_A[41]; // rv 0
assign CAS_IN_DOUT_A_in[42] = (CAS_IN_DOUT_A[42] !== 1'bz) && CAS_IN_DOUT_A[42]; // rv 0
assign CAS_IN_DOUT_A_in[43] = (CAS_IN_DOUT_A[43] !== 1'bz) && CAS_IN_DOUT_A[43]; // rv 0
assign CAS_IN_DOUT_A_in[44] = (CAS_IN_DOUT_A[44] !== 1'bz) && CAS_IN_DOUT_A[44]; // rv 0
assign CAS_IN_DOUT_A_in[45] = (CAS_IN_DOUT_A[45] !== 1'bz) && CAS_IN_DOUT_A[45]; // rv 0
assign CAS_IN_DOUT_A_in[46] = (CAS_IN_DOUT_A[46] !== 1'bz) && CAS_IN_DOUT_A[46]; // rv 0
assign CAS_IN_DOUT_A_in[47] = (CAS_IN_DOUT_A[47] !== 1'bz) && CAS_IN_DOUT_A[47]; // rv 0
assign CAS_IN_DOUT_A_in[48] = (CAS_IN_DOUT_A[48] !== 1'bz) && CAS_IN_DOUT_A[48]; // rv 0
assign CAS_IN_DOUT_A_in[49] = (CAS_IN_DOUT_A[49] !== 1'bz) && CAS_IN_DOUT_A[49]; // rv 0
assign CAS_IN_DOUT_A_in[4] = (CAS_IN_DOUT_A[4] !== 1'bz) && CAS_IN_DOUT_A[4]; // rv 0
assign CAS_IN_DOUT_A_in[50] = (CAS_IN_DOUT_A[50] !== 1'bz) && CAS_IN_DOUT_A[50]; // rv 0
assign CAS_IN_DOUT_A_in[51] = (CAS_IN_DOUT_A[51] !== 1'bz) && CAS_IN_DOUT_A[51]; // rv 0
assign CAS_IN_DOUT_A_in[52] = (CAS_IN_DOUT_A[52] !== 1'bz) && CAS_IN_DOUT_A[52]; // rv 0
assign CAS_IN_DOUT_A_in[53] = (CAS_IN_DOUT_A[53] !== 1'bz) && CAS_IN_DOUT_A[53]; // rv 0
assign CAS_IN_DOUT_A_in[54] = (CAS_IN_DOUT_A[54] !== 1'bz) && CAS_IN_DOUT_A[54]; // rv 0
assign CAS_IN_DOUT_A_in[55] = (CAS_IN_DOUT_A[55] !== 1'bz) && CAS_IN_DOUT_A[55]; // rv 0
assign CAS_IN_DOUT_A_in[56] = (CAS_IN_DOUT_A[56] !== 1'bz) && CAS_IN_DOUT_A[56]; // rv 0
assign CAS_IN_DOUT_A_in[57] = (CAS_IN_DOUT_A[57] !== 1'bz) && CAS_IN_DOUT_A[57]; // rv 0
assign CAS_IN_DOUT_A_in[58] = (CAS_IN_DOUT_A[58] !== 1'bz) && CAS_IN_DOUT_A[58]; // rv 0
assign CAS_IN_DOUT_A_in[59] = (CAS_IN_DOUT_A[59] !== 1'bz) && CAS_IN_DOUT_A[59]; // rv 0
assign CAS_IN_DOUT_A_in[5] = (CAS_IN_DOUT_A[5] !== 1'bz) && CAS_IN_DOUT_A[5]; // rv 0
assign CAS_IN_DOUT_A_in[60] = (CAS_IN_DOUT_A[60] !== 1'bz) && CAS_IN_DOUT_A[60]; // rv 0
assign CAS_IN_DOUT_A_in[61] = (CAS_IN_DOUT_A[61] !== 1'bz) && CAS_IN_DOUT_A[61]; // rv 0
assign CAS_IN_DOUT_A_in[62] = (CAS_IN_DOUT_A[62] !== 1'bz) && CAS_IN_DOUT_A[62]; // rv 0
assign CAS_IN_DOUT_A_in[63] = (CAS_IN_DOUT_A[63] !== 1'bz) && CAS_IN_DOUT_A[63]; // rv 0
assign CAS_IN_DOUT_A_in[64] = (CAS_IN_DOUT_A[64] !== 1'bz) && CAS_IN_DOUT_A[64]; // rv 0
assign CAS_IN_DOUT_A_in[65] = (CAS_IN_DOUT_A[65] !== 1'bz) && CAS_IN_DOUT_A[65]; // rv 0
assign CAS_IN_DOUT_A_in[66] = (CAS_IN_DOUT_A[66] !== 1'bz) && CAS_IN_DOUT_A[66]; // rv 0
assign CAS_IN_DOUT_A_in[67] = (CAS_IN_DOUT_A[67] !== 1'bz) && CAS_IN_DOUT_A[67]; // rv 0
assign CAS_IN_DOUT_A_in[68] = (CAS_IN_DOUT_A[68] !== 1'bz) && CAS_IN_DOUT_A[68]; // rv 0
assign CAS_IN_DOUT_A_in[69] = (CAS_IN_DOUT_A[69] !== 1'bz) && CAS_IN_DOUT_A[69]; // rv 0
assign CAS_IN_DOUT_A_in[6] = (CAS_IN_DOUT_A[6] !== 1'bz) && CAS_IN_DOUT_A[6]; // rv 0
assign CAS_IN_DOUT_A_in[70] = (CAS_IN_DOUT_A[70] !== 1'bz) && CAS_IN_DOUT_A[70]; // rv 0
assign CAS_IN_DOUT_A_in[71] = (CAS_IN_DOUT_A[71] !== 1'bz) && CAS_IN_DOUT_A[71]; // rv 0
assign CAS_IN_DOUT_A_in[7] = (CAS_IN_DOUT_A[7] !== 1'bz) && CAS_IN_DOUT_A[7]; // rv 0
assign CAS_IN_DOUT_A_in[8] = (CAS_IN_DOUT_A[8] !== 1'bz) && CAS_IN_DOUT_A[8]; // rv 0
assign CAS_IN_DOUT_A_in[9] = (CAS_IN_DOUT_A[9] !== 1'bz) && CAS_IN_DOUT_A[9]; // rv 0
assign CAS_IN_DOUT_B_in[0] = (CAS_IN_DOUT_B[0] !== 1'bz) && CAS_IN_DOUT_B[0]; // rv 0
assign CAS_IN_DOUT_B_in[10] = (CAS_IN_DOUT_B[10] !== 1'bz) && CAS_IN_DOUT_B[10]; // rv 0
assign CAS_IN_DOUT_B_in[11] = (CAS_IN_DOUT_B[11] !== 1'bz) && CAS_IN_DOUT_B[11]; // rv 0
assign CAS_IN_DOUT_B_in[12] = (CAS_IN_DOUT_B[12] !== 1'bz) && CAS_IN_DOUT_B[12]; // rv 0
assign CAS_IN_DOUT_B_in[13] = (CAS_IN_DOUT_B[13] !== 1'bz) && CAS_IN_DOUT_B[13]; // rv 0
assign CAS_IN_DOUT_B_in[14] = (CAS_IN_DOUT_B[14] !== 1'bz) && CAS_IN_DOUT_B[14]; // rv 0
assign CAS_IN_DOUT_B_in[15] = (CAS_IN_DOUT_B[15] !== 1'bz) && CAS_IN_DOUT_B[15]; // rv 0
assign CAS_IN_DOUT_B_in[16] = (CAS_IN_DOUT_B[16] !== 1'bz) && CAS_IN_DOUT_B[16]; // rv 0
assign CAS_IN_DOUT_B_in[17] = (CAS_IN_DOUT_B[17] !== 1'bz) && CAS_IN_DOUT_B[17]; // rv 0
assign CAS_IN_DOUT_B_in[18] = (CAS_IN_DOUT_B[18] !== 1'bz) && CAS_IN_DOUT_B[18]; // rv 0
assign CAS_IN_DOUT_B_in[19] = (CAS_IN_DOUT_B[19] !== 1'bz) && CAS_IN_DOUT_B[19]; // rv 0
assign CAS_IN_DOUT_B_in[1] = (CAS_IN_DOUT_B[1] !== 1'bz) && CAS_IN_DOUT_B[1]; // rv 0
assign CAS_IN_DOUT_B_in[20] = (CAS_IN_DOUT_B[20] !== 1'bz) && CAS_IN_DOUT_B[20]; // rv 0
assign CAS_IN_DOUT_B_in[21] = (CAS_IN_DOUT_B[21] !== 1'bz) && CAS_IN_DOUT_B[21]; // rv 0
assign CAS_IN_DOUT_B_in[22] = (CAS_IN_DOUT_B[22] !== 1'bz) && CAS_IN_DOUT_B[22]; // rv 0
assign CAS_IN_DOUT_B_in[23] = (CAS_IN_DOUT_B[23] !== 1'bz) && CAS_IN_DOUT_B[23]; // rv 0
assign CAS_IN_DOUT_B_in[24] = (CAS_IN_DOUT_B[24] !== 1'bz) && CAS_IN_DOUT_B[24]; // rv 0
assign CAS_IN_DOUT_B_in[25] = (CAS_IN_DOUT_B[25] !== 1'bz) && CAS_IN_DOUT_B[25]; // rv 0
assign CAS_IN_DOUT_B_in[26] = (CAS_IN_DOUT_B[26] !== 1'bz) && CAS_IN_DOUT_B[26]; // rv 0
assign CAS_IN_DOUT_B_in[27] = (CAS_IN_DOUT_B[27] !== 1'bz) && CAS_IN_DOUT_B[27]; // rv 0
assign CAS_IN_DOUT_B_in[28] = (CAS_IN_DOUT_B[28] !== 1'bz) && CAS_IN_DOUT_B[28]; // rv 0
assign CAS_IN_DOUT_B_in[29] = (CAS_IN_DOUT_B[29] !== 1'bz) && CAS_IN_DOUT_B[29]; // rv 0
assign CAS_IN_DOUT_B_in[2] = (CAS_IN_DOUT_B[2] !== 1'bz) && CAS_IN_DOUT_B[2]; // rv 0
assign CAS_IN_DOUT_B_in[30] = (CAS_IN_DOUT_B[30] !== 1'bz) && CAS_IN_DOUT_B[30]; // rv 0
assign CAS_IN_DOUT_B_in[31] = (CAS_IN_DOUT_B[31] !== 1'bz) && CAS_IN_DOUT_B[31]; // rv 0
assign CAS_IN_DOUT_B_in[32] = (CAS_IN_DOUT_B[32] !== 1'bz) && CAS_IN_DOUT_B[32]; // rv 0
assign CAS_IN_DOUT_B_in[33] = (CAS_IN_DOUT_B[33] !== 1'bz) && CAS_IN_DOUT_B[33]; // rv 0
assign CAS_IN_DOUT_B_in[34] = (CAS_IN_DOUT_B[34] !== 1'bz) && CAS_IN_DOUT_B[34]; // rv 0
assign CAS_IN_DOUT_B_in[35] = (CAS_IN_DOUT_B[35] !== 1'bz) && CAS_IN_DOUT_B[35]; // rv 0
assign CAS_IN_DOUT_B_in[36] = (CAS_IN_DOUT_B[36] !== 1'bz) && CAS_IN_DOUT_B[36]; // rv 0
assign CAS_IN_DOUT_B_in[37] = (CAS_IN_DOUT_B[37] !== 1'bz) && CAS_IN_DOUT_B[37]; // rv 0
assign CAS_IN_DOUT_B_in[38] = (CAS_IN_DOUT_B[38] !== 1'bz) && CAS_IN_DOUT_B[38]; // rv 0
assign CAS_IN_DOUT_B_in[39] = (CAS_IN_DOUT_B[39] !== 1'bz) && CAS_IN_DOUT_B[39]; // rv 0
assign CAS_IN_DOUT_B_in[3] = (CAS_IN_DOUT_B[3] !== 1'bz) && CAS_IN_DOUT_B[3]; // rv 0
assign CAS_IN_DOUT_B_in[40] = (CAS_IN_DOUT_B[40] !== 1'bz) && CAS_IN_DOUT_B[40]; // rv 0
assign CAS_IN_DOUT_B_in[41] = (CAS_IN_DOUT_B[41] !== 1'bz) && CAS_IN_DOUT_B[41]; // rv 0
assign CAS_IN_DOUT_B_in[42] = (CAS_IN_DOUT_B[42] !== 1'bz) && CAS_IN_DOUT_B[42]; // rv 0
assign CAS_IN_DOUT_B_in[43] = (CAS_IN_DOUT_B[43] !== 1'bz) && CAS_IN_DOUT_B[43]; // rv 0
assign CAS_IN_DOUT_B_in[44] = (CAS_IN_DOUT_B[44] !== 1'bz) && CAS_IN_DOUT_B[44]; // rv 0
assign CAS_IN_DOUT_B_in[45] = (CAS_IN_DOUT_B[45] !== 1'bz) && CAS_IN_DOUT_B[45]; // rv 0
assign CAS_IN_DOUT_B_in[46] = (CAS_IN_DOUT_B[46] !== 1'bz) && CAS_IN_DOUT_B[46]; // rv 0
assign CAS_IN_DOUT_B_in[47] = (CAS_IN_DOUT_B[47] !== 1'bz) && CAS_IN_DOUT_B[47]; // rv 0
assign CAS_IN_DOUT_B_in[48] = (CAS_IN_DOUT_B[48] !== 1'bz) && CAS_IN_DOUT_B[48]; // rv 0
assign CAS_IN_DOUT_B_in[49] = (CAS_IN_DOUT_B[49] !== 1'bz) && CAS_IN_DOUT_B[49]; // rv 0
assign CAS_IN_DOUT_B_in[4] = (CAS_IN_DOUT_B[4] !== 1'bz) && CAS_IN_DOUT_B[4]; // rv 0
assign CAS_IN_DOUT_B_in[50] = (CAS_IN_DOUT_B[50] !== 1'bz) && CAS_IN_DOUT_B[50]; // rv 0
assign CAS_IN_DOUT_B_in[51] = (CAS_IN_DOUT_B[51] !== 1'bz) && CAS_IN_DOUT_B[51]; // rv 0
assign CAS_IN_DOUT_B_in[52] = (CAS_IN_DOUT_B[52] !== 1'bz) && CAS_IN_DOUT_B[52]; // rv 0
assign CAS_IN_DOUT_B_in[53] = (CAS_IN_DOUT_B[53] !== 1'bz) && CAS_IN_DOUT_B[53]; // rv 0
assign CAS_IN_DOUT_B_in[54] = (CAS_IN_DOUT_B[54] !== 1'bz) && CAS_IN_DOUT_B[54]; // rv 0
assign CAS_IN_DOUT_B_in[55] = (CAS_IN_DOUT_B[55] !== 1'bz) && CAS_IN_DOUT_B[55]; // rv 0
assign CAS_IN_DOUT_B_in[56] = (CAS_IN_DOUT_B[56] !== 1'bz) && CAS_IN_DOUT_B[56]; // rv 0
assign CAS_IN_DOUT_B_in[57] = (CAS_IN_DOUT_B[57] !== 1'bz) && CAS_IN_DOUT_B[57]; // rv 0
assign CAS_IN_DOUT_B_in[58] = (CAS_IN_DOUT_B[58] !== 1'bz) && CAS_IN_DOUT_B[58]; // rv 0
assign CAS_IN_DOUT_B_in[59] = (CAS_IN_DOUT_B[59] !== 1'bz) && CAS_IN_DOUT_B[59]; // rv 0
assign CAS_IN_DOUT_B_in[5] = (CAS_IN_DOUT_B[5] !== 1'bz) && CAS_IN_DOUT_B[5]; // rv 0
assign CAS_IN_DOUT_B_in[60] = (CAS_IN_DOUT_B[60] !== 1'bz) && CAS_IN_DOUT_B[60]; // rv 0
assign CAS_IN_DOUT_B_in[61] = (CAS_IN_DOUT_B[61] !== 1'bz) && CAS_IN_DOUT_B[61]; // rv 0
assign CAS_IN_DOUT_B_in[62] = (CAS_IN_DOUT_B[62] !== 1'bz) && CAS_IN_DOUT_B[62]; // rv 0
assign CAS_IN_DOUT_B_in[63] = (CAS_IN_DOUT_B[63] !== 1'bz) && CAS_IN_DOUT_B[63]; // rv 0
assign CAS_IN_DOUT_B_in[64] = (CAS_IN_DOUT_B[64] !== 1'bz) && CAS_IN_DOUT_B[64]; // rv 0
assign CAS_IN_DOUT_B_in[65] = (CAS_IN_DOUT_B[65] !== 1'bz) && CAS_IN_DOUT_B[65]; // rv 0
assign CAS_IN_DOUT_B_in[66] = (CAS_IN_DOUT_B[66] !== 1'bz) && CAS_IN_DOUT_B[66]; // rv 0
assign CAS_IN_DOUT_B_in[67] = (CAS_IN_DOUT_B[67] !== 1'bz) && CAS_IN_DOUT_B[67]; // rv 0
assign CAS_IN_DOUT_B_in[68] = (CAS_IN_DOUT_B[68] !== 1'bz) && CAS_IN_DOUT_B[68]; // rv 0
assign CAS_IN_DOUT_B_in[69] = (CAS_IN_DOUT_B[69] !== 1'bz) && CAS_IN_DOUT_B[69]; // rv 0
assign CAS_IN_DOUT_B_in[6] = (CAS_IN_DOUT_B[6] !== 1'bz) && CAS_IN_DOUT_B[6]; // rv 0
assign CAS_IN_DOUT_B_in[70] = (CAS_IN_DOUT_B[70] !== 1'bz) && CAS_IN_DOUT_B[70]; // rv 0
assign CAS_IN_DOUT_B_in[71] = (CAS_IN_DOUT_B[71] !== 1'bz) && CAS_IN_DOUT_B[71]; // rv 0
assign CAS_IN_DOUT_B_in[7] = (CAS_IN_DOUT_B[7] !== 1'bz) && CAS_IN_DOUT_B[7]; // rv 0
assign CAS_IN_DOUT_B_in[8] = (CAS_IN_DOUT_B[8] !== 1'bz) && CAS_IN_DOUT_B[8]; // rv 0
assign CAS_IN_DOUT_B_in[9] = (CAS_IN_DOUT_B[9] !== 1'bz) && CAS_IN_DOUT_B[9]; // rv 0
assign CAS_IN_EN_A_in = (CAS_IN_EN_A !== 1'bz) && CAS_IN_EN_A; // rv 0
assign CAS_IN_EN_B_in = (CAS_IN_EN_B !== 1'bz) && CAS_IN_EN_B; // rv 0
assign CAS_IN_RDACCESS_A_in = (CAS_IN_RDACCESS_A !== 1'bz) && CAS_IN_RDACCESS_A; // rv 0
assign CAS_IN_RDACCESS_B_in = (CAS_IN_RDACCESS_B !== 1'bz) && CAS_IN_RDACCESS_B; // rv 0
assign CAS_IN_RDB_WR_A_in = (CAS_IN_RDB_WR_A !== 1'bz) && CAS_IN_RDB_WR_A; // rv 0
assign CAS_IN_RDB_WR_B_in = (CAS_IN_RDB_WR_B !== 1'bz) && CAS_IN_RDB_WR_B; // rv 0
assign CAS_IN_SBITERR_A_in = (CAS_IN_SBITERR_A !== 1'bz) && CAS_IN_SBITERR_A; // rv 0
assign CAS_IN_SBITERR_B_in = (CAS_IN_SBITERR_B !== 1'bz) && CAS_IN_SBITERR_B; // rv 0
assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0
assign DIN_A_in = DIN_A;
assign DIN_B_in = DIN_B;
assign EN_A_in = (EN_A !== 1'bz) && (EN_A ^ IS_EN_A_INVERTED_REG); // rv 0
assign EN_B_in = (EN_B !== 1'bz) && (EN_B ^ IS_EN_B_INVERTED_REG); // rv 0
assign INJECT_DBITERR_A_in = (INJECT_DBITERR_A !== 1'bz) && INJECT_DBITERR_A; // rv 0
assign INJECT_DBITERR_B_in = (INJECT_DBITERR_B !== 1'bz) && INJECT_DBITERR_B; // rv 0
assign INJECT_SBITERR_A_in = (INJECT_SBITERR_A !== 1'bz) && INJECT_SBITERR_A; // rv 0
assign INJECT_SBITERR_B_in = (INJECT_SBITERR_B !== 1'bz) && INJECT_SBITERR_B; // rv 0
assign OREG_CE_A_in = (OREG_CE_A === 1'bz) || OREG_CE_A; // rv 1
assign OREG_CE_B_in = (OREG_CE_B === 1'bz) || OREG_CE_B; // rv 1
assign OREG_ECC_CE_A_in = (OREG_ECC_CE_A === 1'bz) || OREG_ECC_CE_A; // rv 1
assign OREG_ECC_CE_B_in = (OREG_ECC_CE_B === 1'bz) || OREG_ECC_CE_B; // rv 1
assign RDB_WR_A_in = (RDB_WR_A !== 1'bz) && (RDB_WR_A ^ IS_RDB_WR_A_INVERTED_REG); // rv 0
assign RDB_WR_B_in = (RDB_WR_B !== 1'bz) && (RDB_WR_B ^ IS_RDB_WR_B_INVERTED_REG); // rv 0
assign RST_A_in = (RST_A !== 1'bz) && (RST_A ^ IS_RST_A_INVERTED_REG); // rv 0
assign RST_B_in = (RST_B !== 1'bz) && (RST_B ^ IS_RST_B_INVERTED_REG); // rv 0
assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP; // rv 0
`endif
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign AUTO_SLEEP_LATENCY_BIN = AUTO_SLEEP_LATENCY_REG[3:0];
assign AVG_CONS_INACTIVE_CYCLES_BIN = AVG_CONS_INACTIVE_CYCLES_REG[16:0];
assign BWE_MODE_A_BIN =
(BWE_MODE_A_REG == "PARITY_INTERLEAVED") ? BWE_MODE_A_PARITY_INTERLEAVED :
(BWE_MODE_A_REG == "PARITY_INDEPENDENT") ? BWE_MODE_A_PARITY_INDEPENDENT :
BWE_MODE_A_PARITY_INTERLEAVED;
assign BWE_MODE_B_BIN =
(BWE_MODE_B_REG == "PARITY_INTERLEAVED") ? BWE_MODE_B_PARITY_INTERLEAVED :
(BWE_MODE_B_REG == "PARITY_INDEPENDENT") ? BWE_MODE_B_PARITY_INDEPENDENT :
BWE_MODE_B_PARITY_INTERLEAVED;
assign CASCADE_ORDER_A_BIN =
(CASCADE_ORDER_A_REG == "NONE") ? CASCADE_ORDER_A_NONE :
(CASCADE_ORDER_A_REG == "FIRST") ? CASCADE_ORDER_A_FIRST :
(CASCADE_ORDER_A_REG == "LAST") ? CASCADE_ORDER_A_LAST :
(CASCADE_ORDER_A_REG == "MIDDLE") ? CASCADE_ORDER_A_MIDDLE :
CASCADE_ORDER_A_NONE;
assign CASCADE_ORDER_B_BIN =
(CASCADE_ORDER_B_REG == "NONE") ? CASCADE_ORDER_B_NONE :
(CASCADE_ORDER_B_REG == "FIRST") ? CASCADE_ORDER_B_FIRST :
(CASCADE_ORDER_B_REG == "LAST") ? CASCADE_ORDER_B_LAST :
(CASCADE_ORDER_B_REG == "MIDDLE") ? CASCADE_ORDER_B_MIDDLE :
CASCADE_ORDER_B_NONE;
assign EN_AUTO_SLEEP_MODE_BIN =
(EN_AUTO_SLEEP_MODE_REG == "FALSE") ? EN_AUTO_SLEEP_MODE_FALSE :
(EN_AUTO_SLEEP_MODE_REG == "TRUE") ? EN_AUTO_SLEEP_MODE_TRUE :
EN_AUTO_SLEEP_MODE_FALSE;
assign EN_ECC_RD_A_BIN =
(EN_ECC_RD_A_REG == "FALSE") ? EN_ECC_RD_A_FALSE :
(EN_ECC_RD_A_REG == "TRUE") ? EN_ECC_RD_A_TRUE :
EN_ECC_RD_A_FALSE;
assign EN_ECC_RD_B_BIN =
(EN_ECC_RD_B_REG == "FALSE") ? EN_ECC_RD_B_FALSE :
(EN_ECC_RD_B_REG == "TRUE") ? EN_ECC_RD_B_TRUE :
EN_ECC_RD_B_FALSE;
assign EN_ECC_WR_A_BIN =
(EN_ECC_WR_A_REG == "FALSE") ? EN_ECC_WR_A_FALSE :
(EN_ECC_WR_A_REG == "TRUE") ? EN_ECC_WR_A_TRUE :
EN_ECC_WR_A_FALSE;
assign EN_ECC_WR_B_BIN =
(EN_ECC_WR_B_REG == "FALSE") ? EN_ECC_WR_B_FALSE :
(EN_ECC_WR_B_REG == "TRUE") ? EN_ECC_WR_B_TRUE :
EN_ECC_WR_B_FALSE;
assign IREG_PRE_A_BIN =
(IREG_PRE_A_REG == "FALSE") ? IREG_PRE_A_FALSE :
(IREG_PRE_A_REG == "TRUE") ? IREG_PRE_A_TRUE :
IREG_PRE_A_FALSE;
assign IREG_PRE_B_BIN =
(IREG_PRE_B_REG == "FALSE") ? IREG_PRE_B_FALSE :
(IREG_PRE_B_REG == "TRUE") ? IREG_PRE_B_TRUE :
IREG_PRE_B_FALSE;
assign NUM_UNIQUE_SELF_ADDR_A_BIN = NUM_UNIQUE_SELF_ADDR_A_REG[11:0];
assign NUM_UNIQUE_SELF_ADDR_B_BIN = NUM_UNIQUE_SELF_ADDR_B_REG[11:0];
assign NUM_URAM_IN_MATRIX_BIN = NUM_URAM_IN_MATRIX_REG[11:0];
assign OREG_A_BIN =
(OREG_A_REG == "FALSE") ? OREG_A_FALSE :
(OREG_A_REG == "TRUE") ? OREG_A_TRUE :
OREG_A_FALSE;
assign OREG_B_BIN =
(OREG_B_REG == "FALSE") ? OREG_B_FALSE :
(OREG_B_REG == "TRUE") ? OREG_B_TRUE :
OREG_B_FALSE;
assign OREG_ECC_A_BIN =
(OREG_ECC_A_REG == "FALSE") ? OREG_ECC_A_FALSE :
(OREG_ECC_A_REG == "TRUE") ? OREG_ECC_A_TRUE :
OREG_ECC_A_FALSE;
assign OREG_ECC_B_BIN =
(OREG_ECC_B_REG == "FALSE") ? OREG_ECC_B_FALSE :
(OREG_ECC_B_REG == "TRUE") ? OREG_ECC_B_TRUE :
OREG_ECC_B_FALSE;
assign REG_CAS_A_BIN =
(REG_CAS_A_REG == "FALSE") ? REG_CAS_A_FALSE :
(REG_CAS_A_REG == "TRUE") ? REG_CAS_A_TRUE :
REG_CAS_A_FALSE;
assign REG_CAS_B_BIN =
(REG_CAS_B_REG == "FALSE") ? REG_CAS_B_FALSE :
(REG_CAS_B_REG == "TRUE") ? REG_CAS_B_TRUE :
REG_CAS_B_FALSE;
assign RST_MODE_A_BIN =
(RST_MODE_A_REG == "SYNC") ? RST_MODE_A_SYNC :
(RST_MODE_A_REG == "ASYNC") ? RST_MODE_A_ASYNC :
RST_MODE_A_SYNC;
assign RST_MODE_B_BIN =
(RST_MODE_B_REG == "SYNC") ? RST_MODE_B_SYNC :
(RST_MODE_B_REG == "ASYNC") ? RST_MODE_B_ASYNC :
RST_MODE_B_SYNC;
assign USE_EXT_CE_A_BIN =
(USE_EXT_CE_A_REG == "FALSE") ? USE_EXT_CE_A_FALSE :
(USE_EXT_CE_A_REG == "TRUE") ? USE_EXT_CE_A_TRUE :
USE_EXT_CE_A_FALSE;
assign USE_EXT_CE_B_BIN =
(USE_EXT_CE_B_REG == "FALSE") ? USE_EXT_CE_B_FALSE :
(USE_EXT_CE_B_REG == "TRUE") ? USE_EXT_CE_B_TRUE :
USE_EXT_CE_B_FALSE;
`else
always @ (trig_attr) begin
#1;
AUTO_SLEEP_LATENCY_BIN = AUTO_SLEEP_LATENCY_REG[3:0];
AVG_CONS_INACTIVE_CYCLES_BIN = AVG_CONS_INACTIVE_CYCLES_REG[16:0];
BWE_MODE_A_BIN =
(BWE_MODE_A_REG == "PARITY_INTERLEAVED") ? BWE_MODE_A_PARITY_INTERLEAVED :
(BWE_MODE_A_REG == "PARITY_INDEPENDENT") ? BWE_MODE_A_PARITY_INDEPENDENT :
BWE_MODE_A_PARITY_INTERLEAVED;
BWE_MODE_B_BIN =
(BWE_MODE_B_REG == "PARITY_INTERLEAVED") ? BWE_MODE_B_PARITY_INTERLEAVED :
(BWE_MODE_B_REG == "PARITY_INDEPENDENT") ? BWE_MODE_B_PARITY_INDEPENDENT :
BWE_MODE_B_PARITY_INTERLEAVED;
CASCADE_ORDER_A_BIN =
(CASCADE_ORDER_A_REG == "NONE") ? CASCADE_ORDER_A_NONE :
(CASCADE_ORDER_A_REG == "FIRST") ? CASCADE_ORDER_A_FIRST :
(CASCADE_ORDER_A_REG == "LAST") ? CASCADE_ORDER_A_LAST :
(CASCADE_ORDER_A_REG == "MIDDLE") ? CASCADE_ORDER_A_MIDDLE :
CASCADE_ORDER_A_NONE;
CASCADE_ORDER_B_BIN =
(CASCADE_ORDER_B_REG == "NONE") ? CASCADE_ORDER_B_NONE :
(CASCADE_ORDER_B_REG == "FIRST") ? CASCADE_ORDER_B_FIRST :
(CASCADE_ORDER_B_REG == "LAST") ? CASCADE_ORDER_B_LAST :
(CASCADE_ORDER_B_REG == "MIDDLE") ? CASCADE_ORDER_B_MIDDLE :
CASCADE_ORDER_B_NONE;
EN_AUTO_SLEEP_MODE_BIN =
(EN_AUTO_SLEEP_MODE_REG == "FALSE") ? EN_AUTO_SLEEP_MODE_FALSE :
(EN_AUTO_SLEEP_MODE_REG == "TRUE") ? EN_AUTO_SLEEP_MODE_TRUE :
EN_AUTO_SLEEP_MODE_FALSE;
EN_ECC_RD_A_BIN =
(EN_ECC_RD_A_REG == "FALSE") ? EN_ECC_RD_A_FALSE :
(EN_ECC_RD_A_REG == "TRUE") ? EN_ECC_RD_A_TRUE :
EN_ECC_RD_A_FALSE;
EN_ECC_RD_B_BIN =
(EN_ECC_RD_B_REG == "FALSE") ? EN_ECC_RD_B_FALSE :
(EN_ECC_RD_B_REG == "TRUE") ? EN_ECC_RD_B_TRUE :
EN_ECC_RD_B_FALSE;
EN_ECC_WR_A_BIN =
(EN_ECC_WR_A_REG == "FALSE") ? EN_ECC_WR_A_FALSE :
(EN_ECC_WR_A_REG == "TRUE") ? EN_ECC_WR_A_TRUE :
EN_ECC_WR_A_FALSE;
EN_ECC_WR_B_BIN =
(EN_ECC_WR_B_REG == "FALSE") ? EN_ECC_WR_B_FALSE :
(EN_ECC_WR_B_REG == "TRUE") ? EN_ECC_WR_B_TRUE :
EN_ECC_WR_B_FALSE;
IREG_PRE_A_BIN =
(IREG_PRE_A_REG == "FALSE") ? IREG_PRE_A_FALSE :
(IREG_PRE_A_REG == "TRUE") ? IREG_PRE_A_TRUE :
IREG_PRE_A_FALSE;
IREG_PRE_B_BIN =
(IREG_PRE_B_REG == "FALSE") ? IREG_PRE_B_FALSE :
(IREG_PRE_B_REG == "TRUE") ? IREG_PRE_B_TRUE :
IREG_PRE_B_FALSE;
NUM_UNIQUE_SELF_ADDR_A_BIN = NUM_UNIQUE_SELF_ADDR_A_REG[11:0];
NUM_UNIQUE_SELF_ADDR_B_BIN = NUM_UNIQUE_SELF_ADDR_B_REG[11:0];
NUM_URAM_IN_MATRIX_BIN = NUM_URAM_IN_MATRIX_REG[11:0];
OREG_A_BIN =
(OREG_A_REG == "FALSE") ? OREG_A_FALSE :
(OREG_A_REG == "TRUE") ? OREG_A_TRUE :
OREG_A_FALSE;
OREG_B_BIN =
(OREG_B_REG == "FALSE") ? OREG_B_FALSE :
(OREG_B_REG == "TRUE") ? OREG_B_TRUE :
OREG_B_FALSE;
OREG_ECC_A_BIN =
(OREG_ECC_A_REG == "FALSE") ? OREG_ECC_A_FALSE :
(OREG_ECC_A_REG == "TRUE") ? OREG_ECC_A_TRUE :
OREG_ECC_A_FALSE;
OREG_ECC_B_BIN =
(OREG_ECC_B_REG == "FALSE") ? OREG_ECC_B_FALSE :
(OREG_ECC_B_REG == "TRUE") ? OREG_ECC_B_TRUE :
OREG_ECC_B_FALSE;
REG_CAS_A_BIN =
(REG_CAS_A_REG == "FALSE") ? REG_CAS_A_FALSE :
(REG_CAS_A_REG == "TRUE") ? REG_CAS_A_TRUE :
REG_CAS_A_FALSE;
REG_CAS_B_BIN =
(REG_CAS_B_REG == "FALSE") ? REG_CAS_B_FALSE :
(REG_CAS_B_REG == "TRUE") ? REG_CAS_B_TRUE :
REG_CAS_B_FALSE;
RST_MODE_A_BIN =
(RST_MODE_A_REG == "SYNC") ? RST_MODE_A_SYNC :
(RST_MODE_A_REG == "ASYNC") ? RST_MODE_A_ASYNC :
RST_MODE_A_SYNC;
RST_MODE_B_BIN =
(RST_MODE_B_REG == "SYNC") ? RST_MODE_B_SYNC :
(RST_MODE_B_REG == "ASYNC") ? RST_MODE_B_ASYNC :
RST_MODE_B_SYNC;
USE_EXT_CE_A_BIN =
(USE_EXT_CE_A_REG == "FALSE") ? USE_EXT_CE_A_FALSE :
(USE_EXT_CE_A_REG == "TRUE") ? USE_EXT_CE_A_TRUE :
USE_EXT_CE_A_FALSE;
USE_EXT_CE_B_BIN =
(USE_EXT_CE_B_REG == "FALSE") ? USE_EXT_CE_B_FALSE :
(USE_EXT_CE_B_REG == "TRUE") ? USE_EXT_CE_B_TRUE :
USE_EXT_CE_B_FALSE;
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((AUTO_SLEEP_LATENCY_REG != 8) &&
(AUTO_SLEEP_LATENCY_REG != 3) &&
(AUTO_SLEEP_LATENCY_REG != 4) &&
(AUTO_SLEEP_LATENCY_REG != 5) &&
(AUTO_SLEEP_LATENCY_REG != 6) &&
(AUTO_SLEEP_LATENCY_REG != 7) &&
(AUTO_SLEEP_LATENCY_REG != 9) &&
(AUTO_SLEEP_LATENCY_REG != 10) &&
(AUTO_SLEEP_LATENCY_REG != 11) &&
(AUTO_SLEEP_LATENCY_REG != 12) &&
(AUTO_SLEEP_LATENCY_REG != 13) &&
(AUTO_SLEEP_LATENCY_REG != 14) &&
(AUTO_SLEEP_LATENCY_REG != 15))) begin
$display("Error: [Unisim %s-101] AUTO_SLEEP_LATENCY attribute is set to %d. Legal values for this attribute are 8, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, AUTO_SLEEP_LATENCY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((AVG_CONS_INACTIVE_CYCLES_REG < 10) || (AVG_CONS_INACTIVE_CYCLES_REG > 100000))) begin
$display("Error: [Unisim %s-102] AVG_CONS_INACTIVE_CYCLES attribute is set to %d. Legal values for this attribute are 10 to 100000. Instance: %m", MODULE_NAME, AVG_CONS_INACTIVE_CYCLES_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((BWE_MODE_A_REG != "PARITY_INTERLEAVED") &&
(BWE_MODE_A_REG != "PARITY_INDEPENDENT"))) begin
$display("Error: [Unisim %s-103] BWE_MODE_A attribute is set to %s. Legal values for this attribute are PARITY_INTERLEAVED or PARITY_INDEPENDENT. Instance: %m", MODULE_NAME, BWE_MODE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((BWE_MODE_B_REG != "PARITY_INTERLEAVED") &&
(BWE_MODE_B_REG != "PARITY_INDEPENDENT"))) begin
$display("Error: [Unisim %s-104] BWE_MODE_B attribute is set to %s. Legal values for this attribute are PARITY_INTERLEAVED or PARITY_INDEPENDENT. Instance: %m", MODULE_NAME, BWE_MODE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CASCADE_ORDER_A_REG != "NONE") &&
(CASCADE_ORDER_A_REG != "FIRST") &&
(CASCADE_ORDER_A_REG != "LAST") &&
(CASCADE_ORDER_A_REG != "MIDDLE"))) begin
$display("Error: [Unisim %s-105] CASCADE_ORDER_A attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CASCADE_ORDER_B_REG != "NONE") &&
(CASCADE_ORDER_B_REG != "FIRST") &&
(CASCADE_ORDER_B_REG != "LAST") &&
(CASCADE_ORDER_B_REG != "MIDDLE"))) begin
$display("Error: [Unisim %s-106] CASCADE_ORDER_B attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_AUTO_SLEEP_MODE_REG != "FALSE") &&
(EN_AUTO_SLEEP_MODE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-107] EN_AUTO_SLEEP_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_RD_A_REG != "FALSE") &&
(EN_ECC_RD_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-108] EN_ECC_RD_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_RD_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_RD_B_REG != "FALSE") &&
(EN_ECC_RD_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-109] EN_ECC_RD_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_RD_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_WR_A_REG != "FALSE") &&
(EN_ECC_WR_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-110] EN_ECC_WR_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WR_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_WR_B_REG != "FALSE") &&
(EN_ECC_WR_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-111] EN_ECC_WR_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WR_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IREG_PRE_A_REG != "FALSE") &&
(IREG_PRE_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-112] IREG_PRE_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IREG_PRE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IREG_PRE_B_REG != "FALSE") &&
(IREG_PRE_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-113] IREG_PRE_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IREG_PRE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((NUM_UNIQUE_SELF_ADDR_A_REG < 1) || (NUM_UNIQUE_SELF_ADDR_A_REG > 2048))) begin
$display("Error: [Unisim %s-122] NUM_UNIQUE_SELF_ADDR_A attribute is set to %d. Legal values for this attribute are 1 to 2048. Instance: %m", MODULE_NAME, NUM_UNIQUE_SELF_ADDR_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((NUM_UNIQUE_SELF_ADDR_B_REG < 1) || (NUM_UNIQUE_SELF_ADDR_B_REG > 2048))) begin
$display("Error: [Unisim %s-123] NUM_UNIQUE_SELF_ADDR_B attribute is set to %d. Legal values for this attribute are 1 to 2048. Instance: %m", MODULE_NAME, NUM_UNIQUE_SELF_ADDR_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((NUM_URAM_IN_MATRIX_REG < 1) || (NUM_URAM_IN_MATRIX_REG > 2048))) begin
$display("Error: [Unisim %s-124] NUM_URAM_IN_MATRIX attribute is set to %d. Legal values for this attribute are 1 to 2048. Instance: %m", MODULE_NAME, NUM_URAM_IN_MATRIX_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OREG_A_REG != "FALSE") &&
(OREG_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-125] OREG_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OREG_B_REG != "FALSE") &&
(OREG_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-126] OREG_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OREG_ECC_A_REG != "FALSE") &&
(OREG_ECC_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-127] OREG_ECC_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_ECC_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OREG_ECC_B_REG != "FALSE") &&
(OREG_ECC_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-128] OREG_ECC_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_ECC_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((REG_CAS_A_REG != "FALSE") &&
(REG_CAS_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-129] REG_CAS_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, REG_CAS_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((REG_CAS_B_REG != "FALSE") &&
(REG_CAS_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-130] REG_CAS_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, REG_CAS_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RST_MODE_A_REG != "SYNC") &&
(RST_MODE_A_REG != "ASYNC"))) begin
$display("Error: [Unisim %s-131] RST_MODE_A attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, RST_MODE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RST_MODE_B_REG != "SYNC") &&
(RST_MODE_B_REG != "ASYNC"))) begin
$display("Error: [Unisim %s-132] RST_MODE_B attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, RST_MODE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_EXT_CE_A_REG != "FALSE") &&
(USE_EXT_CE_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-137] USE_EXT_CE_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_EXT_CE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_EXT_CE_B_REG != "FALSE") &&
(USE_EXT_CE_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-138] USE_EXT_CE_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_EXT_CE_B_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
`ifdef XIL_TIMING
reg notifier;
`endif
// begin behavioral model
// define tasks, functions
reg cas_a_warning = 1'b0;
reg cas_b_warning = 1'b0;
task is_cas_a_zero;
integer i;
begin
cas_a_warning = 1'b0;
for (i=0;i<=22;i=i+1) begin
if (CAS_IN_ADDR_A[i] !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_ADDR_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
for (i=0;i<=8;i=i+1) begin
if (CAS_IN_BWE_A[i] !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_BWE_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
if (CAS_IN_DBITERR_A !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_DBITERR_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DIN_A[i] !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_DIN_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DOUT_A[i] !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_DOUT_A[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
if (CAS_IN_EN_A !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_EN_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if (CAS_IN_RDACCESS_A !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_RDACCESS_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if (CAS_IN_RDB_WR_A !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_RDB_WR_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if (CAS_IN_SBITERR_A !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-15] CAS_IN_SBITERR_A signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
end
endtask // is_cas_a_zero
task is_cas_a_floating;
integer i;
begin
cas_a_warning = 1'b0;
for (i=0;i<=22;i=i+1) begin
if (CAS_IN_ADDR_A[i] === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_ADDR_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
for (i=0;i<=8;i=i+1) begin
if (CAS_IN_BWE_A[i] === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_BWE_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
if (CAS_IN_DBITERR_A === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_DBITERR_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DIN_A[i] === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_DIN_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DOUT_A[i] === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_DOUT_A[%2d] signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_A_REG);
end
end
if (CAS_IN_EN_A === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_EN_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if (CAS_IN_RDACCESS_A === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_RDACCESS_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if (CAS_IN_RDB_WR_A === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_RDB_WR_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if (CAS_IN_SBITERR_A === 1'bz) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-16] CAS_IN_SBITERR_A signal is unconnected in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
end
endtask // is_cas_a_floating
task is_cas_b_zero;
integer i;
begin
cas_b_warning = 1'b0;
for (i=0;i<=22;i=i+1) begin
if (CAS_IN_ADDR_B[i] !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_ADDR_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG);
end
end
for (i=0;i<=8;i=i+1) begin
if (CAS_IN_BWE_B[i] !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_BWE_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG);
end
end
if (CAS_IN_DBITERR_B !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_DBITERR_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DIN_B[i] !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_DIN_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG);
end
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DOUT_B[i] !== 1'b0) begin
cas_a_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_DOUT_B[%2d] signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, i, CASCADE_ORDER_B_REG);
end
end
if (CAS_IN_EN_B !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_EN_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
if (CAS_IN_RDACCESS_B !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_RDACCESS_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
if (CAS_IN_RDB_WR_B !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_RDB_WR_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
if (CAS_IN_SBITERR_B !== 1'b0) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-17] CAS_IN_SBITERR_B signal is not tied low in CASCADE mode (%s) Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
end
endtask // is_cas_b_zero
task is_cas_b_floating;
integer i;
begin
cas_b_warning = 1'b0;
for (i=0;i<=22;i=i+1) begin
if (CAS_IN_ADDR_B[i] === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_ADDR_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
for (i=0;i<=8;i=i+1) begin
if (CAS_IN_BWE_B[i] === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_BWE_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
if (CAS_IN_DBITERR_B === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_DBITERR_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DIN_B[i] === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_DIN_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
for (i=0;i<=71;i=i+1) begin
if (CAS_IN_DOUT_B[i] === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_DOUT_B[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
if (CAS_IN_EN_B === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_EN_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CAS_IN_RDACCESS_B === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_RDACCESS_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CAS_IN_RDB_WR_B === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_RDB_WR_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CAS_IN_SBITERR_B === 1'bz) begin
cas_b_warning = 1'b1;
$display("Warning: [Unisim %s-18] CAS_IN_SBITERR_B signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
end
endtask // is_cas_b_floating
function [7:0] fn_ecc (
input encode,
input [63:0] d_i,
input [7:0] dp_i
);
reg ecc_7;
begin
fn_ecc[0] = d_i[0] ^ d_i[1] ^ d_i[3] ^ d_i[4] ^ d_i[6] ^
d_i[8] ^ d_i[10] ^ d_i[11] ^ d_i[13] ^ d_i[15] ^
d_i[17] ^ d_i[19] ^ d_i[21] ^ d_i[23] ^ d_i[25] ^
d_i[26] ^ d_i[28] ^ d_i[30] ^ d_i[32] ^ d_i[34] ^
d_i[36] ^ d_i[38] ^ d_i[40] ^ d_i[42] ^ d_i[44] ^
d_i[46] ^ d_i[48] ^ d_i[50] ^ d_i[52] ^ d_i[54] ^
d_i[56] ^ d_i[57] ^ d_i[59] ^ d_i[61] ^ d_i[63];
fn_ecc[1] = d_i[0] ^ d_i[2] ^ d_i[3] ^ d_i[5] ^ d_i[6] ^
d_i[9] ^ d_i[10] ^ d_i[12] ^ d_i[13] ^ d_i[16] ^
d_i[17] ^ d_i[20] ^ d_i[21] ^ d_i[24] ^ d_i[25] ^
d_i[27] ^ d_i[28] ^ d_i[31] ^ d_i[32] ^ d_i[35] ^
d_i[36] ^ d_i[39] ^ d_i[40] ^ d_i[43] ^ d_i[44] ^
d_i[47] ^ d_i[48] ^ d_i[51] ^ d_i[52] ^ d_i[55] ^
d_i[56] ^ d_i[58] ^ d_i[59] ^ d_i[62] ^ d_i[63];
fn_ecc[2] = d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^
d_i[17] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[45] ^ d_i[46] ^
d_i[47] ^ d_i[48] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
fn_ecc[3] = d_i[4] ^ d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[4] = d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ d_i[15] ^
d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[5] = d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ d_i[30] ^
d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^
d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[6] = d_i[57] ^ d_i[58] ^ d_i[59] ^ d_i[60] ^ d_i[61] ^
d_i[62] ^ d_i[63];
ecc_7 = d_i[0] ^ d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[4] ^
d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^
d_i[10] ^ d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^
d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^
d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^
d_i[25] ^ d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^
d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^
d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^
d_i[40] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^
d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^
d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^
d_i[55] ^ d_i[56] ^ d_i[57] ^ d_i[58] ^ d_i[59] ^
d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
if (encode) begin
fn_ecc[7] = ecc_7 ^
fn_ecc[0] ^ fn_ecc[1] ^ fn_ecc[2] ^ fn_ecc[3] ^
fn_ecc[4] ^ fn_ecc[5] ^ fn_ecc[6];
end
else begin
fn_ecc[7] = ecc_7 ^
dp_i[0] ^ dp_i[1] ^ dp_i[2] ^ dp_i[3] ^
dp_i[4] ^ dp_i[5] ^ dp_i[6];
end
end
endfunction // fn_ecc
function [71:0] fn_cor_bit (
input [6:0] error_bit,
input [63:0] d_i,
input [7:0] dp_i
);
reg [71:0] cor_int;
begin
cor_int = {d_i[63:57], dp_i[6], d_i[56:26], dp_i[5], d_i[25:11], dp_i[4],
d_i[10:4], dp_i[3], d_i[3:1], dp_i[2], d_i[0], dp_i[1:0],
dp_i[7]};
cor_int[error_bit] = ~cor_int[error_bit];
fn_cor_bit = {cor_int[0], cor_int[64], cor_int[32], cor_int[16],
cor_int[8], cor_int[4], cor_int[2:1], cor_int[71:65],
cor_int[63:33], cor_int[31:17], cor_int[15:9],
cor_int[7:5], cor_int[3]};
end
endfunction // fn_cor_bit
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CASCADE_ORDER_A_REG != "NONE") &&
(USE_EXT_CE_A_REG == "TRUE"))) begin
$display("Error: [Unisim %s-1] CASCADE_ORDER_A attribute is set to %s and USE_EXT_CE_A attribute is set to %s. EXT_CE_A can not be used in cascaded URAM applications. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG, USE_EXT_CE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CASCADE_ORDER_B_REG != "NONE") &&
(USE_EXT_CE_B_REG == "TRUE"))) begin
$display("Error: [Unisim %s-2] CASCADE_ORDER_B attribute is set to %s and USE_EXT_CE_B attribute is set to %s. EXT_CE_B can not be used in cascaded URAM applications. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG, USE_EXT_CE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CASCADE_ORDER_A_REG == "NONE") ||
(CASCADE_ORDER_A_REG == "FIRST")) begin
is_cas_a_zero;
if (cas_a_warning) $display("Warning: [Unisim %s-13] CASCADE_ORDER_A attribute is set to %s and some or all of the CASCADE signals are not tied low. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly tied off. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if ((attr_test == 1'b1) ||
(CASCADE_ORDER_A_REG == "LAST") ||
(CASCADE_ORDER_A_REG == "MIDDLE")) begin
is_cas_a_floating;
if (cas_a_warning) $display("Warning: [Unisim %s-13] CASCADE_ORDER_A attribute is set to %s and some or all of the CASCADE signals are unconnected. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly connected. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
end
if ((attr_test == 1'b1) ||
(CASCADE_ORDER_B_REG == "NONE") ||
(CASCADE_ORDER_B_REG == "FIRST")) begin
is_cas_b_zero;
if (cas_b_warning) $display("Warning: [Unisim %s-14] CASCADE_ORDER_B attribute is set to %s and some or all of the CASCADE signals are not tied low. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly tied off. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
if ((attr_test == 1'b1) ||
(CASCADE_ORDER_B_REG == "LAST") ||
(CASCADE_ORDER_B_REG == "MIDDLE")) begin
is_cas_b_floating;
if (cas_b_warning) $display("Warning: [Unisim %s-14] CASCADE_ORDER_B attribute is set to %s and some or all of the CASCADE signals are unconnected. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly connected. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
end
if ((attr_test == 1'b1) ||
((EN_AUTO_SLEEP_MODE_REG == "TRUE") &&
(USE_EXT_CE_A_REG == "TRUE"))) begin
$display("Error: [Unisim %s-19] EN_AUTO_SLEEP_MODE attribute is set to %s and USE_EXT_CE_A is set to %s. External OREG CE cannot be used when AUTO_SLEEP_MODE is enabled. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG, USE_EXT_CE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_AUTO_SLEEP_MODE_REG == "TRUE") &&
(USE_EXT_CE_B_REG == "TRUE"))) begin
$display("Error: [Unisim %s-20] EN_AUTO_SLEEP_MODE attribute is set to %s and USE_EXT_CE_B is set to %s. External OREG CE cannot be used when AUTO_SLEEP_MODE is enabled. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG, USE_EXT_CE_B_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
localparam mem_width = 72;
localparam mem_depth = 4 * 1024;
localparam encode = 1'b1;
localparam decode = 1'b0;
localparam [22:0] ADDR_INIT = 23'b0;
localparam [8:0] BWE_INIT = 9'b0;
localparam [mem_width-1:0] D_INIT = {mem_width{1'b0}};
localparam [mem_width-1:0] D_UNDEF = {mem_width{1'bx}};
reg [mem_width-1 : 0 ] mem [0 : mem_depth-1];
integer wa;
reg [11:0] ram_addr_a;
reg [11:0] ram_addr_b;
reg ram_ce_a;
reg ram_ce_b;
reg DEEPSLEEP_in = 1'b0;
reg SHUTDOWN_in = 1'b0;
reg ram_ce_a_int=0;
reg ram_ce_b_int=0;
reg ram_ce_a_pre=0;
reg ram_ce_b_pre=0;
reg [15:1] ram_ce_a_fifo;
reg [15:1] ram_ce_b_fifo;
reg [71:0] ram_bwe_a;
reg [71:0] ram_bwe_b;
reg ram_we_a;
reg ram_we_b;
reg ram_we_a_event = 1'b0;
reg ram_we_b_event = 1'b0;
reg [71:0] ram_data_a;
reg [71:0] ram_data_b;
// input register stages
// decisions simulate faster than assignments - wider muxes, less busses
reg [22:0] ADDR_A_reg;
reg [22:0] ADDR_B_reg;
reg [8:0] BWE_A_reg;
reg [8:0] BWE_B_reg;
reg [71:0] DIN_A_reg;
reg [71:0] DIN_B_reg;
reg EN_A_reg;
reg EN_B_reg;
reg INJECT_DBITERR_A_reg;
reg INJECT_DBITERR_B_reg;
reg INJECT_SBITERR_A_reg;
reg INJECT_SBITERR_B_reg;
reg RDB_WR_A_reg;
reg RDB_WR_B_reg;
reg [22:0] ADDR_A_int;
reg [22:0] ADDR_B_int;
reg [8:0] BWE_A_int;
reg [8:0] BWE_B_int;
reg [71:0] DIN_A_int;
reg [71:0] DIN_B_int;
reg EN_A_int;
reg EN_B_int;
reg INJECT_DBITERR_A_int;
reg INJECT_DBITERR_B_int;
reg INJECT_SBITERR_A_int;
reg INJECT_SBITERR_B_int;
reg RDB_WR_A_int;
reg RDB_WR_B_int;
reg RST_A_async = 1'b0;
reg RST_B_async = 1'b0;
reg RST_A_sync = 1'b0;
reg RST_B_sync = 1'b0;
integer wake_count;
wire auto_sleep;
reg shut_down;
reg a_sleep;
reg auto_sleep_A;
reg auto_sleep_B;
wire auto_wake_up_A;
wire auto_wake_up_B;
reg CAS_OUT_DBITERR_A_out;
reg CAS_OUT_DBITERR_B_out;
reg CAS_OUT_EN_A_out;
reg CAS_OUT_EN_B_out;
reg CAS_OUT_RDACCESS_A_out;
reg CAS_OUT_RDACCESS_B_out;
reg CAS_OUT_RDB_WR_A_out;
reg CAS_OUT_RDB_WR_B_out;
reg CAS_OUT_SBITERR_A_out;
reg CAS_OUT_SBITERR_B_out;
reg DBITERR_A_out;
reg DBITERR_B_out;
reg RDACCESS_A_out;
reg RDACCESS_B_out;
reg SBITERR_A_out;
reg SBITERR_B_out;
reg [22:0] CAS_OUT_ADDR_A_out;
reg [22:0] CAS_OUT_ADDR_B_out;
reg [71:0] CAS_OUT_DIN_A_out;
reg [71:0] CAS_OUT_DIN_B_out;
reg [71:0] CAS_OUT_DOUT_A_out;
reg [71:0] CAS_OUT_DOUT_B_out;
reg [71:0] DOUT_A_out;
reg [71:0] DOUT_B_out;
reg [8:0] CAS_OUT_BWE_A_out;
reg [8:0] CAS_OUT_BWE_B_out;
assign CAS_OUT_ADDR_A = CAS_OUT_ADDR_A_out;
assign CAS_OUT_ADDR_B = CAS_OUT_ADDR_B_out;
assign CAS_OUT_BWE_A = CAS_OUT_BWE_A_out;
assign CAS_OUT_BWE_B = CAS_OUT_BWE_B_out;
assign CAS_OUT_DBITERR_A = DBITERR_A_out;
assign CAS_OUT_DBITERR_B = DBITERR_B_out;
assign CAS_OUT_DIN_A = CAS_OUT_DIN_A_out;
assign CAS_OUT_DIN_B = CAS_OUT_DIN_B_out;
assign CAS_OUT_DOUT_A = DOUT_A_out;
assign CAS_OUT_DOUT_B = DOUT_B_out;
assign CAS_OUT_EN_A = CAS_OUT_EN_A_out;
assign CAS_OUT_EN_B = CAS_OUT_EN_B_out;
assign CAS_OUT_RDACCESS_A = RDACCESS_A_out;
assign CAS_OUT_RDACCESS_B = RDACCESS_B_out;
assign CAS_OUT_RDB_WR_A = CAS_OUT_RDB_WR_A_out;
assign CAS_OUT_RDB_WR_B = CAS_OUT_RDB_WR_B_out;
assign CAS_OUT_SBITERR_A = SBITERR_A_out;
assign CAS_OUT_SBITERR_B = SBITERR_B_out;
assign DBITERR_A = DBITERR_A_out;
assign DBITERR_B = DBITERR_B_out;
assign DOUT_A = DOUT_A_out;
assign DOUT_B = DOUT_B_out;
assign RDACCESS_A = RDACCESS_A_out;
assign RDACCESS_B = RDACCESS_B_out;
assign SBITERR_A = SBITERR_A_out;
assign SBITERR_B = SBITERR_B_out;
`ifndef XIL_XECLIB
reg INIT_RAM = 1'b0;
initial begin
#100; INIT_RAM = 1'b1;
end
`endif
`ifndef XIL_XECLIB
reg rst_a_warn_once = 1'b0;
reg rst_b_warn_once = 1'b0;
always @(posedge CLK_in) begin
if ((attr_test == 1'b1) ||
((EN_A_int == 1'b1) && (RDB_WR_A_int == 1'b0) &&
((RST_A_sync == 1'b1) || (RST_A_async == 1'b1)) &&
(CASCADE_ORDER_A_BIN != CASCADE_ORDER_A_NONE) &&
(REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin
if (rst_a_warn_once == 1'b0) begin
$display("Warning: [Unisim %s-11] At time (%.3f) ns: CASCADE_ORDER_A attribute is set to %s and REG_CAS_A attribute is set to %s with RST_A and a READ command both active. In certain circumstances the implementation tools optimize the uram pipeline to achieve optimal timing. This is achieved by manipulating the REG_CAS_A attributes. This will not alter the latency of the pipeline but may result in different reset behavior pre and post implementation under these conditions. To avoid this, deassert EN_A when RST_A is active. Instance: %m", MODULE_NAME, $time/1000.0, CASCADE_ORDER_A_REG, REG_CAS_A_REG);
rst_a_warn_once = 1'b1;
end
end else begin
rst_a_warn_once = 1'b0;
end
end
always @(posedge CLK_in) begin
if ((attr_test == 1'b1) ||
((EN_B_int == 1'b1) && (RDB_WR_B_int == 1'b0) &&
((RST_B_sync == 1'b1) || (RST_B_async == 1'b1)) &&
(CASCADE_ORDER_B_BIN != CASCADE_ORDER_B_NONE) &&
(REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin
if (rst_b_warn_once == 1'b0) begin
$display("Warning: [Unisim %s-12] At time (%.3f) ns: CASCADE_ORDER_B attribute is set to %s and REG_CAS_B attribute is set to %s with RST_B and a READ command both active. In certain circumstances the implementation tools optimize the uram pipeline to achieve optimal timing. This is achieved by manipulating the REG_CAS_B attributes. This will not alter the latency of the pipeline but may result in different reset behavior pre and post implementation under these conditions. To avoid this, deassert EN_B when RST_B is active. Instance: %m", MODULE_NAME, $time/1000.0, CASCADE_ORDER_B_REG, REG_CAS_B_REG);
rst_b_warn_once = 1'b1;
end
end else begin
rst_b_warn_once = 1'b0;
end
end
`endif
always @ (*) begin
if (RST_MODE_A_BIN == RST_MODE_A_ASYNC) begin
RST_A_async = RST_A_in;
end
end
always @ (*) begin
if (RST_MODE_B_BIN == RST_MODE_B_ASYNC) begin
RST_B_async = RST_B_in;
end
end
always @ (posedge CLK_in) begin
if ((RST_MODE_A_BIN == RST_MODE_A_SYNC) && (RST_A_sync !== RST_A_in))
RST_A_sync <= RST_A_in;
if ((RST_MODE_B_BIN == RST_MODE_B_SYNC) && (RST_B_sync !== RST_B_in))
RST_B_sync <= RST_B_in;
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR ||
(((CASCADE_ORDER_A_BIN != CASCADE_ORDER_A_NONE) &&
(REG_CAS_A_BIN == REG_CAS_A_FALSE)) &&
(((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) &&
(IREG_PRE_A_BIN == IREG_PRE_A_FALSE)))) begin
ADDR_A_reg <= ADDR_INIT;
EN_A_reg <= 1'b0;
RDB_WR_A_reg <= 1'b0;
BWE_A_reg <= BWE_INIT;
DIN_A_reg <= D_INIT;
INJECT_DBITERR_A_reg <= 1'b0;
INJECT_SBITERR_A_reg <= 1'b0;
end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_TRUE)) begin
EN_A_reg <= CAS_IN_EN_A_in;
if (CAS_IN_EN_A_in) begin
ADDR_A_reg[22:12] <= CAS_IN_ADDR_A_in[22:12];
end
if (CAS_IN_EN_A_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin
ADDR_A_reg[11:0] <= CAS_IN_ADDR_A_in[11:0];
BWE_A_reg <= CAS_IN_BWE_A_in;
DIN_A_reg <= CAS_IN_DIN_A_in;
RDB_WR_A_reg <= CAS_IN_RDB_WR_A_in;
end
end else begin
EN_A_reg <= EN_A_in;
if (EN_A_in) begin
ADDR_A_reg[22:12] <= ADDR_A_in[22:12];
end
if (EN_A_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin
ADDR_A_reg[11:0] <= ADDR_A_in[11:0];
BWE_A_reg <= BWE_A_in;
DIN_A_reg <= DIN_A_in;
INJECT_DBITERR_A_reg <= INJECT_DBITERR_A_in;
INJECT_SBITERR_A_reg <= INJECT_SBITERR_A_in;
RDB_WR_A_reg <= RDB_WR_A_in;
end
end
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin
ADDR_A_int = CAS_IN_ADDR_A_in;
end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) &&
(IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) ||
(((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin
ADDR_A_int = ADDR_A_reg;
end else begin
ADDR_A_int = ADDR_A_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin
BWE_A_int = CAS_IN_BWE_A_in;
end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) &&
(IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) ||
(((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin
BWE_A_int = BWE_A_reg;
end else begin
BWE_A_int = BWE_A_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin
DIN_A_int = CAS_IN_DIN_A_in;
end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) &&
(IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) ||
(((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin
DIN_A_int = DIN_A_reg;
end else begin
DIN_A_int = DIN_A_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin
EN_A_int = CAS_IN_EN_A_in;
end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) &&
(IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) ||
(((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin
EN_A_int = EN_A_reg;
end else begin
EN_A_int = EN_A_in;
end
end
always @ (*) begin
if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin
INJECT_DBITERR_A_int = INJECT_DBITERR_A_reg;
end else begin
INJECT_DBITERR_A_int = INJECT_DBITERR_A_in;
end
end
always @ (*) begin
if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin
INJECT_SBITERR_A_int = INJECT_SBITERR_A_reg;
end else begin
INJECT_SBITERR_A_int = INJECT_SBITERR_A_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin
RDB_WR_A_int = CAS_IN_RDB_WR_A_in;
end else if ((((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) &&
(IREG_PRE_A_BIN == IREG_PRE_A_TRUE)) ||
(((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
(REG_CAS_A_BIN == REG_CAS_A_TRUE))) begin
RDB_WR_A_int = RDB_WR_A_reg;
end else begin
RDB_WR_A_int = RDB_WR_A_in;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR ||
(((CASCADE_ORDER_B_BIN != CASCADE_ORDER_B_NONE) &&
(REG_CAS_B_BIN == REG_CAS_B_FALSE)) &&
(((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) &&
(IREG_PRE_B_BIN == IREG_PRE_B_FALSE)))) begin
ADDR_B_reg <= ADDR_INIT;
EN_B_reg <= 1'b0;
RDB_WR_B_reg <= 1'b0;
BWE_B_reg <= BWE_INIT;
DIN_B_reg <= D_INIT;
INJECT_DBITERR_B_reg <= 1'b0;
INJECT_SBITERR_B_reg <= 1'b0;
end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_TRUE)) begin
EN_B_reg <= CAS_IN_EN_B_in;
if (CAS_IN_EN_B_in) begin
ADDR_B_reg[22:12] <= CAS_IN_ADDR_B_in[22:12];
end
if (CAS_IN_EN_B_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin
ADDR_B_reg[11:0] <= CAS_IN_ADDR_B_in[11:0];
BWE_B_reg <= CAS_IN_BWE_B_in;
DIN_B_reg <= CAS_IN_DIN_B_in;
RDB_WR_B_reg <= CAS_IN_RDB_WR_B_in;
end
end else begin
EN_B_reg <= EN_B_in;
if (EN_B_in) begin
ADDR_B_reg[22:12] <= ADDR_B_in[22:12];
end
if (EN_B_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin
ADDR_B_reg[11:0] <= ADDR_B_in[11:0];
BWE_B_reg <= BWE_B_in;
DIN_B_reg <= DIN_B_in;
INJECT_DBITERR_B_reg <= INJECT_DBITERR_B_in;
INJECT_SBITERR_B_reg <= INJECT_SBITERR_B_in;
RDB_WR_B_reg <= RDB_WR_B_in;
end
end
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin
ADDR_B_int = CAS_IN_ADDR_B_in;
end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) &&
(IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) ||
(((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin
ADDR_B_int = ADDR_B_reg;
end else begin
ADDR_B_int = ADDR_B_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin
BWE_B_int = CAS_IN_BWE_B_in;
end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) &&
(IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) ||
(((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin
BWE_B_int = BWE_B_reg;
end else begin
BWE_B_int = BWE_B_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin
DIN_B_int = CAS_IN_DIN_B_in;
end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) &&
(IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) ||
(((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin
DIN_B_int = DIN_B_reg;
end else begin
DIN_B_int = DIN_B_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin
EN_B_int = CAS_IN_EN_B_in;
end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) &&
(IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) ||
(((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin
EN_B_int = EN_B_reg;
end else begin
EN_B_int = EN_B_in;
end
end
always @ (*) begin
if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin
INJECT_DBITERR_B_int = INJECT_DBITERR_B_reg;
end else begin
INJECT_DBITERR_B_int = INJECT_DBITERR_B_in;
end
end
always @ (*) begin
if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin
INJECT_SBITERR_B_int = INJECT_SBITERR_B_reg;
end else begin
INJECT_SBITERR_B_int = INJECT_SBITERR_B_in;
end
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin
RDB_WR_B_int = CAS_IN_RDB_WR_B_in;
end else if ((((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) &&
(IREG_PRE_B_BIN == IREG_PRE_B_TRUE)) ||
(((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
(REG_CAS_B_BIN == REG_CAS_B_TRUE))) begin
RDB_WR_B_int = RDB_WR_B_reg;
end else begin
RDB_WR_B_int = RDB_WR_B_in;
end
end
// cascade out - input controls
always @ (*) begin
if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin
CAS_OUT_ADDR_A_out = ADDR_INIT;
end else begin
CAS_OUT_ADDR_A_out = ADDR_A_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin
CAS_OUT_BWE_A_out = BWE_INIT;
end else begin
CAS_OUT_BWE_A_out = BWE_A_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin
CAS_OUT_DIN_A_out = D_INIT;
end else begin
CAS_OUT_DIN_A_out = DIN_A_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin
CAS_OUT_EN_A_out = 1'b0;
end else begin
CAS_OUT_EN_A_out = EN_A_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) || // no cascade out
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_NONE)) begin
CAS_OUT_RDB_WR_A_out = 1'b0;
end else begin
CAS_OUT_RDB_WR_A_out = RDB_WR_A_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin
CAS_OUT_ADDR_B_out = ADDR_INIT;
end else begin
CAS_OUT_ADDR_B_out = ADDR_B_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin
CAS_OUT_BWE_B_out = BWE_INIT;
end else begin
CAS_OUT_BWE_B_out = BWE_B_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin
CAS_OUT_DIN_B_out = D_INIT;
end else begin
CAS_OUT_DIN_B_out = DIN_B_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin
CAS_OUT_EN_B_out = 1'b0;
end else begin
CAS_OUT_EN_B_out = EN_B_int;
end
end
always @ (*) begin
if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) || // no cascade out
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_NONE)) begin
CAS_OUT_RDB_WR_B_out = 1'b0;
end else begin
CAS_OUT_RDB_WR_B_out = RDB_WR_B_int;
end
end
// cascade=data out - outputs
reg [71:0] ram_data_a_lat;
reg [71:0] ram_data_a_out;
// reg [71:0] ram_data_a_hold=D_INIT;
reg [71:0] ram_data_a_reg;
reg [71:0] ram_data_a_ecc=72'h000000000000000000;
reg [71:0] ram_data_b_lat;
reg [71:0] ram_data_b_out;
reg [71:0] ram_data_b_reg;
reg [71:0] ram_data_b_ecc=72'h000000000000000000;
reg RDACCESS_A_lat;
// reg RDACCESS_A_hold;
reg RDACCESS_B_lat;
reg RDACCESS_A_int;
reg RDACCESS_B_int;
reg SBITERR_A_ecc=1'b0;
reg DBITERR_A_ecc=1'b0;
reg SBITERR_B_ecc=1'b0;
reg DBITERR_B_ecc=1'b0;
reg DBITERR_A_reg;
reg DBITERR_B_reg;
reg [71:0] DOUT_A_reg;
reg [71:0] DOUT_B_reg;
reg RDACCESS_A_reg;
reg RDACCESS_B_reg;
reg SBITERR_A_reg;
reg SBITERR_B_reg;
reg RDACCESS_A_ecc_reg;
reg RDACCESS_B_ecc_reg;
reg CAS_IN_DBITERR_A_reg;
reg CAS_IN_DBITERR_B_reg;
reg [71:0] CAS_IN_DOUT_A_reg;
reg [71:0] CAS_IN_DOUT_B_reg;
reg CAS_IN_RDACCESS_A_reg;
reg CAS_IN_RDACCESS_B_reg;
reg CAS_IN_SBITERR_A_reg;
reg CAS_IN_SBITERR_B_reg;
reg data_A_enable = 1'b0;
reg data_B_enable = 1'b0;
// data/cas reg
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR || (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR || (REG_CAS_A_BIN == REG_CAS_A_FALSE)) begin
`endif
CAS_IN_DBITERR_A_reg <= 1'b0;
CAS_IN_DOUT_A_reg <= D_INIT;
CAS_IN_RDACCESS_A_reg <= 1'b0;
CAS_IN_SBITERR_A_reg <= 1'b0;
end else begin
if ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) begin
CAS_IN_RDACCESS_A_reg <= CAS_IN_RDACCESS_A_in;
if (CAS_IN_RDACCESS_A_in) begin
CAS_IN_DBITERR_A_reg <= CAS_IN_DBITERR_A_in;
CAS_IN_DOUT_A_reg <= CAS_IN_DOUT_A_in;
CAS_IN_SBITERR_A_reg <= CAS_IN_SBITERR_A_in;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR || (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR || (REG_CAS_B_BIN == REG_CAS_B_FALSE)) begin
`endif
CAS_IN_DBITERR_B_reg <= 1'b0;
CAS_IN_DOUT_B_reg <= D_INIT;
CAS_IN_RDACCESS_B_reg <= 1'b0;
CAS_IN_SBITERR_B_reg <= 1'b0;
end else begin
if ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) begin
CAS_IN_RDACCESS_B_reg <= CAS_IN_RDACCESS_B_in;
if (CAS_IN_RDACCESS_B_in) begin
CAS_IN_DBITERR_B_reg <= CAS_IN_DBITERR_B_in;
CAS_IN_DOUT_B_reg <= CAS_IN_DOUT_B_in;
CAS_IN_SBITERR_B_reg <= CAS_IN_SBITERR_B_in;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR ||
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR ||
`endif
shut_down || SHUTDOWN_in) begin
RDACCESS_A_int = 1'b0;
end else begin
if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin
if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_ECC_CE_A_in) begin
RDACCESS_A_int = RDACCESS_A_ecc_reg;
end else begin
RDACCESS_A_int = 1'b0;
end
end else if (OREG_A_BIN == OREG_A_TRUE) begin
if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_CE_A_in) begin
RDACCESS_A_int = RDACCESS_A_reg;
end else begin
RDACCESS_A_int = 1'b0;
end
end else begin
RDACCESS_A_int = RDACCESS_A_lat;
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR ||
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR ||
`endif
shut_down || SHUTDOWN_in) begin
RDACCESS_B_int = 1'b0;
end else begin
if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin
if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_ECC_CE_B_in) begin
RDACCESS_B_int = RDACCESS_B_ecc_reg;
end else begin
RDACCESS_B_int = 1'b0;
end
end else if (OREG_B_BIN == OREG_B_TRUE) begin
if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_CE_B_in) begin
RDACCESS_B_int = RDACCESS_B_reg;
end else begin
RDACCESS_B_int = 1'b0;
end
end else begin
RDACCESS_B_int = RDACCESS_B_lat;
end
end
end
reg cas_out_mux_sel_a;
reg cas_out_mux_sel_b;
reg cas_out_mux_sel_a_reg;
reg cas_out_mux_sel_b_reg;
always @ (*) begin
if ((CAS_IN_RDACCESS_A_in && REG_CAS_A_BIN == REG_CAS_A_FALSE) ||
(CAS_IN_RDACCESS_A_reg && REG_CAS_A_BIN == REG_CAS_A_TRUE) ||
RDACCESS_A_int) begin
cas_out_mux_sel_a = ~RDACCESS_A_int;
end else begin
cas_out_mux_sel_a = ~cas_out_mux_sel_a_reg;
end
end
always @ (*) begin
if ((CAS_IN_RDACCESS_B_in && (REG_CAS_B_BIN == REG_CAS_B_FALSE)) ||
(CAS_IN_RDACCESS_B_reg && (REG_CAS_B_BIN == REG_CAS_B_TRUE)) ||
RDACCESS_B_int) begin
cas_out_mux_sel_b = ~RDACCESS_B_int;
end else begin
cas_out_mux_sel_b = ~cas_out_mux_sel_b_reg;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR) begin
`endif
cas_out_mux_sel_a_reg <= 1'b0;
end else begin
cas_out_mux_sel_a_reg <= ~cas_out_mux_sel_a;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR) begin
`endif
cas_out_mux_sel_b_reg <= 1'b0;
end else begin
cas_out_mux_sel_b_reg <= ~cas_out_mux_sel_b;
end
end
// data out mux
always @ (*) begin
if (RST_A_async || RST_A_sync || glblGSR) begin
RDACCESS_A_out = 1'b0;
end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
cas_out_mux_sel_a) begin
if (REG_CAS_A_BIN == REG_CAS_A_TRUE) begin
RDACCESS_A_out = CAS_IN_RDACCESS_A_reg;
end else begin
RDACCESS_A_out = CAS_IN_RDACCESS_A_in;
end
end else begin
RDACCESS_A_out = RDACCESS_A_int;
end
end
always @ (*) begin
if (RST_A_async || RST_A_sync || shut_down || glblGSR) begin
DBITERR_A_out = 1'b0;
SBITERR_A_out = 1'b0;
end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
cas_out_mux_sel_a) begin
if (REG_CAS_A_BIN == REG_CAS_A_TRUE) begin
DBITERR_A_out = CAS_IN_DBITERR_A_reg;
SBITERR_A_out = CAS_IN_SBITERR_A_reg;
end else begin
DBITERR_A_out = CAS_IN_DBITERR_A_in;
SBITERR_A_out = CAS_IN_SBITERR_A_in;
end
end else if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin
DBITERR_A_out = DBITERR_A_reg;
SBITERR_A_out = SBITERR_A_reg;
end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
DBITERR_A_out = DBITERR_A_ecc;
SBITERR_A_out = SBITERR_A_ecc;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin
`endif
data_A_enable <= 1'b0;
end else if ((OREG_A_BIN == OREG_A_TRUE) && ram_ce_a && ~ram_we_a) begin
data_A_enable <= 1'b1;
end else if ((OREG_A_BIN == OREG_A_FALSE) && ram_ce_a_int && ~RDB_WR_A_int) begin
data_A_enable <= 1'b1;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin
`endif
data_B_enable <= 1'b0;
end else if ((OREG_B_BIN == OREG_B_TRUE) && ram_ce_b && ~ram_we_b) begin
data_B_enable <= 1'b1;
end else if ((OREG_B_BIN == OREG_B_FALSE) && ram_ce_b_int && ~RDB_WR_B_int) begin
data_B_enable <= 1'b1;
end
end
always @ (posedge CLK_in) begin
if (ram_ce_a && ~ram_we_a && SLEEP_in && ~a_sleep && (OREG_A_BIN == OREG_A_TRUE)) begin
$display("Warning: [Unisim %s-3] At time (%.3f) ns: Port A READ access at ADDR (%h) just prior to SLEEP with SLEEP asserted and OREG_A attribute set to (%s) will result in READ data getting lost. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a, OREG_A_REG);
end else if (ram_ce_a && ram_we_a && SLEEP_in && ~a_sleep) begin
$display("Warning: [Unisim %s-4] At time (%.3f) ns: Port A WRITE access at ADDR (%h) just prior to SLEEP with SLEEP asserted will result in WRITE data getting ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a);
end else if (ram_ce_a_pre && a_sleep && SLEEP_in) begin
$display("Warning: [Unisim %s-5] At time (%.3f) ns: Port A access at ADDR (%h) during SLEEP will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a);
end else if (ram_ce_a_pre && a_sleep && ~SLEEP_in) begin
$display("Warning: [Unisim %s-6] At time (%.3f) ns: Port A access at ADDR (%h) during WAKEUP time will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a);
end
end
always @ (posedge CLK_in) begin
if (ram_ce_b && ~ram_we_b && SLEEP_in && ~a_sleep && (OREG_B_BIN == OREG_B_TRUE)) begin
$display("Warning: [Unisim %s-7] At time (%.3f) ns: Port B READ access at ADDR (%h) just prior to SLEEP with SLEEP asserted and OREG_B attribute set to (%s) will result in READ data getting lost. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b, OREG_B_REG);
end else if (ram_ce_b && ram_we_b && SLEEP_in && ~a_sleep) begin
$display("Warning: [Unisim %s-8] At time (%.3f) ns: Port B WRITE access at ADDR (%h) just prior to SLEEP with SLEEP asserted will result in WRITE data getting ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b);
end else if (ram_ce_b_pre && a_sleep && SLEEP_in) begin
$display("Warning: [Unisim %s-9] At time (%.3f) ns: Port B access at ADDR (%h) during SLEEP will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b);
end else if (ram_ce_b_pre && a_sleep && ~SLEEP_in) begin
$display("Warning: [Unisim %s-10] At time (%.3f) ns: Port B access at ADDR (%h) during WAKEUP time will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b);
end
end
always @ (*) begin
if (RST_A_async || RST_A_sync || glblGSR) begin
DOUT_A_out = D_INIT;
end else if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST)) &&
cas_out_mux_sel_a) begin
if (REG_CAS_A_BIN == REG_CAS_A_TRUE) begin
DOUT_A_out = CAS_IN_DOUT_A_reg;
end else begin
DOUT_A_out = CAS_IN_DOUT_A_in;
end
end else if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin
DOUT_A_out = DOUT_A_reg;
end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
DOUT_A_out = ram_data_a_ecc;
end else if (data_A_enable) begin
if (OREG_A_BIN == OREG_A_TRUE) begin
DOUT_A_out = ram_data_a_reg;
end else begin
DOUT_A_out = ram_data_a_lat;
end
end else begin
DOUT_A_out = D_INIT;
end
end
always @ (*) begin
if (RST_B_async || RST_B_sync || glblGSR) begin
RDACCESS_B_out = 1'b0;
end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
cas_out_mux_sel_b) begin
if (REG_CAS_B_BIN == REG_CAS_B_TRUE) begin
RDACCESS_B_out = CAS_IN_RDACCESS_B_reg;
end else begin
RDACCESS_B_out = CAS_IN_RDACCESS_B_in;
end
end else begin
RDACCESS_B_out = RDACCESS_B_int;
end
end
always @ (*) begin
if (RST_B_async || RST_B_sync || shut_down || glblGSR) begin
DBITERR_B_out = 1'b0;
SBITERR_B_out = 1'b0;
end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
cas_out_mux_sel_b) begin
if (REG_CAS_B_BIN == REG_CAS_B_TRUE) begin
DBITERR_B_out = CAS_IN_DBITERR_B_reg;
SBITERR_B_out = CAS_IN_SBITERR_B_reg;
end else begin
DBITERR_B_out = CAS_IN_DBITERR_B_in;
SBITERR_B_out = CAS_IN_SBITERR_B_in;
end
end else if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin
DBITERR_B_out = DBITERR_B_reg;
SBITERR_B_out = SBITERR_B_reg;
end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
DBITERR_B_out = DBITERR_B_ecc;
SBITERR_B_out = SBITERR_B_ecc;
end
end
always @ (*) begin
if (RST_B_async || RST_B_sync || glblGSR) begin
DOUT_B_out = D_INIT;
end else if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST)) &&
cas_out_mux_sel_b) begin
if (REG_CAS_B_BIN == REG_CAS_B_TRUE) begin
DOUT_B_out = CAS_IN_DOUT_B_reg;
end else begin
DOUT_B_out = CAS_IN_DOUT_B_in;
end
end else if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin
DOUT_B_out = DOUT_B_reg;
end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
DOUT_B_out = ram_data_b_ecc;
end else if (data_B_enable) begin
if (OREG_B_BIN == OREG_B_TRUE) begin
DOUT_B_out = ram_data_b_reg;
end else begin
DOUT_B_out = ram_data_b_lat;
end
end else begin
DOUT_B_out = D_INIT;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`endif
DBITERR_A_reg <= 1'b0;
SBITERR_A_reg <= 1'b0;
end else if ((~a_sleep && ~shut_down && data_A_enable) &&
(((OREG_A_BIN == OREG_A_TRUE) && (RDACCESS_A_reg || RDACCESS_A_ecc_reg)) ||
((OREG_A_BIN == OREG_A_FALSE) && (RDACCESS_A_lat || RDACCESS_A_ecc_reg)))) begin
if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_ECC_CE_A_in) begin
DBITERR_A_reg <= DBITERR_A_ecc;
SBITERR_A_reg <= SBITERR_A_ecc;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`endif
DOUT_A_reg <= D_INIT;
end else if (~shut_down && data_A_enable) begin
if (USE_EXT_CE_A_BIN == USE_EXT_CE_A_TRUE) begin
if (OREG_ECC_CE_A_in) begin
if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
DOUT_A_reg <= ram_data_a_ecc;
end else if (OREG_A_BIN == OREG_A_TRUE) begin
DOUT_A_reg <= ram_data_a_reg;
end else begin
DOUT_A_reg <= ram_data_a_lat;
end
end
end else if (((OREG_A_BIN == OREG_A_TRUE) && (RDACCESS_A_reg || RDACCESS_A_ecc_reg)) ||
((OREG_A_BIN == OREG_A_FALSE) && (RDACCESS_A_lat || RDACCESS_A_ecc_reg))) begin
if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
DOUT_A_reg <= ram_data_a_ecc;
end else if (OREG_A_BIN == OREG_A_TRUE) begin
DOUT_A_reg <= ram_data_a_reg;
end else begin
DOUT_A_reg <= ram_data_a_lat;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`endif
RDACCESS_A_ecc_reg <= 1'b0;
end else begin
if (OREG_A_BIN == OREG_A_TRUE) begin
if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_CE_A_in) begin
RDACCESS_A_ecc_reg <= RDACCESS_A_reg;
end
end else begin
RDACCESS_A_ecc_reg <= RDACCESS_A_lat;
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`endif
DBITERR_B_reg <= 1'b0;
SBITERR_B_reg <= 1'b0;
end else if ((~a_sleep && ~shut_down && data_B_enable) &&
(((OREG_B_BIN == OREG_B_TRUE) && (RDACCESS_B_reg || RDACCESS_B_ecc_reg)) ||
((OREG_B_BIN == OREG_B_FALSE) && (RDACCESS_B_lat || RDACCESS_B_ecc_reg)))) begin
if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_ECC_CE_B_in) begin
DBITERR_B_reg <= DBITERR_B_ecc;
SBITERR_B_reg <= SBITERR_B_ecc;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`endif
DOUT_B_reg <= D_INIT;
end else if (~shut_down && data_B_enable) begin
if (USE_EXT_CE_B_BIN == USE_EXT_CE_B_TRUE) begin
if (OREG_ECC_CE_B_in) begin
if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
DOUT_B_reg <= ram_data_b_ecc;
end else if (OREG_B_BIN == OREG_B_TRUE) begin
DOUT_B_reg <= ram_data_b_reg;
end else begin
DOUT_B_reg <= ram_data_b_lat;
end
end
end else if (((OREG_B_BIN == OREG_B_TRUE) && (RDACCESS_B_reg || RDACCESS_B_ecc_reg)) ||
((OREG_B_BIN == OREG_B_FALSE) && (RDACCESS_B_lat || RDACCESS_B_ecc_reg))) begin
if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
DOUT_B_reg <= ram_data_b_ecc;
end else if (OREG_B_BIN == OREG_B_TRUE) begin
DOUT_B_reg <= ram_data_b_reg;
end else begin
DOUT_B_reg <= ram_data_b_lat;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`endif
RDACCESS_B_ecc_reg <= 1'b0;
end else begin
if (OREG_B_BIN == OREG_B_TRUE) begin
if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_CE_B_in) begin
RDACCESS_B_ecc_reg <= RDACCESS_B_reg;
end
end else begin
RDACCESS_B_ecc_reg <= RDACCESS_B_lat;
end
end
end
// ram oreg
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || shut_down || a_sleep || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or shut_down or glblGSR) begin
if (RST_A_in || shut_down || a_sleep || glblGSR) begin
`endif
RDACCESS_A_reg <= 1'b0;
end else begin
RDACCESS_A_reg <= RDACCESS_A_lat;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_A_BIN == OREG_A_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or shut_down or glblGSR) begin
if (RST_A_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_A_BIN == OREG_A_FALSE)) begin
`endif
ram_data_a_reg <= D_INIT;
end else if (USE_EXT_CE_A_BIN == USE_EXT_CE_A_TRUE) begin
if (OREG_CE_A_in) begin
ram_data_a_reg = ram_data_a_lat;
end
end else if (ram_ce_a_int || RDACCESS_A_reg) begin
ram_data_a_reg = ram_data_a_lat;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || shut_down || a_sleep || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or shut_down or glblGSR) begin
if (RST_B_in || shut_down || a_sleep || glblGSR) begin
`endif
RDACCESS_B_reg <= 1'b0;
end else begin
RDACCESS_B_reg <= RDACCESS_B_lat;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_B_BIN == OREG_B_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or shut_down or glblGSR) begin
if (RST_B_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_B_BIN == OREG_B_FALSE)) begin
`endif
ram_data_b_reg <= D_INIT;
end else if (USE_EXT_CE_B_BIN == USE_EXT_CE_B_TRUE) begin
if (OREG_CE_B_in) begin
ram_data_b_reg = ram_data_b_lat;
end
end else if (ram_ce_b_int || RDACCESS_B_reg) begin
ram_data_b_reg = ram_data_b_lat;
end
end
reg [15:1] ram_ce_a_fifo_in = 15'b0;
always @ (*) begin
ram_ce_a_fifo_in = 15'b0;
ram_ce_a_fifo_in[AUTO_SLEEP_LATENCY_BIN] = &(~(ADDR_A_int[22:12] ^ SELF_ADDR_A_REG) | SELF_MASK_A_REG) && EN_A_int;
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin
ram_ce_a_fifo <= 15'b0;
end else begin
ram_ce_a_fifo <= {1'b0, ram_ce_a_fifo[15:2]} | ram_ce_a_fifo_in;
end
end
always @ (*) begin
if (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE) begin
ram_ce_a_pre = &(~(ADDR_A_int[22:12] ^ SELF_ADDR_A_REG) | SELF_MASK_A_REG) && EN_A_int;
end else begin
ram_ce_a_pre = ram_ce_a_fifo[1];
end
end
always @ (*) begin
if (a_sleep || SLEEP_in || auto_sleep) begin
ram_ce_a_int = 1'b0;
end else begin
ram_ce_a_int = ram_ce_a_pre;
end
end
reg [15:1] ram_ce_b_fifo_in = 15'b0;
always @ (*) begin
ram_ce_b_fifo_in = 15'b0;
ram_ce_b_fifo_in[AUTO_SLEEP_LATENCY_BIN] = &(~(ADDR_B_int[22:12] ^ SELF_ADDR_B_REG) | SELF_MASK_B_REG) && EN_B_int;
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin
ram_ce_b_fifo <= 15'b0;
end else begin
ram_ce_b_fifo <= {1'b0, ram_ce_b_fifo[15:2]} | ram_ce_b_fifo_in;
end
end
always @ (*) begin
if (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE) begin
ram_ce_b_pre = &(~(ADDR_B_int[22:12] ^ SELF_ADDR_B_REG) | SELF_MASK_B_REG) && EN_B_int;
end else begin
ram_ce_b_pre = ram_ce_b_fifo[1];
end
end
always @ (*) begin
if (a_sleep || SLEEP_in || auto_sleep) begin
ram_ce_b_int = 1'b0;
end else begin
ram_ce_b_int = ram_ce_b_pre;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || ~RDB_WR_A_int || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_bwe_a <= 72'h00;
end else if (ram_ce_a_int) begin
if (EN_ECC_WR_A_BIN == EN_ECC_WR_A_TRUE) begin
ram_bwe_a <= 72'hFFFFFFFFFFFFFFFFFF;
end else if (BWE_MODE_A_BIN == BWE_MODE_A_PARITY_INTERLEAVED) begin
ram_bwe_a <= {BWE_A_int[7:0],
{8{BWE_A_int[7]}}, {8{BWE_A_int[6]}}, {8{BWE_A_int[5]}}, {8{BWE_A_int[4]}},
{8{BWE_A_int[3]}}, {8{BWE_A_int[2]}}, {8{BWE_A_int[1]}}, {8{BWE_A_int[0]}}};
end else begin
ram_bwe_a <= {{8{BWE_A_int[8]}},
{8{BWE_A_int[7]}}, {8{BWE_A_int[6]}}, {8{BWE_A_int[5]}}, {8{BWE_A_int[4]}},
{8{BWE_A_int[3]}}, {8{BWE_A_int[2]}}, {8{BWE_A_int[1]}}, {8{BWE_A_int[0]}}};
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || ~RDB_WR_B_int || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_bwe_b <= 72'b0;
end else if (ram_ce_b_int) begin
if (EN_ECC_WR_B_BIN == EN_ECC_WR_B_TRUE) begin
ram_bwe_b <= 72'hFFFFFFFFFFFFFFFFFF;
end else if (BWE_MODE_B_BIN == BWE_MODE_B_PARITY_INTERLEAVED) begin
ram_bwe_b <= {BWE_B_int[7:0],
{8{BWE_B_int[7]}}, {8{BWE_B_int[6]}}, {8{BWE_B_int[5]}}, {8{BWE_B_int[4]}},
{8{BWE_B_int[3]}}, {8{BWE_B_int[2]}}, {8{BWE_B_int[1]}}, {8{BWE_B_int[0]}}};
end else begin
ram_bwe_b <= {{8{BWE_B_int[8]}},
{8{BWE_B_int[7]}}, {8{BWE_B_int[6]}}, {8{BWE_B_int[5]}}, {8{BWE_B_int[4]}},
{8{BWE_B_int[3]}}, {8{BWE_B_int[2]}}, {8{BWE_B_int[1]}}, {8{BWE_B_int[0]}}};
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_addr_a <= 12'b0;
end else if (ram_ce_a_int) begin
ram_addr_a <= ADDR_A_int[11:0];
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_addr_b <= 12'b0;
end else if (ram_ce_b_int) begin
ram_addr_b <= ADDR_B_int[11:0];
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (glblGSR || (RST_A_async || RST_A_in) || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (glblGSR || RST_A_in || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
`endif
ram_ce_a <= 1'b0;
end else begin
ram_ce_a <= ram_ce_a_int;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (glblGSR || (RST_B_async || RST_B_in) || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (glblGSR || RST_B_in || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
`endif
ram_ce_b <= 1'b0;
end else begin
ram_ce_b <= ram_ce_b_int;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in || ~ram_ce_a_int) begin
ram_we_a <= 1'b0;
end else begin
ram_we_a <= RDB_WR_A_int;
if (RDB_WR_A_int) ram_we_a_event <= ~ram_we_a_event;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in || ~ram_ce_b_int) begin
ram_we_b <= 1'b0;
end else begin
ram_we_b <= RDB_WR_B_int;
if (RDB_WR_B_int) ram_we_b_event <= ~ram_we_b_event;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_data_a <= D_INIT;
end else if (RDB_WR_A_int && ram_ce_a_int) begin
if (EN_ECC_WR_A_BIN == EN_ECC_WR_A_TRUE) begin
ram_data_a[63:0] <= {DIN_A_int[63],
DIN_A_int[62] ^ (INJECT_DBITERR_A_int),
DIN_A_int[61:31],
DIN_A_int[30] ^ (INJECT_DBITERR_A_int || INJECT_SBITERR_A_int),
DIN_A_int[29:0]};
ram_data_a[71:64] <= fn_ecc(encode, DIN_A_int[63:0], DIN_A_int[71:64]);
end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
ram_data_a[63:0] <= {DIN_A_int[63],
DIN_A_int[62] ^ (INJECT_DBITERR_A_int),
DIN_A_int[61:31],
DIN_A_int[30] ^ (INJECT_DBITERR_A_int || INJECT_SBITERR_A_int),
DIN_A_int[29:0]};
ram_data_a[71:64] <= DIN_A_int[71:64];
end else begin
ram_data_a <= DIN_A_int;
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_data_b <= D_INIT;
end else if (RDB_WR_B_int && ram_ce_b_int) begin
if (EN_ECC_WR_B_BIN == EN_ECC_WR_B_TRUE) begin
ram_data_b[63:0] <= {DIN_B_int[63],
DIN_B_int[62] ^ (INJECT_DBITERR_B_int),
DIN_B_int[61:31],
DIN_B_int[30] ^ (INJECT_DBITERR_B_int || INJECT_SBITERR_B_int),
DIN_B_int[29:0]};
ram_data_b[71:64] <= fn_ecc(encode, DIN_B_int[63:0], DIN_B_int[71:64]);
end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
ram_data_b[63:0] <= {DIN_B_int[63],
DIN_B_int[62] ^ (INJECT_DBITERR_B_int),
DIN_B_int[61:31],
DIN_B_int[30] ^ (INJECT_DBITERR_B_int || INJECT_SBITERR_B_int),
DIN_B_int[29:0]};
ram_data_b[71:64] <= DIN_B_int[71:64];
end else begin
ram_data_b <= DIN_B_int;
end
end
end
// ram
always @ (*) begin
if ((auto_sleep || SLEEP_in || SHUTDOWN_in || DEEPSLEEP_in) ||
(((OREG_A_BIN == OREG_A_TRUE) || (OREG_ECC_A_BIN == OREG_ECC_A_TRUE )) &&
(a_sleep || shut_down)))begin
RDACCESS_A_lat <= 1'b0;
end else if ((ram_ce_a_int === 1'b1) && (RDB_WR_A_int === 1'b0)) begin
RDACCESS_A_lat <= 1'b1;
end else begin
RDACCESS_A_lat <= 1'b0;
end
end
always @ (*) begin
if ((auto_sleep || SLEEP_in || SHUTDOWN_in || DEEPSLEEP_in) ||
(((OREG_B_BIN == OREG_B_TRUE) || (OREG_ECC_B_BIN == OREG_ECC_B_TRUE )) &&
(a_sleep || shut_down)))begin
RDACCESS_B_lat <= 1'b0;
end else if ((ram_ce_b_int === 1'b1) && (RDB_WR_B_int === 1'b0)) begin
RDACCESS_B_lat <= 1'b1;
end else begin
RDACCESS_B_lat <= 1'b0;
end
end
`ifndef XIL_XECLIB
// always @ (posedge INIT_RAM or posedge glblGSR) begin
always @ (posedge INIT_RAM) begin
for (wa=0;wa<mem_depth;wa=wa+1) begin
mem[wa] <= D_INIT;
end
end
always @ (posedge shut_down) begin
for (wa=0;wa<mem_depth;wa=wa+1) begin
mem[wa] <= D_UNDEF;
end
end
`endif
always @ (*) begin
if (RST_A_sync || RST_A_async || glblGSR || a_sleep || shut_down) begin
ram_data_a_lat = D_INIT;
end else if (ram_ce_a && ~ram_we_a) begin
ram_data_a_lat = ram_data_a_out;
end
end
always @ (*) begin
if (RST_B_sync || RST_B_async || glblGSR || a_sleep || shut_down) begin
ram_data_b_lat = D_INIT;
end else if (ram_ce_b && ~ram_we_b) begin
ram_data_b_lat = ram_data_b_out;
end
end
`ifdef XIL_XECLIB
always @ (posedge RST_A_async or posedge RST_B_async or posedge CLK_in) begin
`else
always @ (ram_we_a or ram_we_b or ram_ce_a or ram_ce_b or a_sleep or shut_down or ram_addr_a or ram_addr_b or ram_data_a or ram_data_b or ram_bwe_a or ram_bwe_b or ram_we_a_event or ram_we_b_event or posedge RST_A_async or posedge RST_B_async or posedge RST_A_sync or posedge RST_B_sync or glblGSR) begin
`endif
if (RST_A_async || RST_A_sync || shut_down || glblGSR) begin
ram_data_a_out = D_INIT;
end
if (ram_we_a && ~shut_down && ~a_sleep && ~glblGSR) begin
mem [ram_addr_a] = (ram_data_a & ram_bwe_a) | (mem [ram_addr_a] & ~ram_bwe_a);
end
if (ram_ce_a && ~ram_we_a && ~RST_A_in && ~shut_down && ~a_sleep && ~glblGSR) begin
ram_data_a_out = mem[ram_addr_a];
end
if (RST_B_async || RST_B_sync || shut_down || glblGSR) begin
ram_data_b_out = D_INIT;
end
if (ram_we_b && ~shut_down && ~a_sleep && ~glblGSR) begin
mem [ram_addr_b] = (ram_data_b & ram_bwe_b) | (mem [ram_addr_b] & ~ram_bwe_b);
end
if (ram_ce_b && ~ram_we_b && ~RST_B_in && ~shut_down && ~a_sleep && ~glblGSR) begin
ram_data_b_out = mem[ram_addr_b];
end
end
// ecc correction
task ecc_cor;
output [71:0] data_cor; output sbiterr; output dbiterr;
input [71:0] data;
reg [7:0] synd_rd; reg [7:0] synd_ecc; reg decode;
begin
decode = 1'b0;
synd_rd = fn_ecc(decode, data[63:0], data[71:64]);
synd_ecc = synd_rd ^ data[71:64];
sbiterr = (|synd_ecc && synd_ecc[7]);
dbiterr = (|synd_ecc && ~synd_ecc[7]);
if (sbiterr) begin
data_cor = fn_cor_bit(synd_ecc[6:0],data[63:0],data[71:64]);
end else begin
data_cor = data;
end
end
endtask
always @ (*) begin
if (a_sleep || shut_down || glblGSR || (EN_ECC_RD_A_BIN == EN_ECC_RD_A_FALSE)) begin
ram_data_a_ecc <= D_INIT;
end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
if (OREG_A_BIN == OREG_A_TRUE) begin
ecc_cor(ram_data_a_ecc, SBITERR_A_ecc, DBITERR_A_ecc, ram_data_a_reg);
end else begin
ecc_cor(ram_data_a_ecc, SBITERR_A_ecc, DBITERR_A_ecc, ram_data_a_lat);
end
end
end
always @ (*) begin
if (a_sleep || shut_down || glblGSR || (EN_ECC_RD_B_BIN == EN_ECC_RD_B_FALSE)) begin
ram_data_b_ecc <= D_INIT;
end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
if (OREG_B_BIN == OREG_B_TRUE) begin
ecc_cor(ram_data_b_ecc, SBITERR_B_ecc, DBITERR_B_ecc, ram_data_b_reg);
end else begin
ecc_cor(ram_data_b_ecc, SBITERR_B_ecc, DBITERR_B_ecc, ram_data_b_lat);
end
end
end
// sleep, deepsleep, shutdown
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR) begin
wake_count <= 0;
end else if (((wake_count > 0) &&
(~(auto_sleep || SLEEP_in || DEEPSLEEP_in || SHUTDOWN_in))) ||
(~(SHUTDOWN_in || DEEPSLEEP_in) && (wake_count > 2)) ||
(~SHUTDOWN_in && (wake_count > 3))) begin
wake_count <= wake_count - 1;
end else if (SHUTDOWN_in) begin
wake_count <= 9;
end else if (DEEPSLEEP_in && (wake_count <= 3)) begin
wake_count <= 3;
end else if (SLEEP_in && (wake_count <= 2)) begin
wake_count <= 2;
end else if (auto_sleep && (wake_count <= 1)) begin
wake_count <= 1;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (~auto_sleep && wake_count == 1)) begin
a_sleep <= 1'b0;
end else if (DEEPSLEEP_in || SLEEP_in || auto_sleep) begin
a_sleep <= 1'b1;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (wake_count == 1)) begin
shut_down <= 1'b0;
end else if (SHUTDOWN_in) begin
shut_down <= 1'b1;
end
end
assign auto_sleep = auto_sleep_A && auto_sleep_B && ~auto_wake_up_A && ~auto_wake_up_B;
assign auto_wake_up_A = ram_ce_a_fifo[3];
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin
auto_sleep_A <= 1'b0;
end else if (auto_wake_up_A && auto_sleep_A) begin
auto_sleep_A <= 1'b0;
end else if (~|ram_ce_a_fifo && ~auto_sleep_A) begin
auto_sleep_A <= 1'b1;
end
end
assign auto_wake_up_B = ram_ce_b_fifo[3];
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin
auto_sleep_B <= 1'b0;
end else if (auto_wake_up_B && auto_sleep_B) begin
auto_sleep_B <= 1'b0;
end else if (~|ram_ce_b_fifo && ~auto_sleep_B) begin
auto_sleep_B <= 1'b1;
end
end
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
wire clk_en_n;
wire clk_en_p;
assign clk_en_n = IS_CLK_INVERTED_REG;
assign clk_en_p = ~IS_CLK_INVERTED_REG;
`endif
specify
(ADDR_A *> CAS_OUT_ADDR_A) = (0:0:0, 0:0:0);
(ADDR_B *> CAS_OUT_ADDR_B) = (0:0:0, 0:0:0);
(BWE_A *> CAS_OUT_BWE_A) = (0:0:0, 0:0:0);
(BWE_B *> CAS_OUT_BWE_B) = (0:0:0, 0:0:0);
(CAS_IN_ADDR_A *> CAS_OUT_ADDR_A) = (0:0:0, 0:0:0);
(CAS_IN_ADDR_B *> CAS_OUT_ADDR_B) = (0:0:0, 0:0:0);
(CAS_IN_BWE_A *> CAS_OUT_BWE_A) = (0:0:0, 0:0:0);
(CAS_IN_BWE_B *> CAS_OUT_BWE_B) = (0:0:0, 0:0:0);
(CAS_IN_DBITERR_A => CAS_OUT_DBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_DBITERR_A => DBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_DBITERR_B => CAS_OUT_DBITERR_B) = (0:0:0, 0:0:0);
(CAS_IN_DBITERR_B => DBITERR_B) = (0:0:0, 0:0:0);
(CAS_IN_DIN_A *> CAS_OUT_DIN_A) = (0:0:0, 0:0:0);
(CAS_IN_DIN_B *> CAS_OUT_DIN_B) = (0:0:0, 0:0:0);
(CAS_IN_DOUT_A *> CAS_OUT_DOUT_A) = (0:0:0, 0:0:0);
(CAS_IN_DOUT_A *> DOUT_A) = (0:0:0, 0:0:0);
(CAS_IN_DOUT_B *> CAS_OUT_DOUT_B) = (0:0:0, 0:0:0);
(CAS_IN_DOUT_B *> DOUT_B) = (0:0:0, 0:0:0);
(CAS_IN_EN_A => CAS_OUT_EN_A) = (0:0:0, 0:0:0);
(CAS_IN_EN_B => CAS_OUT_EN_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A *> CAS_OUT_DOUT_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A *> DOUT_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A => CAS_OUT_DBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A => CAS_OUT_RDACCESS_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A => CAS_OUT_SBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A => DBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A => RDACCESS_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_A => SBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B *> CAS_OUT_DOUT_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B *> DOUT_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B => CAS_OUT_DBITERR_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B => CAS_OUT_RDACCESS_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B => CAS_OUT_SBITERR_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B => DBITERR_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B => RDACCESS_B) = (0:0:0, 0:0:0);
(CAS_IN_RDACCESS_B => SBITERR_B) = (0:0:0, 0:0:0);
(CAS_IN_RDB_WR_A => CAS_OUT_RDB_WR_A) = (0:0:0, 0:0:0);
(CAS_IN_RDB_WR_B => CAS_OUT_RDB_WR_B) = (0:0:0, 0:0:0);
(CAS_IN_SBITERR_A => CAS_OUT_SBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_SBITERR_A => SBITERR_A) = (0:0:0, 0:0:0);
(CAS_IN_SBITERR_B => CAS_OUT_SBITERR_B) = (0:0:0, 0:0:0);
(CAS_IN_SBITERR_B => SBITERR_B) = (0:0:0, 0:0:0);
(CLK *> CAS_OUT_ADDR_A) = (100:100:100, 100:100:100);
(CLK *> CAS_OUT_ADDR_B) = (100:100:100, 100:100:100);
(CLK *> CAS_OUT_BWE_A) = (100:100:100, 100:100:100);
(CLK *> CAS_OUT_BWE_B) = (100:100:100, 100:100:100);
(CLK *> CAS_OUT_DIN_A) = (100:100:100, 100:100:100);
(CLK *> CAS_OUT_DIN_B) = (100:100:100, 100:100:100);
(CLK *> CAS_OUT_DOUT_A) = (100:100:100, 100:100:100);
(CLK *> CAS_OUT_DOUT_B) = (100:100:100, 100:100:100);
(CLK *> DOUT_A) = (100:100:100, 100:100:100);
(CLK *> DOUT_B) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_DBITERR_A) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_DBITERR_B) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_EN_A) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_EN_B) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_RDACCESS_A) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_RDACCESS_B) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_RDB_WR_A) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_RDB_WR_B) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_SBITERR_A) = (100:100:100, 100:100:100);
(CLK => CAS_OUT_SBITERR_B) = (100:100:100, 100:100:100);
(CLK => DBITERR_A) = (100:100:100, 100:100:100);
(CLK => DBITERR_B) = (100:100:100, 100:100:100);
(CLK => RDACCESS_A) = (100:100:100, 100:100:100);
(CLK => RDACCESS_B) = (100:100:100, 100:100:100);
(CLK => SBITERR_A) = (100:100:100, 100:100:100);
(CLK => SBITERR_B) = (100:100:100, 100:100:100);
(DIN_A *> CAS_OUT_DIN_A) = (0:0:0, 0:0:0);
(DIN_B *> CAS_OUT_DIN_B) = (0:0:0, 0:0:0);
(EN_A => CAS_OUT_EN_A) = (0:0:0, 0:0:0);
(EN_B => CAS_OUT_EN_B) = (0:0:0, 0:0:0);
(RDB_WR_A => CAS_OUT_RDB_WR_A) = (0:0:0, 0:0:0);
(RDB_WR_B => CAS_OUT_RDB_WR_B) = (0:0:0, 0:0:0);
(negedge RST_A *> (CAS_OUT_DOUT_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A *> (DOUT_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A => (CAS_OUT_DBITERR_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A => (CAS_OUT_RDACCESS_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A => (CAS_OUT_SBITERR_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A => (DBITERR_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A => (RDACCESS_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A => (SBITERR_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B *> (CAS_OUT_DOUT_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B *> (DOUT_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B => (CAS_OUT_DBITERR_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B => (CAS_OUT_RDACCESS_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B => (CAS_OUT_SBITERR_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B => (DBITERR_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B => (RDACCESS_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B => (SBITERR_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A *> (CAS_OUT_DOUT_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A *> (DOUT_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A => (CAS_OUT_DBITERR_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A => (CAS_OUT_RDACCESS_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A => (CAS_OUT_SBITERR_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A => (DBITERR_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A => (RDACCESS_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A => (SBITERR_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B *> (CAS_OUT_DOUT_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B *> (DOUT_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B => (CAS_OUT_DBITERR_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B => (CAS_OUT_RDACCESS_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B => (CAS_OUT_SBITERR_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B => (DBITERR_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B => (RDACCESS_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B => (SBITERR_B +: 0)) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$recrem (negedge RST_A, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_A_delay, CLK_delay);
$recrem (negedge RST_A, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_A_delay, CLK_delay);
$recrem (negedge RST_B, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_B_delay, CLK_delay);
$recrem (negedge RST_B, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_B_delay, CLK_delay);
$recrem (posedge RST_A, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_A_delay, CLK_delay);
$recrem (posedge RST_A, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_A_delay, CLK_delay);
$recrem (posedge RST_B, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_B_delay, CLK_delay);
$recrem (posedge RST_B, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_B_delay, CLK_delay);
$setuphold (negedge CLK, negedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_A_delay);
$setuphold (negedge CLK, negedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_B_delay);
$setuphold (negedge CLK, negedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_A_delay);
$setuphold (negedge CLK, negedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_B_delay);
$setuphold (negedge CLK, negedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_A_delay);
$setuphold (negedge CLK, negedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_B_delay);
$setuphold (negedge CLK, negedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_A_delay);
$setuphold (negedge CLK, negedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_B_delay);
$setuphold (negedge CLK, negedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_A_delay);
$setuphold (negedge CLK, negedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_B_delay);
$setuphold (negedge CLK, negedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_A_delay);
$setuphold (negedge CLK, negedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_B_delay);
$setuphold (negedge CLK, negedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_A_delay);
$setuphold (negedge CLK, negedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_B_delay);
$setuphold (negedge CLK, negedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_A_delay);
$setuphold (negedge CLK, negedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_B_delay);
$setuphold (negedge CLK, negedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_A_delay);
$setuphold (negedge CLK, negedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_B_delay);
$setuphold (negedge CLK, negedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_A_delay);
$setuphold (negedge CLK, negedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_B_delay);
$setuphold (negedge CLK, negedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_A_delay);
$setuphold (negedge CLK, negedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_B_delay);
$setuphold (negedge CLK, negedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, SLEEP_delay);
$setuphold (negedge CLK, posedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_A_delay);
$setuphold (negedge CLK, posedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_B_delay);
$setuphold (negedge CLK, posedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_A_delay);
$setuphold (negedge CLK, posedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_ADDR_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_BWE_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DBITERR_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DIN_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_DOUT_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_EN_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDACCESS_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_RDB_WR_B_delay);
$setuphold (negedge CLK, posedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_A_delay);
$setuphold (negedge CLK, posedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CAS_IN_SBITERR_B_delay);
$setuphold (negedge CLK, posedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_A_delay);
$setuphold (negedge CLK, posedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_B_delay);
$setuphold (negedge CLK, posedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_A_delay);
$setuphold (negedge CLK, posedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_B_delay);
$setuphold (negedge CLK, posedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_A_delay);
$setuphold (negedge CLK, posedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_B_delay);
$setuphold (negedge CLK, posedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_A_delay);
$setuphold (negedge CLK, posedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_B_delay);
$setuphold (negedge CLK, posedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_A_delay);
$setuphold (negedge CLK, posedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_B_delay);
$setuphold (negedge CLK, posedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_A_delay);
$setuphold (negedge CLK, posedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_B_delay);
$setuphold (negedge CLK, posedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_A_delay);
$setuphold (negedge CLK, posedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_B_delay);
$setuphold (negedge CLK, posedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_A_delay);
$setuphold (negedge CLK, posedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_B_delay);
$setuphold (negedge CLK, posedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, SLEEP_delay);
$setuphold (posedge CLK, negedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_A_delay);
$setuphold (posedge CLK, negedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_B_delay);
$setuphold (posedge CLK, negedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_A_delay);
$setuphold (posedge CLK, negedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_B_delay);
$setuphold (posedge CLK, negedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_A_delay);
$setuphold (posedge CLK, negedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_B_delay);
$setuphold (posedge CLK, negedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_A_delay);
$setuphold (posedge CLK, negedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_B_delay);
$setuphold (posedge CLK, negedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_A_delay);
$setuphold (posedge CLK, negedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_B_delay);
$setuphold (posedge CLK, negedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_A_delay);
$setuphold (posedge CLK, negedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_B_delay);
$setuphold (posedge CLK, negedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_A_delay);
$setuphold (posedge CLK, negedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_B_delay);
$setuphold (posedge CLK, negedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_A_delay);
$setuphold (posedge CLK, negedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_B_delay);
$setuphold (posedge CLK, negedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_A_delay);
$setuphold (posedge CLK, negedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_B_delay);
$setuphold (posedge CLK, negedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_A_delay);
$setuphold (posedge CLK, negedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_B_delay);
$setuphold (posedge CLK, negedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_A_delay);
$setuphold (posedge CLK, negedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_B_delay);
$setuphold (posedge CLK, negedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, SLEEP_delay);
$setuphold (posedge CLK, posedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_A_delay);
$setuphold (posedge CLK, posedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_B_delay);
$setuphold (posedge CLK, posedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_A_delay);
$setuphold (posedge CLK, posedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_ADDR_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_BWE_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DBITERR_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DIN_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_DOUT_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_DOUT_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_DOUT_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_EN_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_RDACCESS_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_RDACCESS_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDACCESS_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_RDB_WR_B_delay);
$setuphold (posedge CLK, posedge CAS_IN_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_A_delay);
$setuphold (posedge CLK, posedge CAS_IN_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CAS_IN_SBITERR_B_delay);
$setuphold (posedge CLK, posedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_A_delay);
$setuphold (posedge CLK, posedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_B_delay);
$setuphold (posedge CLK, posedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_A_delay);
$setuphold (posedge CLK, posedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_B_delay);
$setuphold (posedge CLK, posedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_A_delay);
$setuphold (posedge CLK, posedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_B_delay);
$setuphold (posedge CLK, posedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_A_delay);
$setuphold (posedge CLK, posedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_B_delay);
$setuphold (posedge CLK, posedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_A_delay);
$setuphold (posedge CLK, posedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_B_delay);
$setuphold (posedge CLK, posedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_A_delay);
$setuphold (posedge CLK, posedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_B_delay);
$setuphold (posedge CLK, posedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_A_delay);
$setuphold (posedge CLK, posedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_B_delay);
$setuphold (posedge CLK, posedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_A_delay);
$setuphold (posedge CLK, posedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_B_delay);
$setuphold (posedge CLK, posedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, SLEEP_delay);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (negedge RST_A, 0:0:0, 0, notifier);
$width (negedge RST_B, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (posedge RST_A, 0:0:0, 0, notifier);
$width (posedge RST_B, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_pm_even.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_pm_even(/*AUTOARG*/
// Outputs
arbpc0_pcxdp_grant_pa, arbpc0_pcxdp_q0_hold_pa_l,
arbpc0_pcxdp_qsel0_pa, arbpc0_pcxdp_qsel1_pa_l,
arbpc0_pcxdp_shift_px, arbpc2_pcxdp_grant_pa,
arbpc2_pcxdp_q0_hold_pa_l, arbpc2_pcxdp_qsel0_pa,
arbpc2_pcxdp_qsel1_pa_l, arbpc2_pcxdp_shift_px,
// Inputs
arbpc0_pcxdp_grant_arbbf_pa, arbpc0_pcxdp_q0_hold_arbbf_pa_l,
arbpc0_pcxdp_qsel0_arbbf_pa, arbpc0_pcxdp_qsel1_arbbf_pa_l,
arbpc0_pcxdp_shift_arbbf_px, arbpc2_pcxdp_grant_arbbf_pa,
arbpc2_pcxdp_q0_hold_arbbf_pa_l, arbpc2_pcxdp_qsel0_arbbf_pa,
arbpc2_pcxdp_qsel1_arbbf_pa_l, arbpc2_pcxdp_shift_arbbf_px
);
output arbpc0_pcxdp_grant_pa ;
output arbpc0_pcxdp_q0_hold_pa_l ;
output arbpc0_pcxdp_qsel0_pa ;
output arbpc0_pcxdp_qsel1_pa_l ;
output arbpc0_pcxdp_shift_px ;
output arbpc2_pcxdp_grant_pa ;
output arbpc2_pcxdp_q0_hold_pa_l ;
output arbpc2_pcxdp_qsel0_pa ;
output arbpc2_pcxdp_qsel1_pa_l ;
output arbpc2_pcxdp_shift_px ;
input arbpc0_pcxdp_grant_arbbf_pa;
input arbpc0_pcxdp_q0_hold_arbbf_pa_l;
input arbpc0_pcxdp_qsel0_arbbf_pa;
input arbpc0_pcxdp_qsel1_arbbf_pa_l;
input arbpc0_pcxdp_shift_arbbf_px;
input arbpc2_pcxdp_grant_arbbf_pa;
input arbpc2_pcxdp_q0_hold_arbbf_pa_l;
input arbpc2_pcxdp_qsel0_arbbf_pa;
input arbpc2_pcxdp_qsel1_arbbf_pa_l;
input arbpc2_pcxdp_shift_arbbf_px;
assign arbpc0_pcxdp_grant_pa = arbpc0_pcxdp_grant_arbbf_pa;
assign arbpc0_pcxdp_q0_hold_pa_l = arbpc0_pcxdp_q0_hold_arbbf_pa_l;
assign arbpc0_pcxdp_qsel0_pa = arbpc0_pcxdp_qsel0_arbbf_pa;
assign arbpc0_pcxdp_qsel1_pa_l = arbpc0_pcxdp_qsel1_arbbf_pa_l;
assign arbpc0_pcxdp_shift_px = arbpc0_pcxdp_shift_arbbf_px;
assign arbpc2_pcxdp_grant_pa = arbpc2_pcxdp_grant_arbbf_pa;
assign arbpc2_pcxdp_q0_hold_pa_l = arbpc2_pcxdp_q0_hold_arbbf_pa_l;
assign arbpc2_pcxdp_qsel0_pa = arbpc2_pcxdp_qsel0_arbbf_pa;
assign arbpc2_pcxdp_qsel1_pa_l = arbpc2_pcxdp_qsel1_arbbf_pa_l;
assign arbpc2_pcxdp_shift_px = arbpc2_pcxdp_shift_arbbf_px;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A222OI_BLACKBOX_V
`define SKY130_FD_SC_HD__A222OI_BLACKBOX_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A222OI_BLACKBOX_V
|
// diseño de una fifo ciclica, para implementar en cada bloque de proyecto
// ferney alberto beltran 2016 electrónica digital 1 universidad Nacional
module fifo
#(
parameter adr_width = 4,
parameter dat_width = 8
)
(
input clk, reset,
input rd, wr,
input [dat_width-1:0] data_in,
output [dat_width-1:0] data_out,
output empty,
output full
);
parameter depth = (1 << adr_width);
//declaración de registros
reg [dat_width-1:0] array_reg [depth-1:0];// register array FIFO
reg [adr_width-1:0] w_ptr_reg, w_ptr_next;
reg [adr_width-1:0] r_ptr_reg, r_ptr_next;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
assign data_out = array_reg[r_ptr_reg];
assign wr_en = wr & ~full_reg;
assign full = full_reg;
assign empty = empty_reg;
always @(posedge clk) begin
if (wr_en)
array_reg[w_ptr_reg] <= data_in;
end
// fifo control logic
// register for read and write pointers
always @(posedge clk, posedge reset) begin
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
end
always @(posedge reset, posedge wr, posedge rd)
begin
if (reset) begin
w_ptr_next = 0;
r_ptr_next = 0;
end else begin
full_next = full_reg;
empty_next = empty_reg;
case ({wr, rd})
2'b01: // read
if (~empty_reg) // not empty
begin
r_ptr_next = r_ptr_reg + 1;
full_next = 1'b0;
if (r_ptr_next==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: // write
if (~full_reg) // not full
begin
w_ptr_next = w_ptr_reg + 1;
empty_next = 1'b0;
if (w_ptr_next==r_ptr_reg)
full_next = 1'b1;
end
2'b11: // write and read
begin
w_ptr_next = w_ptr_reg + 1;
r_ptr_next = r_ptr_reg + 1;
end
endcase
end
end
endmodule
|
//Test Bench for Register File
`define N 16
`define K 4
module regfile_tb;
reg clk;
wire [`N-1:0] a,b;
reg [`N-1:0] x;
reg [`K-1:0] sa, sb, d;
reg ld;
regfile #(.n(`N), .k(`K)) r1 (clk, x, ld, d, sa, sb, a, b);
initial begin
clk = 0;
end
initial begin
$monitor("time:%t\tld: %b\tsa: %d\tsb: %d\td %d\tx: %d\ta: %d\tb: %d", $time, ld, sa, sb, d, x, a, b);
end
initial begin
// Load 10 into register 2
#0 begin
$display("\nStarting test 1");
ld = 1;
x = 16'd10;
d = 3;
sa = 3;
sb = 3;
end
// Retrieve 10 from register 2
#2 begin
$display("Reading register");
ld = 0;
x = 0;
d = 3;
sa = 3;//4'b0010;
sb = 3;//4'b0010;
end
#2 begin
$display("Writing + Reading");
ld = 1;
x = 16'd15;
d = 1;
sa = 3;
sb = 3;
end
#2 begin
$display("Reading both registers");
ld = 0;
x = 0;
d = 0;
sa = 1;
sb = 3;
end
#2 begin
$display("Read again");
ld = 0;
x = 0;
d = 0;
sa = 1;
sb = 3;
end
#4 $finish;
end
//Simulate Clock
always begin
#1 clk = !clk;
end
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1
// RDY_set_verbosity O 1 const
// v_from_masters_0_awready O 1 reg
// v_from_masters_0_wready O 1 reg
// v_from_masters_0_bvalid O 1 reg
// v_from_masters_0_bid O 4 reg
// v_from_masters_0_bresp O 2 reg
// v_from_masters_0_arready O 1 reg
// v_from_masters_0_rvalid O 1 reg
// v_from_masters_0_rid O 4 reg
// v_from_masters_0_rdata O 64 reg
// v_from_masters_0_rresp O 2 reg
// v_from_masters_0_rlast O 1 reg
// v_from_masters_1_awready O 1 reg
// v_from_masters_1_wready O 1 reg
// v_from_masters_1_bvalid O 1 reg
// v_from_masters_1_bid O 4 reg
// v_from_masters_1_bresp O 2 reg
// v_from_masters_1_arready O 1 reg
// v_from_masters_1_rvalid O 1 reg
// v_from_masters_1_rid O 4 reg
// v_from_masters_1_rdata O 64 reg
// v_from_masters_1_rresp O 2 reg
// v_from_masters_1_rlast O 1 reg
// v_to_slaves_0_awvalid O 1 reg
// v_to_slaves_0_awid O 4 reg
// v_to_slaves_0_awaddr O 64 reg
// v_to_slaves_0_awlen O 8 reg
// v_to_slaves_0_awsize O 3 reg
// v_to_slaves_0_awburst O 2 reg
// v_to_slaves_0_awlock O 1 reg
// v_to_slaves_0_awcache O 4 reg
// v_to_slaves_0_awprot O 3 reg
// v_to_slaves_0_awqos O 4 reg
// v_to_slaves_0_awregion O 4 reg
// v_to_slaves_0_wvalid O 1 reg
// v_to_slaves_0_wdata O 64 reg
// v_to_slaves_0_wstrb O 8 reg
// v_to_slaves_0_wlast O 1 reg
// v_to_slaves_0_bready O 1 reg
// v_to_slaves_0_arvalid O 1 reg
// v_to_slaves_0_arid O 4 reg
// v_to_slaves_0_araddr O 64 reg
// v_to_slaves_0_arlen O 8 reg
// v_to_slaves_0_arsize O 3 reg
// v_to_slaves_0_arburst O 2 reg
// v_to_slaves_0_arlock O 1 reg
// v_to_slaves_0_arcache O 4 reg
// v_to_slaves_0_arprot O 3 reg
// v_to_slaves_0_arqos O 4 reg
// v_to_slaves_0_arregion O 4 reg
// v_to_slaves_0_rready O 1 reg
// v_to_slaves_1_awvalid O 1 reg
// v_to_slaves_1_awid O 4 reg
// v_to_slaves_1_awaddr O 64 reg
// v_to_slaves_1_awlen O 8 reg
// v_to_slaves_1_awsize O 3 reg
// v_to_slaves_1_awburst O 2 reg
// v_to_slaves_1_awlock O 1 reg
// v_to_slaves_1_awcache O 4 reg
// v_to_slaves_1_awprot O 3 reg
// v_to_slaves_1_awqos O 4 reg
// v_to_slaves_1_awregion O 4 reg
// v_to_slaves_1_wvalid O 1 reg
// v_to_slaves_1_wdata O 64 reg
// v_to_slaves_1_wstrb O 8 reg
// v_to_slaves_1_wlast O 1 reg
// v_to_slaves_1_bready O 1 reg
// v_to_slaves_1_arvalid O 1 reg
// v_to_slaves_1_arid O 4 reg
// v_to_slaves_1_araddr O 64 reg
// v_to_slaves_1_arlen O 8 reg
// v_to_slaves_1_arsize O 3 reg
// v_to_slaves_1_arburst O 2 reg
// v_to_slaves_1_arlock O 1 reg
// v_to_slaves_1_arcache O 4 reg
// v_to_slaves_1_arprot O 3 reg
// v_to_slaves_1_arqos O 4 reg
// v_to_slaves_1_arregion O 4 reg
// v_to_slaves_1_rready O 1 reg
// v_to_slaves_2_awvalid O 1 reg
// v_to_slaves_2_awid O 4 reg
// v_to_slaves_2_awaddr O 64 reg
// v_to_slaves_2_awlen O 8 reg
// v_to_slaves_2_awsize O 3 reg
// v_to_slaves_2_awburst O 2 reg
// v_to_slaves_2_awlock O 1 reg
// v_to_slaves_2_awcache O 4 reg
// v_to_slaves_2_awprot O 3 reg
// v_to_slaves_2_awqos O 4 reg
// v_to_slaves_2_awregion O 4 reg
// v_to_slaves_2_wvalid O 1 reg
// v_to_slaves_2_wdata O 64 reg
// v_to_slaves_2_wstrb O 8 reg
// v_to_slaves_2_wlast O 1 reg
// v_to_slaves_2_bready O 1 reg
// v_to_slaves_2_arvalid O 1 reg
// v_to_slaves_2_arid O 4 reg
// v_to_slaves_2_araddr O 64 reg
// v_to_slaves_2_arlen O 8 reg
// v_to_slaves_2_arsize O 3 reg
// v_to_slaves_2_arburst O 2 reg
// v_to_slaves_2_arlock O 1 reg
// v_to_slaves_2_arcache O 4 reg
// v_to_slaves_2_arprot O 3 reg
// v_to_slaves_2_arqos O 4 reg
// v_to_slaves_2_arregion O 4 reg
// v_to_slaves_2_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// v_from_masters_0_awvalid I 1
// v_from_masters_0_awid I 4 reg
// v_from_masters_0_awaddr I 64 reg
// v_from_masters_0_awlen I 8 reg
// v_from_masters_0_awsize I 3 reg
// v_from_masters_0_awburst I 2 reg
// v_from_masters_0_awlock I 1 reg
// v_from_masters_0_awcache I 4 reg
// v_from_masters_0_awprot I 3 reg
// v_from_masters_0_awqos I 4 reg
// v_from_masters_0_awregion I 4 reg
// v_from_masters_0_wvalid I 1
// v_from_masters_0_wdata I 64 reg
// v_from_masters_0_wstrb I 8 reg
// v_from_masters_0_wlast I 1 reg
// v_from_masters_0_bready I 1
// v_from_masters_0_arvalid I 1
// v_from_masters_0_arid I 4 reg
// v_from_masters_0_araddr I 64 reg
// v_from_masters_0_arlen I 8 reg
// v_from_masters_0_arsize I 3 reg
// v_from_masters_0_arburst I 2 reg
// v_from_masters_0_arlock I 1 reg
// v_from_masters_0_arcache I 4 reg
// v_from_masters_0_arprot I 3 reg
// v_from_masters_0_arqos I 4 reg
// v_from_masters_0_arregion I 4 reg
// v_from_masters_0_rready I 1
// v_from_masters_1_awvalid I 1
// v_from_masters_1_awid I 4 reg
// v_from_masters_1_awaddr I 64 reg
// v_from_masters_1_awlen I 8 reg
// v_from_masters_1_awsize I 3 reg
// v_from_masters_1_awburst I 2 reg
// v_from_masters_1_awlock I 1 reg
// v_from_masters_1_awcache I 4 reg
// v_from_masters_1_awprot I 3 reg
// v_from_masters_1_awqos I 4 reg
// v_from_masters_1_awregion I 4 reg
// v_from_masters_1_wvalid I 1
// v_from_masters_1_wdata I 64 reg
// v_from_masters_1_wstrb I 8 reg
// v_from_masters_1_wlast I 1 reg
// v_from_masters_1_bready I 1
// v_from_masters_1_arvalid I 1
// v_from_masters_1_arid I 4 reg
// v_from_masters_1_araddr I 64 reg
// v_from_masters_1_arlen I 8 reg
// v_from_masters_1_arsize I 3 reg
// v_from_masters_1_arburst I 2 reg
// v_from_masters_1_arlock I 1 reg
// v_from_masters_1_arcache I 4 reg
// v_from_masters_1_arprot I 3 reg
// v_from_masters_1_arqos I 4 reg
// v_from_masters_1_arregion I 4 reg
// v_from_masters_1_rready I 1
// v_to_slaves_0_awready I 1
// v_to_slaves_0_wready I 1
// v_to_slaves_0_bvalid I 1
// v_to_slaves_0_bid I 4 reg
// v_to_slaves_0_bresp I 2 reg
// v_to_slaves_0_arready I 1
// v_to_slaves_0_rvalid I 1
// v_to_slaves_0_rid I 4 reg
// v_to_slaves_0_rdata I 64 reg
// v_to_slaves_0_rresp I 2 reg
// v_to_slaves_0_rlast I 1 reg
// v_to_slaves_1_awready I 1
// v_to_slaves_1_wready I 1
// v_to_slaves_1_bvalid I 1
// v_to_slaves_1_bid I 4 reg
// v_to_slaves_1_bresp I 2 reg
// v_to_slaves_1_arready I 1
// v_to_slaves_1_rvalid I 1
// v_to_slaves_1_rid I 4 reg
// v_to_slaves_1_rdata I 64 reg
// v_to_slaves_1_rresp I 2 reg
// v_to_slaves_1_rlast I 1 reg
// v_to_slaves_2_awready I 1
// v_to_slaves_2_wready I 1
// v_to_slaves_2_bvalid I 1
// v_to_slaves_2_bid I 4 reg
// v_to_slaves_2_bresp I 2 reg
// v_to_slaves_2_arready I 1
// v_to_slaves_2_rvalid I 1
// v_to_slaves_2_rid I 4 reg
// v_to_slaves_2_rdata I 64 reg
// v_to_slaves_2_rresp I 2 reg
// v_to_slaves_2_rlast I 1 reg
// EN_reset I 1
// EN_set_verbosity I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFabric_2x3(CLK,
RST_N,
EN_reset,
RDY_reset,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
v_from_masters_0_awvalid,
v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion,
v_from_masters_0_awready,
v_from_masters_0_wvalid,
v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast,
v_from_masters_0_wready,
v_from_masters_0_bvalid,
v_from_masters_0_bid,
v_from_masters_0_bresp,
v_from_masters_0_bready,
v_from_masters_0_arvalid,
v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion,
v_from_masters_0_arready,
v_from_masters_0_rvalid,
v_from_masters_0_rid,
v_from_masters_0_rdata,
v_from_masters_0_rresp,
v_from_masters_0_rlast,
v_from_masters_0_rready,
v_from_masters_1_awvalid,
v_from_masters_1_awid,
v_from_masters_1_awaddr,
v_from_masters_1_awlen,
v_from_masters_1_awsize,
v_from_masters_1_awburst,
v_from_masters_1_awlock,
v_from_masters_1_awcache,
v_from_masters_1_awprot,
v_from_masters_1_awqos,
v_from_masters_1_awregion,
v_from_masters_1_awready,
v_from_masters_1_wvalid,
v_from_masters_1_wdata,
v_from_masters_1_wstrb,
v_from_masters_1_wlast,
v_from_masters_1_wready,
v_from_masters_1_bvalid,
v_from_masters_1_bid,
v_from_masters_1_bresp,
v_from_masters_1_bready,
v_from_masters_1_arvalid,
v_from_masters_1_arid,
v_from_masters_1_araddr,
v_from_masters_1_arlen,
v_from_masters_1_arsize,
v_from_masters_1_arburst,
v_from_masters_1_arlock,
v_from_masters_1_arcache,
v_from_masters_1_arprot,
v_from_masters_1_arqos,
v_from_masters_1_arregion,
v_from_masters_1_arready,
v_from_masters_1_rvalid,
v_from_masters_1_rid,
v_from_masters_1_rdata,
v_from_masters_1_rresp,
v_from_masters_1_rlast,
v_from_masters_1_rready,
v_to_slaves_0_awvalid,
v_to_slaves_0_awid,
v_to_slaves_0_awaddr,
v_to_slaves_0_awlen,
v_to_slaves_0_awsize,
v_to_slaves_0_awburst,
v_to_slaves_0_awlock,
v_to_slaves_0_awcache,
v_to_slaves_0_awprot,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_0_awready,
v_to_slaves_0_wvalid,
v_to_slaves_0_wdata,
v_to_slaves_0_wstrb,
v_to_slaves_0_wlast,
v_to_slaves_0_wready,
v_to_slaves_0_bvalid,
v_to_slaves_0_bid,
v_to_slaves_0_bresp,
v_to_slaves_0_bready,
v_to_slaves_0_arvalid,
v_to_slaves_0_arid,
v_to_slaves_0_araddr,
v_to_slaves_0_arlen,
v_to_slaves_0_arsize,
v_to_slaves_0_arburst,
v_to_slaves_0_arlock,
v_to_slaves_0_arcache,
v_to_slaves_0_arprot,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_arready,
v_to_slaves_0_rvalid,
v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast,
v_to_slaves_0_rready,
v_to_slaves_1_awvalid,
v_to_slaves_1_awid,
v_to_slaves_1_awaddr,
v_to_slaves_1_awlen,
v_to_slaves_1_awsize,
v_to_slaves_1_awburst,
v_to_slaves_1_awlock,
v_to_slaves_1_awcache,
v_to_slaves_1_awprot,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_1_awready,
v_to_slaves_1_wvalid,
v_to_slaves_1_wdata,
v_to_slaves_1_wstrb,
v_to_slaves_1_wlast,
v_to_slaves_1_wready,
v_to_slaves_1_bvalid,
v_to_slaves_1_bid,
v_to_slaves_1_bresp,
v_to_slaves_1_bready,
v_to_slaves_1_arvalid,
v_to_slaves_1_arid,
v_to_slaves_1_araddr,
v_to_slaves_1_arlen,
v_to_slaves_1_arsize,
v_to_slaves_1_arburst,
v_to_slaves_1_arlock,
v_to_slaves_1_arcache,
v_to_slaves_1_arprot,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_arready,
v_to_slaves_1_rvalid,
v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast,
v_to_slaves_1_rready,
v_to_slaves_2_awvalid,
v_to_slaves_2_awid,
v_to_slaves_2_awaddr,
v_to_slaves_2_awlen,
v_to_slaves_2_awsize,
v_to_slaves_2_awburst,
v_to_slaves_2_awlock,
v_to_slaves_2_awcache,
v_to_slaves_2_awprot,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion,
v_to_slaves_2_awready,
v_to_slaves_2_wvalid,
v_to_slaves_2_wdata,
v_to_slaves_2_wstrb,
v_to_slaves_2_wlast,
v_to_slaves_2_wready,
v_to_slaves_2_bvalid,
v_to_slaves_2_bid,
v_to_slaves_2_bresp,
v_to_slaves_2_bready,
v_to_slaves_2_arvalid,
v_to_slaves_2_arid,
v_to_slaves_2_araddr,
v_to_slaves_2_arlen,
v_to_slaves_2_arsize,
v_to_slaves_2_arburst,
v_to_slaves_2_arlock,
v_to_slaves_2_arcache,
v_to_slaves_2_arprot,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_arready,
v_to_slaves_2_rvalid,
v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast,
v_to_slaves_2_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method v_from_masters_0_m_awvalid
input v_from_masters_0_awvalid;
input [3 : 0] v_from_masters_0_awid;
input [63 : 0] v_from_masters_0_awaddr;
input [7 : 0] v_from_masters_0_awlen;
input [2 : 0] v_from_masters_0_awsize;
input [1 : 0] v_from_masters_0_awburst;
input v_from_masters_0_awlock;
input [3 : 0] v_from_masters_0_awcache;
input [2 : 0] v_from_masters_0_awprot;
input [3 : 0] v_from_masters_0_awqos;
input [3 : 0] v_from_masters_0_awregion;
// value method v_from_masters_0_m_awready
output v_from_masters_0_awready;
// action method v_from_masters_0_m_wvalid
input v_from_masters_0_wvalid;
input [63 : 0] v_from_masters_0_wdata;
input [7 : 0] v_from_masters_0_wstrb;
input v_from_masters_0_wlast;
// value method v_from_masters_0_m_wready
output v_from_masters_0_wready;
// value method v_from_masters_0_m_bvalid
output v_from_masters_0_bvalid;
// value method v_from_masters_0_m_bid
output [3 : 0] v_from_masters_0_bid;
// value method v_from_masters_0_m_bresp
output [1 : 0] v_from_masters_0_bresp;
// value method v_from_masters_0_m_buser
// action method v_from_masters_0_m_bready
input v_from_masters_0_bready;
// action method v_from_masters_0_m_arvalid
input v_from_masters_0_arvalid;
input [3 : 0] v_from_masters_0_arid;
input [63 : 0] v_from_masters_0_araddr;
input [7 : 0] v_from_masters_0_arlen;
input [2 : 0] v_from_masters_0_arsize;
input [1 : 0] v_from_masters_0_arburst;
input v_from_masters_0_arlock;
input [3 : 0] v_from_masters_0_arcache;
input [2 : 0] v_from_masters_0_arprot;
input [3 : 0] v_from_masters_0_arqos;
input [3 : 0] v_from_masters_0_arregion;
// value method v_from_masters_0_m_arready
output v_from_masters_0_arready;
// value method v_from_masters_0_m_rvalid
output v_from_masters_0_rvalid;
// value method v_from_masters_0_m_rid
output [3 : 0] v_from_masters_0_rid;
// value method v_from_masters_0_m_rdata
output [63 : 0] v_from_masters_0_rdata;
// value method v_from_masters_0_m_rresp
output [1 : 0] v_from_masters_0_rresp;
// value method v_from_masters_0_m_rlast
output v_from_masters_0_rlast;
// value method v_from_masters_0_m_ruser
// action method v_from_masters_0_m_rready
input v_from_masters_0_rready;
// action method v_from_masters_1_m_awvalid
input v_from_masters_1_awvalid;
input [3 : 0] v_from_masters_1_awid;
input [63 : 0] v_from_masters_1_awaddr;
input [7 : 0] v_from_masters_1_awlen;
input [2 : 0] v_from_masters_1_awsize;
input [1 : 0] v_from_masters_1_awburst;
input v_from_masters_1_awlock;
input [3 : 0] v_from_masters_1_awcache;
input [2 : 0] v_from_masters_1_awprot;
input [3 : 0] v_from_masters_1_awqos;
input [3 : 0] v_from_masters_1_awregion;
// value method v_from_masters_1_m_awready
output v_from_masters_1_awready;
// action method v_from_masters_1_m_wvalid
input v_from_masters_1_wvalid;
input [63 : 0] v_from_masters_1_wdata;
input [7 : 0] v_from_masters_1_wstrb;
input v_from_masters_1_wlast;
// value method v_from_masters_1_m_wready
output v_from_masters_1_wready;
// value method v_from_masters_1_m_bvalid
output v_from_masters_1_bvalid;
// value method v_from_masters_1_m_bid
output [3 : 0] v_from_masters_1_bid;
// value method v_from_masters_1_m_bresp
output [1 : 0] v_from_masters_1_bresp;
// value method v_from_masters_1_m_buser
// action method v_from_masters_1_m_bready
input v_from_masters_1_bready;
// action method v_from_masters_1_m_arvalid
input v_from_masters_1_arvalid;
input [3 : 0] v_from_masters_1_arid;
input [63 : 0] v_from_masters_1_araddr;
input [7 : 0] v_from_masters_1_arlen;
input [2 : 0] v_from_masters_1_arsize;
input [1 : 0] v_from_masters_1_arburst;
input v_from_masters_1_arlock;
input [3 : 0] v_from_masters_1_arcache;
input [2 : 0] v_from_masters_1_arprot;
input [3 : 0] v_from_masters_1_arqos;
input [3 : 0] v_from_masters_1_arregion;
// value method v_from_masters_1_m_arready
output v_from_masters_1_arready;
// value method v_from_masters_1_m_rvalid
output v_from_masters_1_rvalid;
// value method v_from_masters_1_m_rid
output [3 : 0] v_from_masters_1_rid;
// value method v_from_masters_1_m_rdata
output [63 : 0] v_from_masters_1_rdata;
// value method v_from_masters_1_m_rresp
output [1 : 0] v_from_masters_1_rresp;
// value method v_from_masters_1_m_rlast
output v_from_masters_1_rlast;
// value method v_from_masters_1_m_ruser
// action method v_from_masters_1_m_rready
input v_from_masters_1_rready;
// value method v_to_slaves_0_m_awvalid
output v_to_slaves_0_awvalid;
// value method v_to_slaves_0_m_awid
output [3 : 0] v_to_slaves_0_awid;
// value method v_to_slaves_0_m_awaddr
output [63 : 0] v_to_slaves_0_awaddr;
// value method v_to_slaves_0_m_awlen
output [7 : 0] v_to_slaves_0_awlen;
// value method v_to_slaves_0_m_awsize
output [2 : 0] v_to_slaves_0_awsize;
// value method v_to_slaves_0_m_awburst
output [1 : 0] v_to_slaves_0_awburst;
// value method v_to_slaves_0_m_awlock
output v_to_slaves_0_awlock;
// value method v_to_slaves_0_m_awcache
output [3 : 0] v_to_slaves_0_awcache;
// value method v_to_slaves_0_m_awprot
output [2 : 0] v_to_slaves_0_awprot;
// value method v_to_slaves_0_m_awqos
output [3 : 0] v_to_slaves_0_awqos;
// value method v_to_slaves_0_m_awregion
output [3 : 0] v_to_slaves_0_awregion;
// value method v_to_slaves_0_m_awuser
// action method v_to_slaves_0_m_awready
input v_to_slaves_0_awready;
// value method v_to_slaves_0_m_wvalid
output v_to_slaves_0_wvalid;
// value method v_to_slaves_0_m_wdata
output [63 : 0] v_to_slaves_0_wdata;
// value method v_to_slaves_0_m_wstrb
output [7 : 0] v_to_slaves_0_wstrb;
// value method v_to_slaves_0_m_wlast
output v_to_slaves_0_wlast;
// value method v_to_slaves_0_m_wuser
// action method v_to_slaves_0_m_wready
input v_to_slaves_0_wready;
// action method v_to_slaves_0_m_bvalid
input v_to_slaves_0_bvalid;
input [3 : 0] v_to_slaves_0_bid;
input [1 : 0] v_to_slaves_0_bresp;
// value method v_to_slaves_0_m_bready
output v_to_slaves_0_bready;
// value method v_to_slaves_0_m_arvalid
output v_to_slaves_0_arvalid;
// value method v_to_slaves_0_m_arid
output [3 : 0] v_to_slaves_0_arid;
// value method v_to_slaves_0_m_araddr
output [63 : 0] v_to_slaves_0_araddr;
// value method v_to_slaves_0_m_arlen
output [7 : 0] v_to_slaves_0_arlen;
// value method v_to_slaves_0_m_arsize
output [2 : 0] v_to_slaves_0_arsize;
// value method v_to_slaves_0_m_arburst
output [1 : 0] v_to_slaves_0_arburst;
// value method v_to_slaves_0_m_arlock
output v_to_slaves_0_arlock;
// value method v_to_slaves_0_m_arcache
output [3 : 0] v_to_slaves_0_arcache;
// value method v_to_slaves_0_m_arprot
output [2 : 0] v_to_slaves_0_arprot;
// value method v_to_slaves_0_m_arqos
output [3 : 0] v_to_slaves_0_arqos;
// value method v_to_slaves_0_m_arregion
output [3 : 0] v_to_slaves_0_arregion;
// value method v_to_slaves_0_m_aruser
// action method v_to_slaves_0_m_arready
input v_to_slaves_0_arready;
// action method v_to_slaves_0_m_rvalid
input v_to_slaves_0_rvalid;
input [3 : 0] v_to_slaves_0_rid;
input [63 : 0] v_to_slaves_0_rdata;
input [1 : 0] v_to_slaves_0_rresp;
input v_to_slaves_0_rlast;
// value method v_to_slaves_0_m_rready
output v_to_slaves_0_rready;
// value method v_to_slaves_1_m_awvalid
output v_to_slaves_1_awvalid;
// value method v_to_slaves_1_m_awid
output [3 : 0] v_to_slaves_1_awid;
// value method v_to_slaves_1_m_awaddr
output [63 : 0] v_to_slaves_1_awaddr;
// value method v_to_slaves_1_m_awlen
output [7 : 0] v_to_slaves_1_awlen;
// value method v_to_slaves_1_m_awsize
output [2 : 0] v_to_slaves_1_awsize;
// value method v_to_slaves_1_m_awburst
output [1 : 0] v_to_slaves_1_awburst;
// value method v_to_slaves_1_m_awlock
output v_to_slaves_1_awlock;
// value method v_to_slaves_1_m_awcache
output [3 : 0] v_to_slaves_1_awcache;
// value method v_to_slaves_1_m_awprot
output [2 : 0] v_to_slaves_1_awprot;
// value method v_to_slaves_1_m_awqos
output [3 : 0] v_to_slaves_1_awqos;
// value method v_to_slaves_1_m_awregion
output [3 : 0] v_to_slaves_1_awregion;
// value method v_to_slaves_1_m_awuser
// action method v_to_slaves_1_m_awready
input v_to_slaves_1_awready;
// value method v_to_slaves_1_m_wvalid
output v_to_slaves_1_wvalid;
// value method v_to_slaves_1_m_wdata
output [63 : 0] v_to_slaves_1_wdata;
// value method v_to_slaves_1_m_wstrb
output [7 : 0] v_to_slaves_1_wstrb;
// value method v_to_slaves_1_m_wlast
output v_to_slaves_1_wlast;
// value method v_to_slaves_1_m_wuser
// action method v_to_slaves_1_m_wready
input v_to_slaves_1_wready;
// action method v_to_slaves_1_m_bvalid
input v_to_slaves_1_bvalid;
input [3 : 0] v_to_slaves_1_bid;
input [1 : 0] v_to_slaves_1_bresp;
// value method v_to_slaves_1_m_bready
output v_to_slaves_1_bready;
// value method v_to_slaves_1_m_arvalid
output v_to_slaves_1_arvalid;
// value method v_to_slaves_1_m_arid
output [3 : 0] v_to_slaves_1_arid;
// value method v_to_slaves_1_m_araddr
output [63 : 0] v_to_slaves_1_araddr;
// value method v_to_slaves_1_m_arlen
output [7 : 0] v_to_slaves_1_arlen;
// value method v_to_slaves_1_m_arsize
output [2 : 0] v_to_slaves_1_arsize;
// value method v_to_slaves_1_m_arburst
output [1 : 0] v_to_slaves_1_arburst;
// value method v_to_slaves_1_m_arlock
output v_to_slaves_1_arlock;
// value method v_to_slaves_1_m_arcache
output [3 : 0] v_to_slaves_1_arcache;
// value method v_to_slaves_1_m_arprot
output [2 : 0] v_to_slaves_1_arprot;
// value method v_to_slaves_1_m_arqos
output [3 : 0] v_to_slaves_1_arqos;
// value method v_to_slaves_1_m_arregion
output [3 : 0] v_to_slaves_1_arregion;
// value method v_to_slaves_1_m_aruser
// action method v_to_slaves_1_m_arready
input v_to_slaves_1_arready;
// action method v_to_slaves_1_m_rvalid
input v_to_slaves_1_rvalid;
input [3 : 0] v_to_slaves_1_rid;
input [63 : 0] v_to_slaves_1_rdata;
input [1 : 0] v_to_slaves_1_rresp;
input v_to_slaves_1_rlast;
// value method v_to_slaves_1_m_rready
output v_to_slaves_1_rready;
// value method v_to_slaves_2_m_awvalid
output v_to_slaves_2_awvalid;
// value method v_to_slaves_2_m_awid
output [3 : 0] v_to_slaves_2_awid;
// value method v_to_slaves_2_m_awaddr
output [63 : 0] v_to_slaves_2_awaddr;
// value method v_to_slaves_2_m_awlen
output [7 : 0] v_to_slaves_2_awlen;
// value method v_to_slaves_2_m_awsize
output [2 : 0] v_to_slaves_2_awsize;
// value method v_to_slaves_2_m_awburst
output [1 : 0] v_to_slaves_2_awburst;
// value method v_to_slaves_2_m_awlock
output v_to_slaves_2_awlock;
// value method v_to_slaves_2_m_awcache
output [3 : 0] v_to_slaves_2_awcache;
// value method v_to_slaves_2_m_awprot
output [2 : 0] v_to_slaves_2_awprot;
// value method v_to_slaves_2_m_awqos
output [3 : 0] v_to_slaves_2_awqos;
// value method v_to_slaves_2_m_awregion
output [3 : 0] v_to_slaves_2_awregion;
// value method v_to_slaves_2_m_awuser
// action method v_to_slaves_2_m_awready
input v_to_slaves_2_awready;
// value method v_to_slaves_2_m_wvalid
output v_to_slaves_2_wvalid;
// value method v_to_slaves_2_m_wdata
output [63 : 0] v_to_slaves_2_wdata;
// value method v_to_slaves_2_m_wstrb
output [7 : 0] v_to_slaves_2_wstrb;
// value method v_to_slaves_2_m_wlast
output v_to_slaves_2_wlast;
// value method v_to_slaves_2_m_wuser
// action method v_to_slaves_2_m_wready
input v_to_slaves_2_wready;
// action method v_to_slaves_2_m_bvalid
input v_to_slaves_2_bvalid;
input [3 : 0] v_to_slaves_2_bid;
input [1 : 0] v_to_slaves_2_bresp;
// value method v_to_slaves_2_m_bready
output v_to_slaves_2_bready;
// value method v_to_slaves_2_m_arvalid
output v_to_slaves_2_arvalid;
// value method v_to_slaves_2_m_arid
output [3 : 0] v_to_slaves_2_arid;
// value method v_to_slaves_2_m_araddr
output [63 : 0] v_to_slaves_2_araddr;
// value method v_to_slaves_2_m_arlen
output [7 : 0] v_to_slaves_2_arlen;
// value method v_to_slaves_2_m_arsize
output [2 : 0] v_to_slaves_2_arsize;
// value method v_to_slaves_2_m_arburst
output [1 : 0] v_to_slaves_2_arburst;
// value method v_to_slaves_2_m_arlock
output v_to_slaves_2_arlock;
// value method v_to_slaves_2_m_arcache
output [3 : 0] v_to_slaves_2_arcache;
// value method v_to_slaves_2_m_arprot
output [2 : 0] v_to_slaves_2_arprot;
// value method v_to_slaves_2_m_arqos
output [3 : 0] v_to_slaves_2_arqos;
// value method v_to_slaves_2_m_arregion
output [3 : 0] v_to_slaves_2_arregion;
// value method v_to_slaves_2_m_aruser
// action method v_to_slaves_2_m_arready
input v_to_slaves_2_arready;
// action method v_to_slaves_2_m_rvalid
input v_to_slaves_2_rvalid;
input [3 : 0] v_to_slaves_2_rid;
input [63 : 0] v_to_slaves_2_rdata;
input [1 : 0] v_to_slaves_2_rresp;
input v_to_slaves_2_rlast;
// value method v_to_slaves_2_m_rready
output v_to_slaves_2_rready;
// signals for module outputs
wire [63 : 0] v_from_masters_0_rdata,
v_from_masters_1_rdata,
v_to_slaves_0_araddr,
v_to_slaves_0_awaddr,
v_to_slaves_0_wdata,
v_to_slaves_1_araddr,
v_to_slaves_1_awaddr,
v_to_slaves_1_wdata,
v_to_slaves_2_araddr,
v_to_slaves_2_awaddr,
v_to_slaves_2_wdata;
wire [7 : 0] v_to_slaves_0_arlen,
v_to_slaves_0_awlen,
v_to_slaves_0_wstrb,
v_to_slaves_1_arlen,
v_to_slaves_1_awlen,
v_to_slaves_1_wstrb,
v_to_slaves_2_arlen,
v_to_slaves_2_awlen,
v_to_slaves_2_wstrb;
wire [3 : 0] v_from_masters_0_bid,
v_from_masters_0_rid,
v_from_masters_1_bid,
v_from_masters_1_rid,
v_to_slaves_0_arcache,
v_to_slaves_0_arid,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_awcache,
v_to_slaves_0_awid,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_1_arcache,
v_to_slaves_1_arid,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_awcache,
v_to_slaves_1_awid,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_2_arcache,
v_to_slaves_2_arid,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_awcache,
v_to_slaves_2_awid,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion;
wire [2 : 0] v_to_slaves_0_arprot,
v_to_slaves_0_arsize,
v_to_slaves_0_awprot,
v_to_slaves_0_awsize,
v_to_slaves_1_arprot,
v_to_slaves_1_arsize,
v_to_slaves_1_awprot,
v_to_slaves_1_awsize,
v_to_slaves_2_arprot,
v_to_slaves_2_arsize,
v_to_slaves_2_awprot,
v_to_slaves_2_awsize;
wire [1 : 0] v_from_masters_0_bresp,
v_from_masters_0_rresp,
v_from_masters_1_bresp,
v_from_masters_1_rresp,
v_to_slaves_0_arburst,
v_to_slaves_0_awburst,
v_to_slaves_1_arburst,
v_to_slaves_1_awburst,
v_to_slaves_2_arburst,
v_to_slaves_2_awburst;
wire RDY_reset,
RDY_set_verbosity,
v_from_masters_0_arready,
v_from_masters_0_awready,
v_from_masters_0_bvalid,
v_from_masters_0_rlast,
v_from_masters_0_rvalid,
v_from_masters_0_wready,
v_from_masters_1_arready,
v_from_masters_1_awready,
v_from_masters_1_bvalid,
v_from_masters_1_rlast,
v_from_masters_1_rvalid,
v_from_masters_1_wready,
v_to_slaves_0_arlock,
v_to_slaves_0_arvalid,
v_to_slaves_0_awlock,
v_to_slaves_0_awvalid,
v_to_slaves_0_bready,
v_to_slaves_0_rready,
v_to_slaves_0_wlast,
v_to_slaves_0_wvalid,
v_to_slaves_1_arlock,
v_to_slaves_1_arvalid,
v_to_slaves_1_awlock,
v_to_slaves_1_awvalid,
v_to_slaves_1_bready,
v_to_slaves_1_rready,
v_to_slaves_1_wlast,
v_to_slaves_1_wvalid,
v_to_slaves_2_arlock,
v_to_slaves_2_arvalid,
v_to_slaves_2_awlock,
v_to_slaves_2_awvalid,
v_to_slaves_2_bready,
v_to_slaves_2_rready,
v_to_slaves_2_wlast,
v_to_slaves_2_wvalid;
// register fabric_cfg_verbosity
reg [3 : 0] fabric_cfg_verbosity;
wire [3 : 0] fabric_cfg_verbosity$D_IN;
wire fabric_cfg_verbosity$EN;
// register fabric_rg_reset
reg fabric_rg_reset;
wire fabric_rg_reset$D_IN, fabric_rg_reset$EN;
// register fabric_v_rg_r_beat_count_0
reg [7 : 0] fabric_v_rg_r_beat_count_0;
reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN;
wire fabric_v_rg_r_beat_count_0$EN;
// register fabric_v_rg_r_beat_count_1
reg [7 : 0] fabric_v_rg_r_beat_count_1;
reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN;
wire fabric_v_rg_r_beat_count_1$EN;
// register fabric_v_rg_r_beat_count_2
reg [7 : 0] fabric_v_rg_r_beat_count_2;
reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN;
wire fabric_v_rg_r_beat_count_2$EN;
// register fabric_v_rg_r_err_beat_count_0
reg [7 : 0] fabric_v_rg_r_err_beat_count_0;
wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN;
wire fabric_v_rg_r_err_beat_count_0$EN;
// register fabric_v_rg_r_err_beat_count_1
reg [7 : 0] fabric_v_rg_r_err_beat_count_1;
wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN;
wire fabric_v_rg_r_err_beat_count_1$EN;
// register fabric_v_rg_wd_beat_count_0
reg [7 : 0] fabric_v_rg_wd_beat_count_0;
wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN;
wire fabric_v_rg_wd_beat_count_0$EN;
// register fabric_v_rg_wd_beat_count_1
reg [7 : 0] fabric_v_rg_wd_beat_count_1;
wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN;
wire fabric_v_rg_wd_beat_count_1$EN;
// ports of submodule fabric_v_f_rd_err_info_0
wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT;
wire fabric_v_f_rd_err_info_0$CLR,
fabric_v_f_rd_err_info_0$DEQ,
fabric_v_f_rd_err_info_0$EMPTY_N,
fabric_v_f_rd_err_info_0$ENQ;
// ports of submodule fabric_v_f_rd_err_info_1
wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT;
wire fabric_v_f_rd_err_info_1$CLR,
fabric_v_f_rd_err_info_1$DEQ,
fabric_v_f_rd_err_info_1$EMPTY_N,
fabric_v_f_rd_err_info_1$ENQ;
// ports of submodule fabric_v_f_rd_mis_0
wire [9 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT;
wire fabric_v_f_rd_mis_0$CLR,
fabric_v_f_rd_mis_0$DEQ,
fabric_v_f_rd_mis_0$EMPTY_N,
fabric_v_f_rd_mis_0$ENQ,
fabric_v_f_rd_mis_0$FULL_N;
// ports of submodule fabric_v_f_rd_mis_1
wire [9 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT;
wire fabric_v_f_rd_mis_1$CLR,
fabric_v_f_rd_mis_1$DEQ,
fabric_v_f_rd_mis_1$EMPTY_N,
fabric_v_f_rd_mis_1$ENQ,
fabric_v_f_rd_mis_1$FULL_N;
// ports of submodule fabric_v_f_rd_mis_2
wire [9 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT;
wire fabric_v_f_rd_mis_2$CLR,
fabric_v_f_rd_mis_2$DEQ,
fabric_v_f_rd_mis_2$EMPTY_N,
fabric_v_f_rd_mis_2$ENQ,
fabric_v_f_rd_mis_2$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_0
reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT;
wire fabric_v_f_rd_sjs_0$CLR,
fabric_v_f_rd_sjs_0$DEQ,
fabric_v_f_rd_sjs_0$EMPTY_N,
fabric_v_f_rd_sjs_0$ENQ,
fabric_v_f_rd_sjs_0$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_1
reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT;
wire fabric_v_f_rd_sjs_1$CLR,
fabric_v_f_rd_sjs_1$DEQ,
fabric_v_f_rd_sjs_1$EMPTY_N,
fabric_v_f_rd_sjs_1$ENQ,
fabric_v_f_rd_sjs_1$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_0
reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT;
wire fabric_v_f_wd_tasks_0$CLR,
fabric_v_f_wd_tasks_0$DEQ,
fabric_v_f_wd_tasks_0$EMPTY_N,
fabric_v_f_wd_tasks_0$ENQ,
fabric_v_f_wd_tasks_0$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_1
reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT;
wire fabric_v_f_wd_tasks_1$CLR,
fabric_v_f_wd_tasks_1$DEQ,
fabric_v_f_wd_tasks_1$EMPTY_N,
fabric_v_f_wd_tasks_1$ENQ,
fabric_v_f_wd_tasks_1$FULL_N;
// ports of submodule fabric_v_f_wr_err_info_0
wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT;
wire fabric_v_f_wr_err_info_0$CLR,
fabric_v_f_wr_err_info_0$DEQ,
fabric_v_f_wr_err_info_0$EMPTY_N,
fabric_v_f_wr_err_info_0$ENQ;
// ports of submodule fabric_v_f_wr_err_info_1
wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT;
wire fabric_v_f_wr_err_info_1$CLR,
fabric_v_f_wr_err_info_1$DEQ,
fabric_v_f_wr_err_info_1$EMPTY_N,
fabric_v_f_wr_err_info_1$ENQ;
// ports of submodule fabric_v_f_wr_mis_0
wire [1 : 0] fabric_v_f_wr_mis_0$D_IN, fabric_v_f_wr_mis_0$D_OUT;
wire fabric_v_f_wr_mis_0$CLR,
fabric_v_f_wr_mis_0$DEQ,
fabric_v_f_wr_mis_0$EMPTY_N,
fabric_v_f_wr_mis_0$ENQ,
fabric_v_f_wr_mis_0$FULL_N;
// ports of submodule fabric_v_f_wr_mis_1
wire [1 : 0] fabric_v_f_wr_mis_1$D_IN, fabric_v_f_wr_mis_1$D_OUT;
wire fabric_v_f_wr_mis_1$CLR,
fabric_v_f_wr_mis_1$DEQ,
fabric_v_f_wr_mis_1$EMPTY_N,
fabric_v_f_wr_mis_1$ENQ,
fabric_v_f_wr_mis_1$FULL_N;
// ports of submodule fabric_v_f_wr_mis_2
wire [1 : 0] fabric_v_f_wr_mis_2$D_IN, fabric_v_f_wr_mis_2$D_OUT;
wire fabric_v_f_wr_mis_2$CLR,
fabric_v_f_wr_mis_2$DEQ,
fabric_v_f_wr_mis_2$EMPTY_N,
fabric_v_f_wr_mis_2$ENQ,
fabric_v_f_wr_mis_2$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_0
reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT;
wire fabric_v_f_wr_sjs_0$CLR,
fabric_v_f_wr_sjs_0$DEQ,
fabric_v_f_wr_sjs_0$EMPTY_N,
fabric_v_f_wr_sjs_0$ENQ,
fabric_v_f_wr_sjs_0$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_1
reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT;
wire fabric_v_f_wr_sjs_1$CLR,
fabric_v_f_wr_sjs_1$DEQ,
fabric_v_f_wr_sjs_1$EMPTY_N,
fabric_v_f_wr_sjs_1$ENQ,
fabric_v_f_wr_sjs_1$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_addr
wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN,
fabric_xactors_from_masters_0_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_addr$CLR,
fabric_xactors_from_masters_0_f_rd_addr$DEQ,
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_addr$ENQ,
fabric_xactors_from_masters_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_data
reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN;
wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_data$CLR,
fabric_xactors_from_masters_0_f_rd_data$DEQ,
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_data$ENQ,
fabric_xactors_from_masters_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_addr
wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN,
fabric_xactors_from_masters_0_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_addr$CLR,
fabric_xactors_from_masters_0_f_wr_addr$DEQ,
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_addr$ENQ,
fabric_xactors_from_masters_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN,
fabric_xactors_from_masters_0_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_data$CLR,
fabric_xactors_from_masters_0_f_wr_data$DEQ,
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_data$ENQ,
fabric_xactors_from_masters_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_resp
reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN;
wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_resp$CLR,
fabric_xactors_from_masters_0_f_wr_resp$DEQ,
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_resp$ENQ,
fabric_xactors_from_masters_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_rd_addr
wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN,
fabric_xactors_from_masters_1_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_1_f_rd_addr$CLR,
fabric_xactors_from_masters_1_f_rd_addr$DEQ,
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_1_f_rd_addr$ENQ,
fabric_xactors_from_masters_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_rd_data
reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN;
wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_1_f_rd_data$CLR,
fabric_xactors_from_masters_1_f_rd_data$DEQ,
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_1_f_rd_data$ENQ,
fabric_xactors_from_masters_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_addr
wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN,
fabric_xactors_from_masters_1_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_addr$CLR,
fabric_xactors_from_masters_1_f_wr_addr$DEQ,
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_addr$ENQ,
fabric_xactors_from_masters_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN,
fabric_xactors_from_masters_1_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_data$CLR,
fabric_xactors_from_masters_1_f_wr_data$DEQ,
fabric_xactors_from_masters_1_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_data$ENQ,
fabric_xactors_from_masters_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_resp
reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN;
wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_resp$CLR,
fabric_xactors_from_masters_1_f_wr_resp$DEQ,
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_resp$ENQ,
fabric_xactors_from_masters_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN,
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_addr$CLR,
fabric_xactors_to_slaves_0_f_rd_addr$DEQ,
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_addr$ENQ,
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_data$CLR,
fabric_xactors_to_slaves_0_f_rd_data$DEQ,
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_data$ENQ,
fabric_xactors_to_slaves_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN,
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_addr$CLR,
fabric_xactors_to_slaves_0_f_wr_addr$DEQ,
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_addr$ENQ,
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN,
fabric_xactors_to_slaves_0_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_data$CLR,
fabric_xactors_to_slaves_0_f_wr_data$DEQ,
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_data$ENQ,
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN,
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_resp$CLR,
fabric_xactors_to_slaves_0_f_wr_resp$DEQ,
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_resp$ENQ,
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN,
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_addr$CLR,
fabric_xactors_to_slaves_1_f_rd_addr$DEQ,
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_addr$ENQ,
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_data$CLR,
fabric_xactors_to_slaves_1_f_rd_data$DEQ,
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_data$ENQ,
fabric_xactors_to_slaves_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN,
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_addr$CLR,
fabric_xactors_to_slaves_1_f_wr_addr$DEQ,
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_addr$ENQ,
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN,
fabric_xactors_to_slaves_1_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_data$CLR,
fabric_xactors_to_slaves_1_f_wr_data$DEQ,
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_data$ENQ,
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN,
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_resp$CLR,
fabric_xactors_to_slaves_1_f_wr_resp$DEQ,
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_resp$ENQ,
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN,
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_addr$CLR,
fabric_xactors_to_slaves_2_f_rd_addr$DEQ,
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_addr$ENQ,
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_data$CLR,
fabric_xactors_to_slaves_2_f_rd_data$DEQ,
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_data$ENQ,
fabric_xactors_to_slaves_2_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN,
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_addr$CLR,
fabric_xactors_to_slaves_2_f_wr_addr$DEQ,
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_addr$ENQ,
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN,
fabric_xactors_to_slaves_2_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_data$CLR,
fabric_xactors_to_slaves_2_f_wr_data$DEQ,
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_data$ENQ,
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN,
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_resp$CLR,
fabric_xactors_to_slaves_2_f_wr_resp$DEQ,
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_resp$ENQ,
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_near_mem_io_addr_base,
soc_map$m_near_mem_io_addr_lim,
soc_map$m_plic_addr_base,
soc_map$m_plic_addr_lim;
// rule scheduling signals
wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5,
CAN_FIRE_RL_fabric_rl_reset,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1,
CAN_FIRE_reset,
CAN_FIRE_set_verbosity,
CAN_FIRE_v_from_masters_0_m_arvalid,
CAN_FIRE_v_from_masters_0_m_awvalid,
CAN_FIRE_v_from_masters_0_m_bready,
CAN_FIRE_v_from_masters_0_m_rready,
CAN_FIRE_v_from_masters_0_m_wvalid,
CAN_FIRE_v_from_masters_1_m_arvalid,
CAN_FIRE_v_from_masters_1_m_awvalid,
CAN_FIRE_v_from_masters_1_m_bready,
CAN_FIRE_v_from_masters_1_m_rready,
CAN_FIRE_v_from_masters_1_m_wvalid,
CAN_FIRE_v_to_slaves_0_m_arready,
CAN_FIRE_v_to_slaves_0_m_awready,
CAN_FIRE_v_to_slaves_0_m_bvalid,
CAN_FIRE_v_to_slaves_0_m_rvalid,
CAN_FIRE_v_to_slaves_0_m_wready,
CAN_FIRE_v_to_slaves_1_m_arready,
CAN_FIRE_v_to_slaves_1_m_awready,
CAN_FIRE_v_to_slaves_1_m_bvalid,
CAN_FIRE_v_to_slaves_1_m_rvalid,
CAN_FIRE_v_to_slaves_1_m_wready,
CAN_FIRE_v_to_slaves_2_m_arready,
CAN_FIRE_v_to_slaves_2_m_awready,
CAN_FIRE_v_to_slaves_2_m_bvalid,
CAN_FIRE_v_to_slaves_2_m_rvalid,
CAN_FIRE_v_to_slaves_2_m_wready,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5,
WILL_FIRE_RL_fabric_rl_reset,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1,
WILL_FIRE_reset,
WILL_FIRE_set_verbosity,
WILL_FIRE_v_from_masters_0_m_arvalid,
WILL_FIRE_v_from_masters_0_m_awvalid,
WILL_FIRE_v_from_masters_0_m_bready,
WILL_FIRE_v_from_masters_0_m_rready,
WILL_FIRE_v_from_masters_0_m_wvalid,
WILL_FIRE_v_from_masters_1_m_arvalid,
WILL_FIRE_v_from_masters_1_m_awvalid,
WILL_FIRE_v_from_masters_1_m_bready,
WILL_FIRE_v_from_masters_1_m_rready,
WILL_FIRE_v_from_masters_1_m_wvalid,
WILL_FIRE_v_to_slaves_0_m_arready,
WILL_FIRE_v_to_slaves_0_m_awready,
WILL_FIRE_v_to_slaves_0_m_bvalid,
WILL_FIRE_v_to_slaves_0_m_rvalid,
WILL_FIRE_v_to_slaves_0_m_wready,
WILL_FIRE_v_to_slaves_1_m_arready,
WILL_FIRE_v_to_slaves_1_m_awready,
WILL_FIRE_v_to_slaves_1_m_bvalid,
WILL_FIRE_v_to_slaves_1_m_rvalid,
WILL_FIRE_v_to_slaves_1_m_wready,
WILL_FIRE_v_to_slaves_2_m_arready,
WILL_FIRE_v_to_slaves_2_m_awready,
WILL_FIRE_v_to_slaves_2_m_bvalid,
WILL_FIRE_v_to_slaves_2_m_rvalid,
WILL_FIRE_v_to_slaves_2_m_wready;
// inputs to muxes for submodule ports
wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4,
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4;
wire [9 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1,
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3;
wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2;
wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4,
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4;
wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1,
MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1,
MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h8466;
reg [31 : 0] v__h8813;
reg [31 : 0] v__h9160;
reg [31 : 0] v__h9570;
reg [31 : 0] v__h9911;
reg [31 : 0] v__h10252;
reg [31 : 0] v__h11228;
reg [31 : 0] v__h11475;
reg [31 : 0] v__h11829;
reg [31 : 0] v__h12076;
reg [31 : 0] v__h12433;
reg [31 : 0] v__h12703;
reg [31 : 0] v__h12973;
reg [31 : 0] v__h13247;
reg [31 : 0] v__h13491;
reg [31 : 0] v__h13735;
reg [31 : 0] v__h13969;
reg [31 : 0] v__h14179;
reg [31 : 0] v__h14579;
reg [31 : 0] v__h14913;
reg [31 : 0] v__h15247;
reg [31 : 0] v__h15635;
reg [31 : 0] v__h15945;
reg [31 : 0] v__h16255;
reg [31 : 0] v__h17211;
reg [31 : 0] v__h17492;
reg [31 : 0] v__h17860;
reg [31 : 0] v__h18131;
reg [31 : 0] v__h18499;
reg [31 : 0] v__h18770;
reg [31 : 0] v__h19118;
reg [31 : 0] v__h19399;
reg [31 : 0] v__h19722;
reg [31 : 0] v__h19993;
reg [31 : 0] v__h20316;
reg [31 : 0] v__h20587;
reg [31 : 0] v__h21067;
reg [31 : 0] v__h21449;
reg [31 : 0] v__h5786;
reg [31 : 0] v__h5780;
reg [31 : 0] v__h8460;
reg [31 : 0] v__h8807;
reg [31 : 0] v__h9154;
reg [31 : 0] v__h9564;
reg [31 : 0] v__h9905;
reg [31 : 0] v__h10246;
reg [31 : 0] v__h11222;
reg [31 : 0] v__h11469;
reg [31 : 0] v__h11823;
reg [31 : 0] v__h12070;
reg [31 : 0] v__h12427;
reg [31 : 0] v__h12697;
reg [31 : 0] v__h12967;
reg [31 : 0] v__h13241;
reg [31 : 0] v__h13485;
reg [31 : 0] v__h13729;
reg [31 : 0] v__h13963;
reg [31 : 0] v__h14173;
reg [31 : 0] v__h14573;
reg [31 : 0] v__h14907;
reg [31 : 0] v__h15241;
reg [31 : 0] v__h15629;
reg [31 : 0] v__h15939;
reg [31 : 0] v__h16249;
reg [31 : 0] v__h17205;
reg [31 : 0] v__h17486;
reg [31 : 0] v__h17854;
reg [31 : 0] v__h18125;
reg [31 : 0] v__h18493;
reg [31 : 0] v__h18764;
reg [31 : 0] v__h19112;
reg [31 : 0] v__h19393;
reg [31 : 0] v__h19716;
reg [31 : 0] v__h19987;
reg [31 : 0] v__h20310;
reg [31 : 0] v__h20581;
reg [31 : 0] v__h21061;
reg [31 : 0] v__h21443;
// synopsys translate_on
// remaining internal signals
reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1,
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2;
wire [7 : 0] x__h11377,
x__h11978,
x__h17375,
x__h18024,
x__h18663,
x__h21004,
x__h21386;
wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403,
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438,
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473,
x1_avValue_rresp__h17353,
x1_avValue_rresp__h18002,
x1_avValue_rresp__h18641;
wire _dor1fabric_v_f_rd_mis_0$EN_deq,
_dor1fabric_v_f_rd_mis_1$EN_deq,
_dor1fabric_v_f_rd_mis_2$EN_deq,
fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130,
fabric_v_f_wd_tasks_1_i_notEmpty__53_AND_fabri_ETC___d159,
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387,
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422,
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457,
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522,
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540,
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146,
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86;
// action method reset
assign RDY_reset = !fabric_rg_reset ;
assign CAN_FIRE_reset = !fabric_rg_reset ;
assign WILL_FIRE_reset = EN_reset ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method v_from_masters_0_m_awvalid
assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
// value method v_from_masters_0_m_awready
assign v_from_masters_0_awready =
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
// action method v_from_masters_0_m_wvalid
assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
// value method v_from_masters_0_m_wready
assign v_from_masters_0_wready =
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
// value method v_from_masters_0_m_bvalid
assign v_from_masters_0_bvalid =
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
// value method v_from_masters_0_m_bid
assign v_from_masters_0_bid =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ;
// value method v_from_masters_0_m_bresp
assign v_from_masters_0_bresp =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_0_m_bready
assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ;
// action method v_from_masters_0_m_arvalid
assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
// value method v_from_masters_0_m_arready
assign v_from_masters_0_arready =
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
// value method v_from_masters_0_m_rvalid
assign v_from_masters_0_rvalid =
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
// value method v_from_masters_0_m_rid
assign v_from_masters_0_rid =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ;
// value method v_from_masters_0_m_rdata
assign v_from_masters_0_rdata =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_0_m_rresp
assign v_from_masters_0_rresp =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_0_m_rlast
assign v_from_masters_0_rlast =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ;
// action method v_from_masters_0_m_rready
assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ;
// action method v_from_masters_1_m_awvalid
assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ;
// value method v_from_masters_1_m_awready
assign v_from_masters_1_awready =
fabric_xactors_from_masters_1_f_wr_addr$FULL_N ;
// action method v_from_masters_1_m_wvalid
assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ;
// value method v_from_masters_1_m_wready
assign v_from_masters_1_wready =
fabric_xactors_from_masters_1_f_wr_data$FULL_N ;
// value method v_from_masters_1_m_bvalid
assign v_from_masters_1_bvalid =
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ;
// value method v_from_masters_1_m_bid
assign v_from_masters_1_bid =
fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ;
// value method v_from_masters_1_m_bresp
assign v_from_masters_1_bresp =
fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_1_m_bready
assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ;
// action method v_from_masters_1_m_arvalid
assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ;
// value method v_from_masters_1_m_arready
assign v_from_masters_1_arready =
fabric_xactors_from_masters_1_f_rd_addr$FULL_N ;
// value method v_from_masters_1_m_rvalid
assign v_from_masters_1_rvalid =
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ;
// value method v_from_masters_1_m_rid
assign v_from_masters_1_rid =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ;
// value method v_from_masters_1_m_rdata
assign v_from_masters_1_rdata =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_1_m_rresp
assign v_from_masters_1_rresp =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_1_m_rlast
assign v_from_masters_1_rlast =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ;
// action method v_from_masters_1_m_rready
assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ;
// value method v_to_slaves_0_m_awvalid
assign v_to_slaves_0_awvalid =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_0_m_awid
assign v_to_slaves_0_awid =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_0_m_awaddr
assign v_to_slaves_0_awaddr =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_awlen
assign v_to_slaves_0_awlen =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_awsize
assign v_to_slaves_0_awsize =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_awburst
assign v_to_slaves_0_awburst =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_awlock
assign v_to_slaves_0_awlock =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_awcache
assign v_to_slaves_0_awcache =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_awprot
assign v_to_slaves_0_awprot =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_awqos
assign v_to_slaves_0_awqos =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_awregion
assign v_to_slaves_0_awregion =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_awready
assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
// value method v_to_slaves_0_m_wvalid
assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ;
// value method v_to_slaves_0_m_wdata
assign v_to_slaves_0_wdata =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_0_m_wstrb
assign v_to_slaves_0_wstrb =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_0_m_wlast
assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_0_m_wready
assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
// action method v_to_slaves_0_m_bvalid
assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
// value method v_to_slaves_0_m_bready
assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
// value method v_to_slaves_0_m_arvalid
assign v_to_slaves_0_arvalid =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_0_m_arid
assign v_to_slaves_0_arid =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_0_m_araddr
assign v_to_slaves_0_araddr =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_arlen
assign v_to_slaves_0_arlen =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_arsize
assign v_to_slaves_0_arsize =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_arburst
assign v_to_slaves_0_arburst =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_arlock
assign v_to_slaves_0_arlock =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_arcache
assign v_to_slaves_0_arcache =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_arprot
assign v_to_slaves_0_arprot =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_arqos
assign v_to_slaves_0_arqos =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_arregion
assign v_to_slaves_0_arregion =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_arready
assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
// action method v_to_slaves_0_m_rvalid
assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
// value method v_to_slaves_0_m_rready
assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
// value method v_to_slaves_1_m_awvalid
assign v_to_slaves_1_awvalid =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_1_m_awid
assign v_to_slaves_1_awid =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_1_m_awaddr
assign v_to_slaves_1_awaddr =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_awlen
assign v_to_slaves_1_awlen =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_awsize
assign v_to_slaves_1_awsize =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_awburst
assign v_to_slaves_1_awburst =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_awlock
assign v_to_slaves_1_awlock =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_awcache
assign v_to_slaves_1_awcache =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_awprot
assign v_to_slaves_1_awprot =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_awqos
assign v_to_slaves_1_awqos =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_awregion
assign v_to_slaves_1_awregion =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_awready
assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
// value method v_to_slaves_1_m_wvalid
assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ;
// value method v_to_slaves_1_m_wdata
assign v_to_slaves_1_wdata =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_1_m_wstrb
assign v_to_slaves_1_wstrb =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_1_m_wlast
assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_1_m_wready
assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
// action method v_to_slaves_1_m_bvalid
assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
// value method v_to_slaves_1_m_bready
assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
// value method v_to_slaves_1_m_arvalid
assign v_to_slaves_1_arvalid =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_1_m_arid
assign v_to_slaves_1_arid =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_1_m_araddr
assign v_to_slaves_1_araddr =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_arlen
assign v_to_slaves_1_arlen =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_arsize
assign v_to_slaves_1_arsize =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_arburst
assign v_to_slaves_1_arburst =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_arlock
assign v_to_slaves_1_arlock =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_arcache
assign v_to_slaves_1_arcache =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_arprot
assign v_to_slaves_1_arprot =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_arqos
assign v_to_slaves_1_arqos =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_arregion
assign v_to_slaves_1_arregion =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_arready
assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
// action method v_to_slaves_1_m_rvalid
assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
// value method v_to_slaves_1_m_rready
assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
// value method v_to_slaves_2_m_awvalid
assign v_to_slaves_2_awvalid =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_2_m_awid
assign v_to_slaves_2_awid =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_2_m_awaddr
assign v_to_slaves_2_awaddr =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_awlen
assign v_to_slaves_2_awlen =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_awsize
assign v_to_slaves_2_awsize =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_awburst
assign v_to_slaves_2_awburst =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_awlock
assign v_to_slaves_2_awlock =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_awcache
assign v_to_slaves_2_awcache =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_awprot
assign v_to_slaves_2_awprot =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_awqos
assign v_to_slaves_2_awqos =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_awregion
assign v_to_slaves_2_awregion =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_awready
assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
// value method v_to_slaves_2_m_wvalid
assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ;
// value method v_to_slaves_2_m_wdata
assign v_to_slaves_2_wdata =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_2_m_wstrb
assign v_to_slaves_2_wstrb =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_2_m_wlast
assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_2_m_wready
assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
// action method v_to_slaves_2_m_bvalid
assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
// value method v_to_slaves_2_m_bready
assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
// value method v_to_slaves_2_m_arvalid
assign v_to_slaves_2_arvalid =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_2_m_arid
assign v_to_slaves_2_arid =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_2_m_araddr
assign v_to_slaves_2_araddr =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_arlen
assign v_to_slaves_2_arlen =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_arsize
assign v_to_slaves_2_arsize =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_arburst
assign v_to_slaves_2_arburst =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_arlock
assign v_to_slaves_2_arlock =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_arcache
assign v_to_slaves_2_arcache =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_arprot
assign v_to_slaves_2_arprot =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_arqos
assign v_to_slaves_2_arqos =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_arregion
assign v_to_slaves_2_arregion =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_arready
assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
// action method v_to_slaves_2_m_rvalid
assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
// value method v_to_slaves_2_m_rready
assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
// submodule fabric_v_f_rd_err_info_0
SizedFIFO #(.p1width(32'd12),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_0$D_IN),
.ENQ(fabric_v_f_rd_err_info_0$ENQ),
.DEQ(fabric_v_f_rd_err_info_0$DEQ),
.CLR(fabric_v_f_rd_err_info_0$CLR),
.D_OUT(fabric_v_f_rd_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N));
// submodule fabric_v_f_rd_err_info_1
SizedFIFO #(.p1width(32'd12),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_1$D_IN),
.ENQ(fabric_v_f_rd_err_info_1$ENQ),
.DEQ(fabric_v_f_rd_err_info_1$DEQ),
.CLR(fabric_v_f_rd_err_info_1$CLR),
.D_OUT(fabric_v_f_rd_err_info_1$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_0
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_0$D_IN),
.ENQ(fabric_v_f_rd_mis_0$ENQ),
.DEQ(fabric_v_f_rd_mis_0$DEQ),
.CLR(fabric_v_f_rd_mis_0$CLR),
.D_OUT(fabric_v_f_rd_mis_0$D_OUT),
.FULL_N(fabric_v_f_rd_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_1
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_1$D_IN),
.ENQ(fabric_v_f_rd_mis_1$ENQ),
.DEQ(fabric_v_f_rd_mis_1$DEQ),
.CLR(fabric_v_f_rd_mis_1$CLR),
.D_OUT(fabric_v_f_rd_mis_1$D_OUT),
.FULL_N(fabric_v_f_rd_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_2
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_2$D_IN),
.ENQ(fabric_v_f_rd_mis_2$ENQ),
.DEQ(fabric_v_f_rd_mis_2$DEQ),
.CLR(fabric_v_f_rd_mis_2$CLR),
.D_OUT(fabric_v_f_rd_mis_2$D_OUT),
.FULL_N(fabric_v_f_rd_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N));
// submodule fabric_v_f_rd_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_0$D_IN),
.ENQ(fabric_v_f_rd_sjs_0$ENQ),
.DEQ(fabric_v_f_rd_sjs_0$DEQ),
.CLR(fabric_v_f_rd_sjs_0$CLR),
.D_OUT(fabric_v_f_rd_sjs_0$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N));
// submodule fabric_v_f_rd_sjs_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_1$D_IN),
.ENQ(fabric_v_f_rd_sjs_1$ENQ),
.DEQ(fabric_v_f_rd_sjs_1$DEQ),
.CLR(fabric_v_f_rd_sjs_1$CLR),
.D_OUT(fabric_v_f_rd_sjs_1$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N));
// submodule fabric_v_f_wd_tasks_0
FIFO2 #(.width(32'd10), .guarded(1'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_0$D_IN),
.ENQ(fabric_v_f_wd_tasks_0$ENQ),
.DEQ(fabric_v_f_wd_tasks_0$DEQ),
.CLR(fabric_v_f_wd_tasks_0$CLR),
.D_OUT(fabric_v_f_wd_tasks_0$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_0$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N));
// submodule fabric_v_f_wd_tasks_1
FIFO2 #(.width(32'd10), .guarded(1'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_1$D_IN),
.ENQ(fabric_v_f_wd_tasks_1$ENQ),
.DEQ(fabric_v_f_wd_tasks_1$DEQ),
.CLR(fabric_v_f_wd_tasks_1$CLR),
.D_OUT(fabric_v_f_wd_tasks_1$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_1$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N));
// submodule fabric_v_f_wr_err_info_0
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_0$D_IN),
.ENQ(fabric_v_f_wr_err_info_0$ENQ),
.DEQ(fabric_v_f_wr_err_info_0$DEQ),
.CLR(fabric_v_f_wr_err_info_0$CLR),
.D_OUT(fabric_v_f_wr_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N));
// submodule fabric_v_f_wr_err_info_1
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_1$D_IN),
.ENQ(fabric_v_f_wr_err_info_1$ENQ),
.DEQ(fabric_v_f_wr_err_info_1$DEQ),
.CLR(fabric_v_f_wr_err_info_1$CLR),
.D_OUT(fabric_v_f_wr_err_info_1$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_0$D_IN),
.ENQ(fabric_v_f_wr_mis_0$ENQ),
.DEQ(fabric_v_f_wr_mis_0$DEQ),
.CLR(fabric_v_f_wr_mis_0$CLR),
.D_OUT(fabric_v_f_wr_mis_0$D_OUT),
.FULL_N(fabric_v_f_wr_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_1$D_IN),
.ENQ(fabric_v_f_wr_mis_1$ENQ),
.DEQ(fabric_v_f_wr_mis_1$DEQ),
.CLR(fabric_v_f_wr_mis_1$CLR),
.D_OUT(fabric_v_f_wr_mis_1$D_OUT),
.FULL_N(fabric_v_f_wr_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_2
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_2$D_IN),
.ENQ(fabric_v_f_wr_mis_2$ENQ),
.DEQ(fabric_v_f_wr_mis_2$DEQ),
.CLR(fabric_v_f_wr_mis_2$CLR),
.D_OUT(fabric_v_f_wr_mis_2$D_OUT),
.FULL_N(fabric_v_f_wr_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N));
// submodule fabric_v_f_wr_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_0$D_IN),
.ENQ(fabric_v_f_wr_sjs_0$ENQ),
.DEQ(fabric_v_f_wr_sjs_0$DEQ),
.CLR(fabric_v_f_wr_sjs_0$CLR),
.D_OUT(fabric_v_f_wr_sjs_0$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N));
// submodule fabric_v_f_wr_sjs_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_1$D_IN),
.ENQ(fabric_v_f_wr_sjs_1$ENQ),
.DEQ(fabric_v_f_wr_sjs_1$DEQ),
.CLR(fabric_v_f_wr_sjs_1$CLR),
.D_OUT(fabric_v_f_wr_sjs_1$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(1'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim),
.m_plic_addr_base(soc_map$m_plic_addr_base),
.m_plic_addr_size(),
.m_plic_addr_lim(soc_map$m_plic_addr_lim),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_fabric_rl_wr_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29) ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_3
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 =
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88) ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_4
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 =
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_5
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 =
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 =
fabric_xactors_from_masters_1_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_1_i_notEmpty__53_AND_fabri_ETC___d159 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_0$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
// rule RL_fabric_rl_wr_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_mis_1$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_mis_2$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_3
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 =
fabric_v_f_wr_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_0$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_4
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 =
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_5
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 =
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ;
// rule RL_fabric_rl_wr_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_0$EMPTY_N &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
// rule RL_fabric_rl_wr_resp_err_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 =
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_1$EMPTY_N &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291) ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_3
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 =
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341) ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_4
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 =
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_5
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 =
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_0$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
// rule RL_fabric_rl_rd_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_1$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_2$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_3
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_0$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_4
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 =
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_1$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_5
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 =
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_2$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ;
// rule RL_fabric_rl_rd_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master =
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_0$EMPTY_N &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// rule RL_fabric_rl_rd_resp_err_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 =
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_1$EMPTY_N &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
// rule RL_fabric_rl_reset
assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
// inputs to muxes for submodule ports
assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ;
assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ;
assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ;
assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 =
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ?
8'd0 :
x__h17375 ;
assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 =
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ?
8'd0 :
x__h18024 ;
assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 =
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ?
8'd0 :
x__h18663 ;
assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 ?
8'd0 :
x__h11377 ;
assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 ?
8'd0 :
x__h11978 ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 =
{ fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 =
{ fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 =
{ fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_0$D_OUT[3:0],
66'd3,
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 } ;
assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ;
assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_1$D_OUT[3:0],
66'd3,
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 } ;
assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ;
// register fabric_cfg_verbosity
assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign fabric_cfg_verbosity$EN = EN_set_verbosity ;
// register fabric_rg_reset
assign fabric_rg_reset$D_IN = !fabric_rg_reset ;
assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ;
// register fabric_v_rg_r_beat_count_0
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3:
fabric_v_rg_r_beat_count_0$D_IN =
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_v_rg_r_beat_count_0$D_IN =
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_0$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_1
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4:
fabric_v_rg_r_beat_count_1$D_IN =
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_v_rg_r_beat_count_1$D_IN =
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_1$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_2
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5:
fabric_v_rg_r_beat_count_2$D_IN =
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_v_rg_r_beat_count_2$D_IN =
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_2$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_2$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
fabric_rg_reset ;
// register fabric_v_rg_r_err_beat_count_0
assign fabric_v_rg_r_err_beat_count_0$D_IN =
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ?
8'd0 :
x__h21004 ;
assign fabric_v_rg_r_err_beat_count_0$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// register fabric_v_rg_r_err_beat_count_1
assign fabric_v_rg_r_err_beat_count_1$D_IN =
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ?
8'd0 :
x__h21386 ;
assign fabric_v_rg_r_err_beat_count_1$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
// register fabric_v_rg_wd_beat_count_0
assign fabric_v_rg_wd_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ||
fabric_rg_reset ;
// register fabric_v_rg_wd_beat_count_1
assign fabric_v_rg_wd_beat_count_1$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ||
fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_0
assign fabric_v_f_rd_err_info_0$D_IN = 12'h0 ;
assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_rd_err_info_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ;
assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_1
assign fabric_v_f_rd_err_info_1$D_IN = 12'h0 ;
assign fabric_v_f_rd_err_info_1$ENQ = 1'b0 ;
assign fabric_v_f_rd_err_info_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ;
assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_0
assign fabric_v_f_rd_mis_0$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_v_f_rd_mis_0$DEQ =
_dor1fabric_v_f_rd_mis_0$EN_deq &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ;
assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_1
assign fabric_v_f_rd_mis_1$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_1$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ;
assign fabric_v_f_rd_mis_1$DEQ =
_dor1fabric_v_f_rd_mis_1$EN_deq &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ;
assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_2
assign fabric_v_f_rd_mis_2$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_2$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_v_f_rd_mis_2$DEQ =
_dor1fabric_v_f_rd_mis_2$EN_deq &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ;
assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_0
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave:
fabric_v_f_rd_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1:
fabric_v_f_rd_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2:
fabric_v_f_rd_sjs_0$D_IN = 2'd2;
default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_v_f_rd_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 ;
assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_1
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3:
fabric_v_f_rd_sjs_1$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4:
fabric_v_f_rd_sjs_1$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5:
fabric_v_f_rd_sjs_1$D_IN = 2'd2;
default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_1$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_v_f_rd_sjs_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 ;
assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
default: fabric_v_f_wd_tasks_0$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wd_tasks_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 ;
assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_1
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3;
default: fabric_v_f_wd_tasks_1$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wd_tasks_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 ;
assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_0
assign fabric_v_f_wr_err_info_0$D_IN = 4'h0 ;
assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_wr_err_info_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_1
assign fabric_v_f_wr_err_info_1$D_IN = 4'h0 ;
assign fabric_v_f_wr_err_info_1$ENQ = 1'b0 ;
assign fabric_v_f_wr_err_info_1$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_0
assign fabric_v_f_wr_mis_0$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? 2'd0 : 2'd1 ;
assign fabric_v_f_wr_mis_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_v_f_wr_mis_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_1
assign fabric_v_f_wr_mis_1$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ?
2'd0 :
2'd1 ;
assign fabric_v_f_wr_mis_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ;
assign fabric_v_f_wr_mis_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_2
assign fabric_v_f_wr_mis_2$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ?
2'd0 :
2'd1 ;
assign fabric_v_f_wr_mis_2$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wr_mis_2$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wr_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wr_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wr_sjs_0$D_IN = 2'd2;
default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wr_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_1
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3:
fabric_v_f_wr_sjs_1$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4:
fabric_v_f_wr_sjs_1$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5:
fabric_v_f_wr_sjs_1$D_IN = 2'd2;
default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wr_sjs_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ;
assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_addr
assign fabric_xactors_from_masters_0_f_rd_addr$D_IN =
{ v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion } ;
assign fabric_xactors_from_masters_0_f_rd_addr$ENQ =
v_from_masters_0_arvalid &&
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_rd_data$D_IN =
71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_rd_data$DEQ =
v_from_masters_0_rready &&
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_addr
assign fabric_xactors_from_masters_0_f_wr_addr$D_IN =
{ v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion } ;
assign fabric_xactors_from_masters_0_f_wr_addr$ENQ =
v_from_masters_0_awvalid &&
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_data
assign fabric_xactors_from_masters_0_f_wr_data$D_IN =
{ v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast } ;
assign fabric_xactors_from_masters_0_f_wr_data$ENQ =
v_from_masters_0_wvalid &&
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_data$DEQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_wr_resp$D_IN =
6'b101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_wr_resp$DEQ =
v_from_masters_0_bready &&
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_rd_addr
assign fabric_xactors_from_masters_1_f_rd_addr$D_IN =
{ v_from_masters_1_arid,
v_from_masters_1_araddr,
v_from_masters_1_arlen,
v_from_masters_1_arsize,
v_from_masters_1_arburst,
v_from_masters_1_arlock,
v_from_masters_1_arcache,
v_from_masters_1_arprot,
v_from_masters_1_arqos,
v_from_masters_1_arregion } ;
assign fabric_xactors_from_masters_1_f_rd_addr$ENQ =
v_from_masters_1_arvalid &&
fabric_xactors_from_masters_1_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_1_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_1_f_rd_data$D_IN =
71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_1_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
assign fabric_xactors_from_masters_1_f_rd_data$DEQ =
v_from_masters_1_rready &&
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_addr
assign fabric_xactors_from_masters_1_f_wr_addr$D_IN =
{ v_from_masters_1_awid,
v_from_masters_1_awaddr,
v_from_masters_1_awlen,
v_from_masters_1_awsize,
v_from_masters_1_awburst,
v_from_masters_1_awlock,
v_from_masters_1_awcache,
v_from_masters_1_awprot,
v_from_masters_1_awqos,
v_from_masters_1_awregion } ;
assign fabric_xactors_from_masters_1_f_wr_addr$ENQ =
v_from_masters_1_awvalid &&
fabric_xactors_from_masters_1_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_1_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_data
assign fabric_xactors_from_masters_1_f_wr_data$D_IN =
{ v_from_masters_1_wdata,
v_from_masters_1_wstrb,
v_from_masters_1_wlast } ;
assign fabric_xactors_from_masters_1_f_wr_data$ENQ =
v_from_masters_1_wvalid &&
fabric_xactors_from_masters_1_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_1_f_wr_data$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ;
assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_1_f_wr_resp$D_IN =
6'b101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_1_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
assign fabric_xactors_from_masters_1_f_wr_resp$DEQ =
v_from_masters_1_bready &&
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_addr
assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N &&
v_to_slaves_0_arready ;
assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_data
assign fabric_xactors_to_slaves_0_f_rd_data$D_IN =
{ v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast } ;
assign fabric_xactors_to_slaves_0_f_rd_data$ENQ =
v_to_slaves_0_rvalid &&
fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_0_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_addr
assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N &&
v_to_slaves_0_awready ;
assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_data
assign fabric_xactors_to_slaves_0_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ;
assign fabric_xactors_to_slaves_0_f_wr_data$DEQ =
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N &&
v_to_slaves_0_wready ;
assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_resp
assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN =
{ v_to_slaves_0_bid, v_to_slaves_0_bresp } ;
assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ =
v_to_slaves_0_bvalid &&
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_addr
assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ;
assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N &&
v_to_slaves_1_arready ;
assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_data
assign fabric_xactors_to_slaves_1_f_rd_data$D_IN =
{ v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast } ;
assign fabric_xactors_to_slaves_1_f_rd_data$ENQ =
v_to_slaves_1_rvalid &&
fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_1_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_addr
assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ;
assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N &&
v_to_slaves_1_awready ;
assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_data
assign fabric_xactors_to_slaves_1_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ;
assign fabric_xactors_to_slaves_1_f_wr_data$DEQ =
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N &&
v_to_slaves_1_wready ;
assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_resp
assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN =
{ v_to_slaves_1_bid, v_to_slaves_1_bresp } ;
assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ =
v_to_slaves_1_bvalid &&
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_addr
assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N &&
v_to_slaves_2_arready ;
assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_data
assign fabric_xactors_to_slaves_2_f_rd_data$D_IN =
{ v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast } ;
assign fabric_xactors_to_slaves_2_f_rd_data$ENQ =
v_to_slaves_2_rvalid &&
fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_2_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_addr
assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N &&
v_to_slaves_2_awready ;
assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_data
assign fabric_xactors_to_slaves_2_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ;
assign fabric_xactors_to_slaves_2_f_wr_data$DEQ =
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N &&
v_to_slaves_2_wready ;
assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_resp
assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN =
{ v_to_slaves_2_bid, v_to_slaves_2_bresp } ;
assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ =
v_to_slaves_2_bvalid &&
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403 =
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 ?
x1_avValue_rresp__h17353 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438 =
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 ?
x1_avValue_rresp__h18002 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473 =
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 ?
x1_avValue_rresp__h18641 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign _dor1fabric_v_f_rd_mis_0$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign _dor1fabric_v_f_rd_mis_1$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign _dor1fabric_v_f_rd_mis_2$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_v_f_wd_tasks_0_i_notEmpty__21_AND_fabri_ETC___d130 =
fabric_v_f_wd_tasks_0$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ;
assign fabric_v_f_wd_tasks_1_i_notEmpty__53_AND_fabri_ETC___d159 =
fabric_v_f_wd_tasks_1$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ;
assign fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 =
fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 =
fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 =
fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ;
assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522 =
fabric_v_rg_r_err_beat_count_0 ==
fabric_v_f_rd_err_info_0$D_OUT[11:4] ;
assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540 =
fabric_v_rg_r_err_beat_count_1 ==
fabric_v_f_rd_err_info_1$D_OUT[11:4] ;
assign fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 =
fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ;
assign fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 =
fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d286 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d291 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d336 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d341 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d83 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d88 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d284 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d334 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d81 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d289 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d339 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d86 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ;
assign x1_avValue_rresp__h17353 =
(fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h18002 =
(fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h18641 =
(fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign x__h11377 = fabric_v_rg_wd_beat_count_0 + 8'd1 ;
assign x__h11978 = fabric_v_rg_wd_beat_count_1 + 8'd1 ;
assign x__h17375 = fabric_v_rg_r_beat_count_0 + 8'd1 ;
assign x__h18024 = fabric_v_rg_r_beat_count_1 + 8'd1 ;
assign x__h18663 = fabric_v_rg_r_beat_count_2 + 8'd1 ;
assign x__h21004 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ;
assign x__h21386 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ;
always@(fabric_v_f_wd_tasks_0$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_0$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1;
endcase
end
always@(fabric_v_f_wd_tasks_1$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_1$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (fabric_cfg_verbosity$EN)
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
fabric_cfg_verbosity$D_IN;
if (fabric_rg_reset$EN)
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN;
if (fabric_v_rg_r_beat_count_0$EN)
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_0$D_IN;
if (fabric_v_rg_r_beat_count_1$EN)
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_1$D_IN;
if (fabric_v_rg_r_beat_count_2$EN)
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_2$D_IN;
if (fabric_v_rg_r_err_beat_count_0$EN)
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_0$D_IN;
if (fabric_v_rg_r_err_beat_count_1$EN)
fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_1$D_IN;
if (fabric_v_rg_wd_beat_count_0$EN)
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_0$D_IN;
if (fabric_v_rg_wd_beat_count_1$EN)
fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_1$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
fabric_cfg_verbosity = 4'hA;
fabric_rg_reset = 1'h0;
fabric_v_rg_r_beat_count_0 = 8'hAA;
fabric_v_rg_r_beat_count_1 = 8'hAA;
fabric_v_rg_r_beat_count_2 = 8'hAA;
fabric_v_rg_r_err_beat_count_0 = 8'hAA;
fabric_v_rg_r_err_beat_count_1 = 8'hAA;
fabric_v_rg_wd_beat_count_0 = 8'hAA;
fabric_v_rg_wd_beat_count_1 = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8466 = $stime;
#0;
end
v__h8460 = v__h8466 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h8460,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8813 = $stime;
#0;
end
v__h8807 = v__h8813 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h8807,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9160 = $stime;
#0;
end
v__h9154 = v__h9160 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9154,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9570 = $stime;
#0;
end
v__h9564 = v__h9570 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9564,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9911 = $stime;
#0;
end
v__h9905 = v__h9911 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9905,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10252 = $stime;
#0;
end
v__h10246 = v__h10252 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h10246,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11228 = $stime;
#0;
end
v__h11222 = v__h11228 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
v__h11222,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8],
fabric_v_rg_wd_beat_count_0,
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
begin
v__h11475 = $stime;
#0;
end
v__h11469 = v__h11475 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h11469,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_38_EQ_fabric_v_f_w_ETC___d146 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11829 = $stime;
#0;
end
v__h11823 = v__h11829 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
v__h11823,
$signed(32'd1),
fabric_v_f_wd_tasks_1$D_OUT[9:8],
fabric_v_rg_wd_beat_count_1,
fabric_v_f_wd_tasks_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
begin
v__h12076 = $stime;
#0;
end
v__h12070 = v__h12076 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h12070,
$signed(32'd1),
fabric_v_f_wd_tasks_1$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_67_EQ_fabric_v_f_w_ETC___d175 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12433 = $stime;
#0;
end
v__h12427 = v__h12433 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h12427,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12703 = $stime;
#0;
end
v__h12697 = v__h12703 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h12697,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12973 = $stime;
#0;
end
v__h12967 = v__h12973 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h12967,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13247 = $stime;
#0;
end
v__h13241 = v__h13247 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13241,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13491 = $stime;
#0;
end
v__h13485 = v__h13491 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13485,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13735 = $stime;
#0;
end
v__h13729 = v__h13735 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13729,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13969 = $stime;
#0;
end
v__h13963 = v__h13969 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h13963,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_0$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14179 = $stime;
#0;
end
v__h14173 = v__h14179 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h14173,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_1$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14579 = $stime;
#0;
end
v__h14573 = v__h14579 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h14573,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14913 = $stime;
#0;
end
v__h14907 = v__h14913 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h14907,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15247 = $stime;
#0;
end
v__h15241 = v__h15247 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15241,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15635 = $stime;
#0;
end
v__h15629 = v__h15635 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15629,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15945 = $stime;
#0;
end
v__h15939 = v__h15945 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15939,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h16255 = $stime;
#0;
end
v__h16249 = v__h16255 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h16249,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h17211 = $stime;
#0;
end
v__h17205 = v__h17211 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h17205,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h17492 = $stime;
#0;
end
v__h17486 = v__h17492 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h17486,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h17860 = $stime;
#0;
end
v__h17854 = v__h17860 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h17854,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h18131 = $stime;
#0;
end
v__h18125 = v__h18131 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h18125,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h18499 = $stime;
#0;
end
v__h18493 = v__h18499 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h18493,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h18770 = $stime;
#0;
end
v__h18764 = v__h18770 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h18764,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h19118 = $stime;
#0;
end
v__h19112 = v__h19118 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h19112,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d387 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h19399 = $stime;
#0;
end
v__h19393 = v__h19399 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h19393,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d403);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h19722 = $stime;
#0;
end
v__h19716 = v__h19722 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h19716,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d422 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h19993 = $stime;
#0;
end
v__h19987 = v__h19993 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h19987,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d438);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h20316 = $stime;
#0;
end
v__h20310 = v__h20316 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h20310,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d457 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h20587 = $stime;
#0;
end
v__h20581 = v__h20587 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h20581,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d473);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21067 = $stime;
#0;
end
v__h21061 = v__h21067 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h21061,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d522)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21449 = $stime;
#0;
end
v__h21443 = v__h21449 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h21443,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d540)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
begin
v__h5786 = $stime;
#0;
end
v__h5780 = v__h5786 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_reset", v__h5780);
end
// synopsys translate_on
endmodule // mkFabric_2x3
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTN_1_V
`define SKY130_FD_SC_MS__SDFRTN_1_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog wrapper for sdfrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTN_1_V
|
/******************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: Branch prediction module
Generates a predicted flag output and compares that to the real flag
when it comes back in the following pipeline stage.
Signals are deliberately not named after the pipeline stage they belong to,
in order to keep this module generic.
Copyright (C) 2013 Stefan Kristiansson <[email protected]>
Copyright (C) 2016 Alexey Baturo <[email protected]>
******************************************************************************/
`include "mor1kx-defines.v"
module mor1kx_branch_prediction
#(
parameter FEATURE_BRANCH_PREDICTOR = "NONE"
)
(
input clk,
input rst,
// Signals belonging to the stage where the branch is predicted.
input op_bf_i, // from decode stage, brn is bf
input op_bnf_i, // from decode stage, brn is bnf
input [9:0] immjbr_upper_i, // from decode stage, imm
output predicted_flag_o, // to decode-execute stage, flag we predict to be
// Signals belonging to the stage where the branch is resolved.
input prev_op_brcond_i, // from decode-execute stage, prev brn was cond
input prev_predicted_flag_i, // from decode-execute, prev predicted flag
input flag_i, // from execute-ctrl stage, real flag we got
input padv_decode_i, // is decode stage stalled
input execute_bf_i, // prev insn was bf
input execute_bnf_i, // prev insn was bnf
// Branch misprediction indicator
output branch_mispredict_o // to decode-execute stage, was brn mispredicted or not
);
// Compare the real flag with the previously predicted flag and signal a
// misprediction in case of a mismatch.
assign branch_mispredict_o = prev_op_brcond_i & (flag_i != prev_predicted_flag_i);
generate
if (FEATURE_BRANCH_PREDICTOR=="SAT_COUNTER") begin : branch_predictor_saturation_counter
mor1kx_branch_predictor_saturation_counter
mor1kx_branch_predictor_saturation_counter
(
// Outputs
.predicted_flag_o (predicted_flag_o),
// Inputs
.clk (clk),
.rst (rst),
.flag_i (flag_i),
.execute_op_bf_i (execute_bf_i),
.execute_op_bnf_i (execute_bnf_i),
.op_bf_i (op_bf_i),
.op_bnf_i (op_bnf_i),
.prev_op_brcond_i (prev_op_brcond_i),
.branch_mispredict_i (branch_mispredict_o));
end else if (FEATURE_BRANCH_PREDICTOR=="SIMPLE") begin : branch_predictor_simple
mor1kx_branch_predictor_simple
mor1kx_branch_predictor_simple
(
// Outputs
.predicted_flag_o (predicted_flag_o),
// Inputs
.op_bf_i (op_bf_i),
.op_bnf_i (op_bnf_i),
.immjbr_upper_i (immjbr_upper_i));
end else begin
initial begin
$display("Error: FEATURE_PREDICTOR_TYPE, %s, not valid", FEATURE_BRANCH_PREDICTOR);
$finish();
end
end
endgenerate
endmodule
|
module fir_inj (x_in,clk,y,p_desc0_p_O_FD,p_desc1_p_O_FD,p_desc2_p_O_FD,p_desc3_p_O_FD,p_desc4_p_O_FD,p_desc5_p_O_FD,p_desc6_p_O_FD,p_desc7_p_O_FD,p_desc8_p_O_FD,p_desc9_p_O_FD,p_desc10_p_O_FD,p_desc11_p_O_FD,p_desc12_p_O_FD,p_desc13_p_O_FD,p_desc14_p_O_FD,p_desc15_p_O_FD,p_desc16_p_O_FD,p_desc17_p_O_FD,p_desc18_p_O_FD,p_desc19_p_O_FD,p_desc20_p_O_FD,p_desc21_p_O_FD,p_desc22_p_O_FD,p_desc23_p_O_FD,p_desc24_p_O_FD,p_desc25_p_O_FD,p_desc26_p_O_FD,p_desc27_p_O_FD,p_desc28_p_O_FD,p_desc29_p_O_FD,p_desc30_p_O_FD,p_desc31_p_O_FD,p_desc32_p_O_FD,p_x_14_pipe_0_Z_p_O_FD,p_x_14_pipe_9_Z_p_O_FD,p_x_14_pipe_10_Z_p_O_FD,p_x_14_pipe_11_Z_p_O_FD,p_x_14_pipe_12_Z_p_O_FD,p_x_14_pipe_13_Z_p_O_FD,p_x_14_pipe_14_Z_p_O_FD,p_x_14_pipe_15_Z_p_O_FD,p_x_14_pipe_16_Z_p_O_FD,p_x_14_pipe_17_Z_p_O_FD,p_x_9_pipe_1_Z_p_O_FD,p_x_9_pipe_2_Z_p_O_FD,p_x_9_pipe_3_Z_p_O_FD,p_x_9_pipe_4_Z_p_O_FD,p_x_9_pipe_5_Z_p_O_FD,p_x_9_pipe_6_Z_p_O_FD,p_x_9_pipe_7_Z_p_O_FD,p_x_9_pipe_8_Z_p_O_FD,p_x_15_pipe_0_0_15_Z_p_O_FD,p_x_15_pipe_0_0_16_Z_p_O_FD,p_x_15_pipe_0_0_17_Z_p_O_FD,p_x_15_pipe_0_0_18_Z_p_O_FD,p_x_15_pipe_0_0_19_Z_p_O_FD,p_x_15_pipe_0_0_20_Z_p_O_FD,p_x_15_pipe_0_0_21_Z_p_O_FD,p_x_15_pipe_0_0_22_Z_p_O_FD,p_x_15_pipe_0_0_23_Z_p_O_FD,p_x_15_pipe_0_0_24_Z_p_O_FD,p_x_15_pipe_0_0_25_Z_p_O_FD,p_x_15_pipe_0_0_26_Z_p_O_FD,p_x_15_pipe_0_0_27_Z_p_O_FD,p_x_15_pipe_0_0_28_Z_p_O_FD,p_x_15_pipe_0_0_29_Z_p_O_FD,p_x_16_pipe_0_0_0_Z_p_O_FD,p_x_16_pipe_0_0_1_Z_p_O_FD,p_x_16_pipe_0_0_2_Z_p_O_FD,p_x_16_pipe_0_0_3_Z_p_O_FD,p_x_16_pipe_0_0_4_Z_p_O_FD,p_x_16_pipe_0_0_5_Z_p_O_FD,p_x_16_pipe_0_0_6_Z_p_O_FD,p_x_16_pipe_0_0_7_Z_p_O_FD,p_x_16_pipe_0_0_8_Z_p_O_FD,p_x_16_pipe_0_0_9_Z_p_O_FD,p_x_16_pipe_0_0_10_Z_p_O_FD,p_x_16_pipe_0_0_11_Z_p_O_FD,p_x_16_pipe_0_0_12_Z_p_O_FD,p_x_16_pipe_0_0_13_Z_p_O_FD,p_x_16_pipe_0_0_14_Z_p_O_FD,p_desc33_p_O_FD,p_desc34_p_O_FD,p_desc35_p_O_FD,p_desc36_p_O_FD,p_desc37_p_O_FD,p_desc38_p_O_FD,p_desc39_p_O_FD,p_desc40_p_O_FD,p_desc41_p_O_FD,p_desc42_p_O_FD,p_desc43_p_O_FD,p_desc44_p_O_FD,p_desc45_p_O_FD,p_desc46_p_O_FD,p_desc47_p_O_FD,p_desc48_p_O_FD,p_desc49_p_O_FD,p_desc50_p_O_FD,p_desc51_p_O_FD,p_desc52_p_O_FD,p_desc53_p_O_FD,p_desc54_p_O_FD,p_desc55_p_O_FD,p_desc56_p_O_FD);
input [7:0] x_in ;
input clk ;
output [7:0] y ;
wire clk ;
wire [7:0] x_0 ;
wire [15:4] un1_x_1 ;
wire [15:5] un1_x_2 ;
wire [15:4] un1_x_3 ;
wire [7:0] x_4 ;
wire [15:2] un1_x_4 ;
wire [14:0] un84_sop_0_0_0_0_5 ;
wire [7:0] x_7 ;
wire [7:0] x_8 ;
wire x_9 ;
wire [7:0] x_12 ;
wire [7:0] x_13 ;
wire [9:0] un84_sop_0_0_0_0_0 ;
wire [9:0] un84_sop_0_0_0_0_1 ;
wire [15:4] un1_x_14_0_0 ;
wire [15:5] un1_x_13_0_0 ;
wire [15:4] un1_x_12_0_0 ;
wire [14:7] un1_x_11_0_0 ;
wire [14:0] un84_sop_0_0_0_10_0 ;
wire [15:8] un1_x_10_0_0 ;
wire [15:5] un1_x_9_0 ;
wire [15:4] un1_x_8_0 ;
wire [15:2] un1_x_7_0 ;
wire [15:1] un1_x_6_0 ;
wire [14:0] un84_sop_0_0_0_5_0 ;
wire [47:11] P_uc ;
wire [29:0] ACOUT ;
wire [3:0] CARRYOUT ;
wire [47:0] PCOUT ;
wire [47:11] P_uc_0 ;
wire [29:0] ACOUT_0 ;
wire [3:0] CARRYOUT_0 ;
wire [47:0] PCOUT_0 ;
wire [47:11] P_uc_1 ;
wire [29:0] ACOUT_1 ;
wire [17:0] BCOUT_1 ;
wire [3:0] CARRYOUT_1 ;
wire [47:0] PCOUT_1 ;
wire [47:12] P_uc_2 ;
wire [29:0] ACOUT_2 ;
wire [3:0] CARRYOUT_2 ;
wire [47:0] PCOUT_2 ;
wire [47:12] P_uc_3 ;
wire [29:0] ACOUT_3 ;
wire [3:0] CARRYOUT_3 ;
wire [47:0] PCOUT_3 ;
wire [47:12] P_uc_4 ;
wire [29:0] ACOUT_4 ;
wire [3:0] CARRYOUT_4 ;
wire [47:0] PCOUT_4 ;
wire [47:12] P_uc_5 ;
wire [29:0] ACOUT_5 ;
wire [3:0] CARRYOUT_5 ;
wire [47:0] PCOUT_5 ;
wire [47:12] P_uc_6 ;
wire [29:0] ACOUT_6 ;
wire [3:0] CARRYOUT_6 ;
wire [47:0] PCOUT_6 ;
wire [47:14] P_uc_7 ;
wire [29:0] ACOUT_7 ;
wire [3:0] CARRYOUT_7 ;
wire [47:0] PCOUT_7 ;
wire [47:14] P_uc_8 ;
wire [29:0] ACOUT_8 ;
wire [3:0] CARRYOUT_8 ;
wire [47:0] PCOUT_8 ;
wire [47:15] P_uc_9 ;
wire [29:0] ACOUT_9 ;
wire [17:0] BCOUT_9 ;
wire [3:0] CARRYOUT_9 ;
wire [47:0] PCOUT_9 ;
wire [7:0] x_10_0 ;
wire [7:7] x_10_1 ;
wire [7:7] x_10_2 ;
wire [7:7] x_10_3 ;
wire [7:7] x_10_4 ;
wire [7:7] x_10_5 ;
wire [7:7] x_10_6 ;
wire [7:7] x_10_7 ;
wire [7:7] x_10_8 ;
wire [7:7] x_10_9 ;
wire [7:7] x_10_10 ;
wire [7:0] x_9_0 ;
wire [7:7] x_9_1 ;
wire [7:7] x_9_2 ;
wire [7:7] x_9_3 ;
wire [7:7] x_9_4 ;
wire [7:7] x_9_5 ;
wire [7:7] x_9_6 ;
wire [7:7] x_9_7 ;
wire [7:7] x_9_8 ;
wire [7:7] x_9_9 ;
wire [7:7] x_9_10 ;
wire [7:0] x_6_0 ;
wire [7:7] x_6_1 ;
wire [7:7] x_6_2 ;
wire [7:7] x_6_3 ;
wire [7:7] x_6_4 ;
wire [7:7] x_6_5 ;
wire [7:7] x_6_6 ;
wire [7:7] x_6_7 ;
wire [7:7] x_6_8 ;
wire [7:7] x_6_9 ;
wire [7:7] x_6_10 ;
wire [7:0] x_5_0 ;
wire [7:7] x_5_1 ;
wire [7:7] x_5_2 ;
wire [7:7] x_5_3 ;
wire [7:7] x_5_4 ;
wire [7:7] x_5_5 ;
wire [7:7] x_5_6 ;
wire [7:7] x_5_7 ;
wire [7:7] x_5_8 ;
wire [7:7] x_5_9 ;
wire [7:7] x_5_10 ;
wire [7:0] x_4_0 ;
wire [7:7] x_4_1 ;
wire [7:7] x_4_2 ;
wire [7:7] x_4_3 ;
wire [7:7] x_4_4 ;
wire [7:7] x_4_5 ;
wire [7:7] x_4_6 ;
wire [7:7] x_4_7 ;
wire [7:7] x_4_8 ;
wire [7:7] x_4_9 ;
wire [7:7] x_4_10 ;
wire [7:0] x_3_0 ;
wire [7:7] x_3_1 ;
wire [7:7] x_3_2 ;
wire [7:7] x_3_3 ;
wire [7:7] x_3_4 ;
wire [7:7] x_3_5 ;
wire [7:7] x_3_6 ;
wire [7:7] x_3_7 ;
wire [7:7] x_3_8 ;
wire [7:7] x_3_9 ;
wire [7:7] x_3_10 ;
wire [7:0] x_2_0 ;
wire [7:7] x_2_1 ;
wire [7:7] x_2_2 ;
wire [7:7] x_2_3 ;
wire [7:7] x_2_4 ;
wire [7:7] x_2_5 ;
wire [7:7] x_2_6 ;
wire [7:7] x_2_7 ;
wire [7:7] x_2_8 ;
wire [7:7] x_2_9 ;
wire [7:7] x_2_10 ;
wire [7:0] x_1_0 ;
wire [7:7] x_1_1 ;
wire [7:7] x_1_2 ;
wire [7:7] x_1_3 ;
wire [7:7] x_1_4 ;
wire [7:7] x_1_5 ;
wire [7:7] x_1_6 ;
wire [7:7] x_1_7 ;
wire [7:7] x_1_8 ;
wire [7:7] x_1_9 ;
wire [7:7] x_1_10 ;
wire [7:0] x_0_0 ;
wire [7:7] x_0_1 ;
wire [7:7] x_0_2 ;
wire [7:7] x_0_3 ;
wire [7:7] x_0_4 ;
wire [7:7] x_0_5 ;
wire [7:7] x_0_6 ;
wire [7:7] x_0_7 ;
wire [7:7] x_0_8 ;
wire [7:7] x_0_9 ;
wire [7:7] x_0_10 ;
wire [14:3] un84_sop_0_0_0_1_6_8 ;
wire [14:0] un84_sop_1_7 ;
wire [14:0] un84_sop_0_0_0_0_11_7 ;
wire [14:0] un84_sop_1_4 ;
wire [10:2] un1_x_10_4 ;
wire [14:0] un84_sop_0_0_0_1_6_4 ;
wire [14:0] un84_sop_0_0_0_0_11_6 ;
wire [14:0] un84_sop_0_0_0_0_8 ;
wire [14:0] un84_sop_0_0_0_1_6_6 ;
wire [14:0] un84_sop_1_6 ;
wire [14:7] un1_x_15_0_0_0 ;
wire [14:7] un1_x_11_0_0_0 ;
wire [14:7] un1_x_16_0_0_0 ;
wire x_12_6_tmp_d_array_0 ;
wire x_12_5_tmp_d_array_0 ;
wire x_12_4_tmp_d_array_0 ;
wire x_12_3_tmp_d_array_0 ;
wire x_12_2_tmp_d_array_0 ;
wire x_12_1_tmp_d_array_0 ;
wire x_12_0_tmp_d_array_0 ;
wire x_12_tmp_d_array_0 ;
wire x_7_6_tmp_d_array_0 ;
wire x_7_5_tmp_d_array_0 ;
wire x_7_4_tmp_d_array_0 ;
wire x_7_3_tmp_d_array_0 ;
wire x_7_2_tmp_d_array_0 ;
wire x_7_1_tmp_d_array_0 ;
wire x_7_0_tmp_d_array_0 ;
wire x_7_tmp_d_array_0 ;
wire x_4_6_tmp_d_array_0 ;
wire x_4_5_tmp_d_array_0 ;
wire x_4_4_tmp_d_array_0 ;
wire x_4_3_tmp_d_array_0 ;
wire x_4_2_tmp_d_array_0 ;
wire x_4_1_tmp_d_array_0 ;
wire x_4_0_tmp_d_array_0 ;
wire x_4_tmp_d_array_0 ;
wire [4:4] un1_x_14_0_0_0 ;
wire [5:5] un1_x_9_0_0 ;
wire [4:4] un1_x_3_0 ;
wire VCC ;
wire GND ;
wire un84_sop_1_s_7 ;
wire un84_sop_1_s_8 ;
wire un84_sop_1_s_9 ;
wire un84_sop_1_s_10 ;
wire un84_sop_1_s_11 ;
wire un84_sop_1_s_12 ;
wire un84_sop_1_s_13 ;
wire un84_sop_1_s_14 ;
wire un1_x_10_s_2_sf ;
wire un1_x_10_axb_3 ;
wire CARRYCASCOUT ;
wire OVERFLOW ;
wire MULTSIGNOUT ;
wire PATTERNBDETECT ;
wire PATTERNDETECT ;
wire UNDERFLOW ;
wire CARRYCASCOUT_0 ;
wire OVERFLOW_0 ;
wire MULTSIGNOUT_0 ;
wire PATTERNBDETECT_0 ;
wire PATTERNDETECT_0 ;
wire UNDERFLOW_0 ;
wire CARRYCASCOUT_1 ;
wire OVERFLOW_1 ;
wire MULTSIGNOUT_1 ;
wire PATTERNBDETECT_1 ;
wire PATTERNDETECT_1 ;
wire UNDERFLOW_1 ;
wire CARRYCASCOUT_2 ;
wire OVERFLOW_2 ;
wire MULTSIGNOUT_2 ;
wire PATTERNBDETECT_2 ;
wire PATTERNDETECT_2 ;
wire UNDERFLOW_2 ;
wire CARRYCASCOUT_3 ;
wire OVERFLOW_3 ;
wire MULTSIGNOUT_3 ;
wire PATTERNBDETECT_3 ;
wire PATTERNDETECT_3 ;
wire UNDERFLOW_3 ;
wire CARRYCASCOUT_4 ;
wire OVERFLOW_4 ;
wire MULTSIGNOUT_4 ;
wire PATTERNBDETECT_4 ;
wire PATTERNDETECT_4 ;
wire UNDERFLOW_4 ;
wire CARRYCASCOUT_5 ;
wire OVERFLOW_5 ;
wire MULTSIGNOUT_5 ;
wire PATTERNBDETECT_5 ;
wire PATTERNDETECT_5 ;
wire UNDERFLOW_5 ;
wire CARRYCASCOUT_6 ;
wire OVERFLOW_6 ;
wire MULTSIGNOUT_6 ;
wire PATTERNBDETECT_6 ;
wire PATTERNDETECT_6 ;
wire UNDERFLOW_6 ;
wire CARRYCASCOUT_7 ;
wire OVERFLOW_7 ;
wire MULTSIGNOUT_7 ;
wire PATTERNBDETECT_7 ;
wire PATTERNDETECT_7 ;
wire UNDERFLOW_7 ;
wire CARRYCASCOUT_8 ;
wire OVERFLOW_8 ;
wire MULTSIGNOUT_8 ;
wire PATTERNBDETECT_8 ;
wire PATTERNDETECT_8 ;
wire UNDERFLOW_8 ;
wire CARRYCASCOUT_9 ;
wire OVERFLOW_9 ;
wire MULTSIGNOUT_9 ;
wire PATTERNBDETECT_9 ;
wire PATTERNDETECT_9 ;
wire UNDERFLOW_9 ;
wire un84_sop_1_6_0_axb_1_lut6_2_O5 ;
wire un84_sop_1_6_0_o5_2 ;
wire un84_sop_1_6_0_o5_3 ;
wire un84_sop_1_6_0_o5_4 ;
wire un84_sop_1_6_0_o5_5 ;
wire un84_sop_1_6_0_o5_6 ;
wire un84_sop_1_6_0_o5_7 ;
wire un84_sop_1_6_0_o5_8 ;
wire un84_sop_1_6_0_o5_9 ;
wire un84_sop_1_6_0_o5_10 ;
wire un84_sop_1_6_0_o5_11 ;
wire un84_sop_0_0_0_1_6_8_axb_2_lut6_2_O5 ;
wire un84_sop_0_0_0_1_6_8_o5_3 ;
wire un84_sop_0_0_0_1_6_8_o5_4 ;
wire un84_sop_0_0_0_1_6_8_o5_5 ;
wire un84_sop_0_0_0_1_6_8_o5_6 ;
wire un84_sop_0_0_0_1_6_8_o5_7 ;
wire un84_sop_0_0_0_6_6_0_axb_1_lut6_2_O5 ;
wire un84_sop_0_0_0_6_6_0_o5_2 ;
wire un84_sop_0_0_0_6_6_0_o5_3 ;
wire un84_sop_0_0_0_6_6_0_o5_4 ;
wire un84_sop_0_0_0_6_6_0_o5_5 ;
wire un84_sop_0_0_0_6_6_0_o5_6 ;
wire un84_sop_0_0_0_6_6_0_o5_7 ;
wire un84_sop_0_0_0_6_6_0_o5_8 ;
wire un84_sop_0_0_0_6_6_0_o5_9 ;
wire un84_sop_0_0_0_6_6_0_o5_10 ;
wire un84_sop_0_0_0_6_6_0_o5_11 ;
wire un84_sop_0_0_0_6_6_0_o5_12 ;
wire un84_sop_0_0_0_11_0_o5_2 ;
wire un84_sop_0_0_0_11_0_o5_3 ;
wire un84_sop_0_0_0_11_0_o5_4 ;
wire un84_sop_0_0_0_11_0_o5_5 ;
wire un84_sop_0_0_0_11_0_o5_6 ;
wire un84_sop_0_0_0_11_0_o5_7 ;
wire un84_sop_0_0_0_11_0_o5_8 ;
wire un84_sop_0_0_0_11_0_o5_9 ;
wire un84_sop_0_0_0_11_0_o5_10 ;
wire un84_sop_0_0_0_11_0_o5_11 ;
wire un84_sop_0_0_0_11_0_o5_12 ;
wire un84_sop_0_0_0_11_6_0_axb_1_lut6_2_O5 ;
wire un84_sop_0_0_0_11_6_0_o5_2 ;
wire un84_sop_0_0_0_11_6_0_o5_3 ;
wire un84_sop_0_0_0_11_6_0_o5_4 ;
wire un84_sop_0_0_0_11_6_0_o5_5 ;
wire un84_sop_0_0_0_11_6_0_o5_6 ;
wire un84_sop_0_0_0_11_6_0_o5_7 ;
wire un84_sop_0_0_0_11_6_0_o5_8 ;
wire un84_sop_0_0_0_11_6_0_o5_9 ;
wire un84_sop_0_0_0_11_6_0_o5_10 ;
wire un84_sop_0_0_0_11_6_0_o5_11 ;
wire un84_sop_0_0_0_11_6_0_cry_0 ;
wire un84_sop_0_0_0_11_6_0_axb_1 ;
wire un84_sop_0_0_0_11_6_0_cry_1 ;
wire un84_sop_0_0_0_11_6_0_axb_2 ;
wire un84_sop_0_0_0_11_6_0_cry_2 ;
wire un84_sop_0_0_0_11_6_0_axb_3 ;
wire un84_sop_0_0_0_11_6_0_cry_3 ;
wire un84_sop_0_0_0_11_6_0_axb_4 ;
wire un84_sop_0_0_0_11_6_0_cry_4 ;
wire un84_sop_0_0_0_11_6_0_axb_5 ;
wire un84_sop_0_0_0_11_6_0_cry_5 ;
wire un84_sop_0_0_0_11_6_0_axb_6 ;
wire un84_sop_0_0_0_11_6_0_cry_6 ;
wire un84_sop_0_0_0_11_6_0_axb_7 ;
wire un84_sop_0_0_0_11_6_0_cry_7 ;
wire un84_sop_0_0_0_11_6_0_axb_8 ;
wire un84_sop_0_0_0_11_6_0_cry_8 ;
wire un84_sop_0_0_0_11_6_0_axb_9 ;
wire un84_sop_0_0_0_11_6_0_cry_9 ;
wire un84_sop_0_0_0_11_6_0_axb_10 ;
wire un84_sop_0_0_0_11_6_0_cry_10 ;
wire un84_sop_0_0_0_11_6_0_axb_11 ;
wire un84_sop_0_0_0_11_6_0_cry_11 ;
wire un84_sop_0_0_0_11_6_0_axb_12 ;
wire un84_sop_0_0_0_11_6_0_cry_12 ;
wire un84_sop_0_0_0_11_6_0_axb_13 ;
wire un84_sop_0_0_0_11_0_axb_0 ;
wire un84_sop_0_0_0_11_0_cry_0 ;
wire un84_sop_0_0_0_11_0_axb_1 ;
wire un84_sop_0_0_0_11_0_cry_1 ;
wire un84_sop_0_0_0_11_0_cry_2_RNO ;
wire un84_sop_0_0_0_11_0_axb_2 ;
wire un84_sop_0_0_0_11_0_cry_2 ;
wire un84_sop_0_0_0_11_0_axb_3 ;
wire un84_sop_0_0_0_11_0_cry_3 ;
wire un84_sop_0_0_0_11_0_axb_4 ;
wire un84_sop_0_0_0_11_0_cry_4 ;
wire un84_sop_0_0_0_11_0_axb_5 ;
wire un84_sop_0_0_0_11_0_cry_5 ;
wire un84_sop_0_0_0_11_0_axb_6 ;
wire un84_sop_0_0_0_11_0_cry_6 ;
wire un84_sop_0_0_0_11_0_axb_7 ;
wire un84_sop_0_0_0_11_0_cry_7 ;
wire un84_sop_0_0_0_11_0_axb_8 ;
wire un84_sop_0_0_0_11_0_cry_8 ;
wire un84_sop_0_0_0_11_0_axb_9 ;
wire un84_sop_0_0_0_11_0_cry_9 ;
wire un84_sop_0_0_0_11_0_axb_10 ;
wire un84_sop_0_0_0_11_0_cry_10 ;
wire un84_sop_0_0_0_11_0_axb_11 ;
wire un84_sop_0_0_0_11_0_cry_11 ;
wire un84_sop_0_0_0_11_0_axb_12 ;
wire un84_sop_0_0_0_11_0_cry_12 ;
wire un84_sop_0_0_0_11_0_axb_13 ;
wire un84_sop_0_0_0_11_0_cry_13 ;
wire un84_sop_0_0_0_11_0_axb_14 ;
wire un84_sop_0_0_0_6_6_0_cry_0 ;
wire un84_sop_0_0_0_6_6_0_axb_1 ;
wire un84_sop_0_0_0_6_6_0_cry_1 ;
wire un84_sop_0_0_0_6_6_0_axb_2 ;
wire un84_sop_0_0_0_6_6_0_cry_2 ;
wire un84_sop_0_0_0_6_6_0_axb_3 ;
wire un84_sop_0_0_0_6_6_0_cry_3 ;
wire un84_sop_0_0_0_6_6_0_axb_4 ;
wire un84_sop_0_0_0_6_6_0_cry_4 ;
wire un84_sop_0_0_0_6_6_0_axb_5 ;
wire un84_sop_0_0_0_6_6_0_cry_5 ;
wire un84_sop_0_0_0_6_6_0_axb_6 ;
wire un84_sop_0_0_0_6_6_0_cry_6 ;
wire un84_sop_0_0_0_6_6_0_axb_7 ;
wire un84_sop_0_0_0_6_6_0_cry_7 ;
wire un84_sop_0_0_0_6_6_0_axb_8 ;
wire un84_sop_0_0_0_6_6_0_cry_8 ;
wire un84_sop_0_0_0_6_6_0_axb_9 ;
wire un84_sop_0_0_0_6_6_0_cry_9 ;
wire un84_sop_0_0_0_6_6_0_axb_10 ;
wire un84_sop_0_0_0_6_6_0_cry_10 ;
wire un84_sop_0_0_0_6_6_0_axb_11 ;
wire un84_sop_0_0_0_6_6_0_cry_11 ;
wire un84_sop_0_0_0_6_6_0_axb_12 ;
wire un84_sop_0_0_0_6_6_0_cry_12 ;
wire un84_sop_0_0_0_6_6_0_axb_13 ;
wire un84_sop_0_0_0_6_6_0_cry_13 ;
wire un84_sop_0_0_0_6_6_0_axb_14 ;
wire un84_sop_0_0_0_1_6_8_cry_0 ;
wire un84_sop_0_0_0_1_6_8_axb_1 ;
wire un84_sop_0_0_0_1_6_8_cry_1 ;
wire un84_sop_0_0_0_1_6_8_axb_2 ;
wire un84_sop_0_0_0_1_6_8_cry_2 ;
wire un84_sop_0_0_0_1_6_8_axb_3 ;
wire un84_sop_0_0_0_1_6_8_cry_3 ;
wire un84_sop_0_0_0_1_6_8_axb_4 ;
wire un84_sop_0_0_0_1_6_8_cry_4 ;
wire un84_sop_0_0_0_1_6_8_axb_5 ;
wire un84_sop_0_0_0_1_6_8_cry_5 ;
wire un84_sop_0_0_0_1_6_8_axb_6 ;
wire un84_sop_0_0_0_1_6_8_cry_6 ;
wire un84_sop_0_0_0_1_6_8_axb_7 ;
wire un84_sop_0_0_0_1_6_8_cry_7 ;
wire un84_sop_0_0_0_1_6_8_axb_8 ;
wire un84_sop_0_0_0_1_6_8_cry_8 ;
wire un84_sop_0_0_0_1_6_8_axb_9 ;
wire un84_sop_0_0_0_1_6_8_cry_9 ;
wire un84_sop_0_0_0_1_6_8_axb_10 ;
wire un84_sop_0_0_0_1_6_8_cry_10 ;
wire un84_sop_0_0_0_1_6_8_axb_11 ;
wire un84_sop_1_6_0_cry_0 ;
wire un84_sop_1_6_0_axb_1 ;
wire un84_sop_1_6_0_cry_1 ;
wire un84_sop_1_6_0_axb_2 ;
wire un84_sop_1_6_0_cry_2 ;
wire un84_sop_1_6_0_axb_3 ;
wire un84_sop_1_6_0_cry_3 ;
wire un84_sop_1_6_0_axb_4 ;
wire un84_sop_1_6_0_cry_4 ;
wire un84_sop_1_6_0_axb_5 ;
wire un84_sop_1_6_0_cry_5 ;
wire un84_sop_1_6_0_axb_6 ;
wire un84_sop_1_6_0_cry_6 ;
wire un84_sop_1_6_0_axb_7 ;
wire un84_sop_1_6_0_cry_7 ;
wire un84_sop_1_6_0_axb_8 ;
wire un84_sop_1_6_0_cry_8 ;
wire un84_sop_1_6_0_axb_9 ;
wire un84_sop_1_6_0_cry_9 ;
wire un84_sop_1_6_0_axb_10 ;
wire un84_sop_1_6_0_cry_10 ;
wire un84_sop_1_6_0_axb_11 ;
wire un84_sop_1_6_0_cry_11 ;
wire un84_sop_1_6_0_axb_12 ;
wire un84_sop_1_6_0_cry_12 ;
wire un84_sop_1_6_0_axb_13 ;
wire un1_x_10_cry_3 ;
wire un1_x_10_axb_4 ;
wire un1_x_10_cry_4 ;
wire un1_x_10_axb_5 ;
wire un1_x_10_cry_5 ;
wire un1_x_10_axb_6 ;
wire un1_x_10_cry_6 ;
wire un1_x_10_axb_7 ;
wire un1_x_10_cry_7 ;
wire un1_x_10_axb_8 ;
wire un1_x_10_cry_8 ;
wire un1_x_10_axb_9 ;
wire un1_x_10_cry_9 ;
wire un1_x_10_axb_10 ;
wire un1_x_10_cry_10 ;
wire un1_x_10_axb_11 ;
wire un84_sop_0_0_0_1_6_4_cry_0 ;
wire un84_sop_0_0_0_1_6_4_axb_1 ;
wire un84_sop_0_0_0_1_6_4_cry_1 ;
wire un84_sop_0_0_0_1_6_4_axb_2 ;
wire un84_sop_0_0_0_1_6_4_cry_2 ;
wire un84_sop_0_0_0_1_6_4_axb_3 ;
wire un84_sop_0_0_0_1_6_4_cry_3 ;
wire un84_sop_0_0_0_1_6_4_axb_4 ;
wire un84_sop_0_0_0_1_6_4_cry_4 ;
wire un84_sop_0_0_0_1_6_4_axb_5 ;
wire un84_sop_0_0_0_1_6_4_cry_5 ;
wire un84_sop_0_0_0_1_6_4_axb_6 ;
wire un84_sop_0_0_0_1_6_4_cry_6 ;
wire un84_sop_0_0_0_1_6_4_axb_7 ;
wire un84_sop_0_0_0_1_6_4_cry_7 ;
wire un84_sop_0_0_0_1_6_4_axb_8 ;
wire un84_sop_0_0_0_1_6_4_cry_8 ;
wire un84_sop_0_0_0_1_6_4_axb_9 ;
wire un84_sop_0_0_0_1_6_4_cry_9 ;
wire un84_sop_0_0_0_1_6_4_axb_10 ;
wire un84_sop_0_0_0_1_6_4_cry_10 ;
wire un84_sop_0_0_0_1_6_4_axb_11 ;
wire un84_sop_0_0_0_1_6_4_cry_11 ;
wire un84_sop_0_0_0_1_6_4_axb_12 ;
wire un84_sop_0_0_0_1_6_4_cry_12 ;
wire un84_sop_0_0_0_1_6_4_axb_13 ;
wire un84_sop_0_0_0_1_6_4_cry_13 ;
wire un84_sop_0_0_0_1_6_4_axb_14 ;
wire un84_sop_0_0_0_1_6_cry_0 ;
wire un84_sop_0_0_0_1_6_axb_1 ;
wire un84_sop_0_0_0_1_6_cry_1 ;
wire un84_sop_0_0_0_1_6_axb_2 ;
wire un84_sop_0_0_0_1_6_cry_2 ;
wire un84_sop_0_0_0_1_6_axb_3 ;
wire un84_sop_0_0_0_1_6_cry_3 ;
wire un84_sop_0_0_0_1_6_axb_4 ;
wire un84_sop_0_0_0_1_6_cry_4 ;
wire un84_sop_0_0_0_1_6_axb_5 ;
wire un84_sop_0_0_0_1_6_cry_5 ;
wire un84_sop_0_0_0_1_6_axb_6 ;
wire un84_sop_0_0_0_1_6_cry_6 ;
wire un84_sop_0_0_0_1_6_axb_7 ;
wire un84_sop_0_0_0_1_6_cry_7 ;
wire un84_sop_0_0_0_1_6_axb_8 ;
wire un84_sop_0_0_0_1_6_cry_8 ;
wire un84_sop_0_0_0_1_6_axb_9 ;
wire un84_sop_0_0_0_1_6_cry_9 ;
wire un84_sop_0_0_0_1_6_axb_10 ;
wire un84_sop_0_0_0_1_6_cry_10 ;
wire un84_sop_0_0_0_1_6_axb_11 ;
wire un84_sop_0_0_0_1_6_cry_11 ;
wire un84_sop_0_0_0_1_6_axb_12 ;
wire un84_sop_0_0_0_1_6_cry_12 ;
wire un84_sop_0_0_0_1_6_axb_13 ;
wire un84_sop_0_0_0_1_6_cry_13 ;
wire un84_sop_0_0_0_1_6_axb_14 ;
wire un1_x_0_0_c4 ;
wire un1_x_10_5_c5 ;
wire un84_sop_1_7_cry_0 ;
wire un84_sop_1_7_axb_1 ;
wire un84_sop_1_7_cry_1 ;
wire un84_sop_1_7_axb_2 ;
wire un84_sop_1_7_cry_2 ;
wire un84_sop_1_7_axb_3 ;
wire un84_sop_1_7_cry_3 ;
wire un84_sop_1_7_axb_4 ;
wire un84_sop_1_7_cry_4 ;
wire un84_sop_1_7_axb_5 ;
wire un84_sop_1_7_cry_5 ;
wire un84_sop_1_7_axb_6 ;
wire un84_sop_1_7_cry_6 ;
wire un84_sop_1_7_axb_7 ;
wire un84_sop_1_7_cry_7 ;
wire un84_sop_1_7_axb_8 ;
wire un84_sop_1_7_cry_8 ;
wire un84_sop_1_7_axb_9 ;
wire un84_sop_1_7_cry_9 ;
wire un84_sop_1_7_axb_10 ;
wire un84_sop_1_7_cry_10 ;
wire un84_sop_1_7_axb_11 ;
wire un84_sop_1_7_cry_11 ;
wire un84_sop_1_7_axb_12 ;
wire un84_sop_1_7_cry_12 ;
wire un84_sop_1_7_axb_13 ;
wire un84_sop_1_7_cry_13 ;
wire un84_sop_1_7_axb_14 ;
wire un84_sop_0_0_0_0_11_7_cry_0 ;
wire un84_sop_0_0_0_0_11_7_axb_1 ;
wire un84_sop_0_0_0_0_11_7_cry_1 ;
wire un84_sop_0_0_0_0_11_7_axb_2 ;
wire un84_sop_0_0_0_0_11_7_cry_2 ;
wire un84_sop_0_0_0_0_11_7_axb_3 ;
wire un84_sop_0_0_0_0_11_7_cry_3 ;
wire un84_sop_0_0_0_0_11_7_axb_4 ;
wire un84_sop_0_0_0_0_11_7_cry_4 ;
wire un84_sop_0_0_0_0_11_7_axb_5 ;
wire un84_sop_0_0_0_0_11_7_cry_5 ;
wire un84_sop_0_0_0_0_11_7_axb_6 ;
wire un84_sop_0_0_0_0_11_7_cry_6 ;
wire un84_sop_0_0_0_0_11_7_axb_7 ;
wire un84_sop_0_0_0_0_11_7_cry_7 ;
wire un84_sop_0_0_0_0_11_7_axb_8 ;
wire un84_sop_0_0_0_0_11_7_cry_8 ;
wire un84_sop_0_0_0_0_11_7_axb_9 ;
wire un84_sop_0_0_0_0_11_7_cry_9 ;
wire un84_sop_0_0_0_0_11_7_axb_10 ;
wire un84_sop_1_4_cry_0 ;
wire un84_sop_1_4_axb_1 ;
wire un84_sop_1_4_cry_1 ;
wire un84_sop_1_4_axb_2 ;
wire un84_sop_1_4_cry_2 ;
wire un84_sop_1_4_axb_3 ;
wire un84_sop_1_4_cry_3 ;
wire un84_sop_1_4_axb_4 ;
wire un84_sop_1_4_cry_4 ;
wire un84_sop_1_4_axb_5 ;
wire un84_sop_1_4_cry_5 ;
wire un84_sop_1_4_axb_6 ;
wire un84_sop_1_4_cry_6 ;
wire un84_sop_1_4_axb_7 ;
wire un84_sop_1_4_cry_7 ;
wire un84_sop_1_4_axb_8 ;
wire un84_sop_1_4_cry_8 ;
wire un84_sop_1_4_axb_9 ;
wire un84_sop_1_4_cry_9 ;
wire un84_sop_1_4_axb_10 ;
wire un84_sop_1_4_cry_10 ;
wire un84_sop_1_4_axb_11 ;
wire un84_sop_1_4_cry_11 ;
wire un84_sop_1_4_axb_12 ;
wire un84_sop_1_4_cry_12 ;
wire un84_sop_1_4_axb_13 ;
wire un84_sop_1_4_cry_13 ;
wire un84_sop_1_4_axb_14 ;
wire un84_sop_1_axb_0 ;
wire un84_sop_1_cry_0 ;
wire un84_sop_1_axb_1 ;
wire un84_sop_1_cry_1 ;
wire un84_sop_1_axb_2 ;
wire un84_sop_1_cry_2 ;
wire un84_sop_1_axb_3 ;
wire un84_sop_1_cry_3 ;
wire un84_sop_1_axb_4 ;
wire un84_sop_1_cry_4 ;
wire un84_sop_1_axb_5 ;
wire un84_sop_1_cry_5 ;
wire un84_sop_1_axb_6 ;
wire un84_sop_1_cry_6 ;
wire un84_sop_1_axb_7 ;
wire un84_sop_1_cry_7 ;
wire un84_sop_1_axb_8 ;
wire un84_sop_1_cry_8 ;
wire un84_sop_1_axb_9 ;
wire un84_sop_1_cry_9 ;
wire un84_sop_1_axb_10 ;
wire un84_sop_1_cry_10 ;
wire un84_sop_1_axb_11 ;
wire un84_sop_1_cry_11 ;
wire un84_sop_1_axb_12 ;
wire un84_sop_1_cry_12 ;
wire un84_sop_1_axb_13 ;
wire un84_sop_1_cry_13 ;
wire un84_sop_1_axb_14 ;
wire un1_x_10_4_cry_1 ;
wire un1_x_10_4_axb_2 ;
wire un1_x_10_4_cry_2 ;
wire un1_x_10_4_axb_3 ;
wire un1_x_10_4_cry_3 ;
wire un1_x_10_4_axb_4 ;
wire un1_x_10_4_cry_4 ;
wire un1_x_10_4_axb_5 ;
wire un1_x_10_4_cry_5 ;
wire un1_x_10_4_axb_6 ;
wire un1_x_10_4_cry_6 ;
wire un1_x_10_4_axb_7 ;
wire un1_x_10_4_cry_7 ;
wire un1_x_15_0_axb_0 ;
wire un1_x_15_0_cry_0 ;
wire un1_x_15_0_axb_1 ;
wire un1_x_15_0_cry_1 ;
wire un1_x_15_0_axb_2 ;
wire un1_x_15_0_cry_2 ;
wire un1_x_15_0_axb_3 ;
wire un1_x_15_0_cry_3 ;
wire un1_x_15_0_axb_4 ;
wire un1_x_15_0_cry_4 ;
wire un1_x_15_0_axb_5 ;
wire un1_x_15_0_cry_5 ;
wire un1_x_15_0_axb_6 ;
wire un1_x_15_0_cry_6 ;
wire un1_x_15_0_axb_7 ;
wire un1_x_15_0_cry_7 ;
wire un1_x_15_0_axb_8 ;
wire un1_x_11_0_axb_0 ;
wire un1_x_11_0_cry_0 ;
wire un1_x_11_0_axb_1 ;
wire un1_x_11_0_cry_1 ;
wire un1_x_11_0_axb_2 ;
wire un1_x_11_0_cry_2 ;
wire un1_x_11_0_axb_3 ;
wire un1_x_11_0_cry_3 ;
wire un1_x_11_0_axb_4 ;
wire un1_x_11_0_cry_4 ;
wire un1_x_11_0_axb_5 ;
wire un1_x_11_0_cry_5 ;
wire un1_x_11_0_axb_6 ;
wire un1_x_11_0_cry_6 ;
wire un1_x_11_0_axb_7 ;
wire un1_x_11_0_cry_7 ;
wire un1_x_11_0_axb_8 ;
wire un1_x_16_0_axb_0 ;
wire un1_x_16_0_cry_0 ;
wire un1_x_16_0_axb_1 ;
wire un1_x_16_0_cry_1 ;
wire un1_x_16_0_axb_2 ;
wire un1_x_16_0_cry_2 ;
wire un1_x_16_0_axb_3 ;
wire un1_x_16_0_cry_3 ;
wire un1_x_16_0_axb_4 ;
wire un1_x_16_0_cry_4 ;
wire un1_x_16_0_axb_5 ;
wire un1_x_16_0_cry_5 ;
wire un1_x_16_0_axb_6 ;
wire un1_x_16_0_cry_6 ;
wire un1_x_16_0_axb_7 ;
wire un1_x_16_0_cry_7 ;
wire un1_x_16_0_axb_8 ;
wire un84_sop_0_0_0_1_cry_0 ;
wire un84_sop_0_0_0_1_axb_1 ;
wire un84_sop_0_0_0_1_cry_1 ;
wire un84_sop_0_0_0_1_axb_2 ;
wire un84_sop_0_0_0_1_cry_2 ;
wire un84_sop_0_0_0_1_axb_3 ;
wire un84_sop_0_0_0_1_cry_3 ;
wire un84_sop_0_0_0_1_axb_4 ;
wire un84_sop_0_0_0_1_cry_4 ;
wire un84_sop_0_0_0_1_axb_5 ;
wire un84_sop_0_0_0_1_cry_5 ;
wire un84_sop_0_0_0_1_axb_6 ;
wire un84_sop_0_0_0_1_cry_6 ;
wire un84_sop_0_0_0_1_axb_7 ;
wire un84_sop_0_0_0_1_cry_7 ;
wire un84_sop_0_0_0_1_axb_8 ;
wire un84_sop_0_0_0_1_cry_8 ;
wire un84_sop_0_0_0_1_axb_9 ;
wire un1_x_10_4_cry_1_sf ;
wire un84_sop_0_0_0_0_11_7_axb_0_ci ;
wire un84_sop_0_0_0_11_0_cry_0_cy ;
wire un84_sop_0_0_0_11_6_0_cry_0_cy ;
wire un84_sop_0_0_0_6_6_0_cry_0_cy ;
wire un84_sop_1_6_0_cry_0_cy ;
wire un84_sop_0_0_0_6_0_axb_0_0 ;
wire un84_sop_0_0_0_6_0_axb_0_1 ;
wire un84_sop_1_6_0_axb_0_0 ;
wire un1_x_10_4_s_8_false ;
wire x_4_x_4_1Q_Q31 ;
wire x_4_0_x_4_1Q_Q31 ;
wire x_4_1_x_4_1Q_Q31 ;
wire x_4_2_x_4_1Q_Q31 ;
wire x_4_3_x_4_1Q_Q31 ;
wire x_4_4_x_4_1Q_Q31 ;
wire x_4_5_x_4_1Q_Q31 ;
wire x_4_6_x_4_1Q_Q31 ;
wire x_7_x_7_1Q_Q31 ;
wire x_7_0_x_7_1Q_Q31 ;
wire x_7_1_x_7_1Q_Q31 ;
wire x_7_2_x_7_1Q_Q31 ;
wire x_7_3_x_7_1Q_Q31 ;
wire x_7_4_x_7_1Q_Q31 ;
wire x_7_5_x_7_1Q_Q31 ;
wire x_7_6_x_7_1Q_Q31 ;
wire x_12_x_4_1Q_Q31 ;
wire x_12_0_x_4_1Q_Q31 ;
wire x_12_1_x_4_1Q_Q31 ;
wire x_12_2_x_4_1Q_Q31 ;
wire x_12_3_x_4_1Q_Q31 ;
wire x_12_4_x_4_1Q_Q31 ;
wire x_12_5_x_4_1Q_Q31 ;
wire x_12_6_x_7_1Q_Q31 ;
input p_desc0_p_O_FD ;
input p_desc1_p_O_FD ;
input p_desc2_p_O_FD ;
input p_desc3_p_O_FD ;
input p_desc4_p_O_FD ;
input p_desc5_p_O_FD ;
input p_desc6_p_O_FD ;
input p_desc7_p_O_FD ;
input p_desc8_p_O_FD ;
input p_desc9_p_O_FD ;
input p_desc10_p_O_FD ;
input p_desc11_p_O_FD ;
input p_desc12_p_O_FD ;
input p_desc13_p_O_FD ;
input p_desc14_p_O_FD ;
input p_desc15_p_O_FD ;
input p_desc16_p_O_FD ;
input p_desc17_p_O_FD ;
input p_desc18_p_O_FD ;
input p_desc19_p_O_FD ;
input p_desc20_p_O_FD ;
input p_desc21_p_O_FD ;
input p_desc22_p_O_FD ;
input p_desc23_p_O_FD ;
input p_desc24_p_O_FD ;
input p_desc25_p_O_FD ;
input p_desc26_p_O_FD ;
input p_desc27_p_O_FD ;
input p_desc28_p_O_FD ;
input p_desc29_p_O_FD ;
input p_desc30_p_O_FD ;
input p_desc31_p_O_FD ;
input p_desc32_p_O_FD ;
input p_x_14_pipe_0_Z_p_O_FD ;
input p_x_14_pipe_9_Z_p_O_FD ;
input p_x_14_pipe_10_Z_p_O_FD ;
input p_x_14_pipe_11_Z_p_O_FD ;
input p_x_14_pipe_12_Z_p_O_FD ;
input p_x_14_pipe_13_Z_p_O_FD ;
input p_x_14_pipe_14_Z_p_O_FD ;
input p_x_14_pipe_15_Z_p_O_FD ;
input p_x_14_pipe_16_Z_p_O_FD ;
input p_x_14_pipe_17_Z_p_O_FD ;
input p_x_9_pipe_1_Z_p_O_FD ;
input p_x_9_pipe_2_Z_p_O_FD ;
input p_x_9_pipe_3_Z_p_O_FD ;
input p_x_9_pipe_4_Z_p_O_FD ;
input p_x_9_pipe_5_Z_p_O_FD ;
input p_x_9_pipe_6_Z_p_O_FD ;
input p_x_9_pipe_7_Z_p_O_FD ;
input p_x_9_pipe_8_Z_p_O_FD ;
input p_x_15_pipe_0_0_15_Z_p_O_FD ;
input p_x_15_pipe_0_0_16_Z_p_O_FD ;
input p_x_15_pipe_0_0_17_Z_p_O_FD ;
input p_x_15_pipe_0_0_18_Z_p_O_FD ;
input p_x_15_pipe_0_0_19_Z_p_O_FD ;
input p_x_15_pipe_0_0_20_Z_p_O_FD ;
input p_x_15_pipe_0_0_21_Z_p_O_FD ;
input p_x_15_pipe_0_0_22_Z_p_O_FD ;
input p_x_15_pipe_0_0_23_Z_p_O_FD ;
input p_x_15_pipe_0_0_24_Z_p_O_FD ;
input p_x_15_pipe_0_0_25_Z_p_O_FD ;
input p_x_15_pipe_0_0_26_Z_p_O_FD ;
input p_x_15_pipe_0_0_27_Z_p_O_FD ;
input p_x_15_pipe_0_0_28_Z_p_O_FD ;
input p_x_15_pipe_0_0_29_Z_p_O_FD ;
input p_x_16_pipe_0_0_0_Z_p_O_FD ;
input p_x_16_pipe_0_0_1_Z_p_O_FD ;
input p_x_16_pipe_0_0_2_Z_p_O_FD ;
input p_x_16_pipe_0_0_3_Z_p_O_FD ;
input p_x_16_pipe_0_0_4_Z_p_O_FD ;
input p_x_16_pipe_0_0_5_Z_p_O_FD ;
input p_x_16_pipe_0_0_6_Z_p_O_FD ;
input p_x_16_pipe_0_0_7_Z_p_O_FD ;
input p_x_16_pipe_0_0_8_Z_p_O_FD ;
input p_x_16_pipe_0_0_9_Z_p_O_FD ;
input p_x_16_pipe_0_0_10_Z_p_O_FD ;
input p_x_16_pipe_0_0_11_Z_p_O_FD ;
input p_x_16_pipe_0_0_12_Z_p_O_FD ;
input p_x_16_pipe_0_0_13_Z_p_O_FD ;
input p_x_16_pipe_0_0_14_Z_p_O_FD ;
input p_desc33_p_O_FD ;
input p_desc34_p_O_FD ;
input p_desc35_p_O_FD ;
input p_desc36_p_O_FD ;
input p_desc37_p_O_FD ;
input p_desc38_p_O_FD ;
input p_desc39_p_O_FD ;
input p_desc40_p_O_FD ;
input p_desc41_p_O_FD ;
input p_desc42_p_O_FD ;
input p_desc43_p_O_FD ;
input p_desc44_p_O_FD ;
input p_desc45_p_O_FD ;
input p_desc46_p_O_FD ;
input p_desc47_p_O_FD ;
input p_desc48_p_O_FD ;
input p_desc49_p_O_FD ;
input p_desc50_p_O_FD ;
input p_desc51_p_O_FD ;
input p_desc52_p_O_FD ;
input p_desc53_p_O_FD ;
input p_desc54_p_O_FD ;
input p_desc55_p_O_FD ;
input p_desc56_p_O_FD ;
// instances
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
SRLC32E x_12_6_x_7_1Q(.Q(x_12_6_tmp_d_array_0),.Q31(x_12_6_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_9),.CLK(clk),.CE(VCC));
SRLC32E x_12_5_x_4_1Q(.Q(x_12_5_tmp_d_array_0),.Q31(x_12_5_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[1:1]),.CLK(clk),.CE(VCC));
SRLC32E x_12_4_x_4_1Q(.Q(x_12_4_tmp_d_array_0),.Q31(x_12_4_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[2:2]),.CLK(clk),.CE(VCC));
SRLC32E x_12_3_x_4_1Q(.Q(x_12_3_tmp_d_array_0),.Q31(x_12_3_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[3:3]),.CLK(clk),.CE(VCC));
SRLC32E x_12_2_x_4_1Q(.Q(x_12_2_tmp_d_array_0),.Q31(x_12_2_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[4:4]),.CLK(clk),.CE(VCC));
SRLC32E x_12_1_x_4_1Q(.Q(x_12_1_tmp_d_array_0),.Q31(x_12_1_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[5:5]),.CLK(clk),.CE(VCC));
SRLC32E x_12_0_x_4_1Q(.Q(x_12_0_tmp_d_array_0),.Q31(x_12_0_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[6:6]),.CLK(clk),.CE(VCC));
SRLC32E x_12_x_4_1Q(.Q(x_12_tmp_d_array_0),.Q31(x_12_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_8[7:7]),.CLK(clk),.CE(VCC));
SRLC32E x_7_6_x_7_1Q(.Q(x_7_6_tmp_d_array_0),.Q31(x_7_6_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[0:0]),.CLK(clk),.CE(VCC));
SRLC32E x_7_5_x_7_1Q(.Q(x_7_5_tmp_d_array_0),.Q31(x_7_5_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[1:1]),.CLK(clk),.CE(VCC));
SRLC32E x_7_4_x_7_1Q(.Q(x_7_4_tmp_d_array_0),.Q31(x_7_4_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[2:2]),.CLK(clk),.CE(VCC));
SRLC32E x_7_3_x_7_1Q(.Q(x_7_3_tmp_d_array_0),.Q31(x_7_3_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[3:3]),.CLK(clk),.CE(VCC));
SRLC32E x_7_2_x_7_1Q(.Q(x_7_2_tmp_d_array_0),.Q31(x_7_2_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[4:4]),.CLK(clk),.CE(VCC));
SRLC32E x_7_1_x_7_1Q(.Q(x_7_1_tmp_d_array_0),.Q31(x_7_1_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[5:5]),.CLK(clk),.CE(VCC));
SRLC32E x_7_0_x_7_1Q(.Q(x_7_0_tmp_d_array_0),.Q31(x_7_0_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[6:6]),.CLK(clk),.CE(VCC));
SRLC32E x_7_x_7_1Q(.Q(x_7_tmp_d_array_0),.Q31(x_7_x_7_1Q_Q31),.A({GND,GND,GND,GND,VCC}),.D(x_4[7:7]),.CLK(clk),.CE(VCC));
SRLC32E x_4_6_x_4_1Q(.Q(x_4_6_tmp_d_array_0),.Q31(x_4_6_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[0:0]),.CLK(clk),.CE(VCC));
SRLC32E x_4_5_x_4_1Q(.Q(x_4_5_tmp_d_array_0),.Q31(x_4_5_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[1:1]),.CLK(clk),.CE(VCC));
SRLC32E x_4_4_x_4_1Q(.Q(x_4_4_tmp_d_array_0),.Q31(x_4_4_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[2:2]),.CLK(clk),.CE(VCC));
SRLC32E x_4_3_x_4_1Q(.Q(x_4_3_tmp_d_array_0),.Q31(x_4_3_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[3:3]),.CLK(clk),.CE(VCC));
SRLC32E x_4_2_x_4_1Q(.Q(x_4_2_tmp_d_array_0),.Q31(x_4_2_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[4:4]),.CLK(clk),.CE(VCC));
SRLC32E x_4_1_x_4_1Q(.Q(x_4_1_tmp_d_array_0),.Q31(x_4_1_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[5:5]),.CLK(clk),.CE(VCC));
SRLC32E x_4_0_x_4_1Q(.Q(x_4_0_tmp_d_array_0),.Q31(x_4_0_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[6:6]),.CLK(clk),.CE(VCC));
SRLC32E x_4_x_4_1Q(.Q(x_4_tmp_d_array_0),.Q31(x_4_x_4_1Q_Q31),.A({GND,GND,GND,VCC,GND}),.D(x_0[7:7]),.CLK(clk),.CE(VCC));
LUT1 un1_x_10_4_s_8_false_cZ(.I0(GND),.O(un1_x_10_4_s_8_false));
defparam un1_x_10_4_s_8_false_cZ.INIT=2'h0;
LUT3 un84_sop_1_6_0_s_0_lut(.I0(un1_x_1[4:4]),.I1(un1_x_2[5:5]),.I2(un1_x_3[4:4]),.O(un84_sop_1_6[0:0]));
defparam un84_sop_1_6_0_s_0_lut.INIT=8'h96;
LUT3 un84_sop_0_0_0_11_6_0_s_0_lut(.I0(un1_x_12_0_0[4:4]),.I1(un1_x_13_0_0[5:5]),.I2(un1_x_14_0_0[4:4]),.O(un84_sop_0_0_0_0_11_6[0:0]));
defparam un84_sop_0_0_0_11_6_0_s_0_lut.INIT=8'h96;
LUT3 un84_sop_0_0_0_6_6_0_s_0_lut(.I0(un1_x_7_0[2:2]),.I1(un1_x_8_0[4:4]),.I2(un1_x_9_0[5:5]),.O(un84_sop_0_0_0_1_6_6[0:0]));
defparam un84_sop_0_0_0_6_6_0_s_0_lut.INIT=8'h96;
LUT2 un84_sop_0_0_0_6_0_axb_0_0_cZ(.I0(un1_x_12_0_0[4:4]),.I1(un1_x_13_0_0[5:5]),.O(un84_sop_0_0_0_6_0_axb_0_0));
defparam un84_sop_0_0_0_6_0_axb_0_0_cZ.INIT=4'h6;
LUT3 un84_sop_0_0_0_11_6_0_axb_12_cZ(.I0(un1_x_12_0_0[15:15]),.I1(un1_x_13_0_0[15:15]),.I2(un1_x_14_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_axb_12));
defparam un84_sop_0_0_0_11_6_0_axb_12_cZ.INIT=8'h7E;
LUT2 un84_sop_0_0_0_6_0_axb_0_1_cZ(.I0(un1_x_7_0[2:2]),.I1(un1_x_8_0[4:4]),.O(un84_sop_0_0_0_6_0_axb_0_1));
defparam un84_sop_0_0_0_6_0_axb_0_1_cZ.INIT=4'h6;
LUT4 un84_sop_0_0_0_6_6_0_axb_12_cZ(.I0(un1_x_7_0[13:13]),.I1(un1_x_7_0[14:14]),.I2(un1_x_8_0[15:15]),.I3(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_12));
defparam un84_sop_0_0_0_6_6_0_axb_12_cZ.INIT=16'h399C;
LUT4 un84_sop_0_0_0_6_6_0_axb_13_cZ(.I0(un1_x_7_0[14:14]),.I1(un1_x_7_0[15:15]),.I2(un1_x_8_0[15:15]),.I3(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_13));
defparam un84_sop_0_0_0_6_6_0_axb_13_cZ.INIT=16'h399C;
LUT2 un84_sop_0_0_0_1_6_8_axb_0(.I0(un84_sop_0_0_0_10_0[3:3]),.I1(x_4[0:0]),.O(un84_sop_0_0_0_1_6_8[3:3]));
defparam un84_sop_0_0_0_1_6_8_axb_0.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_8_axb_1_cZ(.I0(un84_sop_0_0_0_10_0[4:4]),.I1(x_4[1:1]),.O(un84_sop_0_0_0_1_6_8_axb_1));
defparam un84_sop_0_0_0_1_6_8_axb_1_cZ.INIT=4'h6;
LUT4 un84_sop_0_0_0_1_6_8_axb_9_cZ(.I0(un84_sop_0_0_0_10_0[11:11]),.I1(un84_sop_0_0_0_10_0[12:12]),.I2(x_4[6:6]),.I3(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_9));
defparam un84_sop_0_0_0_1_6_8_axb_9_cZ.INIT=16'h366C;
LUT2 un84_sop_0_0_0_1_6_8_axb_10_cZ(.I0(un84_sop_0_0_0_10_0[13:13]),.I1(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_10));
defparam un84_sop_0_0_0_1_6_8_axb_10_cZ.INIT=4'h6;
LUT2 un84_sop_1_6_0_axb_0_0_cZ(.I0(un1_x_1[4:4]),.I1(un1_x_2[5:5]),.O(un84_sop_1_6_0_axb_0_0));
defparam un84_sop_1_6_0_axb_0_0_cZ.INIT=4'h6;
LUT3 un84_sop_1_6_0_axb_12_cZ(.I0(un1_x_1[15:15]),.I1(un1_x_2[15:15]),.I2(un1_x_3[15:15]),.O(un84_sop_1_6_0_axb_12));
defparam un84_sop_1_6_0_axb_12_cZ.INIT=8'h7E;
LUT3 un1_x_10_axb_4_cZ(.I0(un1_x_10_4[4:4]),.I1(x_8[0:0]),.I2(x_8[1:1]),.O(un1_x_10_axb_4));
defparam un1_x_10_axb_4_cZ.INIT=8'h96;
LUT4 un1_x_10_axb_5_cZ(.I0(un1_x_10_4[5:5]),.I1(x_8[0:0]),.I2(x_8[1:1]),.I3(x_8[2:2]),.O(un1_x_10_axb_5));
defparam un1_x_10_axb_5_cZ.INIT=16'hA956;
LUT3 un1_x_10_axb_8_cZ(.I0(un1_x_10_4[8:8]),.I1(un1_x_10_5_c5),.I2(x_8[5:5]),.O(un1_x_10_axb_8));
defparam un1_x_10_axb_8_cZ.INIT=8'h69;
LUT4 un1_x_10_axb_9_cZ(.I0(un1_x_10_5_c5),.I1(x_8[5:5]),.I2(x_8[6:6]),.I3(x_8[7:7]),.O(un1_x_10_axb_9));
defparam un1_x_10_axb_9_cZ.INIT=16'hD22D;
LUT3 un1_x_10_axb_10_cZ(.I0(un1_x_10_5_c5),.I1(x_8[5:5]),.I2(x_8[6:6]),.O(un1_x_10_axb_10));
defparam un1_x_10_axb_10_cZ.INIT=8'hFD;
LUT2 un84_sop_0_0_0_1_6_4_axb_0(.I0(un1_x_6_0[1:1]),.I1(un84_sop_0_0_0_10_0[0:0]),.O(un84_sop_0_0_0_1_6_4[0:0]));
defparam un84_sop_0_0_0_1_6_4_axb_0.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_1_cZ(.I0(un1_x_6_0[2:2]),.I1(un84_sop_0_0_0_10_0[1:1]),.O(un84_sop_0_0_0_1_6_4_axb_1));
defparam un84_sop_0_0_0_1_6_4_axb_1_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_2_cZ(.I0(un1_x_6_0[3:3]),.I1(un84_sop_0_0_0_10_0[2:2]),.O(un84_sop_0_0_0_1_6_4_axb_2));
defparam un84_sop_0_0_0_1_6_4_axb_2_cZ.INIT=4'h6;
LUT3 un84_sop_0_0_0_1_6_4_axb_3_cZ(.I0(un1_x_6_0[4:4]),.I1(un84_sop_0_0_0_10_0[3:3]),.I2(x_4[0:0]),.O(un84_sop_0_0_0_1_6_4_axb_3));
defparam un84_sop_0_0_0_1_6_4_axb_3_cZ.INIT=8'h96;
LUT2 un84_sop_0_0_0_1_6_4_axb_4_cZ(.I0(un1_x_6_0[5:5]),.I1(un84_sop_0_0_0_1_6_8[4:4]),.O(un84_sop_0_0_0_1_6_4_axb_4));
defparam un84_sop_0_0_0_1_6_4_axb_4_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_5_cZ(.I0(un1_x_6_0[6:6]),.I1(un84_sop_0_0_0_1_6_8[5:5]),.O(un84_sop_0_0_0_1_6_4_axb_5));
defparam un84_sop_0_0_0_1_6_4_axb_5_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_6_cZ(.I0(un1_x_6_0[7:7]),.I1(un84_sop_0_0_0_1_6_8[6:6]),.O(un84_sop_0_0_0_1_6_4_axb_6));
defparam un84_sop_0_0_0_1_6_4_axb_6_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_7_cZ(.I0(un1_x_6_0[8:8]),.I1(un84_sop_0_0_0_1_6_8[7:7]),.O(un84_sop_0_0_0_1_6_4_axb_7));
defparam un84_sop_0_0_0_1_6_4_axb_7_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_8_cZ(.I0(un1_x_6_0[9:9]),.I1(un84_sop_0_0_0_1_6_8[8:8]),.O(un84_sop_0_0_0_1_6_4_axb_8));
defparam un84_sop_0_0_0_1_6_4_axb_8_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_9_cZ(.I0(un1_x_6_0[10:10]),.I1(un84_sop_0_0_0_1_6_8[9:9]),.O(un84_sop_0_0_0_1_6_4_axb_9));
defparam un84_sop_0_0_0_1_6_4_axb_9_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_10_cZ(.I0(un1_x_6_0[11:11]),.I1(un84_sop_0_0_0_1_6_8[10:10]),.O(un84_sop_0_0_0_1_6_4_axb_10));
defparam un84_sop_0_0_0_1_6_4_axb_10_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_11_cZ(.I0(un1_x_6_0[12:12]),.I1(un84_sop_0_0_0_1_6_8[11:11]),.O(un84_sop_0_0_0_1_6_4_axb_11));
defparam un84_sop_0_0_0_1_6_4_axb_11_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_12_cZ(.I0(un1_x_6_0[13:13]),.I1(un84_sop_0_0_0_1_6_8[12:12]),.O(un84_sop_0_0_0_1_6_4_axb_12));
defparam un84_sop_0_0_0_1_6_4_axb_12_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_13_cZ(.I0(un1_x_6_0[14:14]),.I1(un84_sop_0_0_0_1_6_8[13:13]),.O(un84_sop_0_0_0_1_6_4_axb_13));
defparam un84_sop_0_0_0_1_6_4_axb_13_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_1_cZ(.I0(un1_x_4[3:3]),.I1(un84_sop_0_0_0_0_5[1:1]),.O(un84_sop_1_7_axb_1));
defparam un84_sop_1_7_axb_1_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_2_cZ(.I0(un1_x_4[4:4]),.I1(un84_sop_0_0_0_0_5[2:2]),.O(un84_sop_1_7_axb_2));
defparam un84_sop_1_7_axb_2_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_3_cZ(.I0(un1_x_4[5:5]),.I1(un84_sop_0_0_0_0_5[3:3]),.O(un84_sop_1_7_axb_3));
defparam un84_sop_1_7_axb_3_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_4_cZ(.I0(un1_x_4[6:6]),.I1(un84_sop_0_0_0_0_5[4:4]),.O(un84_sop_1_7_axb_4));
defparam un84_sop_1_7_axb_4_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_5_cZ(.I0(un1_x_4[7:7]),.I1(un84_sop_0_0_0_0_5[5:5]),.O(un84_sop_1_7_axb_5));
defparam un84_sop_1_7_axb_5_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_6_cZ(.I0(un1_x_4[8:8]),.I1(un84_sop_0_0_0_0_5[6:6]),.O(un84_sop_1_7_axb_6));
defparam un84_sop_1_7_axb_6_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_7_cZ(.I0(un1_x_4[9:9]),.I1(un84_sop_0_0_0_0_5[7:7]),.O(un84_sop_1_7_axb_7));
defparam un84_sop_1_7_axb_7_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_8_cZ(.I0(un1_x_4[10:10]),.I1(un84_sop_0_0_0_0_5[8:8]),.O(un84_sop_1_7_axb_8));
defparam un84_sop_1_7_axb_8_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_9_cZ(.I0(un1_x_4[11:11]),.I1(un84_sop_0_0_0_0_5[9:9]),.O(un84_sop_1_7_axb_9));
defparam un84_sop_1_7_axb_9_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_10_cZ(.I0(un1_x_4[12:12]),.I1(un84_sop_0_0_0_0_5[10:10]),.O(un84_sop_1_7_axb_10));
defparam un84_sop_1_7_axb_10_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_11_cZ(.I0(un1_x_4[13:13]),.I1(un84_sop_0_0_0_0_5[11:11]),.O(un84_sop_1_7_axb_11));
defparam un84_sop_1_7_axb_11_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_12_cZ(.I0(un1_x_4[14:14]),.I1(un84_sop_0_0_0_0_5[12:12]),.O(un84_sop_1_7_axb_12));
defparam un84_sop_1_7_axb_12_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_13_cZ(.I0(un1_x_4[15:15]),.I1(un84_sop_0_0_0_0_5[13:13]),.O(un84_sop_1_7_axb_13));
defparam un84_sop_1_7_axb_13_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_0(.I0(un84_sop_0_0_0_0_0[0:0]),.I1(x_9),.O(un84_sop_0_0_0_0_11_7[0:0]));
defparam un84_sop_0_0_0_0_11_7_axb_0.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_1_cZ(.I0(un1_x_11_0_0[7:7]),.I1(un84_sop_0_0_0_0_0[1:1]),.O(un84_sop_0_0_0_0_11_7_axb_1));
defparam un84_sop_0_0_0_0_11_7_axb_1_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_2_cZ(.I0(un1_x_11_0_0[8:8]),.I1(un84_sop_0_0_0_0_0[2:2]),.O(un84_sop_0_0_0_0_11_7_axb_2));
defparam un84_sop_0_0_0_0_11_7_axb_2_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_3_cZ(.I0(un1_x_11_0_0[9:9]),.I1(un84_sop_0_0_0_0_0[3:3]),.O(un84_sop_0_0_0_0_11_7_axb_3));
defparam un84_sop_0_0_0_0_11_7_axb_3_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_4_cZ(.I0(un1_x_11_0_0[10:10]),.I1(un84_sop_0_0_0_0_0[4:4]),.O(un84_sop_0_0_0_0_11_7_axb_4));
defparam un84_sop_0_0_0_0_11_7_axb_4_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_5_cZ(.I0(un1_x_11_0_0[11:11]),.I1(un84_sop_0_0_0_0_0[5:5]),.O(un84_sop_0_0_0_0_11_7_axb_5));
defparam un84_sop_0_0_0_0_11_7_axb_5_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_6_cZ(.I0(un1_x_11_0_0[12:12]),.I1(un84_sop_0_0_0_0_0[6:6]),.O(un84_sop_0_0_0_0_11_7_axb_6));
defparam un84_sop_0_0_0_0_11_7_axb_6_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_7_cZ(.I0(un1_x_11_0_0[13:13]),.I1(un84_sop_0_0_0_0_0[7:7]),.O(un84_sop_0_0_0_0_11_7_axb_7));
defparam un84_sop_0_0_0_0_11_7_axb_7_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_8_cZ(.I0(un1_x_11_0_0[14:14]),.I1(un84_sop_0_0_0_0_0[8:8]),.O(un84_sop_0_0_0_0_11_7_axb_8));
defparam un84_sop_0_0_0_0_11_7_axb_8_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_9_cZ(.I0(un1_x_11_0_0[14:14]),.I1(un84_sop_0_0_0_0_0[9:9]),.O(un84_sop_0_0_0_0_11_7_axb_9));
defparam un84_sop_0_0_0_0_11_7_axb_9_cZ.INIT=4'h6;
LUT3 un84_sop_1_4_cry_0_RNO(.I0(un1_x_4[2:2]),.I1(un84_sop_0_0_0_0_5[0:0]),.I2(x_0[0:0]),.O(un84_sop_1_4[0:0]));
defparam un84_sop_1_4_cry_0_RNO.INIT=8'h96;
LUT3 un84_sop_1_4_axb_1_cZ(.I0(un84_sop_1_7[1:1]),.I1(x_0[0:0]),.I2(x_0[1:1]),.O(un84_sop_1_4_axb_1));
defparam un84_sop_1_4_axb_1_cZ.INIT=8'h96;
LUT4 un84_sop_1_4_axb_2_cZ(.I0(un84_sop_1_7[2:2]),.I1(x_0[0:0]),.I2(x_0[1:1]),.I3(x_0[2:2]),.O(un84_sop_1_4_axb_2));
defparam un84_sop_1_4_axb_2_cZ.INIT=16'hA956;
LUT4 un84_sop_1_4_axb_5_cZ(.I0(un1_x_0_0_c4),.I1(un84_sop_1_7[5:5]),.I2(x_0[4:4]),.I3(x_0[5:5]),.O(un84_sop_1_4_axb_5));
defparam un84_sop_1_4_axb_5_cZ.INIT=16'hC639;
LUT4 un84_sop_1_axb_0_cZ(.I0(un1_x_4[2:2]),.I1(un84_sop_0_0_0_0_5[0:0]),.I2(un84_sop_1_6[0:0]),.I3(x_0[0:0]),.O(un84_sop_1_axb_0));
defparam un84_sop_1_axb_0_cZ.INIT=16'h6996;
LUT2 un84_sop_1_axb_1_cZ(.I0(un84_sop_1_4[1:1]),.I1(un84_sop_1_6[1:1]),.O(un84_sop_1_axb_1));
defparam un84_sop_1_axb_1_cZ.INIT=4'h6;
LUT2 un84_sop_1_axb_2_cZ(.I0(un84_sop_1_4[2:2]),.I1(un84_sop_1_6[2:2]),.O(un84_sop_1_axb_2));
defparam un84_sop_1_axb_2_cZ.INIT=4'h6;
LUT2 un84_sop_1_axb_3_cZ(.I0(un84_sop_1_4[3:3]),.I1(un84_sop_1_6[3:3]),.O(un84_sop_1_axb_3));
defparam un84_sop_1_axb_3_cZ.INIT=4'h6;
LUT2 un84_sop_1_axb_4_cZ(.I0(un84_sop_1_4[4:4]),.I1(un84_sop_1_6[4:4]),.O(un84_sop_1_axb_4));
defparam un84_sop_1_axb_4_cZ.INIT=4'h6;
LUT2 un84_sop_1_axb_5_cZ(.I0(un84_sop_1_4[5:5]),.I1(un84_sop_1_6[5:5]),.O(un84_sop_1_axb_5));
defparam un84_sop_1_axb_5_cZ.INIT=4'h6;
LUT2 un84_sop_1_axb_6_cZ(.I0(un84_sop_1_4[6:6]),.I1(un84_sop_1_6[6:6]),.O(un84_sop_1_axb_6));
defparam un84_sop_1_axb_6_cZ.INIT=4'h6;
LUT2 un1_x_10_4_cry_1_RNO(.I0(x_8[0:0]),.I1(x_8[1:1]),.O(un1_x_10_4_cry_1_sf));
defparam un1_x_10_4_cry_1_RNO.INIT=4'h6;
LUT2 un1_x_10_4_axb_2_cZ(.I0(x_8[1:1]),.I1(x_8[2:2]),.O(un1_x_10_4_axb_2));
defparam un1_x_10_4_axb_2_cZ.INIT=4'h6;
LUT2 un1_x_10_4_axb_3_cZ(.I0(x_8[2:2]),.I1(x_8[3:3]),.O(un1_x_10_4_axb_3));
defparam un1_x_10_4_axb_3_cZ.INIT=4'h6;
LUT2 un1_x_10_4_axb_4_cZ(.I0(x_8[3:3]),.I1(x_8[4:4]),.O(un1_x_10_4_axb_4));
defparam un1_x_10_4_axb_4_cZ.INIT=4'h6;
LUT2 un1_x_10_4_axb_5_cZ(.I0(x_8[4:4]),.I1(x_8[5:5]),.O(un1_x_10_4_axb_5));
defparam un1_x_10_4_axb_5_cZ.INIT=4'h6;
LUT2 un1_x_10_4_axb_6_cZ(.I0(x_8[5:5]),.I1(x_8[6:6]),.O(un1_x_10_4_axb_6));
defparam un1_x_10_4_axb_6_cZ.INIT=4'h6;
LUT2 un1_x_10_4_axb_7_cZ(.I0(x_8[6:6]),.I1(x_8[7:7]),.O(un1_x_10_4_axb_7));
defparam un1_x_10_4_axb_7_cZ.INIT=4'h6;
LUT1 un1_x_15_0_axb_0_cZ(.I0(x_12[0:0]),.O(un1_x_15_0_axb_0));
defparam un1_x_15_0_axb_0_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_1_cZ(.I0(x_12[1:1]),.O(un1_x_15_0_axb_1));
defparam un1_x_15_0_axb_1_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_2_cZ(.I0(x_12[2:2]),.O(un1_x_15_0_axb_2));
defparam un1_x_15_0_axb_2_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_3_cZ(.I0(x_12[3:3]),.O(un1_x_15_0_axb_3));
defparam un1_x_15_0_axb_3_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_4_cZ(.I0(x_12[4:4]),.O(un1_x_15_0_axb_4));
defparam un1_x_15_0_axb_4_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_5_cZ(.I0(x_12[5:5]),.O(un1_x_15_0_axb_5));
defparam un1_x_15_0_axb_5_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_6_cZ(.I0(x_12[6:6]),.O(un1_x_15_0_axb_6));
defparam un1_x_15_0_axb_6_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_7_cZ(.I0(x_12[7:7]),.O(un1_x_15_0_axb_7));
defparam un1_x_15_0_axb_7_cZ.INIT=2'h1;
LUT1 un1_x_11_0_axb_0_cZ(.I0(x_8[0:0]),.O(un1_x_11_0_axb_0));
defparam un1_x_11_0_axb_0_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_0_cZ(.I0(x_13[0:0]),.O(un1_x_16_0_axb_0));
defparam un1_x_16_0_axb_0_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_1_cZ(.I0(x_13[1:1]),.O(un1_x_16_0_axb_1));
defparam un1_x_16_0_axb_1_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_2_cZ(.I0(x_13[2:2]),.O(un1_x_16_0_axb_2));
defparam un1_x_16_0_axb_2_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_3_cZ(.I0(x_13[3:3]),.O(un1_x_16_0_axb_3));
defparam un1_x_16_0_axb_3_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_4_cZ(.I0(x_13[4:4]),.O(un1_x_16_0_axb_4));
defparam un1_x_16_0_axb_4_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_5_cZ(.I0(x_13[5:5]),.O(un1_x_16_0_axb_5));
defparam un1_x_16_0_axb_5_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_6_cZ(.I0(x_13[6:6]),.O(un1_x_16_0_axb_6));
defparam un1_x_16_0_axb_6_cZ.INIT=2'h1;
LUT1 un1_x_16_0_axb_7_cZ(.I0(x_13[7:7]),.O(un1_x_16_0_axb_7));
defparam un1_x_16_0_axb_7_cZ.INIT=2'h1;
LUT2 un84_sop_0_0_0_0_11_7_axb_0_ci_cZ(.I0(un84_sop_0_0_0_0_0[0:0]),.I1(x_9),.O(un84_sop_0_0_0_0_11_7_axb_0_ci));
defparam un84_sop_0_0_0_0_11_7_axb_0_ci_cZ.INIT=4'h6;
LUT1 un84_sop_0_0_0_11_6_0_cry_0_thru(.I0(un1_x_14_0_0[4:4]),.O(un1_x_14_0_0_0[4:4]));
defparam un84_sop_0_0_0_11_6_0_cry_0_thru.INIT=2'h2;
LUT1 un84_sop_0_0_0_6_6_0_cry_0_thru(.I0(un1_x_9_0[5:5]),.O(un1_x_9_0_0[5:5]));
defparam un84_sop_0_0_0_6_6_0_cry_0_thru.INIT=2'h2;
LUT1 un84_sop_1_6_0_cry_0_thru(.I0(un1_x_3[4:4]),.O(un1_x_3_0[4:4]));
defparam un84_sop_1_6_0_cry_0_thru.INIT=2'h2;
p_O_FD desc0(.Q(x_0[0:0]),.D(x_in[0:0]),.C(clk),.E(p_desc0_p_O_FD));
p_O_FD desc1(.Q(x_0[1:1]),.D(x_in[1:1]),.C(clk),.E(p_desc1_p_O_FD));
p_O_FD desc2(.Q(x_0[2:2]),.D(x_in[2:2]),.C(clk),.E(p_desc2_p_O_FD));
p_O_FD desc3(.Q(x_0[3:3]),.D(x_in[3:3]),.C(clk),.E(p_desc3_p_O_FD));
p_O_FD desc4(.Q(x_0[4:4]),.D(x_in[4:4]),.C(clk),.E(p_desc4_p_O_FD));
p_O_FD desc5(.Q(x_0[5:5]),.D(x_in[5:5]),.C(clk),.E(p_desc5_p_O_FD));
p_O_FD desc6(.Q(x_0[6:6]),.D(x_in[6:6]),.C(clk),.E(p_desc6_p_O_FD));
p_O_FD desc7(.Q(x_0[7:7]),.D(x_in[7:7]),.C(clk),.E(p_desc7_p_O_FD));
p_O_FD desc8(.Q(y[7:7]),.D(un84_sop_1_s_14),.C(clk),.E(p_desc8_p_O_FD));
p_O_FD desc9(.Q(y[0:0]),.D(un84_sop_1_s_7),.C(clk),.E(p_desc9_p_O_FD));
p_O_FD desc10(.Q(y[1:1]),.D(un84_sop_1_s_8),.C(clk),.E(p_desc10_p_O_FD));
p_O_FD desc11(.Q(y[2:2]),.D(un84_sop_1_s_9),.C(clk),.E(p_desc11_p_O_FD));
p_O_FD desc12(.Q(y[3:3]),.D(un84_sop_1_s_10),.C(clk),.E(p_desc12_p_O_FD));
p_O_FD desc13(.Q(y[4:4]),.D(un84_sop_1_s_11),.C(clk),.E(p_desc13_p_O_FD));
p_O_FD desc14(.Q(y[5:5]),.D(un84_sop_1_s_12),.C(clk),.E(p_desc14_p_O_FD));
p_O_FD desc15(.Q(y[6:6]),.D(un84_sop_1_s_13),.C(clk),.E(p_desc15_p_O_FD));
p_O_FD desc16(.Q(x_8[7:7]),.D(x_7[7:7]),.C(clk),.E(p_desc16_p_O_FD));
p_O_FD desc17(.Q(x_8[6:6]),.D(x_7[6:6]),.C(clk),.E(p_desc17_p_O_FD));
p_O_FD desc18(.Q(x_8[5:5]),.D(x_7[5:5]),.C(clk),.E(p_desc18_p_O_FD));
p_O_FD desc19(.Q(x_8[4:4]),.D(x_7[4:4]),.C(clk),.E(p_desc19_p_O_FD));
p_O_FD desc20(.Q(x_8[3:3]),.D(x_7[3:3]),.C(clk),.E(p_desc20_p_O_FD));
p_O_FD desc21(.Q(x_8[2:2]),.D(x_7[2:2]),.C(clk),.E(p_desc21_p_O_FD));
p_O_FD desc22(.Q(x_8[1:1]),.D(x_7[1:1]),.C(clk),.E(p_desc22_p_O_FD));
p_O_FD desc23(.Q(x_8[0:0]),.D(x_7[0:0]),.C(clk),.E(p_desc23_p_O_FD));
p_O_FD desc24(.Q(x_9),.D(x_8[0:0]),.C(clk),.E(p_desc24_p_O_FD));
p_O_FD desc25(.Q(x_13[7:7]),.D(x_12[7:7]),.C(clk),.E(p_desc25_p_O_FD));
p_O_FD desc26(.Q(x_13[6:6]),.D(x_12[6:6]),.C(clk),.E(p_desc26_p_O_FD));
p_O_FD desc27(.Q(x_13[5:5]),.D(x_12[5:5]),.C(clk),.E(p_desc27_p_O_FD));
p_O_FD desc28(.Q(x_13[4:4]),.D(x_12[4:4]),.C(clk),.E(p_desc28_p_O_FD));
p_O_FD desc29(.Q(x_13[3:3]),.D(x_12[3:3]),.C(clk),.E(p_desc29_p_O_FD));
p_O_FD desc30(.Q(x_13[2:2]),.D(x_12[2:2]),.C(clk),.E(p_desc30_p_O_FD));
p_O_FD desc31(.Q(x_13[1:1]),.D(x_12[1:1]),.C(clk),.E(p_desc31_p_O_FD));
p_O_FD desc32(.Q(x_13[0:0]),.D(x_12[0:0]),.C(clk),.E(p_desc32_p_O_FD));
p_O_FD x_14_pipe_0_Z(.Q(un84_sop_0_0_0_0_0[0:0]),.D(un84_sop_0_0_0_0_1[0:0]),.C(clk),.E(p_x_14_pipe_0_Z_p_O_FD));
p_O_FD x_14_pipe_9_Z(.Q(un84_sop_0_0_0_0_0[1:1]),.D(un84_sop_0_0_0_0_1[1:1]),.C(clk),.E(p_x_14_pipe_9_Z_p_O_FD));
p_O_FD x_14_pipe_10_Z(.Q(un84_sop_0_0_0_0_0[2:2]),.D(un84_sop_0_0_0_0_1[2:2]),.C(clk),.E(p_x_14_pipe_10_Z_p_O_FD));
p_O_FD x_14_pipe_11_Z(.Q(un84_sop_0_0_0_0_0[3:3]),.D(un84_sop_0_0_0_0_1[3:3]),.C(clk),.E(p_x_14_pipe_11_Z_p_O_FD));
p_O_FD x_14_pipe_12_Z(.Q(un84_sop_0_0_0_0_0[4:4]),.D(un84_sop_0_0_0_0_1[4:4]),.C(clk),.E(p_x_14_pipe_12_Z_p_O_FD));
p_O_FD x_14_pipe_13_Z(.Q(un84_sop_0_0_0_0_0[5:5]),.D(un84_sop_0_0_0_0_1[5:5]),.C(clk),.E(p_x_14_pipe_13_Z_p_O_FD));
p_O_FD x_14_pipe_14_Z(.Q(un84_sop_0_0_0_0_0[6:6]),.D(un84_sop_0_0_0_0_1[6:6]),.C(clk),.E(p_x_14_pipe_14_Z_p_O_FD));
p_O_FD x_14_pipe_15_Z(.Q(un84_sop_0_0_0_0_0[7:7]),.D(un84_sop_0_0_0_0_1[7:7]),.C(clk),.E(p_x_14_pipe_15_Z_p_O_FD));
p_O_FD x_14_pipe_16_Z(.Q(un84_sop_0_0_0_0_0[8:8]),.D(un84_sop_0_0_0_0_1[8:8]),.C(clk),.E(p_x_14_pipe_16_Z_p_O_FD));
p_O_FD x_14_pipe_17_Z(.Q(un84_sop_0_0_0_0_0[9:9]),.D(un84_sop_0_0_0_0_1[9:9]),.C(clk),.E(p_x_14_pipe_17_Z_p_O_FD));
p_O_FD x_9_pipe_1_Z(.Q(un1_x_11_0_0[7:7]),.D(un1_x_11_0_0_0[7:7]),.C(clk),.E(p_x_9_pipe_1_Z_p_O_FD));
p_O_FD x_9_pipe_2_Z(.Q(un1_x_11_0_0[8:8]),.D(un1_x_11_0_0_0[8:8]),.C(clk),.E(p_x_9_pipe_2_Z_p_O_FD));
p_O_FD x_9_pipe_3_Z(.Q(un1_x_11_0_0[9:9]),.D(un1_x_11_0_0_0[9:9]),.C(clk),.E(p_x_9_pipe_3_Z_p_O_FD));
p_O_FD x_9_pipe_4_Z(.Q(un1_x_11_0_0[10:10]),.D(un1_x_11_0_0_0[10:10]),.C(clk),.E(p_x_9_pipe_4_Z_p_O_FD));
p_O_FD x_9_pipe_5_Z(.Q(un1_x_11_0_0[11:11]),.D(un1_x_11_0_0_0[11:11]),.C(clk),.E(p_x_9_pipe_5_Z_p_O_FD));
p_O_FD x_9_pipe_6_Z(.Q(un1_x_11_0_0[12:12]),.D(un1_x_11_0_0_0[12:12]),.C(clk),.E(p_x_9_pipe_6_Z_p_O_FD));
p_O_FD x_9_pipe_7_Z(.Q(un1_x_11_0_0[13:13]),.D(un1_x_11_0_0_0[13:13]),.C(clk),.E(p_x_9_pipe_7_Z_p_O_FD));
p_O_FD x_9_pipe_8_Z(.Q(un1_x_11_0_0[14:14]),.D(un1_x_11_0_0_0[14:14]),.C(clk),.E(p_x_9_pipe_8_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_15_Z(.Q(un84_sop_0_0_0_10_0[0:0]),.D(un84_sop_0_0_0_0_8[0:0]),.C(clk),.E(p_x_15_pipe_0_0_15_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_16_Z(.Q(un84_sop_0_0_0_10_0[1:1]),.D(un84_sop_0_0_0_0_8[1:1]),.C(clk),.E(p_x_15_pipe_0_0_16_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_17_Z(.Q(un84_sop_0_0_0_10_0[2:2]),.D(un84_sop_0_0_0_0_8[2:2]),.C(clk),.E(p_x_15_pipe_0_0_17_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_18_Z(.Q(un84_sop_0_0_0_10_0[3:3]),.D(un84_sop_0_0_0_0_8[3:3]),.C(clk),.E(p_x_15_pipe_0_0_18_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_19_Z(.Q(un84_sop_0_0_0_10_0[4:4]),.D(un84_sop_0_0_0_0_8[4:4]),.C(clk),.E(p_x_15_pipe_0_0_19_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_20_Z(.Q(un84_sop_0_0_0_10_0[5:5]),.D(un84_sop_0_0_0_0_8[5:5]),.C(clk),.E(p_x_15_pipe_0_0_20_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_21_Z(.Q(un84_sop_0_0_0_10_0[6:6]),.D(un84_sop_0_0_0_0_8[6:6]),.C(clk),.E(p_x_15_pipe_0_0_21_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_22_Z(.Q(un84_sop_0_0_0_10_0[7:7]),.D(un84_sop_0_0_0_0_8[7:7]),.C(clk),.E(p_x_15_pipe_0_0_22_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_23_Z(.Q(un84_sop_0_0_0_10_0[8:8]),.D(un84_sop_0_0_0_0_8[8:8]),.C(clk),.E(p_x_15_pipe_0_0_23_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_24_Z(.Q(un84_sop_0_0_0_10_0[9:9]),.D(un84_sop_0_0_0_0_8[9:9]),.C(clk),.E(p_x_15_pipe_0_0_24_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_25_Z(.Q(un84_sop_0_0_0_10_0[10:10]),.D(un84_sop_0_0_0_0_8[10:10]),.C(clk),.E(p_x_15_pipe_0_0_25_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_26_Z(.Q(un84_sop_0_0_0_10_0[11:11]),.D(un84_sop_0_0_0_0_8[11:11]),.C(clk),.E(p_x_15_pipe_0_0_26_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_27_Z(.Q(un84_sop_0_0_0_10_0[12:12]),.D(un84_sop_0_0_0_0_8[12:12]),.C(clk),.E(p_x_15_pipe_0_0_27_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_28_Z(.Q(un84_sop_0_0_0_10_0[13:13]),.D(un84_sop_0_0_0_0_8[13:13]),.C(clk),.E(p_x_15_pipe_0_0_28_Z_p_O_FD));
p_O_FD x_15_pipe_0_0_29_Z(.Q(un84_sop_0_0_0_10_0[14:14]),.D(un84_sop_0_0_0_0_8[14:14]),.C(clk),.E(p_x_15_pipe_0_0_29_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_0_Z(.Q(un84_sop_0_0_0_0_5[0:0]),.D(un84_sop_0_0_0_5_0[0:0]),.C(clk),.E(p_x_16_pipe_0_0_0_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_1_Z(.Q(un84_sop_0_0_0_0_5[1:1]),.D(un84_sop_0_0_0_5_0[1:1]),.C(clk),.E(p_x_16_pipe_0_0_1_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_2_Z(.Q(un84_sop_0_0_0_0_5[2:2]),.D(un84_sop_0_0_0_5_0[2:2]),.C(clk),.E(p_x_16_pipe_0_0_2_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_3_Z(.Q(un84_sop_0_0_0_0_5[3:3]),.D(un84_sop_0_0_0_5_0[3:3]),.C(clk),.E(p_x_16_pipe_0_0_3_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_4_Z(.Q(un84_sop_0_0_0_0_5[4:4]),.D(un84_sop_0_0_0_5_0[4:4]),.C(clk),.E(p_x_16_pipe_0_0_4_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_5_Z(.Q(un84_sop_0_0_0_0_5[5:5]),.D(un84_sop_0_0_0_5_0[5:5]),.C(clk),.E(p_x_16_pipe_0_0_5_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_6_Z(.Q(un84_sop_0_0_0_0_5[6:6]),.D(un84_sop_0_0_0_5_0[6:6]),.C(clk),.E(p_x_16_pipe_0_0_6_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_7_Z(.Q(un84_sop_0_0_0_0_5[7:7]),.D(un84_sop_0_0_0_5_0[7:7]),.C(clk),.E(p_x_16_pipe_0_0_7_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_8_Z(.Q(un84_sop_0_0_0_0_5[8:8]),.D(un84_sop_0_0_0_5_0[8:8]),.C(clk),.E(p_x_16_pipe_0_0_8_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_9_Z(.Q(un84_sop_0_0_0_0_5[9:9]),.D(un84_sop_0_0_0_5_0[9:9]),.C(clk),.E(p_x_16_pipe_0_0_9_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_10_Z(.Q(un84_sop_0_0_0_0_5[10:10]),.D(un84_sop_0_0_0_5_0[10:10]),.C(clk),.E(p_x_16_pipe_0_0_10_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_11_Z(.Q(un84_sop_0_0_0_0_5[11:11]),.D(un84_sop_0_0_0_5_0[11:11]),.C(clk),.E(p_x_16_pipe_0_0_11_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_12_Z(.Q(un84_sop_0_0_0_0_5[12:12]),.D(un84_sop_0_0_0_5_0[12:12]),.C(clk),.E(p_x_16_pipe_0_0_12_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_13_Z(.Q(un84_sop_0_0_0_0_5[13:13]),.D(un84_sop_0_0_0_5_0[13:13]),.C(clk),.E(p_x_16_pipe_0_0_13_Z_p_O_FD));
p_O_FD x_16_pipe_0_0_14_Z(.Q(un84_sop_0_0_0_0_5[14:14]),.D(un84_sop_0_0_0_5_0[14:14]),.C(clk),.E(p_x_16_pipe_0_0_14_Z_p_O_FD));
p_O_FD desc33(.Q(x_4[7:7]),.D(x_4_tmp_d_array_0),.C(clk),.E(p_desc33_p_O_FD));
p_O_FD desc34(.Q(x_4[6:6]),.D(x_4_0_tmp_d_array_0),.C(clk),.E(p_desc34_p_O_FD));
p_O_FD desc35(.Q(x_4[5:5]),.D(x_4_1_tmp_d_array_0),.C(clk),.E(p_desc35_p_O_FD));
p_O_FD desc36(.Q(x_4[4:4]),.D(x_4_2_tmp_d_array_0),.C(clk),.E(p_desc36_p_O_FD));
p_O_FD desc37(.Q(x_4[3:3]),.D(x_4_3_tmp_d_array_0),.C(clk),.E(p_desc37_p_O_FD));
p_O_FD desc38(.Q(x_4[2:2]),.D(x_4_4_tmp_d_array_0),.C(clk),.E(p_desc38_p_O_FD));
p_O_FD desc39(.Q(x_4[1:1]),.D(x_4_5_tmp_d_array_0),.C(clk),.E(p_desc39_p_O_FD));
p_O_FD desc40(.Q(x_4[0:0]),.D(x_4_6_tmp_d_array_0),.C(clk),.E(p_desc40_p_O_FD));
p_O_FD desc41(.Q(x_7[7:7]),.D(x_7_tmp_d_array_0),.C(clk),.E(p_desc41_p_O_FD));
p_O_FD desc42(.Q(x_7[6:6]),.D(x_7_0_tmp_d_array_0),.C(clk),.E(p_desc42_p_O_FD));
p_O_FD desc43(.Q(x_7[5:5]),.D(x_7_1_tmp_d_array_0),.C(clk),.E(p_desc43_p_O_FD));
p_O_FD desc44(.Q(x_7[4:4]),.D(x_7_2_tmp_d_array_0),.C(clk),.E(p_desc44_p_O_FD));
p_O_FD desc45(.Q(x_7[3:3]),.D(x_7_3_tmp_d_array_0),.C(clk),.E(p_desc45_p_O_FD));
p_O_FD desc46(.Q(x_7[2:2]),.D(x_7_4_tmp_d_array_0),.C(clk),.E(p_desc46_p_O_FD));
p_O_FD desc47(.Q(x_7[1:1]),.D(x_7_5_tmp_d_array_0),.C(clk),.E(p_desc47_p_O_FD));
p_O_FD desc48(.Q(x_7[0:0]),.D(x_7_6_tmp_d_array_0),.C(clk),.E(p_desc48_p_O_FD));
p_O_FD desc49(.Q(x_12[7:7]),.D(x_12_tmp_d_array_0),.C(clk),.E(p_desc49_p_O_FD));
p_O_FD desc50(.Q(x_12[6:6]),.D(x_12_0_tmp_d_array_0),.C(clk),.E(p_desc50_p_O_FD));
p_O_FD desc51(.Q(x_12[5:5]),.D(x_12_1_tmp_d_array_0),.C(clk),.E(p_desc51_p_O_FD));
p_O_FD desc52(.Q(x_12[4:4]),.D(x_12_2_tmp_d_array_0),.C(clk),.E(p_desc52_p_O_FD));
p_O_FD desc53(.Q(x_12[3:3]),.D(x_12_3_tmp_d_array_0),.C(clk),.E(p_desc53_p_O_FD));
p_O_FD desc54(.Q(x_12[2:2]),.D(x_12_4_tmp_d_array_0),.C(clk),.E(p_desc54_p_O_FD));
p_O_FD desc55(.Q(x_12[1:1]),.D(x_12_5_tmp_d_array_0),.C(clk),.E(p_desc55_p_O_FD));
p_O_FD desc56(.Q(x_12[0:0]),.D(x_12_6_tmp_d_array_0),.C(clk),.E(p_desc56_p_O_FD));
MUXCY_L un84_sop_1_6_0_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(un1_x_3_0[4:4]),.LO(un84_sop_1_6_0_cry_0_cy));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(un1_x_9_0_0[5:5]),.LO(un84_sop_0_0_0_6_6_0_cry_0_cy));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(un1_x_14_0_0_0[4:4]),.LO(un84_sop_0_0_0_11_6_0_cry_0_cy));
LUT3 un84_sop_0_0_0_11_0_cry_2_RNO_cZ(.I0(x_8[1:1]),.I1(x_8[0:0]),.I2(un84_sop_0_0_0_0_11_7[1:1]),.O(un84_sop_0_0_0_11_0_cry_2_RNO));
defparam un84_sop_0_0_0_11_0_cry_2_RNO_cZ.INIT=8'h60;
LUT6 un84_sop_0_0_0_11_6_0_axb_8_cZ(.I0(un1_x_12_0_0[11:11]),.I1(un1_x_12_0_0[12:12]),.I2(un1_x_13_0_0[12:12]),.I3(un1_x_13_0_0[13:13]),.I4(un1_x_14_0_0[11:11]),.I5(un1_x_14_0_0[12:12]),.O(un84_sop_0_0_0_11_6_0_axb_8));
defparam un84_sop_0_0_0_11_6_0_axb_8_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_11_6_0_axb_3_cZ(.I0(un1_x_12_0_0[6:6]),.I1(un1_x_12_0_0[7:7]),.I2(un1_x_13_0_0[7:7]),.I3(un1_x_13_0_0[8:8]),.I4(un1_x_14_0_0[6:6]),.I5(un1_x_14_0_0[7:7]),.O(un84_sop_0_0_0_11_6_0_axb_3));
defparam un84_sop_0_0_0_11_6_0_axb_3_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_11_6_0_axb_4_cZ(.I0(un1_x_12_0_0[7:7]),.I1(un1_x_12_0_0[8:8]),.I2(un1_x_13_0_0[8:8]),.I3(un1_x_13_0_0[9:9]),.I4(un1_x_14_0_0[7:7]),.I5(un1_x_14_0_0[8:8]),.O(un84_sop_0_0_0_11_6_0_axb_4));
defparam un84_sop_0_0_0_11_6_0_axb_4_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_11_6_0_axb_9_cZ(.I0(un1_x_12_0_0[12:12]),.I1(un1_x_12_0_0[13:13]),.I2(un1_x_13_0_0[13:13]),.I3(un1_x_13_0_0[14:14]),.I4(un1_x_14_0_0[12:12]),.I5(un1_x_14_0_0[13:13]),.O(un84_sop_0_0_0_11_6_0_axb_9));
defparam un84_sop_0_0_0_11_6_0_axb_9_cZ.INIT=64'h36C96C93C936936C;
LUT5 un84_sop_0_0_0_11_6_0_axb_11_cZ(.I0(un1_x_12_0_0[14:14]),.I1(un1_x_14_0_0[14:14]),.I2(un1_x_12_0_0[15:15]),.I3(un1_x_14_0_0[15:15]),.I4(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_axb_11));
defparam un84_sop_0_0_0_11_6_0_axb_11_cZ.INIT=32'h1EE18778;
LUT6 un84_sop_1_6_0_axb_4_cZ(.I0(un1_x_1[7:7]),.I1(un1_x_1[8:8]),.I2(un1_x_2[8:8]),.I3(un1_x_2[9:9]),.I4(un1_x_3[7:7]),.I5(un1_x_3[8:8]),.O(un84_sop_1_6_0_axb_4));
defparam un84_sop_1_6_0_axb_4_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_11_6_0_axb_10_cZ(.I0(un1_x_12_0_0[13:13]),.I1(un1_x_12_0_0[14:14]),.I2(un1_x_13_0_0[14:14]),.I3(un1_x_14_0_0[13:13]),.I4(un1_x_14_0_0[14:14]),.I5(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_axb_10));
defparam un84_sop_0_0_0_11_6_0_axb_10_cZ.INIT=64'h366CC993C993366C;
LUT6 un84_sop_0_0_0_11_6_0_axb_2_cZ(.I0(un1_x_12_0_0[5:5]),.I1(un1_x_12_0_0[6:6]),.I2(un1_x_13_0_0[6:6]),.I3(un1_x_13_0_0[7:7]),.I4(un1_x_14_0_0[5:5]),.I5(un1_x_14_0_0[6:6]),.O(un84_sop_0_0_0_11_6_0_axb_2));
defparam un84_sop_0_0_0_11_6_0_axb_2_cZ.INIT=64'h36C96C93C936936C;
LUT6_L un84_sop_0_0_0_11_0_axb_5_cZ(.I0(un84_sop_0_0_0_0_11_7[4:4]),.I1(un84_sop_0_0_0_0_11_7[5:5]),.I2(un84_sop_0_0_0_0_11_6[4:4]),.I3(un84_sop_0_0_0_0_11_6[5:5]),.I4(un1_x_10_0_0[8:8]),.I5(un1_x_10_0_0[9:9]),.LO(un84_sop_0_0_0_11_0_axb_5));
defparam un84_sop_0_0_0_11_0_axb_5_cZ.INIT=64'h36C96C93C936936C;
LUT6_L un84_sop_0_0_0_11_0_axb_6_cZ(.I0(un84_sop_0_0_0_0_11_7[5:5]),.I1(un84_sop_0_0_0_0_11_7[6:6]),.I2(un84_sop_0_0_0_0_11_6[5:5]),.I3(un84_sop_0_0_0_0_11_6[6:6]),.I4(un1_x_10_0_0[9:9]),.I5(un1_x_10_0_0[10:10]),.LO(un84_sop_0_0_0_11_0_axb_6));
defparam un84_sop_0_0_0_11_0_axb_6_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_11_6_0_axb_6_cZ(.I0(un1_x_12_0_0[9:9]),.I1(un1_x_12_0_0[10:10]),.I2(un1_x_13_0_0[10:10]),.I3(un1_x_13_0_0[11:11]),.I4(un1_x_14_0_0[9:9]),.I5(un1_x_14_0_0[10:10]),.O(un84_sop_0_0_0_11_6_0_axb_6));
defparam un84_sop_0_0_0_11_6_0_axb_6_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_11_6_0_axb_7_cZ(.I0(un1_x_12_0_0[10:10]),.I1(un1_x_12_0_0[11:11]),.I2(un1_x_13_0_0[11:11]),.I3(un1_x_13_0_0[12:12]),.I4(un1_x_14_0_0[10:10]),.I5(un1_x_14_0_0[11:11]),.O(un84_sop_0_0_0_11_6_0_axb_7));
defparam un84_sop_0_0_0_11_6_0_axb_7_cZ.INIT=64'h36C96C93C936936C;
LUT6_L un84_sop_0_0_0_11_0_axb_10_cZ(.I0(un84_sop_0_0_0_0_11_7[9:9]),.I1(un84_sop_0_0_0_0_11_7[14:14]),.I2(un84_sop_0_0_0_0_11_6[9:9]),.I3(un84_sop_0_0_0_0_11_6[10:10]),.I4(un1_x_10_0_0[13:13]),.I5(un1_x_10_0_0[14:14]),.LO(un84_sop_0_0_0_11_0_axb_10));
defparam un84_sop_0_0_0_11_0_axb_10_cZ.INIT=64'h36C96C93C936936C;
LUT4_L un84_sop_0_0_0_11_0_axb_12_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[11:11]),.I2(un84_sop_0_0_0_0_11_6[12:12]),.I3(un1_x_10_0_0[15:15]),.LO(un84_sop_0_0_0_11_0_axb_12));
defparam un84_sop_0_0_0_11_0_axb_12_cZ.INIT=16'h4BD2;
LUT4_L un84_sop_0_0_0_11_0_axb_13_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[14:14]),.I2(un84_sop_0_0_0_0_11_6[12:12]),.I3(un1_x_10_0_0[15:15]),.LO(un84_sop_0_0_0_11_0_axb_13));
defparam un84_sop_0_0_0_11_0_axb_13_cZ.INIT=16'h63C6;
LUT3 un84_sop_0_0_0_11_6_0_axb_13_cZ(.I0(un1_x_12_0_0[15:15]),.I1(un1_x_14_0_0[15:15]),.I2(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_axb_13));
defparam un84_sop_0_0_0_11_6_0_axb_13_cZ.INIT=8'h7E;
LUT6_L un84_sop_0_0_0_11_0_axb_3_cZ(.I0(un84_sop_0_0_0_0_11_7[2:2]),.I1(un84_sop_0_0_0_0_11_7[3:3]),.I2(un84_sop_0_0_0_0_11_6[2:2]),.I3(un1_x_10_s_2_sf),.I4(un1_x_10_axb_3),.I5(un84_sop_0_0_0_0_11_6[3:3]),.LO(un84_sop_0_0_0_11_0_axb_3));
defparam un84_sop_0_0_0_11_0_axb_3_cZ.INIT=64'h366CC993C993366C;
LUT6_L un84_sop_0_0_0_11_0_axb_4_cZ(.I0(un84_sop_0_0_0_0_11_7[3:3]),.I1(un84_sop_0_0_0_0_11_7[4:4]),.I2(un1_x_10_axb_3),.I3(un84_sop_0_0_0_0_11_6[3:3]),.I4(un84_sop_0_0_0_0_11_6[4:4]),.I5(un1_x_10_0_0[8:8]),.LO(un84_sop_0_0_0_11_0_axb_4));
defparam un84_sop_0_0_0_11_0_axb_4_cZ.INIT=64'h366CC993C993366C;
LUT6 un84_sop_0_0_0_6_6_0_axb_5_cZ(.I0(un1_x_7_0[6:6]),.I1(un1_x_7_0[7:7]),.I2(un1_x_8_0[8:8]),.I3(un1_x_8_0[9:9]),.I4(un1_x_9_0[9:9]),.I5(un1_x_9_0[10:10]),.O(un84_sop_0_0_0_6_6_0_axb_5));
defparam un84_sop_0_0_0_6_6_0_axb_5_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_6_6_0_axb_6_cZ(.I0(un1_x_7_0[7:7]),.I1(un1_x_7_0[8:8]),.I2(un1_x_8_0[9:9]),.I3(un1_x_8_0[10:10]),.I4(un1_x_9_0[10:10]),.I5(un1_x_9_0[11:11]),.O(un84_sop_0_0_0_6_6_0_axb_6));
defparam un84_sop_0_0_0_6_6_0_axb_6_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_6_6_0_axb_10_cZ(.I0(un1_x_7_0[11:11]),.I1(un1_x_7_0[12:12]),.I2(un1_x_8_0[13:13]),.I3(un1_x_8_0[14:14]),.I4(un1_x_9_0[14:14]),.I5(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_10));
defparam un84_sop_0_0_0_6_6_0_axb_10_cZ.INIT=64'h36C96C93C936936C;
LUT5 un84_sop_0_0_0_6_6_0_axb_11_cZ(.I0(un1_x_7_0[12:12]),.I1(un1_x_7_0[13:13]),.I2(un1_x_8_0[14:14]),.I3(un1_x_8_0[15:15]),.I4(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_11));
defparam un84_sop_0_0_0_6_6_0_axb_11_cZ.INIT=32'h36C9936C;
LUT6 un84_sop_0_0_0_1_6_8_axb_3_cZ(.I0(un84_sop_0_0_0_10_0[5:5]),.I1(un84_sop_0_0_0_10_0[6:6]),.I2(x_4[1:1]),.I3(x_4[0:0]),.I4(x_4[2:2]),.I5(x_4[3:3]),.O(un84_sop_0_0_0_1_6_8_axb_3));
defparam un84_sop_0_0_0_1_6_8_axb_3_cZ.INIT=64'h3C6969C3C396963C;
LUT6 un84_sop_0_0_0_1_6_8_axb_4_cZ(.I0(un84_sop_0_0_0_10_0[6:6]),.I1(un84_sop_0_0_0_10_0[7:7]),.I2(x_4[1:1]),.I3(x_4[2:2]),.I4(x_4[3:3]),.I5(x_4[4:4]),.O(un84_sop_0_0_0_1_6_8_axb_4));
defparam un84_sop_0_0_0_1_6_8_axb_4_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_1_6_8_axb_5_cZ(.I0(un84_sop_0_0_0_10_0[7:7]),.I1(un84_sop_0_0_0_10_0[8:8]),.I2(x_4[2:2]),.I3(x_4[3:3]),.I4(x_4[4:4]),.I5(x_4[5:5]),.O(un84_sop_0_0_0_1_6_8_axb_5));
defparam un84_sop_0_0_0_1_6_8_axb_5_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_1_6_8_axb_6_cZ(.I0(un84_sop_0_0_0_10_0[8:8]),.I1(un84_sop_0_0_0_10_0[9:9]),.I2(x_4[6:6]),.I3(x_4[3:3]),.I4(x_4[4:4]),.I5(x_4[5:5]),.O(un84_sop_0_0_0_1_6_8_axb_6));
defparam un84_sop_0_0_0_1_6_8_axb_6_cZ.INIT=64'h3C69C39669C3963C;
LUT6 un84_sop_0_0_0_1_6_8_axb_7_cZ(.I0(un84_sop_0_0_0_10_0[9:9]),.I1(un84_sop_0_0_0_10_0[10:10]),.I2(x_4[6:6]),.I3(x_4[4:4]),.I4(x_4[5:5]),.I5(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_7));
defparam un84_sop_0_0_0_1_6_8_axb_7_cZ.INIT=64'h366CC993C993366C;
LUT5 un84_sop_0_0_0_1_6_8_axb_8_cZ(.I0(un84_sop_0_0_0_10_0[11:11]),.I1(un84_sop_0_0_0_10_0[10:10]),.I2(x_4[6:6]),.I3(x_4[5:5]),.I4(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_8));
defparam un84_sop_0_0_0_1_6_8_axb_8_cZ.INIT=32'h5A69965A;
LUT6 un84_sop_0_0_0_11_6_0_axb_5_cZ(.I0(un1_x_12_0_0[8:8]),.I1(un1_x_12_0_0[9:9]),.I2(un1_x_13_0_0[9:9]),.I3(un1_x_13_0_0[10:10]),.I4(un1_x_14_0_0[8:8]),.I5(un1_x_14_0_0[9:9]),.O(un84_sop_0_0_0_11_6_0_axb_5));
defparam un84_sop_0_0_0_11_6_0_axb_5_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_2_cZ(.I0(un1_x_1[5:5]),.I1(un1_x_1[6:6]),.I2(un1_x_2[6:6]),.I3(un1_x_2[7:7]),.I4(un1_x_3[5:5]),.I5(un1_x_3[6:6]),.O(un84_sop_1_6_0_axb_2));
defparam un84_sop_1_6_0_axb_2_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_3_cZ(.I0(un1_x_1[6:6]),.I1(un1_x_1[7:7]),.I2(un1_x_2[7:7]),.I3(un1_x_2[8:8]),.I4(un1_x_3[6:6]),.I5(un1_x_3[7:7]),.O(un84_sop_1_6_0_axb_3));
defparam un84_sop_1_6_0_axb_3_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_5_cZ(.I0(un1_x_1[8:8]),.I1(un1_x_1[9:9]),.I2(un1_x_2[9:9]),.I3(un1_x_2[10:10]),.I4(un1_x_3[8:8]),.I5(un1_x_3[9:9]),.O(un84_sop_1_6_0_axb_5));
defparam un84_sop_1_6_0_axb_5_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_6_cZ(.I0(un1_x_1[9:9]),.I1(un1_x_1[10:10]),.I2(un1_x_2[10:10]),.I3(un1_x_2[11:11]),.I4(un1_x_3[9:9]),.I5(un1_x_3[10:10]),.O(un84_sop_1_6_0_axb_6));
defparam un84_sop_1_6_0_axb_6_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_7_cZ(.I0(un1_x_1[10:10]),.I1(un1_x_1[11:11]),.I2(un1_x_2[11:11]),.I3(un1_x_2[12:12]),.I4(un1_x_3[10:10]),.I5(un1_x_3[11:11]),.O(un84_sop_1_6_0_axb_7));
defparam un84_sop_1_6_0_axb_7_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_8_cZ(.I0(un1_x_1[11:11]),.I1(un1_x_1[12:12]),.I2(un1_x_2[12:12]),.I3(un1_x_2[13:13]),.I4(un1_x_3[11:11]),.I5(un1_x_3[12:12]),.O(un84_sop_1_6_0_axb_8));
defparam un84_sop_1_6_0_axb_8_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_9_cZ(.I0(un1_x_1[12:12]),.I1(un1_x_1[13:13]),.I2(un1_x_2[13:13]),.I3(un1_x_2[14:14]),.I4(un1_x_3[12:12]),.I5(un1_x_3[13:13]),.O(un84_sop_1_6_0_axb_9));
defparam un84_sop_1_6_0_axb_9_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_1_6_0_axb_10_cZ(.I0(un1_x_1[13:13]),.I1(un1_x_1[14:14]),.I2(un1_x_2[14:14]),.I3(un1_x_3[13:13]),.I4(un1_x_3[14:14]),.I5(un1_x_2[15:15]),.O(un84_sop_1_6_0_axb_10));
defparam un84_sop_1_6_0_axb_10_cZ.INIT=64'h366CC993C993366C;
LUT5 un84_sop_1_6_0_axb_11_cZ(.I0(un1_x_1[14:14]),.I1(un1_x_3[14:14]),.I2(un1_x_1[15:15]),.I3(un1_x_3[15:15]),.I4(un1_x_2[15:15]),.O(un84_sop_1_6_0_axb_11));
defparam un84_sop_1_6_0_axb_11_cZ.INIT=32'h1EE18778;
LUT3 un84_sop_1_6_0_axb_13_cZ(.I0(un1_x_1[15:15]),.I1(un1_x_3[15:15]),.I2(un1_x_2[15:15]),.O(un84_sop_1_6_0_axb_13));
defparam un84_sop_1_6_0_axb_13_cZ.INIT=8'h7E;
LUT6_L un84_sop_0_0_0_11_0_axb_7_cZ(.I0(un84_sop_0_0_0_0_11_7[6:6]),.I1(un84_sop_0_0_0_0_11_7[7:7]),.I2(un84_sop_0_0_0_0_11_6[6:6]),.I3(un84_sop_0_0_0_0_11_6[7:7]),.I4(un1_x_10_0_0[10:10]),.I5(un1_x_10_0_0[11:11]),.LO(un84_sop_0_0_0_11_0_axb_7));
defparam un84_sop_0_0_0_11_0_axb_7_cZ.INIT=64'h36C96C93C936936C;
LUT6_L un84_sop_0_0_0_11_0_axb_8_cZ(.I0(un84_sop_0_0_0_0_11_7[7:7]),.I1(un84_sop_0_0_0_0_11_7[8:8]),.I2(un84_sop_0_0_0_0_11_6[7:7]),.I3(un84_sop_0_0_0_0_11_6[8:8]),.I4(un1_x_10_0_0[11:11]),.I5(un1_x_10_0_0[12:12]),.LO(un84_sop_0_0_0_11_0_axb_8));
defparam un84_sop_0_0_0_11_0_axb_8_cZ.INIT=64'h36C96C93C936936C;
LUT6_L un84_sop_0_0_0_11_0_axb_9_cZ(.I0(un84_sop_0_0_0_0_11_7[8:8]),.I1(un84_sop_0_0_0_0_11_7[9:9]),.I2(un84_sop_0_0_0_0_11_6[8:8]),.I3(un84_sop_0_0_0_0_11_6[9:9]),.I4(un1_x_10_0_0[12:12]),.I5(un1_x_10_0_0[13:13]),.LO(un84_sop_0_0_0_11_0_axb_9));
defparam un84_sop_0_0_0_11_0_axb_9_cZ.INIT=64'h36C96C93C936936C;
LUT4_L un84_sop_0_0_0_11_0_axb_1_cZ(.I0(x_8[1:1]),.I1(x_8[0:0]),.I2(un84_sop_0_0_0_0_11_7[1:1]),.I3(un84_sop_0_0_0_0_11_6[1:1]),.LO(un84_sop_0_0_0_11_0_axb_1));
defparam un84_sop_0_0_0_11_0_axb_1_cZ.INIT=16'h6996;
LUT5_L un84_sop_0_0_0_11_0_axb_11_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[10:10]),.I2(un84_sop_0_0_0_0_11_6[11:11]),.I3(un1_x_10_0_0[14:14]),.I4(un1_x_10_0_0[15:15]),.LO(un84_sop_0_0_0_11_0_axb_11));
defparam un84_sop_0_0_0_11_0_axb_11_cZ.INIT=32'h4B2DB4D2;
LUT3 un84_sop_0_0_0_1_6_axb_0(.I0(un84_sop_0_0_0_10_0[0:0]),.I1(un1_x_6_0[1:1]),.I2(un84_sop_0_0_0_1_6_6[0:0]),.O(un84_sop_0_0_0_5_0[0:0]));
defparam un84_sop_0_0_0_1_6_axb_0.INIT=8'h96;
LUT6 un84_sop_1_4_axb_4_cZ(.I0(x_0[3:3]),.I1(x_0[2:2]),.I2(x_0[1:1]),.I3(x_0[0:0]),.I4(x_0[4:4]),.I5(un84_sop_1_7[4:4]),.O(un84_sop_1_4_axb_4));
defparam un84_sop_1_4_axb_4_cZ.INIT=64'hFFFE00010001FFFE;
LUT6 un84_sop_0_0_0_6_6_0_axb_2_cZ(.I0(un1_x_7_0[3:3]),.I1(un1_x_7_0[4:4]),.I2(un1_x_8_0[5:5]),.I3(un1_x_8_0[6:6]),.I4(un1_x_9_0[6:6]),.I5(un1_x_9_0[7:7]),.O(un84_sop_0_0_0_6_6_0_axb_2));
defparam un84_sop_0_0_0_6_6_0_axb_2_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_6_6_0_axb_3_cZ(.I0(un1_x_7_0[4:4]),.I1(un1_x_7_0[5:5]),.I2(un1_x_8_0[6:6]),.I3(un1_x_8_0[7:7]),.I4(un1_x_9_0[7:7]),.I5(un1_x_9_0[8:8]),.O(un84_sop_0_0_0_6_6_0_axb_3));
defparam un84_sop_0_0_0_6_6_0_axb_3_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_6_6_0_axb_4_cZ(.I0(un1_x_7_0[5:5]),.I1(un1_x_7_0[6:6]),.I2(un1_x_8_0[7:7]),.I3(un1_x_8_0[8:8]),.I4(un1_x_9_0[8:8]),.I5(un1_x_9_0[9:9]),.O(un84_sop_0_0_0_6_6_0_axb_4));
defparam un84_sop_0_0_0_6_6_0_axb_4_cZ.INIT=64'h36C96C93C936936C;
LUT6_L un84_sop_0_0_0_11_6_0_s_2_RNIGK751(.I0(x_8[1:1]),.I1(x_8[0:0]),.I2(un84_sop_0_0_0_0_11_7[1:1]),.I3(un84_sop_0_0_0_0_11_7[2:2]),.I4(un84_sop_0_0_0_0_11_6[2:2]),.I5(un1_x_10_s_2_sf),.LO(un84_sop_0_0_0_11_0_axb_2));
defparam un84_sop_0_0_0_11_6_0_s_2_RNIGK751.INIT=64'h9F60609F609F9F60;
LUT6 un84_sop_0_0_0_6_6_0_axb_7_cZ(.I0(un1_x_7_0[8:8]),.I1(un1_x_7_0[9:9]),.I2(un1_x_8_0[10:10]),.I3(un1_x_8_0[11:11]),.I4(un1_x_9_0[11:11]),.I5(un1_x_9_0[12:12]),.O(un84_sop_0_0_0_6_6_0_axb_7));
defparam un84_sop_0_0_0_6_6_0_axb_7_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_6_6_0_axb_8_cZ(.I0(un1_x_7_0[9:9]),.I1(un1_x_7_0[10:10]),.I2(un1_x_8_0[11:11]),.I3(un1_x_8_0[12:12]),.I4(un1_x_9_0[12:12]),.I5(un1_x_9_0[13:13]),.O(un84_sop_0_0_0_6_6_0_axb_8));
defparam un84_sop_0_0_0_6_6_0_axb_8_cZ.INIT=64'h36C96C93C936936C;
LUT6 un84_sop_0_0_0_6_6_0_axb_9_cZ(.I0(un1_x_7_0[10:10]),.I1(un1_x_7_0[11:11]),.I2(un1_x_8_0[12:12]),.I3(un1_x_8_0[13:13]),.I4(un1_x_9_0[13:13]),.I5(un1_x_9_0[14:14]),.O(un84_sop_0_0_0_6_6_0_axb_9));
defparam un84_sop_0_0_0_6_6_0_axb_9_cZ.INIT=64'h36C96C93C936936C;
LUT4 un1_x_10_axb_11_cZ(.I0(x_8[6:6]),.I1(x_8[7:7]),.I2(x_8[5:5]),.I3(un1_x_10_5_c5),.O(un1_x_10_axb_11));
defparam un1_x_10_axb_11_cZ.INIT=16'hFEFF;
LUT3_L un84_sop_0_0_0_11_0_axb_14_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[14:14]),.I2(un1_x_10_0_0[15:15]),.LO(un84_sop_0_0_0_11_0_axb_14));
defparam un84_sop_0_0_0_11_0_axb_14_cZ.INIT=8'h7E;
LUT3 un84_sop_0_0_0_6_6_0_axb_14_cZ(.I0(un1_x_7_0[15:15]),.I1(un1_x_8_0[15:15]),.I2(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_axb_14));
defparam un84_sop_0_0_0_6_6_0_axb_14_cZ.INIT=8'h7E;
MUXCY_L un84_sop_0_0_0_11_0_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(un84_sop_0_0_0_0_11_7_axb_0_ci),.LO(un84_sop_0_0_0_11_0_cry_0_cy));
LUT1 un1_x_10_4_s_2_RNI13H1(.I0(un1_x_10_4[2:2]),.O(un1_x_10_s_2_sf));
defparam un1_x_10_4_s_2_RNI13H1.INIT=2'h2;
LUT2_L un84_sop_0_0_0_1_axb_9_cZ(.I0(un1_x_16_0_0_0[14:14]),.I1(un1_x_15_0_0_0[14:14]),.LO(un84_sop_0_0_0_1_axb_9));
defparam un84_sop_0_0_0_1_axb_9_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_8_cZ(.I0(un1_x_16_0_0_0[14:14]),.I1(un1_x_15_0_0_0[14:14]),.LO(un84_sop_0_0_0_1_axb_8));
defparam un84_sop_0_0_0_1_axb_8_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_7_cZ(.I0(un1_x_16_0_0_0[13:13]),.I1(un1_x_15_0_0_0[13:13]),.LO(un84_sop_0_0_0_1_axb_7));
defparam un84_sop_0_0_0_1_axb_7_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_6_cZ(.I0(un1_x_16_0_0_0[12:12]),.I1(un1_x_15_0_0_0[12:12]),.LO(un84_sop_0_0_0_1_axb_6));
defparam un84_sop_0_0_0_1_axb_6_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_5_cZ(.I0(un1_x_16_0_0_0[11:11]),.I1(un1_x_15_0_0_0[11:11]),.LO(un84_sop_0_0_0_1_axb_5));
defparam un84_sop_0_0_0_1_axb_5_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_4_cZ(.I0(un1_x_16_0_0_0[10:10]),.I1(un1_x_15_0_0_0[10:10]),.LO(un84_sop_0_0_0_1_axb_4));
defparam un84_sop_0_0_0_1_axb_4_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_3_cZ(.I0(un1_x_16_0_0_0[9:9]),.I1(un1_x_15_0_0_0[9:9]),.LO(un84_sop_0_0_0_1_axb_3));
defparam un84_sop_0_0_0_1_axb_3_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_2_cZ(.I0(un1_x_16_0_0_0[8:8]),.I1(un1_x_15_0_0_0[8:8]),.LO(un84_sop_0_0_0_1_axb_2));
defparam un84_sop_0_0_0_1_axb_2_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_axb_1_cZ(.I0(un1_x_16_0_0_0[7:7]),.I1(un1_x_15_0_0_0[7:7]),.LO(un84_sop_0_0_0_1_axb_1));
defparam un84_sop_0_0_0_1_axb_1_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_axb_0(.I0(x_12[0:0]),.I1(x_13[0:0]),.O(un84_sop_0_0_0_0_1[0:0]));
defparam un84_sop_0_0_0_1_axb_0.INIT=4'h6;
LUT1 un1_x_16_0_axb_8_cZ(.I0(x_13[7:7]),.O(un1_x_16_0_axb_8));
defparam un1_x_16_0_axb_8_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_8_cZ(.I0(x_8[7:7]),.LO(un1_x_11_0_axb_8));
defparam un1_x_11_0_axb_8_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_7_cZ(.I0(x_8[7:7]),.LO(un1_x_11_0_axb_7));
defparam un1_x_11_0_axb_7_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_6_cZ(.I0(x_8[6:6]),.LO(un1_x_11_0_axb_6));
defparam un1_x_11_0_axb_6_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_5_cZ(.I0(x_8[5:5]),.LO(un1_x_11_0_axb_5));
defparam un1_x_11_0_axb_5_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_4_cZ(.I0(x_8[4:4]),.LO(un1_x_11_0_axb_4));
defparam un1_x_11_0_axb_4_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_3_cZ(.I0(x_8[3:3]),.LO(un1_x_11_0_axb_3));
defparam un1_x_11_0_axb_3_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_2_cZ(.I0(x_8[2:2]),.LO(un1_x_11_0_axb_2));
defparam un1_x_11_0_axb_2_cZ.INIT=2'h1;
LUT1_L un1_x_11_0_axb_1_cZ(.I0(x_8[1:1]),.LO(un1_x_11_0_axb_1));
defparam un1_x_11_0_axb_1_cZ.INIT=2'h1;
LUT1 un1_x_15_0_axb_8_cZ(.I0(x_12[7:7]),.O(un1_x_15_0_axb_8));
defparam un1_x_15_0_axb_8_cZ.INIT=2'h1;
LUT1 un1_x_10_4_axb_10(.I0(x_8[7:7]),.O(un1_x_10_4[10:10]));
defparam un1_x_10_4_axb_10.INIT=2'h2;
LUT1 un1_x_10_4_axb_9(.I0(x_8[7:7]),.O(un1_x_10_4[9:9]));
defparam un1_x_10_4_axb_9.INIT=2'h2;
LUT2_L un84_sop_1_axb_14_cZ(.I0(un84_sop_1_6[14:14]),.I1(un84_sop_1_4[14:14]),.LO(un84_sop_1_axb_14));
defparam un84_sop_1_axb_14_cZ.INIT=4'h6;
LUT2_L un84_sop_1_axb_13_cZ(.I0(un84_sop_1_6[14:14]),.I1(un84_sop_1_4[13:13]),.LO(un84_sop_1_axb_13));
defparam un84_sop_1_axb_13_cZ.INIT=4'h6;
LUT2_L un84_sop_1_axb_12_cZ(.I0(un84_sop_1_6[12:12]),.I1(un84_sop_1_4[12:12]),.LO(un84_sop_1_axb_12));
defparam un84_sop_1_axb_12_cZ.INIT=4'h6;
LUT2_L un84_sop_1_axb_11_cZ(.I0(un84_sop_1_6[11:11]),.I1(un84_sop_1_4[11:11]),.LO(un84_sop_1_axb_11));
defparam un84_sop_1_axb_11_cZ.INIT=4'h6;
LUT2_L un84_sop_1_axb_10_cZ(.I0(un84_sop_1_6[10:10]),.I1(un84_sop_1_4[10:10]),.LO(un84_sop_1_axb_10));
defparam un84_sop_1_axb_10_cZ.INIT=4'h6;
LUT2_L un84_sop_1_axb_9_cZ(.I0(un84_sop_1_6[9:9]),.I1(un84_sop_1_4[9:9]),.LO(un84_sop_1_axb_9));
defparam un84_sop_1_axb_9_cZ.INIT=4'h6;
LUT2_L un84_sop_1_axb_8_cZ(.I0(un84_sop_1_6[8:8]),.I1(un84_sop_1_4[8:8]),.LO(un84_sop_1_axb_8));
defparam un84_sop_1_axb_8_cZ.INIT=4'h6;
LUT2_L un84_sop_1_axb_7_cZ(.I0(un84_sop_1_6[7:7]),.I1(un84_sop_1_4[7:7]),.LO(un84_sop_1_axb_7));
defparam un84_sop_1_axb_7_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_0_11_7_axb_10_cZ(.I0(un1_x_11_0_0[14:14]),.I1(un84_sop_0_0_0_0_0[9:9]),.O(un84_sop_0_0_0_0_11_7_axb_10));
defparam un84_sop_0_0_0_0_11_7_axb_10_cZ.INIT=4'h6;
LUT2 un84_sop_1_7_axb_14_cZ(.I0(un84_sop_0_0_0_0_5[14:14]),.I1(un1_x_4[15:15]),.O(un84_sop_1_7_axb_14));
defparam un84_sop_1_7_axb_14_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_14_cZ(.I0(un84_sop_0_0_0_1_6_6[14:14]),.I1(un84_sop_0_0_0_1_6_4[14:14]),.LO(un84_sop_0_0_0_1_6_axb_14));
defparam un84_sop_0_0_0_1_6_axb_14_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_13_cZ(.I0(un84_sop_0_0_0_1_6_6[13:13]),.I1(un84_sop_0_0_0_1_6_4[13:13]),.LO(un84_sop_0_0_0_1_6_axb_13));
defparam un84_sop_0_0_0_1_6_axb_13_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_12_cZ(.I0(un84_sop_0_0_0_1_6_6[12:12]),.I1(un84_sop_0_0_0_1_6_4[12:12]),.LO(un84_sop_0_0_0_1_6_axb_12));
defparam un84_sop_0_0_0_1_6_axb_12_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_11_cZ(.I0(un84_sop_0_0_0_1_6_6[11:11]),.I1(un84_sop_0_0_0_1_6_4[11:11]),.LO(un84_sop_0_0_0_1_6_axb_11));
defparam un84_sop_0_0_0_1_6_axb_11_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_10_cZ(.I0(un84_sop_0_0_0_1_6_6[10:10]),.I1(un84_sop_0_0_0_1_6_4[10:10]),.LO(un84_sop_0_0_0_1_6_axb_10));
defparam un84_sop_0_0_0_1_6_axb_10_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_9_cZ(.I0(un84_sop_0_0_0_1_6_6[9:9]),.I1(un84_sop_0_0_0_1_6_4[9:9]),.LO(un84_sop_0_0_0_1_6_axb_9));
defparam un84_sop_0_0_0_1_6_axb_9_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_8_cZ(.I0(un84_sop_0_0_0_1_6_6[8:8]),.I1(un84_sop_0_0_0_1_6_4[8:8]),.LO(un84_sop_0_0_0_1_6_axb_8));
defparam un84_sop_0_0_0_1_6_axb_8_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_7_cZ(.I0(un84_sop_0_0_0_1_6_6[7:7]),.I1(un84_sop_0_0_0_1_6_4[7:7]),.LO(un84_sop_0_0_0_1_6_axb_7));
defparam un84_sop_0_0_0_1_6_axb_7_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_6_cZ(.I0(un84_sop_0_0_0_1_6_6[6:6]),.I1(un84_sop_0_0_0_1_6_4[6:6]),.LO(un84_sop_0_0_0_1_6_axb_6));
defparam un84_sop_0_0_0_1_6_axb_6_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_5_cZ(.I0(un84_sop_0_0_0_1_6_6[5:5]),.I1(un84_sop_0_0_0_1_6_4[5:5]),.LO(un84_sop_0_0_0_1_6_axb_5));
defparam un84_sop_0_0_0_1_6_axb_5_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_4_cZ(.I0(un84_sop_0_0_0_1_6_6[4:4]),.I1(un84_sop_0_0_0_1_6_4[4:4]),.LO(un84_sop_0_0_0_1_6_axb_4));
defparam un84_sop_0_0_0_1_6_axb_4_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_3_cZ(.I0(un84_sop_0_0_0_1_6_4[3:3]),.I1(un84_sop_0_0_0_1_6_6[3:3]),.LO(un84_sop_0_0_0_1_6_axb_3));
defparam un84_sop_0_0_0_1_6_axb_3_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_2_cZ(.I0(un84_sop_0_0_0_1_6_4[2:2]),.I1(un84_sop_0_0_0_1_6_6[2:2]),.LO(un84_sop_0_0_0_1_6_axb_2));
defparam un84_sop_0_0_0_1_6_axb_2_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_1_6_axb_1_cZ(.I0(un84_sop_0_0_0_1_6_4[1:1]),.I1(un84_sop_0_0_0_1_6_6[1:1]),.LO(un84_sop_0_0_0_1_6_axb_1));
defparam un84_sop_0_0_0_1_6_axb_1_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_4_axb_14_cZ(.I0(un1_x_6_0[15:15]),.I1(un84_sop_0_0_0_1_6_8[14:14]),.O(un84_sop_0_0_0_1_6_4_axb_14));
defparam un84_sop_0_0_0_1_6_4_axb_14_cZ.INIT=4'h6;
LUT2 un1_x_10_axb_3_cZ(.I0(x_8[0:0]),.I1(un1_x_10_4[3:3]),.O(un1_x_10_axb_3));
defparam un1_x_10_axb_3_cZ.INIT=4'h6;
LUT2 un84_sop_0_0_0_1_6_8_axb_11_cZ(.I0(un84_sop_0_0_0_10_0[14:14]),.I1(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_axb_11));
defparam un84_sop_0_0_0_1_6_8_axb_11_cZ.INIT=4'h6;
LUT2_L un84_sop_0_0_0_11_0_axb_0_cZ(.I0(x_8[0:0]),.I1(un84_sop_0_0_0_0_11_6[0:0]),.LO(un84_sop_0_0_0_11_0_axb_0));
defparam un84_sop_0_0_0_11_0_axb_0_cZ.INIT=4'h6;
LUT4 un1_x_0_0_ac0_5(.I0(x_0[3:3]),.I1(x_0[2:2]),.I2(x_0[1:1]),.I3(x_0[0:0]),.O(un1_x_0_0_c4));
defparam un1_x_0_0_ac0_5.INIT=16'h0001;
LUT3 un84_sop_0_0_0_11_6_0_o5_11_cZ(.I0(un1_x_12_0_0[15:15]),.I1(un1_x_14_0_0[15:15]),.I2(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_o5_11));
defparam un84_sop_0_0_0_11_6_0_o5_11_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_10_cZ(.I0(un1_x_12_0_0[14:14]),.I1(un1_x_14_0_0[14:14]),.I2(un1_x_13_0_0[15:15]),.O(un84_sop_0_0_0_11_6_0_o5_10));
defparam un84_sop_0_0_0_11_6_0_o5_10_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_9_cZ(.I0(un1_x_12_0_0[13:13]),.I1(un1_x_13_0_0[14:14]),.I2(un1_x_14_0_0[13:13]),.O(un84_sop_0_0_0_11_6_0_o5_9));
defparam un84_sop_0_0_0_11_6_0_o5_9_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_8_cZ(.I0(un1_x_12_0_0[12:12]),.I1(un1_x_13_0_0[13:13]),.I2(un1_x_14_0_0[12:12]),.O(un84_sop_0_0_0_11_6_0_o5_8));
defparam un84_sop_0_0_0_11_6_0_o5_8_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_7_cZ(.I0(un1_x_12_0_0[11:11]),.I1(un1_x_13_0_0[12:12]),.I2(un1_x_14_0_0[11:11]),.O(un84_sop_0_0_0_11_6_0_o5_7));
defparam un84_sop_0_0_0_11_6_0_o5_7_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_6_cZ(.I0(un1_x_12_0_0[10:10]),.I1(un1_x_13_0_0[11:11]),.I2(un1_x_14_0_0[10:10]),.O(un84_sop_0_0_0_11_6_0_o5_6));
defparam un84_sop_0_0_0_11_6_0_o5_6_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_5_cZ(.I0(un1_x_12_0_0[9:9]),.I1(un1_x_13_0_0[10:10]),.I2(un1_x_14_0_0[9:9]),.O(un84_sop_0_0_0_11_6_0_o5_5));
defparam un84_sop_0_0_0_11_6_0_o5_5_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_4_cZ(.I0(un1_x_12_0_0[8:8]),.I1(un1_x_13_0_0[9:9]),.I2(un1_x_14_0_0[8:8]),.O(un84_sop_0_0_0_11_6_0_o5_4));
defparam un84_sop_0_0_0_11_6_0_o5_4_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_3_cZ(.I0(un1_x_12_0_0[7:7]),.I1(un1_x_13_0_0[8:8]),.I2(un1_x_14_0_0[7:7]),.O(un84_sop_0_0_0_11_6_0_o5_3));
defparam un84_sop_0_0_0_11_6_0_o5_3_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_6_0_o5_2_cZ(.I0(un1_x_12_0_0[6:6]),.I1(un1_x_13_0_0[7:7]),.I2(un1_x_14_0_0[6:6]),.O(un84_sop_0_0_0_11_6_0_o5_2));
defparam un84_sop_0_0_0_11_6_0_o5_2_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_12_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[12:12]),.I2(un1_x_10_0_0[15:15]),.O(un84_sop_0_0_0_11_0_o5_12));
defparam un84_sop_0_0_0_11_0_o5_12_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_11_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[11:11]),.I2(un1_x_10_0_0[15:15]),.O(un84_sop_0_0_0_11_0_o5_11));
defparam un84_sop_0_0_0_11_0_o5_11_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_10_cZ(.I0(un84_sop_0_0_0_0_11_7[14:14]),.I1(un84_sop_0_0_0_0_11_6[10:10]),.I2(un1_x_10_0_0[14:14]),.O(un84_sop_0_0_0_11_0_o5_10));
defparam un84_sop_0_0_0_11_0_o5_10_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_9_cZ(.I0(un84_sop_0_0_0_0_11_7[9:9]),.I1(un84_sop_0_0_0_0_11_6[9:9]),.I2(un1_x_10_0_0[13:13]),.O(un84_sop_0_0_0_11_0_o5_9));
defparam un84_sop_0_0_0_11_0_o5_9_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_8_cZ(.I0(un84_sop_0_0_0_0_11_7[8:8]),.I1(un84_sop_0_0_0_0_11_6[8:8]),.I2(un1_x_10_0_0[12:12]),.O(un84_sop_0_0_0_11_0_o5_8));
defparam un84_sop_0_0_0_11_0_o5_8_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_7_cZ(.I0(un84_sop_0_0_0_0_11_7[7:7]),.I1(un84_sop_0_0_0_0_11_6[7:7]),.I2(un1_x_10_0_0[11:11]),.O(un84_sop_0_0_0_11_0_o5_7));
defparam un84_sop_0_0_0_11_0_o5_7_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_6_cZ(.I0(un84_sop_0_0_0_0_11_7[6:6]),.I1(un84_sop_0_0_0_0_11_6[6:6]),.I2(un1_x_10_0_0[10:10]),.O(un84_sop_0_0_0_11_0_o5_6));
defparam un84_sop_0_0_0_11_0_o5_6_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_5_cZ(.I0(un84_sop_0_0_0_0_11_7[5:5]),.I1(un84_sop_0_0_0_0_11_6[5:5]),.I2(un1_x_10_0_0[9:9]),.O(un84_sop_0_0_0_11_0_o5_5));
defparam un84_sop_0_0_0_11_0_o5_5_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_4_cZ(.I0(un84_sop_0_0_0_0_11_7[4:4]),.I1(un84_sop_0_0_0_0_11_6[4:4]),.I2(un1_x_10_0_0[8:8]),.O(un84_sop_0_0_0_11_0_o5_4));
defparam un84_sop_0_0_0_11_0_o5_4_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_3_cZ(.I0(un84_sop_0_0_0_0_11_7[3:3]),.I1(un1_x_10_axb_3),.I2(un84_sop_0_0_0_0_11_6[3:3]),.O(un84_sop_0_0_0_11_0_o5_3));
defparam un84_sop_0_0_0_11_0_o5_3_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_11_0_o5_2_cZ(.I0(un84_sop_0_0_0_0_11_7[2:2]),.I1(un84_sop_0_0_0_0_11_6[2:2]),.I2(un1_x_10_s_2_sf),.O(un84_sop_0_0_0_11_0_o5_2));
defparam un84_sop_0_0_0_11_0_o5_2_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_12_cZ(.I0(un1_x_7_0[14:14]),.I1(un1_x_8_0[15:15]),.I2(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_o5_12));
defparam un84_sop_0_0_0_6_6_0_o5_12_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_11_cZ(.I0(un1_x_7_0[13:13]),.I1(un1_x_8_0[15:15]),.I2(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_o5_11));
defparam un84_sop_0_0_0_6_6_0_o5_11_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_10_cZ(.I0(un1_x_7_0[12:12]),.I1(un1_x_8_0[14:14]),.I2(un1_x_9_0[15:15]),.O(un84_sop_0_0_0_6_6_0_o5_10));
defparam un84_sop_0_0_0_6_6_0_o5_10_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_9_cZ(.I0(un1_x_7_0[11:11]),.I1(un1_x_8_0[13:13]),.I2(un1_x_9_0[14:14]),.O(un84_sop_0_0_0_6_6_0_o5_9));
defparam un84_sop_0_0_0_6_6_0_o5_9_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_8_cZ(.I0(un1_x_7_0[10:10]),.I1(un1_x_8_0[12:12]),.I2(un1_x_9_0[13:13]),.O(un84_sop_0_0_0_6_6_0_o5_8));
defparam un84_sop_0_0_0_6_6_0_o5_8_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_7_cZ(.I0(un1_x_7_0[9:9]),.I1(un1_x_8_0[11:11]),.I2(un1_x_9_0[12:12]),.O(un84_sop_0_0_0_6_6_0_o5_7));
defparam un84_sop_0_0_0_6_6_0_o5_7_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_6_cZ(.I0(un1_x_7_0[8:8]),.I1(un1_x_8_0[10:10]),.I2(un1_x_9_0[11:11]),.O(un84_sop_0_0_0_6_6_0_o5_6));
defparam un84_sop_0_0_0_6_6_0_o5_6_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_5_cZ(.I0(un1_x_7_0[7:7]),.I1(un1_x_8_0[9:9]),.I2(un1_x_9_0[10:10]),.O(un84_sop_0_0_0_6_6_0_o5_5));
defparam un84_sop_0_0_0_6_6_0_o5_5_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_4_cZ(.I0(un1_x_7_0[6:6]),.I1(un1_x_8_0[8:8]),.I2(un1_x_9_0[9:9]),.O(un84_sop_0_0_0_6_6_0_o5_4));
defparam un84_sop_0_0_0_6_6_0_o5_4_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_3_cZ(.I0(un1_x_7_0[5:5]),.I1(un1_x_8_0[7:7]),.I2(un1_x_9_0[8:8]),.O(un84_sop_0_0_0_6_6_0_o5_3));
defparam un84_sop_0_0_0_6_6_0_o5_3_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_o5_2_cZ(.I0(un1_x_7_0[4:4]),.I1(un1_x_8_0[6:6]),.I2(un1_x_9_0[7:7]),.O(un84_sop_0_0_0_6_6_0_o5_2));
defparam un84_sop_0_0_0_6_6_0_o5_2_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_1_6_8_o5_7_cZ(.I0(un84_sop_0_0_0_10_0[10:10]),.I1(x_4[5:5]),.I2(x_4[7:7]),.O(un84_sop_0_0_0_1_6_8_o5_7));
defparam un84_sop_0_0_0_1_6_8_o5_7_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_1_6_8_o5_6_cZ(.I0(un84_sop_0_0_0_10_0[9:9]),.I1(x_4[6:6]),.I2(x_4[4:4]),.O(un84_sop_0_0_0_1_6_8_o5_6));
defparam un84_sop_0_0_0_1_6_8_o5_6_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_1_6_8_o5_5_cZ(.I0(un84_sop_0_0_0_10_0[8:8]),.I1(x_4[3:3]),.I2(x_4[5:5]),.O(un84_sop_0_0_0_1_6_8_o5_5));
defparam un84_sop_0_0_0_1_6_8_o5_5_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_1_6_8_o5_4_cZ(.I0(un84_sop_0_0_0_10_0[7:7]),.I1(x_4[2:2]),.I2(x_4[4:4]),.O(un84_sop_0_0_0_1_6_8_o5_4));
defparam un84_sop_0_0_0_1_6_8_o5_4_cZ.INIT=8'hE8;
LUT3 un84_sop_0_0_0_1_6_8_o5_3_cZ(.I0(un84_sop_0_0_0_10_0[6:6]),.I1(x_4[1:1]),.I2(x_4[3:3]),.O(un84_sop_0_0_0_1_6_8_o5_3));
defparam un84_sop_0_0_0_1_6_8_o5_3_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_11_cZ(.I0(un1_x_1[15:15]),.I1(un1_x_3[15:15]),.I2(un1_x_2[15:15]),.O(un84_sop_1_6_0_o5_11));
defparam un84_sop_1_6_0_o5_11_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_10_cZ(.I0(un1_x_1[14:14]),.I1(un1_x_3[14:14]),.I2(un1_x_2[15:15]),.O(un84_sop_1_6_0_o5_10));
defparam un84_sop_1_6_0_o5_10_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_9_cZ(.I0(un1_x_1[13:13]),.I1(un1_x_2[14:14]),.I2(un1_x_3[13:13]),.O(un84_sop_1_6_0_o5_9));
defparam un84_sop_1_6_0_o5_9_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_8_cZ(.I0(un1_x_1[12:12]),.I1(un1_x_2[13:13]),.I2(un1_x_3[12:12]),.O(un84_sop_1_6_0_o5_8));
defparam un84_sop_1_6_0_o5_8_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_7_cZ(.I0(un1_x_1[11:11]),.I1(un1_x_2[12:12]),.I2(un1_x_3[11:11]),.O(un84_sop_1_6_0_o5_7));
defparam un84_sop_1_6_0_o5_7_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_6_cZ(.I0(un1_x_1[10:10]),.I1(un1_x_2[11:11]),.I2(un1_x_3[10:10]),.O(un84_sop_1_6_0_o5_6));
defparam un84_sop_1_6_0_o5_6_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_5_cZ(.I0(un1_x_1[9:9]),.I1(un1_x_2[10:10]),.I2(un1_x_3[9:9]),.O(un84_sop_1_6_0_o5_5));
defparam un84_sop_1_6_0_o5_5_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_4_cZ(.I0(un1_x_1[8:8]),.I1(un1_x_2[9:9]),.I2(un1_x_3[8:8]),.O(un84_sop_1_6_0_o5_4));
defparam un84_sop_1_6_0_o5_4_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_3_cZ(.I0(un1_x_1[7:7]),.I1(un1_x_2[8:8]),.I2(un1_x_3[7:7]),.O(un84_sop_1_6_0_o5_3));
defparam un84_sop_1_6_0_o5_3_cZ.INIT=8'hE8;
LUT3 un84_sop_1_6_0_o5_2_cZ(.I0(un1_x_1[6:6]),.I1(un1_x_2[7:7]),.I2(un1_x_3[6:6]),.O(un84_sop_1_6_0_o5_2));
defparam un84_sop_1_6_0_o5_2_cZ.INIT=8'hE8;
LUT5 un84_sop_1_4_axb_3_cZ(.I0(x_0[3:3]),.I1(x_0[2:2]),.I2(x_0[1:1]),.I3(x_0[0:0]),.I4(un84_sop_1_7[3:3]),.O(un84_sop_1_4_axb_3));
defparam un84_sop_1_4_axb_3_cZ.INIT=32'hAAA95556;
LUT5 un1_x_10_5_ac0_7(.I0(x_8[4:4]),.I1(x_8[3:3]),.I2(x_8[2:2]),.I3(x_8[1:1]),.I4(x_8[0:0]),.O(un1_x_10_5_c5));
defparam un1_x_10_5_ac0_7.INIT=32'h00000001;
LUT5 un1_x_10_axb_6_cZ(.I0(x_8[3:3]),.I1(x_8[2:2]),.I2(x_8[1:1]),.I3(x_8[0:0]),.I4(un1_x_10_4[6:6]),.O(un1_x_10_axb_6));
defparam un1_x_10_axb_6_cZ.INIT=32'hAAA95556;
LUT6 un1_x_10_axb_7_cZ(.I0(x_8[4:4]),.I1(x_8[3:3]),.I2(x_8[2:2]),.I3(x_8[1:1]),.I4(x_8[0:0]),.I5(un1_x_10_4[7:7]),.O(un1_x_10_axb_7));
defparam un1_x_10_axb_7_cZ.INIT=64'hAAAAAAA955555556;
LUT5 un84_sop_1_4_axb_6_cZ(.I0(x_0[6:6]),.I1(x_0[5:5]),.I2(x_0[4:4]),.I3(un1_x_0_0_c4),.I4(un84_sop_1_7[6:6]),.O(un84_sop_1_4_axb_6));
defparam un84_sop_1_4_axb_6_cZ.INIT=32'hA9AA5655;
LUT6 un84_sop_1_4_axb_7_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[7:7]),.O(un84_sop_1_4_axb_7));
defparam un84_sop_1_4_axb_7_cZ.INIT=64'hAAA9AAAA55565555;
LUT6 un84_sop_1_4_axb_14_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[14:14]),.O(un84_sop_1_4_axb_14));
defparam un84_sop_1_4_axb_14_cZ.INIT=64'hAAABAAAA55545555;
LUT6 un84_sop_1_4_axb_13_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[13:13]),.O(un84_sop_1_4_axb_13));
defparam un84_sop_1_4_axb_13_cZ.INIT=64'hAAABAAAA55545555;
LUT6 un84_sop_1_4_axb_12_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[12:12]),.O(un84_sop_1_4_axb_12));
defparam un84_sop_1_4_axb_12_cZ.INIT=64'hAAABAAAA55545555;
LUT6 un84_sop_1_4_axb_11_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[11:11]),.O(un84_sop_1_4_axb_11));
defparam un84_sop_1_4_axb_11_cZ.INIT=64'hAAABAAAA55545555;
LUT6 un84_sop_1_4_axb_10_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[10:10]),.O(un84_sop_1_4_axb_10));
defparam un84_sop_1_4_axb_10_cZ.INIT=64'hAAABAAAA55545555;
LUT6 un84_sop_1_4_axb_9_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[9:9]),.O(un84_sop_1_4_axb_9));
defparam un84_sop_1_4_axb_9_cZ.INIT=64'hAAABAAAA55545555;
LUT6 un84_sop_1_4_axb_8_cZ(.I0(x_0[7:7]),.I1(x_0[6:6]),.I2(x_0[5:5]),.I3(x_0[4:4]),.I4(un1_x_0_0_c4),.I5(un84_sop_1_7[8:8]),.O(un84_sop_1_4_axb_8));
defparam un84_sop_1_4_axb_8_cZ.INIT=64'hAAABAAAA55545555;
LUT2 x_16_pipe_0_0_0_RNI0KBH(.I0(un84_sop_0_0_0_0_5[0:0]),.I1(un1_x_4[2:2]),.O(un84_sop_1_7[0:0]));
defparam x_16_pipe_0_0_0_RNI0KBH.INIT=4'h6;
XORCY un84_sop_0_0_0_1_s_9(.LI(un84_sop_0_0_0_1_axb_9),.CI(un84_sop_0_0_0_1_cry_8),.O(un84_sop_0_0_0_0_1[9:9]));
XORCY un84_sop_0_0_0_1_s_8(.LI(un84_sop_0_0_0_1_axb_8),.CI(un84_sop_0_0_0_1_cry_7),.O(un84_sop_0_0_0_0_1[8:8]));
MUXCY_L un84_sop_0_0_0_1_cry_8_cZ(.DI(un1_x_15_0_0_0[14:14]),.CI(un84_sop_0_0_0_1_cry_7),.S(un84_sop_0_0_0_1_axb_8),.LO(un84_sop_0_0_0_1_cry_8));
XORCY un84_sop_0_0_0_1_s_7(.LI(un84_sop_0_0_0_1_axb_7),.CI(un84_sop_0_0_0_1_cry_6),.O(un84_sop_0_0_0_0_1[7:7]));
MUXCY_L un84_sop_0_0_0_1_cry_7_cZ(.DI(un1_x_15_0_0_0[13:13]),.CI(un84_sop_0_0_0_1_cry_6),.S(un84_sop_0_0_0_1_axb_7),.LO(un84_sop_0_0_0_1_cry_7));
XORCY un84_sop_0_0_0_1_s_6(.LI(un84_sop_0_0_0_1_axb_6),.CI(un84_sop_0_0_0_1_cry_5),.O(un84_sop_0_0_0_0_1[6:6]));
MUXCY_L un84_sop_0_0_0_1_cry_6_cZ(.DI(un1_x_15_0_0_0[12:12]),.CI(un84_sop_0_0_0_1_cry_5),.S(un84_sop_0_0_0_1_axb_6),.LO(un84_sop_0_0_0_1_cry_6));
XORCY un84_sop_0_0_0_1_s_5(.LI(un84_sop_0_0_0_1_axb_5),.CI(un84_sop_0_0_0_1_cry_4),.O(un84_sop_0_0_0_0_1[5:5]));
MUXCY_L un84_sop_0_0_0_1_cry_5_cZ(.DI(un1_x_15_0_0_0[11:11]),.CI(un84_sop_0_0_0_1_cry_4),.S(un84_sop_0_0_0_1_axb_5),.LO(un84_sop_0_0_0_1_cry_5));
XORCY un84_sop_0_0_0_1_s_4(.LI(un84_sop_0_0_0_1_axb_4),.CI(un84_sop_0_0_0_1_cry_3),.O(un84_sop_0_0_0_0_1[4:4]));
MUXCY_L un84_sop_0_0_0_1_cry_4_cZ(.DI(un1_x_15_0_0_0[10:10]),.CI(un84_sop_0_0_0_1_cry_3),.S(un84_sop_0_0_0_1_axb_4),.LO(un84_sop_0_0_0_1_cry_4));
XORCY un84_sop_0_0_0_1_s_3(.LI(un84_sop_0_0_0_1_axb_3),.CI(un84_sop_0_0_0_1_cry_2),.O(un84_sop_0_0_0_0_1[3:3]));
MUXCY_L un84_sop_0_0_0_1_cry_3_cZ(.DI(un1_x_15_0_0_0[9:9]),.CI(un84_sop_0_0_0_1_cry_2),.S(un84_sop_0_0_0_1_axb_3),.LO(un84_sop_0_0_0_1_cry_3));
XORCY un84_sop_0_0_0_1_s_2(.LI(un84_sop_0_0_0_1_axb_2),.CI(un84_sop_0_0_0_1_cry_1),.O(un84_sop_0_0_0_0_1[2:2]));
MUXCY_L un84_sop_0_0_0_1_cry_2_cZ(.DI(un1_x_15_0_0_0[8:8]),.CI(un84_sop_0_0_0_1_cry_1),.S(un84_sop_0_0_0_1_axb_2),.LO(un84_sop_0_0_0_1_cry_2));
XORCY un84_sop_0_0_0_1_s_1(.LI(un84_sop_0_0_0_1_axb_1),.CI(un84_sop_0_0_0_1_cry_0),.O(un84_sop_0_0_0_0_1[1:1]));
MUXCY_L un84_sop_0_0_0_1_cry_1_cZ(.DI(un1_x_15_0_0_0[7:7]),.CI(un84_sop_0_0_0_1_cry_0),.S(un84_sop_0_0_0_1_axb_1),.LO(un84_sop_0_0_0_1_cry_1));
MUXCY_L un84_sop_0_0_0_1_cry_0_cZ(.DI(x_13[0:0]),.CI(GND),.S(un84_sop_0_0_0_0_1[0:0]),.LO(un84_sop_0_0_0_1_cry_0));
XORCY un1_x_16_0_s_8(.LI(un1_x_16_0_axb_8),.CI(un1_x_16_0_cry_7),.O(un1_x_16_0_0_0[14:14]));
XORCY un1_x_16_0_s_7(.LI(un1_x_16_0_axb_7),.CI(un1_x_16_0_cry_6),.O(un1_x_16_0_0_0[13:13]));
MUXCY_L un1_x_16_0_cry_7_cZ(.DI(GND),.CI(un1_x_16_0_cry_6),.S(un1_x_16_0_axb_7),.LO(un1_x_16_0_cry_7));
XORCY un1_x_16_0_s_6(.LI(un1_x_16_0_axb_6),.CI(un1_x_16_0_cry_5),.O(un1_x_16_0_0_0[12:12]));
MUXCY_L un1_x_16_0_cry_6_cZ(.DI(GND),.CI(un1_x_16_0_cry_5),.S(un1_x_16_0_axb_6),.LO(un1_x_16_0_cry_6));
XORCY un1_x_16_0_s_5(.LI(un1_x_16_0_axb_5),.CI(un1_x_16_0_cry_4),.O(un1_x_16_0_0_0[11:11]));
MUXCY_L un1_x_16_0_cry_5_cZ(.DI(GND),.CI(un1_x_16_0_cry_4),.S(un1_x_16_0_axb_5),.LO(un1_x_16_0_cry_5));
XORCY un1_x_16_0_s_4(.LI(un1_x_16_0_axb_4),.CI(un1_x_16_0_cry_3),.O(un1_x_16_0_0_0[10:10]));
MUXCY_L un1_x_16_0_cry_4_cZ(.DI(GND),.CI(un1_x_16_0_cry_3),.S(un1_x_16_0_axb_4),.LO(un1_x_16_0_cry_4));
XORCY un1_x_16_0_s_3(.LI(un1_x_16_0_axb_3),.CI(un1_x_16_0_cry_2),.O(un1_x_16_0_0_0[9:9]));
MUXCY_L un1_x_16_0_cry_3_cZ(.DI(GND),.CI(un1_x_16_0_cry_2),.S(un1_x_16_0_axb_3),.LO(un1_x_16_0_cry_3));
XORCY un1_x_16_0_s_2(.LI(un1_x_16_0_axb_2),.CI(un1_x_16_0_cry_1),.O(un1_x_16_0_0_0[8:8]));
MUXCY_L un1_x_16_0_cry_2_cZ(.DI(GND),.CI(un1_x_16_0_cry_1),.S(un1_x_16_0_axb_2),.LO(un1_x_16_0_cry_2));
XORCY un1_x_16_0_s_1(.LI(un1_x_16_0_axb_1),.CI(un1_x_16_0_cry_0),.O(un1_x_16_0_0_0[7:7]));
MUXCY_L un1_x_16_0_cry_1_cZ(.DI(GND),.CI(un1_x_16_0_cry_0),.S(un1_x_16_0_axb_1),.LO(un1_x_16_0_cry_1));
MUXCY_L un1_x_16_0_cry_0_cZ(.DI(GND),.CI(VCC),.S(un1_x_16_0_axb_0),.LO(un1_x_16_0_cry_0));
XORCY un1_x_11_0_s_8(.LI(un1_x_11_0_axb_8),.CI(un1_x_11_0_cry_7),.O(un1_x_11_0_0_0[14:14]));
XORCY un1_x_11_0_s_7(.LI(un1_x_11_0_axb_7),.CI(un1_x_11_0_cry_6),.O(un1_x_11_0_0_0[13:13]));
MUXCY_L un1_x_11_0_cry_7_cZ(.DI(GND),.CI(un1_x_11_0_cry_6),.S(un1_x_11_0_axb_7),.LO(un1_x_11_0_cry_7));
XORCY un1_x_11_0_s_6(.LI(un1_x_11_0_axb_6),.CI(un1_x_11_0_cry_5),.O(un1_x_11_0_0_0[12:12]));
MUXCY_L un1_x_11_0_cry_6_cZ(.DI(GND),.CI(un1_x_11_0_cry_5),.S(un1_x_11_0_axb_6),.LO(un1_x_11_0_cry_6));
XORCY un1_x_11_0_s_5(.LI(un1_x_11_0_axb_5),.CI(un1_x_11_0_cry_4),.O(un1_x_11_0_0_0[11:11]));
MUXCY_L un1_x_11_0_cry_5_cZ(.DI(GND),.CI(un1_x_11_0_cry_4),.S(un1_x_11_0_axb_5),.LO(un1_x_11_0_cry_5));
XORCY un1_x_11_0_s_4(.LI(un1_x_11_0_axb_4),.CI(un1_x_11_0_cry_3),.O(un1_x_11_0_0_0[10:10]));
MUXCY_L un1_x_11_0_cry_4_cZ(.DI(GND),.CI(un1_x_11_0_cry_3),.S(un1_x_11_0_axb_4),.LO(un1_x_11_0_cry_4));
XORCY un1_x_11_0_s_3(.LI(un1_x_11_0_axb_3),.CI(un1_x_11_0_cry_2),.O(un1_x_11_0_0_0[9:9]));
MUXCY_L un1_x_11_0_cry_3_cZ(.DI(GND),.CI(un1_x_11_0_cry_2),.S(un1_x_11_0_axb_3),.LO(un1_x_11_0_cry_3));
XORCY un1_x_11_0_s_2(.LI(un1_x_11_0_axb_2),.CI(un1_x_11_0_cry_1),.O(un1_x_11_0_0_0[8:8]));
MUXCY_L un1_x_11_0_cry_2_cZ(.DI(GND),.CI(un1_x_11_0_cry_1),.S(un1_x_11_0_axb_2),.LO(un1_x_11_0_cry_2));
XORCY un1_x_11_0_s_1(.LI(un1_x_11_0_axb_1),.CI(un1_x_11_0_cry_0),.O(un1_x_11_0_0_0[7:7]));
MUXCY_L un1_x_11_0_cry_1_cZ(.DI(GND),.CI(un1_x_11_0_cry_0),.S(un1_x_11_0_axb_1),.LO(un1_x_11_0_cry_1));
MUXCY_L un1_x_11_0_cry_0_cZ(.DI(GND),.CI(VCC),.S(un1_x_11_0_axb_0),.LO(un1_x_11_0_cry_0));
XORCY un1_x_15_0_s_8(.LI(un1_x_15_0_axb_8),.CI(un1_x_15_0_cry_7),.O(un1_x_15_0_0_0[14:14]));
XORCY un1_x_15_0_s_7(.LI(un1_x_15_0_axb_7),.CI(un1_x_15_0_cry_6),.O(un1_x_15_0_0_0[13:13]));
MUXCY_L un1_x_15_0_cry_7_cZ(.DI(GND),.CI(un1_x_15_0_cry_6),.S(un1_x_15_0_axb_7),.LO(un1_x_15_0_cry_7));
XORCY un1_x_15_0_s_6(.LI(un1_x_15_0_axb_6),.CI(un1_x_15_0_cry_5),.O(un1_x_15_0_0_0[12:12]));
MUXCY_L un1_x_15_0_cry_6_cZ(.DI(GND),.CI(un1_x_15_0_cry_5),.S(un1_x_15_0_axb_6),.LO(un1_x_15_0_cry_6));
XORCY un1_x_15_0_s_5(.LI(un1_x_15_0_axb_5),.CI(un1_x_15_0_cry_4),.O(un1_x_15_0_0_0[11:11]));
MUXCY_L un1_x_15_0_cry_5_cZ(.DI(GND),.CI(un1_x_15_0_cry_4),.S(un1_x_15_0_axb_5),.LO(un1_x_15_0_cry_5));
XORCY un1_x_15_0_s_4(.LI(un1_x_15_0_axb_4),.CI(un1_x_15_0_cry_3),.O(un1_x_15_0_0_0[10:10]));
MUXCY_L un1_x_15_0_cry_4_cZ(.DI(GND),.CI(un1_x_15_0_cry_3),.S(un1_x_15_0_axb_4),.LO(un1_x_15_0_cry_4));
XORCY un1_x_15_0_s_3(.LI(un1_x_15_0_axb_3),.CI(un1_x_15_0_cry_2),.O(un1_x_15_0_0_0[9:9]));
MUXCY_L un1_x_15_0_cry_3_cZ(.DI(GND),.CI(un1_x_15_0_cry_2),.S(un1_x_15_0_axb_3),.LO(un1_x_15_0_cry_3));
XORCY un1_x_15_0_s_2(.LI(un1_x_15_0_axb_2),.CI(un1_x_15_0_cry_1),.O(un1_x_15_0_0_0[8:8]));
MUXCY_L un1_x_15_0_cry_2_cZ(.DI(GND),.CI(un1_x_15_0_cry_1),.S(un1_x_15_0_axb_2),.LO(un1_x_15_0_cry_2));
XORCY un1_x_15_0_s_1(.LI(un1_x_15_0_axb_1),.CI(un1_x_15_0_cry_0),.O(un1_x_15_0_0_0[7:7]));
MUXCY_L un1_x_15_0_cry_1_cZ(.DI(GND),.CI(un1_x_15_0_cry_0),.S(un1_x_15_0_axb_1),.LO(un1_x_15_0_cry_1));
MUXCY_L un1_x_15_0_cry_0_cZ(.DI(GND),.CI(VCC),.S(un1_x_15_0_axb_0),.LO(un1_x_15_0_cry_0));
XORCY un1_x_10_4_s_8(.LI(un1_x_10_4_s_8_false),.CI(un1_x_10_4_cry_7),.O(un1_x_10_4[8:8]));
XORCY un1_x_10_4_s_7(.LI(un1_x_10_4_axb_7),.CI(un1_x_10_4_cry_6),.O(un1_x_10_4[7:7]));
MUXCY_L un1_x_10_4_cry_7_cZ(.DI(x_8[6:6]),.CI(un1_x_10_4_cry_6),.S(un1_x_10_4_axb_7),.LO(un1_x_10_4_cry_7));
XORCY un1_x_10_4_s_6(.LI(un1_x_10_4_axb_6),.CI(un1_x_10_4_cry_5),.O(un1_x_10_4[6:6]));
MUXCY_L un1_x_10_4_cry_6_cZ(.DI(x_8[5:5]),.CI(un1_x_10_4_cry_5),.S(un1_x_10_4_axb_6),.LO(un1_x_10_4_cry_6));
XORCY un1_x_10_4_s_5(.LI(un1_x_10_4_axb_5),.CI(un1_x_10_4_cry_4),.O(un1_x_10_4[5:5]));
MUXCY_L un1_x_10_4_cry_5_cZ(.DI(x_8[4:4]),.CI(un1_x_10_4_cry_4),.S(un1_x_10_4_axb_5),.LO(un1_x_10_4_cry_5));
XORCY un1_x_10_4_s_4(.LI(un1_x_10_4_axb_4),.CI(un1_x_10_4_cry_3),.O(un1_x_10_4[4:4]));
MUXCY_L un1_x_10_4_cry_4_cZ(.DI(x_8[3:3]),.CI(un1_x_10_4_cry_3),.S(un1_x_10_4_axb_4),.LO(un1_x_10_4_cry_4));
XORCY un1_x_10_4_s_3(.LI(un1_x_10_4_axb_3),.CI(un1_x_10_4_cry_2),.O(un1_x_10_4[3:3]));
MUXCY_L un1_x_10_4_cry_3_cZ(.DI(x_8[2:2]),.CI(un1_x_10_4_cry_2),.S(un1_x_10_4_axb_3),.LO(un1_x_10_4_cry_3));
XORCY un1_x_10_4_s_2(.LI(un1_x_10_4_axb_2),.CI(un1_x_10_4_cry_1),.O(un1_x_10_4[2:2]));
MUXCY_L un1_x_10_4_cry_2_cZ(.DI(x_8[1:1]),.CI(un1_x_10_4_cry_1),.S(un1_x_10_4_axb_2),.LO(un1_x_10_4_cry_2));
MUXCY_L un1_x_10_4_cry_1_cZ(.DI(x_8[0:0]),.CI(GND),.S(un1_x_10_4_cry_1_sf),.LO(un1_x_10_4_cry_1));
XORCY un84_sop_1_s_14_cZ(.LI(un84_sop_1_axb_14),.CI(un84_sop_1_cry_13),.O(un84_sop_1_s_14));
XORCY un84_sop_1_s_13_cZ(.LI(un84_sop_1_axb_13),.CI(un84_sop_1_cry_12),.O(un84_sop_1_s_13));
MUXCY_L un84_sop_1_cry_13_cZ(.DI(un84_sop_1_4[13:13]),.CI(un84_sop_1_cry_12),.S(un84_sop_1_axb_13),.LO(un84_sop_1_cry_13));
XORCY un84_sop_1_s_12_cZ(.LI(un84_sop_1_axb_12),.CI(un84_sop_1_cry_11),.O(un84_sop_1_s_12));
MUXCY_L un84_sop_1_cry_12_cZ(.DI(un84_sop_1_4[12:12]),.CI(un84_sop_1_cry_11),.S(un84_sop_1_axb_12),.LO(un84_sop_1_cry_12));
XORCY un84_sop_1_s_11_cZ(.LI(un84_sop_1_axb_11),.CI(un84_sop_1_cry_10),.O(un84_sop_1_s_11));
MUXCY_L un84_sop_1_cry_11_cZ(.DI(un84_sop_1_4[11:11]),.CI(un84_sop_1_cry_10),.S(un84_sop_1_axb_11),.LO(un84_sop_1_cry_11));
XORCY un84_sop_1_s_10_cZ(.LI(un84_sop_1_axb_10),.CI(un84_sop_1_cry_9),.O(un84_sop_1_s_10));
MUXCY_L un84_sop_1_cry_10_cZ(.DI(un84_sop_1_4[10:10]),.CI(un84_sop_1_cry_9),.S(un84_sop_1_axb_10),.LO(un84_sop_1_cry_10));
XORCY un84_sop_1_s_9_cZ(.LI(un84_sop_1_axb_9),.CI(un84_sop_1_cry_8),.O(un84_sop_1_s_9));
MUXCY_L un84_sop_1_cry_9_cZ(.DI(un84_sop_1_4[9:9]),.CI(un84_sop_1_cry_8),.S(un84_sop_1_axb_9),.LO(un84_sop_1_cry_9));
XORCY un84_sop_1_s_8_cZ(.LI(un84_sop_1_axb_8),.CI(un84_sop_1_cry_7),.O(un84_sop_1_s_8));
MUXCY_L un84_sop_1_cry_8_cZ(.DI(un84_sop_1_4[8:8]),.CI(un84_sop_1_cry_7),.S(un84_sop_1_axb_8),.LO(un84_sop_1_cry_8));
XORCY un84_sop_1_s_7_cZ(.LI(un84_sop_1_axb_7),.CI(un84_sop_1_cry_6),.O(un84_sop_1_s_7));
MUXCY_L un84_sop_1_cry_7_cZ(.DI(un84_sop_1_4[7:7]),.CI(un84_sop_1_cry_6),.S(un84_sop_1_axb_7),.LO(un84_sop_1_cry_7));
MUXCY_L un84_sop_1_cry_6_cZ(.DI(un84_sop_1_4[6:6]),.CI(un84_sop_1_cry_5),.S(un84_sop_1_axb_6),.LO(un84_sop_1_cry_6));
MUXCY_L un84_sop_1_cry_5_cZ(.DI(un84_sop_1_4[5:5]),.CI(un84_sop_1_cry_4),.S(un84_sop_1_axb_5),.LO(un84_sop_1_cry_5));
MUXCY_L un84_sop_1_cry_4_cZ(.DI(un84_sop_1_4[4:4]),.CI(un84_sop_1_cry_3),.S(un84_sop_1_axb_4),.LO(un84_sop_1_cry_4));
MUXCY_L un84_sop_1_cry_3_cZ(.DI(un84_sop_1_4[3:3]),.CI(un84_sop_1_cry_2),.S(un84_sop_1_axb_3),.LO(un84_sop_1_cry_3));
MUXCY_L un84_sop_1_cry_2_cZ(.DI(un84_sop_1_4[2:2]),.CI(un84_sop_1_cry_1),.S(un84_sop_1_axb_2),.LO(un84_sop_1_cry_2));
MUXCY_L un84_sop_1_cry_1_cZ(.DI(un84_sop_1_4[1:1]),.CI(un84_sop_1_cry_0),.S(un84_sop_1_axb_1),.LO(un84_sop_1_cry_1));
MUXCY_L un84_sop_1_cry_0_cZ(.DI(un84_sop_1_6[0:0]),.CI(GND),.S(un84_sop_1_axb_0),.LO(un84_sop_1_cry_0));
XORCY un84_sop_1_4_s_14(.LI(un84_sop_1_4_axb_14),.CI(un84_sop_1_4_cry_13),.O(un84_sop_1_4[14:14]));
XORCY un84_sop_1_4_s_13(.LI(un84_sop_1_4_axb_13),.CI(un84_sop_1_4_cry_12),.O(un84_sop_1_4[13:13]));
MUXCY_L un84_sop_1_4_cry_13_cZ(.DI(un84_sop_1_7[13:13]),.CI(un84_sop_1_4_cry_12),.S(un84_sop_1_4_axb_13),.LO(un84_sop_1_4_cry_13));
XORCY un84_sop_1_4_s_12(.LI(un84_sop_1_4_axb_12),.CI(un84_sop_1_4_cry_11),.O(un84_sop_1_4[12:12]));
MUXCY_L un84_sop_1_4_cry_12_cZ(.DI(un84_sop_1_7[12:12]),.CI(un84_sop_1_4_cry_11),.S(un84_sop_1_4_axb_12),.LO(un84_sop_1_4_cry_12));
XORCY un84_sop_1_4_s_11(.LI(un84_sop_1_4_axb_11),.CI(un84_sop_1_4_cry_10),.O(un84_sop_1_4[11:11]));
MUXCY_L un84_sop_1_4_cry_11_cZ(.DI(un84_sop_1_7[11:11]),.CI(un84_sop_1_4_cry_10),.S(un84_sop_1_4_axb_11),.LO(un84_sop_1_4_cry_11));
XORCY un84_sop_1_4_s_10(.LI(un84_sop_1_4_axb_10),.CI(un84_sop_1_4_cry_9),.O(un84_sop_1_4[10:10]));
MUXCY_L un84_sop_1_4_cry_10_cZ(.DI(un84_sop_1_7[10:10]),.CI(un84_sop_1_4_cry_9),.S(un84_sop_1_4_axb_10),.LO(un84_sop_1_4_cry_10));
XORCY un84_sop_1_4_s_9(.LI(un84_sop_1_4_axb_9),.CI(un84_sop_1_4_cry_8),.O(un84_sop_1_4[9:9]));
MUXCY_L un84_sop_1_4_cry_9_cZ(.DI(un84_sop_1_7[9:9]),.CI(un84_sop_1_4_cry_8),.S(un84_sop_1_4_axb_9),.LO(un84_sop_1_4_cry_9));
XORCY un84_sop_1_4_s_8(.LI(un84_sop_1_4_axb_8),.CI(un84_sop_1_4_cry_7),.O(un84_sop_1_4[8:8]));
MUXCY_L un84_sop_1_4_cry_8_cZ(.DI(un84_sop_1_7[8:8]),.CI(un84_sop_1_4_cry_7),.S(un84_sop_1_4_axb_8),.LO(un84_sop_1_4_cry_8));
XORCY un84_sop_1_4_s_7(.LI(un84_sop_1_4_axb_7),.CI(un84_sop_1_4_cry_6),.O(un84_sop_1_4[7:7]));
MUXCY_L un84_sop_1_4_cry_7_cZ(.DI(un84_sop_1_7[7:7]),.CI(un84_sop_1_4_cry_6),.S(un84_sop_1_4_axb_7),.LO(un84_sop_1_4_cry_7));
XORCY un84_sop_1_4_s_6(.LI(un84_sop_1_4_axb_6),.CI(un84_sop_1_4_cry_5),.O(un84_sop_1_4[6:6]));
MUXCY_L un84_sop_1_4_cry_6_cZ(.DI(un84_sop_1_7[6:6]),.CI(un84_sop_1_4_cry_5),.S(un84_sop_1_4_axb_6),.LO(un84_sop_1_4_cry_6));
XORCY un84_sop_1_4_s_5(.LI(un84_sop_1_4_axb_5),.CI(un84_sop_1_4_cry_4),.O(un84_sop_1_4[5:5]));
MUXCY_L un84_sop_1_4_cry_5_cZ(.DI(un84_sop_1_7[5:5]),.CI(un84_sop_1_4_cry_4),.S(un84_sop_1_4_axb_5),.LO(un84_sop_1_4_cry_5));
XORCY un84_sop_1_4_s_4(.LI(un84_sop_1_4_axb_4),.CI(un84_sop_1_4_cry_3),.O(un84_sop_1_4[4:4]));
MUXCY_L un84_sop_1_4_cry_4_cZ(.DI(un84_sop_1_7[4:4]),.CI(un84_sop_1_4_cry_3),.S(un84_sop_1_4_axb_4),.LO(un84_sop_1_4_cry_4));
XORCY un84_sop_1_4_s_3(.LI(un84_sop_1_4_axb_3),.CI(un84_sop_1_4_cry_2),.O(un84_sop_1_4[3:3]));
MUXCY_L un84_sop_1_4_cry_3_cZ(.DI(un84_sop_1_7[3:3]),.CI(un84_sop_1_4_cry_2),.S(un84_sop_1_4_axb_3),.LO(un84_sop_1_4_cry_3));
XORCY un84_sop_1_4_s_2(.LI(un84_sop_1_4_axb_2),.CI(un84_sop_1_4_cry_1),.O(un84_sop_1_4[2:2]));
MUXCY_L un84_sop_1_4_cry_2_cZ(.DI(un84_sop_1_7[2:2]),.CI(un84_sop_1_4_cry_1),.S(un84_sop_1_4_axb_2),.LO(un84_sop_1_4_cry_2));
XORCY un84_sop_1_4_s_1(.LI(un84_sop_1_4_axb_1),.CI(un84_sop_1_4_cry_0),.O(un84_sop_1_4[1:1]));
MUXCY_L un84_sop_1_4_cry_1_cZ(.DI(un84_sop_1_7[1:1]),.CI(un84_sop_1_4_cry_0),.S(un84_sop_1_4_axb_1),.LO(un84_sop_1_4_cry_1));
MUXCY_L un84_sop_1_4_cry_0_cZ(.DI(un84_sop_1_7[0:0]),.CI(GND),.S(un84_sop_1_4[0:0]),.LO(un84_sop_1_4_cry_0));
XORCY un84_sop_0_0_0_0_11_7_s_10(.LI(un84_sop_0_0_0_0_11_7_axb_10),.CI(un84_sop_0_0_0_0_11_7_cry_9),.O(un84_sop_0_0_0_0_11_7[14:14]));
XORCY un84_sop_0_0_0_0_11_7_s_9(.LI(un84_sop_0_0_0_0_11_7_axb_9),.CI(un84_sop_0_0_0_0_11_7_cry_8),.O(un84_sop_0_0_0_0_11_7[9:9]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_9_cZ(.DI(un84_sop_0_0_0_0_0[9:9]),.CI(un84_sop_0_0_0_0_11_7_cry_8),.S(un84_sop_0_0_0_0_11_7_axb_9),.LO(un84_sop_0_0_0_0_11_7_cry_9));
XORCY un84_sop_0_0_0_0_11_7_s_8(.LI(un84_sop_0_0_0_0_11_7_axb_8),.CI(un84_sop_0_0_0_0_11_7_cry_7),.O(un84_sop_0_0_0_0_11_7[8:8]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_8_cZ(.DI(un84_sop_0_0_0_0_0[8:8]),.CI(un84_sop_0_0_0_0_11_7_cry_7),.S(un84_sop_0_0_0_0_11_7_axb_8),.LO(un84_sop_0_0_0_0_11_7_cry_8));
XORCY un84_sop_0_0_0_0_11_7_s_7(.LI(un84_sop_0_0_0_0_11_7_axb_7),.CI(un84_sop_0_0_0_0_11_7_cry_6),.O(un84_sop_0_0_0_0_11_7[7:7]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_7_cZ(.DI(un84_sop_0_0_0_0_0[7:7]),.CI(un84_sop_0_0_0_0_11_7_cry_6),.S(un84_sop_0_0_0_0_11_7_axb_7),.LO(un84_sop_0_0_0_0_11_7_cry_7));
XORCY un84_sop_0_0_0_0_11_7_s_6(.LI(un84_sop_0_0_0_0_11_7_axb_6),.CI(un84_sop_0_0_0_0_11_7_cry_5),.O(un84_sop_0_0_0_0_11_7[6:6]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_6_cZ(.DI(un84_sop_0_0_0_0_0[6:6]),.CI(un84_sop_0_0_0_0_11_7_cry_5),.S(un84_sop_0_0_0_0_11_7_axb_6),.LO(un84_sop_0_0_0_0_11_7_cry_6));
XORCY un84_sop_0_0_0_0_11_7_s_5(.LI(un84_sop_0_0_0_0_11_7_axb_5),.CI(un84_sop_0_0_0_0_11_7_cry_4),.O(un84_sop_0_0_0_0_11_7[5:5]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_5_cZ(.DI(un84_sop_0_0_0_0_0[5:5]),.CI(un84_sop_0_0_0_0_11_7_cry_4),.S(un84_sop_0_0_0_0_11_7_axb_5),.LO(un84_sop_0_0_0_0_11_7_cry_5));
XORCY un84_sop_0_0_0_0_11_7_s_4(.LI(un84_sop_0_0_0_0_11_7_axb_4),.CI(un84_sop_0_0_0_0_11_7_cry_3),.O(un84_sop_0_0_0_0_11_7[4:4]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_4_cZ(.DI(un84_sop_0_0_0_0_0[4:4]),.CI(un84_sop_0_0_0_0_11_7_cry_3),.S(un84_sop_0_0_0_0_11_7_axb_4),.LO(un84_sop_0_0_0_0_11_7_cry_4));
XORCY un84_sop_0_0_0_0_11_7_s_3(.LI(un84_sop_0_0_0_0_11_7_axb_3),.CI(un84_sop_0_0_0_0_11_7_cry_2),.O(un84_sop_0_0_0_0_11_7[3:3]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_3_cZ(.DI(un84_sop_0_0_0_0_0[3:3]),.CI(un84_sop_0_0_0_0_11_7_cry_2),.S(un84_sop_0_0_0_0_11_7_axb_3),.LO(un84_sop_0_0_0_0_11_7_cry_3));
XORCY un84_sop_0_0_0_0_11_7_s_2(.LI(un84_sop_0_0_0_0_11_7_axb_2),.CI(un84_sop_0_0_0_0_11_7_cry_1),.O(un84_sop_0_0_0_0_11_7[2:2]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_2_cZ(.DI(un84_sop_0_0_0_0_0[2:2]),.CI(un84_sop_0_0_0_0_11_7_cry_1),.S(un84_sop_0_0_0_0_11_7_axb_2),.LO(un84_sop_0_0_0_0_11_7_cry_2));
XORCY un84_sop_0_0_0_0_11_7_s_1(.LI(un84_sop_0_0_0_0_11_7_axb_1),.CI(un84_sop_0_0_0_0_11_7_cry_0),.O(un84_sop_0_0_0_0_11_7[1:1]));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_1_cZ(.DI(un84_sop_0_0_0_0_0[1:1]),.CI(un84_sop_0_0_0_0_11_7_cry_0),.S(un84_sop_0_0_0_0_11_7_axb_1),.LO(un84_sop_0_0_0_0_11_7_cry_1));
MUXCY_L un84_sop_0_0_0_0_11_7_cry_0_cZ(.DI(un84_sop_0_0_0_0_0[0:0]),.CI(GND),.S(un84_sop_0_0_0_0_11_7[0:0]),.LO(un84_sop_0_0_0_0_11_7_cry_0));
XORCY un84_sop_1_7_s_14(.LI(un84_sop_1_7_axb_14),.CI(un84_sop_1_7_cry_13),.O(un84_sop_1_7[14:14]));
XORCY un84_sop_1_7_s_13(.LI(un84_sop_1_7_axb_13),.CI(un84_sop_1_7_cry_12),.O(un84_sop_1_7[13:13]));
MUXCY_L un84_sop_1_7_cry_13_cZ(.DI(un84_sop_0_0_0_0_5[13:13]),.CI(un84_sop_1_7_cry_12),.S(un84_sop_1_7_axb_13),.LO(un84_sop_1_7_cry_13));
XORCY un84_sop_1_7_s_12(.LI(un84_sop_1_7_axb_12),.CI(un84_sop_1_7_cry_11),.O(un84_sop_1_7[12:12]));
MUXCY_L un84_sop_1_7_cry_12_cZ(.DI(un84_sop_0_0_0_0_5[12:12]),.CI(un84_sop_1_7_cry_11),.S(un84_sop_1_7_axb_12),.LO(un84_sop_1_7_cry_12));
XORCY un84_sop_1_7_s_11(.LI(un84_sop_1_7_axb_11),.CI(un84_sop_1_7_cry_10),.O(un84_sop_1_7[11:11]));
MUXCY_L un84_sop_1_7_cry_11_cZ(.DI(un84_sop_0_0_0_0_5[11:11]),.CI(un84_sop_1_7_cry_10),.S(un84_sop_1_7_axb_11),.LO(un84_sop_1_7_cry_11));
XORCY un84_sop_1_7_s_10(.LI(un84_sop_1_7_axb_10),.CI(un84_sop_1_7_cry_9),.O(un84_sop_1_7[10:10]));
MUXCY_L un84_sop_1_7_cry_10_cZ(.DI(un84_sop_0_0_0_0_5[10:10]),.CI(un84_sop_1_7_cry_9),.S(un84_sop_1_7_axb_10),.LO(un84_sop_1_7_cry_10));
XORCY un84_sop_1_7_s_9(.LI(un84_sop_1_7_axb_9),.CI(un84_sop_1_7_cry_8),.O(un84_sop_1_7[9:9]));
MUXCY_L un84_sop_1_7_cry_9_cZ(.DI(un84_sop_0_0_0_0_5[9:9]),.CI(un84_sop_1_7_cry_8),.S(un84_sop_1_7_axb_9),.LO(un84_sop_1_7_cry_9));
XORCY un84_sop_1_7_s_8(.LI(un84_sop_1_7_axb_8),.CI(un84_sop_1_7_cry_7),.O(un84_sop_1_7[8:8]));
MUXCY_L un84_sop_1_7_cry_8_cZ(.DI(un84_sop_0_0_0_0_5[8:8]),.CI(un84_sop_1_7_cry_7),.S(un84_sop_1_7_axb_8),.LO(un84_sop_1_7_cry_8));
XORCY un84_sop_1_7_s_7(.LI(un84_sop_1_7_axb_7),.CI(un84_sop_1_7_cry_6),.O(un84_sop_1_7[7:7]));
MUXCY_L un84_sop_1_7_cry_7_cZ(.DI(un84_sop_0_0_0_0_5[7:7]),.CI(un84_sop_1_7_cry_6),.S(un84_sop_1_7_axb_7),.LO(un84_sop_1_7_cry_7));
XORCY un84_sop_1_7_s_6(.LI(un84_sop_1_7_axb_6),.CI(un84_sop_1_7_cry_5),.O(un84_sop_1_7[6:6]));
MUXCY_L un84_sop_1_7_cry_6_cZ(.DI(un84_sop_0_0_0_0_5[6:6]),.CI(un84_sop_1_7_cry_5),.S(un84_sop_1_7_axb_6),.LO(un84_sop_1_7_cry_6));
XORCY un84_sop_1_7_s_5(.LI(un84_sop_1_7_axb_5),.CI(un84_sop_1_7_cry_4),.O(un84_sop_1_7[5:5]));
MUXCY_L un84_sop_1_7_cry_5_cZ(.DI(un84_sop_0_0_0_0_5[5:5]),.CI(un84_sop_1_7_cry_4),.S(un84_sop_1_7_axb_5),.LO(un84_sop_1_7_cry_5));
XORCY un84_sop_1_7_s_4(.LI(un84_sop_1_7_axb_4),.CI(un84_sop_1_7_cry_3),.O(un84_sop_1_7[4:4]));
MUXCY_L un84_sop_1_7_cry_4_cZ(.DI(un84_sop_0_0_0_0_5[4:4]),.CI(un84_sop_1_7_cry_3),.S(un84_sop_1_7_axb_4),.LO(un84_sop_1_7_cry_4));
XORCY un84_sop_1_7_s_3(.LI(un84_sop_1_7_axb_3),.CI(un84_sop_1_7_cry_2),.O(un84_sop_1_7[3:3]));
MUXCY_L un84_sop_1_7_cry_3_cZ(.DI(un84_sop_0_0_0_0_5[3:3]),.CI(un84_sop_1_7_cry_2),.S(un84_sop_1_7_axb_3),.LO(un84_sop_1_7_cry_3));
XORCY un84_sop_1_7_s_2(.LI(un84_sop_1_7_axb_2),.CI(un84_sop_1_7_cry_1),.O(un84_sop_1_7[2:2]));
MUXCY_L un84_sop_1_7_cry_2_cZ(.DI(un84_sop_0_0_0_0_5[2:2]),.CI(un84_sop_1_7_cry_1),.S(un84_sop_1_7_axb_2),.LO(un84_sop_1_7_cry_2));
XORCY un84_sop_1_7_s_1(.LI(un84_sop_1_7_axb_1),.CI(un84_sop_1_7_cry_0),.O(un84_sop_1_7[1:1]));
MUXCY_L un84_sop_1_7_cry_1_cZ(.DI(un84_sop_0_0_0_0_5[1:1]),.CI(un84_sop_1_7_cry_0),.S(un84_sop_1_7_axb_1),.LO(un84_sop_1_7_cry_1));
MUXCY_L un84_sop_1_7_cry_0_cZ(.DI(un84_sop_0_0_0_0_5[0:0]),.CI(GND),.S(un84_sop_1_7[0:0]),.LO(un84_sop_1_7_cry_0));
XORCY un84_sop_0_0_0_1_6_s_14(.LI(un84_sop_0_0_0_1_6_axb_14),.CI(un84_sop_0_0_0_1_6_cry_13),.O(un84_sop_0_0_0_5_0[14:14]));
XORCY un84_sop_0_0_0_1_6_s_13(.LI(un84_sop_0_0_0_1_6_axb_13),.CI(un84_sop_0_0_0_1_6_cry_12),.O(un84_sop_0_0_0_5_0[13:13]));
MUXCY_L un84_sop_0_0_0_1_6_cry_13_cZ(.DI(un84_sop_0_0_0_1_6_4[13:13]),.CI(un84_sop_0_0_0_1_6_cry_12),.S(un84_sop_0_0_0_1_6_axb_13),.LO(un84_sop_0_0_0_1_6_cry_13));
XORCY un84_sop_0_0_0_1_6_s_12(.LI(un84_sop_0_0_0_1_6_axb_12),.CI(un84_sop_0_0_0_1_6_cry_11),.O(un84_sop_0_0_0_5_0[12:12]));
MUXCY_L un84_sop_0_0_0_1_6_cry_12_cZ(.DI(un84_sop_0_0_0_1_6_4[12:12]),.CI(un84_sop_0_0_0_1_6_cry_11),.S(un84_sop_0_0_0_1_6_axb_12),.LO(un84_sop_0_0_0_1_6_cry_12));
XORCY un84_sop_0_0_0_1_6_s_11(.LI(un84_sop_0_0_0_1_6_axb_11),.CI(un84_sop_0_0_0_1_6_cry_10),.O(un84_sop_0_0_0_5_0[11:11]));
MUXCY_L un84_sop_0_0_0_1_6_cry_11_cZ(.DI(un84_sop_0_0_0_1_6_4[11:11]),.CI(un84_sop_0_0_0_1_6_cry_10),.S(un84_sop_0_0_0_1_6_axb_11),.LO(un84_sop_0_0_0_1_6_cry_11));
XORCY un84_sop_0_0_0_1_6_s_10(.LI(un84_sop_0_0_0_1_6_axb_10),.CI(un84_sop_0_0_0_1_6_cry_9),.O(un84_sop_0_0_0_5_0[10:10]));
MUXCY_L un84_sop_0_0_0_1_6_cry_10_cZ(.DI(un84_sop_0_0_0_1_6_4[10:10]),.CI(un84_sop_0_0_0_1_6_cry_9),.S(un84_sop_0_0_0_1_6_axb_10),.LO(un84_sop_0_0_0_1_6_cry_10));
XORCY un84_sop_0_0_0_1_6_s_9(.LI(un84_sop_0_0_0_1_6_axb_9),.CI(un84_sop_0_0_0_1_6_cry_8),.O(un84_sop_0_0_0_5_0[9:9]));
MUXCY_L un84_sop_0_0_0_1_6_cry_9_cZ(.DI(un84_sop_0_0_0_1_6_4[9:9]),.CI(un84_sop_0_0_0_1_6_cry_8),.S(un84_sop_0_0_0_1_6_axb_9),.LO(un84_sop_0_0_0_1_6_cry_9));
XORCY un84_sop_0_0_0_1_6_s_8(.LI(un84_sop_0_0_0_1_6_axb_8),.CI(un84_sop_0_0_0_1_6_cry_7),.O(un84_sop_0_0_0_5_0[8:8]));
MUXCY_L un84_sop_0_0_0_1_6_cry_8_cZ(.DI(un84_sop_0_0_0_1_6_4[8:8]),.CI(un84_sop_0_0_0_1_6_cry_7),.S(un84_sop_0_0_0_1_6_axb_8),.LO(un84_sop_0_0_0_1_6_cry_8));
XORCY un84_sop_0_0_0_1_6_s_7(.LI(un84_sop_0_0_0_1_6_axb_7),.CI(un84_sop_0_0_0_1_6_cry_6),.O(un84_sop_0_0_0_5_0[7:7]));
MUXCY_L un84_sop_0_0_0_1_6_cry_7_cZ(.DI(un84_sop_0_0_0_1_6_4[7:7]),.CI(un84_sop_0_0_0_1_6_cry_6),.S(un84_sop_0_0_0_1_6_axb_7),.LO(un84_sop_0_0_0_1_6_cry_7));
XORCY un84_sop_0_0_0_1_6_s_6(.LI(un84_sop_0_0_0_1_6_axb_6),.CI(un84_sop_0_0_0_1_6_cry_5),.O(un84_sop_0_0_0_5_0[6:6]));
MUXCY_L un84_sop_0_0_0_1_6_cry_6_cZ(.DI(un84_sop_0_0_0_1_6_4[6:6]),.CI(un84_sop_0_0_0_1_6_cry_5),.S(un84_sop_0_0_0_1_6_axb_6),.LO(un84_sop_0_0_0_1_6_cry_6));
XORCY un84_sop_0_0_0_1_6_s_5(.LI(un84_sop_0_0_0_1_6_axb_5),.CI(un84_sop_0_0_0_1_6_cry_4),.O(un84_sop_0_0_0_5_0[5:5]));
MUXCY_L un84_sop_0_0_0_1_6_cry_5_cZ(.DI(un84_sop_0_0_0_1_6_4[5:5]),.CI(un84_sop_0_0_0_1_6_cry_4),.S(un84_sop_0_0_0_1_6_axb_5),.LO(un84_sop_0_0_0_1_6_cry_5));
XORCY un84_sop_0_0_0_1_6_s_4(.LI(un84_sop_0_0_0_1_6_axb_4),.CI(un84_sop_0_0_0_1_6_cry_3),.O(un84_sop_0_0_0_5_0[4:4]));
MUXCY_L un84_sop_0_0_0_1_6_cry_4_cZ(.DI(un84_sop_0_0_0_1_6_4[4:4]),.CI(un84_sop_0_0_0_1_6_cry_3),.S(un84_sop_0_0_0_1_6_axb_4),.LO(un84_sop_0_0_0_1_6_cry_4));
XORCY un84_sop_0_0_0_1_6_s_3(.LI(un84_sop_0_0_0_1_6_axb_3),.CI(un84_sop_0_0_0_1_6_cry_2),.O(un84_sop_0_0_0_5_0[3:3]));
MUXCY_L un84_sop_0_0_0_1_6_cry_3_cZ(.DI(un84_sop_0_0_0_1_6_4[3:3]),.CI(un84_sop_0_0_0_1_6_cry_2),.S(un84_sop_0_0_0_1_6_axb_3),.LO(un84_sop_0_0_0_1_6_cry_3));
XORCY un84_sop_0_0_0_1_6_s_2(.LI(un84_sop_0_0_0_1_6_axb_2),.CI(un84_sop_0_0_0_1_6_cry_1),.O(un84_sop_0_0_0_5_0[2:2]));
MUXCY_L un84_sop_0_0_0_1_6_cry_2_cZ(.DI(un84_sop_0_0_0_1_6_4[2:2]),.CI(un84_sop_0_0_0_1_6_cry_1),.S(un84_sop_0_0_0_1_6_axb_2),.LO(un84_sop_0_0_0_1_6_cry_2));
XORCY un84_sop_0_0_0_1_6_s_1(.LI(un84_sop_0_0_0_1_6_axb_1),.CI(un84_sop_0_0_0_1_6_cry_0),.O(un84_sop_0_0_0_5_0[1:1]));
MUXCY_L un84_sop_0_0_0_1_6_cry_1_cZ(.DI(un84_sop_0_0_0_1_6_4[1:1]),.CI(un84_sop_0_0_0_1_6_cry_0),.S(un84_sop_0_0_0_1_6_axb_1),.LO(un84_sop_0_0_0_1_6_cry_1));
MUXCY_L un84_sop_0_0_0_1_6_cry_0_cZ(.DI(un84_sop_0_0_0_1_6_6[0:0]),.CI(GND),.S(un84_sop_0_0_0_5_0[0:0]),.LO(un84_sop_0_0_0_1_6_cry_0));
XORCY un84_sop_0_0_0_1_6_4_s_14(.LI(un84_sop_0_0_0_1_6_4_axb_14),.CI(un84_sop_0_0_0_1_6_4_cry_13),.O(un84_sop_0_0_0_1_6_4[14:14]));
XORCY un84_sop_0_0_0_1_6_4_s_13(.LI(un84_sop_0_0_0_1_6_4_axb_13),.CI(un84_sop_0_0_0_1_6_4_cry_12),.O(un84_sop_0_0_0_1_6_4[13:13]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_13_cZ(.DI(un84_sop_0_0_0_1_6_8[13:13]),.CI(un84_sop_0_0_0_1_6_4_cry_12),.S(un84_sop_0_0_0_1_6_4_axb_13),.LO(un84_sop_0_0_0_1_6_4_cry_13));
XORCY un84_sop_0_0_0_1_6_4_s_12(.LI(un84_sop_0_0_0_1_6_4_axb_12),.CI(un84_sop_0_0_0_1_6_4_cry_11),.O(un84_sop_0_0_0_1_6_4[12:12]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_12_cZ(.DI(un84_sop_0_0_0_1_6_8[12:12]),.CI(un84_sop_0_0_0_1_6_4_cry_11),.S(un84_sop_0_0_0_1_6_4_axb_12),.LO(un84_sop_0_0_0_1_6_4_cry_12));
XORCY un84_sop_0_0_0_1_6_4_s_11(.LI(un84_sop_0_0_0_1_6_4_axb_11),.CI(un84_sop_0_0_0_1_6_4_cry_10),.O(un84_sop_0_0_0_1_6_4[11:11]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_11_cZ(.DI(un84_sop_0_0_0_1_6_8[11:11]),.CI(un84_sop_0_0_0_1_6_4_cry_10),.S(un84_sop_0_0_0_1_6_4_axb_11),.LO(un84_sop_0_0_0_1_6_4_cry_11));
XORCY un84_sop_0_0_0_1_6_4_s_10(.LI(un84_sop_0_0_0_1_6_4_axb_10),.CI(un84_sop_0_0_0_1_6_4_cry_9),.O(un84_sop_0_0_0_1_6_4[10:10]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_10_cZ(.DI(un84_sop_0_0_0_1_6_8[10:10]),.CI(un84_sop_0_0_0_1_6_4_cry_9),.S(un84_sop_0_0_0_1_6_4_axb_10),.LO(un84_sop_0_0_0_1_6_4_cry_10));
XORCY un84_sop_0_0_0_1_6_4_s_9(.LI(un84_sop_0_0_0_1_6_4_axb_9),.CI(un84_sop_0_0_0_1_6_4_cry_8),.O(un84_sop_0_0_0_1_6_4[9:9]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_9_cZ(.DI(un84_sop_0_0_0_1_6_8[9:9]),.CI(un84_sop_0_0_0_1_6_4_cry_8),.S(un84_sop_0_0_0_1_6_4_axb_9),.LO(un84_sop_0_0_0_1_6_4_cry_9));
XORCY un84_sop_0_0_0_1_6_4_s_8(.LI(un84_sop_0_0_0_1_6_4_axb_8),.CI(un84_sop_0_0_0_1_6_4_cry_7),.O(un84_sop_0_0_0_1_6_4[8:8]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_8_cZ(.DI(un84_sop_0_0_0_1_6_8[8:8]),.CI(un84_sop_0_0_0_1_6_4_cry_7),.S(un84_sop_0_0_0_1_6_4_axb_8),.LO(un84_sop_0_0_0_1_6_4_cry_8));
XORCY un84_sop_0_0_0_1_6_4_s_7(.LI(un84_sop_0_0_0_1_6_4_axb_7),.CI(un84_sop_0_0_0_1_6_4_cry_6),.O(un84_sop_0_0_0_1_6_4[7:7]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_7_cZ(.DI(un84_sop_0_0_0_1_6_8[7:7]),.CI(un84_sop_0_0_0_1_6_4_cry_6),.S(un84_sop_0_0_0_1_6_4_axb_7),.LO(un84_sop_0_0_0_1_6_4_cry_7));
XORCY un84_sop_0_0_0_1_6_4_s_6(.LI(un84_sop_0_0_0_1_6_4_axb_6),.CI(un84_sop_0_0_0_1_6_4_cry_5),.O(un84_sop_0_0_0_1_6_4[6:6]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_6_cZ(.DI(un84_sop_0_0_0_1_6_8[6:6]),.CI(un84_sop_0_0_0_1_6_4_cry_5),.S(un84_sop_0_0_0_1_6_4_axb_6),.LO(un84_sop_0_0_0_1_6_4_cry_6));
XORCY un84_sop_0_0_0_1_6_4_s_5(.LI(un84_sop_0_0_0_1_6_4_axb_5),.CI(un84_sop_0_0_0_1_6_4_cry_4),.O(un84_sop_0_0_0_1_6_4[5:5]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_5_cZ(.DI(un84_sop_0_0_0_1_6_8[5:5]),.CI(un84_sop_0_0_0_1_6_4_cry_4),.S(un84_sop_0_0_0_1_6_4_axb_5),.LO(un84_sop_0_0_0_1_6_4_cry_5));
XORCY un84_sop_0_0_0_1_6_4_s_4(.LI(un84_sop_0_0_0_1_6_4_axb_4),.CI(un84_sop_0_0_0_1_6_4_cry_3),.O(un84_sop_0_0_0_1_6_4[4:4]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_4_cZ(.DI(un84_sop_0_0_0_1_6_8[4:4]),.CI(un84_sop_0_0_0_1_6_4_cry_3),.S(un84_sop_0_0_0_1_6_4_axb_4),.LO(un84_sop_0_0_0_1_6_4_cry_4));
XORCY un84_sop_0_0_0_1_6_4_s_3(.LI(un84_sop_0_0_0_1_6_4_axb_3),.CI(un84_sop_0_0_0_1_6_4_cry_2),.O(un84_sop_0_0_0_1_6_4[3:3]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_3_cZ(.DI(un1_x_6_0[4:4]),.CI(un84_sop_0_0_0_1_6_4_cry_2),.S(un84_sop_0_0_0_1_6_4_axb_3),.LO(un84_sop_0_0_0_1_6_4_cry_3));
XORCY un84_sop_0_0_0_1_6_4_s_2(.LI(un84_sop_0_0_0_1_6_4_axb_2),.CI(un84_sop_0_0_0_1_6_4_cry_1),.O(un84_sop_0_0_0_1_6_4[2:2]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_2_cZ(.DI(un1_x_6_0[3:3]),.CI(un84_sop_0_0_0_1_6_4_cry_1),.S(un84_sop_0_0_0_1_6_4_axb_2),.LO(un84_sop_0_0_0_1_6_4_cry_2));
XORCY un84_sop_0_0_0_1_6_4_s_1(.LI(un84_sop_0_0_0_1_6_4_axb_1),.CI(un84_sop_0_0_0_1_6_4_cry_0),.O(un84_sop_0_0_0_1_6_4[1:1]));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_1_cZ(.DI(un1_x_6_0[2:2]),.CI(un84_sop_0_0_0_1_6_4_cry_0),.S(un84_sop_0_0_0_1_6_4_axb_1),.LO(un84_sop_0_0_0_1_6_4_cry_1));
MUXCY_L un84_sop_0_0_0_1_6_4_cry_0_cZ(.DI(un1_x_6_0[1:1]),.CI(GND),.S(un84_sop_0_0_0_1_6_4[0:0]),.LO(un84_sop_0_0_0_1_6_4_cry_0));
XORCY un1_x_10_s_11(.LI(un1_x_10_axb_11),.CI(un1_x_10_cry_10),.O(un1_x_10_0_0[15:15]));
XORCY un1_x_10_s_10(.LI(un1_x_10_axb_10),.CI(un1_x_10_cry_9),.O(un1_x_10_0_0[14:14]));
MUXCY_L un1_x_10_cry_10_cZ(.DI(un1_x_10_4[10:10]),.CI(un1_x_10_cry_9),.S(un1_x_10_axb_10),.LO(un1_x_10_cry_10));
XORCY un1_x_10_s_9(.LI(un1_x_10_axb_9),.CI(un1_x_10_cry_8),.O(un1_x_10_0_0[13:13]));
MUXCY_L un1_x_10_cry_9_cZ(.DI(un1_x_10_4[9:9]),.CI(un1_x_10_cry_8),.S(un1_x_10_axb_9),.LO(un1_x_10_cry_9));
XORCY un1_x_10_s_8(.LI(un1_x_10_axb_8),.CI(un1_x_10_cry_7),.O(un1_x_10_0_0[12:12]));
MUXCY_L un1_x_10_cry_8_cZ(.DI(un1_x_10_4[8:8]),.CI(un1_x_10_cry_7),.S(un1_x_10_axb_8),.LO(un1_x_10_cry_8));
XORCY un1_x_10_s_7(.LI(un1_x_10_axb_7),.CI(un1_x_10_cry_6),.O(un1_x_10_0_0[11:11]));
MUXCY_L un1_x_10_cry_7_cZ(.DI(un1_x_10_4[7:7]),.CI(un1_x_10_cry_6),.S(un1_x_10_axb_7),.LO(un1_x_10_cry_7));
XORCY un1_x_10_s_6(.LI(un1_x_10_axb_6),.CI(un1_x_10_cry_5),.O(un1_x_10_0_0[10:10]));
MUXCY_L un1_x_10_cry_6_cZ(.DI(un1_x_10_4[6:6]),.CI(un1_x_10_cry_5),.S(un1_x_10_axb_6),.LO(un1_x_10_cry_6));
XORCY un1_x_10_s_5(.LI(un1_x_10_axb_5),.CI(un1_x_10_cry_4),.O(un1_x_10_0_0[9:9]));
MUXCY_L un1_x_10_cry_5_cZ(.DI(un1_x_10_4[5:5]),.CI(un1_x_10_cry_4),.S(un1_x_10_axb_5),.LO(un1_x_10_cry_5));
XORCY un1_x_10_s_4(.LI(un1_x_10_axb_4),.CI(un1_x_10_cry_3),.O(un1_x_10_0_0[8:8]));
MUXCY_L un1_x_10_cry_4_cZ(.DI(un1_x_10_4[4:4]),.CI(un1_x_10_cry_3),.S(un1_x_10_axb_4),.LO(un1_x_10_cry_4));
MUXCY_L un1_x_10_cry_3_cZ(.DI(un1_x_10_4[3:3]),.CI(GND),.S(un1_x_10_axb_3),.LO(un1_x_10_cry_3));
XORCY un84_sop_1_6_0_s_13(.LI(un84_sop_1_6_0_axb_13),.CI(un84_sop_1_6_0_cry_12),.O(un84_sop_1_6[14:14]));
XORCY un84_sop_1_6_0_s_12(.LI(un84_sop_1_6_0_axb_12),.CI(un84_sop_1_6_0_cry_11),.O(un84_sop_1_6[12:12]));
MUXCY_L un84_sop_1_6_0_cry_12_cZ(.DI(un84_sop_1_6_0_o5_11),.CI(un84_sop_1_6_0_cry_11),.S(un84_sop_1_6_0_axb_12),.LO(un84_sop_1_6_0_cry_12));
XORCY un84_sop_1_6_0_s_11(.LI(un84_sop_1_6_0_axb_11),.CI(un84_sop_1_6_0_cry_10),.O(un84_sop_1_6[11:11]));
MUXCY_L un84_sop_1_6_0_cry_11_cZ(.DI(un84_sop_1_6_0_o5_10),.CI(un84_sop_1_6_0_cry_10),.S(un84_sop_1_6_0_axb_11),.LO(un84_sop_1_6_0_cry_11));
XORCY un84_sop_1_6_0_s_10(.LI(un84_sop_1_6_0_axb_10),.CI(un84_sop_1_6_0_cry_9),.O(un84_sop_1_6[10:10]));
MUXCY_L un84_sop_1_6_0_cry_10_cZ(.DI(un84_sop_1_6_0_o5_9),.CI(un84_sop_1_6_0_cry_9),.S(un84_sop_1_6_0_axb_10),.LO(un84_sop_1_6_0_cry_10));
XORCY un84_sop_1_6_0_s_9(.LI(un84_sop_1_6_0_axb_9),.CI(un84_sop_1_6_0_cry_8),.O(un84_sop_1_6[9:9]));
MUXCY_L un84_sop_1_6_0_cry_9_cZ(.DI(un84_sop_1_6_0_o5_8),.CI(un84_sop_1_6_0_cry_8),.S(un84_sop_1_6_0_axb_9),.LO(un84_sop_1_6_0_cry_9));
XORCY un84_sop_1_6_0_s_8(.LI(un84_sop_1_6_0_axb_8),.CI(un84_sop_1_6_0_cry_7),.O(un84_sop_1_6[8:8]));
MUXCY_L un84_sop_1_6_0_cry_8_cZ(.DI(un84_sop_1_6_0_o5_7),.CI(un84_sop_1_6_0_cry_7),.S(un84_sop_1_6_0_axb_8),.LO(un84_sop_1_6_0_cry_8));
XORCY un84_sop_1_6_0_s_7(.LI(un84_sop_1_6_0_axb_7),.CI(un84_sop_1_6_0_cry_6),.O(un84_sop_1_6[7:7]));
MUXCY_L un84_sop_1_6_0_cry_7_cZ(.DI(un84_sop_1_6_0_o5_6),.CI(un84_sop_1_6_0_cry_6),.S(un84_sop_1_6_0_axb_7),.LO(un84_sop_1_6_0_cry_7));
XORCY un84_sop_1_6_0_s_6(.LI(un84_sop_1_6_0_axb_6),.CI(un84_sop_1_6_0_cry_5),.O(un84_sop_1_6[6:6]));
MUXCY_L un84_sop_1_6_0_cry_6_cZ(.DI(un84_sop_1_6_0_o5_5),.CI(un84_sop_1_6_0_cry_5),.S(un84_sop_1_6_0_axb_6),.LO(un84_sop_1_6_0_cry_6));
XORCY un84_sop_1_6_0_s_5(.LI(un84_sop_1_6_0_axb_5),.CI(un84_sop_1_6_0_cry_4),.O(un84_sop_1_6[5:5]));
MUXCY_L un84_sop_1_6_0_cry_5_cZ(.DI(un84_sop_1_6_0_o5_4),.CI(un84_sop_1_6_0_cry_4),.S(un84_sop_1_6_0_axb_5),.LO(un84_sop_1_6_0_cry_5));
XORCY un84_sop_1_6_0_s_4(.LI(un84_sop_1_6_0_axb_4),.CI(un84_sop_1_6_0_cry_3),.O(un84_sop_1_6[4:4]));
MUXCY_L un84_sop_1_6_0_cry_4_cZ(.DI(un84_sop_1_6_0_o5_3),.CI(un84_sop_1_6_0_cry_3),.S(un84_sop_1_6_0_axb_4),.LO(un84_sop_1_6_0_cry_4));
XORCY un84_sop_1_6_0_s_3(.LI(un84_sop_1_6_0_axb_3),.CI(un84_sop_1_6_0_cry_2),.O(un84_sop_1_6[3:3]));
MUXCY_L un84_sop_1_6_0_cry_3_cZ(.DI(un84_sop_1_6_0_o5_2),.CI(un84_sop_1_6_0_cry_2),.S(un84_sop_1_6_0_axb_3),.LO(un84_sop_1_6_0_cry_3));
XORCY un84_sop_1_6_0_s_2(.LI(un84_sop_1_6_0_axb_2),.CI(un84_sop_1_6_0_cry_1),.O(un84_sop_1_6[2:2]));
MUXCY_L un84_sop_1_6_0_cry_2_cZ(.DI(un84_sop_1_6_0_axb_1_lut6_2_O5),.CI(un84_sop_1_6_0_cry_1),.S(un84_sop_1_6_0_axb_2),.LO(un84_sop_1_6_0_cry_2));
XORCY un84_sop_1_6_0_s_1(.LI(un84_sop_1_6_0_axb_1),.CI(un84_sop_1_6_0_cry_0),.O(un84_sop_1_6[1:1]));
MUXCY_L un84_sop_1_6_0_cry_1_cZ(.DI(GND),.CI(un84_sop_1_6_0_cry_0),.S(un84_sop_1_6_0_axb_1),.LO(un84_sop_1_6_0_cry_1));
MUXCY_L un84_sop_1_6_0_cry_0_cZ(.DI(un1_x_2[5:5]),.CI(un84_sop_1_6_0_cry_0_cy),.S(un84_sop_1_6_0_axb_0_0),.LO(un84_sop_1_6_0_cry_0));
XORCY un84_sop_0_0_0_1_6_8_s_11(.LI(un84_sop_0_0_0_1_6_8_axb_11),.CI(un84_sop_0_0_0_1_6_8_cry_10),.O(un84_sop_0_0_0_1_6_8[14:14]));
XORCY un84_sop_0_0_0_1_6_8_s_10(.LI(un84_sop_0_0_0_1_6_8_axb_10),.CI(un84_sop_0_0_0_1_6_8_cry_9),.O(un84_sop_0_0_0_1_6_8[13:13]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_10_cZ(.DI(un84_sop_0_0_0_10_0[13:13]),.CI(un84_sop_0_0_0_1_6_8_cry_9),.S(un84_sop_0_0_0_1_6_8_axb_10),.LO(un84_sop_0_0_0_1_6_8_cry_10));
XORCY un84_sop_0_0_0_1_6_8_s_9(.LI(un84_sop_0_0_0_1_6_8_axb_9),.CI(un84_sop_0_0_0_1_6_8_cry_8),.O(un84_sop_0_0_0_1_6_8[12:12]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_9_cZ(.DI(un84_sop_0_0_0_10_0[12:12]),.CI(un84_sop_0_0_0_1_6_8_cry_8),.S(un84_sop_0_0_0_1_6_8_axb_9),.LO(un84_sop_0_0_0_1_6_8_cry_9));
XORCY un84_sop_0_0_0_1_6_8_s_8(.LI(un84_sop_0_0_0_1_6_8_axb_8),.CI(un84_sop_0_0_0_1_6_8_cry_7),.O(un84_sop_0_0_0_1_6_8[11:11]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_8_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_7),.CI(un84_sop_0_0_0_1_6_8_cry_7),.S(un84_sop_0_0_0_1_6_8_axb_8),.LO(un84_sop_0_0_0_1_6_8_cry_8));
XORCY un84_sop_0_0_0_1_6_8_s_7(.LI(un84_sop_0_0_0_1_6_8_axb_7),.CI(un84_sop_0_0_0_1_6_8_cry_6),.O(un84_sop_0_0_0_1_6_8[10:10]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_7_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_6),.CI(un84_sop_0_0_0_1_6_8_cry_6),.S(un84_sop_0_0_0_1_6_8_axb_7),.LO(un84_sop_0_0_0_1_6_8_cry_7));
XORCY un84_sop_0_0_0_1_6_8_s_6(.LI(un84_sop_0_0_0_1_6_8_axb_6),.CI(un84_sop_0_0_0_1_6_8_cry_5),.O(un84_sop_0_0_0_1_6_8[9:9]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_6_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_5),.CI(un84_sop_0_0_0_1_6_8_cry_5),.S(un84_sop_0_0_0_1_6_8_axb_6),.LO(un84_sop_0_0_0_1_6_8_cry_6));
XORCY un84_sop_0_0_0_1_6_8_s_5(.LI(un84_sop_0_0_0_1_6_8_axb_5),.CI(un84_sop_0_0_0_1_6_8_cry_4),.O(un84_sop_0_0_0_1_6_8[8:8]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_5_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_4),.CI(un84_sop_0_0_0_1_6_8_cry_4),.S(un84_sop_0_0_0_1_6_8_axb_5),.LO(un84_sop_0_0_0_1_6_8_cry_5));
XORCY un84_sop_0_0_0_1_6_8_s_4(.LI(un84_sop_0_0_0_1_6_8_axb_4),.CI(un84_sop_0_0_0_1_6_8_cry_3),.O(un84_sop_0_0_0_1_6_8[7:7]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_4_cZ(.DI(un84_sop_0_0_0_1_6_8_o5_3),.CI(un84_sop_0_0_0_1_6_8_cry_3),.S(un84_sop_0_0_0_1_6_8_axb_4),.LO(un84_sop_0_0_0_1_6_8_cry_4));
XORCY un84_sop_0_0_0_1_6_8_s_3(.LI(un84_sop_0_0_0_1_6_8_axb_3),.CI(un84_sop_0_0_0_1_6_8_cry_2),.O(un84_sop_0_0_0_1_6_8[6:6]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_3_cZ(.DI(un84_sop_0_0_0_1_6_8_axb_2_lut6_2_O5),.CI(un84_sop_0_0_0_1_6_8_cry_2),.S(un84_sop_0_0_0_1_6_8_axb_3),.LO(un84_sop_0_0_0_1_6_8_cry_3));
XORCY un84_sop_0_0_0_1_6_8_s_2(.LI(un84_sop_0_0_0_1_6_8_axb_2),.CI(un84_sop_0_0_0_1_6_8_cry_1),.O(un84_sop_0_0_0_1_6_8[5:5]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_2_cZ(.DI(GND),.CI(un84_sop_0_0_0_1_6_8_cry_1),.S(un84_sop_0_0_0_1_6_8_axb_2),.LO(un84_sop_0_0_0_1_6_8_cry_2));
XORCY un84_sop_0_0_0_1_6_8_s_1(.LI(un84_sop_0_0_0_1_6_8_axb_1),.CI(un84_sop_0_0_0_1_6_8_cry_0),.O(un84_sop_0_0_0_1_6_8[4:4]));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_1_cZ(.DI(un84_sop_0_0_0_10_0[4:4]),.CI(un84_sop_0_0_0_1_6_8_cry_0),.S(un84_sop_0_0_0_1_6_8_axb_1),.LO(un84_sop_0_0_0_1_6_8_cry_1));
MUXCY_L un84_sop_0_0_0_1_6_8_cry_0_cZ(.DI(un84_sop_0_0_0_10_0[3:3]),.CI(GND),.S(un84_sop_0_0_0_1_6_8[3:3]),.LO(un84_sop_0_0_0_1_6_8_cry_0));
XORCY un84_sop_0_0_0_6_6_0_s_14(.LI(un84_sop_0_0_0_6_6_0_axb_14),.CI(un84_sop_0_0_0_6_6_0_cry_13),.O(un84_sop_0_0_0_1_6_6[14:14]));
XORCY un84_sop_0_0_0_6_6_0_s_13(.LI(un84_sop_0_0_0_6_6_0_axb_13),.CI(un84_sop_0_0_0_6_6_0_cry_12),.O(un84_sop_0_0_0_1_6_6[13:13]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_13_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_12),.CI(un84_sop_0_0_0_6_6_0_cry_12),.S(un84_sop_0_0_0_6_6_0_axb_13),.LO(un84_sop_0_0_0_6_6_0_cry_13));
XORCY un84_sop_0_0_0_6_6_0_s_12(.LI(un84_sop_0_0_0_6_6_0_axb_12),.CI(un84_sop_0_0_0_6_6_0_cry_11),.O(un84_sop_0_0_0_1_6_6[12:12]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_12_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_11),.CI(un84_sop_0_0_0_6_6_0_cry_11),.S(un84_sop_0_0_0_6_6_0_axb_12),.LO(un84_sop_0_0_0_6_6_0_cry_12));
XORCY un84_sop_0_0_0_6_6_0_s_11(.LI(un84_sop_0_0_0_6_6_0_axb_11),.CI(un84_sop_0_0_0_6_6_0_cry_10),.O(un84_sop_0_0_0_1_6_6[11:11]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_11_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_10),.CI(un84_sop_0_0_0_6_6_0_cry_10),.S(un84_sop_0_0_0_6_6_0_axb_11),.LO(un84_sop_0_0_0_6_6_0_cry_11));
XORCY un84_sop_0_0_0_6_6_0_s_10(.LI(un84_sop_0_0_0_6_6_0_axb_10),.CI(un84_sop_0_0_0_6_6_0_cry_9),.O(un84_sop_0_0_0_1_6_6[10:10]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_10_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_9),.CI(un84_sop_0_0_0_6_6_0_cry_9),.S(un84_sop_0_0_0_6_6_0_axb_10),.LO(un84_sop_0_0_0_6_6_0_cry_10));
XORCY un84_sop_0_0_0_6_6_0_s_9(.LI(un84_sop_0_0_0_6_6_0_axb_9),.CI(un84_sop_0_0_0_6_6_0_cry_8),.O(un84_sop_0_0_0_1_6_6[9:9]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_9_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_8),.CI(un84_sop_0_0_0_6_6_0_cry_8),.S(un84_sop_0_0_0_6_6_0_axb_9),.LO(un84_sop_0_0_0_6_6_0_cry_9));
XORCY un84_sop_0_0_0_6_6_0_s_8(.LI(un84_sop_0_0_0_6_6_0_axb_8),.CI(un84_sop_0_0_0_6_6_0_cry_7),.O(un84_sop_0_0_0_1_6_6[8:8]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_8_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_7),.CI(un84_sop_0_0_0_6_6_0_cry_7),.S(un84_sop_0_0_0_6_6_0_axb_8),.LO(un84_sop_0_0_0_6_6_0_cry_8));
XORCY un84_sop_0_0_0_6_6_0_s_7(.LI(un84_sop_0_0_0_6_6_0_axb_7),.CI(un84_sop_0_0_0_6_6_0_cry_6),.O(un84_sop_0_0_0_1_6_6[7:7]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_7_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_6),.CI(un84_sop_0_0_0_6_6_0_cry_6),.S(un84_sop_0_0_0_6_6_0_axb_7),.LO(un84_sop_0_0_0_6_6_0_cry_7));
XORCY un84_sop_0_0_0_6_6_0_s_6(.LI(un84_sop_0_0_0_6_6_0_axb_6),.CI(un84_sop_0_0_0_6_6_0_cry_5),.O(un84_sop_0_0_0_1_6_6[6:6]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_6_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_5),.CI(un84_sop_0_0_0_6_6_0_cry_5),.S(un84_sop_0_0_0_6_6_0_axb_6),.LO(un84_sop_0_0_0_6_6_0_cry_6));
XORCY un84_sop_0_0_0_6_6_0_s_5(.LI(un84_sop_0_0_0_6_6_0_axb_5),.CI(un84_sop_0_0_0_6_6_0_cry_4),.O(un84_sop_0_0_0_1_6_6[5:5]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_5_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_4),.CI(un84_sop_0_0_0_6_6_0_cry_4),.S(un84_sop_0_0_0_6_6_0_axb_5),.LO(un84_sop_0_0_0_6_6_0_cry_5));
XORCY un84_sop_0_0_0_6_6_0_s_4(.LI(un84_sop_0_0_0_6_6_0_axb_4),.CI(un84_sop_0_0_0_6_6_0_cry_3),.O(un84_sop_0_0_0_1_6_6[4:4]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_4_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_3),.CI(un84_sop_0_0_0_6_6_0_cry_3),.S(un84_sop_0_0_0_6_6_0_axb_4),.LO(un84_sop_0_0_0_6_6_0_cry_4));
XORCY un84_sop_0_0_0_6_6_0_s_3(.LI(un84_sop_0_0_0_6_6_0_axb_3),.CI(un84_sop_0_0_0_6_6_0_cry_2),.O(un84_sop_0_0_0_1_6_6[3:3]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_3_cZ(.DI(un84_sop_0_0_0_6_6_0_o5_2),.CI(un84_sop_0_0_0_6_6_0_cry_2),.S(un84_sop_0_0_0_6_6_0_axb_3),.LO(un84_sop_0_0_0_6_6_0_cry_3));
XORCY un84_sop_0_0_0_6_6_0_s_2(.LI(un84_sop_0_0_0_6_6_0_axb_2),.CI(un84_sop_0_0_0_6_6_0_cry_1),.O(un84_sop_0_0_0_1_6_6[2:2]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_2_cZ(.DI(un84_sop_0_0_0_6_6_0_axb_1_lut6_2_O5),.CI(un84_sop_0_0_0_6_6_0_cry_1),.S(un84_sop_0_0_0_6_6_0_axb_2),.LO(un84_sop_0_0_0_6_6_0_cry_2));
XORCY un84_sop_0_0_0_6_6_0_s_1(.LI(un84_sop_0_0_0_6_6_0_axb_1),.CI(un84_sop_0_0_0_6_6_0_cry_0),.O(un84_sop_0_0_0_1_6_6[1:1]));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_1_cZ(.DI(GND),.CI(un84_sop_0_0_0_6_6_0_cry_0),.S(un84_sop_0_0_0_6_6_0_axb_1),.LO(un84_sop_0_0_0_6_6_0_cry_1));
MUXCY_L un84_sop_0_0_0_6_6_0_cry_0_cZ(.DI(un1_x_8_0[4:4]),.CI(un84_sop_0_0_0_6_6_0_cry_0_cy),.S(un84_sop_0_0_0_6_0_axb_0_1),.LO(un84_sop_0_0_0_6_6_0_cry_0));
XORCY un84_sop_0_0_0_11_0_s_14(.LI(un84_sop_0_0_0_11_0_axb_14),.CI(un84_sop_0_0_0_11_0_cry_13),.O(un84_sop_0_0_0_0_8[14:14]));
XORCY un84_sop_0_0_0_11_0_s_13(.LI(un84_sop_0_0_0_11_0_axb_13),.CI(un84_sop_0_0_0_11_0_cry_12),.O(un84_sop_0_0_0_0_8[13:13]));
MUXCY_L un84_sop_0_0_0_11_0_cry_13_cZ(.DI(un84_sop_0_0_0_11_0_o5_12),.CI(un84_sop_0_0_0_11_0_cry_12),.S(un84_sop_0_0_0_11_0_axb_13),.LO(un84_sop_0_0_0_11_0_cry_13));
XORCY un84_sop_0_0_0_11_0_s_12(.LI(un84_sop_0_0_0_11_0_axb_12),.CI(un84_sop_0_0_0_11_0_cry_11),.O(un84_sop_0_0_0_0_8[12:12]));
MUXCY_L un84_sop_0_0_0_11_0_cry_12_cZ(.DI(un84_sop_0_0_0_11_0_o5_11),.CI(un84_sop_0_0_0_11_0_cry_11),.S(un84_sop_0_0_0_11_0_axb_12),.LO(un84_sop_0_0_0_11_0_cry_12));
XORCY un84_sop_0_0_0_11_0_s_11(.LI(un84_sop_0_0_0_11_0_axb_11),.CI(un84_sop_0_0_0_11_0_cry_10),.O(un84_sop_0_0_0_0_8[11:11]));
MUXCY_L un84_sop_0_0_0_11_0_cry_11_cZ(.DI(un84_sop_0_0_0_11_0_o5_10),.CI(un84_sop_0_0_0_11_0_cry_10),.S(un84_sop_0_0_0_11_0_axb_11),.LO(un84_sop_0_0_0_11_0_cry_11));
XORCY un84_sop_0_0_0_11_0_s_10(.LI(un84_sop_0_0_0_11_0_axb_10),.CI(un84_sop_0_0_0_11_0_cry_9),.O(un84_sop_0_0_0_0_8[10:10]));
MUXCY_L un84_sop_0_0_0_11_0_cry_10_cZ(.DI(un84_sop_0_0_0_11_0_o5_9),.CI(un84_sop_0_0_0_11_0_cry_9),.S(un84_sop_0_0_0_11_0_axb_10),.LO(un84_sop_0_0_0_11_0_cry_10));
XORCY un84_sop_0_0_0_11_0_s_9(.LI(un84_sop_0_0_0_11_0_axb_9),.CI(un84_sop_0_0_0_11_0_cry_8),.O(un84_sop_0_0_0_0_8[9:9]));
MUXCY_L un84_sop_0_0_0_11_0_cry_9_cZ(.DI(un84_sop_0_0_0_11_0_o5_8),.CI(un84_sop_0_0_0_11_0_cry_8),.S(un84_sop_0_0_0_11_0_axb_9),.LO(un84_sop_0_0_0_11_0_cry_9));
XORCY un84_sop_0_0_0_11_0_s_8(.LI(un84_sop_0_0_0_11_0_axb_8),.CI(un84_sop_0_0_0_11_0_cry_7),.O(un84_sop_0_0_0_0_8[8:8]));
MUXCY_L un84_sop_0_0_0_11_0_cry_8_cZ(.DI(un84_sop_0_0_0_11_0_o5_7),.CI(un84_sop_0_0_0_11_0_cry_7),.S(un84_sop_0_0_0_11_0_axb_8),.LO(un84_sop_0_0_0_11_0_cry_8));
XORCY un84_sop_0_0_0_11_0_s_7(.LI(un84_sop_0_0_0_11_0_axb_7),.CI(un84_sop_0_0_0_11_0_cry_6),.O(un84_sop_0_0_0_0_8[7:7]));
MUXCY_L un84_sop_0_0_0_11_0_cry_7_cZ(.DI(un84_sop_0_0_0_11_0_o5_6),.CI(un84_sop_0_0_0_11_0_cry_6),.S(un84_sop_0_0_0_11_0_axb_7),.LO(un84_sop_0_0_0_11_0_cry_7));
XORCY un84_sop_0_0_0_11_0_s_6(.LI(un84_sop_0_0_0_11_0_axb_6),.CI(un84_sop_0_0_0_11_0_cry_5),.O(un84_sop_0_0_0_0_8[6:6]));
MUXCY_L un84_sop_0_0_0_11_0_cry_6_cZ(.DI(un84_sop_0_0_0_11_0_o5_5),.CI(un84_sop_0_0_0_11_0_cry_5),.S(un84_sop_0_0_0_11_0_axb_6),.LO(un84_sop_0_0_0_11_0_cry_6));
XORCY un84_sop_0_0_0_11_0_s_5(.LI(un84_sop_0_0_0_11_0_axb_5),.CI(un84_sop_0_0_0_11_0_cry_4),.O(un84_sop_0_0_0_0_8[5:5]));
MUXCY_L un84_sop_0_0_0_11_0_cry_5_cZ(.DI(un84_sop_0_0_0_11_0_o5_4),.CI(un84_sop_0_0_0_11_0_cry_4),.S(un84_sop_0_0_0_11_0_axb_5),.LO(un84_sop_0_0_0_11_0_cry_5));
XORCY un84_sop_0_0_0_11_0_s_4(.LI(un84_sop_0_0_0_11_0_axb_4),.CI(un84_sop_0_0_0_11_0_cry_3),.O(un84_sop_0_0_0_0_8[4:4]));
MUXCY_L un84_sop_0_0_0_11_0_cry_4_cZ(.DI(un84_sop_0_0_0_11_0_o5_3),.CI(un84_sop_0_0_0_11_0_cry_3),.S(un84_sop_0_0_0_11_0_axb_4),.LO(un84_sop_0_0_0_11_0_cry_4));
XORCY un84_sop_0_0_0_11_0_s_3(.LI(un84_sop_0_0_0_11_0_axb_3),.CI(un84_sop_0_0_0_11_0_cry_2),.O(un84_sop_0_0_0_0_8[3:3]));
MUXCY_L un84_sop_0_0_0_11_0_cry_3_cZ(.DI(un84_sop_0_0_0_11_0_o5_2),.CI(un84_sop_0_0_0_11_0_cry_2),.S(un84_sop_0_0_0_11_0_axb_3),.LO(un84_sop_0_0_0_11_0_cry_3));
XORCY un84_sop_0_0_0_11_0_s_2(.LI(un84_sop_0_0_0_11_0_axb_2),.CI(un84_sop_0_0_0_11_0_cry_1),.O(un84_sop_0_0_0_0_8[2:2]));
MUXCY_L un84_sop_0_0_0_11_0_cry_2_cZ(.DI(un84_sop_0_0_0_11_0_cry_2_RNO),.CI(un84_sop_0_0_0_11_0_cry_1),.S(un84_sop_0_0_0_11_0_axb_2),.LO(un84_sop_0_0_0_11_0_cry_2));
XORCY un84_sop_0_0_0_11_0_s_1(.LI(un84_sop_0_0_0_11_0_axb_1),.CI(un84_sop_0_0_0_11_0_cry_0),.O(un84_sop_0_0_0_0_8[1:1]));
MUXCY_L un84_sop_0_0_0_11_0_cry_1_cZ(.DI(un84_sop_0_0_0_0_11_6[1:1]),.CI(un84_sop_0_0_0_11_0_cry_0),.S(un84_sop_0_0_0_11_0_axb_1),.LO(un84_sop_0_0_0_11_0_cry_1));
XORCY un84_sop_0_0_0_11_0_s_0(.LI(un84_sop_0_0_0_11_0_axb_0),.CI(un84_sop_0_0_0_11_0_cry_0_cy),.O(un84_sop_0_0_0_0_8[0:0]));
MUXCY_L un84_sop_0_0_0_11_0_cry_0_cZ(.DI(un84_sop_0_0_0_0_11_6[0:0]),.CI(un84_sop_0_0_0_11_0_cry_0_cy),.S(un84_sop_0_0_0_11_0_axb_0),.LO(un84_sop_0_0_0_11_0_cry_0));
XORCY un84_sop_0_0_0_11_6_0_s_13(.LI(un84_sop_0_0_0_11_6_0_axb_13),.CI(un84_sop_0_0_0_11_6_0_cry_12),.O(un84_sop_0_0_0_0_11_6[14:14]));
XORCY un84_sop_0_0_0_11_6_0_s_12(.LI(un84_sop_0_0_0_11_6_0_axb_12),.CI(un84_sop_0_0_0_11_6_0_cry_11),.O(un84_sop_0_0_0_0_11_6[12:12]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_12_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_11),.CI(un84_sop_0_0_0_11_6_0_cry_11),.S(un84_sop_0_0_0_11_6_0_axb_12),.LO(un84_sop_0_0_0_11_6_0_cry_12));
XORCY un84_sop_0_0_0_11_6_0_s_11(.LI(un84_sop_0_0_0_11_6_0_axb_11),.CI(un84_sop_0_0_0_11_6_0_cry_10),.O(un84_sop_0_0_0_0_11_6[11:11]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_11_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_10),.CI(un84_sop_0_0_0_11_6_0_cry_10),.S(un84_sop_0_0_0_11_6_0_axb_11),.LO(un84_sop_0_0_0_11_6_0_cry_11));
XORCY un84_sop_0_0_0_11_6_0_s_10(.LI(un84_sop_0_0_0_11_6_0_axb_10),.CI(un84_sop_0_0_0_11_6_0_cry_9),.O(un84_sop_0_0_0_0_11_6[10:10]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_10_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_9),.CI(un84_sop_0_0_0_11_6_0_cry_9),.S(un84_sop_0_0_0_11_6_0_axb_10),.LO(un84_sop_0_0_0_11_6_0_cry_10));
XORCY un84_sop_0_0_0_11_6_0_s_9(.LI(un84_sop_0_0_0_11_6_0_axb_9),.CI(un84_sop_0_0_0_11_6_0_cry_8),.O(un84_sop_0_0_0_0_11_6[9:9]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_9_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_8),.CI(un84_sop_0_0_0_11_6_0_cry_8),.S(un84_sop_0_0_0_11_6_0_axb_9),.LO(un84_sop_0_0_0_11_6_0_cry_9));
XORCY un84_sop_0_0_0_11_6_0_s_8(.LI(un84_sop_0_0_0_11_6_0_axb_8),.CI(un84_sop_0_0_0_11_6_0_cry_7),.O(un84_sop_0_0_0_0_11_6[8:8]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_8_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_7),.CI(un84_sop_0_0_0_11_6_0_cry_7),.S(un84_sop_0_0_0_11_6_0_axb_8),.LO(un84_sop_0_0_0_11_6_0_cry_8));
XORCY un84_sop_0_0_0_11_6_0_s_7(.LI(un84_sop_0_0_0_11_6_0_axb_7),.CI(un84_sop_0_0_0_11_6_0_cry_6),.O(un84_sop_0_0_0_0_11_6[7:7]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_7_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_6),.CI(un84_sop_0_0_0_11_6_0_cry_6),.S(un84_sop_0_0_0_11_6_0_axb_7),.LO(un84_sop_0_0_0_11_6_0_cry_7));
XORCY un84_sop_0_0_0_11_6_0_s_6(.LI(un84_sop_0_0_0_11_6_0_axb_6),.CI(un84_sop_0_0_0_11_6_0_cry_5),.O(un84_sop_0_0_0_0_11_6[6:6]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_6_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_5),.CI(un84_sop_0_0_0_11_6_0_cry_5),.S(un84_sop_0_0_0_11_6_0_axb_6),.LO(un84_sop_0_0_0_11_6_0_cry_6));
XORCY un84_sop_0_0_0_11_6_0_s_5(.LI(un84_sop_0_0_0_11_6_0_axb_5),.CI(un84_sop_0_0_0_11_6_0_cry_4),.O(un84_sop_0_0_0_0_11_6[5:5]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_5_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_4),.CI(un84_sop_0_0_0_11_6_0_cry_4),.S(un84_sop_0_0_0_11_6_0_axb_5),.LO(un84_sop_0_0_0_11_6_0_cry_5));
XORCY un84_sop_0_0_0_11_6_0_s_4(.LI(un84_sop_0_0_0_11_6_0_axb_4),.CI(un84_sop_0_0_0_11_6_0_cry_3),.O(un84_sop_0_0_0_0_11_6[4:4]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_4_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_3),.CI(un84_sop_0_0_0_11_6_0_cry_3),.S(un84_sop_0_0_0_11_6_0_axb_4),.LO(un84_sop_0_0_0_11_6_0_cry_4));
XORCY un84_sop_0_0_0_11_6_0_s_3(.LI(un84_sop_0_0_0_11_6_0_axb_3),.CI(un84_sop_0_0_0_11_6_0_cry_2),.O(un84_sop_0_0_0_0_11_6[3:3]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_3_cZ(.DI(un84_sop_0_0_0_11_6_0_o5_2),.CI(un84_sop_0_0_0_11_6_0_cry_2),.S(un84_sop_0_0_0_11_6_0_axb_3),.LO(un84_sop_0_0_0_11_6_0_cry_3));
XORCY un84_sop_0_0_0_11_6_0_s_2(.LI(un84_sop_0_0_0_11_6_0_axb_2),.CI(un84_sop_0_0_0_11_6_0_cry_1),.O(un84_sop_0_0_0_0_11_6[2:2]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_2_cZ(.DI(un84_sop_0_0_0_11_6_0_axb_1_lut6_2_O5),.CI(un84_sop_0_0_0_11_6_0_cry_1),.S(un84_sop_0_0_0_11_6_0_axb_2),.LO(un84_sop_0_0_0_11_6_0_cry_2));
XORCY un84_sop_0_0_0_11_6_0_s_1(.LI(un84_sop_0_0_0_11_6_0_axb_1),.CI(un84_sop_0_0_0_11_6_0_cry_0),.O(un84_sop_0_0_0_0_11_6[1:1]));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_1_cZ(.DI(GND),.CI(un84_sop_0_0_0_11_6_0_cry_0),.S(un84_sop_0_0_0_11_6_0_axb_1),.LO(un84_sop_0_0_0_11_6_0_cry_1));
MUXCY_L un84_sop_0_0_0_11_6_0_cry_0_cZ(.DI(un1_x_13_0_0[5:5]),.CI(un84_sop_0_0_0_11_6_0_cry_0_cy),.S(un84_sop_0_0_0_6_0_axb_0_0),.LO(un84_sop_0_0_0_11_6_0_cry_0));
DSP48E1 desc57(.ACOUT(ACOUT[29:0]),.BCOUT({x_0_10[7:7],x_0_9[7:7],x_0_8[7:7],x_0_7[7:7],x_0_6[7:7],x_0_5[7:7],x_0_4[7:7],x_0_3[7:7],x_0_2[7:7],x_0_1[7:7],x_0_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT),.CARRYOUT(CARRYOUT[3:0]),.MULTSIGNOUT(MULTSIGNOUT),.OVERFLOW(OVERFLOW),.P({P_uc[47:12],un1_x_1[15:4]}),.PATTERNBDETECT(PATTERNBDETECT),.PATTERNDETECT(PATTERNDETECT),.PCOUT(PCOUT[47:0]),.UNDERFLOW(UNDERFLOW),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:7],x_in[7:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc57.ACASCREG=0;
defparam desc57.ADREG=0;
defparam desc57.ALUMODEREG=0;
defparam desc57.AREG=0;
defparam desc57.AUTORESET_PATDET="NO_RESET";
defparam desc57.A_INPUT="DIRECT";
defparam desc57.BCASCREG=1;
defparam desc57.BREG=1;
defparam desc57.B_INPUT="DIRECT";
defparam desc57.CARRYINREG=0;
defparam desc57.CARRYINSELREG=0;
defparam desc57.CREG=1;
defparam desc57.DREG=0;
defparam desc57.INMODEREG=0;
defparam desc57.MREG=0;
defparam desc57.OPMODEREG=0;
defparam desc57.PREG=1;
defparam desc57.USE_DPORT="FALSE";
defparam desc57.USE_MULT="MULTIPLY";
defparam desc57.USE_SIMD="ONE48";
DSP48E1 desc58(.ACOUT(ACOUT_0[29:0]),.BCOUT({x_9_10[7:7],x_9_9[7:7],x_9_8[7:7],x_9_7[7:7],x_9_6[7:7],x_9_5[7:7],x_9_4[7:7],x_9_3[7:7],x_9_2[7:7],x_9_1[7:7],x_9_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_0),.CARRYOUT(CARRYOUT_0[3:0]),.MULTSIGNOUT(MULTSIGNOUT_0),.OVERFLOW(OVERFLOW_0),.P({P_uc_0[47:12],un1_x_12_0_0[15:4]}),.PATTERNBDETECT(PATTERNBDETECT_0),.PATTERNDETECT(PATTERNDETECT_0),.PCOUT(PCOUT_0[47:0]),.UNDERFLOW(UNDERFLOW_0),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:7],x_7[7:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(VCC),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(VCC),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc58.ACASCREG=2;
defparam desc58.ADREG=0;
defparam desc58.ALUMODEREG=0;
defparam desc58.AREG=2;
defparam desc58.AUTORESET_PATDET="NO_RESET";
defparam desc58.A_INPUT="DIRECT";
defparam desc58.BCASCREG=2;
defparam desc58.BREG=2;
defparam desc58.B_INPUT="DIRECT";
defparam desc58.CARRYINREG=0;
defparam desc58.CARRYINSELREG=0;
defparam desc58.CREG=1;
defparam desc58.DREG=0;
defparam desc58.INMODEREG=0;
defparam desc58.MREG=0;
defparam desc58.OPMODEREG=0;
defparam desc58.PREG=1;
defparam desc58.USE_DPORT="FALSE";
defparam desc58.USE_MULT="MULTIPLY";
defparam desc58.USE_SIMD="ONE48";
DSP48E1 desc59(.ACOUT(ACOUT_1[29:0]),.BCOUT(BCOUT_1[17:0]),.CARRYCASCOUT(CARRYCASCOUT_1),.CARRYOUT(CARRYOUT_1[3:0]),.MULTSIGNOUT(MULTSIGNOUT_1),.OVERFLOW(OVERFLOW_1),.P({P_uc_1[47:12],un1_x_14_0_0[15:4]}),.PATTERNBDETECT(PATTERNBDETECT_1),.PATTERNDETECT(PATTERNDETECT_1),.PCOUT(PCOUT_1[47:0]),.UNDERFLOW(UNDERFLOW_1),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_10_10[7:7],x_10_9[7:7],x_10_8[7:7],x_10_7[7:7],x_10_6[7:7],x_10_5[7:7],x_10_4[7:7],x_10_3[7:7],x_10_2[7:7],x_10_1[7:7],x_10_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc59.ACASCREG=0;
defparam desc59.ADREG=0;
defparam desc59.ALUMODEREG=0;
defparam desc59.AREG=0;
defparam desc59.AUTORESET_PATDET="NO_RESET";
defparam desc59.A_INPUT="DIRECT";
defparam desc59.BCASCREG=1;
defparam desc59.BREG=1;
defparam desc59.B_INPUT="CASCADE";
defparam desc59.CARRYINREG=0;
defparam desc59.CARRYINSELREG=0;
defparam desc59.CREG=1;
defparam desc59.DREG=0;
defparam desc59.INMODEREG=0;
defparam desc59.MREG=0;
defparam desc59.OPMODEREG=0;
defparam desc59.PREG=1;
defparam desc59.USE_DPORT="FALSE";
defparam desc59.USE_MULT="MULTIPLY";
defparam desc59.USE_SIMD="ONE48";
DSP48E1 desc60(.ACOUT(ACOUT_2[29:0]),.BCOUT({x_2_10[7:7],x_2_9[7:7],x_2_8[7:7],x_2_7[7:7],x_2_6[7:7],x_2_5[7:7],x_2_4[7:7],x_2_3[7:7],x_2_2[7:7],x_2_1[7:7],x_2_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_2),.CARRYOUT(CARRYOUT_2[3:0]),.MULTSIGNOUT(MULTSIGNOUT_2),.OVERFLOW(OVERFLOW_2),.P({P_uc_2[47:12],un1_x_3[15:4]}),.PATTERNBDETECT(PATTERNBDETECT_2),.PATTERNDETECT(PATTERNDETECT_2),.PCOUT(PCOUT_2[47:0]),.UNDERFLOW(UNDERFLOW_2),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_1_10[7:7],x_1_9[7:7],x_1_8[7:7],x_1_7[7:7],x_1_6[7:7],x_1_5[7:7],x_1_4[7:7],x_1_3[7:7],x_1_2[7:7],x_1_1[7:7],x_1_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc60.ACASCREG=0;
defparam desc60.ADREG=0;
defparam desc60.ALUMODEREG=0;
defparam desc60.AREG=0;
defparam desc60.AUTORESET_PATDET="NO_RESET";
defparam desc60.A_INPUT="DIRECT";
defparam desc60.BCASCREG=1;
defparam desc60.BREG=1;
defparam desc60.B_INPUT="CASCADE";
defparam desc60.CARRYINREG=0;
defparam desc60.CARRYINSELREG=0;
defparam desc60.CREG=1;
defparam desc60.DREG=0;
defparam desc60.INMODEREG=0;
defparam desc60.MREG=0;
defparam desc60.OPMODEREG=0;
defparam desc60.PREG=1;
defparam desc60.USE_DPORT="FALSE";
defparam desc60.USE_MULT="MULTIPLY";
defparam desc60.USE_SIMD="ONE48";
DSP48E1 desc61(.ACOUT(ACOUT_3[29:0]),.BCOUT({x_6_10[7:7],x_6_9[7:7],x_6_8[7:7],x_6_7[7:7],x_6_6[7:7],x_6_5[7:7],x_6_4[7:7],x_6_3[7:7],x_6_2[7:7],x_6_1[7:7],x_6_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_3),.CARRYOUT(CARRYOUT_3[3:0]),.MULTSIGNOUT(MULTSIGNOUT_3),.OVERFLOW(OVERFLOW_3),.P({P_uc_3[47:12],un1_x_8_0[15:4]}),.PATTERNBDETECT(PATTERNBDETECT_3),.PATTERNDETECT(PATTERNDETECT_3),.PCOUT(PCOUT_3[47:0]),.UNDERFLOW(UNDERFLOW_3),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_5_10[7:7],x_5_9[7:7],x_5_8[7:7],x_5_7[7:7],x_5_6[7:7],x_5_5[7:7],x_5_4[7:7],x_5_3[7:7],x_5_2[7:7],x_5_1[7:7],x_5_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc61.ACASCREG=0;
defparam desc61.ADREG=0;
defparam desc61.ALUMODEREG=0;
defparam desc61.AREG=0;
defparam desc61.AUTORESET_PATDET="NO_RESET";
defparam desc61.A_INPUT="DIRECT";
defparam desc61.BCASCREG=1;
defparam desc61.BREG=1;
defparam desc61.B_INPUT="CASCADE";
defparam desc61.CARRYINREG=0;
defparam desc61.CARRYINSELREG=0;
defparam desc61.CREG=1;
defparam desc61.DREG=0;
defparam desc61.INMODEREG=0;
defparam desc61.MREG=0;
defparam desc61.OPMODEREG=0;
defparam desc61.PREG=1;
defparam desc61.USE_DPORT="FALSE";
defparam desc61.USE_MULT="MULTIPLY";
defparam desc61.USE_SIMD="ONE48";
DSP48E1 desc62(.ACOUT(ACOUT_4[29:0]),.BCOUT({x_4_10[7:7],x_4_9[7:7],x_4_8[7:7],x_4_7[7:7],x_4_6[7:7],x_4_5[7:7],x_4_4[7:7],x_4_3[7:7],x_4_2[7:7],x_4_1[7:7],x_4_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_4),.CARRYOUT(CARRYOUT_4[3:0]),.MULTSIGNOUT(MULTSIGNOUT_4),.OVERFLOW(OVERFLOW_4),.P({P_uc_4[47:15],un1_x_6_0[15:1]}),.PATTERNBDETECT(PATTERNBDETECT_4),.PATTERNDETECT(PATTERNDETECT_4),.PCOUT(PCOUT_4[47:0]),.UNDERFLOW(UNDERFLOW_4),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,GND,VCC,GND,GND,GND}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_3_10[7:7],x_3_9[7:7],x_3_8[7:7],x_3_7[7:7],x_3_6[7:7],x_3_5[7:7],x_3_4[7:7],x_3_3[7:7],x_3_2[7:7],x_3_1[7:7],x_3_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc62.ACASCREG=0;
defparam desc62.ADREG=0;
defparam desc62.ALUMODEREG=0;
defparam desc62.AREG=0;
defparam desc62.AUTORESET_PATDET="NO_RESET";
defparam desc62.A_INPUT="DIRECT";
defparam desc62.BCASCREG=1;
defparam desc62.BREG=1;
defparam desc62.B_INPUT="CASCADE";
defparam desc62.CARRYINREG=0;
defparam desc62.CARRYINSELREG=0;
defparam desc62.CREG=1;
defparam desc62.DREG=0;
defparam desc62.INMODEREG=0;
defparam desc62.MREG=0;
defparam desc62.OPMODEREG=0;
defparam desc62.PREG=1;
defparam desc62.USE_DPORT="FALSE";
defparam desc62.USE_MULT="MULTIPLY";
defparam desc62.USE_SIMD="ONE48";
DSP48E1 desc63(.ACOUT(ACOUT_5[29:0]),.BCOUT({x_3_10[7:7],x_3_9[7:7],x_3_8[7:7],x_3_7[7:7],x_3_6[7:7],x_3_5[7:7],x_3_4[7:7],x_3_3[7:7],x_3_2[7:7],x_3_1[7:7],x_3_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_5),.CARRYOUT(CARRYOUT_5[3:0]),.MULTSIGNOUT(MULTSIGNOUT_5),.OVERFLOW(OVERFLOW_5),.P({P_uc_5[47:15],P_uc_4[14:14],un1_x_4[15:2]}),.PATTERNBDETECT(PATTERNBDETECT_5),.PATTERNDETECT(PATTERNDETECT_5),.PCOUT(PCOUT_5[47:0]),.UNDERFLOW(UNDERFLOW_5),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,GND,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_2_10[7:7],x_2_9[7:7],x_2_8[7:7],x_2_7[7:7],x_2_6[7:7],x_2_5[7:7],x_2_4[7:7],x_2_3[7:7],x_2_2[7:7],x_2_1[7:7],x_2_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc63.ACASCREG=0;
defparam desc63.ADREG=0;
defparam desc63.ALUMODEREG=0;
defparam desc63.AREG=0;
defparam desc63.AUTORESET_PATDET="NO_RESET";
defparam desc63.A_INPUT="DIRECT";
defparam desc63.BCASCREG=1;
defparam desc63.BREG=1;
defparam desc63.B_INPUT="CASCADE";
defparam desc63.CARRYINREG=0;
defparam desc63.CARRYINSELREG=0;
defparam desc63.CREG=1;
defparam desc63.DREG=0;
defparam desc63.INMODEREG=0;
defparam desc63.MREG=0;
defparam desc63.OPMODEREG=0;
defparam desc63.PREG=1;
defparam desc63.USE_DPORT="FALSE";
defparam desc63.USE_MULT="MULTIPLY";
defparam desc63.USE_SIMD="ONE48";
DSP48E1 desc64(.ACOUT(ACOUT_6[29:0]),.BCOUT({x_5_10[7:7],x_5_9[7:7],x_5_8[7:7],x_5_7[7:7],x_5_6[7:7],x_5_5[7:7],x_5_4[7:7],x_5_3[7:7],x_5_2[7:7],x_5_1[7:7],x_5_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_6),.CARRYOUT(CARRYOUT_6[3:0]),.MULTSIGNOUT(MULTSIGNOUT_6),.OVERFLOW(OVERFLOW_6),.P({P_uc_6[47:15],P_uc_5[14:14],un1_x_7_0[15:2]}),.PATTERNBDETECT(PATTERNBDETECT_6),.PATTERNDETECT(PATTERNDETECT_6),.PCOUT(PCOUT_6[47:0]),.UNDERFLOW(UNDERFLOW_6),.A({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,VCC,GND,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_4_10[7:7],x_4_9[7:7],x_4_8[7:7],x_4_7[7:7],x_4_6[7:7],x_4_5[7:7],x_4_4[7:7],x_4_3[7:7],x_4_2[7:7],x_4_1[7:7],x_4_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc64.ACASCREG=0;
defparam desc64.ADREG=0;
defparam desc64.ALUMODEREG=0;
defparam desc64.AREG=0;
defparam desc64.AUTORESET_PATDET="NO_RESET";
defparam desc64.A_INPUT="DIRECT";
defparam desc64.BCASCREG=1;
defparam desc64.BREG=1;
defparam desc64.B_INPUT="CASCADE";
defparam desc64.CARRYINREG=0;
defparam desc64.CARRYINSELREG=0;
defparam desc64.CREG=1;
defparam desc64.DREG=0;
defparam desc64.INMODEREG=0;
defparam desc64.MREG=0;
defparam desc64.OPMODEREG=0;
defparam desc64.PREG=1;
defparam desc64.USE_DPORT="FALSE";
defparam desc64.USE_MULT="MULTIPLY";
defparam desc64.USE_SIMD="ONE48";
DSP48E1 desc65(.ACOUT(ACOUT_7[29:0]),.BCOUT({x_10_10[7:7],x_10_9[7:7],x_10_8[7:7],x_10_7[7:7],x_10_6[7:7],x_10_5[7:7],x_10_4[7:7],x_10_3[7:7],x_10_2[7:7],x_10_1[7:7],x_10_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_7),.CARRYOUT(CARRYOUT_7[3:0]),.MULTSIGNOUT(MULTSIGNOUT_7),.OVERFLOW(OVERFLOW_7),.P({P_uc_7[47:15],P_uc_6[14:14],P_uc_4[13:12],P_uc[11:11],un1_x_13_0_0[15:5]}),.PATTERNBDETECT(PATTERNBDETECT_7),.PATTERNDETECT(PATTERNDETECT_7),.PCOUT(PCOUT_7[47:0]),.UNDERFLOW(UNDERFLOW_7),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_9_10[7:7],x_9_9[7:7],x_9_8[7:7],x_9_7[7:7],x_9_6[7:7],x_9_5[7:7],x_9_4[7:7],x_9_3[7:7],x_9_2[7:7],x_9_1[7:7],x_9_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc65.ACASCREG=0;
defparam desc65.ADREG=0;
defparam desc65.ALUMODEREG=0;
defparam desc65.AREG=0;
defparam desc65.AUTORESET_PATDET="NO_RESET";
defparam desc65.A_INPUT="DIRECT";
defparam desc65.BCASCREG=1;
defparam desc65.BREG=1;
defparam desc65.B_INPUT="CASCADE";
defparam desc65.CARRYINREG=0;
defparam desc65.CARRYINSELREG=0;
defparam desc65.CREG=1;
defparam desc65.DREG=0;
defparam desc65.INMODEREG=0;
defparam desc65.MREG=0;
defparam desc65.OPMODEREG=0;
defparam desc65.PREG=1;
defparam desc65.USE_DPORT="FALSE";
defparam desc65.USE_MULT="MULTIPLY";
defparam desc65.USE_SIMD="ONE48";
DSP48E1 desc66(.ACOUT(ACOUT_8[29:0]),.BCOUT({x_1_10[7:7],x_1_9[7:7],x_1_8[7:7],x_1_7[7:7],x_1_6[7:7],x_1_5[7:7],x_1_4[7:7],x_1_3[7:7],x_1_2[7:7],x_1_1[7:7],x_1_0[7:0]}),.CARRYCASCOUT(CARRYCASCOUT_8),.CARRYOUT(CARRYOUT_8[3:0]),.MULTSIGNOUT(MULTSIGNOUT_8),.OVERFLOW(OVERFLOW_8),.P({P_uc_8[47:15],P_uc_7[14:14],P_uc_5[13:12],P_uc_0[11:11],un1_x_2[15:5]}),.PATTERNBDETECT(PATTERNBDETECT_8),.PATTERNDETECT(PATTERNDETECT_8),.PCOUT(PCOUT_8[47:0]),.UNDERFLOW(UNDERFLOW_8),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_0_10[7:7],x_0_9[7:7],x_0_8[7:7],x_0_7[7:7],x_0_6[7:7],x_0_5[7:7],x_0_4[7:7],x_0_3[7:7],x_0_2[7:7],x_0_1[7:7],x_0_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc66.ACASCREG=0;
defparam desc66.ADREG=0;
defparam desc66.ALUMODEREG=0;
defparam desc66.AREG=0;
defparam desc66.AUTORESET_PATDET="NO_RESET";
defparam desc66.A_INPUT="DIRECT";
defparam desc66.BCASCREG=1;
defparam desc66.BREG=1;
defparam desc66.B_INPUT="CASCADE";
defparam desc66.CARRYINREG=0;
defparam desc66.CARRYINSELREG=0;
defparam desc66.CREG=1;
defparam desc66.DREG=0;
defparam desc66.INMODEREG=0;
defparam desc66.MREG=0;
defparam desc66.OPMODEREG=0;
defparam desc66.PREG=1;
defparam desc66.USE_DPORT="FALSE";
defparam desc66.USE_MULT="MULTIPLY";
defparam desc66.USE_SIMD="ONE48";
DSP48E1 desc67(.ACOUT(ACOUT_9[29:0]),.BCOUT(BCOUT_9[17:0]),.CARRYCASCOUT(CARRYCASCOUT_9),.CARRYOUT(CARRYOUT_9[3:0]),.MULTSIGNOUT(MULTSIGNOUT_9),.OVERFLOW(OVERFLOW_9),.P({P_uc_9[47:15],P_uc_8[14:14],P_uc_6[13:12],P_uc_1[11:11],un1_x_9_0[15:5]}),.PATTERNBDETECT(PATTERNBDETECT_9),.PATTERNDETECT(PATTERNDETECT_9),.PCOUT(PCOUT_9[47:0]),.UNDERFLOW(UNDERFLOW_9),.A({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,GND,VCC}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.BCIN({x_6_10[7:7],x_6_9[7:7],x_6_8[7:7],x_6_7[7:7],x_6_6[7:7],x_6_5[7:7],x_6_4[7:7],x_6_3[7:7],x_6_2[7:7],x_6_1[7:7],x_6_0[7:0]}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc67.ACASCREG=0;
defparam desc67.ADREG=0;
defparam desc67.ALUMODEREG=0;
defparam desc67.AREG=0;
defparam desc67.AUTORESET_PATDET="NO_RESET";
defparam desc67.A_INPUT="DIRECT";
defparam desc67.BCASCREG=1;
defparam desc67.BREG=1;
defparam desc67.B_INPUT="CASCADE";
defparam desc67.CARRYINREG=0;
defparam desc67.CARRYINSELREG=0;
defparam desc67.CREG=1;
defparam desc67.DREG=0;
defparam desc67.INMODEREG=0;
defparam desc67.MREG=0;
defparam desc67.OPMODEREG=0;
defparam desc67.PREG=1;
defparam desc67.USE_DPORT="FALSE";
defparam desc67.USE_MULT="MULTIPLY";
defparam desc67.USE_SIMD="ONE48";
LUT3 un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o6(.I0(un1_x_12_0_0[5:5]),.I1(un1_x_13_0_0[6:6]),.I2(un1_x_14_0_0[5:5]),.O(un84_sop_0_0_0_11_6_0_axb_1));
defparam un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o6.INIT=8'h96;
LUT3 un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o5(.I0(un1_x_12_0_0[5:5]),.I1(un1_x_13_0_0[6:6]),.I2(un1_x_14_0_0[5:5]),.O(un84_sop_0_0_0_11_6_0_axb_1_lut6_2_O5));
defparam un84_sop_0_0_0_11_6_0_axb_1_lut6_2_o5.INIT=8'hE8;
LUT3 un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o6(.I0(un1_x_7_0[3:3]),.I1(un1_x_8_0[5:5]),.I2(un1_x_9_0[6:6]),.O(un84_sop_0_0_0_6_6_0_axb_1));
defparam un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o6.INIT=8'h96;
LUT3 un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o5(.I0(un1_x_7_0[3:3]),.I1(un1_x_8_0[5:5]),.I2(un1_x_9_0[6:6]),.O(un84_sop_0_0_0_6_6_0_axb_1_lut6_2_O5));
defparam un84_sop_0_0_0_6_6_0_axb_1_lut6_2_o5.INIT=8'hE8;
LUT3 un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o6(.I0(un84_sop_0_0_0_10_0[5:5]),.I1(x_4[0:0]),.I2(x_4[2:2]),.O(un84_sop_0_0_0_1_6_8_axb_2));
defparam un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o6.INIT=8'h96;
LUT3 un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o5(.I0(un84_sop_0_0_0_10_0[5:5]),.I1(x_4[0:0]),.I2(x_4[2:2]),.O(un84_sop_0_0_0_1_6_8_axb_2_lut6_2_O5));
defparam un84_sop_0_0_0_1_6_8_axb_2_lut6_2_o5.INIT=8'hE8;
LUT3 un84_sop_1_6_0_axb_1_lut6_2_o6(.I0(un1_x_1[5:5]),.I1(un1_x_2[6:6]),.I2(un1_x_3[5:5]),.O(un84_sop_1_6_0_axb_1));
defparam un84_sop_1_6_0_axb_1_lut6_2_o6.INIT=8'h96;
LUT3 un84_sop_1_6_0_axb_1_lut6_2_o5(.I0(un1_x_1[5:5]),.I1(un1_x_2[6:6]),.I2(un1_x_3[5:5]),.O(un84_sop_1_6_0_axb_1_lut6_2_O5));
defparam un84_sop_1_6_0_axb_1_lut6_2_o5.INIT=8'hE8;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_wrcal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Write calibration logic to align DQS to correct CK edge
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $
**$Date: 2011/06/02 08:35:09 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_phy_wrcal #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 2500,
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter SIM_CAL_OPTION = "NONE" // Skip various calibration steps
)
(
input clk,
input rst,
// Calibration status, control signals
input wrcal_start,
input wrcal_rd_wait,
input wrcal_sanity_chk,
input dqsfound_retry_done,
input phy_rddata_en,
output dqsfound_retry,
output wrcal_read_req,
output reg wrcal_act_req,
output reg wrcal_done,
output reg wrcal_pat_err,
output reg wrcal_prech_req,
output reg temp_wrcal_done,
output reg wrcal_sanity_chk_done,
input prech_done,
// Captured data in resync clock domain
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Write level values of Phaser_Out coarse and fine
// delay taps required to load Phaser_Out register
input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
input wrlvl_byte_done,
output reg wrlvl_byte_redo,
output reg early1_data,
output reg early2_data,
// DQ IDELAY
output reg idelay_ld,
output reg wrcal_pat_resume, // to phy_init for write
output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt,
output phy_if_reset,
// Debug Port
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [99:0] dbg_phy_wrcal
);
// Length of calibration sequence (in # of words)
//localparam CAL_PAT_LEN = 8;
// Read data shift register length
localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2;
// # of reads for reliable read capture
localparam NUM_READS = 2;
// # of cycles to wait after changing RDEN count value
localparam RDEN_WAIT_CNT = 12;
localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6;
localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44;
localparam CAL2_IDLE = 4'h0;
localparam CAL2_READ_WAIT = 4'h1;
localparam CAL2_NEXT_DQS = 4'h2;
localparam CAL2_WRLVL_WAIT = 4'h3;
localparam CAL2_IFIFO_RESET = 4'h4;
localparam CAL2_DQ_IDEL_DEC = 4'h5;
localparam CAL2_DONE = 4'h6;
localparam CAL2_SANITY_WAIT = 4'h7;
localparam CAL2_ERR = 4'h8;
integer i,j,k,l,m,p,q,d;
reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1];
reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w;
reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1];
reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w;
reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */;
reg [4:0] not_empty_wait_cnt;
reg [3:0] tap_inc_wait_cnt;
reg cal2_done_r;
reg cal2_done_r1;
reg cal2_prech_req_r;
reg [3:0] cal2_state_r;
reg [3:0] cal2_state_r1;
reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1];
reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1];
reg cal2_if_reset;
reg wrcal_pat_resume_r;
reg wrcal_pat_resume_r1;
reg wrcal_pat_resume_r2;
reg wrcal_pat_resume_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r;
reg pat_data_match_r;
reg pat1_data_match_r;
reg pat1_data_match_r1;
reg pat2_data_match_r;
reg pat_data_match_valid_r;
wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0];
reg [DRAM_WIDTH-1:0] pat_match_fall0_r;
reg pat_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall1_r;
reg pat_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall2_r;
reg pat_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall3_r;
reg pat_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise0_r;
reg pat_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise1_r;
reg pat_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise2_r;
reg pat_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise3_r;
reg pat_match_rise3_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall1_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall1_r;
reg pat1_match_rise0_and_r;
reg pat1_match_rise1_and_r;
reg pat1_match_fall0_and_r;
reg pat1_match_fall1_and_r;
reg pat2_match_rise0_and_r;
reg pat2_match_rise1_and_r;
reg pat2_match_fall0_and_r;
reg pat2_match_fall1_and_r;
reg early1_data_match_r;
reg early1_data_match_r1;
reg [DRAM_WIDTH-1:0] early1_match_fall0_r;
reg early1_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall1_r;
reg early1_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall2_r;
reg early1_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall3_r;
reg early1_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise0_r;
reg early1_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise1_r;
reg early1_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise2_r;
reg early1_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise3_r;
reg early1_match_rise3_and_r;
reg early2_data_match_r;
reg [DRAM_WIDTH-1:0] early2_match_fall0_r;
reg early2_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall1_r;
reg early2_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall2_r;
reg early2_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall3_r;
reg early2_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise0_r;
reg early2_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise1_r;
reg early2_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise2_r;
reg early2_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise3_r;
reg early2_match_rise3_and_r;
wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0];
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;
reg rd_active_posedge_r;
reg rd_active_r;
reg rd_active_r1;
reg rd_active_r2;
reg rd_active_r3;
reg rd_active_r4;
reg rd_active_r5;
reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0];
reg wrlvl_byte_done_r;
reg idelay_ld_done;
reg pat1_detect;
reg early1_detect;
reg wrcal_sanity_chk_r;
reg wrcal_sanity_chk_err;
//***************************************************************************
// Debug
//***************************************************************************
always @(*) begin
for (d = 0; d < DQS_WIDTH; d = d + 1) begin
po_fine_tap_cnt_w[(6*d)+:6] = po_fine_tap_cnt[d];
po_coarse_tap_cnt_w[(3*d)+:3] = po_coarse_tap_cnt[d];
end
end
assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w;
assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w;
generate
if (nCK_PER_CLK == 4) begin: match_data_4
assign dbg_phy_wrcal[0] = pat_data_match_r;
end else begin:match_data_2
assign dbg_phy_wrcal[0] = 1'b0;
end
endgenerate
assign dbg_phy_wrcal[4:1] = cal2_state_r1[3:0];
assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err;
assign dbg_phy_wrcal[6] = wrcal_start;
assign dbg_phy_wrcal[7] = wrcal_done;
assign dbg_phy_wrcal[8] = pat_data_match_valid_r;
assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r;
assign dbg_phy_wrcal[17+:5] = not_empty_wait_cnt;
assign dbg_phy_wrcal[22] = early1_data;
assign dbg_phy_wrcal[23] = early2_data;
assign dbg_phy_wrcal[24+:8] = mux_rd_rise0_r;
assign dbg_phy_wrcal[32+:8] = mux_rd_fall0_r;
assign dbg_phy_wrcal[40+:8] = mux_rd_rise1_r;
assign dbg_phy_wrcal[48+:8] = mux_rd_fall1_r;
generate
if (nCK_PER_CLK == 4) begin: mux_data_4
assign dbg_phy_wrcal[56+:8] = mux_rd_rise2_r;
assign dbg_phy_wrcal[64+:8] = mux_rd_fall2_r;
assign dbg_phy_wrcal[72+:8] = mux_rd_rise3_r;
assign dbg_phy_wrcal[80+:8] = mux_rd_fall3_r;
end else begin: mux_data_2
assign dbg_phy_wrcal[56+:8] = {8{1'b0}};
assign dbg_phy_wrcal[64+:8] = {8{1'b0}};
assign dbg_phy_wrcal[72+:8] = {8{1'b0}};
assign dbg_phy_wrcal[80+:8] = {8{1'b0}};
end
endgenerate
assign dbg_phy_wrcal[88] = early1_data_match_r;
assign dbg_phy_wrcal[89] = early2_data_match_r;
assign dbg_phy_wrcal[90] = wrcal_sanity_chk_r & pat_data_match_valid_r;
assign dbg_phy_wrcal[91] = wrcal_sanity_chk_r;
assign dbg_phy_wrcal[92] = wrcal_sanity_chk_done;
assign dqsfound_retry = 1'b0;
assign wrcal_read_req = 1'b0;
assign phy_if_reset = cal2_if_reset;
//**************************************************************************
// DQS count to hard PHY during write calibration using Phaser_OUT Stage2
// coarse delay
//**************************************************************************
always @(posedge clk) begin
po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r;
wrlvl_byte_done_r <= #TCQ wrlvl_byte_done;
wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk;
end
//***************************************************************************
// Data mux to route appropriate byte to calibration logic - i.e. calibration
// is done sequentially, one byte (or DQS group) at a time
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_rd_data_div4
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
end
endgenerate
//**************************************************************************
// Final Phaser OUT coarse and fine delay taps after write calibration
// Sum of taps used during write leveling taps and write calibration
//**************************************************************************
always @(*) begin
for (m = 0; m < DQS_WIDTH; m = m + 1) begin
wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3];
wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6];
end
end
always @(posedge clk) begin
if (rst) begin
for (p = 0; p < DQS_WIDTH; p = p + 1) begin
po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}};
po_fine_tap_cnt[p] <= #TCQ {6{1'b0}};
end
end else if (cal2_done_r && ~cal2_done_r1) begin
for (q = 0; q < DQS_WIDTH; q = q + 1) begin
po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i];
po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i];
end
end
end
always @(posedge clk) begin
rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r;
end
// Register outputs for improved timing.
// NOTE: Will need to change when per-bit DQ deskew is supported.
// Currenly all bits in DQS group are checked in aggregate
generate
genvar mux_i;
if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
end
endgenerate
//***************************************************************************
// generate request to PHY_INIT logic to issue precharged. Required when
// calibration can take a long time (during which there are only constant
// reads present on this bus). In this case need to issue perioidic
// precharges to avoid tRAS violation. This signal must meet the following
// requirements: (1) only transition from 0->1 when prech is first needed,
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
//***************************************************************************
always @(posedge clk)
if (rst)
wrcal_prech_req <= #TCQ 1'b0;
else
// Combine requests from all stages here
wrcal_prech_req <= #TCQ cal2_prech_req_r;
//***************************************************************************
// Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES
// NOTE: Written using discrete flops, but SRL can be used if the matching
// logic does the comparison sequentially, rather than parallel
//***************************************************************************
generate
genvar rd_i;
if (nCK_PER_CLK == 4) begin: gen_sr_div4
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i];
sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i];
sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i];
sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_sr_div2
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
end
end
end
endgenerate
//***************************************************************************
// Write calibration:
// During write leveling DQS is aligned to the nearest CK edge that may not
// be the correct CK edge. Write calibration is required to align the DQS to
// the correct CK edge that clocks the write command.
// The Phaser_Out coarse delay line is adjusted if required to add a memory
// clock cycle of delay in order to read back the expected pattern.
//***************************************************************************
always @(posedge clk) begin
rd_active_r <= #TCQ phy_rddata_en;
rd_active_r1 <= #TCQ rd_active_r;
rd_active_r2 <= #TCQ rd_active_r1;
rd_active_r3 <= #TCQ rd_active_r2;
rd_active_r4 <= #TCQ rd_active_r3;
rd_active_r5 <= #TCQ rd_active_r4;
end
//*****************************************************************
// Expected data pattern when properly received by read capture
// logic:
// Based on pattern of ({rise,fall}) =
// 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
// Each nibble will look like:
// bit3: 1, 0, 1, 0, 0, 1, 1, 0
// bit2: 1, 0, 0, 1, 1, 0, 0, 1
// bit1: 1, 0, 1, 0, 0, 1, 0, 1
// bit0: 1, 0, 0, 1, 1, 0, 1, 0
// Change the hard-coded pattern below accordingly as RD_SHIFT_LEN
// and the actual training pattern contents change
//*****************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_pat_div4
// FF00AA5555AA9966
assign pat_rise0[3] = 1'b1;
assign pat_fall0[3] = 1'b0;
assign pat_rise1[3] = 1'b1;
assign pat_fall1[3] = 1'b0;
assign pat_rise2[3] = 1'b0;
assign pat_fall2[3] = 1'b1;
assign pat_rise3[3] = 1'b1;
assign pat_fall3[3] = 1'b0;
assign pat_rise0[2] = 1'b1;
assign pat_fall0[2] = 1'b0;
assign pat_rise1[2] = 1'b0;
assign pat_fall1[2] = 1'b1;
assign pat_rise2[2] = 1'b1;
assign pat_fall2[2] = 1'b0;
assign pat_rise3[2] = 1'b0;
assign pat_fall3[2] = 1'b1;
assign pat_rise0[1] = 1'b1;
assign pat_fall0[1] = 1'b0;
assign pat_rise1[1] = 1'b1;
assign pat_fall1[1] = 1'b0;
assign pat_rise2[1] = 1'b0;
assign pat_fall2[1] = 1'b1;
assign pat_rise3[1] = 1'b0;
assign pat_fall3[1] = 1'b1;
assign pat_rise0[0] = 1'b1;
assign pat_fall0[0] = 1'b0;
assign pat_rise1[0] = 1'b0;
assign pat_fall1[0] = 1'b1;
assign pat_rise2[0] = 1'b1;
assign pat_fall2[0] = 1'b0;
assign pat_rise3[0] = 1'b1;
assign pat_fall3[0] = 1'b0;
// Pattern to distinguish between early write and incorrect read
// BB11EE4444EEDD88
assign early_rise0[3] = 1'b1;
assign early_fall0[3] = 1'b0;
assign early_rise1[3] = 1'b1;
assign early_fall1[3] = 1'b0;
assign early_rise2[3] = 1'b0;
assign early_fall2[3] = 1'b1;
assign early_rise3[3] = 1'b1;
assign early_fall3[3] = 1'b1;
assign early_rise0[2] = 1'b0;
assign early_fall0[2] = 1'b0;
assign early_rise1[2] = 1'b1;
assign early_fall1[2] = 1'b1;
assign early_rise2[2] = 1'b1;
assign early_fall2[2] = 1'b1;
assign early_rise3[2] = 1'b1;
assign early_fall3[2] = 1'b0;
assign early_rise0[1] = 1'b1;
assign early_fall0[1] = 1'b0;
assign early_rise1[1] = 1'b1;
assign early_fall1[1] = 1'b0;
assign early_rise2[1] = 1'b0;
assign early_fall2[1] = 1'b1;
assign early_rise3[1] = 1'b0;
assign early_fall3[1] = 1'b0;
assign early_rise0[0] = 1'b1;
assign early_fall0[0] = 1'b1;
assign early_rise1[0] = 1'b0;
assign early_fall1[0] = 1'b0;
assign early_rise2[0] = 1'b0;
assign early_fall2[0] = 1'b0;
assign early_rise3[0] = 1'b1;
assign early_fall3[0] = 1'b0;
end else if (nCK_PER_CLK == 2) begin: gen_pat_div2
// First cycle pattern FF00AA55
assign pat1_rise0[3] = 1'b1;
assign pat1_fall0[3] = 1'b0;
assign pat1_rise1[3] = 1'b1;
assign pat1_fall1[3] = 1'b0;
assign pat1_rise0[2] = 1'b1;
assign pat1_fall0[2] = 1'b0;
assign pat1_rise1[2] = 1'b0;
assign pat1_fall1[2] = 1'b1;
assign pat1_rise0[1] = 1'b1;
assign pat1_fall0[1] = 1'b0;
assign pat1_rise1[1] = 1'b1;
assign pat1_fall1[1] = 1'b0;
assign pat1_rise0[0] = 1'b1;
assign pat1_fall0[0] = 1'b0;
assign pat1_rise1[0] = 1'b0;
assign pat1_fall1[0] = 1'b1;
// Second cycle pattern 55AA9966
assign pat2_rise0[3] = 1'b0;
assign pat2_fall0[3] = 1'b1;
assign pat2_rise1[3] = 1'b1;
assign pat2_fall1[3] = 1'b0;
assign pat2_rise0[2] = 1'b1;
assign pat2_fall0[2] = 1'b0;
assign pat2_rise1[2] = 1'b0;
assign pat2_fall1[2] = 1'b1;
assign pat2_rise0[1] = 1'b0;
assign pat2_fall0[1] = 1'b1;
assign pat2_rise1[1] = 1'b0;
assign pat2_fall1[1] = 1'b1;
assign pat2_rise0[0] = 1'b1;
assign pat2_fall0[0] = 1'b0;
assign pat2_rise1[0] = 1'b1;
assign pat2_fall1[0] = 1'b0;
//Pattern to distinguish between early write and incorrect read
// First cycle pattern AA5555AA
assign early1_rise0[3] = 2'b1;
assign early1_fall0[3] = 2'b0;
assign early1_rise1[3] = 2'b0;
assign early1_fall1[3] = 2'b1;
assign early1_rise0[2] = 2'b0;
assign early1_fall0[2] = 2'b1;
assign early1_rise1[2] = 2'b1;
assign early1_fall1[2] = 2'b0;
assign early1_rise0[1] = 2'b1;
assign early1_fall0[1] = 2'b0;
assign early1_rise1[1] = 2'b0;
assign early1_fall1[1] = 2'b1;
assign early1_rise0[0] = 2'b0;
assign early1_fall0[0] = 2'b1;
assign early1_rise1[0] = 2'b1;
assign early1_fall1[0] = 2'b0;
// Second cycle pattern 9966BB11
assign early2_rise0[3] = 2'b1;
assign early2_fall0[3] = 2'b0;
assign early2_rise1[3] = 2'b1;
assign early2_fall1[3] = 2'b0;
assign early2_rise0[2] = 2'b0;
assign early2_fall0[2] = 2'b1;
assign early2_rise1[2] = 2'b0;
assign early2_fall1[2] = 2'b0;
assign early2_rise0[1] = 2'b0;
assign early2_fall0[1] = 2'b1;
assign early2_rise1[1] = 2'b1;
assign early2_fall1[1] = 2'b0;
assign early2_rise0[0] = 2'b1;
assign early2_fall0[0] = 2'b0;
assign early2_rise1[0] = 2'b1;
assign early2_fall1[0] = 2'b1;
end
endgenerate
// Each bit of each byte is compared to expected pattern.
// This was done to prevent (and "drastically decrease") the chance that
// invalid data clocked in when the DQ bus is tri-state (along with a
// combination of the correct data) will resemble the expected data
// pattern. A better fix for this is to change the training pattern and/or
// make the pattern longer.
generate
genvar pt_i;
if (nCK_PER_CLK == 4) begin: gen_pat_match_div4
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4])
pat_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4])
pat_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4])
pat_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4])
pat_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4])
pat_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4])
pat_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4])
pat_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4])
pat_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4])
early1_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4])
early1_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise0[pt_i%4])
early1_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall0[pt_i%4])
early1_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == early_rise0[pt_i%4])
early2_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == early_fall0[pt_i%4])
early2_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise1[pt_i%4])
early2_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall1[pt_i%4])
early2_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;
pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;
pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;
pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;
pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r;
pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r;
pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r;
pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r;
pat_data_match_r <= #TCQ (pat_match_rise0_and_r &&
pat_match_fall0_and_r &&
pat_match_rise1_and_r &&
pat_match_fall1_and_r &&
pat_match_rise2_and_r &&
pat_match_fall2_and_r &&
pat_match_rise3_and_r &&
pat_match_fall3_and_r);
pat_data_match_valid_r <= #TCQ rd_active_r3;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r;
early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r;
early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r;
early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r &&
early1_match_rise2_and_r &&
early1_match_fall2_and_r &&
early1_match_rise3_and_r &&
early1_match_fall3_and_r);
end
always @(posedge clk) begin
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r;
early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r;
early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r;
early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r;
early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r &&
early2_match_rise2_and_r &&
early2_match_fall2_and_r &&
early2_match_rise3_and_r &&
early2_match_fall3_and_r);
end
end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])
pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])
pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4])
pat2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4])
pat2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4])
pat2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4])
pat2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
// early2 in this case does not mean 2 cycles early but
// the second cycle of read data in 2:1 mode
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_fall0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_fall1_and_r);
pat1_data_match_r1 <= #TCQ pat1_data_match_r;
pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3;
pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3;
pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3;
pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3;
pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r &&
pat2_match_fall0_and_r &&
pat2_match_rise1_and_r &&
pat2_match_fall1_and_r);
// For 2:1 mode, read valid is asserted for 2 clock cycles -
// here we generate a "match valid" pulse that is only 1 clock
// cycle wide that is simulatenous when the match calculation
// is complete
pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r);
early1_data_match_r1 <= #TCQ early1_data_match_r;
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r);
end
end
endgenerate
// Need to delay it by 3 cycles in order to wait for Phaser_Out
// coarse delay to take effect before issuing a write command
always @(posedge clk) begin
wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r;
wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1;
wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2;
end
always @(posedge clk) begin
if (rst)
tap_inc_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) ||
(cal2_state_r == CAL2_IFIFO_RESET) ||
(cal2_state_r == CAL2_SANITY_WAIT))
tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1;
else
tap_inc_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk) begin
if (rst)
not_empty_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait)
not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1;
else
not_empty_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk)
cal2_state_r1 <= #TCQ cal2_state_r;
//*****************************************************************
// Write Calibration state machine
//*****************************************************************
// when calibrating, check to see if the expected pattern is received.
// Otherwise delay DQS to align to correct CK edge.
// NOTES:
// 1. An error condition can occur due to two reasons:
// a. If the matching logic does not receive the expected data
// pattern. However, the error may be "recoverable" because
// the write calibration is still in progress. If an error is
// found the write calibration logic delays DQS by an additional
// clock cycle and restarts the pattern detection process.
// By design, if the write path timing is incorrect, the correct
// data pattern will never be detected.
// b. Valid data not found even after incrementing Phaser_Out
// coarse delay line.
always @(posedge clk) begin
if (rst) begin
wrcal_dqs_cnt_r <= #TCQ 'b0;
cal2_done_r <= #TCQ 1'b0;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IDLE;
wrcal_pat_err <= #TCQ 1'b0;
wrcal_pat_resume_r <= #TCQ 1'b0;
wrcal_act_req <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
temp_wrcal_done <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b0;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
idelay_ld <= #TCQ 1'b0;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
early1_detect <= #TCQ 1'b0;
wrcal_sanity_chk_done <= #TCQ 1'b0;
wrcal_sanity_chk_err <= #TCQ 1'b0;
end else begin
cal2_prech_req_r <= #TCQ 1'b0;
case (cal2_state_r)
CAL2_IDLE: begin
wrcal_pat_err <= #TCQ 1'b0;
if (wrcal_start) begin
cal2_if_reset <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "SKIP_CAL")
// If skip write calibration, then proceed to end.
cal2_state_r <= #TCQ CAL2_DONE;
else
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
// General wait state to wait for read data to be output by the
// IN_FIFO
CAL2_READ_WAIT: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
// Wait until read data is received, and pattern matching
// calculation is complete. NOTE: Need to add a timeout here
// in case for some reason data is never received (or rather
// the PHASER_IN and IN_FIFO think they never receives data)
if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin
if (pat_data_match_r)
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else begin
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_ERR;
// If writes are one or two cycles early then redo
// write leveling for the byte
else if (early1_data_match_r) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early2_data_match_r) begin
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b1;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin
if ((pat1_data_match_r1 && pat2_data_match_r) ||
(pat1_detect && pat2_data_match_r))
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else if (pat1_data_match_r1 && ~pat2_data_match_r) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
pat1_detect <= #TCQ 1'b1;
end else begin
// If writes are one or two cycles early then redo
// write leveling for the byte
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_ERR;
else if ((early1_data_match_r1 && early2_data_match_r) ||
(early1_detect && early2_data_match_r)) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early1_data_match_r1 && ~early2_data_match_r) begin
early1_detect <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (not_empty_wait_cnt == 'd31)
cal2_state_r <= #TCQ CAL2_ERR;
end
CAL2_WRLVL_WAIT: begin
early1_detect <= #TCQ 1'b0;
if (wrlvl_byte_done && ~wrlvl_byte_done_r)
wrlvl_byte_redo <= #TCQ 1'b0;
if (wrlvl_byte_done) begin
if (rd_active_r1 && ~rd_active_r) begin
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
end
end
end
CAL2_DQ_IDEL_DEC: begin
if (tap_inc_wait_cnt == 'd4) begin
idelay_ld <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b1;
end
end
CAL2_IFIFO_RESET: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_if_reset <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_DONE;
else if (idelay_ld_done) begin
wrcal_pat_resume_r <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end else
cal2_state_r <= #TCQ CAL2_IDLE;
end
end
// Final processing for current DQS group. Move on to next group
CAL2_NEXT_DQS: begin
// At this point, we've just found the correct pattern for the
// current DQS group.
// Request bank/row precharge, and wait for its completion. Always
// precharge after each DQS group to avoid tRAS(max) violation
//verilint STARC-2.2.3.3 off
if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin
cal2_prech_req_r <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_SANITY_WAIT;
end else
cal2_prech_req_r <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
if (prech_done)
if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) ||
(wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin
// If either FAST_CAL is enabled and first DQS group is
// finished, or if the last DQS group was just finished,
// then end of write calibration
if (wrcal_sanity_chk_r) begin
cal2_if_reset <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
end else
cal2_state_r <= #TCQ CAL2_DONE;
end else begin
// Continue to next DQS group
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
//verilint STARC-2.2.3.3 on
CAL2_SANITY_WAIT: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
wrcal_pat_resume_r <= #TCQ 1'b1;
end
end
// Finished with read enable calibration
CAL2_DONE: begin
if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin
cal2_done_r <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ 'd0;
cal2_state_r <= #TCQ CAL2_IDLE;
end else
cal2_done_r <= #TCQ 1'b1;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
wrcal_sanity_chk_done <= #TCQ 1'b1;
end
// Assert error signal indicating that writes timing is incorrect
CAL2_ERR: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
wrcal_sanity_chk_err <= #TCQ 1'b1;
else
wrcal_pat_err <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_ERR;
end
endcase
end
end
// Delay assertion of wrcal_done for write calibration by a few cycles after
// we've reached CAL2_DONE
always @(posedge clk)
if (rst)
cal2_done_r1 <= #TCQ 1'b0;
else
cal2_done_r1 <= #TCQ cal2_done_r;
always @(posedge clk)
if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r))
wrcal_done <= #TCQ 1'b0;
else if (cal2_done_r)
wrcal_done <= #TCQ 1'b1;
endmodule
|
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 32-bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Wed Aug 31 18:10:14 2016"
module carads(
clk,
rst_n_key,
echo1,
echo2,
switch1,
switch2,
key1,
uart_rx,
to_sr,
led7,
led6,
voice,
sda,
scl,
MotorA,
MotorB,
ServoPPM,
uart_tx,
clkout,
MotorPWM,
led5,
num,
sel,
testICC
);
input wire clk;
input wire rst_n_key;
input wire echo1;
input wire echo2;
input wire switch1;
input wire switch2;
input wire key1;
input wire uart_rx;
output wire to_sr;
output wire led7;
output wire led6;
output wire voice;
inout wire sda;
output wire scl;
output wire MotorA;
output wire MotorB;
output wire ServoPPM;
output wire uart_tx;
output wire clkout;
output wire MotorPWM;
output wire led5;
output wire [6:0] num;
output wire [3:0] sel;
output wire testICC;
wire [6:0] num_ALTERA_SYNTHESIZED;
wire [3:0] sel_ALTERA_SYNTHESIZED;
wire [9:0] SYNTHESIZED_WIRE_1;
wire [15:0] SYNTHESIZED_WIRE_2;
wire [15:0] SYNTHESIZED_WIRE_3;
wire [9:0] SYNTHESIZED_WIRE_4;
wire [15:0] angle_control;
wire [13:0] distance;
reg rst_n_inside;
wire rst_n;
assign rst_n = rst_n_key && rst_n_inside;
reg[15:0]autoResetCnt;
always@(posedge clk) begin
if(autoResetCnt<10000) begin rst_n_inside <= 1; autoResetCnt = autoResetCnt + 1; end
else if(autoResetCnt>=10000 && autoResetCnt < 60000) begin autoResetCnt = autoResetCnt + 1; rst_n_inside <= 0; end
else if(autoResetCnt >= 60000) rst_n_inside = 1;
else autoResetCnt = 0;
end
transtop b2v_inst(
.clk(clk),
.rst_n(rst_n),
.echo1(echo1),
.echo2(echo2),
.clkout(to_sr),
.distance(distance),
.speed(SYNTHESIZED_WIRE_1));
mainlogic b2v_inst1(
.rst_n(rst_n),
.switch1(switch1),
.switch2(switch2),
.clk(clk),
.distance(distance),
.speed(SYNTHESIZED_WIRE_1),
.triangle(SYNTHESIZED_WIRE_2),
.led1(led7),
.led2(led6),
.voice(voice),
.out_num(SYNTHESIZED_WIRE_4),
.speed_control(SYNTHESIZED_WIRE_3),
.angle_control(angle_control));
top b2v_inst2(
.clk(clk),
.rst_n(rst_n),
.key1(key1),
.uart_rx(uart_rx),
.sda(sda),
.speed_control(SYNTHESIZED_WIRE_3),
.scl(scl),
.MotorPWM(MotorPWM),
.MotorA(MotorA),
.MotorB(MotorB),
.ServoPPM(ServoPPM),
.clkOut(clkout),
.uart_tx(uart_tx),
.newControlDataW(led5),
.accXdata(SYNTHESIZED_WIRE_2),
.angle_control(angle_control),
.testICC(testICC)
);
shumaguan b2v_inst9(
.clk(clk),
.rst_n(rst_n),
.distance(distance),
.num(num),
.sel(sel)
);
endmodule
|
module ADT7310P32S16 (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output CpuIntr_o,
(* intersynth_port="Outputs_o", intersynth_conntype="Bit" *)
output ADT7310CS_n_o,
(* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *)
input[7:0] SPI_Data_i,
(* intersynth_port="SPI_Write", intersynth_conntype="Bit" *)
output SPI_Write_o,
(* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *)
output SPI_ReadNext_o,
(* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *)
output[7:0] SPI_Data_o,
(* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *)
input SPI_FIFOFull_i,
(* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *)
input SPI_FIFOEmpty_i,
(* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *)
input SPI_Transmission_i,
(* intersynth_param="SPICounterPreset_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPreset_i,
(* intersynth_param="Threshold_i", intersynth_conntype="Word" *)
input[15:0] Threshold_i,
(* intersynth_param="PeriodCounterPresetH_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetH_i,
(* intersynth_param="PeriodCounterPresetL_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetL_i,
(* intersynth_param="SensorValue_o", intersynth_conntype="Word" *)
output[15:0] SensorValue_o,
(* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *)
output SPI_CPOL_o,
(* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *)
output SPI_CPHA_o,
(* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *)
output SPI_LSBFE_o
);
/* constant value for dynamic signal */
assign SPI_CPOL_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_CPHA_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_LSBFE_o = 1'b0;
(* keep *)
wire SPIFSM_Start_s;
(* keep *)
wire SPIFSM_Done_s;
(* keep *)
wire [7:0] SPIFSM_Byte0_s;
(* keep *)
wire [7:0] SPIFSM_Byte1_s;
SPIFSM #(
.SPPRWidth (4),
.SPRWidth (4),
.DataWidth (8)
) SPIFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
// FSM control
.Start_i (SPIFSM_Start_s),
.Done_o (SPIFSM_Done_s),
.Byte0_o (SPIFSM_Byte0_s),
.Byte1_o (SPIFSM_Byte1_s),
// to/from SPI_Master
.SPI_Transmission_i (SPI_Transmission_i),
.SPI_Write_o (SPI_Write_o),
.SPI_ReadNext_o (SPI_ReadNext_o),
.SPI_Data_o (SPI_Data_o),
.SPI_Data_i (SPI_Data_i),
.SPI_FIFOFull_i (SPI_FIFOFull_i),
.SPI_FIFOEmpty_i (SPI_FIFOEmpty_i),
// to ADT7310
.ADT7310CS_n_o (ADT7310CS_n_o),
// parameters
.ParamCounterPreset_i(SPICounterPreset_i)
);
SensorFSM #(
.DataWidth (8)
) SensorFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.Enable_i (Enable_i),
.CpuIntr_o (CpuIntr_o),
.SensorValue_o (SensorValue_o),
.MeasureFSM_Start_o (SPIFSM_Start_s),
.MeasureFSM_Done_i (SPIFSM_Done_s),
.MeasureFSM_Byte0_i (SPIFSM_Byte0_s),
.MeasureFSM_Byte1_i (SPIFSM_Byte1_s),
// parameters
.ParamThreshold_i (Threshold_i),
.ParamCounterPreset_i({PeriodCounterPresetH_i, PeriodCounterPresetL_i})
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:58:55 05/17/2016
// Design Name:
// Module Name: escritor_lector_rtc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module escritor_lector_rtc(
input clk,reset,
input [7:0]port_id,in_dato,
input write_strobe,read_strobe,
output reg_a_d,reg_cs,reg_rd,reg_wr,
output reg[7:0]out_dato,
output flag_done,
inout [7:0]dato
);
reg en_funcion;
reg [7:0]addr_RAM,dato_escribir;
wire [7:0]dato_leido;
reg [7:0]next_out_dato;
reg [7:0]reg_addr_RAM, reg_dato_escribir,reg_dato_leido;
reg reg_escribir_leer,escribir_leer;
wire direccion_dato;
/// I/O Datos
Driver_bus_bidireccional instance_driver_bus_bidireccional (
.in_flag_escritura(~reg_wr),
.in_flag_lectura(~reg_rd),
.in_direccion_dato(direccion_dato),
.in_dato(dato_escribir),
.out_reg_dato(dato_leido),
.addr_RAM(addr_RAM),
.dato(dato)
);
//Generador de señales de control
signal_control_rtc_generator instance_signal_control_rtc_generator (
.clk(clk),
.reset(reset),
.in_escribir_leer(escribir_leer),
.en_funcion(en_funcion),
.reg_a_d(reg_a_d),
.reg_cs(reg_cs),
.reg_wr(reg_wr),
.reg_rd(reg_rd),
.out_direccion_dato(direccion_dato),
.flag_done(flag_done)
);
// logica secuencial
always@(negedge clk , posedge reset) begin
if (reset)begin
addr_RAM <= 8'h0;
dato_escribir <= 8'h0;
escribir_leer <= 1'b0;
out_dato <= 8'b0;
end
else begin
addr_RAM <= reg_addr_RAM;
dato_escribir <= reg_dato_escribir;
escribir_leer <= reg_escribir_leer;
out_dato <= next_out_dato;
end
end
// logica combinacional para port_id
always@* begin
if (~reg_rd) next_out_dato = dato_leido;
next_out_dato = out_dato;
if ( write_strobe == 1'b1 || read_strobe == 1'b1) begin
// inicio de secuencia de lectura_escritura rtc
if(port_id == 8'h0E) en_funcion = 1'b1;
else en_funcion = 1'b0;
case (port_id)
8'h00: begin //actualiza direccion
reg_addr_RAM = in_dato;
reg_dato_escribir = dato_escribir;
reg_escribir_leer = escribir_leer;
end
8'h01: begin // actualiza dato
reg_dato_escribir = in_dato;
reg_addr_RAM = addr_RAM;
reg_escribir_leer = escribir_leer;
end
8'h0E: begin // inicia secuancia de rtc
reg_addr_RAM = addr_RAM;
reg_dato_escribir = dato_escribir;
reg_escribir_leer = in_dato[0];
end
default: begin
reg_addr_RAM = addr_RAM;
reg_dato_escribir = dato_escribir;
reg_escribir_leer = escribir_leer;
end
endcase
end
else begin
reg_addr_RAM = addr_RAM;
reg_dato_escribir = dato_escribir;
reg_escribir_leer = escribir_leer;
en_funcion = 1'b0;
end
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Test.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module Test (
address,
clock,
q);
input [0:0] address;
input clock;
output [15:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "test"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "test.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "1"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "test.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=test"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 1 0 INPUT NODEFVAL address[0..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: CONNECT: @address_a 0 0 1 0 address 0 0 1 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Test.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Test_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_async_frame_fifo_64;
// Inputs
reg input_clk = 0;
reg input_rst = 0;
reg output_clk = 0;
reg output_rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
initial begin
// myhdl integration
$from_myhdl(input_clk,
input_rst,
output_clk,
output_rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast);
// dump file
$dumpfile("test_axis_async_frame_fifo_64.lxt");
$dumpvars(0, test_axis_async_frame_fifo_64);
end
axis_async_frame_fifo_64 #(
.ADDR_WIDTH(6),
.DATA_WIDTH(64),
.DROP_WHEN_FULL(0)
)
UUT (
// AXI input
.input_clk(input_clk),
.input_rst(input_rst),
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_clk(output_clk),
.output_rst(output_rst),
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast)
);
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:44:16 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch2v1_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, ack_add_subt, add_subt_dataA,
add_subt_dataB, result_add_subt, op_add_subt, ready_add_subt );
input [63:0] data_in;
input [1:0] shift_region_flag;
output [63:0] data_output;
output [63:0] add_subt_dataA;
output [63:0] add_subt_dataB;
input [63:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, ack_add_subt, op_add_subt;
wire d_ff1_operation_out, sel_mux_1_reg, d_ff3_sign_out, sel_mux_3_reg,
data_output2_63_, cordic_FSM_state_next_1_, n564, n569, n570, n571,
n572, n573, n574, n575, n576, n577, n578, n579, n580, n581, n582,
n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, n593,
n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604,
n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626,
n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637,
n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648,
n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, n659,
n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670,
n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681,
n682, n683, n684, n685, n686, n687, n688, n689, n690, n691, n692,
n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703,
n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714,
n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725,
n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736,
n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758,
n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769,
n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780,
n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791,
n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802,
n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813,
n814, n815, n816, n817, n818, n819, n820, n821, n822, n823, n824,
n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, n835,
n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846,
n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, n857,
n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868,
n869, n870, n871, n872, n873, n874, n875, n876, n877, n878, n879,
n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, n890,
n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, n901,
n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912,
n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923,
n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934,
n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945,
n946, n947, n948, n949, n950, n951, n952, n953, n954, n955, n956,
n957, n958, n959, n960, n961, n962, n963, n964, n965, n966, n967,
n968, n969, n970, n971, n972, n973, n974, n975, n976, n977, n978,
n979, n980, n981, n982, n983, n984, n985, n986, n987, n988, n989,
n990, n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000,
n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010,
n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020,
n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030,
n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040,
n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050,
n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060,
n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070,
n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080,
n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090,
n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100,
n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1475, n1476, n1477, n1478, n1479,
n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489,
n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499,
n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509,
n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519,
n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529,
n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539,
n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549,
n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559,
n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569,
n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579,
n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589,
n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599,
n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609,
n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619,
n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629,
n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639,
n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649,
n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659,
n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669,
n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679,
n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689,
n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699,
n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709,
n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719,
n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729,
n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739,
n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749,
n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759,
n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769,
n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779,
n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789,
n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799,
n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809,
n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819,
n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829,
n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839,
n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849,
n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859,
n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869,
n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879,
n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889,
n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899,
n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909,
n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919,
n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929,
n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939,
n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949,
n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959,
n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969,
n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979,
n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989,
n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999,
n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009,
n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019,
n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029,
n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039,
n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049,
n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059,
n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069,
n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079,
n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089,
n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099,
n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109,
n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119,
n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129,
n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139,
n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149,
n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159,
n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169,
n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179,
n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189,
n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199,
n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209,
n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219,
n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229,
n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239,
n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249,
n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259,
n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269,
n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279,
n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289,
n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299,
n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309,
n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319,
n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329,
n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339,
n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349,
n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359,
n2360, n2361, n2362, n2363, n2364, n2365, n2366;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:0] cont_iter_out;
wire [63:0] d_ff1_Z;
wire [63:0] d_ff_Xn;
wire [63:0] d_ff_Yn;
wire [63:0] d_ff_Zn;
wire [63:0] d_ff2_X;
wire [63:0] d_ff2_Y;
wire [63:0] d_ff2_Z;
wire [63:0] d_ff3_sh_x_out;
wire [63:0] d_ff3_sh_y_out;
wire [56:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [62:0] sign_inv_out;
wire [3:0] cordic_FSM_state_reg;
DFFRXLTS cont_iter_count_reg_3_ ( .D(n1338), .CK(clk), .RN(n2342), .Q(
cont_iter_out[3]), .QN(n1478) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n1333), .CK(clk), .RN(n2341), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n1332), .CK(clk), .RN(n2350), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n1331), .CK(clk), .RN(n2345), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n1330), .CK(clk), .RN(n1488), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n1329), .CK(clk), .RN(n2346), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n1328), .CK(clk), .RN(n2340), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n1327), .CK(clk), .RN(n2349), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n1326), .CK(clk), .RN(n2346), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n1325), .CK(clk), .RN(n2344), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n1324), .CK(clk), .RN(n2344), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n1323), .CK(clk), .RN(n2340), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n1322), .CK(clk), .RN(n1488), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n1321), .CK(clk), .RN(n2348), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n1320), .CK(clk), .RN(n2348), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n1319), .CK(clk), .RN(n2348), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n1318), .CK(clk), .RN(n2348), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n1317), .CK(clk), .RN(n2348), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n1316), .CK(clk), .RN(n2355), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n1315), .CK(clk), .RN(n2353), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n1314), .CK(clk), .RN(n2352), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n1313), .CK(clk), .RN(n2351), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n1312), .CK(clk), .RN(n2357), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n1311), .CK(clk), .RN(n2340), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n1310), .CK(clk), .RN(n2346), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n1309), .CK(clk), .RN(n1489), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n1308), .CK(clk), .RN(n2345), .Q(d_ff1_Z[25])
);
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n1307), .CK(clk), .RN(n2345), .Q(d_ff1_Z[26])
);
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n1306), .CK(clk), .RN(n2346), .Q(d_ff1_Z[27])
);
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n1305), .CK(clk), .RN(n2349), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n1304), .CK(clk), .RN(n2345), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n1303), .CK(clk), .RN(n1489), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n1302), .CK(clk), .RN(n1488), .Q(d_ff1_Z[31])
);
DFFRXLTS reg_Z0_Q_reg_32_ ( .D(n1301), .CK(clk), .RN(n2346), .Q(d_ff1_Z[32])
);
DFFRXLTS reg_Z0_Q_reg_33_ ( .D(n1300), .CK(clk), .RN(n2344), .Q(d_ff1_Z[33])
);
DFFRXLTS reg_Z0_Q_reg_34_ ( .D(n1299), .CK(clk), .RN(n2346), .Q(d_ff1_Z[34])
);
DFFRXLTS reg_Z0_Q_reg_35_ ( .D(n1298), .CK(clk), .RN(n2346), .Q(d_ff1_Z[35])
);
DFFRXLTS reg_Z0_Q_reg_36_ ( .D(n1297), .CK(clk), .RN(n2345), .Q(d_ff1_Z[36])
);
DFFRXLTS reg_Z0_Q_reg_37_ ( .D(n1296), .CK(clk), .RN(n2344), .Q(d_ff1_Z[37])
);
DFFRXLTS reg_Z0_Q_reg_38_ ( .D(n1295), .CK(clk), .RN(n1488), .Q(d_ff1_Z[38])
);
DFFRXLTS reg_Z0_Q_reg_39_ ( .D(n1294), .CK(clk), .RN(n2340), .Q(d_ff1_Z[39])
);
DFFRXLTS reg_Z0_Q_reg_40_ ( .D(n1293), .CK(clk), .RN(n2347), .Q(d_ff1_Z[40])
);
DFFRXLTS reg_Z0_Q_reg_41_ ( .D(n1292), .CK(clk), .RN(n2349), .Q(d_ff1_Z[41])
);
DFFRXLTS reg_Z0_Q_reg_42_ ( .D(n1291), .CK(clk), .RN(n2345), .Q(d_ff1_Z[42])
);
DFFRXLTS reg_Z0_Q_reg_43_ ( .D(n1290), .CK(clk), .RN(n2344), .Q(d_ff1_Z[43])
);
DFFRXLTS reg_Z0_Q_reg_44_ ( .D(n1289), .CK(clk), .RN(n2340), .Q(d_ff1_Z[44])
);
DFFRXLTS reg_Z0_Q_reg_45_ ( .D(n1288), .CK(clk), .RN(n2349), .Q(d_ff1_Z[45])
);
DFFRXLTS reg_Z0_Q_reg_46_ ( .D(n1287), .CK(clk), .RN(n2347), .Q(d_ff1_Z[46])
);
DFFRXLTS reg_Z0_Q_reg_47_ ( .D(n1286), .CK(clk), .RN(n1489), .Q(d_ff1_Z[47])
);
DFFRXLTS reg_Z0_Q_reg_48_ ( .D(n1285), .CK(clk), .RN(n2349), .Q(d_ff1_Z[48])
);
DFFRXLTS reg_Z0_Q_reg_49_ ( .D(n1284), .CK(clk), .RN(n2344), .Q(d_ff1_Z[49])
);
DFFRXLTS reg_Z0_Q_reg_50_ ( .D(n1283), .CK(clk), .RN(n2344), .Q(d_ff1_Z[50])
);
DFFRXLTS reg_Z0_Q_reg_51_ ( .D(n1282), .CK(clk), .RN(n2347), .Q(d_ff1_Z[51])
);
DFFRXLTS reg_Z0_Q_reg_52_ ( .D(n1281), .CK(clk), .RN(n1488), .Q(d_ff1_Z[52])
);
DFFRXLTS reg_Z0_Q_reg_53_ ( .D(n1280), .CK(clk), .RN(n2349), .Q(d_ff1_Z[53])
);
DFFRXLTS reg_Z0_Q_reg_54_ ( .D(n1279), .CK(clk), .RN(n2347), .Q(d_ff1_Z[54])
);
DFFRXLTS reg_Z0_Q_reg_55_ ( .D(n1278), .CK(clk), .RN(n2340), .Q(d_ff1_Z[55])
);
DFFRXLTS reg_Z0_Q_reg_56_ ( .D(n1277), .CK(clk), .RN(n2347), .Q(d_ff1_Z[56])
);
DFFRXLTS reg_Z0_Q_reg_57_ ( .D(n1276), .CK(clk), .RN(n1489), .Q(d_ff1_Z[57])
);
DFFRXLTS reg_Z0_Q_reg_58_ ( .D(n1275), .CK(clk), .RN(n2340), .Q(d_ff1_Z[58])
);
DFFRXLTS reg_Z0_Q_reg_59_ ( .D(n1274), .CK(clk), .RN(n2345), .Q(d_ff1_Z[59])
);
DFFRXLTS reg_Z0_Q_reg_60_ ( .D(n1273), .CK(clk), .RN(n2344), .Q(d_ff1_Z[60])
);
DFFRXLTS reg_Z0_Q_reg_61_ ( .D(n1272), .CK(clk), .RN(n2347), .Q(d_ff1_Z[61])
);
DFFRXLTS reg_Z0_Q_reg_62_ ( .D(n1271), .CK(clk), .RN(n1509), .Q(d_ff1_Z[62])
);
DFFRXLTS reg_Z0_Q_reg_63_ ( .D(n1270), .CK(clk), .RN(n1508), .Q(d_ff1_Z[63])
);
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n1265), .CK(clk), .RN(n2343), .Q(d_ff_Zn[0])
);
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n1264), .CK(clk), .RN(n2341), .Q(d_ff_Zn[1])
);
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n1263), .CK(clk), .RN(n2342), .Q(d_ff_Zn[2])
);
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n1262), .CK(clk), .RN(n2339), .Q(d_ff_Zn[3])
);
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n1261), .CK(clk), .RN(n2339), .Q(d_ff_Zn[4])
);
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n1260), .CK(clk), .RN(n1509), .Q(d_ff_Zn[5])
);
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n1259), .CK(clk), .RN(n1508), .Q(d_ff_Zn[6])
);
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n1258), .CK(clk), .RN(n2341), .Q(d_ff_Zn[7])
);
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n1257), .CK(clk), .RN(n2350), .Q(d_ff_Zn[8])
);
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n1256), .CK(clk), .RN(n2343), .Q(d_ff_Zn[9])
);
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n1255), .CK(clk), .RN(n2342), .Q(
d_ff_Zn[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n1254), .CK(clk), .RN(n2339), .Q(
d_ff_Zn[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n1253), .CK(clk), .RN(n1509), .Q(
d_ff_Zn[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n1252), .CK(clk), .RN(n1508), .Q(
d_ff_Zn[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n1251), .CK(clk), .RN(n2350), .Q(
d_ff_Zn[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n1250), .CK(clk), .RN(n1509), .Q(
d_ff_Zn[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n2357), .Q(
d_ff_Zn[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n1248), .CK(clk), .RN(n1508), .Q(
d_ff_Zn[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n1247), .CK(clk), .RN(n2343), .Q(
d_ff_Zn[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n1246), .CK(clk), .RN(n2341), .Q(
d_ff_Zn[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n1245), .CK(clk), .RN(n2339), .Q(
d_ff_Zn[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n1244), .CK(clk), .RN(n2350), .Q(
d_ff_Zn[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n1243), .CK(clk), .RN(n2343), .Q(
d_ff_Zn[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n1242), .CK(clk), .RN(n2342), .Q(
d_ff_Zn[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n1241), .CK(clk), .RN(n2345), .Q(
d_ff_Zn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n1240), .CK(clk), .RN(n1489), .Q(
d_ff_Zn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n1239), .CK(clk), .RN(n2349), .Q(
d_ff_Zn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n1238), .CK(clk), .RN(n2349), .Q(
d_ff_Zn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n1237), .CK(clk), .RN(n2340), .Q(
d_ff_Zn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n1236), .CK(clk), .RN(n2345), .Q(
d_ff_Zn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n1235), .CK(clk), .RN(n1488), .Q(
d_ff_Zn[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n1234), .CK(clk), .RN(n2346), .Q(
d_ff_Zn[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_32_ ( .D(n1233), .CK(clk), .RN(n2347), .Q(
d_ff_Zn[32]) );
DFFRXLTS d_ff4_Zn_Q_reg_33_ ( .D(n1232), .CK(clk), .RN(n2347), .Q(
d_ff_Zn[33]) );
DFFRXLTS d_ff4_Zn_Q_reg_34_ ( .D(n1231), .CK(clk), .RN(n1509), .Q(
d_ff_Zn[34]) );
DFFRXLTS d_ff4_Zn_Q_reg_35_ ( .D(n1230), .CK(clk), .RN(n2335), .Q(
d_ff_Zn[35]) );
DFFRXLTS d_ff4_Zn_Q_reg_36_ ( .D(n1229), .CK(clk), .RN(n1494), .Q(
d_ff_Zn[36]) );
DFFRXLTS d_ff4_Zn_Q_reg_37_ ( .D(n1228), .CK(clk), .RN(n1506), .Q(
d_ff_Zn[37]) );
DFFRXLTS d_ff4_Zn_Q_reg_38_ ( .D(n1227), .CK(clk), .RN(n1501), .Q(
d_ff_Zn[38]) );
DFFRXLTS d_ff4_Zn_Q_reg_39_ ( .D(n1226), .CK(clk), .RN(n1493), .Q(
d_ff_Zn[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_40_ ( .D(n1225), .CK(clk), .RN(n2354), .Q(
d_ff_Zn[40]) );
DFFRXLTS d_ff4_Zn_Q_reg_41_ ( .D(n1224), .CK(clk), .RN(n2340), .Q(
d_ff_Zn[41]) );
DFFRXLTS d_ff4_Zn_Q_reg_42_ ( .D(n1223), .CK(clk), .RN(n2345), .Q(
d_ff_Zn[42]) );
DFFRXLTS d_ff4_Zn_Q_reg_43_ ( .D(n1222), .CK(clk), .RN(n2366), .Q(
d_ff_Zn[43]) );
DFFRXLTS d_ff4_Zn_Q_reg_44_ ( .D(n1221), .CK(clk), .RN(n2341), .Q(
d_ff_Zn[44]) );
DFFRXLTS d_ff4_Zn_Q_reg_45_ ( .D(n1220), .CK(clk), .RN(n2350), .Q(
d_ff_Zn[45]) );
DFFRXLTS d_ff4_Zn_Q_reg_46_ ( .D(n1219), .CK(clk), .RN(n2343), .Q(
d_ff_Zn[46]) );
DFFRXLTS d_ff4_Zn_Q_reg_47_ ( .D(n1218), .CK(clk), .RN(n2342), .Q(
d_ff_Zn[47]) );
DFFRXLTS d_ff4_Zn_Q_reg_48_ ( .D(n1217), .CK(clk), .RN(n2339), .Q(
d_ff_Zn[48]) );
DFFRXLTS d_ff4_Zn_Q_reg_49_ ( .D(n1216), .CK(clk), .RN(n1509), .Q(
d_ff_Zn[49]) );
DFFRXLTS d_ff4_Zn_Q_reg_50_ ( .D(n1215), .CK(clk), .RN(n1508), .Q(
d_ff_Zn[50]) );
DFFRXLTS d_ff4_Zn_Q_reg_51_ ( .D(n1214), .CK(clk), .RN(n2341), .Q(
d_ff_Zn[51]) );
DFFRXLTS d_ff4_Zn_Q_reg_52_ ( .D(n1213), .CK(clk), .RN(n2350), .Q(
d_ff_Zn[52]) );
DFFRXLTS d_ff4_Zn_Q_reg_53_ ( .D(n1212), .CK(clk), .RN(n2343), .Q(
d_ff_Zn[53]) );
DFFRXLTS d_ff4_Zn_Q_reg_54_ ( .D(n1211), .CK(clk), .RN(n2337), .Q(
d_ff_Zn[54]) );
DFFRXLTS d_ff4_Zn_Q_reg_55_ ( .D(n1210), .CK(clk), .RN(n2336), .Q(
d_ff_Zn[55]) );
DFFRXLTS d_ff4_Zn_Q_reg_56_ ( .D(n1209), .CK(clk), .RN(n2356), .Q(
d_ff_Zn[56]) );
DFFRXLTS d_ff4_Zn_Q_reg_57_ ( .D(n1208), .CK(clk), .RN(n2338), .Q(
d_ff_Zn[57]) );
DFFRXLTS d_ff4_Zn_Q_reg_58_ ( .D(n1207), .CK(clk), .RN(n2337), .Q(
d_ff_Zn[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_59_ ( .D(n1206), .CK(clk), .RN(n2336), .Q(
d_ff_Zn[59]) );
DFFRXLTS d_ff4_Zn_Q_reg_60_ ( .D(n1205), .CK(clk), .RN(n2356), .Q(
d_ff_Zn[60]) );
DFFRXLTS d_ff4_Zn_Q_reg_61_ ( .D(n1204), .CK(clk), .RN(n2338), .Q(
d_ff_Zn[61]) );
DFFRXLTS d_ff4_Zn_Q_reg_62_ ( .D(n1203), .CK(clk), .RN(n2337), .Q(
d_ff_Zn[62]) );
DFFRXLTS d_ff4_Zn_Q_reg_63_ ( .D(n1202), .CK(clk), .RN(n2336), .Q(
d_ff_Zn[63]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n1201), .CK(clk), .RN(n2356), .Q(d_ff_Yn[0]),
.QN(n2239) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n1200), .CK(clk), .RN(n2338), .Q(d_ff_Yn[1]),
.QN(n2240) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n1199), .CK(clk), .RN(n2337), .Q(d_ff_Yn[2]),
.QN(n2241) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n1198), .CK(clk), .RN(n2336), .Q(d_ff_Yn[3]),
.QN(n2242) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n1197), .CK(clk), .RN(n2356), .Q(d_ff_Yn[4]),
.QN(n2243) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n1196), .CK(clk), .RN(n2338), .Q(d_ff_Yn[5]),
.QN(n2244) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n1195), .CK(clk), .RN(n2337), .Q(d_ff_Yn[6]),
.QN(n2245) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(n1194), .CK(clk), .RN(n2336), .Q(d_ff_Yn[7]),
.QN(n2246) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n1193), .CK(clk), .RN(n2356), .Q(d_ff_Yn[8]),
.QN(n2247) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n1192), .CK(clk), .RN(n2338), .Q(d_ff_Yn[9]),
.QN(n2248) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n1191), .CK(clk), .RN(n2337), .Q(
d_ff_Yn[10]), .QN(n2249) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n1190), .CK(clk), .RN(n2336), .Q(
d_ff_Yn[11]), .QN(n2250) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n1189), .CK(clk), .RN(n2356), .Q(
d_ff_Yn[12]), .QN(n2251) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(n1188), .CK(clk), .RN(n2338), .Q(
d_ff_Yn[13]), .QN(n2252) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(n1187), .CK(clk), .RN(n2337), .Q(
d_ff_Yn[14]), .QN(n2253) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(n1186), .CK(clk), .RN(n2336), .Q(
d_ff_Yn[15]), .QN(n2254) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(n1185), .CK(clk), .RN(n2356), .Q(
d_ff_Yn[16]), .QN(n2255) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(n1184), .CK(clk), .RN(n2338), .Q(
d_ff_Yn[17]), .QN(n2256) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(n1183), .CK(clk), .RN(n2337), .Q(
d_ff_Yn[18]), .QN(n2257) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(n1182), .CK(clk), .RN(n2336), .Q(
d_ff_Yn[19]), .QN(n2258) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n1181), .CK(clk), .RN(n2317), .Q(
d_ff_Yn[20]), .QN(n2259) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(n1180), .CK(clk), .RN(n2314), .Q(
d_ff_Yn[21]), .QN(n2260) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(n1179), .CK(clk), .RN(n2333), .Q(
d_ff_Yn[22]), .QN(n2261) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(n1178), .CK(clk), .RN(n2334), .Q(
d_ff_Yn[23]), .QN(n2262) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(n1177), .CK(clk), .RN(n2335), .Q(
d_ff_Yn[24]), .QN(n2263) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(n1176), .CK(clk), .RN(n2315), .Q(
d_ff_Yn[25]), .QN(n2264) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(n1175), .CK(clk), .RN(n2316), .Q(
d_ff_Yn[26]), .QN(n2265) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(n1174), .CK(clk), .RN(n1513), .Q(
d_ff_Yn[27]), .QN(n2266) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(n1173), .CK(clk), .RN(n1514), .Q(
d_ff_Yn[28]), .QN(n2267) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(n1172), .CK(clk), .RN(n2317), .Q(
d_ff_Yn[29]), .QN(n2268) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(n1171), .CK(clk), .RN(n2314), .Q(
d_ff_Yn[30]), .QN(n2269) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(n1170), .CK(clk), .RN(n2333), .Q(
d_ff_Yn[31]), .QN(n2270) );
DFFRXLTS d_ff4_Yn_Q_reg_32_ ( .D(n1169), .CK(clk), .RN(n2334), .Q(
d_ff_Yn[32]), .QN(n2271) );
DFFRXLTS d_ff4_Yn_Q_reg_33_ ( .D(n1168), .CK(clk), .RN(n2335), .Q(
d_ff_Yn[33]), .QN(n2272) );
DFFRXLTS d_ff4_Yn_Q_reg_34_ ( .D(n1167), .CK(clk), .RN(n2315), .Q(
d_ff_Yn[34]), .QN(n2273) );
DFFRXLTS d_ff4_Yn_Q_reg_35_ ( .D(n1166), .CK(clk), .RN(n2316), .Q(
d_ff_Yn[35]), .QN(n2274) );
DFFRXLTS d_ff4_Yn_Q_reg_36_ ( .D(n1165), .CK(clk), .RN(n1513), .Q(
d_ff_Yn[36]), .QN(n2275) );
DFFRXLTS d_ff4_Yn_Q_reg_37_ ( .D(n1164), .CK(clk), .RN(n1514), .Q(
d_ff_Yn[37]), .QN(n2276) );
DFFRXLTS d_ff4_Yn_Q_reg_38_ ( .D(n1163), .CK(clk), .RN(n2317), .Q(
d_ff_Yn[38]), .QN(n2277) );
DFFRXLTS d_ff4_Yn_Q_reg_39_ ( .D(n1162), .CK(clk), .RN(n2314), .Q(
d_ff_Yn[39]), .QN(n2278) );
DFFRXLTS d_ff4_Yn_Q_reg_40_ ( .D(n1161), .CK(clk), .RN(n2333), .Q(
d_ff_Yn[40]), .QN(n2279) );
DFFRXLTS d_ff4_Yn_Q_reg_41_ ( .D(n1160), .CK(clk), .RN(n2334), .Q(
d_ff_Yn[41]), .QN(n2280) );
DFFRXLTS d_ff4_Yn_Q_reg_42_ ( .D(n1159), .CK(clk), .RN(n2335), .Q(
d_ff_Yn[42]), .QN(n2281) );
DFFRXLTS d_ff4_Yn_Q_reg_43_ ( .D(n1158), .CK(clk), .RN(n2315), .Q(
d_ff_Yn[43]), .QN(n2282) );
DFFRXLTS d_ff4_Yn_Q_reg_44_ ( .D(n1157), .CK(clk), .RN(n2316), .Q(
d_ff_Yn[44]), .QN(n2283) );
DFFRXLTS d_ff4_Yn_Q_reg_45_ ( .D(n1156), .CK(clk), .RN(n1513), .Q(
d_ff_Yn[45]), .QN(n2284) );
DFFRXLTS d_ff4_Yn_Q_reg_46_ ( .D(n1155), .CK(clk), .RN(n1514), .Q(
d_ff_Yn[46]), .QN(n2285) );
DFFRXLTS d_ff4_Yn_Q_reg_47_ ( .D(n1154), .CK(clk), .RN(n2317), .Q(
d_ff_Yn[47]), .QN(n2286) );
DFFRXLTS d_ff4_Yn_Q_reg_48_ ( .D(n1153), .CK(clk), .RN(n2314), .Q(
d_ff_Yn[48]), .QN(n2287) );
DFFRXLTS d_ff4_Yn_Q_reg_49_ ( .D(n1152), .CK(clk), .RN(n2333), .Q(
d_ff_Yn[49]), .QN(n2288) );
DFFRXLTS d_ff4_Yn_Q_reg_50_ ( .D(n1151), .CK(clk), .RN(n2304), .Q(
d_ff_Yn[50]), .QN(n2289) );
DFFRXLTS d_ff4_Yn_Q_reg_51_ ( .D(n1150), .CK(clk), .RN(n2342), .Q(
d_ff_Yn[51]), .QN(n2290) );
DFFRXLTS d_ff4_Yn_Q_reg_52_ ( .D(n1149), .CK(clk), .RN(n1507), .Q(
d_ff_Yn[52]) );
DFFRXLTS d_ff4_Yn_Q_reg_53_ ( .D(n1148), .CK(clk), .RN(n2356), .Q(
d_ff_Yn[53]) );
DFFRXLTS d_ff4_Yn_Q_reg_54_ ( .D(n1147), .CK(clk), .RN(n2336), .Q(
d_ff_Yn[54]), .QN(n2291) );
DFFRXLTS d_ff4_Yn_Q_reg_55_ ( .D(n1146), .CK(clk), .RN(n2357), .Q(
d_ff_Yn[55]) );
DFFRXLTS d_ff4_Yn_Q_reg_56_ ( .D(n1145), .CK(clk), .RN(n2351), .Q(
d_ff_Yn[56]) );
DFFRXLTS d_ff4_Yn_Q_reg_57_ ( .D(n1144), .CK(clk), .RN(n2352), .Q(
d_ff_Yn[57]) );
DFFRXLTS d_ff4_Yn_Q_reg_58_ ( .D(n1143), .CK(clk), .RN(n2353), .Q(
d_ff_Yn[58]) );
DFFRXLTS d_ff4_Yn_Q_reg_59_ ( .D(n1142), .CK(clk), .RN(n2348), .Q(
d_ff_Yn[59]) );
DFFRXLTS d_ff4_Yn_Q_reg_60_ ( .D(n1141), .CK(clk), .RN(n2357), .Q(
d_ff_Yn[60]) );
DFFRXLTS d_ff4_Yn_Q_reg_61_ ( .D(n1140), .CK(clk), .RN(n2351), .Q(
d_ff_Yn[61]) );
DFFRXLTS d_ff4_Yn_Q_reg_62_ ( .D(n1139), .CK(clk), .RN(n2352), .Q(
d_ff_Yn[62]) );
DFFRXLTS d_ff4_Yn_Q_reg_63_ ( .D(n1138), .CK(clk), .RN(n2353), .Q(
d_ff_Yn[63]), .QN(n2292) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(n1073), .CK(clk), .RN(n2358), .Q(
sign_inv_out[0]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(n1071), .CK(clk), .RN(n2358), .Q(
sign_inv_out[1]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(n1069), .CK(clk), .RN(n2358), .Q(
sign_inv_out[2]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(n1067), .CK(clk), .RN(n2358), .Q(
sign_inv_out[3]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(n1065), .CK(clk), .RN(n2362), .Q(
sign_inv_out[4]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(n1063), .CK(clk), .RN(n2363), .Q(
sign_inv_out[5]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(n1061), .CK(clk), .RN(n2359), .Q(
sign_inv_out[6]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(n1053), .CK(clk), .RN(n2365), .Q(
sign_inv_out[10]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(n1051), .CK(clk), .RN(n2361), .Q(
sign_inv_out[11]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(n1049), .CK(clk), .RN(n2360), .Q(
sign_inv_out[12]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(n1047), .CK(clk), .RN(n2359), .Q(
sign_inv_out[13]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(n1045), .CK(clk), .RN(n2362), .Q(
sign_inv_out[14]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(n1043), .CK(clk), .RN(n2363), .Q(
sign_inv_out[15]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(n1041), .CK(clk), .RN(n2359), .Q(
sign_inv_out[16]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(n1039), .CK(clk), .RN(n2359), .Q(
sign_inv_out[17]) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(n1037), .CK(clk), .RN(n2362), .Q(
sign_inv_out[18]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(n1035), .CK(clk), .RN(n2363), .Q(
sign_inv_out[19]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(n1033), .CK(clk), .RN(n2360), .Q(
sign_inv_out[20]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(n1031), .CK(clk), .RN(n2361), .Q(
sign_inv_out[21]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(n1029), .CK(clk), .RN(n1507), .Q(
sign_inv_out[22]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(n1027), .CK(clk), .RN(n1506), .Q(
sign_inv_out[23]) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(n1025), .CK(clk), .RN(n2308), .Q(
sign_inv_out[24]) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(n1023), .CK(clk), .RN(n2360), .Q(
sign_inv_out[25]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(n1021), .CK(clk), .RN(n2361), .Q(
sign_inv_out[26]) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(n1019), .CK(clk), .RN(n1507), .Q(
sign_inv_out[27]) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(n1017), .CK(clk), .RN(n2337), .Q(
sign_inv_out[28]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(n1015), .CK(clk), .RN(n2356), .Q(
sign_inv_out[29]) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(n1013), .CK(clk), .RN(n1488), .Q(
sign_inv_out[30]) );
DFFRXLTS d_ff5_Q_reg_31_ ( .D(n1011), .CK(clk), .RN(n2348), .Q(
sign_inv_out[31]) );
DFFRXLTS d_ff5_Q_reg_32_ ( .D(n1009), .CK(clk), .RN(n1489), .Q(
sign_inv_out[32]) );
DFFRXLTS d_ff5_Q_reg_33_ ( .D(n1007), .CK(clk), .RN(n1510), .Q(
sign_inv_out[33]) );
DFFRXLTS d_ff5_Q_reg_34_ ( .D(n1005), .CK(clk), .RN(n1510), .Q(
sign_inv_out[34]) );
DFFRXLTS d_ff5_Q_reg_35_ ( .D(n1003), .CK(clk), .RN(n2353), .Q(
sign_inv_out[35]) );
DFFRXLTS d_ff5_Q_reg_36_ ( .D(n1001), .CK(clk), .RN(n2351), .Q(
sign_inv_out[36]) );
DFFRXLTS d_ff5_Q_reg_40_ ( .D(n993), .CK(clk), .RN(n1502), .Q(
sign_inv_out[40]) );
DFFRXLTS d_ff5_Q_reg_41_ ( .D(n991), .CK(clk), .RN(n1502), .Q(
sign_inv_out[41]) );
DFFRXLTS d_ff5_Q_reg_42_ ( .D(n989), .CK(clk), .RN(n2329), .Q(
sign_inv_out[42]) );
DFFRXLTS d_ff5_Q_reg_43_ ( .D(n987), .CK(clk), .RN(n1502), .Q(
sign_inv_out[43]) );
DFFRXLTS d_ff5_Q_reg_44_ ( .D(n985), .CK(clk), .RN(n2351), .Q(
sign_inv_out[44]) );
DFFRXLTS d_ff5_Q_reg_45_ ( .D(n983), .CK(clk), .RN(n1510), .Q(
sign_inv_out[45]) );
DFFRXLTS d_ff5_Q_reg_46_ ( .D(n981), .CK(clk), .RN(n2353), .Q(
sign_inv_out[46]) );
DFFRXLTS d_ff5_Q_reg_47_ ( .D(n979), .CK(clk), .RN(n1507), .Q(
sign_inv_out[47]) );
DFFRXLTS d_ff5_Q_reg_48_ ( .D(n977), .CK(clk), .RN(n1510), .Q(
sign_inv_out[48]) );
DFFRXLTS d_ff5_Q_reg_49_ ( .D(n975), .CK(clk), .RN(n2334), .Q(
sign_inv_out[49]) );
DFFRXLTS d_ff5_Q_reg_50_ ( .D(n973), .CK(clk), .RN(n1510), .Q(
sign_inv_out[50]) );
DFFRXLTS d_ff5_Q_reg_51_ ( .D(n971), .CK(clk), .RN(n2355), .Q(
sign_inv_out[51]) );
DFFRXLTS d_ff5_Q_reg_52_ ( .D(n969), .CK(clk), .RN(n2353), .Q(
sign_inv_out[52]) );
DFFRXLTS d_ff5_Q_reg_53_ ( .D(n967), .CK(clk), .RN(n2352), .Q(
sign_inv_out[53]) );
DFFRXLTS d_ff5_Q_reg_54_ ( .D(n965), .CK(clk), .RN(n2366), .Q(
sign_inv_out[54]) );
DFFRXLTS d_ff5_Q_reg_55_ ( .D(n963), .CK(clk), .RN(n1502), .Q(
sign_inv_out[55]) );
DFFRXLTS d_ff5_Q_reg_56_ ( .D(n961), .CK(clk), .RN(n1508), .Q(
sign_inv_out[56]) );
DFFRXLTS d_ff5_Q_reg_57_ ( .D(n959), .CK(clk), .RN(n2355), .Q(
sign_inv_out[57]) );
DFFRXLTS d_ff5_Q_reg_58_ ( .D(n957), .CK(clk), .RN(n2353), .Q(
sign_inv_out[58]) );
DFFRXLTS d_ff5_Q_reg_59_ ( .D(n955), .CK(clk), .RN(n2351), .Q(
sign_inv_out[59]) );
DFFRXLTS d_ff5_Q_reg_60_ ( .D(n953), .CK(clk), .RN(n2312), .Q(
sign_inv_out[60]) );
DFFRXLTS d_ff5_Q_reg_61_ ( .D(n951), .CK(clk), .RN(n2313), .Q(
sign_inv_out[61]) );
DFFRXLTS d_ff5_Q_reg_62_ ( .D(n949), .CK(clk), .RN(n2296), .Q(
sign_inv_out[62]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n945), .CK(clk), .RN(n2294), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n944), .CK(clk), .RN(n2312), .Q(
d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n943), .CK(clk), .RN(n2296), .Q(
d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n941), .CK(clk), .RN(n2327), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n940), .CK(clk), .RN(n2309), .Q(
d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n939), .CK(clk), .RN(n2329), .Q(
d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n938), .CK(clk), .RN(n2328), .Q(
d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n937), .CK(clk), .RN(n2310), .QN(n1517) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n936), .CK(clk), .RN(n2311), .Q(
d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n935), .CK(clk), .RN(n2309), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_11_ ( .D(n934), .CK(clk), .RN(n1511), .Q(
d_ff3_LUT_out[11]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n933), .CK(clk), .RN(n2330), .Q(
d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n932), .CK(clk), .RN(n2327), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(n931), .CK(clk), .RN(n2329), .Q(
d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n929), .CK(clk), .RN(n2311), .Q(
d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(n928), .CK(clk), .RN(n2328), .Q(
d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n927), .CK(clk), .RN(n2309), .Q(
d_ff3_LUT_out[18]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n926), .CK(clk), .RN(n2328), .QN(n1515) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n925), .CK(clk), .RN(n2310), .Q(
d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n924), .CK(clk), .RN(n2311), .Q(
d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n923), .CK(clk), .RN(n2309), .Q(
d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n922), .CK(clk), .RN(n1511), .Q(
d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n921), .CK(clk), .RN(n2330), .Q(
d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(n920), .CK(clk), .RN(n2327), .Q(
d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n919), .CK(clk), .RN(n2329), .Q(
d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(n918), .CK(clk), .RN(n1511), .Q(
d_ff3_LUT_out[27]) );
DFFRXLTS reg_LUT_Q_reg_28_ ( .D(n917), .CK(clk), .RN(n2330), .Q(
d_ff3_LUT_out[28]) );
DFFRXLTS reg_LUT_Q_reg_29_ ( .D(n916), .CK(clk), .RN(n2327), .Q(
d_ff3_LUT_out[29]) );
DFFRXLTS reg_LUT_Q_reg_30_ ( .D(n915), .CK(clk), .RN(n2329), .Q(
d_ff3_LUT_out[30]) );
DFFRXLTS reg_LUT_Q_reg_31_ ( .D(n914), .CK(clk), .RN(n1511), .Q(
d_ff3_LUT_out[31]) );
DFFRXLTS reg_LUT_Q_reg_32_ ( .D(n913), .CK(clk), .RN(n2330), .Q(
d_ff3_LUT_out[32]) );
DFFRXLTS reg_LUT_Q_reg_33_ ( .D(n912), .CK(clk), .RN(n2361), .Q(
d_ff3_LUT_out[33]) );
DFFRXLTS reg_LUT_Q_reg_34_ ( .D(n911), .CK(clk), .RN(n2364), .Q(
d_ff3_LUT_out[34]) );
DFFRXLTS reg_LUT_Q_reg_35_ ( .D(n910), .CK(clk), .RN(n2360), .Q(
d_ff3_LUT_out[35]) );
DFFRXLTS reg_LUT_Q_reg_36_ ( .D(n909), .CK(clk), .RN(n2365), .Q(
d_ff3_LUT_out[36]) );
DFFRXLTS reg_LUT_Q_reg_37_ ( .D(n908), .CK(clk), .RN(n2308), .Q(
d_ff3_LUT_out[37]) );
DFFRXLTS reg_LUT_Q_reg_38_ ( .D(n907), .CK(clk), .RN(n1507), .Q(
d_ff3_LUT_out[38]) );
DFFRXLTS reg_LUT_Q_reg_39_ ( .D(n906), .CK(clk), .RN(n1506), .Q(
d_ff3_LUT_out[39]) );
DFFRXLTS reg_LUT_Q_reg_40_ ( .D(n905), .CK(clk), .RN(n2361), .Q(
d_ff3_LUT_out[40]) );
DFFRXLTS reg_LUT_Q_reg_41_ ( .D(n904), .CK(clk), .RN(n2364), .QN(n1516) );
DFFRXLTS reg_LUT_Q_reg_42_ ( .D(n903), .CK(clk), .RN(n2360), .Q(
d_ff3_LUT_out[42]) );
DFFRXLTS reg_LUT_Q_reg_43_ ( .D(n902), .CK(clk), .RN(n2322), .Q(
d_ff3_LUT_out[43]) );
DFFRXLTS reg_LUT_Q_reg_44_ ( .D(n901), .CK(clk), .RN(n2306), .Q(
d_ff3_LUT_out[44]) );
DFFRXLTS reg_LUT_Q_reg_45_ ( .D(n900), .CK(clk), .RN(n2303), .Q(
d_ff3_LUT_out[45]) );
DFFRXLTS reg_LUT_Q_reg_46_ ( .D(n899), .CK(clk), .RN(n2307), .Q(
d_ff3_LUT_out[46]) );
DFFRXLTS reg_LUT_Q_reg_47_ ( .D(n898), .CK(clk), .RN(n2322), .Q(
d_ff3_LUT_out[47]) );
DFFRXLTS reg_LUT_Q_reg_49_ ( .D(n896), .CK(clk), .RN(n2306), .Q(
d_ff3_LUT_out[49]) );
DFFRXLTS reg_LUT_Q_reg_50_ ( .D(n895), .CK(clk), .RN(n2303), .Q(
d_ff3_LUT_out[50]) );
DFFRXLTS reg_LUT_Q_reg_52_ ( .D(n894), .CK(clk), .RN(n2307), .Q(
d_ff3_LUT_out[52]) );
DFFRXLTS reg_LUT_Q_reg_53_ ( .D(n893), .CK(clk), .RN(n2307), .Q(
d_ff3_LUT_out[53]), .QN(n2293) );
DFFRXLTS reg_LUT_Q_reg_54_ ( .D(n892), .CK(clk), .RN(n2322), .Q(
d_ff3_LUT_out[54]) );
DFFRXLTS reg_LUT_Q_reg_55_ ( .D(n891), .CK(clk), .RN(n2306), .Q(
d_ff3_LUT_out[55]) );
DFFRXLTS reg_LUT_Q_reg_56_ ( .D(n890), .CK(clk), .RN(n2303), .Q(
d_ff3_LUT_out[56]) );
DFFRXLTS reg_shift_y_Q_reg_52_ ( .D(n709), .CK(clk), .RN(n2307), .Q(
d_ff3_sh_y_out[52]) );
DFFRXLTS reg_shift_y_Q_reg_53_ ( .D(n708), .CK(clk), .RN(n2322), .Q(
d_ff3_sh_y_out[53]) );
DFFRXLTS reg_shift_y_Q_reg_54_ ( .D(n707), .CK(clk), .RN(n2306), .Q(
d_ff3_sh_y_out[54]) );
DFFRXLTS reg_shift_y_Q_reg_55_ ( .D(n706), .CK(clk), .RN(n2303), .Q(
d_ff3_sh_y_out[55]) );
DFFRXLTS reg_shift_y_Q_reg_56_ ( .D(n705), .CK(clk), .RN(n2307), .Q(
d_ff3_sh_y_out[56]) );
DFFRXLTS reg_shift_y_Q_reg_57_ ( .D(n704), .CK(clk), .RN(n2322), .Q(
d_ff3_sh_y_out[57]) );
DFFRXLTS reg_shift_y_Q_reg_58_ ( .D(n703), .CK(clk), .RN(n2306), .Q(
d_ff3_sh_y_out[58]) );
DFFRXLTS reg_shift_y_Q_reg_59_ ( .D(n702), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_y_out[59]) );
DFFRXLTS reg_shift_y_Q_reg_60_ ( .D(n701), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_y_out[60]) );
DFFRXLTS reg_shift_y_Q_reg_61_ ( .D(n700), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_y_out[61]) );
DFFRXLTS reg_shift_y_Q_reg_62_ ( .D(n699), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_y_out[62]) );
DFFRXLTS reg_shift_x_Q_reg_52_ ( .D(n581), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_x_out[52]) );
DFFRXLTS reg_shift_x_Q_reg_53_ ( .D(n580), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_x_out[53]) );
DFFRXLTS reg_shift_x_Q_reg_54_ ( .D(n579), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_x_out[54]) );
DFFRXLTS reg_shift_x_Q_reg_55_ ( .D(n578), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_x_out[55]) );
DFFRXLTS reg_shift_x_Q_reg_56_ ( .D(n577), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_x_out[56]) );
DFFRXLTS reg_shift_x_Q_reg_57_ ( .D(n576), .CK(clk), .RN(n2305), .Q(
d_ff3_sh_x_out[57]) );
DFFRXLTS reg_shift_x_Q_reg_58_ ( .D(n575), .CK(clk), .RN(n2332), .Q(
d_ff3_sh_x_out[58]) );
DFFRXLTS reg_shift_x_Q_reg_59_ ( .D(n574), .CK(clk), .RN(n2331), .Q(
d_ff3_sh_x_out[59]) );
DFFRXLTS reg_shift_x_Q_reg_60_ ( .D(n573), .CK(clk), .RN(n2304), .Q(
d_ff3_sh_x_out[60]) );
DFFRXLTS reg_shift_x_Q_reg_61_ ( .D(n572), .CK(clk), .RN(n2332), .Q(
d_ff3_sh_x_out[61]) );
DFFRXLTS reg_shift_x_Q_reg_62_ ( .D(n571), .CK(clk), .RN(n2331), .Q(
d_ff3_sh_x_out[62]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n889), .CK(clk), .RN(n2304), .Q(
d_ff2_Z[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_47_ ( .D(n842), .CK(clk), .RN(n2319), .Q(
d_ff2_Z[47]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_48_ ( .D(n841), .CK(clk), .RN(n2318), .Q(
d_ff2_Z[48]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_49_ ( .D(n840), .CK(clk), .RN(n2299), .Q(
d_ff2_Z[49]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_50_ ( .D(n839), .CK(clk), .RN(n2298), .Q(
d_ff2_Z[50]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_51_ ( .D(n838), .CK(clk), .RN(n2319), .Q(
d_ff2_Z[51]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_52_ ( .D(n837), .CK(clk), .RN(n2318), .Q(
d_ff2_Z[52]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_53_ ( .D(n836), .CK(clk), .RN(n2299), .Q(
d_ff2_Z[53]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_54_ ( .D(n835), .CK(clk), .RN(n2298), .Q(
d_ff2_Z[54]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_55_ ( .D(n834), .CK(clk), .RN(n2319), .Q(
d_ff2_Z[55]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_56_ ( .D(n833), .CK(clk), .RN(n2318), .Q(
d_ff2_Z[56]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_58_ ( .D(n831), .CK(clk), .RN(n2298), .Q(
d_ff2_Z[58]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_60_ ( .D(n829), .CK(clk), .RN(n2318), .Q(
d_ff2_Z[60]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n825), .CK(clk), .RN(n2297), .Q(
d_ff3_sign_out) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n823), .CK(clk), .RN(n2297), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n821), .CK(clk), .RN(n2297), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n819), .CK(clk), .RN(n2297), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n817), .CK(clk), .RN(n2297), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n815), .CK(clk), .RN(n2313), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n813), .CK(clk), .RN(n2294), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n811), .CK(clk), .RN(n2296), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n809), .CK(clk), .RN(n2313), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n807), .CK(clk), .RN(n2294), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n805), .CK(clk), .RN(n2312), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n803), .CK(clk), .RN(n2313), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n801), .CK(clk), .RN(n2294), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n799), .CK(clk), .RN(n2296), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n797), .CK(clk), .RN(n2312), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n795), .CK(clk), .RN(n2294), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n793), .CK(clk), .RN(n2312), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n791), .CK(clk), .RN(n2296), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n789), .CK(clk), .RN(n2313), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n787), .CK(clk), .RN(n2294), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n785), .CK(clk), .RN(n2332), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n783), .CK(clk), .RN(n2304), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n781), .CK(clk), .RN(n2331), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n779), .CK(clk), .RN(n2304), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(n777), .CK(clk), .RN(n2331), .Q(
d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n775), .CK(clk), .RN(n2332), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n773), .CK(clk), .RN(n2304), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n771), .CK(clk), .RN(n2331), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n769), .CK(clk), .RN(n2332), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n767), .CK(clk), .RN(n2330), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n765), .CK(clk), .RN(n2327), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n763), .CK(clk), .RN(n2329), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n761), .CK(clk), .RN(n2330), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_y_Q_reg_32_ ( .D(n759), .CK(clk), .RN(n2327), .Q(
d_ff3_sh_y_out[32]) );
DFFRXLTS reg_shift_y_Q_reg_33_ ( .D(n757), .CK(clk), .RN(n1511), .Q(
d_ff3_sh_y_out[33]) );
DFFRXLTS reg_shift_y_Q_reg_34_ ( .D(n755), .CK(clk), .RN(n2310), .Q(
d_ff3_sh_y_out[34]) );
DFFRXLTS reg_shift_y_Q_reg_35_ ( .D(n753), .CK(clk), .RN(n2311), .Q(
d_ff3_sh_y_out[35]) );
DFFRXLTS reg_shift_y_Q_reg_36_ ( .D(n751), .CK(clk), .RN(n1511), .Q(
d_ff3_sh_y_out[36]) );
DFFRXLTS reg_shift_y_Q_reg_37_ ( .D(n749), .CK(clk), .RN(n2328), .Q(
d_ff3_sh_y_out[37]) );
DFFRXLTS reg_shift_y_Q_reg_38_ ( .D(n747), .CK(clk), .RN(n1511), .Q(
d_ff3_sh_y_out[38]) );
DFFRXLTS reg_shift_y_Q_reg_39_ ( .D(n745), .CK(clk), .RN(n2328), .Q(
d_ff3_sh_y_out[39]) );
DFFRXLTS reg_shift_y_Q_reg_40_ ( .D(n743), .CK(clk), .RN(n2310), .Q(
d_ff3_sh_y_out[40]) );
DFFRXLTS reg_shift_y_Q_reg_41_ ( .D(n741), .CK(clk), .RN(n2311), .Q(
d_ff3_sh_y_out[41]) );
DFFRXLTS reg_shift_y_Q_reg_42_ ( .D(n739), .CK(clk), .RN(n2330), .Q(
d_ff3_sh_y_out[42]) );
DFFRXLTS reg_shift_y_Q_reg_43_ ( .D(n737), .CK(clk), .RN(n2329), .Q(
d_ff3_sh_y_out[43]) );
DFFRXLTS reg_shift_y_Q_reg_44_ ( .D(n735), .CK(clk), .RN(n2328), .Q(
d_ff3_sh_y_out[44]) );
DFFRXLTS reg_shift_y_Q_reg_45_ ( .D(n733), .CK(clk), .RN(n2310), .Q(
d_ff3_sh_y_out[45]) );
DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(n731), .CK(clk), .RN(n2311), .Q(
d_ff3_sh_y_out[46]) );
DFFRXLTS reg_shift_y_Q_reg_47_ ( .D(n729), .CK(clk), .RN(n2309), .Q(
d_ff3_sh_y_out[47]) );
DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(n727), .CK(clk), .RN(n1494), .Q(
d_ff3_sh_y_out[48]) );
DFFRXLTS reg_shift_y_Q_reg_49_ ( .D(n725), .CK(clk), .RN(n2302), .Q(
d_ff3_sh_y_out[49]) );
DFFRXLTS reg_shift_y_Q_reg_50_ ( .D(n723), .CK(clk), .RN(n2320), .Q(
d_ff3_sh_y_out[50]) );
DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(n721), .CK(clk), .RN(n1494), .Q(
d_ff3_sh_y_out[51]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_56_ ( .D(n716), .CK(clk), .RN(n2320), .Q(
d_ff2_Y[56]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_58_ ( .D(n714), .CK(clk), .RN(n2320), .Q(
d_ff2_Y[58]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_60_ ( .D(n712), .CK(clk), .RN(n2326), .Q(
d_ff2_Y[60]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_62_ ( .D(n710), .CK(clk), .RN(n2324), .Q(
d_ff2_Y[62]), .QN(n2237) );
DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(n697), .CK(clk), .RN(n2326), .Q(
d_ff3_sh_y_out[63]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n695), .CK(clk), .RN(n2324), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n693), .CK(clk), .RN(n2301), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n691), .CK(clk), .RN(n1494), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n689), .CK(clk), .RN(n1494), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n687), .CK(clk), .RN(n2302), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n685), .CK(clk), .RN(n2323), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n683), .CK(clk), .RN(n2323), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n681), .CK(clk), .RN(n2323), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n679), .CK(clk), .RN(n2323), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n677), .CK(clk), .RN(n2307), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n675), .CK(clk), .RN(n2322), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n673), .CK(clk), .RN(n2306), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n671), .CK(clk), .RN(n2322), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n669), .CK(clk), .RN(n2306), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n667), .CK(clk), .RN(n2303), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n665), .CK(clk), .RN(n2307), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n663), .CK(clk), .RN(n2322), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n661), .CK(clk), .RN(n2306), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n659), .CK(clk), .RN(n2303), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n657), .CK(clk), .RN(n2325), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n655), .CK(clk), .RN(n2301), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n653), .CK(clk), .RN(n2325), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n2301), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n2325), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n647), .CK(clk), .RN(n2298), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n645), .CK(clk), .RN(n2319), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n643), .CK(clk), .RN(n2318), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n641), .CK(clk), .RN(n2299), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n639), .CK(clk), .RN(n2298), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n637), .CK(clk), .RN(n2319), .Q(
d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n635), .CK(clk), .RN(n2318), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n633), .CK(clk), .RN(n2299), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_32_ ( .D(n631), .CK(clk), .RN(n2298), .Q(
d_ff3_sh_x_out[32]) );
DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(n629), .CK(clk), .RN(n2319), .Q(
d_ff3_sh_x_out[33]) );
DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(n627), .CK(clk), .RN(n1514), .Q(
d_ff3_sh_x_out[34]) );
DFFRXLTS reg_shift_x_Q_reg_35_ ( .D(n625), .CK(clk), .RN(n2314), .Q(
d_ff3_sh_x_out[35]) );
DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(n623), .CK(clk), .RN(n2334), .Q(
d_ff3_sh_x_out[36]) );
DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(n621), .CK(clk), .RN(n2315), .Q(
d_ff3_sh_x_out[37]) );
DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(n619), .CK(clk), .RN(n1513), .Q(
d_ff3_sh_x_out[38]) );
DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(n617), .CK(clk), .RN(n2315), .Q(
d_ff3_sh_x_out[39]) );
DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(n615), .CK(clk), .RN(n1513), .Q(
d_ff3_sh_x_out[40]) );
DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(n613), .CK(clk), .RN(n2314), .Q(
d_ff3_sh_x_out[41]) );
DFFRXLTS reg_shift_x_Q_reg_42_ ( .D(n611), .CK(clk), .RN(n2334), .Q(
d_ff3_sh_x_out[42]) );
DFFRXLTS reg_shift_x_Q_reg_43_ ( .D(n609), .CK(clk), .RN(n2315), .Q(
d_ff3_sh_x_out[43]) );
DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(n607), .CK(clk), .RN(n1513), .Q(
d_ff3_sh_x_out[44]) );
DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(n605), .CK(clk), .RN(n2317), .Q(
d_ff3_sh_x_out[45]) );
DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(n603), .CK(clk), .RN(n2333), .Q(
d_ff3_sh_x_out[46]) );
DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(n601), .CK(clk), .RN(n2335), .Q(
d_ff3_sh_x_out[47]) );
DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(n599), .CK(clk), .RN(n2316), .Q(
d_ff3_sh_x_out[48]) );
DFFRXLTS reg_shift_x_Q_reg_49_ ( .D(n597), .CK(clk), .RN(n2317), .Q(
d_ff3_sh_x_out[49]) );
DFFRXLTS reg_shift_x_Q_reg_50_ ( .D(n595), .CK(clk), .RN(n2316), .Q(
d_ff3_sh_x_out[50]) );
DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(n593), .CK(clk), .RN(n1514), .Q(
d_ff3_sh_x_out[51]) );
DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(n569), .CK(clk), .RN(n2331), .Q(
d_ff3_sh_x_out[63]) );
DFFRX2TS cont_var_count_reg_0_ ( .D(n1337), .CK(clk), .RN(n1509), .Q(
cont_var_out[0]), .QN(n2231) );
DFFRX1TS reg_ch_mux_2_Q_reg_0_ ( .D(n1267), .CK(clk), .RN(n2339), .Q(
sel_mux_2_reg[0]), .QN(n2230) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_53_ ( .D(n591), .CK(clk), .RN(n2314), .Q(
d_ff2_X[53]), .QN(n2228) );
DFFRX2TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(clk), .RN(n564), .Q(cordic_FSM_state_reg[1]), .QN(n2222) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n1072), .CK(clk), .RN(n2358), .Q(
data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n1070), .CK(clk), .RN(n2358), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n1068), .CK(clk), .RN(n2358), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n1066), .CK(clk), .RN(n2363), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n1064), .CK(clk), .RN(n2363), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n1062), .CK(clk), .RN(n2362), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n1060), .CK(clk), .RN(n2359), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n1058), .CK(clk), .RN(n2365), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n1056), .CK(clk), .RN(n2364), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n1054), .CK(clk), .RN(n2361), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n1052), .CK(clk), .RN(n2365), .Q(
data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n1050), .CK(clk), .RN(n2364), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n1048), .CK(clk), .RN(n2361), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n1046), .CK(clk), .RN(n2363), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n1044), .CK(clk), .RN(n2362), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n1042), .CK(clk), .RN(n2359), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n1040), .CK(clk), .RN(n2362), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n1038), .CK(clk), .RN(n2359), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n1036), .CK(clk), .RN(n2363), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n1034), .CK(clk), .RN(n2362), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n1032), .CK(clk), .RN(n2365), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n1030), .CK(clk), .RN(n2360), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n1028), .CK(clk), .RN(n2308), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n1026), .CK(clk), .RN(n1506), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n1024), .CK(clk), .RN(n1507), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n1022), .CK(clk), .RN(n2308), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n1020), .CK(clk), .RN(n2360), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n1018), .CK(clk), .RN(n2308), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n1016), .CK(clk), .RN(n2337), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n1014), .CK(clk), .RN(n2338), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n1012), .CK(clk), .RN(n1488), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n1010), .CK(clk), .RN(n2355), .Q(
data_output[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(n1008), .CK(clk), .RN(n1501), .Q(
data_output[32]) );
DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(n1006), .CK(clk), .RN(n2351), .Q(
data_output[33]) );
DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(n1004), .CK(clk), .RN(n2352), .Q(
data_output[34]) );
DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(n1002), .CK(clk), .RN(n2353), .Q(
data_output[35]) );
DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(n1000), .CK(clk), .RN(n2355), .Q(
data_output[36]) );
DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(n998), .CK(clk), .RN(n2350), .Q(
data_output[37]) );
DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(n996), .CK(clk), .RN(n2350), .Q(
data_output[38]) );
DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(n994), .CK(clk), .RN(n2341), .Q(
data_output[39]) );
DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(n992), .CK(clk), .RN(n1502), .Q(
data_output[40]) );
DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(n990), .CK(clk), .RN(n1502), .Q(
data_output[41]) );
DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(n988), .CK(clk), .RN(n2327), .Q(
data_output[42]) );
DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(n986), .CK(clk), .RN(n2353), .Q(
data_output[43]) );
DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(n984), .CK(clk), .RN(n2355), .Q(
data_output[44]) );
DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(n982), .CK(clk), .RN(n1510), .Q(
data_output[45]) );
DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(n980), .CK(clk), .RN(n2357), .Q(
data_output[46]) );
DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(n978), .CK(clk), .RN(n1502), .Q(
data_output[47]) );
DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(n976), .CK(clk), .RN(n1493), .Q(
data_output[48]) );
DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(n974), .CK(clk), .RN(n1489), .Q(
data_output[49]) );
DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(n972), .CK(clk), .RN(n2357), .Q(
data_output[50]) );
DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(n970), .CK(clk), .RN(n2351), .Q(
data_output[51]) );
DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(n968), .CK(clk), .RN(n2352), .Q(
data_output[52]) );
DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(n966), .CK(clk), .RN(n2343), .Q(
data_output[53]) );
DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(n964), .CK(clk), .RN(n1502), .Q(
data_output[54]) );
DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(n962), .CK(clk), .RN(n2339), .Q(
data_output[55]) );
DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(n960), .CK(clk), .RN(n1489), .Q(
data_output[56]) );
DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(n958), .CK(clk), .RN(n2357), .Q(
data_output[57]) );
DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(n956), .CK(clk), .RN(n2351), .Q(
data_output[58]) );
DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(n954), .CK(clk), .RN(n2356), .Q(
data_output[59]) );
DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(n952), .CK(clk), .RN(n2296), .Q(
data_output[60]) );
DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(n950), .CK(clk), .RN(n2294), .Q(
data_output[61]) );
DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(n948), .CK(clk), .RN(n2313), .Q(
data_output[62]) );
DFFRXLTS d_ff5_data_out_Q_reg_63_ ( .D(n946), .CK(clk), .RN(n2296), .Q(
data_output[63]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_55_ ( .D(n589), .CK(clk), .RN(n2317), .Q(
d_ff2_X[55]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_59_ ( .D(n585), .CK(clk), .RN(n2294), .Q(
d_ff2_X[59]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_57_ ( .D(n587), .CK(clk), .RN(n2313), .Q(
d_ff2_X[57]) );
DFFRX4TS cordic_FSM_state_reg_reg_3_ ( .D(n1345), .CK(clk), .RN(n564), .Q(
cordic_FSM_state_reg[3]), .QN(n2229) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_61_ ( .D(n583), .CK(clk), .RN(n2296), .Q(
d_ff2_X[61]) );
DFFRX1TS reg_ch_mux_2_Q_reg_1_ ( .D(n1266), .CK(clk), .RN(n2342), .Q(
sel_mux_2_reg[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_54_ ( .D(n590), .CK(clk), .RN(n2334), .Q(
d_ff2_X[54]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_56_ ( .D(n588), .CK(clk), .RN(n2335), .Q(
d_ff2_X[56]), .QN(n1481) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_53_ ( .D(n719), .CK(clk), .RN(n2301), .Q(
d_ff2_Y[53]), .QN(n1480) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_54_ ( .D(n718), .CK(clk), .RN(n1493), .Q(
d_ff2_Y[54]) );
DFFRX1TS reg_ch_mux_1_Q_reg_0_ ( .D(n1268), .CK(clk), .RN(n2343), .Q(
sel_mux_1_reg) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_63_ ( .D(n826), .CK(clk), .RN(n2299), .Q(
d_ff2_Z[63]) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n1335), .CK(clk), .RN(n2350), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n2238) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_62_ ( .D(n582), .CK(clk), .RN(n2323), .Q(
d_ff2_X[62]) );
DFFRX1TS reg_ch_mux_3_Q_reg_0_ ( .D(n1269), .CK(clk), .RN(n1508), .Q(
sel_mux_3_reg) );
DFFRX1TS cont_var_count_reg_1_ ( .D(n1342), .CK(clk), .RN(n1510), .Q(
cont_var_out[1]), .QN(n1482) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n1336), .CK(clk), .RN(n2341), .Q(
d_ff1_operation_out), .QN(n2224) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_63_ ( .D(n698), .CK(clk), .RN(n2300), .Q(
d_ff2_Y[63]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_51_ ( .D(n722), .CK(clk), .RN(n2300), .Q(
d_ff2_Y[51]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_50_ ( .D(n724), .CK(clk), .RN(n2324), .Q(
d_ff2_Y[50]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_49_ ( .D(n726), .CK(clk), .RN(n2326), .Q(
d_ff2_Y[49]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_48_ ( .D(n728), .CK(clk), .RN(n2328), .Q(
d_ff2_Y[48]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_47_ ( .D(n730), .CK(clk), .RN(n2309), .Q(
d_ff2_Y[47]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_46_ ( .D(n732), .CK(clk), .RN(n2311), .Q(
d_ff2_Y[46]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_45_ ( .D(n734), .CK(clk), .RN(n2310), .Q(
d_ff2_Y[45]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_44_ ( .D(n736), .CK(clk), .RN(n2328), .Q(
d_ff2_Y[44]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_43_ ( .D(n738), .CK(clk), .RN(n2330), .Q(
d_ff2_Y[43]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_42_ ( .D(n740), .CK(clk), .RN(n1511), .Q(
d_ff2_Y[42]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_41_ ( .D(n742), .CK(clk), .RN(n2309), .Q(
d_ff2_Y[41]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_40_ ( .D(n744), .CK(clk), .RN(n2311), .Q(
d_ff2_Y[40]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_39_ ( .D(n746), .CK(clk), .RN(n2310), .Q(
d_ff2_Y[39]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_38_ ( .D(n748), .CK(clk), .RN(n2311), .Q(
d_ff2_Y[38]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_37_ ( .D(n750), .CK(clk), .RN(n2329), .Q(
d_ff2_Y[37]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_36_ ( .D(n752), .CK(clk), .RN(n2309), .Q(
d_ff2_Y[36]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_35_ ( .D(n754), .CK(clk), .RN(n2309), .Q(
d_ff2_Y[35]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_34_ ( .D(n756), .CK(clk), .RN(n2328), .Q(
d_ff2_Y[34]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_33_ ( .D(n758), .CK(clk), .RN(n2310), .Q(
d_ff2_Y[33]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_32_ ( .D(n760), .CK(clk), .RN(n2311), .Q(
d_ff2_Y[32]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n762), .CK(clk), .RN(n2310), .Q(
d_ff2_Y[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n764), .CK(clk), .RN(n2309), .Q(
d_ff2_Y[30]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n766), .CK(clk), .RN(n2328), .Q(
d_ff2_Y[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n768), .CK(clk), .RN(n2332), .Q(
d_ff2_Y[28]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n770), .CK(clk), .RN(n2331), .Q(
d_ff2_Y[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n772), .CK(clk), .RN(n2304), .Q(
d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n774), .CK(clk), .RN(n2332), .Q(
d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n776), .CK(clk), .RN(n2331), .Q(
d_ff2_Y[24]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n778), .CK(clk), .RN(n2332), .Q(
d_ff2_Y[23]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n780), .CK(clk), .RN(n2304), .Q(
d_ff2_Y[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n782), .CK(clk), .RN(n2331), .Q(
d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n784), .CK(clk), .RN(n2304), .Q(
d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n786), .CK(clk), .RN(n2303), .Q(
d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n788), .CK(clk), .RN(n2294), .Q(
d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n790), .CK(clk), .RN(n2313), .Q(
d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n792), .CK(clk), .RN(n2296), .Q(
d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n794), .CK(clk), .RN(n2312), .Q(
d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n796), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n798), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n800), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n802), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n804), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n806), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n808), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n810), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n812), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n814), .CK(clk), .RN(n2295), .Q(
d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n816), .CK(clk), .RN(n2297), .Q(
d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n818), .CK(clk), .RN(n2297), .Q(
d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n820), .CK(clk), .RN(n2297), .Q(
d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n822), .CK(clk), .RN(n2297), .Q(
d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n824), .CK(clk), .RN(n2297), .Q(
d_ff2_Y[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_49_ ( .D(n598), .CK(clk), .RN(n1513), .Q(
d_ff2_X[49]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_48_ ( .D(n600), .CK(clk), .RN(n2315), .Q(
d_ff2_X[48]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_46_ ( .D(n604), .CK(clk), .RN(n2314), .Q(
d_ff2_X[46]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_45_ ( .D(n606), .CK(clk), .RN(n1514), .Q(
d_ff2_X[45]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_43_ ( .D(n610), .CK(clk), .RN(n2335), .Q(
d_ff2_X[43]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_42_ ( .D(n612), .CK(clk), .RN(n2333), .Q(
d_ff2_X[42]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_41_ ( .D(n614), .CK(clk), .RN(n1514), .Q(
d_ff2_X[41]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_39_ ( .D(n618), .CK(clk), .RN(n1514), .Q(
d_ff2_X[39]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_36_ ( .D(n624), .CK(clk), .RN(n2333), .Q(
d_ff2_X[36]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_35_ ( .D(n626), .CK(clk), .RN(n2317), .Q(
d_ff2_X[35]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_34_ ( .D(n628), .CK(clk), .RN(n2318), .Q(
d_ff2_X[34]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_32_ ( .D(n632), .CK(clk), .RN(n2319), .Q(
d_ff2_X[32]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n634), .CK(clk), .RN(n2298), .Q(
d_ff2_X[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n638), .CK(clk), .RN(n2319), .Q(
d_ff2_X[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n640), .CK(clk), .RN(n2298), .Q(
d_ff2_X[28]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n644), .CK(clk), .RN(n2299), .Q(
d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n648), .CK(clk), .RN(n1494), .Q(
d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n658), .CK(clk), .RN(n2321), .Q(
d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n668), .CK(clk), .RN(n2321), .Q(
d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n670), .CK(clk), .RN(n2321), .Q(
d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n674), .CK(clk), .RN(n2321), .Q(
d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n678), .CK(clk), .RN(n2323), .Q(
d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n680), .CK(clk), .RN(n2323), .Q(
d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n682), .CK(clk), .RN(n2323), .Q(
d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n684), .CK(clk), .RN(n2323), .Q(
d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n690), .CK(clk), .RN(n2302), .Q(
d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n696), .CK(clk), .RN(n2320), .Q(
d_ff2_X[0]) );
DFFRX1TS d_ff4_Xn_Q_reg_60_ ( .D(n1077), .CK(clk), .RN(n2312), .Q(
d_ff_Xn[60]) );
DFFRX1TS d_ff4_Xn_Q_reg_58_ ( .D(n1079), .CK(clk), .RN(n2357), .Q(
d_ff_Xn[58]) );
DFFRX1TS d_ff4_Xn_Q_reg_56_ ( .D(n1081), .CK(clk), .RN(n1501), .Q(
d_ff_Xn[56]) );
DFFRX1TS d_ff4_Xn_Q_reg_54_ ( .D(n1083), .CK(clk), .RN(n2342), .Q(
d_ff_Xn[54]) );
DFFRX1TS d_ff4_Xn_Q_reg_53_ ( .D(n1084), .CK(clk), .RN(n2351), .Q(
d_ff_Xn[53]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_47_ ( .D(n602), .CK(clk), .RN(n2334), .Q(
d_ff2_X[47]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_44_ ( .D(n608), .CK(clk), .RN(n2316), .Q(
d_ff2_X[44]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_40_ ( .D(n616), .CK(clk), .RN(n2316), .Q(
d_ff2_X[40]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_38_ ( .D(n620), .CK(clk), .RN(n2316), .Q(
d_ff2_X[38]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_37_ ( .D(n622), .CK(clk), .RN(n2335), .Q(
d_ff2_X[37]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_33_ ( .D(n630), .CK(clk), .RN(n2299), .Q(
d_ff2_X[33]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n636), .CK(clk), .RN(n2318), .Q(
d_ff2_X[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n642), .CK(clk), .RN(n2318), .Q(
d_ff2_X[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n646), .CK(clk), .RN(n2319), .Q(
d_ff2_X[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n2325), .Q(
d_ff2_X[23]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n2325), .Q(
d_ff2_X[22]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n2302), .Q(
d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n656), .CK(clk), .RN(n2320), .Q(
d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n660), .CK(clk), .RN(n2321), .Q(
d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n662), .CK(clk), .RN(n2321), .Q(
d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n664), .CK(clk), .RN(n2321), .Q(
d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n666), .CK(clk), .RN(n2321), .Q(
d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n672), .CK(clk), .RN(n2321), .Q(
d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n676), .CK(clk), .RN(n2321), .Q(
d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n686), .CK(clk), .RN(n2323), .Q(
d_ff2_X[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n688), .CK(clk), .RN(n2301), .Q(
d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n692), .CK(clk), .RN(n1494), .Q(
d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n694), .CK(clk), .RN(n2324), .Q(
d_ff2_X[1]) );
DFFRX1TS d_ff4_Xn_Q_reg_63_ ( .D(n1074), .CK(clk), .RN(n2312), .Q(
d_ff_Xn[63]) );
DFFRX1TS d_ff4_Xn_Q_reg_52_ ( .D(n1085), .CK(clk), .RN(n2352), .Q(
d_ff_Xn[52]) );
DFFRX1TS d_ff4_Xn_Q_reg_51_ ( .D(n1086), .CK(clk), .RN(n2353), .Q(
d_ff_Xn[51]) );
DFFRX1TS d_ff4_Xn_Q_reg_50_ ( .D(n1087), .CK(clk), .RN(n1494), .Q(
d_ff_Xn[50]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_55_ ( .D(n717), .CK(clk), .RN(n2320), .Q(
d_ff2_Y[55]), .QN(n2232) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_59_ ( .D(n713), .CK(clk), .RN(n2302), .Q(
d_ff2_Y[59]), .QN(n2235) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_57_ ( .D(n715), .CK(clk), .RN(n2301), .Q(
d_ff2_Y[57]), .QN(n2233) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_61_ ( .D(n711), .CK(clk), .RN(n2325), .Q(
d_ff2_Y[61]), .QN(n2236) );
DFFRX1TS reg_LUT_Q_reg_3_ ( .D(n942), .CK(clk), .RN(n2327), .Q(
d_ff3_LUT_out[3]) );
DFFRX1TS reg_LUT_Q_reg_48_ ( .D(n897), .CK(clk), .RN(n2307), .Q(
d_ff3_LUT_out[48]) );
DFFRX4TS cont_iter_count_reg_2_ ( .D(n1339), .CK(clk), .RN(n2350), .Q(
cont_iter_out[2]), .QN(n2227) );
DFFRX1TS d_ff4_Xn_Q_reg_47_ ( .D(n1090), .CK(clk), .RN(n2366), .Q(
d_ff_Xn[47]) );
DFFRX1TS d_ff4_Xn_Q_reg_37_ ( .D(n1100), .CK(clk), .RN(n2354), .Q(
d_ff_Xn[37]) );
DFFRX1TS d_ff4_Xn_Q_reg_38_ ( .D(n1099), .CK(clk), .RN(n2354), .Q(
d_ff_Xn[38]) );
DFFRX1TS d_ff4_Xn_Q_reg_39_ ( .D(n1098), .CK(clk), .RN(n2354), .Q(
d_ff_Xn[39]) );
DFFRX1TS d_ff4_Xn_Q_reg_40_ ( .D(n1097), .CK(clk), .RN(n2354), .Q(
d_ff_Xn[40]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n1127), .CK(clk), .RN(n2365), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n1128), .CK(clk), .RN(n2361), .Q(d_ff_Xn[9])
);
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n1129), .CK(clk), .RN(n2360), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n1130), .CK(clk), .RN(n1506), .Q(d_ff_Xn[7])
);
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n1334), .CK(clk), .RN(n1508), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n2226) );
DFFRX1TS d_ff4_Xn_Q_reg_55_ ( .D(n1082), .CK(clk), .RN(n2366), .Q(
d_ff_Xn[55]) );
DFFRX1TS d_ff4_Xn_Q_reg_57_ ( .D(n1080), .CK(clk), .RN(n1510), .Q(
d_ff_Xn[57]) );
DFFRX1TS d_ff4_Xn_Q_reg_59_ ( .D(n1078), .CK(clk), .RN(n2352), .Q(
d_ff_Xn[59]) );
DFFRX1TS d_ff4_Xn_Q_reg_61_ ( .D(n1076), .CK(clk), .RN(n2296), .Q(
d_ff_Xn[61]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n1137), .CK(clk), .RN(n2348), .Q(d_ff_Xn[0])
);
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n1134), .CK(clk), .RN(n2358), .Q(d_ff_Xn[3])
);
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n1131), .CK(clk), .RN(n2362), .Q(d_ff_Xn[6])
);
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n1126), .CK(clk), .RN(n2364), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n1124), .CK(clk), .RN(n2308), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n1123), .CK(clk), .RN(n2363), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n1118), .CK(clk), .RN(n2359), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n1113), .CK(clk), .RN(n1507), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n1111), .CK(clk), .RN(n2364), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n1109), .CK(clk), .RN(n2338), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n1108), .CK(clk), .RN(n2336), .Q(
d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n1106), .CK(clk), .RN(n1501), .Q(
d_ff_Xn[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_32_ ( .D(n1105), .CK(clk), .RN(n2320), .Q(
d_ff_Xn[32]) );
DFFRX1TS d_ff4_Xn_Q_reg_34_ ( .D(n1103), .CK(clk), .RN(n2357), .Q(
d_ff_Xn[34]) );
DFFRX1TS d_ff4_Xn_Q_reg_35_ ( .D(n1102), .CK(clk), .RN(n2355), .Q(
d_ff_Xn[35]) );
DFFRX1TS d_ff4_Xn_Q_reg_36_ ( .D(n1101), .CK(clk), .RN(n2352), .Q(
d_ff_Xn[36]) );
DFFRX1TS d_ff4_Xn_Q_reg_41_ ( .D(n1096), .CK(clk), .RN(n1501), .Q(
d_ff_Xn[41]) );
DFFRX1TS d_ff4_Xn_Q_reg_42_ ( .D(n1095), .CK(clk), .RN(n2325), .Q(
d_ff_Xn[42]) );
DFFRX1TS d_ff4_Xn_Q_reg_43_ ( .D(n1094), .CK(clk), .RN(n1501), .Q(
d_ff_Xn[43]) );
DFFRX1TS d_ff4_Xn_Q_reg_45_ ( .D(n1092), .CK(clk), .RN(n2357), .Q(
d_ff_Xn[45]) );
DFFRX1TS d_ff4_Xn_Q_reg_46_ ( .D(n1091), .CK(clk), .RN(n2355), .Q(
d_ff_Xn[46]) );
DFFRX1TS d_ff4_Xn_Q_reg_48_ ( .D(n1089), .CK(clk), .RN(n2301), .Q(
d_ff_Xn[48]) );
DFFRX1TS d_ff4_Xn_Q_reg_49_ ( .D(n1088), .CK(clk), .RN(n1501), .Q(
d_ff_Xn[49]) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n1136), .CK(clk), .RN(n2358), .Q(d_ff_Xn[1])
);
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n1135), .CK(clk), .RN(n2358), .Q(d_ff_Xn[2])
);
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n1133), .CK(clk), .RN(n2363), .Q(d_ff_Xn[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n1132), .CK(clk), .RN(n2359), .Q(d_ff_Xn[5])
);
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n1125), .CK(clk), .RN(n1506), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n1122), .CK(clk), .RN(n2359), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n1121), .CK(clk), .RN(n2362), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n1120), .CK(clk), .RN(n2362), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n1119), .CK(clk), .RN(n2363), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n1117), .CK(clk), .RN(n2365), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n1116), .CK(clk), .RN(n2364), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n1115), .CK(clk), .RN(n1506), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n1114), .CK(clk), .RN(n2308), .Q(
d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n1112), .CK(clk), .RN(n2365), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n1110), .CK(clk), .RN(n1506), .Q(
d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n1107), .CK(clk), .RN(n2338), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_33_ ( .D(n1104), .CK(clk), .RN(n1501), .Q(
d_ff_Xn[33]) );
DFFRX1TS d_ff4_Xn_Q_reg_44_ ( .D(n1093), .CK(clk), .RN(n2352), .Q(
d_ff_Xn[44]) );
DFFRX1TS d_ff4_Xn_Q_reg_62_ ( .D(n1075), .CK(clk), .RN(n2312), .Q(
d_ff_Xn[62]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_50_ ( .D(n596), .CK(clk), .RN(n2315), .Q(
d_ff2_X[50]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_51_ ( .D(n594), .CK(clk), .RN(n1513), .Q(
d_ff2_X[51]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_63_ ( .D(n570), .CK(clk), .RN(n2312), .Q(
d_ff2_X[63]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_52_ ( .D(n720), .CK(clk), .RN(n2300), .Q(
d_ff2_Y[52]), .QN(n2234) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_58_ ( .D(n586), .CK(clk), .RN(n2313), .Q(
d_ff2_X[58]), .QN(n1483) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_60_ ( .D(n584), .CK(clk), .RN(n2294), .Q(
d_ff2_X[60]), .QN(n1485) );
DFFRX1TS reg_LUT_Q_reg_15_ ( .D(n930), .CK(clk), .RN(n2310), .Q(
d_ff3_LUT_out[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_57_ ( .D(n832), .CK(clk), .RN(n2299), .Q(
d_ff2_Z[57]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_59_ ( .D(n830), .CK(clk), .RN(n2319), .Q(
d_ff2_Z[59]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_61_ ( .D(n828), .CK(clk), .RN(n2299), .Q(
d_ff2_Z[61]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_62_ ( .D(n827), .CK(clk), .RN(n2298), .Q(
d_ff2_Z[62]) );
DFFRX1TS d_ff5_Q_reg_63_ ( .D(n947), .CK(clk), .RN(n2313), .Q(
data_output2_63_) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n888), .CK(clk), .RN(n2332), .Q(
d_ff2_Z[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n887), .CK(clk), .RN(n2331), .Q(
d_ff2_Z[2]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n886), .CK(clk), .RN(n2304), .Q(
d_ff2_Z[3]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n885), .CK(clk), .RN(n2332), .Q(
d_ff2_Z[4]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n884), .CK(clk), .RN(n2303), .Q(
d_ff2_Z[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n883), .CK(clk), .RN(n2307), .Q(
d_ff2_Z[6]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n882), .CK(clk), .RN(n2322), .Q(
d_ff2_Z[7]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n881), .CK(clk), .RN(n2306), .Q(
d_ff2_Z[8]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n880), .CK(clk), .RN(n2303), .Q(
d_ff2_Z[9]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n879), .CK(clk), .RN(n2307), .Q(
d_ff2_Z[10]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n878), .CK(clk), .RN(n2322), .Q(
d_ff2_Z[11]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n877), .CK(clk), .RN(n2306), .Q(
d_ff2_Z[12]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n876), .CK(clk), .RN(n2303), .Q(
d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n875), .CK(clk), .RN(n1493), .Q(
d_ff2_Z[14]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n874), .CK(clk), .RN(n2300), .Q(
d_ff2_Z[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n873), .CK(clk), .RN(n2320), .Q(
d_ff2_Z[16]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n872), .CK(clk), .RN(n2326), .Q(
d_ff2_Z[17]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n871), .CK(clk), .RN(n2324), .Q(
d_ff2_Z[18]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n870), .CK(clk), .RN(n2320), .Q(
d_ff2_Z[19]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n869), .CK(clk), .RN(n2325), .Q(
d_ff2_Z[20]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n868), .CK(clk), .RN(n1493), .Q(
d_ff2_Z[21]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n867), .CK(clk), .RN(n2300), .Q(
d_ff2_Z[22]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n866), .CK(clk), .RN(n2302), .Q(
d_ff2_Z[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n865), .CK(clk), .RN(n2325), .Q(
d_ff2_Z[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n864), .CK(clk), .RN(n1493), .Q(
d_ff2_Z[25]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n863), .CK(clk), .RN(n2300), .Q(
d_ff2_Z[26]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n862), .CK(clk), .RN(n2324), .Q(
d_ff2_Z[27]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n861), .CK(clk), .RN(n2301), .Q(
d_ff2_Z[28]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n860), .CK(clk), .RN(n2326), .Q(
d_ff2_Z[29]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n859), .CK(clk), .RN(n2302), .Q(
d_ff2_Z[30]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n858), .CK(clk), .RN(n2302), .Q(
d_ff2_Z[31]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_32_ ( .D(n857), .CK(clk), .RN(n2325), .Q(
d_ff2_Z[32]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_33_ ( .D(n856), .CK(clk), .RN(n2324), .Q(
d_ff2_Z[33]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_34_ ( .D(n855), .CK(clk), .RN(n2324), .Q(
d_ff2_Z[34]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_35_ ( .D(n854), .CK(clk), .RN(n2301), .Q(
d_ff2_Z[35]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_36_ ( .D(n853), .CK(clk), .RN(n2326), .Q(
d_ff2_Z[36]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_37_ ( .D(n852), .CK(clk), .RN(n2326), .Q(
d_ff2_Z[37]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_38_ ( .D(n851), .CK(clk), .RN(n1493), .Q(
d_ff2_Z[38]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_39_ ( .D(n850), .CK(clk), .RN(n2300), .Q(
d_ff2_Z[39]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_40_ ( .D(n849), .CK(clk), .RN(n2326), .Q(
d_ff2_Z[40]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_41_ ( .D(n848), .CK(clk), .RN(n2320), .Q(
d_ff2_Z[41]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_42_ ( .D(n847), .CK(clk), .RN(n1493), .Q(
d_ff2_Z[42]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_43_ ( .D(n846), .CK(clk), .RN(n2300), .Q(
d_ff2_Z[43]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_44_ ( .D(n845), .CK(clk), .RN(n2318), .Q(
d_ff2_Z[44]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_45_ ( .D(n844), .CK(clk), .RN(n2299), .Q(
d_ff2_Z[45]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_46_ ( .D(n843), .CK(clk), .RN(n2298), .Q(
d_ff2_Z[46]) );
DFFRX2TS cordic_FSM_state_reg_reg_2_ ( .D(n1344), .CK(clk), .RN(n564), .Q(
cordic_FSM_state_reg[2]), .QN(n2225) );
DFFRX1TS cont_iter_count_reg_1_ ( .D(n1340), .CK(clk), .RN(n1509), .Q(n1477),
.QN(n1479) );
DFFRXLTS d_ff5_Q_reg_37_ ( .D(n999), .CK(clk), .RN(n2354), .Q(
sign_inv_out[37]) );
DFFRXLTS d_ff5_Q_reg_38_ ( .D(n997), .CK(clk), .RN(n2354), .Q(
sign_inv_out[38]) );
DFFRXLTS d_ff5_Q_reg_39_ ( .D(n995), .CK(clk), .RN(n2354), .Q(
sign_inv_out[39]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(n1055), .CK(clk), .RN(n2308), .Q(
sign_inv_out[9]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(n1057), .CK(clk), .RN(n2364), .Q(
sign_inv_out[8]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(n1059), .CK(clk), .RN(n1507), .Q(
sign_inv_out[7]) );
DFFRX4TS cont_iter_count_reg_0_ ( .D(n1341), .CK(clk), .RN(n2339), .Q(
cont_iter_out[0]), .QN(n1484) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_52_ ( .D(n592), .CK(clk), .RN(n2333), .Q(
d_ff2_X[52]) );
DFFRX2TS cordic_FSM_state_reg_reg_0_ ( .D(n1343), .CK(clk), .RN(n564), .Q(
cordic_FSM_state_reg[0]), .QN(n2223) );
AOI222X1TS U1472 ( .A0(n1844), .A1(d_ff2_Z[60]), .B0(n1736), .B1(d_ff1_Z[60]), .C0(d_ff_Zn[60]), .C1(n1842), .Y(n1826) );
AOI222X1TS U1473 ( .A0(n1837), .A1(d_ff2_Z[56]), .B0(n1736), .B1(d_ff1_Z[56]), .C0(d_ff_Zn[56]), .C1(n1842), .Y(n1832) );
AOI222X1TS U1474 ( .A0(n1844), .A1(d_ff2_Z[58]), .B0(n1683), .B1(d_ff1_Z[58]), .C0(d_ff_Zn[58]), .C1(n1840), .Y(n1830) );
AOI32X1TS U1475 ( .A0(n2064), .A1(n2089), .A2(n2195), .B0(d_ff3_LUT_out[0]),
.B1(n2044), .Y(n2024) );
AOI222X1TS U1476 ( .A0(n1837), .A1(d_ff2_Z[55]), .B0(n1821), .B1(d_ff1_Z[55]), .C0(d_ff_Zn[55]), .C1(n1840), .Y(n1838) );
AOI222X1TS U1477 ( .A0(n1837), .A1(d_ff2_Z[52]), .B0(n1719), .B1(d_ff1_Z[52]), .C0(d_ff_Zn[52]), .C1(n1817), .Y(n1706) );
AOI222X1TS U1478 ( .A0(n1837), .A1(d_ff2_Z[53]), .B0(n1719), .B1(d_ff1_Z[53]), .C0(d_ff_Zn[53]), .C1(n1817), .Y(n1704) );
AOI222X1TS U1479 ( .A0(d_ff2_Z[54]), .A1(n1789), .B0(d_ff2_Y[54]), .B1(n1497), .C0(d_ff2_X[54]), .C1(n1889), .Y(n1790) );
AOI222X1TS U1480 ( .A0(d_ff2_Z[51]), .A1(n1789), .B0(d_ff2_Y[51]), .B1(n1497), .C0(d_ff2_X[51]), .C1(n1889), .Y(n1788) );
AOI222X1TS U1481 ( .A0(d_ff2_Z[0]), .A1(n1789), .B0(d_ff2_Y[0]), .B1(n1887),
.C0(d_ff2_X[0]), .C1(n1889), .Y(n1785) );
AOI222X1TS U1482 ( .A0(d_ff2_Z[47]), .A1(n1789), .B0(d_ff2_Y[47]), .B1(n1782), .C0(d_ff2_X[47]), .C1(n1889), .Y(n1783) );
AOI222X1TS U1483 ( .A0(d_ff2_Z[48]), .A1(n1789), .B0(d_ff2_Y[48]), .B1(n1871), .C0(d_ff2_X[48]), .C1(n1889), .Y(n1787) );
AOI222X1TS U1484 ( .A0(d_ff2_Z[49]), .A1(n1789), .B0(d_ff2_Y[49]), .B1(n1871), .C0(d_ff2_X[49]), .C1(n1889), .Y(n1784) );
AOI222X1TS U1485 ( .A0(d_ff2_Z[50]), .A1(n1789), .B0(d_ff2_Y[50]), .B1(n1871), .C0(d_ff2_X[50]), .C1(n1889), .Y(n1786) );
AOI222X1TS U1486 ( .A0(d_ff3_LUT_out[50]), .A1(n1892), .B0(n1887), .B1(
d_ff3_sh_x_out[50]), .C0(n1886), .C1(d_ff3_sh_y_out[50]), .Y(n1888) );
AOI222X1TS U1487 ( .A0(d_ff3_LUT_out[47]), .A1(n1892), .B0(n1887), .B1(
d_ff3_sh_x_out[47]), .C0(n1886), .C1(d_ff3_sh_y_out[47]), .Y(n1884) );
AOI222X1TS U1488 ( .A0(d_ff3_LUT_out[43]), .A1(n1892), .B0(n1887), .B1(
d_ff3_sh_x_out[43]), .C0(n1886), .C1(d_ff3_sh_y_out[43]), .Y(n1883) );
AOI222X1TS U1489 ( .A0(d_ff3_LUT_out[45]), .A1(n1892), .B0(n1887), .B1(
d_ff3_sh_x_out[45]), .C0(n1886), .C1(d_ff3_sh_y_out[45]), .Y(n1882) );
AOI222X1TS U1490 ( .A0(d_ff3_LUT_out[55]), .A1(n1892), .B0(
d_ff3_sh_y_out[55]), .B1(n1889), .C0(d_ff3_sh_x_out[55]), .C1(n1806),
.Y(n1890) );
AOI222X1TS U1491 ( .A0(d_ff3_LUT_out[54]), .A1(n1892), .B0(n1887), .B1(
d_ff3_sh_x_out[54]), .C0(n1889), .C1(d_ff3_sh_y_out[54]), .Y(n1885) );
AOI222X1TS U1492 ( .A0(d_ff3_LUT_out[1]), .A1(n1873), .B0(n1893), .B1(
d_ff3_sh_x_out[1]), .C0(n1894), .C1(d_ff3_sh_y_out[1]), .Y(n1864) );
AOI222X1TS U1493 ( .A0(d_ff3_LUT_out[6]), .A1(n1873), .B0(n1498), .B1(
d_ff3_sh_x_out[6]), .C0(n1894), .C1(d_ff3_sh_y_out[6]), .Y(n1869) );
AOI222X1TS U1494 ( .A0(d_ff3_LUT_out[7]), .A1(n1873), .B0(n1782), .B1(
d_ff3_sh_x_out[7]), .C0(n1894), .C1(d_ff3_sh_y_out[7]), .Y(n1872) );
AOI222X1TS U1495 ( .A0(d_ff3_LUT_out[5]), .A1(n1873), .B0(n1893), .B1(
d_ff3_sh_x_out[5]), .C0(n1894), .C1(d_ff3_sh_y_out[5]), .Y(n1870) );
AOI222X1TS U1496 ( .A0(d_ff3_LUT_out[0]), .A1(n1873), .B0(n1498), .B1(
d_ff3_sh_x_out[0]), .C0(n1894), .C1(d_ff3_sh_y_out[0]), .Y(n1862) );
AOI222X1TS U1497 ( .A0(d_ff3_LUT_out[9]), .A1(n1873), .B0(n1782), .B1(
d_ff3_sh_x_out[9]), .C0(n1867), .C1(d_ff3_sh_y_out[9]), .Y(n1868) );
AOI222X1TS U1498 ( .A0(d_ff3_LUT_out[39]), .A1(n1881), .B0(n1852), .B1(
d_ff3_sh_x_out[39]), .C0(n1886), .C1(d_ff3_sh_y_out[39]), .Y(n1849) );
AOI222X1TS U1499 ( .A0(d_ff3_LUT_out[27]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[27]), .C0(n1812), .C1(d_ff3_sh_y_out[27]), .Y(n1815) );
AOI222X1TS U1500 ( .A0(d_ff3_LUT_out[25]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[25]), .C0(n1812), .C1(d_ff3_sh_y_out[25]), .Y(n1808) );
AOI222X1TS U1501 ( .A0(d_ff3_LUT_out[29]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[29]), .C0(n1851), .C1(d_ff3_sh_y_out[29]), .Y(n1767) );
AOI222X1TS U1502 ( .A0(d_ff3_LUT_out[33]), .A1(n1881), .B0(n1852), .B1(
d_ff3_sh_x_out[33]), .C0(n1851), .C1(d_ff3_sh_y_out[33]), .Y(n1853) );
AOI222X1TS U1503 ( .A0(d_ff3_LUT_out[26]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[26]), .C0(n1812), .C1(d_ff3_sh_y_out[26]), .Y(n1805) );
AOI222X1TS U1504 ( .A0(d_ff2_Z[9]), .A1(n1881), .B0(d_ff2_Y[9]), .B1(n1854),
.C0(d_ff2_X[9]), .C1(n1910), .Y(n1855) );
AOI222X1TS U1505 ( .A0(d_ff3_LUT_out[14]), .A1(n1810), .B0(n1498), .B1(
d_ff3_sh_x_out[14]), .C0(n1867), .C1(d_ff3_sh_y_out[14]), .Y(n1796) );
AOI222X1TS U1506 ( .A0(d_ff3_LUT_out[11]), .A1(n1810), .B0(n1893), .B1(
d_ff3_sh_x_out[11]), .C0(n1867), .C1(d_ff3_sh_y_out[11]), .Y(n1811) );
INVX2TS U1507 ( .A(n1906), .Y(n1727) );
NAND2X1TS U1508 ( .A(n2139), .B(n2138), .Y(n2142) );
CMPR32X2TS U1509 ( .A(d_ff2_Y[54]), .B(n1491), .C(n1534), .CO(n1550), .S(
n1535) );
CMPR32X2TS U1510 ( .A(n1491), .B(d_ff2_X[54]), .C(n2193), .CO(n2197), .S(
n2194) );
INVX4TS U1511 ( .A(cont_iter_out[0]), .Y(n2188) );
NOR2X1TS U1512 ( .A(sel_mux_1_reg), .B(n2187), .Y(n1664) );
AOI31XLTS U1513 ( .A0(n1505), .A1(n1678), .A2(n2227), .B0(n1937), .Y(n1679)
);
NAND2BX1TS U1514 ( .AN(n2050), .B(n2083), .Y(n2079) );
NAND2X2TS U1515 ( .A(n2141), .B(n2127), .Y(n2144) );
AO22XLTS U1516 ( .A0(n2221), .A1(n2140), .B0(n2152), .B1(d_ff3_sh_y_out[56]),
.Y(n705) );
AO22XLTS U1517 ( .A0(n2204), .A1(n2199), .B0(n2220), .B1(d_ff3_sh_x_out[56]),
.Y(n577) );
AOI222X1TS U1518 ( .A0(n2187), .A1(d_ff2_Z[3]), .B0(n1821), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n2118), .Y(n1737) );
AOI222X1TS U1519 ( .A0(n2187), .A1(d_ff2_Z[4]), .B0(n1821), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n2118), .Y(n1741) );
AO22XLTS U1520 ( .A0(n2119), .A1(d_ff2_Y[42]), .B0(n2117), .B1(
d_ff3_sh_y_out[42]), .Y(n739) );
AO22XLTS U1521 ( .A0(n2119), .A1(d_ff2_Y[40]), .B0(n2117), .B1(
d_ff3_sh_y_out[40]), .Y(n743) );
AO22XLTS U1522 ( .A0(n2110), .A1(d_ff2_Y[18]), .B0(n2109), .B1(
d_ff3_sh_y_out[18]), .Y(n787) );
AO22XLTS U1523 ( .A0(n2110), .A1(d_ff2_Y[23]), .B0(n2109), .B1(
d_ff3_sh_y_out[23]), .Y(n777) );
AO22XLTS U1524 ( .A0(n2115), .A1(d_ff2_Y[38]), .B0(n2117), .B1(
d_ff3_sh_y_out[38]), .Y(n747) );
AO22XLTS U1525 ( .A0(n2115), .A1(d_ff2_Y[37]), .B0(n2117), .B1(
d_ff3_sh_y_out[37]), .Y(n749) );
AO22XLTS U1526 ( .A0(n2115), .A1(d_ff2_Y[36]), .B0(n2117), .B1(
d_ff3_sh_y_out[36]), .Y(n751) );
AO22XLTS U1527 ( .A0(n2115), .A1(d_ff2_Y[35]), .B0(n2117), .B1(
d_ff3_sh_y_out[35]), .Y(n753) );
AOI222X1TS U1528 ( .A0(n2187), .A1(d_ff2_Z[5]), .B0(n1736), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n2118), .Y(n1686) );
AO22XLTS U1529 ( .A0(n2104), .A1(d_ff2_Y[2]), .B0(n2103), .B1(
d_ff3_sh_y_out[2]), .Y(n819) );
AO22XLTS U1530 ( .A0(n2110), .A1(d_ff2_Y[24]), .B0(n2109), .B1(
d_ff3_sh_y_out[24]), .Y(n775) );
AO22XLTS U1531 ( .A0(n2104), .A1(d_ff2_Y[4]), .B0(n2103), .B1(
d_ff3_sh_y_out[4]), .Y(n815) );
AO22XLTS U1532 ( .A0(n2110), .A1(d_ff2_Y[22]), .B0(n2109), .B1(
d_ff3_sh_y_out[22]), .Y(n779) );
AO22XLTS U1533 ( .A0(n2110), .A1(d_ff2_Y[21]), .B0(n2109), .B1(
d_ff3_sh_y_out[21]), .Y(n781) );
AO22XLTS U1534 ( .A0(n2221), .A1(d_ff2_Y[20]), .B0(n2109), .B1(
d_ff3_sh_y_out[20]), .Y(n783) );
AO22XLTS U1535 ( .A0(n2115), .A1(d_ff2_Y[16]), .B0(n2109), .B1(
d_ff3_sh_y_out[16]), .Y(n791) );
AO22XLTS U1536 ( .A0(n2107), .A1(d_ff2_Y[17]), .B0(n2109), .B1(
d_ff3_sh_y_out[17]), .Y(n789) );
AO22XLTS U1537 ( .A0(n2206), .A1(n2080), .B0(n2103), .B1(d_ff3_LUT_out[37]),
.Y(n908) );
AO22XLTS U1538 ( .A0(n2104), .A1(n2101), .B0(n2103), .B1(d_ff3_LUT_out[56]),
.Y(n890) );
AO22XLTS U1539 ( .A0(d_ff_Yn[46]), .A1(n2186), .B0(d_ff2_Y[46]), .B1(n2218),
.Y(n732) );
AO22XLTS U1540 ( .A0(d_ff_Yn[47]), .A1(n2186), .B0(d_ff2_Y[47]), .B1(n2218),
.Y(n730) );
AO22XLTS U1541 ( .A0(n2104), .A1(n2077), .B0(n2103), .B1(d_ff3_LUT_out[24]),
.Y(n921) );
AO22XLTS U1542 ( .A0(d_ff_Yn[48]), .A1(n2186), .B0(d_ff2_Y[48]), .B1(n2218),
.Y(n728) );
AO22XLTS U1543 ( .A0(d_ff_Yn[50]), .A1(n2186), .B0(d_ff2_Y[50]), .B1(n2155),
.Y(n724) );
AO22XLTS U1544 ( .A0(d_ff_Yn[49]), .A1(n2186), .B0(d_ff2_Y[49]), .B1(n2218),
.Y(n726) );
AO22XLTS U1545 ( .A0(n2204), .A1(n2192), .B0(n2220), .B1(d_ff3_sh_x_out[53]),
.Y(n580) );
AO22XLTS U1546 ( .A0(d_ff_Yn[22]), .A1(n2114), .B0(d_ff2_Y[22]), .B1(n2111),
.Y(n780) );
AO22XLTS U1547 ( .A0(d_ff_Yn[21]), .A1(n2114), .B0(d_ff2_Y[21]), .B1(n2111),
.Y(n782) );
AO22XLTS U1548 ( .A0(d_ff_Yn[23]), .A1(n2172), .B0(d_ff2_Y[23]), .B1(n2111),
.Y(n778) );
AO22XLTS U1549 ( .A0(d_ff_Yn[24]), .A1(n2172), .B0(d_ff2_Y[24]), .B1(n2111),
.Y(n776) );
AO22XLTS U1550 ( .A0(d_ff_Yn[25]), .A1(n2172), .B0(d_ff2_Y[25]), .B1(n2111),
.Y(n774) );
AO22XLTS U1551 ( .A0(n2110), .A1(d_ff2_Y[28]), .B0(n2113), .B1(
d_ff3_sh_y_out[28]), .Y(n767) );
AO22XLTS U1552 ( .A0(n2119), .A1(d_ff2_Y[30]), .B0(n2113), .B1(
d_ff3_sh_y_out[30]), .Y(n763) );
AO22XLTS U1553 ( .A0(n2115), .A1(d_ff2_Y[31]), .B0(n2113), .B1(
d_ff3_sh_y_out[31]), .Y(n761) );
AO22XLTS U1554 ( .A0(n2115), .A1(d_ff2_Y[32]), .B0(n2113), .B1(
d_ff3_sh_y_out[32]), .Y(n759) );
AO22XLTS U1555 ( .A0(n2115), .A1(d_ff2_Y[34]), .B0(n2113), .B1(
d_ff3_sh_y_out[34]), .Y(n755) );
INVX3TS U1556 ( .A(n2185), .Y(n1739) );
INVX3TS U1557 ( .A(n2131), .Y(n1819) );
NAND3X1TS U1558 ( .A(cont_iter_out[2]), .B(n2076), .C(n1496), .Y(n2071) );
INVX3TS U1559 ( .A(n2131), .Y(n1835) );
INVX3TS U1560 ( .A(n2131), .Y(n1817) );
NOR2X1TS U1561 ( .A(n2089), .B(d_ff3_LUT_out[55]), .Y(n1700) );
AOI222X1TS U1562 ( .A0(d_ff3_LUT_out[3]), .A1(n1873), .B0(n1498), .B1(
d_ff3_sh_x_out[3]), .C0(n1894), .C1(d_ff3_sh_y_out[3]), .Y(n1865) );
AO22XLTS U1563 ( .A0(d_ff_Xn[4]), .A1(n2168), .B0(d_ff2_X[4]), .B1(n2155),
.Y(n688) );
AO22XLTS U1564 ( .A0(d_ff_Xn[10]), .A1(n2168), .B0(d_ff2_X[10]), .B1(n2155),
.Y(n676) );
AO22XLTS U1565 ( .A0(d_ff_Yn[29]), .A1(n2112), .B0(d_ff2_Y[29]), .B1(n2111),
.Y(n766) );
AO22XLTS U1566 ( .A0(d_ff_Xn[5]), .A1(n2168), .B0(d_ff2_X[5]), .B1(n2155),
.Y(n686) );
AO22XLTS U1567 ( .A0(d_ff_Xn[2]), .A1(n2168), .B0(d_ff2_X[2]), .B1(n2155),
.Y(n692) );
AO22XLTS U1568 ( .A0(d_ff_Yn[32]), .A1(n2112), .B0(d_ff2_Y[32]), .B1(n2116),
.Y(n760) );
AO22XLTS U1569 ( .A0(d_ff_Xn[44]), .A1(n2168), .B0(d_ff2_X[44]), .B1(n2218),
.Y(n608) );
AO22XLTS U1570 ( .A0(d_ff_Yn[27]), .A1(n2112), .B0(d_ff2_Y[27]), .B1(n2111),
.Y(n770) );
AO22XLTS U1571 ( .A0(d_ff_Yn[35]), .A1(n2114), .B0(d_ff2_Y[35]), .B1(n2116),
.Y(n754) );
AO22XLTS U1572 ( .A0(d_ff_Xn[12]), .A1(n2168), .B0(d_ff2_X[12]), .B1(n2155),
.Y(n672) );
AO22XLTS U1573 ( .A0(d_ff_Yn[33]), .A1(n2114), .B0(d_ff2_Y[33]), .B1(n2116),
.Y(n758) );
AO22XLTS U1574 ( .A0(d_ff_Yn[31]), .A1(n2112), .B0(d_ff2_Y[31]), .B1(n2116),
.Y(n762) );
AO22XLTS U1575 ( .A0(d_ff_Yn[30]), .A1(n2112), .B0(d_ff2_Y[30]), .B1(n2111),
.Y(n764) );
AO22XLTS U1576 ( .A0(d_ff_Yn[28]), .A1(n2112), .B0(d_ff2_Y[28]), .B1(n2111),
.Y(n768) );
AO22XLTS U1577 ( .A0(d_ff_Yn[26]), .A1(n2112), .B0(d_ff2_Y[26]), .B1(n2111),
.Y(n772) );
AO22XLTS U1578 ( .A0(d_ff_Yn[34]), .A1(n2114), .B0(d_ff2_Y[34]), .B1(n2116),
.Y(n756) );
AO22X1TS U1579 ( .A0(n2101), .A1(n2231), .B0(n1476), .B1(n1989), .Y(n1900)
);
AOI222X1TS U1580 ( .A0(d_ff3_LUT_out[15]), .A1(n1810), .B0(n1498), .B1(
d_ff3_sh_x_out[15]), .C0(n1867), .C1(d_ff3_sh_y_out[15]), .Y(n1803) );
INVX2TS U1581 ( .A(n2153), .Y(n2213) );
INVX2TS U1582 ( .A(n2153), .Y(n2076) );
INVX1TS U1583 ( .A(n2082), .Y(n2054) );
INVX3TS U1584 ( .A(n2153), .Y(n2065) );
INVX3TS U1585 ( .A(n2153), .Y(n2089) );
NAND2XLTS U1586 ( .A(sel_mux_2_reg[1]), .B(n2366), .Y(n1545) );
NAND2X1TS U1587 ( .A(n2040), .B(n2188), .Y(n2037) );
CLKBUFX3TS U1588 ( .A(n1950), .Y(n1940) );
BUFX3TS U1589 ( .A(n1560), .Y(n1475) );
INVX3TS U1590 ( .A(n2176), .Y(n2187) );
INVX3TS U1591 ( .A(n1880), .Y(n1776) );
INVX3TS U1592 ( .A(n1880), .Y(n1852) );
NOR2X4TS U1593 ( .A(sel_mux_3_reg), .B(n1605), .Y(n1555) );
OR3X2TS U1594 ( .A(n2225), .B(n2229), .C(n1929), .Y(n2008) );
CLKINVX2TS U1595 ( .A(n1519), .Y(n2211) );
NAND3X2TS U1596 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[3]),
.C(n1932), .Y(n1605) );
OAI211X4TS U1597 ( .A0(n2032), .A1(n1682), .B0(n1681), .C0(n1680), .Y(n934)
);
INVX2TS U1598 ( .A(n2188), .Y(n2100) );
BUFX3TS U1599 ( .A(n1792), .Y(n1881) );
BUFX3TS U1600 ( .A(n1860), .Y(n1877) );
INVX2TS U1601 ( .A(cordic_FSM_state_reg[2]), .Y(n1486) );
NAND4BXLTS U1602 ( .AN(ack_cordic), .B(n1512), .C(cordic_FSM_state_reg[2]),
.D(n2222), .Y(n1934) );
NAND2X1TS U1603 ( .A(n2208), .B(n1485), .Y(n2210) );
NAND2X1TS U1604 ( .A(n2202), .B(n1483), .Y(n2205) );
NAND2X1TS U1605 ( .A(n1481), .B(n2198), .Y(n2200) );
NAND2X1TS U1606 ( .A(n2147), .B(n2146), .Y(n2150) );
AO22XLTS U1607 ( .A0(n2006), .A1(result_add_subt[62]), .B0(n2005), .B1(
d_ff_Xn[62]), .Y(n1075) );
AO22XLTS U1608 ( .A0(n2001), .A1(result_add_subt[44]), .B0(n1999), .B1(
d_ff_Xn[44]), .Y(n1093) );
AO22XLTS U1609 ( .A0(n1998), .A1(result_add_subt[33]), .B0(n1997), .B1(
d_ff_Xn[33]), .Y(n1104) );
AO22XLTS U1610 ( .A0(n1998), .A1(result_add_subt[30]), .B0(n1997), .B1(
d_ff_Xn[30]), .Y(n1107) );
AO22XLTS U1611 ( .A0(n1996), .A1(result_add_subt[27]), .B0(n1995), .B1(
d_ff_Xn[27]), .Y(n1110) );
AO22XLTS U1612 ( .A0(n1996), .A1(result_add_subt[23]), .B0(n1995), .B1(
d_ff_Xn[23]), .Y(n1114) );
AO22XLTS U1613 ( .A0(n1996), .A1(result_add_subt[22]), .B0(n1995), .B1(
d_ff_Xn[22]), .Y(n1115) );
AO22XLTS U1614 ( .A0(n1996), .A1(result_add_subt[21]), .B0(n1995), .B1(
d_ff_Xn[21]), .Y(n1116) );
AO22XLTS U1615 ( .A0(n1996), .A1(result_add_subt[20]), .B0(n1995), .B1(
d_ff_Xn[20]), .Y(n1117) );
AO22XLTS U1616 ( .A0(n1994), .A1(result_add_subt[18]), .B0(n1993), .B1(
d_ff_Xn[18]), .Y(n1119) );
AO22XLTS U1617 ( .A0(n1994), .A1(result_add_subt[17]), .B0(n1993), .B1(
d_ff_Xn[17]), .Y(n1120) );
AO22XLTS U1618 ( .A0(n1994), .A1(result_add_subt[16]), .B0(n1993), .B1(
d_ff_Xn[16]), .Y(n1121) );
AO22XLTS U1619 ( .A0(n1994), .A1(result_add_subt[15]), .B0(n1993), .B1(
d_ff_Xn[15]), .Y(n1122) );
AO22XLTS U1620 ( .A0(n1992), .A1(result_add_subt[4]), .B0(n2000), .B1(
d_ff_Xn[4]), .Y(n1133) );
AO22XLTS U1621 ( .A0(n1992), .A1(result_add_subt[2]), .B0(n2000), .B1(
d_ff_Xn[2]), .Y(n1135) );
AO22XLTS U1622 ( .A0(n1992), .A1(result_add_subt[1]), .B0(n2004), .B1(
d_ff_Xn[1]), .Y(n1136) );
AO22XLTS U1623 ( .A0(n2001), .A1(result_add_subt[49]), .B0(n2002), .B1(
d_ff_Xn[49]), .Y(n1088) );
AO22XLTS U1624 ( .A0(n2001), .A1(result_add_subt[48]), .B0(n1999), .B1(
d_ff_Xn[48]), .Y(n1089) );
AO22XLTS U1625 ( .A0(n2001), .A1(result_add_subt[46]), .B0(n1999), .B1(
d_ff_Xn[46]), .Y(n1091) );
AO22XLTS U1626 ( .A0(n2001), .A1(result_add_subt[45]), .B0(n1999), .B1(
d_ff_Xn[45]), .Y(n1092) );
AO22XLTS U1627 ( .A0(n2001), .A1(result_add_subt[43]), .B0(n1999), .B1(
d_ff_Xn[43]), .Y(n1094) );
AO22XLTS U1628 ( .A0(n2001), .A1(result_add_subt[42]), .B0(n1999), .B1(
d_ff_Xn[42]), .Y(n1095) );
AO22XLTS U1629 ( .A0(n2001), .A1(result_add_subt[41]), .B0(n1999), .B1(
d_ff_Xn[41]), .Y(n1096) );
AO22XLTS U1630 ( .A0(n1998), .A1(result_add_subt[36]), .B0(n1997), .B1(
d_ff_Xn[36]), .Y(n1101) );
AO22XLTS U1631 ( .A0(n1998), .A1(result_add_subt[35]), .B0(n1997), .B1(
d_ff_Xn[35]), .Y(n1102) );
AO22XLTS U1632 ( .A0(n1998), .A1(result_add_subt[34]), .B0(n1997), .B1(
d_ff_Xn[34]), .Y(n1103) );
AO22XLTS U1633 ( .A0(n1998), .A1(result_add_subt[32]), .B0(n1997), .B1(
d_ff_Xn[32]), .Y(n1105) );
AO22XLTS U1634 ( .A0(n1998), .A1(result_add_subt[31]), .B0(n1997), .B1(
d_ff_Xn[31]), .Y(n1106) );
AO22XLTS U1635 ( .A0(n1996), .A1(result_add_subt[29]), .B0(n1997), .B1(
d_ff_Xn[29]), .Y(n1108) );
AO22XLTS U1636 ( .A0(n1996), .A1(result_add_subt[28]), .B0(n1995), .B1(
d_ff_Xn[28]), .Y(n1109) );
AO22XLTS U1637 ( .A0(n1996), .A1(result_add_subt[26]), .B0(n1995), .B1(
d_ff_Xn[26]), .Y(n1111) );
AO22XLTS U1638 ( .A0(n1996), .A1(result_add_subt[24]), .B0(n1995), .B1(
d_ff_Xn[24]), .Y(n1113) );
AO22XLTS U1639 ( .A0(n1994), .A1(result_add_subt[19]), .B0(n1995), .B1(
d_ff_Xn[19]), .Y(n1118) );
AO22XLTS U1640 ( .A0(n1994), .A1(result_add_subt[14]), .B0(n1993), .B1(
d_ff_Xn[14]), .Y(n1123) );
AO22XLTS U1641 ( .A0(n1994), .A1(result_add_subt[13]), .B0(n1993), .B1(
d_ff_Xn[13]), .Y(n1124) );
AO22XLTS U1642 ( .A0(n1994), .A1(result_add_subt[11]), .B0(n1993), .B1(
d_ff_Xn[11]), .Y(n1126) );
AO22XLTS U1643 ( .A0(n1992), .A1(result_add_subt[6]), .B0(n2000), .B1(
d_ff_Xn[6]), .Y(n1131) );
AO22XLTS U1644 ( .A0(n1992), .A1(result_add_subt[3]), .B0(n2000), .B1(
d_ff_Xn[3]), .Y(n1134) );
AO22XLTS U1645 ( .A0(n1992), .A1(result_add_subt[0]), .B0(n2005), .B1(
d_ff_Xn[0]), .Y(n1137) );
AO22XLTS U1646 ( .A0(n2006), .A1(result_add_subt[61]), .B0(n2005), .B1(
d_ff_Xn[61]), .Y(n1076) );
AO22XLTS U1647 ( .A0(n2003), .A1(result_add_subt[59]), .B0(n2005), .B1(
d_ff_Xn[59]), .Y(n1078) );
AO22XLTS U1648 ( .A0(n2003), .A1(result_add_subt[57]), .B0(n2002), .B1(
d_ff_Xn[57]), .Y(n1080) );
AO22XLTS U1649 ( .A0(n2003), .A1(result_add_subt[55]), .B0(n2002), .B1(
d_ff_Xn[55]), .Y(n1082) );
AO22XLTS U1650 ( .A0(n1992), .A1(result_add_subt[7]), .B0(n2000), .B1(
d_ff_Xn[7]), .Y(n1130) );
AO22XLTS U1651 ( .A0(n1992), .A1(result_add_subt[8]), .B0(n2000), .B1(
d_ff_Xn[8]), .Y(n1129) );
AO22XLTS U1652 ( .A0(n1992), .A1(result_add_subt[9]), .B0(n1993), .B1(
d_ff_Xn[9]), .Y(n1128) );
AO22XLTS U1653 ( .A0(n1994), .A1(result_add_subt[10]), .B0(n1993), .B1(
d_ff_Xn[10]), .Y(n1127) );
AO22XLTS U1654 ( .A0(n2001), .A1(result_add_subt[40]), .B0(n1999), .B1(
d_ff_Xn[40]), .Y(n1097) );
AO22XLTS U1655 ( .A0(n2001), .A1(result_add_subt[47]), .B0(n1999), .B1(
d_ff_Xn[47]), .Y(n1090) );
AO22XLTS U1656 ( .A0(n2003), .A1(result_add_subt[50]), .B0(n2002), .B1(
d_ff_Xn[50]), .Y(n1087) );
AO22XLTS U1657 ( .A0(n2003), .A1(result_add_subt[52]), .B0(n2002), .B1(
d_ff_Xn[52]), .Y(n1085) );
AO22XLTS U1658 ( .A0(n2003), .A1(result_add_subt[53]), .B0(n2002), .B1(
d_ff_Xn[53]), .Y(n1084) );
AO22XLTS U1659 ( .A0(n2003), .A1(result_add_subt[54]), .B0(n2002), .B1(
d_ff_Xn[54]), .Y(n1083) );
AO22XLTS U1660 ( .A0(n2003), .A1(result_add_subt[56]), .B0(n2002), .B1(
d_ff_Xn[56]), .Y(n1081) );
AO22XLTS U1661 ( .A0(n2006), .A1(result_add_subt[60]), .B0(n2005), .B1(
d_ff_Xn[60]), .Y(n1077) );
AO22XLTS U1662 ( .A0(d_ff2_X[62]), .A1(n2187), .B0(d_ff_Xn[62]), .B1(n2186),
.Y(n582) );
AO22XLTS U1663 ( .A0(d_ff_Xn[52]), .A1(n2175), .B0(d_ff2_X[52]), .B1(n2174),
.Y(n592) );
CLKINVX3TS U1664 ( .A(n1880), .Y(n1813) );
BUFX3TS U1665 ( .A(n1727), .Y(n1770) );
OR2X2TS U1666 ( .A(n1991), .B(n1990), .Y(n2004) );
AOI32X1TS U1667 ( .A0(n2231), .A1(n2101), .A2(n1482), .B0(n1989), .B1(n1476),
.Y(n1991) );
BUFX3TS U1668 ( .A(n2120), .Y(n2170) );
CLKAND2X2TS U1669 ( .A(n2197), .B(d_ff2_X[55]), .Y(n2196) );
INVX2TS U1670 ( .A(d_ff_Yn[62]), .Y(n2132) );
INVX2TS U1671 ( .A(d_ff_Yn[61]), .Y(n2130) );
INVX2TS U1672 ( .A(d_ff_Yn[60]), .Y(n2129) );
INVX2TS U1673 ( .A(d_ff_Yn[59]), .Y(n2128) );
INVX2TS U1674 ( .A(d_ff_Yn[58]), .Y(n2126) );
INVX2TS U1675 ( .A(d_ff_Yn[56]), .Y(n2124) );
INVX2TS U1676 ( .A(d_ff_Yn[55]), .Y(n2123) );
INVX2TS U1677 ( .A(d_ff_Yn[53]), .Y(n2122) );
INVX2TS U1678 ( .A(d_ff_Yn[52]), .Y(n2121) );
INVX2TS U1679 ( .A(n1957), .Y(n1966) );
OAI21XLTS U1680 ( .A0(n1480), .A1(n1860), .B0(n1856), .Y(add_subt_dataA[53])
);
OAI21XLTS U1681 ( .A0(n2232), .A1(n1860), .B0(n1523), .Y(add_subt_dataA[55])
);
OAI21XLTS U1682 ( .A0(n2138), .A1(n1860), .B0(n1859), .Y(add_subt_dataA[56])
);
OAI21XLTS U1683 ( .A0(n2233), .A1(n1877), .B0(n1875), .Y(add_subt_dataA[57])
);
OAI21XLTS U1684 ( .A0(n2127), .A1(n1877), .B0(n1857), .Y(add_subt_dataA[58])
);
OAI21XLTS U1685 ( .A0(n2235), .A1(n1880), .B0(n1879), .Y(add_subt_dataA[59])
);
OAI21XLTS U1686 ( .A0(n2146), .A1(n1877), .B0(n1858), .Y(add_subt_dataA[60])
);
OAI21XLTS U1687 ( .A0(n2236), .A1(n1877), .B0(n1876), .Y(add_subt_dataA[61])
);
AOI222X1TS U1688 ( .A0(d_ff2_Z[63]), .A1(n1873), .B0(d_ff2_Y[63]), .B1(n1497), .C0(d_ff2_X[63]), .C1(n1889), .Y(n1874) );
OAI21XLTS U1689 ( .A0(n1938), .A1(n2078), .B0(n1658), .Y(n1340) );
AOI32X1TS U1690 ( .A0(n1928), .A1(n1927), .A2(n1926), .B0(n2223), .B1(n1927),
.Y(n1344) );
NAND4XLTS U1691 ( .A(n1512), .B(n2225), .C(n2101), .D(n1925), .Y(n1926) );
NAND4BXLTS U1692 ( .AN(n1935), .B(n1938), .C(n1934), .D(n1933), .Y(n1343) );
OAI31X1TS U1693 ( .A0(n1932), .A1(n1931), .A2(n2229), .B0(n2223), .Y(n1933)
);
NAND3BXLTS U1694 ( .AN(n2085), .B(n2045), .C(n2072), .Y(n930) );
AOI2BB2XLTS U1695 ( .B0(n1485), .B1(n1844), .A0N(d_ff_Xn[60]), .A1N(n2185),
.Y(n584) );
AOI2BB2XLTS U1696 ( .B0(n1483), .B1(n2105), .A0N(d_ff_Xn[58]), .A1N(n2181),
.Y(n586) );
AO22XLTS U1697 ( .A0(d_ff_Xn[63]), .A1(n2219), .B0(d_ff2_X[63]), .B1(n2218),
.Y(n570) );
AO22XLTS U1698 ( .A0(d_ff_Xn[51]), .A1(n2172), .B0(d_ff2_X[51]), .B1(n2174),
.Y(n594) );
AO22XLTS U1699 ( .A0(d_ff_Xn[50]), .A1(n2172), .B0(d_ff2_X[50]), .B1(n2174),
.Y(n596) );
AO22XLTS U1700 ( .A0(n1996), .A1(result_add_subt[25]), .B0(n1995), .B1(
d_ff_Xn[25]), .Y(n1112) );
AO22XLTS U1701 ( .A0(n1994), .A1(result_add_subt[12]), .B0(n1993), .B1(
d_ff_Xn[12]), .Y(n1125) );
AO22XLTS U1702 ( .A0(n1992), .A1(result_add_subt[5]), .B0(n2000), .B1(
d_ff_Xn[5]), .Y(n1132) );
AO22XLTS U1703 ( .A0(n1952), .A1(d_ff1_shift_region_flag_out[1]), .B0(n1955),
.B1(shift_region_flag[1]), .Y(n1334) );
OAI21XLTS U1704 ( .A0(n2246), .A1(n1645), .B0(n1638), .Y(n1059) );
OAI21XLTS U1705 ( .A0(n2247), .A1(n1645), .B0(n1644), .Y(n1057) );
OAI21XLTS U1706 ( .A0(n2248), .A1(n1645), .B0(n1636), .Y(n1055) );
OAI21XLTS U1707 ( .A0(n2278), .A1(n1604), .B0(n1586), .Y(n995) );
AO22XLTS U1708 ( .A0(n1998), .A1(result_add_subt[39]), .B0(n1999), .B1(
d_ff_Xn[39]), .Y(n1098) );
AO22XLTS U1709 ( .A0(n1998), .A1(result_add_subt[38]), .B0(n1997), .B1(
d_ff_Xn[38]), .Y(n1099) );
OAI21XLTS U1710 ( .A0(n2276), .A1(n1604), .B0(n1583), .Y(n999) );
AO22XLTS U1711 ( .A0(n1998), .A1(result_add_subt[37]), .B0(n1997), .B1(
d_ff_Xn[37]), .Y(n1100) );
NAND2BXLTS U1712 ( .AN(d_ff3_LUT_out[48]), .B(n2152), .Y(n897) );
NOR2XLTS U1713 ( .A(n2049), .B(n1571), .Y(n1572) );
AO22XLTS U1714 ( .A0(n2003), .A1(result_add_subt[51]), .B0(n2002), .B1(
d_ff_Xn[51]), .Y(n1086) );
AO22XLTS U1715 ( .A0(n2006), .A1(result_add_subt[63]), .B0(n2005), .B1(
d_ff_Xn[63]), .Y(n1074) );
AO22XLTS U1716 ( .A0(d_ff_Xn[1]), .A1(n2219), .B0(d_ff2_X[1]), .B1(n2155),
.Y(n694) );
AO22XLTS U1717 ( .A0(d_ff_Xn[15]), .A1(n2168), .B0(d_ff2_X[15]), .B1(n2160),
.Y(n666) );
AO22XLTS U1718 ( .A0(d_ff_Xn[16]), .A1(n2172), .B0(d_ff2_X[16]), .B1(n2160),
.Y(n664) );
AO22XLTS U1719 ( .A0(d_ff_Xn[17]), .A1(n2172), .B0(d_ff2_X[17]), .B1(n2160),
.Y(n662) );
AO22XLTS U1720 ( .A0(d_ff_Xn[18]), .A1(n2172), .B0(d_ff2_X[18]), .B1(n2160),
.Y(n660) );
AO22XLTS U1721 ( .A0(d_ff_Xn[20]), .A1(n2172), .B0(d_ff2_X[20]), .B1(n2160),
.Y(n656) );
AO22XLTS U1722 ( .A0(d_ff_Xn[21]), .A1(n2164), .B0(d_ff2_X[21]), .B1(n2160),
.Y(n654) );
AO22XLTS U1723 ( .A0(d_ff_Xn[22]), .A1(n2164), .B0(d_ff2_X[22]), .B1(n2160),
.Y(n652) );
AO22XLTS U1724 ( .A0(d_ff_Xn[23]), .A1(n2164), .B0(d_ff2_X[23]), .B1(n2160),
.Y(n650) );
AO22XLTS U1725 ( .A0(d_ff_Xn[25]), .A1(n2164), .B0(d_ff2_X[25]), .B1(n2160),
.Y(n646) );
AO22XLTS U1726 ( .A0(d_ff_Xn[27]), .A1(n2164), .B0(d_ff2_X[27]), .B1(n2160),
.Y(n642) );
AO22XLTS U1727 ( .A0(d_ff_Xn[30]), .A1(n2164), .B0(d_ff2_X[30]), .B1(n2174),
.Y(n636) );
AO22XLTS U1728 ( .A0(d_ff_Xn[33]), .A1(n2168), .B0(d_ff2_X[33]), .B1(n2174),
.Y(n630) );
AO22XLTS U1729 ( .A0(d_ff_Xn[37]), .A1(n2164), .B0(d_ff2_X[37]), .B1(n2174),
.Y(n622) );
AO22XLTS U1730 ( .A0(d_ff_Xn[38]), .A1(n2168), .B0(d_ff2_X[38]), .B1(n2174),
.Y(n620) );
AO22XLTS U1731 ( .A0(d_ff_Xn[40]), .A1(n2168), .B0(d_ff2_X[40]), .B1(n2174),
.Y(n616) );
AO22XLTS U1732 ( .A0(d_ff_Xn[47]), .A1(n2172), .B0(d_ff2_X[47]), .B1(n2174),
.Y(n602) );
AO22XLTS U1733 ( .A0(n2003), .A1(result_add_subt[58]), .B0(n2002), .B1(
d_ff_Xn[58]), .Y(n1079) );
AO22XLTS U1734 ( .A0(d_ff_Yn[0]), .A1(n2118), .B0(d_ff2_Y[0]), .B1(n2187),
.Y(n824) );
AO22XLTS U1735 ( .A0(d_ff_Yn[1]), .A1(n2175), .B0(d_ff2_Y[1]), .B1(n2105),
.Y(n822) );
AO22XLTS U1736 ( .A0(d_ff_Yn[2]), .A1(n2175), .B0(d_ff2_Y[2]), .B1(n1844),
.Y(n820) );
AO22XLTS U1737 ( .A0(d_ff_Yn[3]), .A1(n2112), .B0(d_ff2_Y[3]), .B1(n2183),
.Y(n818) );
AO22XLTS U1738 ( .A0(d_ff_Yn[4]), .A1(n2112), .B0(d_ff2_Y[4]), .B1(n2105),
.Y(n816) );
AO22XLTS U1739 ( .A0(d_ff_Yn[5]), .A1(n2112), .B0(d_ff2_Y[5]), .B1(n1844),
.Y(n814) );
AO22XLTS U1740 ( .A0(d_ff_Yn[6]), .A1(n2118), .B0(d_ff2_Y[6]), .B1(n2105),
.Y(n812) );
AO22XLTS U1741 ( .A0(d_ff_Yn[7]), .A1(n2118), .B0(d_ff2_Y[7]), .B1(n1844),
.Y(n810) );
AO22XLTS U1742 ( .A0(d_ff_Yn[8]), .A1(n2118), .B0(d_ff2_Y[8]), .B1(n2183),
.Y(n808) );
AO22XLTS U1743 ( .A0(d_ff_Yn[9]), .A1(n2175), .B0(d_ff2_Y[9]), .B1(n2105),
.Y(n806) );
AO22XLTS U1744 ( .A0(d_ff_Yn[10]), .A1(n2175), .B0(d_ff2_Y[10]), .B1(n1844),
.Y(n804) );
AO22XLTS U1745 ( .A0(d_ff_Yn[11]), .A1(n2175), .B0(d_ff2_Y[11]), .B1(n1717),
.Y(n802) );
AO22XLTS U1746 ( .A0(d_ff_Yn[12]), .A1(n2175), .B0(d_ff2_Y[12]), .B1(n2108),
.Y(n800) );
AO22XLTS U1747 ( .A0(d_ff_Yn[13]), .A1(n2175), .B0(d_ff2_Y[13]), .B1(n1833),
.Y(n798) );
AO22XLTS U1748 ( .A0(d_ff_Yn[14]), .A1(n2175), .B0(d_ff2_Y[14]), .B1(n1717),
.Y(n796) );
AO22XLTS U1749 ( .A0(d_ff_Yn[15]), .A1(n2175), .B0(d_ff2_Y[15]), .B1(n2108),
.Y(n794) );
AO22XLTS U1750 ( .A0(d_ff_Yn[16]), .A1(n2114), .B0(d_ff2_Y[16]), .B1(n1833),
.Y(n792) );
AO22XLTS U1751 ( .A0(d_ff_Yn[17]), .A1(n2114), .B0(d_ff2_Y[17]), .B1(n1717),
.Y(n790) );
AO22XLTS U1752 ( .A0(d_ff_Yn[18]), .A1(n2114), .B0(d_ff2_Y[18]), .B1(n2108),
.Y(n788) );
AO22XLTS U1753 ( .A0(d_ff_Yn[19]), .A1(n2114), .B0(d_ff2_Y[19]), .B1(n1833),
.Y(n786) );
AO22XLTS U1754 ( .A0(d_ff_Yn[20]), .A1(n2114), .B0(d_ff2_Y[20]), .B1(n1717),
.Y(n784) );
AO22XLTS U1755 ( .A0(d_ff_Yn[36]), .A1(n2219), .B0(d_ff2_Y[36]), .B1(n2116),
.Y(n752) );
AO22XLTS U1756 ( .A0(d_ff_Yn[37]), .A1(n2219), .B0(d_ff2_Y[37]), .B1(n2116),
.Y(n750) );
AO22XLTS U1757 ( .A0(d_ff_Yn[38]), .A1(n2219), .B0(d_ff2_Y[38]), .B1(n2116),
.Y(n748) );
AO22XLTS U1758 ( .A0(d_ff_Yn[39]), .A1(n2219), .B0(d_ff2_Y[39]), .B1(n2116),
.Y(n746) );
AO22XLTS U1759 ( .A0(d_ff_Yn[40]), .A1(n2219), .B0(d_ff2_Y[40]), .B1(n2116),
.Y(n744) );
AO22XLTS U1760 ( .A0(d_ff_Yn[41]), .A1(n2118), .B0(d_ff2_Y[41]), .B1(n2218),
.Y(n742) );
AO22XLTS U1761 ( .A0(d_ff_Yn[42]), .A1(n2164), .B0(d_ff2_Y[42]), .B1(n2218),
.Y(n740) );
AO22XLTS U1762 ( .A0(d_ff_Yn[43]), .A1(n2164), .B0(d_ff2_Y[43]), .B1(n2174),
.Y(n738) );
AO22XLTS U1763 ( .A0(d_ff_Yn[44]), .A1(n2164), .B0(d_ff2_Y[44]), .B1(n2218),
.Y(n736) );
AO22XLTS U1764 ( .A0(d_ff_Yn[45]), .A1(n2118), .B0(d_ff2_Y[45]), .B1(n2218),
.Y(n734) );
AO22XLTS U1765 ( .A0(d_ff_Yn[51]), .A1(n2219), .B0(d_ff2_Y[51]), .B1(n2155),
.Y(n722) );
AO22XLTS U1766 ( .A0(d_ff_Yn[63]), .A1(n2219), .B0(d_ff2_Y[63]), .B1(n2155),
.Y(n698) );
AO22XLTS U1767 ( .A0(n1950), .A1(d_ff1_operation_out), .B0(n1955), .B1(
operation), .Y(n1336) );
NAND3XLTS U1768 ( .A(n1544), .B(sel_mux_3_reg), .C(n2366), .Y(n1543) );
NAND3XLTS U1769 ( .A(cordic_FSM_state_reg[3]), .B(n1932), .C(n2223), .Y(
n1544) );
AO22XLTS U1770 ( .A0(n1944), .A1(d_ff1_shift_region_flag_out[0]), .B0(n1955),
.B1(shift_region_flag[0]), .Y(n1335) );
AOI222X1TS U1771 ( .A0(n2183), .A1(d_ff2_Z[63]), .B0(n1736), .B1(d_ff1_Z[63]), .C0(d_ff_Zn[63]), .C1(n1840), .Y(n1822) );
NAND3XLTS U1772 ( .A(n1542), .B(sel_mux_1_reg), .C(n2366), .Y(n1541) );
NAND3XLTS U1773 ( .A(cordic_FSM_state_reg[0]), .B(n1932), .C(n2229), .Y(
n1542) );
AO22XLTS U1774 ( .A0(d_ff_Yn[54]), .A1(n2219), .B0(d_ff2_Y[54]), .B1(n2155),
.Y(n718) );
AOI2BB2XLTS U1775 ( .B0(n1481), .B1(n2183), .A0N(d_ff_Xn[56]), .A1N(n2185),
.Y(n588) );
OAI32X1TS U1776 ( .A0(n1899), .A1(n1476), .A2(n1482), .B0(n1902), .B1(n1545),
.Y(n1266) );
AO22XLTS U1777 ( .A0(n2022), .A1(n1537), .B0(n2021), .B1(data_output[63]),
.Y(n946) );
AO22XLTS U1778 ( .A0(n2022), .A1(sign_inv_out[62]), .B0(n2021), .B1(
data_output[62]), .Y(n948) );
AO22XLTS U1779 ( .A0(n2022), .A1(sign_inv_out[61]), .B0(n2021), .B1(
data_output[61]), .Y(n950) );
AO22XLTS U1780 ( .A0(n2022), .A1(sign_inv_out[60]), .B0(n2021), .B1(
data_output[60]), .Y(n952) );
AO22XLTS U1781 ( .A0(n2020), .A1(sign_inv_out[59]), .B0(n2021), .B1(
data_output[59]), .Y(n954) );
AO22XLTS U1782 ( .A0(n2020), .A1(sign_inv_out[58]), .B0(n2019), .B1(
data_output[58]), .Y(n956) );
AO22XLTS U1783 ( .A0(n2020), .A1(sign_inv_out[57]), .B0(n2019), .B1(
data_output[57]), .Y(n958) );
AO22XLTS U1784 ( .A0(n2020), .A1(sign_inv_out[56]), .B0(n2019), .B1(
data_output[56]), .Y(n960) );
AO22XLTS U1785 ( .A0(n2020), .A1(sign_inv_out[55]), .B0(n2019), .B1(
data_output[55]), .Y(n962) );
AO22XLTS U1786 ( .A0(n2020), .A1(sign_inv_out[54]), .B0(n2019), .B1(
data_output[54]), .Y(n964) );
AO22XLTS U1787 ( .A0(n2020), .A1(sign_inv_out[53]), .B0(n2019), .B1(
data_output[53]), .Y(n966) );
AO22XLTS U1788 ( .A0(n2020), .A1(sign_inv_out[52]), .B0(n2019), .B1(
data_output[52]), .Y(n968) );
AO22XLTS U1789 ( .A0(n2020), .A1(sign_inv_out[51]), .B0(n2019), .B1(
data_output[51]), .Y(n970) );
AO22XLTS U1790 ( .A0(n2020), .A1(sign_inv_out[50]), .B0(n2019), .B1(
data_output[50]), .Y(n972) );
AO22XLTS U1791 ( .A0(n2017), .A1(sign_inv_out[49]), .B0(n2019), .B1(
data_output[49]), .Y(n974) );
AO22XLTS U1792 ( .A0(n2017), .A1(sign_inv_out[48]), .B0(n2015), .B1(
data_output[48]), .Y(n976) );
AO22XLTS U1793 ( .A0(n2017), .A1(sign_inv_out[47]), .B0(n2015), .B1(
data_output[47]), .Y(n978) );
AO22XLTS U1794 ( .A0(n2017), .A1(sign_inv_out[46]), .B0(n2015), .B1(
data_output[46]), .Y(n980) );
AO22XLTS U1795 ( .A0(n2017), .A1(sign_inv_out[45]), .B0(n2015), .B1(
data_output[45]), .Y(n982) );
AO22XLTS U1796 ( .A0(n2017), .A1(sign_inv_out[44]), .B0(n2015), .B1(
data_output[44]), .Y(n984) );
AO22XLTS U1797 ( .A0(n2017), .A1(sign_inv_out[43]), .B0(n2015), .B1(
data_output[43]), .Y(n986) );
AO22XLTS U1798 ( .A0(n2017), .A1(sign_inv_out[42]), .B0(n2015), .B1(
data_output[42]), .Y(n988) );
AO22XLTS U1799 ( .A0(n2017), .A1(sign_inv_out[41]), .B0(n2015), .B1(
data_output[41]), .Y(n990) );
AO22XLTS U1800 ( .A0(n2017), .A1(sign_inv_out[40]), .B0(n2015), .B1(
data_output[40]), .Y(n992) );
AO22XLTS U1801 ( .A0(n2014), .A1(sign_inv_out[39]), .B0(n2015), .B1(
data_output[39]), .Y(n994) );
AO22XLTS U1802 ( .A0(n2014), .A1(sign_inv_out[38]), .B0(n2013), .B1(
data_output[38]), .Y(n996) );
AO22XLTS U1803 ( .A0(n2014), .A1(sign_inv_out[37]), .B0(n2013), .B1(
data_output[37]), .Y(n998) );
AO22XLTS U1804 ( .A0(n2014), .A1(sign_inv_out[36]), .B0(n2013), .B1(
data_output[36]), .Y(n1000) );
AO22XLTS U1805 ( .A0(n2014), .A1(sign_inv_out[35]), .B0(n2013), .B1(
data_output[35]), .Y(n1002) );
AO22XLTS U1806 ( .A0(n2014), .A1(sign_inv_out[34]), .B0(n2013), .B1(
data_output[34]), .Y(n1004) );
AO22XLTS U1807 ( .A0(n2014), .A1(sign_inv_out[33]), .B0(n2013), .B1(
data_output[33]), .Y(n1006) );
AO22XLTS U1808 ( .A0(n2014), .A1(sign_inv_out[32]), .B0(n2013), .B1(
data_output[32]), .Y(n1008) );
AO22XLTS U1809 ( .A0(n2014), .A1(sign_inv_out[31]), .B0(n2013), .B1(
data_output[31]), .Y(n1010) );
AO22XLTS U1810 ( .A0(n2014), .A1(sign_inv_out[30]), .B0(n2013), .B1(
data_output[30]), .Y(n1012) );
AO22XLTS U1811 ( .A0(n2011), .A1(sign_inv_out[29]), .B0(n2013), .B1(
data_output[29]), .Y(n1014) );
AO22XLTS U1812 ( .A0(n2011), .A1(sign_inv_out[28]), .B0(n2012), .B1(
data_output[28]), .Y(n1016) );
AO22XLTS U1813 ( .A0(n2011), .A1(sign_inv_out[27]), .B0(n2012), .B1(
data_output[27]), .Y(n1018) );
AO22XLTS U1814 ( .A0(n2011), .A1(sign_inv_out[26]), .B0(n2012), .B1(
data_output[26]), .Y(n1020) );
AO22XLTS U1815 ( .A0(n2011), .A1(sign_inv_out[25]), .B0(n2012), .B1(
data_output[25]), .Y(n1022) );
AO22XLTS U1816 ( .A0(n2011), .A1(sign_inv_out[24]), .B0(n2012), .B1(
data_output[24]), .Y(n1024) );
AO22XLTS U1817 ( .A0(n2011), .A1(sign_inv_out[23]), .B0(n2012), .B1(
data_output[23]), .Y(n1026) );
AO22XLTS U1818 ( .A0(n2011), .A1(sign_inv_out[22]), .B0(n2010), .B1(
data_output[22]), .Y(n1028) );
AO22XLTS U1819 ( .A0(n2011), .A1(sign_inv_out[21]), .B0(n2010), .B1(
data_output[21]), .Y(n1030) );
AO22XLTS U1820 ( .A0(n2011), .A1(sign_inv_out[20]), .B0(n2016), .B1(
data_output[20]), .Y(n1032) );
AO22XLTS U1821 ( .A0(n2009), .A1(sign_inv_out[19]), .B0(n2016), .B1(
data_output[19]), .Y(n1034) );
AO22XLTS U1822 ( .A0(n2009), .A1(sign_inv_out[18]), .B0(n2018), .B1(
data_output[18]), .Y(n1036) );
AO22XLTS U1823 ( .A0(n2009), .A1(sign_inv_out[17]), .B0(n2008), .B1(
data_output[17]), .Y(n1038) );
AO22XLTS U1824 ( .A0(n2009), .A1(sign_inv_out[16]), .B0(n2021), .B1(
data_output[16]), .Y(n1040) );
AO22XLTS U1825 ( .A0(n2009), .A1(sign_inv_out[15]), .B0(n2008), .B1(
data_output[15]), .Y(n1042) );
AO22XLTS U1826 ( .A0(n2009), .A1(sign_inv_out[14]), .B0(n2008), .B1(
data_output[14]), .Y(n1044) );
AO22XLTS U1827 ( .A0(n2009), .A1(sign_inv_out[13]), .B0(n2008), .B1(
data_output[13]), .Y(n1046) );
AO22XLTS U1828 ( .A0(n2009), .A1(sign_inv_out[12]), .B0(n2021), .B1(
data_output[12]), .Y(n1048) );
AO22XLTS U1829 ( .A0(n2009), .A1(sign_inv_out[11]), .B0(n2008), .B1(
data_output[11]), .Y(n1050) );
AO22XLTS U1830 ( .A0(n2009), .A1(sign_inv_out[10]), .B0(n2008), .B1(
data_output[10]), .Y(n1052) );
AO22XLTS U1831 ( .A0(n2007), .A1(sign_inv_out[9]), .B0(n2018), .B1(
data_output[9]), .Y(n1054) );
AO22XLTS U1832 ( .A0(n2007), .A1(sign_inv_out[8]), .B0(n2010), .B1(
data_output[8]), .Y(n1056) );
AO22XLTS U1833 ( .A0(n2007), .A1(sign_inv_out[7]), .B0(n2010), .B1(
data_output[7]), .Y(n1058) );
AO22XLTS U1834 ( .A0(n2007), .A1(sign_inv_out[6]), .B0(n2010), .B1(
data_output[6]), .Y(n1060) );
AO22XLTS U1835 ( .A0(n2007), .A1(sign_inv_out[5]), .B0(n2010), .B1(
data_output[5]), .Y(n1062) );
AO22XLTS U1836 ( .A0(n2007), .A1(sign_inv_out[4]), .B0(n2010), .B1(
data_output[4]), .Y(n1064) );
AO22XLTS U1837 ( .A0(n2007), .A1(sign_inv_out[3]), .B0(n2010), .B1(
data_output[3]), .Y(n1066) );
AO22XLTS U1838 ( .A0(n2007), .A1(sign_inv_out[2]), .B0(n2010), .B1(
data_output[2]), .Y(n1068) );
AO22XLTS U1839 ( .A0(n2007), .A1(sign_inv_out[1]), .B0(n2012), .B1(
data_output[1]), .Y(n1070) );
AO22XLTS U1840 ( .A0(n2007), .A1(sign_inv_out[0]), .B0(n2018), .B1(
data_output[0]), .Y(n1072) );
NAND3XLTS U1841 ( .A(n1533), .B(n2091), .C(n1575), .Y(
cordic_FSM_state_next_1_) );
NOR3XLTS U1842 ( .A(n2213), .B(n1908), .C(n1576), .Y(n1337) );
AOI31XLTS U1843 ( .A0(ack_add_subt), .A1(n2101), .A2(n1482), .B0(
cont_var_out[0]), .Y(n1576) );
AO22XLTS U1844 ( .A0(n2221), .A1(d_ff2_X[63]), .B0(n2220), .B1(
d_ff3_sh_x_out[63]), .Y(n569) );
AO22XLTS U1845 ( .A0(n2204), .A1(d_ff2_X[51]), .B0(n2173), .B1(
d_ff3_sh_x_out[51]), .Y(n593) );
AO22XLTS U1846 ( .A0(n2204), .A1(d_ff2_X[50]), .B0(n2173), .B1(
d_ff3_sh_x_out[50]), .Y(n595) );
AO22XLTS U1847 ( .A0(n2204), .A1(d_ff2_X[49]), .B0(n2173), .B1(
d_ff3_sh_x_out[49]), .Y(n597) );
AO22XLTS U1848 ( .A0(n2204), .A1(d_ff2_X[48]), .B0(n2173), .B1(
d_ff3_sh_x_out[48]), .Y(n599) );
AO22XLTS U1849 ( .A0(n2204), .A1(d_ff2_X[47]), .B0(n2173), .B1(
d_ff3_sh_x_out[47]), .Y(n601) );
AO22XLTS U1850 ( .A0(n2204), .A1(d_ff2_X[46]), .B0(n2173), .B1(
d_ff3_sh_x_out[46]), .Y(n603) );
AO22XLTS U1851 ( .A0(n2169), .A1(d_ff2_X[45]), .B0(n2173), .B1(
d_ff3_sh_x_out[45]), .Y(n605) );
AO22XLTS U1852 ( .A0(n2169), .A1(d_ff2_X[44]), .B0(n2173), .B1(
d_ff3_sh_x_out[44]), .Y(n607) );
AO22XLTS U1853 ( .A0(n2169), .A1(d_ff2_X[43]), .B0(n2173), .B1(
d_ff3_sh_x_out[43]), .Y(n609) );
AO22XLTS U1854 ( .A0(n2169), .A1(d_ff2_X[42]), .B0(n2173), .B1(
d_ff3_sh_x_out[42]), .Y(n611) );
AO22XLTS U1855 ( .A0(n2169), .A1(d_ff2_X[41]), .B0(n2165), .B1(
d_ff3_sh_x_out[41]), .Y(n613) );
AO22XLTS U1856 ( .A0(n2169), .A1(d_ff2_X[40]), .B0(n2165), .B1(
d_ff3_sh_x_out[40]), .Y(n615) );
AO22XLTS U1857 ( .A0(n2169), .A1(d_ff2_X[39]), .B0(n2165), .B1(
d_ff3_sh_x_out[39]), .Y(n617) );
AO22XLTS U1858 ( .A0(n2169), .A1(d_ff2_X[38]), .B0(n2165), .B1(
d_ff3_sh_x_out[38]), .Y(n619) );
AO22XLTS U1859 ( .A0(n2169), .A1(d_ff2_X[37]), .B0(n2165), .B1(
d_ff3_sh_x_out[37]), .Y(n621) );
AO22XLTS U1860 ( .A0(n2169), .A1(d_ff2_X[36]), .B0(n2165), .B1(
d_ff3_sh_x_out[36]), .Y(n623) );
AO22XLTS U1861 ( .A0(n2162), .A1(d_ff2_X[35]), .B0(n2165), .B1(
d_ff3_sh_x_out[35]), .Y(n625) );
AO22XLTS U1862 ( .A0(n2162), .A1(d_ff2_X[34]), .B0(n2165), .B1(
d_ff3_sh_x_out[34]), .Y(n627) );
AO22XLTS U1863 ( .A0(n2162), .A1(d_ff2_X[33]), .B0(n2165), .B1(
d_ff3_sh_x_out[33]), .Y(n629) );
AO22XLTS U1864 ( .A0(n2162), .A1(d_ff2_X[32]), .B0(n2165), .B1(
d_ff3_sh_x_out[32]), .Y(n631) );
AO22XLTS U1865 ( .A0(n2162), .A1(d_ff2_X[31]), .B0(n2161), .B1(
d_ff3_sh_x_out[31]), .Y(n633) );
AO22XLTS U1866 ( .A0(n2162), .A1(d_ff2_X[30]), .B0(n2161), .B1(
d_ff3_sh_x_out[30]), .Y(n635) );
AO22XLTS U1867 ( .A0(n2162), .A1(d_ff2_X[29]), .B0(n2161), .B1(
d_ff3_sh_x_out[29]), .Y(n637) );
AO22XLTS U1868 ( .A0(n2162), .A1(d_ff2_X[28]), .B0(n2161), .B1(
d_ff3_sh_x_out[28]), .Y(n639) );
AO22XLTS U1869 ( .A0(n2162), .A1(d_ff2_X[27]), .B0(n2161), .B1(
d_ff3_sh_x_out[27]), .Y(n641) );
AO22XLTS U1870 ( .A0(n2162), .A1(d_ff2_X[26]), .B0(n2161), .B1(
d_ff3_sh_x_out[26]), .Y(n643) );
AO22XLTS U1871 ( .A0(n2159), .A1(d_ff2_X[25]), .B0(n2161), .B1(
d_ff3_sh_x_out[25]), .Y(n645) );
AO22XLTS U1872 ( .A0(n2159), .A1(d_ff2_X[24]), .B0(n2161), .B1(
d_ff3_sh_x_out[24]), .Y(n647) );
AO22XLTS U1873 ( .A0(n2159), .A1(d_ff2_X[23]), .B0(n2161), .B1(
d_ff3_sh_x_out[23]), .Y(n649) );
AO22XLTS U1874 ( .A0(n2159), .A1(d_ff2_X[22]), .B0(n2215), .B1(
d_ff3_sh_x_out[22]), .Y(n651) );
AO22XLTS U1875 ( .A0(n2159), .A1(d_ff2_X[21]), .B0(n2215), .B1(
d_ff3_sh_x_out[21]), .Y(n653) );
AO22XLTS U1876 ( .A0(n2159), .A1(d_ff2_X[20]), .B0(n2215), .B1(
d_ff3_sh_x_out[20]), .Y(n655) );
AO22XLTS U1877 ( .A0(n2159), .A1(d_ff2_X[19]), .B0(n2158), .B1(
d_ff3_sh_x_out[19]), .Y(n657) );
AO22XLTS U1878 ( .A0(n2159), .A1(d_ff2_X[18]), .B0(n2215), .B1(
d_ff3_sh_x_out[18]), .Y(n659) );
AO22XLTS U1879 ( .A0(n2159), .A1(d_ff2_X[17]), .B0(n2215), .B1(
d_ff3_sh_x_out[17]), .Y(n661) );
AO22XLTS U1880 ( .A0(n2157), .A1(d_ff2_X[16]), .B0(n2215), .B1(
d_ff3_sh_x_out[16]), .Y(n663) );
AO22XLTS U1881 ( .A0(n2157), .A1(d_ff2_X[15]), .B0(n2171), .B1(
d_ff3_sh_x_out[15]), .Y(n665) );
AO22XLTS U1882 ( .A0(n2157), .A1(d_ff2_X[14]), .B0(n2158), .B1(
d_ff3_sh_x_out[14]), .Y(n667) );
AO22XLTS U1883 ( .A0(n2157), .A1(d_ff2_X[13]), .B0(n2158), .B1(
d_ff3_sh_x_out[13]), .Y(n669) );
AO22XLTS U1884 ( .A0(n2159), .A1(d_ff2_X[12]), .B0(n2156), .B1(
d_ff3_sh_x_out[12]), .Y(n671) );
AO22XLTS U1885 ( .A0(n2157), .A1(d_ff2_X[11]), .B0(n2154), .B1(
d_ff3_sh_x_out[11]), .Y(n673) );
AO22XLTS U1886 ( .A0(n2157), .A1(d_ff2_X[10]), .B0(n2156), .B1(
d_ff3_sh_x_out[10]), .Y(n675) );
AO22XLTS U1887 ( .A0(n2157), .A1(d_ff2_X[9]), .B0(n2154), .B1(
d_ff3_sh_x_out[9]), .Y(n677) );
AO22XLTS U1888 ( .A0(n2157), .A1(d_ff2_X[8]), .B0(n2154), .B1(
d_ff3_sh_x_out[8]), .Y(n679) );
AO22XLTS U1889 ( .A0(n2157), .A1(d_ff2_X[7]), .B0(n2153), .B1(
d_ff3_sh_x_out[7]), .Y(n681) );
AO22XLTS U1890 ( .A0(n2157), .A1(d_ff2_X[6]), .B0(n2153), .B1(
d_ff3_sh_x_out[6]), .Y(n683) );
AO22XLTS U1891 ( .A0(n2217), .A1(d_ff2_X[5]), .B0(n2152), .B1(
d_ff3_sh_x_out[5]), .Y(n685) );
AO22XLTS U1892 ( .A0(n2217), .A1(d_ff2_X[4]), .B0(n2152), .B1(
d_ff3_sh_x_out[4]), .Y(n687) );
AO22XLTS U1893 ( .A0(n2217), .A1(d_ff2_X[3]), .B0(n2154), .B1(
d_ff3_sh_x_out[3]), .Y(n689) );
AO22XLTS U1894 ( .A0(n2217), .A1(d_ff2_X[2]), .B0(n2152), .B1(
d_ff3_sh_x_out[2]), .Y(n691) );
AO22XLTS U1895 ( .A0(n2217), .A1(d_ff2_X[1]), .B0(n2152), .B1(
d_ff3_sh_x_out[1]), .Y(n693) );
AO22XLTS U1896 ( .A0(n2217), .A1(d_ff2_X[0]), .B0(n2152), .B1(
d_ff3_sh_x_out[0]), .Y(n695) );
AO22XLTS U1897 ( .A0(n2217), .A1(d_ff2_Y[63]), .B0(n2156), .B1(
d_ff3_sh_y_out[63]), .Y(n697) );
AO22XLTS U1898 ( .A0(n2221), .A1(d_ff2_Y[51]), .B0(n2171), .B1(
d_ff3_sh_y_out[51]), .Y(n721) );
AO22XLTS U1899 ( .A0(n2221), .A1(d_ff2_Y[50]), .B0(n1519), .B1(
d_ff3_sh_y_out[50]), .Y(n723) );
AO22XLTS U1900 ( .A0(n2119), .A1(d_ff2_Y[49]), .B0(n2161), .B1(
d_ff3_sh_y_out[49]), .Y(n725) );
AO22XLTS U1901 ( .A0(n2119), .A1(d_ff2_Y[48]), .B0(n2220), .B1(
d_ff3_sh_y_out[48]), .Y(n727) );
AO22XLTS U1902 ( .A0(n2119), .A1(d_ff2_Y[47]), .B0(n2220), .B1(
d_ff3_sh_y_out[47]), .Y(n729) );
AO22XLTS U1903 ( .A0(n2119), .A1(d_ff2_Y[46]), .B0(n2220), .B1(
d_ff3_sh_y_out[46]), .Y(n731) );
AO22XLTS U1904 ( .A0(n2119), .A1(d_ff2_Y[45]), .B0(n2220), .B1(
d_ff3_sh_y_out[45]), .Y(n733) );
AO22XLTS U1905 ( .A0(n2221), .A1(d_ff2_Y[44]), .B0(n2117), .B1(
d_ff3_sh_y_out[44]), .Y(n735) );
AO22XLTS U1906 ( .A0(n2119), .A1(d_ff2_Y[43]), .B0(n2117), .B1(
d_ff3_sh_y_out[43]), .Y(n737) );
AO22XLTS U1907 ( .A0(n2119), .A1(d_ff2_Y[41]), .B0(n2117), .B1(
d_ff3_sh_y_out[41]), .Y(n741) );
AO22XLTS U1908 ( .A0(n2115), .A1(d_ff2_Y[39]), .B0(n2117), .B1(
d_ff3_sh_y_out[39]), .Y(n745) );
AO22XLTS U1909 ( .A0(n2115), .A1(d_ff2_Y[33]), .B0(n2113), .B1(
d_ff3_sh_y_out[33]), .Y(n757) );
AO22XLTS U1910 ( .A0(n2110), .A1(d_ff2_Y[29]), .B0(n2113), .B1(
d_ff3_sh_y_out[29]), .Y(n765) );
AO22XLTS U1911 ( .A0(n2110), .A1(d_ff2_Y[27]), .B0(n2113), .B1(
d_ff3_sh_y_out[27]), .Y(n769) );
AO22XLTS U1912 ( .A0(n2110), .A1(d_ff2_Y[26]), .B0(n2113), .B1(
d_ff3_sh_y_out[26]), .Y(n771) );
AO22XLTS U1913 ( .A0(n2110), .A1(d_ff2_Y[25]), .B0(n2113), .B1(
d_ff3_sh_y_out[25]), .Y(n773) );
AO22XLTS U1914 ( .A0(n2107), .A1(d_ff2_Y[19]), .B0(n2109), .B1(
d_ff3_sh_y_out[19]), .Y(n785) );
AO22XLTS U1915 ( .A0(n2107), .A1(d_ff2_Y[15]), .B0(n2109), .B1(
d_ff3_sh_y_out[15]), .Y(n793) );
AO22XLTS U1916 ( .A0(n2107), .A1(d_ff2_Y[14]), .B0(n1519), .B1(
d_ff3_sh_y_out[14]), .Y(n795) );
AO22XLTS U1917 ( .A0(n2107), .A1(d_ff2_Y[13]), .B0(n1519), .B1(
d_ff3_sh_y_out[13]), .Y(n797) );
AO22XLTS U1918 ( .A0(n2107), .A1(d_ff2_Y[12]), .B0(n1519), .B1(
d_ff3_sh_y_out[12]), .Y(n799) );
AO22XLTS U1919 ( .A0(n2107), .A1(d_ff2_Y[11]), .B0(n1519), .B1(
d_ff3_sh_y_out[11]), .Y(n801) );
AO22XLTS U1920 ( .A0(n2107), .A1(d_ff2_Y[10]), .B0(n1519), .B1(
d_ff3_sh_y_out[10]), .Y(n803) );
AO22XLTS U1921 ( .A0(n2104), .A1(d_ff2_Y[9]), .B0(n2156), .B1(
d_ff3_sh_y_out[9]), .Y(n805) );
AO22XLTS U1922 ( .A0(n2107), .A1(d_ff2_Y[8]), .B0(n2044), .B1(
d_ff3_sh_y_out[8]), .Y(n807) );
AO22XLTS U1923 ( .A0(n2104), .A1(d_ff2_Y[7]), .B0(n2171), .B1(
d_ff3_sh_y_out[7]), .Y(n809) );
AO22XLTS U1924 ( .A0(n2107), .A1(d_ff2_Y[6]), .B0(n2167), .B1(
d_ff3_sh_y_out[6]), .Y(n811) );
AO22XLTS U1925 ( .A0(n2104), .A1(d_ff2_Y[5]), .B0(n2163), .B1(
d_ff3_sh_y_out[5]), .Y(n813) );
AO22XLTS U1926 ( .A0(n2104), .A1(d_ff2_Y[3]), .B0(n2103), .B1(
d_ff3_sh_y_out[3]), .Y(n817) );
AO22XLTS U1927 ( .A0(n2104), .A1(d_ff2_Y[1]), .B0(n2103), .B1(
d_ff3_sh_y_out[1]), .Y(n821) );
AO22XLTS U1928 ( .A0(n2104), .A1(d_ff2_Y[0]), .B0(n2103), .B1(
d_ff3_sh_y_out[0]), .Y(n823) );
AO22XLTS U1929 ( .A0(n1519), .A1(d_ff3_sign_out), .B0(n2206), .B1(
d_ff2_Z[63]), .Y(n825) );
AO22XLTS U1930 ( .A0(n2217), .A1(n2216), .B0(n2215), .B1(d_ff3_sh_x_out[62]),
.Y(n571) );
AOI2BB2XLTS U1931 ( .B0(n2213), .B1(n2212), .A0N(d_ff3_sh_x_out[61]), .A1N(
n2211), .Y(n572) );
AO22XLTS U1932 ( .A0(n2221), .A1(n2209), .B0(n2220), .B1(d_ff3_sh_x_out[60]),
.Y(n573) );
OAI21XLTS U1933 ( .A0(n2208), .A1(n1485), .B0(n2210), .Y(n2209) );
AOI2BB2XLTS U1934 ( .B0(n2213), .B1(n2207), .A0N(d_ff3_sh_x_out[59]), .A1N(
n2206), .Y(n574) );
AO22XLTS U1935 ( .A0(n2204), .A1(n2203), .B0(n2220), .B1(d_ff3_sh_x_out[58]),
.Y(n575) );
OAI21XLTS U1936 ( .A0(n2202), .A1(n1483), .B0(n2205), .Y(n2203) );
AOI2BB2XLTS U1937 ( .B0(n2076), .B1(n2201), .A0N(d_ff3_sh_x_out[57]), .A1N(
n2206), .Y(n576) );
AO22XLTS U1938 ( .A0(n2204), .A1(n2194), .B0(n2220), .B1(d_ff3_sh_x_out[54]),
.Y(n579) );
AOI2BB2XLTS U1939 ( .B0(n2076), .B1(n2189), .A0N(d_ff3_sh_x_out[52]), .A1N(
n2206), .Y(n581) );
AO22X1TS U1940 ( .A0(n2217), .A1(n1521), .B0(n2153), .B1(d_ff3_sh_y_out[62]),
.Y(n699) );
AOI2BB2XLTS U1941 ( .B0(n2076), .B1(n2151), .A0N(d_ff3_sh_y_out[61]), .A1N(
n2206), .Y(n700) );
AO22XLTS U1942 ( .A0(n2217), .A1(n2148), .B0(n2156), .B1(d_ff3_sh_y_out[60]),
.Y(n701) );
OAI21XLTS U1943 ( .A0(n2147), .A1(n2146), .B0(n2150), .Y(n2148) );
AOI2BB2XLTS U1944 ( .B0(n2089), .B1(n2145), .A0N(d_ff3_sh_y_out[59]), .A1N(
n2206), .Y(n702) );
AO22XLTS U1945 ( .A0(n2221), .A1(n1539), .B0(n2152), .B1(d_ff3_sh_y_out[58]),
.Y(n703) );
OAI21XLTS U1946 ( .A0(n2141), .A1(n2127), .B0(n2144), .Y(n1539) );
AOI2BB2XLTS U1947 ( .B0(n2213), .B1(n2143), .A0N(d_ff3_sh_y_out[57]), .A1N(
n2206), .Y(n704) );
OAI21XLTS U1948 ( .A0(n2139), .A1(n2138), .B0(n2142), .Y(n2140) );
OAI21XLTS U1949 ( .A0(n1682), .A1(n1552), .B0(n1551), .Y(n706) );
AO22XLTS U1950 ( .A0(n2221), .A1(n1535), .B0(n2153), .B1(d_ff3_sh_y_out[54]),
.Y(n707) );
AO22XLTS U1951 ( .A0(n2221), .A1(n2137), .B0(n1519), .B1(d_ff3_sh_y_out[53]),
.Y(n708) );
AOI2BB2XLTS U1952 ( .B0(n2089), .B1(n2134), .A0N(d_ff3_sh_y_out[52]), .A1N(
n2206), .Y(n709) );
AOI31XLTS U1953 ( .A0(n2052), .A1(n2101), .A2(n2037), .B0(n1700), .Y(n891)
);
OAI21XLTS U1954 ( .A0(n2087), .A1(n2036), .B0(n1554), .Y(n892) );
OAI32X1TS U1955 ( .A0(n2044), .A1(n2064), .A2(n1699), .B0(n2089), .B1(n2293),
.Y(n893) );
AO22XLTS U1956 ( .A0(n2206), .A1(cont_iter_out[0]), .B0(n2103), .B1(
d_ff3_LUT_out[52]), .Y(n894) );
AO21XLTS U1957 ( .A0(d_ff3_LUT_out[49]), .A1(n2103), .B0(n2096), .Y(n896) );
AO21XLTS U1958 ( .A0(d_ff3_LUT_out[47]), .A1(n2095), .B0(n2094), .Y(n898) );
AO21XLTS U1959 ( .A0(d_ff3_LUT_out[46]), .A1(n2095), .B0(n2096), .Y(n899) );
AO21XLTS U1960 ( .A0(d_ff3_LUT_out[44]), .A1(n2095), .B0(n2096), .Y(n901) );
AO21XLTS U1961 ( .A0(d_ff3_LUT_out[43]), .A1(n2095), .B0(n2092), .Y(n902) );
AO21XLTS U1962 ( .A0(d_ff3_LUT_out[42]), .A1(n2095), .B0(n2094), .Y(n903) );
NAND2BXLTS U1963 ( .AN(n2085), .B(n2084), .Y(n906) );
AO21XLTS U1964 ( .A0(d_ff3_LUT_out[34]), .A1(n2095), .B0(n2092), .Y(n911) );
AOI2BB2XLTS U1965 ( .B0(n2075), .B1(n2088), .A0N(n2097), .A1N(
d_ff3_LUT_out[31]), .Y(n914) );
AO21XLTS U1966 ( .A0(d_ff3_LUT_out[30]), .A1(n2095), .B0(n2074), .Y(n915) );
NAND4XLTS U1967 ( .A(n2073), .B(n2072), .C(n2071), .D(n2070), .Y(n916) );
NAND4XLTS U1968 ( .A(n2069), .B(n2072), .C(n2068), .D(n2067), .Y(n918) );
NAND3XLTS U1969 ( .A(n2068), .B(n2062), .C(n2061), .Y(n920) );
AOI2BB2XLTS U1970 ( .B0(n2058), .B1(n2057), .A0N(n2097), .A1N(
d_ff3_LUT_out[23]), .Y(n922) );
AOI2BB2XLTS U1971 ( .B0(n2052), .B1(n2057), .A0N(n2097), .A1N(
d_ff3_LUT_out[21]), .Y(n924) );
AOI2BB2XLTS U1972 ( .B0(n2089), .B1(n2090), .A0N(d_ff3_LUT_out[20]), .A1N(
n2211), .Y(n925) );
AO21XLTS U1973 ( .A0(d_ff3_LUT_out[16]), .A1(n2095), .B0(n2046), .Y(n929) );
OAI211XLTS U1974 ( .A0(n1682), .A1(n1496), .B0(n2071), .C0(n1562), .Y(n931)
);
AOI2BB2XLTS U1975 ( .B0(n2041), .B1(n2096), .A0N(n2097), .A1N(
d_ff3_LUT_out[13]), .Y(n932) );
AOI211XLTS U1976 ( .A0(d_ff3_LUT_out[11]), .A1(n2087), .B0(n2085), .C0(n2035), .Y(n1681) );
AOI2BB2XLTS U1977 ( .B0(n2075), .B1(n2037), .A0N(n2097), .A1N(
d_ff3_LUT_out[10]), .Y(n935) );
NAND4BXLTS U1978 ( .AN(n2035), .B(n2047), .C(n2034), .D(n2033), .Y(n936) );
NAND3XLTS U1979 ( .A(n2089), .B(n2064), .C(n2195), .Y(n2034) );
NAND3XLTS U1980 ( .A(n2073), .B(n2072), .C(n2030), .Y(n939) );
AO21XLTS U1981 ( .A0(d_ff3_LUT_out[4]), .A1(n2095), .B0(n2074), .Y(n941) );
AO21XLTS U1982 ( .A0(d_ff3_LUT_out[2]), .A1(n2095), .B0(n2026), .Y(n943) );
AOI31XLTS U1983 ( .A0(n2195), .A1(n1490), .A2(n2025), .B0(n2091), .Y(n2026)
);
OAI211XLTS U1984 ( .A0(n2073), .A1(n2078), .B0(n2047), .C0(n1570), .Y(n944)
);
NAND3XLTS U1985 ( .A(n2024), .B(n2068), .C(n2023), .Y(n945) );
OAI21XLTS U1986 ( .A0(n2132), .A1(n1475), .B0(n1561), .Y(n949) );
OAI21XLTS U1987 ( .A0(n2130), .A1(n1560), .B0(n1557), .Y(n951) );
OAI21XLTS U1988 ( .A0(n2129), .A1(n1475), .B0(n1559), .Y(n953) );
OAI21XLTS U1989 ( .A0(n2128), .A1(n1657), .B0(n1653), .Y(n955) );
OAI21XLTS U1990 ( .A0(n2125), .A1(n1657), .B0(n1649), .Y(n959) );
OAI21XLTS U1991 ( .A0(n2124), .A1(n1657), .B0(n1651), .Y(n961) );
OAI21XLTS U1992 ( .A0(n2123), .A1(n1657), .B0(n1648), .Y(n963) );
OAI21XLTS U1993 ( .A0(n2291), .A1(n1657), .B0(n1646), .Y(n965) );
OAI21XLTS U1994 ( .A0(n2122), .A1(n1657), .B0(n1656), .Y(n967) );
OAI21XLTS U1995 ( .A0(n2121), .A1(n1657), .B0(n1647), .Y(n969) );
OAI21XLTS U1996 ( .A0(n2289), .A1(n1657), .B0(n1633), .Y(n973) );
OAI21XLTS U1997 ( .A0(n2288), .A1(n1599), .B0(n1580), .Y(n975) );
OAI21XLTS U1998 ( .A0(n2287), .A1(n1599), .B0(n1590), .Y(n977) );
OAI21XLTS U1999 ( .A0(n2286), .A1(n1599), .B0(n1578), .Y(n979) );
OAI21XLTS U2000 ( .A0(n2285), .A1(n1599), .B0(n1589), .Y(n981) );
OAI21XLTS U2001 ( .A0(n2284), .A1(n1599), .B0(n1584), .Y(n983) );
OAI21XLTS U2002 ( .A0(n2283), .A1(n1599), .B0(n1581), .Y(n985) );
OAI21XLTS U2003 ( .A0(n2282), .A1(n1599), .B0(n1592), .Y(n987) );
OAI21XLTS U2004 ( .A0(n2281), .A1(n1599), .B0(n1595), .Y(n989) );
OAI21XLTS U2005 ( .A0(n2280), .A1(n1599), .B0(n1579), .Y(n991) );
OAI21XLTS U2006 ( .A0(n2279), .A1(n1599), .B0(n1598), .Y(n993) );
OAI21XLTS U2007 ( .A0(n2275), .A1(n1604), .B0(n1593), .Y(n1001) );
OAI21XLTS U2008 ( .A0(n2274), .A1(n1604), .B0(n1582), .Y(n1003) );
OAI21XLTS U2009 ( .A0(n2273), .A1(n1604), .B0(n1603), .Y(n1005) );
OAI21XLTS U2010 ( .A0(n2272), .A1(n1604), .B0(n1600), .Y(n1007) );
OAI21XLTS U2011 ( .A0(n2271), .A1(n1604), .B0(n1587), .Y(n1009) );
OAI21XLTS U2012 ( .A0(n2270), .A1(n1604), .B0(n1588), .Y(n1011) );
OAI21XLTS U2013 ( .A0(n2269), .A1(n1604), .B0(n1591), .Y(n1013) );
OAI21XLTS U2014 ( .A0(n2268), .A1(n1624), .B0(n1594), .Y(n1015) );
OAI21XLTS U2015 ( .A0(n2267), .A1(n1624), .B0(n1596), .Y(n1017) );
OAI21XLTS U2016 ( .A0(n2266), .A1(n1624), .B0(n1608), .Y(n1019) );
OAI21XLTS U2017 ( .A0(n2265), .A1(n1624), .B0(n1613), .Y(n1021) );
OAI21XLTS U2018 ( .A0(n2263), .A1(n1624), .B0(n1620), .Y(n1025) );
OAI21XLTS U2019 ( .A0(n2262), .A1(n1624), .B0(n1609), .Y(n1027) );
OAI21XLTS U2020 ( .A0(n2261), .A1(n1624), .B0(n1623), .Y(n1029) );
OAI21XLTS U2021 ( .A0(n2260), .A1(n1624), .B0(n1606), .Y(n1031) );
OAI21XLTS U2022 ( .A0(n2259), .A1(n1624), .B0(n1610), .Y(n1033) );
OAI21XLTS U2023 ( .A0(n2258), .A1(n1629), .B0(n1607), .Y(n1035) );
OAI21XLTS U2024 ( .A0(n2257), .A1(n1629), .B0(n1628), .Y(n1037) );
OAI21XLTS U2025 ( .A0(n2256), .A1(n1629), .B0(n1612), .Y(n1039) );
OAI21XLTS U2026 ( .A0(n2255), .A1(n1629), .B0(n1625), .Y(n1041) );
OAI21XLTS U2027 ( .A0(n2254), .A1(n1629), .B0(n1614), .Y(n1043) );
OAI21XLTS U2028 ( .A0(n2253), .A1(n1629), .B0(n1615), .Y(n1045) );
OAI21XLTS U2029 ( .A0(n2252), .A1(n1629), .B0(n1617), .Y(n1047) );
OAI21XLTS U2030 ( .A0(n2250), .A1(n1629), .B0(n1611), .Y(n1051) );
OAI21XLTS U2031 ( .A0(n2249), .A1(n1629), .B0(n1621), .Y(n1053) );
OAI21XLTS U2032 ( .A0(n2245), .A1(n1645), .B0(n1639), .Y(n1061) );
OAI21XLTS U2033 ( .A0(n2243), .A1(n1645), .B0(n1634), .Y(n1065) );
OAI21XLTS U2034 ( .A0(n2242), .A1(n1645), .B0(n1641), .Y(n1067) );
OAI21XLTS U2035 ( .A0(n2241), .A1(n1645), .B0(n1632), .Y(n1069) );
OAI21XLTS U2036 ( .A0(n2240), .A1(n1645), .B0(n1630), .Y(n1071) );
OAI21XLTS U2037 ( .A0(n2239), .A1(n1645), .B0(n1637), .Y(n1073) );
AO22XLTS U2038 ( .A0(n1973), .A1(result_add_subt[63]), .B0(n1972), .B1(
d_ff_Zn[63]), .Y(n1202) );
AO22XLTS U2039 ( .A0(n1973), .A1(result_add_subt[62]), .B0(n1972), .B1(
d_ff_Zn[62]), .Y(n1203) );
AO22XLTS U2040 ( .A0(n1973), .A1(result_add_subt[61]), .B0(n1972), .B1(
d_ff_Zn[61]), .Y(n1204) );
AO22XLTS U2041 ( .A0(n1973), .A1(result_add_subt[60]), .B0(n1972), .B1(
d_ff_Zn[60]), .Y(n1205) );
AO22XLTS U2042 ( .A0(n1970), .A1(result_add_subt[59]), .B0(n1972), .B1(
d_ff_Zn[59]), .Y(n1206) );
AO22XLTS U2043 ( .A0(n1970), .A1(result_add_subt[58]), .B0(n1969), .B1(
d_ff_Zn[58]), .Y(n1207) );
AO22XLTS U2044 ( .A0(n1970), .A1(result_add_subt[57]), .B0(n1969), .B1(
d_ff_Zn[57]), .Y(n1208) );
AO22XLTS U2045 ( .A0(n1970), .A1(result_add_subt[56]), .B0(n1969), .B1(
d_ff_Zn[56]), .Y(n1209) );
AO22XLTS U2046 ( .A0(n1970), .A1(result_add_subt[55]), .B0(n1969), .B1(
d_ff_Zn[55]), .Y(n1210) );
AO22XLTS U2047 ( .A0(n1970), .A1(result_add_subt[54]), .B0(n1969), .B1(
d_ff_Zn[54]), .Y(n1211) );
AO22XLTS U2048 ( .A0(n1970), .A1(result_add_subt[53]), .B0(n1969), .B1(
d_ff_Zn[53]), .Y(n1212) );
AO22XLTS U2049 ( .A0(n1970), .A1(result_add_subt[52]), .B0(n1969), .B1(
d_ff_Zn[52]), .Y(n1213) );
AO22XLTS U2050 ( .A0(n1970), .A1(result_add_subt[51]), .B0(n1969), .B1(
d_ff_Zn[51]), .Y(n1214) );
AO22XLTS U2051 ( .A0(n1970), .A1(result_add_subt[50]), .B0(n1969), .B1(
d_ff_Zn[50]), .Y(n1215) );
AO22XLTS U2052 ( .A0(n1968), .A1(result_add_subt[49]), .B0(n1969), .B1(
d_ff_Zn[49]), .Y(n1216) );
AO22XLTS U2053 ( .A0(n1968), .A1(result_add_subt[48]), .B0(n1972), .B1(
d_ff_Zn[48]), .Y(n1217) );
AO22XLTS U2054 ( .A0(n1968), .A1(result_add_subt[47]), .B0(n1967), .B1(
d_ff_Zn[47]), .Y(n1218) );
AO22XLTS U2055 ( .A0(n1968), .A1(result_add_subt[46]), .B0(n1967), .B1(
d_ff_Zn[46]), .Y(n1219) );
AO22XLTS U2056 ( .A0(n1968), .A1(result_add_subt[45]), .B0(n1967), .B1(
d_ff_Zn[45]), .Y(n1220) );
AO22XLTS U2057 ( .A0(n1968), .A1(result_add_subt[44]), .B0(n1967), .B1(
d_ff_Zn[44]), .Y(n1221) );
AO22XLTS U2058 ( .A0(n1968), .A1(result_add_subt[43]), .B0(n1966), .B1(
d_ff_Zn[43]), .Y(n1222) );
AO22XLTS U2059 ( .A0(n1968), .A1(result_add_subt[42]), .B0(n1966), .B1(
d_ff_Zn[42]), .Y(n1223) );
AO22XLTS U2060 ( .A0(n1968), .A1(result_add_subt[41]), .B0(n1966), .B1(
d_ff_Zn[41]), .Y(n1224) );
AO22XLTS U2061 ( .A0(n1968), .A1(result_add_subt[40]), .B0(n1966), .B1(
d_ff_Zn[40]), .Y(n1225) );
AO22XLTS U2062 ( .A0(n1965), .A1(result_add_subt[39]), .B0(n1966), .B1(
d_ff_Zn[39]), .Y(n1226) );
AO22XLTS U2063 ( .A0(n1965), .A1(result_add_subt[38]), .B0(n1964), .B1(
d_ff_Zn[38]), .Y(n1227) );
AO22XLTS U2064 ( .A0(n1965), .A1(result_add_subt[37]), .B0(n1964), .B1(
d_ff_Zn[37]), .Y(n1228) );
AO22XLTS U2065 ( .A0(n1965), .A1(result_add_subt[36]), .B0(n1964), .B1(
d_ff_Zn[36]), .Y(n1229) );
AO22XLTS U2066 ( .A0(n1965), .A1(result_add_subt[35]), .B0(n1964), .B1(
d_ff_Zn[35]), .Y(n1230) );
AO22XLTS U2067 ( .A0(n1965), .A1(result_add_subt[34]), .B0(n1964), .B1(
d_ff_Zn[34]), .Y(n1231) );
AO22XLTS U2068 ( .A0(n1965), .A1(result_add_subt[33]), .B0(n1964), .B1(
d_ff_Zn[33]), .Y(n1232) );
AO22XLTS U2069 ( .A0(n1965), .A1(result_add_subt[32]), .B0(n1964), .B1(
d_ff_Zn[32]), .Y(n1233) );
AO22XLTS U2070 ( .A0(n1965), .A1(result_add_subt[31]), .B0(n1964), .B1(
d_ff_Zn[31]), .Y(n1234) );
AO22XLTS U2071 ( .A0(n1965), .A1(result_add_subt[30]), .B0(n1964), .B1(
d_ff_Zn[30]), .Y(n1235) );
AO22XLTS U2072 ( .A0(n1963), .A1(result_add_subt[29]), .B0(n1964), .B1(
d_ff_Zn[29]), .Y(n1236) );
AO22XLTS U2073 ( .A0(n1963), .A1(result_add_subt[28]), .B0(n1962), .B1(
d_ff_Zn[28]), .Y(n1237) );
AO22XLTS U2074 ( .A0(n1963), .A1(result_add_subt[27]), .B0(n1962), .B1(
d_ff_Zn[27]), .Y(n1238) );
AO22XLTS U2075 ( .A0(n1963), .A1(result_add_subt[26]), .B0(n1962), .B1(
d_ff_Zn[26]), .Y(n1239) );
AO22XLTS U2076 ( .A0(n1963), .A1(result_add_subt[25]), .B0(n1962), .B1(
d_ff_Zn[25]), .Y(n1240) );
AO22XLTS U2077 ( .A0(n1963), .A1(result_add_subt[24]), .B0(n1962), .B1(
d_ff_Zn[24]), .Y(n1241) );
AO22XLTS U2078 ( .A0(n1963), .A1(result_add_subt[23]), .B0(n1962), .B1(
d_ff_Zn[23]), .Y(n1242) );
AO22XLTS U2079 ( .A0(n1963), .A1(result_add_subt[22]), .B0(n1962), .B1(
d_ff_Zn[22]), .Y(n1243) );
AO22XLTS U2080 ( .A0(n1963), .A1(result_add_subt[21]), .B0(n1962), .B1(
d_ff_Zn[21]), .Y(n1244) );
AO22XLTS U2081 ( .A0(n1963), .A1(result_add_subt[20]), .B0(n1962), .B1(
d_ff_Zn[20]), .Y(n1245) );
AO22XLTS U2082 ( .A0(n1961), .A1(result_add_subt[19]), .B0(n1962), .B1(
d_ff_Zn[19]), .Y(n1246) );
AO22XLTS U2083 ( .A0(n1961), .A1(result_add_subt[18]), .B0(n1960), .B1(
d_ff_Zn[18]), .Y(n1247) );
AO22XLTS U2084 ( .A0(n1961), .A1(result_add_subt[17]), .B0(n1960), .B1(
d_ff_Zn[17]), .Y(n1248) );
AO22XLTS U2085 ( .A0(n1961), .A1(result_add_subt[16]), .B0(n1960), .B1(
d_ff_Zn[16]), .Y(n1249) );
AO22XLTS U2086 ( .A0(n1961), .A1(result_add_subt[15]), .B0(n1960), .B1(
d_ff_Zn[15]), .Y(n1250) );
AO22XLTS U2087 ( .A0(n1961), .A1(result_add_subt[14]), .B0(n1960), .B1(
d_ff_Zn[14]), .Y(n1251) );
AO22XLTS U2088 ( .A0(n1961), .A1(result_add_subt[13]), .B0(n1960), .B1(
d_ff_Zn[13]), .Y(n1252) );
AO22XLTS U2089 ( .A0(n1961), .A1(result_add_subt[12]), .B0(n1960), .B1(
d_ff_Zn[12]), .Y(n1253) );
AO22XLTS U2090 ( .A0(n1961), .A1(result_add_subt[11]), .B0(n1960), .B1(
d_ff_Zn[11]), .Y(n1254) );
AO22XLTS U2091 ( .A0(n1961), .A1(result_add_subt[10]), .B0(n1960), .B1(
d_ff_Zn[10]), .Y(n1255) );
AO22XLTS U2092 ( .A0(n1959), .A1(result_add_subt[9]), .B0(n1960), .B1(
d_ff_Zn[9]), .Y(n1256) );
AO22XLTS U2093 ( .A0(n1959), .A1(result_add_subt[8]), .B0(n1958), .B1(
d_ff_Zn[8]), .Y(n1257) );
AO22XLTS U2094 ( .A0(n1959), .A1(result_add_subt[7]), .B0(n1958), .B1(
d_ff_Zn[7]), .Y(n1258) );
AO22XLTS U2095 ( .A0(n1959), .A1(result_add_subt[6]), .B0(n1958), .B1(
d_ff_Zn[6]), .Y(n1259) );
AO22XLTS U2096 ( .A0(n1959), .A1(result_add_subt[5]), .B0(n1958), .B1(
d_ff_Zn[5]), .Y(n1260) );
AO22XLTS U2097 ( .A0(n1959), .A1(result_add_subt[4]), .B0(n1958), .B1(
d_ff_Zn[4]), .Y(n1261) );
AO22XLTS U2098 ( .A0(n1959), .A1(result_add_subt[3]), .B0(n1958), .B1(
d_ff_Zn[3]), .Y(n1262) );
AO22XLTS U2099 ( .A0(n1959), .A1(result_add_subt[2]), .B0(n1958), .B1(
d_ff_Zn[2]), .Y(n1263) );
AO22XLTS U2100 ( .A0(n1959), .A1(result_add_subt[1]), .B0(n1971), .B1(
d_ff_Zn[1]), .Y(n1264) );
AO22XLTS U2101 ( .A0(n1959), .A1(result_add_subt[0]), .B0(n1971), .B1(
d_ff_Zn[0]), .Y(n1265) );
AO22XLTS U2102 ( .A0(n1955), .A1(data_in[63]), .B0(n1954), .B1(d_ff1_Z[63]),
.Y(n1270) );
AO22XLTS U2103 ( .A0(n1953), .A1(data_in[62]), .B0(n1952), .B1(d_ff1_Z[62]),
.Y(n1271) );
AO22XLTS U2104 ( .A0(n1953), .A1(data_in[61]), .B0(n1951), .B1(d_ff1_Z[61]),
.Y(n1272) );
AO22XLTS U2105 ( .A0(n1953), .A1(data_in[60]), .B0(n1951), .B1(d_ff1_Z[60]),
.Y(n1273) );
AO22XLTS U2106 ( .A0(n1953), .A1(data_in[59]), .B0(n1950), .B1(d_ff1_Z[59]),
.Y(n1274) );
AO22XLTS U2107 ( .A0(n1949), .A1(data_in[58]), .B0(n1950), .B1(d_ff1_Z[58]),
.Y(n1275) );
AO22XLTS U2108 ( .A0(n1949), .A1(data_in[57]), .B0(n1940), .B1(d_ff1_Z[57]),
.Y(n1276) );
AO22XLTS U2109 ( .A0(n1949), .A1(data_in[56]), .B0(n1940), .B1(d_ff1_Z[56]),
.Y(n1277) );
AO22XLTS U2110 ( .A0(n1949), .A1(data_in[55]), .B0(n1950), .B1(d_ff1_Z[55]),
.Y(n1278) );
AO22XLTS U2111 ( .A0(n1949), .A1(data_in[54]), .B0(n1952), .B1(d_ff1_Z[54]),
.Y(n1279) );
AO22XLTS U2112 ( .A0(n1948), .A1(data_in[53]), .B0(n1952), .B1(d_ff1_Z[53]),
.Y(n1280) );
AO22XLTS U2113 ( .A0(n1948), .A1(data_in[52]), .B0(n1952), .B1(d_ff1_Z[52]),
.Y(n1281) );
AO22XLTS U2114 ( .A0(n1948), .A1(data_in[51]), .B0(n1947), .B1(d_ff1_Z[51]),
.Y(n1282) );
AO22XLTS U2115 ( .A0(n1948), .A1(data_in[50]), .B0(n1947), .B1(d_ff1_Z[50]),
.Y(n1283) );
AO22XLTS U2116 ( .A0(n1946), .A1(data_in[49]), .B0(n1947), .B1(d_ff1_Z[49]),
.Y(n1284) );
AO22XLTS U2117 ( .A0(n1946), .A1(data_in[48]), .B0(n1947), .B1(d_ff1_Z[48]),
.Y(n1285) );
AO22XLTS U2118 ( .A0(n1946), .A1(data_in[47]), .B0(n1947), .B1(d_ff1_Z[47]),
.Y(n1286) );
AO22XLTS U2119 ( .A0(n1946), .A1(data_in[46]), .B0(n1947), .B1(d_ff1_Z[46]),
.Y(n1287) );
AO22XLTS U2120 ( .A0(n1946), .A1(data_in[45]), .B0(n1947), .B1(d_ff1_Z[45]),
.Y(n1288) );
AO22XLTS U2121 ( .A0(n1946), .A1(data_in[44]), .B0(n1947), .B1(d_ff1_Z[44]),
.Y(n1289) );
AO22XLTS U2122 ( .A0(n1949), .A1(data_in[43]), .B0(n1947), .B1(d_ff1_Z[43]),
.Y(n1290) );
AO22XLTS U2123 ( .A0(n1949), .A1(data_in[42]), .B0(n1947), .B1(d_ff1_Z[42]),
.Y(n1291) );
AO22XLTS U2124 ( .A0(n1949), .A1(data_in[41]), .B0(n1945), .B1(d_ff1_Z[41]),
.Y(n1292) );
AO22XLTS U2125 ( .A0(n1949), .A1(data_in[40]), .B0(n1945), .B1(d_ff1_Z[40]),
.Y(n1293) );
AO22XLTS U2126 ( .A0(n1949), .A1(data_in[39]), .B0(n1945), .B1(d_ff1_Z[39]),
.Y(n1294) );
AO22XLTS U2127 ( .A0(n1948), .A1(data_in[38]), .B0(n1945), .B1(d_ff1_Z[38]),
.Y(n1295) );
AO22XLTS U2128 ( .A0(n1948), .A1(data_in[37]), .B0(n1945), .B1(d_ff1_Z[37]),
.Y(n1296) );
AO22XLTS U2129 ( .A0(n1948), .A1(data_in[36]), .B0(n1945), .B1(d_ff1_Z[36]),
.Y(n1297) );
AO22XLTS U2130 ( .A0(n1948), .A1(data_in[35]), .B0(n1945), .B1(d_ff1_Z[35]),
.Y(n1298) );
AO22XLTS U2131 ( .A0(n1948), .A1(data_in[34]), .B0(n1945), .B1(d_ff1_Z[34]),
.Y(n1299) );
AO22XLTS U2132 ( .A0(n1943), .A1(data_in[33]), .B0(n1945), .B1(d_ff1_Z[33]),
.Y(n1300) );
AO22XLTS U2133 ( .A0(n1943), .A1(data_in[32]), .B0(n1945), .B1(d_ff1_Z[32]),
.Y(n1301) );
AO22XLTS U2134 ( .A0(n1943), .A1(data_in[31]), .B0(n1954), .B1(d_ff1_Z[31]),
.Y(n1302) );
AO22XLTS U2135 ( .A0(n1943), .A1(data_in[30]), .B0(n1954), .B1(d_ff1_Z[30]),
.Y(n1303) );
AO22XLTS U2136 ( .A0(n1955), .A1(data_in[29]), .B0(n1954), .B1(d_ff1_Z[29]),
.Y(n1304) );
AO22XLTS U2137 ( .A0(n1955), .A1(data_in[28]), .B0(n1954), .B1(d_ff1_Z[28]),
.Y(n1305) );
AO22XLTS U2138 ( .A0(n1955), .A1(data_in[27]), .B0(n1954), .B1(d_ff1_Z[27]),
.Y(n1306) );
AO22XLTS U2139 ( .A0(n1955), .A1(data_in[26]), .B0(n1954), .B1(d_ff1_Z[26]),
.Y(n1307) );
AO22XLTS U2140 ( .A0(n1942), .A1(data_in[25]), .B0(n1954), .B1(d_ff1_Z[25]),
.Y(n1308) );
AO22XLTS U2141 ( .A0(n1946), .A1(data_in[24]), .B0(n1954), .B1(d_ff1_Z[24]),
.Y(n1309) );
AO22XLTS U2142 ( .A0(n1946), .A1(data_in[23]), .B0(n1954), .B1(d_ff1_Z[23]),
.Y(n1310) );
AO22XLTS U2143 ( .A0(n1946), .A1(data_in[22]), .B0(n1941), .B1(d_ff1_Z[22]),
.Y(n1311) );
AO22XLTS U2144 ( .A0(n1946), .A1(data_in[21]), .B0(n1941), .B1(d_ff1_Z[21]),
.Y(n1312) );
AO22XLTS U2145 ( .A0(n1943), .A1(data_in[20]), .B0(n1941), .B1(d_ff1_Z[20]),
.Y(n1313) );
AO22XLTS U2146 ( .A0(n1943), .A1(data_in[19]), .B0(n1941), .B1(d_ff1_Z[19]),
.Y(n1314) );
AO22XLTS U2147 ( .A0(n1943), .A1(data_in[18]), .B0(n1941), .B1(d_ff1_Z[18]),
.Y(n1315) );
AO22XLTS U2148 ( .A0(n1943), .A1(data_in[17]), .B0(n1941), .B1(d_ff1_Z[17]),
.Y(n1316) );
AO22XLTS U2149 ( .A0(n1943), .A1(data_in[16]), .B0(n1941), .B1(d_ff1_Z[16]),
.Y(n1317) );
AO22XLTS U2150 ( .A0(n1943), .A1(data_in[15]), .B0(n1941), .B1(d_ff1_Z[15]),
.Y(n1318) );
AO22XLTS U2151 ( .A0(n1942), .A1(data_in[14]), .B0(n1941), .B1(d_ff1_Z[14]),
.Y(n1319) );
AO22XLTS U2152 ( .A0(n1942), .A1(data_in[13]), .B0(n1941), .B1(d_ff1_Z[13]),
.Y(n1320) );
AO22XLTS U2153 ( .A0(n1942), .A1(data_in[12]), .B0(n1940), .B1(d_ff1_Z[12]),
.Y(n1321) );
AO22XLTS U2154 ( .A0(n1942), .A1(data_in[11]), .B0(n1940), .B1(d_ff1_Z[11]),
.Y(n1322) );
AO22XLTS U2155 ( .A0(n1953), .A1(data_in[10]), .B0(n1940), .B1(d_ff1_Z[10]),
.Y(n1323) );
AO22XLTS U2156 ( .A0(n1953), .A1(data_in[9]), .B0(n1940), .B1(d_ff1_Z[9]),
.Y(n1324) );
AO22XLTS U2157 ( .A0(n1953), .A1(data_in[8]), .B0(n1940), .B1(d_ff1_Z[8]),
.Y(n1325) );
AO22XLTS U2158 ( .A0(n1953), .A1(data_in[7]), .B0(n1939), .B1(d_ff1_Z[7]),
.Y(n1326) );
AO22XLTS U2159 ( .A0(n1953), .A1(data_in[6]), .B0(n1939), .B1(d_ff1_Z[6]),
.Y(n1327) );
AO22XLTS U2160 ( .A0(n1953), .A1(data_in[5]), .B0(n1939), .B1(d_ff1_Z[5]),
.Y(n1328) );
AO22XLTS U2161 ( .A0(n1948), .A1(data_in[4]), .B0(n1939), .B1(d_ff1_Z[4]),
.Y(n1329) );
AO22XLTS U2162 ( .A0(n1942), .A1(data_in[3]), .B0(n1939), .B1(d_ff1_Z[3]),
.Y(n1330) );
AO22XLTS U2163 ( .A0(n1942), .A1(data_in[2]), .B0(n1939), .B1(d_ff1_Z[2]),
.Y(n1331) );
AO22XLTS U2164 ( .A0(n1942), .A1(data_in[1]), .B0(n1939), .B1(d_ff1_Z[1]),
.Y(n1332) );
AO22XLTS U2165 ( .A0(n1942), .A1(data_in[0]), .B0(n1952), .B1(d_ff1_Z[0]),
.Y(n1333) );
NOR3X6TS U2166 ( .A(n1503), .B(n1491), .C(n1676), .Y(n1476) );
INVX2TS U2167 ( .A(n1504), .Y(n2195) );
INVX2TS U2168 ( .A(n1877), .Y(n1806) );
CLKBUFX2TS U2169 ( .A(cont_iter_out[3]), .Y(n2049) );
BUFX3TS U2170 ( .A(n2120), .Y(n2176) );
CLKBUFX2TS U2171 ( .A(n1518), .Y(n1526) );
BUFX3TS U2172 ( .A(n1518), .Y(n1525) );
BUFX3TS U2173 ( .A(n1518), .Y(n1527) );
CLKINVX3TS U2174 ( .A(n1524), .Y(n2345) );
CLKINVX3TS U2175 ( .A(n1524), .Y(n2340) );
INVX2TS U2176 ( .A(n1524), .Y(n2344) );
INVX2TS U2177 ( .A(n1524), .Y(n2346) );
INVX2TS U2178 ( .A(n2340), .Y(n1487) );
INVX2TS U2179 ( .A(n1487), .Y(n1488) );
INVX2TS U2180 ( .A(n1487), .Y(n1489) );
INVX2TS U2181 ( .A(n2100), .Y(n1490) );
INVX2TS U2182 ( .A(cont_iter_out[2]), .Y(n1491) );
CLKINVX3TS U2183 ( .A(n1529), .Y(n2320) );
CLKINVX3TS U2184 ( .A(n1529), .Y(n2325) );
CLKINVX3TS U2185 ( .A(n1529), .Y(n2301) );
INVX2TS U2186 ( .A(n1529), .Y(n2300) );
INVX2TS U2187 ( .A(n2301), .Y(n1492) );
INVX2TS U2188 ( .A(n1492), .Y(n1493) );
INVX2TS U2189 ( .A(n1492), .Y(n1494) );
INVX2TS U2190 ( .A(n1477), .Y(n1495) );
CLKINVX3TS U2191 ( .A(n1499), .Y(n1496) );
INVX2TS U2192 ( .A(n1880), .Y(n1497) );
INVX2TS U2193 ( .A(n1880), .Y(n1498) );
INVX2TS U2194 ( .A(n1479), .Y(n1499) );
INVX2TS U2195 ( .A(n1479), .Y(n1500) );
INVX2TS U2196 ( .A(n1487), .Y(n1501) );
INVX2TS U2197 ( .A(n1487), .Y(n1502) );
INVX2TS U2198 ( .A(n2049), .Y(n1503) );
INVX2TS U2199 ( .A(n1503), .Y(n1504) );
INVX2TS U2200 ( .A(n1503), .Y(n1505) );
AOI211X1TS U2201 ( .A0(n1476), .A1(n1486), .B0(n1896), .C0(n1932), .Y(n1898)
);
NOR2X4TS U2202 ( .A(cordic_FSM_state_reg[2]), .B(n2222), .Y(n1932) );
OAI21XLTS U2203 ( .A0(n2237), .A1(n1877), .B0(n1861), .Y(add_subt_dataA[62])
);
AOI222X1TS U2204 ( .A0(d_ff2_Z[46]), .A1(n1792), .B0(d_ff2_Y[46]), .B1(n1497), .C0(d_ff2_X[46]), .C1(n1780), .Y(n1769) );
AOI222X1TS U2205 ( .A0(d_ff2_Z[45]), .A1(n1789), .B0(d_ff2_Y[45]), .B1(n1871), .C0(d_ff2_X[45]), .C1(n1780), .Y(n1778) );
AOI222X1TS U2206 ( .A0(d_ff2_Z[44]), .A1(n1789), .B0(d_ff2_Y[44]), .B1(n1893), .C0(d_ff2_X[44]), .C1(n1780), .Y(n1771) );
AOI222X1TS U2207 ( .A0(d_ff2_Z[43]), .A1(n1727), .B0(d_ff2_Y[43]), .B1(n1782), .C0(d_ff2_X[43]), .C1(n1780), .Y(n1779) );
AOI222X1TS U2208 ( .A0(d_ff2_Z[42]), .A1(n1792), .B0(d_ff2_Y[42]), .B1(n1871), .C0(d_ff2_X[42]), .C1(n1780), .Y(n1772) );
AOI222X1TS U2209 ( .A0(d_ff2_Z[41]), .A1(n1892), .B0(d_ff2_Y[41]), .B1(n1893), .C0(d_ff2_X[41]), .C1(n1780), .Y(n1768) );
AOI222X1TS U2210 ( .A0(d_ff2_Z[40]), .A1(n1727), .B0(d_ff2_Y[40]), .B1(n1782), .C0(d_ff2_X[40]), .C1(n1780), .Y(n1775) );
AOI222X1TS U2211 ( .A0(d_ff2_Z[39]), .A1(n1789), .B0(d_ff2_Y[39]), .B1(n1893), .C0(d_ff2_X[39]), .C1(n1780), .Y(n1781) );
AOI222X1TS U2212 ( .A0(d_ff2_Z[38]), .A1(n1773), .B0(d_ff2_Y[38]), .B1(n1782), .C0(d_ff2_X[38]), .C1(n1780), .Y(n1774) );
AOI222X1TS U2213 ( .A0(d_ff2_Z[37]), .A1(n1727), .B0(d_ff2_Y[37]), .B1(n1776), .C0(d_ff2_X[37]), .C1(n1780), .Y(n1777) );
AOI222X1TS U2214 ( .A0(d_ff2_Z[36]), .A1(n1773), .B0(d_ff2_Y[36]), .B1(n1893), .C0(d_ff2_X[36]), .C1(n1730), .Y(n1746) );
AOI222X1TS U2215 ( .A0(d_ff2_Z[35]), .A1(n1892), .B0(d_ff2_Y[35]), .B1(n1782), .C0(d_ff2_X[35]), .C1(n1730), .Y(n1749) );
AOI222X1TS U2216 ( .A0(d_ff2_Z[34]), .A1(n1727), .B0(d_ff2_Y[34]), .B1(n1776), .C0(d_ff2_X[34]), .C1(n1910), .Y(n1751) );
AOI222X1TS U2217 ( .A0(d_ff2_Z[33]), .A1(n1727), .B0(d_ff2_Y[33]), .B1(n1776), .C0(d_ff2_X[33]), .C1(n1730), .Y(n1743) );
AOI222X1TS U2218 ( .A0(d_ff2_Z[32]), .A1(n1773), .B0(d_ff2_Y[32]), .B1(n1776), .C0(d_ff2_X[32]), .C1(n1909), .Y(n1748) );
AOI222X1TS U2219 ( .A0(d_ff2_Z[31]), .A1(n1773), .B0(d_ff2_Y[31]), .B1(n1776), .C0(d_ff2_X[31]), .C1(n1730), .Y(n1755) );
AOI222X1TS U2220 ( .A0(d_ff2_Z[30]), .A1(n1773), .B0(d_ff2_Y[30]), .B1(n1776), .C0(d_ff2_X[30]), .C1(n1910), .Y(n1745) );
AOI222X1TS U2221 ( .A0(d_ff2_Z[29]), .A1(n1727), .B0(d_ff2_Y[29]), .B1(n1776), .C0(d_ff2_X[29]), .C1(n1730), .Y(n1747) );
AOI222X1TS U2222 ( .A0(d_ff2_Z[28]), .A1(n1773), .B0(d_ff2_Y[28]), .B1(n1776), .C0(d_ff2_X[28]), .C1(n1909), .Y(n1756) );
AOI222X1TS U2223 ( .A0(d_ff2_Z[27]), .A1(n1770), .B0(d_ff2_Y[27]), .B1(n1776), .C0(d_ff2_X[27]), .C1(n1910), .Y(n1731) );
AOI222X1TS U2224 ( .A0(d_ff2_Z[26]), .A1(n1773), .B0(d_ff2_Y[26]), .B1(n1920), .C0(d_ff2_X[26]), .C1(n1752), .Y(n1750) );
AOI222X1TS U2225 ( .A0(d_ff2_Z[25]), .A1(n1773), .B0(d_ff2_Y[25]), .B1(n1920), .C0(d_ff2_X[25]), .C1(n1752), .Y(n1742) );
AOI222X1TS U2226 ( .A0(d_ff2_Z[24]), .A1(n1773), .B0(d_ff2_Y[24]), .B1(n1920), .C0(d_ff2_X[24]), .C1(n1752), .Y(n1754) );
AOI222X1TS U2227 ( .A0(d_ff2_Z[23]), .A1(n1727), .B0(d_ff2_Y[23]), .B1(n1920), .C0(d_ff2_X[23]), .C1(n1752), .Y(n1728) );
AOI222X1TS U2228 ( .A0(d_ff2_Z[22]), .A1(n1792), .B0(d_ff2_Y[22]), .B1(n1920), .C0(d_ff2_X[22]), .C1(n1752), .Y(n1726) );
AOI222X1TS U2229 ( .A0(d_ff2_Z[21]), .A1(n1770), .B0(d_ff2_Y[21]), .B1(n1776), .C0(d_ff2_X[21]), .C1(n1752), .Y(n1732) );
AOI222X1TS U2230 ( .A0(d_ff2_Z[20]), .A1(n1773), .B0(d_ff2_Y[20]), .B1(n1920), .C0(d_ff2_X[20]), .C1(n1752), .Y(n1744) );
AOI222X1TS U2231 ( .A0(d_ff2_Z[19]), .A1(n1734), .B0(d_ff2_Y[19]), .B1(n1920), .C0(d_ff2_X[19]), .C1(n1752), .Y(n1735) );
AOI222X1TS U2232 ( .A0(d_ff2_Z[18]), .A1(n1770), .B0(d_ff2_Y[18]), .B1(n1920), .C0(d_ff2_X[18]), .C1(n1752), .Y(n1729) );
AOI222X1TS U2233 ( .A0(d_ff2_Z[15]), .A1(n1770), .B0(d_ff2_Y[15]), .B1(n1920), .C0(d_ff2_X[15]), .C1(n1910), .Y(n1691) );
AOI222X1TS U2234 ( .A0(d_ff2_Z[14]), .A1(n1727), .B0(d_ff2_Y[14]), .B1(n1920), .C0(d_ff2_X[14]), .C1(n1909), .Y(n1695) );
AOI222X1TS U2235 ( .A0(d_ff2_Z[5]), .A1(n1911), .B0(d_ff2_Y[5]), .B1(n1753),
.C0(d_ff2_X[5]), .C1(n1910), .Y(n1692) );
AOI222X1TS U2236 ( .A0(d_ff2_Z[4]), .A1(n1911), .B0(d_ff2_Y[4]), .B1(n1806),
.C0(d_ff2_X[4]), .C1(n1909), .Y(n1697) );
AOI222X1TS U2237 ( .A0(d_ff2_Z[3]), .A1(n1734), .B0(d_ff2_Y[3]), .B1(n1753),
.C0(d_ff2_X[3]), .C1(n1694), .Y(n1565) );
AOI222X1TS U2238 ( .A0(d_ff2_Z[2]), .A1(n1911), .B0(d_ff2_Y[2]), .B1(n1806),
.C0(d_ff2_X[2]), .C1(n1909), .Y(n1698) );
AOI222X1TS U2239 ( .A0(d_ff2_Z[1]), .A1(n1734), .B0(d_ff2_Y[1]), .B1(n1753),
.C0(d_ff2_X[1]), .C1(n1730), .Y(n1689) );
AOI222X4TS U2240 ( .A0(n2187), .A1(d_ff2_Z[0]), .B0(n1817), .B1(d_ff_Zn[0]),
.C0(n1821), .C1(d_ff1_Z[0]), .Y(n1757) );
INVX1TS U2241 ( .A(beg_add_subt), .Y(n1897) );
OAI21XLTS U2242 ( .A0(n2292), .A1(n1560), .B0(n1556), .Y(n947) );
OAI32X1TS U2243 ( .A0(n1902), .A1(n1901), .A2(n2230), .B0(n1900), .B1(n1899),
.Y(n1267) );
BUFX3TS U2244 ( .A(n1527), .Y(n1901) );
NOR4X1TS U2245 ( .A(cordic_FSM_state_reg[1]), .B(n2223), .C(n2225), .D(n2229), .Y(ready_cordic) );
OAI32X1TS U2246 ( .A0(cordic_FSM_state_reg[2]), .A1(beg_fsm_cordic), .A2(
n1930), .B0(n1929), .B1(n2225), .Y(n1935) );
OAI21X2TS U2247 ( .A0(n1571), .A1(n2080), .B0(n2065), .Y(n2060) );
NOR2X2TS U2248 ( .A(n1676), .B(n2080), .Y(n1937) );
OAI21X2TS U2249 ( .A0(n1678), .A1(n1563), .B0(n2065), .Y(n2048) );
NOR2X2TS U2250 ( .A(n2100), .B(n1499), .Y(n1678) );
OAI211XLTS U2251 ( .A0(n1569), .A1(n2087), .B0(n2023), .C0(n1564), .Y(n938)
);
OAI211XLTS U2252 ( .A0(n2076), .A1(n1515), .B0(n2062), .C0(n2023), .Y(n926)
);
OAI21X2TS U2253 ( .A0(n2051), .A1(n2039), .B0(n2089), .Y(n2023) );
CLKINVX3TS U2254 ( .A(n1860), .Y(n1920) );
NOR2X2TS U2255 ( .A(n2100), .B(n1496), .Y(n1699) );
CLKINVX3TS U2256 ( .A(n1525), .Y(n2319) );
CLKINVX3TS U2257 ( .A(n1525), .Y(n2297) );
CLKINVX3TS U2258 ( .A(n1525), .Y(n2298) );
CLKINVX3TS U2259 ( .A(n1525), .Y(n2299) );
CLKINVX3TS U2260 ( .A(n1525), .Y(n2318) );
AOI222X4TS U2261 ( .A0(n1911), .A1(d_ff3_LUT_out[44]), .B0(n1887), .B1(
d_ff3_sh_x_out[44]), .C0(n1886), .C1(d_ff3_sh_y_out[44]), .Y(n1764) );
AOI222X4TS U2262 ( .A0(n1911), .A1(d_ff3_LUT_out[52]), .B0(n1887), .B1(
d_ff3_sh_x_out[52]), .C0(n1886), .C1(d_ff3_sh_y_out[52]), .Y(n1761) );
AOI222X4TS U2263 ( .A0(n1911), .A1(d_ff3_LUT_out[49]), .B0(n1887), .B1(
d_ff3_sh_x_out[49]), .C0(n1886), .C1(d_ff3_sh_y_out[49]), .Y(n1760) );
AOI222X4TS U2264 ( .A0(n1911), .A1(d_ff3_LUT_out[46]), .B0(n1887), .B1(
d_ff3_sh_x_out[46]), .C0(n1886), .C1(d_ff3_sh_y_out[46]), .Y(n1758) );
CLKINVX3TS U2265 ( .A(n2185), .Y(n1842) );
CLKINVX3TS U2266 ( .A(n2185), .Y(n1840) );
CLKINVX3TS U2267 ( .A(n2106), .Y(n1724) );
CLKINVX3TS U2268 ( .A(n2106), .Y(n1717) );
CLKINVX3TS U2269 ( .A(n2106), .Y(n1833) );
CLKINVX3TS U2270 ( .A(n2106), .Y(n2108) );
OAI33X1TS U2271 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n2238), .B0(n2226), .B1(n2224), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n1536) );
CLKINVX3TS U2272 ( .A(n1527), .Y(n2294) );
CLKINVX3TS U2273 ( .A(n1527), .Y(n2296) );
CLKINVX3TS U2274 ( .A(n1527), .Y(n2312) );
CLKINVX3TS U2275 ( .A(n1527), .Y(n2295) );
CLKINVX3TS U2276 ( .A(n1527), .Y(n2313) );
CLKBUFX3TS U2277 ( .A(n1492), .Y(n1524) );
CLKINVX3TS U2278 ( .A(n1518), .Y(n2305) );
CLKINVX3TS U2279 ( .A(n1518), .Y(n2304) );
CLKINVX3TS U2280 ( .A(n1518), .Y(n2332) );
CLKINVX3TS U2281 ( .A(n1518), .Y(n2331) );
CLKINVX3TS U2282 ( .A(n1526), .Y(n2358) );
CLKINVX3TS U2283 ( .A(n1526), .Y(n2363) );
CLKINVX3TS U2284 ( .A(n1526), .Y(n2362) );
CLKINVX3TS U2285 ( .A(n1526), .Y(n2359) );
INVX2TS U2286 ( .A(n1901), .Y(n1506) );
INVX2TS U2287 ( .A(n1487), .Y(n1507) );
INVX2TS U2288 ( .A(n1527), .Y(n1508) );
INVX2TS U2289 ( .A(n1527), .Y(n1509) );
CLKINVX3TS U2290 ( .A(n1492), .Y(n2356) );
INVX2TS U2291 ( .A(n1525), .Y(n1510) );
CLKINVX3TS U2292 ( .A(n1492), .Y(n2357) );
CLKINVX3TS U2293 ( .A(n1487), .Y(n2351) );
CLKINVX3TS U2294 ( .A(n1492), .Y(n2352) );
CLKINVX3TS U2295 ( .A(n1487), .Y(n2353) );
BUFX3TS U2296 ( .A(n1525), .Y(n1529) );
CLKINVX3TS U2297 ( .A(n1901), .Y(n2321) );
CLKINVX3TS U2298 ( .A(n1901), .Y(n2307) );
CLKINVX3TS U2299 ( .A(n1901), .Y(n2303) );
CLKINVX3TS U2300 ( .A(n1901), .Y(n2306) );
CLKINVX3TS U2301 ( .A(n1901), .Y(n2322) );
INVX2TS U2302 ( .A(n1530), .Y(n1511) );
CLKINVX3TS U2303 ( .A(n1530), .Y(n2328) );
CLKINVX3TS U2304 ( .A(n1530), .Y(n2309) );
CLKINVX3TS U2305 ( .A(n1530), .Y(n2310) );
CLKINVX3TS U2306 ( .A(n1530), .Y(n2311) );
BUFX3TS U2307 ( .A(n1527), .Y(n1530) );
CLKINVX3TS U2308 ( .A(n1525), .Y(n2323) );
CLKINVX3TS U2309 ( .A(n1529), .Y(n2336) );
CLKINVX3TS U2310 ( .A(n1524), .Y(n2337) );
CLKINVX3TS U2311 ( .A(n1487), .Y(n2338) );
NOR2X2TS U2312 ( .A(n1504), .B(n2227), .Y(n2055) );
CLKINVX3TS U2313 ( .A(n1530), .Y(n2350) );
AOI32X4TS U2314 ( .A0(n2195), .A1(n2213), .A2(n1552), .B0(d_ff3_sh_y_out[55]), .B1(n2087), .Y(n1551) );
OAI21XLTS U2315 ( .A0(n2065), .A1(d_ff3_LUT_out[1]), .B0(n2029), .Y(n1570)
);
OAI21XLTS U2316 ( .A0(n2213), .A1(d_ff3_LUT_out[6]), .B0(n2029), .Y(n2030)
);
OAI21XLTS U2317 ( .A0(n2065), .A1(d_ff3_LUT_out[7]), .B0(n2048), .Y(n1564)
);
OAI21XLTS U2318 ( .A0(n2065), .A1(d_ff3_LUT_out[14]), .B0(n2060), .Y(n1562)
);
AOI32X4TS U2319 ( .A0(n2100), .A1(n2076), .A2(n1553), .B0(d_ff3_LUT_out[54]),
.B1(n2087), .Y(n1554) );
OAI32X4TS U2320 ( .A0(n2044), .A1(n2043), .A2(n2054), .B0(n2076), .B1(
d_ff3_LUT_out[9]), .Y(n2033) );
OAI32X4TS U2321 ( .A0(n2044), .A1(n1937), .A2(n2042), .B0(d_ff3_LUT_out[26]),
.B1(n2213), .Y(n1538) );
NOR2X2TS U2322 ( .A(n1679), .B(n2152), .Y(n2085) );
NOR2X1TS U2323 ( .A(d_ff2_Y[61]), .B(n2150), .Y(n2149) );
OAI211XLTS U2324 ( .A0(n1682), .A1(n2025), .B0(n1577), .C0(n1680), .Y(n912)
);
OAI211XLTS U2325 ( .A0(n1574), .A1(n2073), .B0(n1680), .C0(n1573), .Y(n942)
);
OAI21X2TS U2326 ( .A0(n2040), .A1(n2050), .B0(n2089), .Y(n1680) );
NOR2X2TS U2327 ( .A(d_ff2_Y[57]), .B(n2142), .Y(n2141) );
NOR2X2TS U2328 ( .A(d_ff2_Y[59]), .B(n2144), .Y(n2147) );
NOR2XLTS U2329 ( .A(n1476), .B(n2066), .Y(n2058) );
AOI222X4TS U2330 ( .A0(n1837), .A1(d_ff2_Z[54]), .B0(n1821), .B1(d_ff1_Z[54]), .C0(d_ff_Zn[54]), .C1(n1835), .Y(n1836) );
AOI222X4TS U2331 ( .A0(n1837), .A1(d_ff2_Z[47]), .B0(n1719), .B1(d_ff1_Z[47]), .C0(d_ff_Zn[47]), .C1(n1817), .Y(n1714) );
AOI222X4TS U2332 ( .A0(n1837), .A1(d_ff2_Z[49]), .B0(n1719), .B1(d_ff1_Z[49]), .C0(d_ff_Zn[49]), .C1(n1817), .Y(n1712) );
AOI222X4TS U2333 ( .A0(n1837), .A1(d_ff2_Z[50]), .B0(n1719), .B1(d_ff1_Z[50]), .C0(d_ff_Zn[50]), .C1(n1835), .Y(n1711) );
AOI222X4TS U2334 ( .A0(n1837), .A1(d_ff2_Z[51]), .B0(n1719), .B1(d_ff1_Z[51]), .C0(d_ff_Zn[51]), .C1(n1835), .Y(n1710) );
AOI222X4TS U2335 ( .A0(n1837), .A1(d_ff2_Z[48]), .B0(n1719), .B1(d_ff1_Z[48]), .C0(d_ff_Zn[48]), .C1(n1835), .Y(n1705) );
CLKINVX3TS U2336 ( .A(n2102), .Y(n1837) );
CLKINVX3TS U2337 ( .A(n2102), .Y(n1844) );
CLKINVX3TS U2338 ( .A(n2102), .Y(n2183) );
CLKINVX3TS U2339 ( .A(n2102), .Y(n2105) );
AOI222X4TS U2340 ( .A0(d_ff2_Z[6]), .A1(n1734), .B0(d_ff2_Y[6]), .B1(n1854),
.C0(d_ff2_X[6]), .C1(n1567), .Y(n1568) );
AOI222X4TS U2341 ( .A0(d_ff2_Z[7]), .A1(n1734), .B0(d_ff2_Y[7]), .B1(n1854),
.C0(d_ff2_X[7]), .C1(n1694), .Y(n1566) );
AOI222X4TS U2342 ( .A0(d_ff2_Z[8]), .A1(n1734), .B0(d_ff2_Y[8]), .B1(n1854),
.C0(d_ff2_X[8]), .C1(n1694), .Y(n1701) );
AOI222X4TS U2343 ( .A0(d_ff2_Z[10]), .A1(n1734), .B0(d_ff2_Y[10]), .B1(n1854), .C0(d_ff2_X[10]), .C1(n1730), .Y(n1688) );
AOI222X4TS U2344 ( .A0(d_ff2_Z[11]), .A1(n1770), .B0(d_ff2_Y[11]), .B1(n1854), .C0(d_ff2_X[11]), .C1(n1909), .Y(n1696) );
AOI222X4TS U2345 ( .A0(d_ff2_Z[12]), .A1(n1734), .B0(d_ff2_Y[12]), .B1(n1854), .C0(d_ff2_X[12]), .C1(n1910), .Y(n1693) );
AOI222X4TS U2346 ( .A0(d_ff2_Z[13]), .A1(n1734), .B0(d_ff2_Y[13]), .B1(n1854), .C0(d_ff2_X[13]), .C1(n1730), .Y(n1690) );
AOI222X4TS U2347 ( .A0(d_ff2_Z[16]), .A1(n1770), .B0(d_ff2_Y[16]), .B1(n1854), .C0(d_ff2_X[16]), .C1(n1730), .Y(n1687) );
AOI222X4TS U2348 ( .A0(d_ff2_Z[17]), .A1(n1734), .B0(d_ff2_Y[17]), .B1(n1854), .C0(d_ff2_X[17]), .C1(n1752), .Y(n1733) );
OAI21XLTS U2349 ( .A0(n1989), .A1(n1544), .B0(n1543), .Y(n1269) );
OAI21XLTS U2350 ( .A0(n2093), .A1(n1542), .B0(n1541), .Y(n1268) );
CLKBUFX2TS U2351 ( .A(cordic_FSM_state_reg[3]), .Y(n1512) );
NOR4X2TS U2352 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[0]),
.C(n2225), .D(n2222), .Y(n1902) );
OAI21X2TS U2353 ( .A0(n2049), .A1(n2032), .B0(n2065), .Y(n2086) );
INVX2TS U2354 ( .A(n1528), .Y(n1513) );
INVX2TS U2355 ( .A(n1528), .Y(n1514) );
BUFX3TS U2356 ( .A(n1527), .Y(n1528) );
NOR4X4TS U2357 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[1]),
.C(n2223), .D(n2229), .Y(ack_add_subt) );
BUFX3TS U2358 ( .A(n1770), .Y(n1792) );
BUFX3TS U2359 ( .A(n1694), .Y(n1916) );
BUFX3TS U2360 ( .A(n1567), .Y(n1694) );
BUFX3TS U2361 ( .A(n1683), .Y(n1736) );
BUFX3TS U2362 ( .A(n1664), .Y(n1683) );
AND3X2TS U2363 ( .A(n1896), .B(n2225), .C(n2229), .Y(n1518) );
OR4X2TS U2364 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[1]),
.C(n2223), .D(n1486), .Y(n1519) );
OR2X1TS U2365 ( .A(n1550), .B(d_ff2_Y[55]), .Y(n1549) );
OAI21XLTS U2366 ( .A0(n2065), .A1(d_ff3_LUT_out[25]), .B0(n2060), .Y(n2061)
);
INVX2TS U2367 ( .A(d_ff_Yn[57]), .Y(n2125) );
OAI211XLTS U2368 ( .A0(n2188), .A1(n1938), .B0(n1500), .C0(n1952), .Y(n1658)
);
OAI21XLTS U2369 ( .A0(n2126), .A1(n1657), .B0(n1650), .Y(n957) );
OAI21XLTS U2370 ( .A0(n2290), .A1(n1657), .B0(n1635), .Y(n971) );
OAI21XLTS U2371 ( .A0(n2277), .A1(n1604), .B0(n1585), .Y(n997) );
OAI21XLTS U2372 ( .A0(n2264), .A1(n1624), .B0(n1616), .Y(n1023) );
OAI21XLTS U2373 ( .A0(n2251), .A1(n1629), .B0(n1618), .Y(n1049) );
OAI21XLTS U2374 ( .A0(n2244), .A1(n1645), .B0(n1631), .Y(n1063) );
OAI21XLTS U2375 ( .A0(n2234), .A1(n1860), .B0(n1522), .Y(add_subt_dataA[52])
);
BUFX3TS U2376 ( .A(n2154), .Y(n2215) );
INVX2TS U2377 ( .A(n2215), .Y(n2217) );
NOR2X2TS U2378 ( .A(d_ff2_Y[52]), .B(n2188), .Y(n2136) );
NAND2X1TS U2379 ( .A(d_ff2_Y[53]), .B(n1495), .Y(n1520) );
AOI22X1TS U2380 ( .A0(n1500), .A1(n1480), .B0(n2136), .B1(n1520), .Y(n1534)
);
AOI22X1TS U2381 ( .A0(n1550), .A1(d_ff2_Y[55]), .B0(n1503), .B1(n1549), .Y(
n2139) );
INVX2TS U2382 ( .A(d_ff2_Y[56]), .Y(n2138) );
INVX2TS U2383 ( .A(d_ff2_Y[58]), .Y(n2127) );
INVX2TS U2384 ( .A(d_ff2_Y[60]), .Y(n2146) );
XOR2X1TS U2385 ( .A(d_ff2_Y[62]), .B(n2149), .Y(n1521) );
BUFX3TS U2386 ( .A(n1519), .Y(n2156) );
BUFX3TS U2387 ( .A(n2156), .Y(n2044) );
BUFX3TS U2388 ( .A(n2044), .Y(n2153) );
OR2X2TS U2389 ( .A(sel_mux_2_reg[1]), .B(n2230), .Y(n1860) );
NAND2X1TS U2390 ( .A(n2230), .B(sel_mux_2_reg[1]), .Y(n1906) );
BUFX3TS U2391 ( .A(n1881), .Y(n1878) );
NOR2X1TS U2392 ( .A(sel_mux_2_reg[0]), .B(sel_mux_2_reg[1]), .Y(n1567) );
BUFX3TS U2393 ( .A(n1909), .Y(n1919) );
AOI22X1TS U2394 ( .A0(n1878), .A1(d_ff2_Z[52]), .B0(d_ff2_X[52]), .B1(n1919),
.Y(n1522) );
AOI22X1TS U2395 ( .A0(d_ff2_X[55]), .A1(n1916), .B0(d_ff2_Z[55]), .B1(n1878),
.Y(n1523) );
NOR2X2TS U2396 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[1]),
.Y(n1896) );
INVX2TS U2397 ( .A(n1524), .Y(n2308) );
INVX2TS U2398 ( .A(n1529), .Y(n2302) );
INVX2TS U2399 ( .A(n1901), .Y(n2339) );
INVX2TS U2400 ( .A(n1901), .Y(n2342) );
INVX2TS U2401 ( .A(n1524), .Y(n2347) );
INVX2TS U2402 ( .A(n1492), .Y(n2348) );
INVX2TS U2403 ( .A(n1524), .Y(n2349) );
INVX2TS U2404 ( .A(n1901), .Y(n2341) );
INVX2TS U2405 ( .A(n1528), .Y(n2333) );
INVX2TS U2406 ( .A(n1528), .Y(n2334) );
INVX2TS U2407 ( .A(n1528), .Y(n2335) );
INVX2TS U2408 ( .A(n1528), .Y(n2317) );
INVX2TS U2409 ( .A(n1529), .Y(n2324) );
INVX2TS U2410 ( .A(n1529), .Y(n2354) );
INVX2TS U2411 ( .A(n1492), .Y(n2355) );
INVX2TS U2412 ( .A(n1529), .Y(n2365) );
INVX2TS U2413 ( .A(n1525), .Y(n2364) );
INVX2TS U2414 ( .A(n1530), .Y(n2361) );
INVX2TS U2415 ( .A(n1528), .Y(n2360) );
INVX2TS U2416 ( .A(n1525), .Y(n2343) );
INVX2TS U2417 ( .A(n1528), .Y(n2314) );
INVX2TS U2418 ( .A(n1528), .Y(n2315) );
INVX2TS U2419 ( .A(n1528), .Y(n2316) );
INVX2TS U2420 ( .A(n1530), .Y(n2329) );
INVX2TS U2421 ( .A(n1530), .Y(n2330) );
INVX2TS U2422 ( .A(n1529), .Y(n2326) );
INVX2TS U2423 ( .A(n1530), .Y(n2327) );
INVX2TS U2424 ( .A(n1526), .Y(n2366) );
NAND2X1TS U2425 ( .A(n2229), .B(n2222), .Y(n1930) );
INVX2TS U2426 ( .A(n1930), .Y(n1532) );
AOI21X1TS U2427 ( .A0(cordic_FSM_state_reg[3]), .A1(cordic_FSM_state_reg[2]),
.B0(n2222), .Y(n1531) );
AOI32X1TS U2428 ( .A0(beg_fsm_cordic), .A1(cordic_FSM_state_reg[0]), .A2(
n1532), .B0(n2223), .B1(n1531), .Y(n1533) );
BUFX3TS U2429 ( .A(n2156), .Y(n2154) );
BUFX3TS U2430 ( .A(n2154), .Y(n2091) );
INVX2TS U2431 ( .A(ack_add_subt), .Y(n1575) );
BUFX3TS U2432 ( .A(n2154), .Y(n2171) );
INVX2TS U2433 ( .A(n2171), .Y(n2221) );
AND3X2TS U2434 ( .A(cordic_FSM_state_reg[2]), .B(n1896), .C(n2229), .Y(n2120) );
NAND2X1TS U2435 ( .A(n2170), .B(sel_mux_1_reg), .Y(n2181) );
BUFX3TS U2436 ( .A(n2182), .Y(n2166) );
OA22X1TS U2437 ( .A0(n2106), .A1(d_ff2_X[19]), .B0(d_ff_Xn[19]), .B1(n2166),
.Y(n658) );
BUFX3TS U2438 ( .A(n2182), .Y(n2177) );
OA22X1TS U2439 ( .A0(n2176), .A1(d_ff2_X[36]), .B0(d_ff_Xn[36]), .B1(n2177),
.Y(n624) );
CLKBUFX2TS U2440 ( .A(n2176), .Y(n2102) );
OA22X1TS U2441 ( .A0(n2102), .A1(d_ff2_X[48]), .B0(d_ff_Xn[48]), .B1(n2177),
.Y(n600) );
OA22X1TS U2442 ( .A0(n2120), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n2166),
.Y(n638) );
CLKBUFX2TS U2443 ( .A(n2176), .Y(n2106) );
OA22X1TS U2444 ( .A0(n2106), .A1(d_ff2_X[49]), .B0(d_ff_Xn[49]), .B1(n2177),
.Y(n598) );
OA22X1TS U2445 ( .A0(n2120), .A1(d_ff2_X[26]), .B0(d_ff_Xn[26]), .B1(n2166),
.Y(n644) );
OA22X1TS U2446 ( .A0(n2120), .A1(d_ff2_X[31]), .B0(d_ff_Xn[31]), .B1(n2166),
.Y(n634) );
OA22X1TS U2447 ( .A0(n2120), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n2166),
.Y(n640) );
OA22X1TS U2448 ( .A0(n2120), .A1(d_ff2_X[24]), .B0(d_ff_Xn[24]), .B1(n2166),
.Y(n648) );
BUFX3TS U2449 ( .A(n2181), .Y(n2180) );
BUFX3TS U2450 ( .A(n2180), .Y(n2185) );
OA22X1TS U2451 ( .A0(n2120), .A1(d_ff2_X[14]), .B0(d_ff_Xn[14]), .B1(n2185),
.Y(n668) );
OA22X1TS U2452 ( .A0(n2176), .A1(d_ff2_X[13]), .B0(d_ff_Xn[13]), .B1(n2185),
.Y(n670) );
CLKBUFX2TS U2453 ( .A(n2120), .Y(n2178) );
BUFX3TS U2454 ( .A(n2181), .Y(n2182) );
BUFX3TS U2455 ( .A(n2182), .Y(n2131) );
OA22X1TS U2456 ( .A0(n2178), .A1(d_ff2_X[0]), .B0(d_ff_Xn[0]), .B1(n2131),
.Y(n696) );
INVX2TS U2457 ( .A(n1896), .Y(n1929) );
CLKBUFX2TS U2458 ( .A(n2008), .Y(n2018) );
INVX2TS U2459 ( .A(n2018), .Y(n2022) );
XOR2X1TS U2460 ( .A(data_output2_63_), .B(n1536), .Y(n1537) );
CLKBUFX2TS U2461 ( .A(n2008), .Y(n2016) );
CLKBUFX2TS U2462 ( .A(n2016), .Y(n2021) );
NAND2X2TS U2463 ( .A(n2100), .B(n1499), .Y(n1676) );
INVX2TS U2464 ( .A(n2055), .Y(n2080) );
NAND3X1TS U2465 ( .A(n2055), .B(n2188), .C(n1495), .Y(n1569) );
INVX2TS U2466 ( .A(n1569), .Y(n2042) );
OAI211X4TS U2467 ( .A0(n1505), .A1(n1496), .B0(n2076), .C0(n2080), .Y(n2053)
);
NAND2X1TS U2468 ( .A(n1538), .B(n2053), .Y(n919) );
BUFX3TS U2469 ( .A(n2154), .Y(n2152) );
INVX2TS U2470 ( .A(n1476), .Y(n2101) );
XNOR2X1TS U2471 ( .A(d_ff1_shift_region_flag_out[1]), .B(d_ff1_operation_out), .Y(n1540) );
CLKXOR2X2TS U2472 ( .A(d_ff1_shift_region_flag_out[0]), .B(n1540), .Y(n1989)
);
NAND4X1TS U2473 ( .A(cordic_FSM_state_reg[3]), .B(n1896), .C(ready_add_subt),
.D(n2225), .Y(n1990) );
NOR2X2TS U2474 ( .A(n1900), .B(n1990), .Y(n1974) );
BUFX3TS U2475 ( .A(n1974), .Y(n1979) );
BUFX3TS U2476 ( .A(n1979), .Y(n1987) );
OAI2BB2XLTS U2477 ( .B0(n1987), .B1(n2129), .A0N(n1979), .A1N(
result_add_subt[60]), .Y(n1141) );
OAI2BB2XLTS U2478 ( .B0(n1987), .B1(n2128), .A0N(n1976), .A1N(
result_add_subt[59]), .Y(n1142) );
OAI2BB2XLTS U2479 ( .B0(n1987), .B1(n2130), .A0N(n1976), .A1N(
result_add_subt[61]), .Y(n1140) );
OAI2BB2XLTS U2480 ( .B0(n1987), .B1(n2132), .A0N(n1976), .A1N(
result_add_subt[62]), .Y(n1139) );
INVX2TS U2481 ( .A(rst), .Y(n564) );
NOR4X1TS U2482 ( .A(cordic_FSM_state_reg[3]), .B(n2223), .C(n1486), .D(n2222), .Y(beg_add_subt) );
NOR3X2TS U2483 ( .A(n1505), .B(cont_iter_out[2]), .C(n1500), .Y(n2040) );
INVX2TS U2484 ( .A(n2037), .Y(n2093) );
INVX2TS U2485 ( .A(n1902), .Y(n1899) );
NAND2X2TS U2486 ( .A(n2100), .B(n1496), .Y(n2078) );
INVX2TS U2487 ( .A(n2078), .Y(n2064) );
NOR2X2TS U2488 ( .A(d_ff2_X[52]), .B(n2188), .Y(n2191) );
NAND2X1TS U2489 ( .A(d_ff2_X[53]), .B(n1495), .Y(n1546) );
AOI22X1TS U2490 ( .A0(n1499), .A1(n2228), .B0(n2191), .B1(n1546), .Y(n2193)
);
AOI2BB1X1TS U2491 ( .A0N(n2197), .A1N(d_ff2_X[55]), .B0(n2196), .Y(n1548) );
BUFX3TS U2492 ( .A(n2154), .Y(n2087) );
NOR2X2TS U2493 ( .A(n2087), .B(n1478), .Y(n2027) );
AOI22X1TS U2494 ( .A0(n1548), .A1(n2027), .B0(d_ff3_sh_x_out[55]), .B1(n2091), .Y(n1547) );
OAI31X1TS U2495 ( .A0(n2049), .A1(n1548), .A2(n2087), .B0(n1547), .Y(n578)
);
INVX2TS U2496 ( .A(n2027), .Y(n1682) );
OAI2BB1X1TS U2497 ( .A0N(d_ff2_Y[55]), .A1N(n1550), .B0(n1549), .Y(n1552) );
NAND2X1TS U2498 ( .A(n2227), .B(n1676), .Y(n2036) );
NOR2XLTS U2499 ( .A(n2227), .B(n1496), .Y(n1553) );
NAND2BX1TS U2500 ( .AN(n1605), .B(sel_mux_3_reg), .Y(n1560) );
CLKBUFX2TS U2501 ( .A(n1605), .Y(n1640) );
BUFX3TS U2502 ( .A(n1640), .Y(n1652) );
AOI22X1TS U2503 ( .A0(d_ff_Xn[63]), .A1(n1555), .B0(data_output2_63_), .B1(
n1652), .Y(n1556) );
AOI22X1TS U2504 ( .A0(d_ff_Xn[61]), .A1(n1555), .B0(sign_inv_out[61]), .B1(
n1652), .Y(n1557) );
INVX2TS U2505 ( .A(n2180), .Y(n2118) );
AOI222X1TS U2506 ( .A0(n2187), .A1(d_ff2_Z[6]), .B0(n1683), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n2118), .Y(n1558) );
INVX2TS U2507 ( .A(n1558), .Y(n883) );
AOI22X1TS U2508 ( .A0(d_ff_Xn[60]), .A1(n1555), .B0(sign_inv_out[60]), .B1(
n1652), .Y(n1559) );
AOI22X1TS U2509 ( .A0(d_ff_Xn[62]), .A1(n1555), .B0(sign_inv_out[62]), .B1(
n1652), .Y(n1561) );
NAND2X2TS U2510 ( .A(n1499), .B(n2227), .Y(n2025) );
NOR2X2TS U2511 ( .A(n1504), .B(n2025), .Y(n2099) );
NAND2X1TS U2512 ( .A(n2100), .B(n2099), .Y(n2082) );
OAI21X2TS U2513 ( .A0(n1500), .A1(n2080), .B0(n2082), .Y(n2038) );
NAND2X1TS U2514 ( .A(n2065), .B(n2038), .Y(n2062) );
NAND2X2TS U2515 ( .A(n2099), .B(n2188), .Y(n2088) );
INVX2TS U2516 ( .A(n2088), .Y(n2051) );
NAND2X1TS U2517 ( .A(n1505), .B(n2227), .Y(n1563) );
OAI32X4TS U2518 ( .A0(n1500), .A1(n2100), .A2(n1563), .B0(n2080), .B1(n1496),
.Y(n2039) );
INVX2TS U2519 ( .A(n1699), .Y(n1571) );
BUFX3TS U2520 ( .A(n1770), .Y(n1734) );
INVX2TS U2521 ( .A(n1565), .Y(add_subt_dataA[3]) );
INVX2TS U2522 ( .A(n1880), .Y(n1854) );
INVX2TS U2523 ( .A(n1566), .Y(add_subt_dataA[7]) );
INVX2TS U2524 ( .A(n1568), .Y(add_subt_dataA[6]) );
NAND2X2TS U2525 ( .A(cont_iter_out[2]), .B(n2027), .Y(n2073) );
NAND2X1TS U2526 ( .A(n2065), .B(n2039), .Y(n2047) );
NAND2X1TS U2527 ( .A(n2082), .B(n1569), .Y(n2050) );
NOR2X1TS U2528 ( .A(n2087), .B(n2050), .Y(n2031) );
OAI31X1TS U2529 ( .A0(n1505), .A1(cont_iter_out[2]), .A2(n2078), .B0(n2031),
.Y(n2029) );
INVX2TS U2530 ( .A(n1678), .Y(n1574) );
OAI22X1TS U2531 ( .A0(n2076), .A1(d_ff3_LUT_out[3]), .B0(n1572), .B1(n2048),
.Y(n1573) );
NOR3X2TS U2532 ( .A(n1476), .B(n2231), .C(n1575), .Y(n1908) );
INVX2TS U2533 ( .A(n2073), .Y(n2063) );
AOI21X1TS U2534 ( .A0(d_ff3_LUT_out[33]), .A1(n2091), .B0(n2063), .Y(n1577)
);
BUFX3TS U2535 ( .A(n1475), .Y(n1599) );
BUFX3TS U2536 ( .A(n1555), .Y(n1597) );
BUFX3TS U2537 ( .A(n1605), .Y(n1654) );
AOI22X1TS U2538 ( .A0(d_ff_Xn[47]), .A1(n1597), .B0(sign_inv_out[47]), .B1(
n1654), .Y(n1578) );
BUFX3TS U2539 ( .A(n1605), .Y(n1601) );
AOI22X1TS U2540 ( .A0(d_ff_Xn[41]), .A1(n1597), .B0(sign_inv_out[41]), .B1(
n1601), .Y(n1579) );
AOI22X1TS U2541 ( .A0(d_ff_Xn[49]), .A1(n1597), .B0(sign_inv_out[49]), .B1(
n1654), .Y(n1580) );
AOI22X1TS U2542 ( .A0(d_ff_Xn[44]), .A1(n1597), .B0(sign_inv_out[44]), .B1(
n1654), .Y(n1581) );
BUFX3TS U2543 ( .A(n1475), .Y(n1604) );
BUFX3TS U2544 ( .A(n1555), .Y(n1602) );
AOI22X1TS U2545 ( .A0(d_ff_Xn[35]), .A1(n1602), .B0(sign_inv_out[35]), .B1(
n1601), .Y(n1582) );
AOI22X1TS U2546 ( .A0(d_ff_Xn[37]), .A1(n1602), .B0(sign_inv_out[37]), .B1(
n1601), .Y(n1583) );
AOI22X1TS U2547 ( .A0(d_ff_Xn[45]), .A1(n1597), .B0(sign_inv_out[45]), .B1(
n1654), .Y(n1584) );
AOI22X1TS U2548 ( .A0(d_ff_Xn[38]), .A1(n1602), .B0(sign_inv_out[38]), .B1(
n1601), .Y(n1585) );
AOI22X1TS U2549 ( .A0(d_ff_Xn[39]), .A1(n1602), .B0(sign_inv_out[39]), .B1(
n1601), .Y(n1586) );
BUFX3TS U2550 ( .A(n1605), .Y(n1619) );
AOI22X1TS U2551 ( .A0(d_ff_Xn[32]), .A1(n1602), .B0(sign_inv_out[32]), .B1(
n1619), .Y(n1587) );
AOI22X1TS U2552 ( .A0(d_ff_Xn[31]), .A1(n1602), .B0(sign_inv_out[31]), .B1(
n1619), .Y(n1588) );
AOI22X1TS U2553 ( .A0(d_ff_Xn[46]), .A1(n1597), .B0(sign_inv_out[46]), .B1(
n1654), .Y(n1589) );
AOI22X1TS U2554 ( .A0(d_ff_Xn[48]), .A1(n1597), .B0(sign_inv_out[48]), .B1(
n1654), .Y(n1590) );
AOI22X1TS U2555 ( .A0(d_ff_Xn[30]), .A1(n1602), .B0(sign_inv_out[30]), .B1(
n1619), .Y(n1591) );
AOI22X1TS U2556 ( .A0(d_ff_Xn[43]), .A1(n1597), .B0(sign_inv_out[43]), .B1(
n1601), .Y(n1592) );
AOI22X1TS U2557 ( .A0(d_ff_Xn[36]), .A1(n1602), .B0(sign_inv_out[36]), .B1(
n1601), .Y(n1593) );
BUFX3TS U2558 ( .A(n1475), .Y(n1624) );
BUFX3TS U2559 ( .A(n1555), .Y(n1622) );
AOI22X1TS U2560 ( .A0(d_ff_Xn[29]), .A1(n1622), .B0(sign_inv_out[29]), .B1(
n1619), .Y(n1594) );
AOI22X1TS U2561 ( .A0(d_ff_Xn[42]), .A1(n1597), .B0(sign_inv_out[42]), .B1(
n1601), .Y(n1595) );
AOI22X1TS U2562 ( .A0(d_ff_Xn[28]), .A1(n1622), .B0(sign_inv_out[28]), .B1(
n1619), .Y(n1596) );
AOI22X1TS U2563 ( .A0(d_ff_Xn[40]), .A1(n1597), .B0(sign_inv_out[40]), .B1(
n1601), .Y(n1598) );
AOI22X1TS U2564 ( .A0(d_ff_Xn[33]), .A1(n1602), .B0(sign_inv_out[33]), .B1(
n1619), .Y(n1600) );
AOI22X1TS U2565 ( .A0(d_ff_Xn[34]), .A1(n1602), .B0(sign_inv_out[34]), .B1(
n1601), .Y(n1603) );
BUFX3TS U2566 ( .A(n1605), .Y(n1626) );
AOI22X1TS U2567 ( .A0(d_ff_Xn[21]), .A1(n1622), .B0(sign_inv_out[21]), .B1(
n1626), .Y(n1606) );
BUFX3TS U2568 ( .A(n1475), .Y(n1629) );
BUFX3TS U2569 ( .A(n1555), .Y(n1627) );
AOI22X1TS U2570 ( .A0(d_ff_Xn[19]), .A1(n1627), .B0(sign_inv_out[19]), .B1(
n1626), .Y(n1607) );
AOI22X1TS U2571 ( .A0(d_ff_Xn[27]), .A1(n1622), .B0(sign_inv_out[27]), .B1(
n1619), .Y(n1608) );
AOI22X1TS U2572 ( .A0(d_ff_Xn[23]), .A1(n1622), .B0(sign_inv_out[23]), .B1(
n1626), .Y(n1609) );
AOI22X1TS U2573 ( .A0(d_ff_Xn[20]), .A1(n1622), .B0(sign_inv_out[20]), .B1(
n1626), .Y(n1610) );
BUFX3TS U2574 ( .A(n1640), .Y(n1642) );
AOI22X1TS U2575 ( .A0(d_ff_Xn[11]), .A1(n1627), .B0(sign_inv_out[11]), .B1(
n1642), .Y(n1611) );
AOI22X1TS U2576 ( .A0(d_ff_Xn[17]), .A1(n1627), .B0(sign_inv_out[17]), .B1(
n1626), .Y(n1612) );
AOI22X1TS U2577 ( .A0(d_ff_Xn[26]), .A1(n1622), .B0(sign_inv_out[26]), .B1(
n1619), .Y(n1613) );
AOI22X1TS U2578 ( .A0(d_ff_Xn[15]), .A1(n1627), .B0(sign_inv_out[15]), .B1(
n1626), .Y(n1614) );
AOI22X1TS U2579 ( .A0(d_ff_Xn[14]), .A1(n1627), .B0(sign_inv_out[14]), .B1(
n1626), .Y(n1615) );
AOI22X1TS U2580 ( .A0(d_ff_Xn[25]), .A1(n1622), .B0(sign_inv_out[25]), .B1(
n1619), .Y(n1616) );
AOI22X1TS U2581 ( .A0(d_ff_Xn[13]), .A1(n1627), .B0(sign_inv_out[13]), .B1(
n1642), .Y(n1617) );
AOI22X1TS U2582 ( .A0(d_ff_Xn[12]), .A1(n1627), .B0(sign_inv_out[12]), .B1(
n1642), .Y(n1618) );
AOI22X1TS U2583 ( .A0(d_ff_Xn[24]), .A1(n1622), .B0(sign_inv_out[24]), .B1(
n1619), .Y(n1620) );
AOI22X1TS U2584 ( .A0(d_ff_Xn[10]), .A1(n1627), .B0(sign_inv_out[10]), .B1(
n1642), .Y(n1621) );
AOI22X1TS U2585 ( .A0(d_ff_Xn[22]), .A1(n1622), .B0(sign_inv_out[22]), .B1(
n1626), .Y(n1623) );
AOI22X1TS U2586 ( .A0(d_ff_Xn[16]), .A1(n1627), .B0(sign_inv_out[16]), .B1(
n1626), .Y(n1625) );
AOI22X1TS U2587 ( .A0(d_ff_Xn[18]), .A1(n1627), .B0(sign_inv_out[18]), .B1(
n1626), .Y(n1628) );
BUFX3TS U2588 ( .A(n1475), .Y(n1645) );
BUFX3TS U2589 ( .A(n1555), .Y(n1643) );
AOI22X1TS U2590 ( .A0(d_ff_Xn[1]), .A1(n1643), .B0(sign_inv_out[1]), .B1(
n1640), .Y(n1630) );
AOI22X1TS U2591 ( .A0(d_ff_Xn[5]), .A1(n1643), .B0(sign_inv_out[5]), .B1(
n1642), .Y(n1631) );
AOI22X1TS U2592 ( .A0(d_ff_Xn[2]), .A1(n1643), .B0(sign_inv_out[2]), .B1(
n1640), .Y(n1632) );
BUFX3TS U2593 ( .A(n1475), .Y(n1657) );
BUFX3TS U2594 ( .A(n1555), .Y(n1655) );
AOI22X1TS U2595 ( .A0(d_ff_Xn[50]), .A1(n1655), .B0(sign_inv_out[50]), .B1(
n1654), .Y(n1633) );
AOI22X1TS U2596 ( .A0(d_ff_Xn[4]), .A1(n1643), .B0(sign_inv_out[4]), .B1(
n1642), .Y(n1634) );
AOI22X1TS U2597 ( .A0(d_ff_Xn[51]), .A1(n1655), .B0(sign_inv_out[51]), .B1(
n1654), .Y(n1635) );
AOI22X1TS U2598 ( .A0(d_ff_Xn[9]), .A1(n1643), .B0(sign_inv_out[9]), .B1(
n1642), .Y(n1636) );
AOI22X1TS U2599 ( .A0(d_ff_Xn[0]), .A1(n1643), .B0(sign_inv_out[0]), .B1(
n1640), .Y(n1637) );
AOI22X1TS U2600 ( .A0(d_ff_Xn[7]), .A1(n1643), .B0(sign_inv_out[7]), .B1(
n1642), .Y(n1638) );
AOI22X1TS U2601 ( .A0(d_ff_Xn[6]), .A1(n1643), .B0(sign_inv_out[6]), .B1(
n1642), .Y(n1639) );
AOI22X1TS U2602 ( .A0(d_ff_Xn[3]), .A1(n1643), .B0(sign_inv_out[3]), .B1(
n1640), .Y(n1641) );
AOI22X1TS U2603 ( .A0(d_ff_Xn[8]), .A1(n1643), .B0(sign_inv_out[8]), .B1(
n1642), .Y(n1644) );
AOI22X1TS U2604 ( .A0(d_ff_Xn[54]), .A1(n1655), .B0(sign_inv_out[54]), .B1(
n1652), .Y(n1646) );
AOI22X1TS U2605 ( .A0(d_ff_Xn[52]), .A1(n1655), .B0(sign_inv_out[52]), .B1(
n1654), .Y(n1647) );
AOI22X1TS U2606 ( .A0(d_ff_Xn[55]), .A1(n1655), .B0(sign_inv_out[55]), .B1(
n1652), .Y(n1648) );
AOI22X1TS U2607 ( .A0(d_ff_Xn[57]), .A1(n1655), .B0(sign_inv_out[57]), .B1(
n1652), .Y(n1649) );
AOI22X1TS U2608 ( .A0(d_ff_Xn[58]), .A1(n1655), .B0(sign_inv_out[58]), .B1(
n1652), .Y(n1650) );
AOI22X1TS U2609 ( .A0(d_ff_Xn[56]), .A1(n1655), .B0(sign_inv_out[56]), .B1(
n1652), .Y(n1651) );
AOI22X1TS U2610 ( .A0(d_ff_Xn[59]), .A1(n1655), .B0(sign_inv_out[59]), .B1(
n1652), .Y(n1653) );
AOI22X1TS U2611 ( .A0(d_ff_Xn[53]), .A1(n1655), .B0(sign_inv_out[53]), .B1(
n1654), .Y(n1656) );
NAND2X1TS U2612 ( .A(cont_var_out[1]), .B(n2231), .Y(n1925) );
NOR2X1TS U2613 ( .A(n1476), .B(n1925), .Y(n1956) );
NAND2X2TS U2614 ( .A(ack_add_subt), .B(n1956), .Y(n1938) );
NAND3X1TS U2615 ( .A(n1932), .B(n2223), .C(n2229), .Y(n1951) );
BUFX3TS U2616 ( .A(n1951), .Y(n1950) );
BUFX3TS U2617 ( .A(n1950), .Y(n1952) );
AOI222X1TS U2618 ( .A0(n1833), .A1(d_ff2_Z[8]), .B0(n1683), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n1739), .Y(n1659) );
INVX2TS U2619 ( .A(n1659), .Y(n881) );
AOI222X1TS U2620 ( .A0(n1717), .A1(d_ff2_Z[10]), .B0(n1683), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n1739), .Y(n1660) );
INVX2TS U2621 ( .A(n1660), .Y(n879) );
AOI222X1TS U2622 ( .A0(n2108), .A1(d_ff2_Z[11]), .B0(n1683), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n1739), .Y(n1661) );
INVX2TS U2623 ( .A(n1661), .Y(n878) );
AOI222X1TS U2624 ( .A0(n1833), .A1(d_ff2_Z[9]), .B0(n1683), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n1739), .Y(n1662) );
INVX2TS U2625 ( .A(n1662), .Y(n880) );
AOI222X1TS U2626 ( .A0(n1717), .A1(d_ff2_Z[7]), .B0(n1683), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n1739), .Y(n1663) );
INVX2TS U2627 ( .A(n1663), .Y(n882) );
BUFX3TS U2628 ( .A(n1664), .Y(n1674) );
AOI222X1TS U2629 ( .A0(n2108), .A1(d_ff2_Z[25]), .B0(n1674), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n1817), .Y(n1665) );
INVX2TS U2630 ( .A(n1665), .Y(n864) );
AOI222X1TS U2631 ( .A0(n1724), .A1(d_ff2_Z[24]), .B0(n1674), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n1819), .Y(n1666) );
INVX2TS U2632 ( .A(n1666), .Y(n865) );
AOI222X1TS U2633 ( .A0(n1724), .A1(d_ff2_Z[27]), .B0(n1674), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n1835), .Y(n1667) );
INVX2TS U2634 ( .A(n1667), .Y(n862) );
AOI222X1TS U2635 ( .A0(n1833), .A1(d_ff2_Z[32]), .B0(n1674), .B1(d_ff1_Z[32]), .C0(d_ff_Zn[32]), .C1(n1817), .Y(n1668) );
INVX2TS U2636 ( .A(n1668), .Y(n857) );
AOI222X1TS U2637 ( .A0(n1724), .A1(d_ff2_Z[26]), .B0(n1674), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n1835), .Y(n1669) );
INVX2TS U2638 ( .A(n1669), .Y(n863) );
AOI222X1TS U2639 ( .A0(n1717), .A1(d_ff2_Z[30]), .B0(n1674), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n1817), .Y(n1670) );
INVX2TS U2640 ( .A(n1670), .Y(n859) );
AOI222X1TS U2641 ( .A0(n2108), .A1(d_ff2_Z[33]), .B0(n1674), .B1(d_ff1_Z[33]), .C0(d_ff_Zn[33]), .C1(n1835), .Y(n1671) );
INVX2TS U2642 ( .A(n1671), .Y(n856) );
AOI222X1TS U2643 ( .A0(n1833), .A1(d_ff2_Z[29]), .B0(n1674), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n1817), .Y(n1672) );
INVX2TS U2644 ( .A(n1672), .Y(n860) );
AOI222X1TS U2645 ( .A0(n1717), .A1(d_ff2_Z[28]), .B0(n1674), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n1835), .Y(n1673) );
INVX2TS U2646 ( .A(n1673), .Y(n861) );
AOI222X1TS U2647 ( .A0(n2108), .A1(d_ff2_Z[31]), .B0(n1674), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n1817), .Y(n1675) );
INVX2TS U2648 ( .A(n1675), .Y(n858) );
OAI211XLTS U2649 ( .A0(n1676), .A1(n1938), .B0(cont_iter_out[2]), .C0(n1952),
.Y(n1677) );
OAI31X1TS U2650 ( .A0(n1938), .A1(n1490), .A2(n2025), .B0(n1677), .Y(n1339)
);
NAND2X1TS U2651 ( .A(n2064), .B(n2227), .Y(n2032) );
NOR3X1TS U2652 ( .A(cont_iter_out[0]), .B(n2025), .C(n1682), .Y(n2035) );
AOI222X1TS U2653 ( .A0(n2108), .A1(d_ff2_Z[13]), .B0(n1736), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n1739), .Y(n1684) );
INVX2TS U2654 ( .A(n1684), .Y(n876) );
AOI222X1TS U2655 ( .A0(n1833), .A1(d_ff2_Z[12]), .B0(n1736), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n1739), .Y(n1685) );
INVX2TS U2656 ( .A(n1685), .Y(n877) );
INVX2TS U2657 ( .A(n1686), .Y(n884) );
BUFX3TS U2658 ( .A(n1694), .Y(n1730) );
INVX2TS U2659 ( .A(n1687), .Y(add_subt_dataA[16]) );
INVX2TS U2660 ( .A(n1688), .Y(add_subt_dataA[10]) );
INVX2TS U2661 ( .A(n1689), .Y(add_subt_dataA[1]) );
INVX2TS U2662 ( .A(n1690), .Y(add_subt_dataA[13]) );
INVX2TS U2663 ( .A(n1860), .Y(n1753) );
BUFX3TS U2664 ( .A(n1694), .Y(n1910) );
INVX2TS U2665 ( .A(n1691), .Y(add_subt_dataA[15]) );
BUFX3TS U2666 ( .A(n1770), .Y(n1911) );
INVX2TS U2667 ( .A(n1692), .Y(add_subt_dataA[5]) );
INVX2TS U2668 ( .A(n1693), .Y(add_subt_dataA[12]) );
BUFX3TS U2669 ( .A(n1694), .Y(n1909) );
INVX2TS U2670 ( .A(n1695), .Y(add_subt_dataA[14]) );
INVX2TS U2671 ( .A(n1696), .Y(add_subt_dataA[11]) );
INVX2TS U2672 ( .A(n1697), .Y(add_subt_dataA[4]) );
INVX2TS U2673 ( .A(n1698), .Y(add_subt_dataA[2]) );
AOI211X1TS U2674 ( .A0(n1699), .A1(n2195), .B0(n2086), .C0(n2038), .Y(n2052)
);
INVX2TS U2675 ( .A(n1701), .Y(add_subt_dataA[8]) );
BUFX3TS U2676 ( .A(n1736), .Y(n1723) );
AOI222X1TS U2677 ( .A0(n1724), .A1(d_ff2_Z[21]), .B0(n1723), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n1819), .Y(n1702) );
INVX2TS U2678 ( .A(n1702), .Y(n868) );
BUFX3TS U2679 ( .A(n1736), .Y(n1719) );
AOI222X1TS U2680 ( .A0(n2183), .A1(d_ff2_Z[44]), .B0(n1719), .B1(d_ff1_Z[44]), .C0(d_ff_Zn[44]), .C1(n1840), .Y(n1703) );
INVX2TS U2681 ( .A(n1703), .Y(n845) );
INVX2TS U2682 ( .A(n1704), .Y(n836) );
INVX2TS U2683 ( .A(n1705), .Y(n841) );
INVX2TS U2684 ( .A(n1706), .Y(n837) );
AOI222X1TS U2685 ( .A0(n1724), .A1(d_ff2_Z[23]), .B0(n1723), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n1819), .Y(n1707) );
INVX2TS U2686 ( .A(n1707), .Y(n866) );
AOI222X1TS U2687 ( .A0(n1717), .A1(d_ff2_Z[15]), .B0(n1723), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n1739), .Y(n1708) );
INVX2TS U2688 ( .A(n1708), .Y(n874) );
AOI222X1TS U2689 ( .A0(n2105), .A1(d_ff2_Z[45]), .B0(n1719), .B1(d_ff1_Z[45]), .C0(d_ff_Zn[45]), .C1(n1842), .Y(n1709) );
INVX2TS U2690 ( .A(n1709), .Y(n844) );
INVX2TS U2691 ( .A(n1710), .Y(n838) );
INVX2TS U2692 ( .A(n1711), .Y(n839) );
INVX2TS U2693 ( .A(n1712), .Y(n840) );
AOI222X1TS U2694 ( .A0(n1724), .A1(d_ff2_Z[19]), .B0(n1723), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n1819), .Y(n1713) );
INVX2TS U2695 ( .A(n1713), .Y(n870) );
INVX2TS U2696 ( .A(n1714), .Y(n842) );
AOI222X1TS U2697 ( .A0(n2108), .A1(d_ff2_Z[14]), .B0(n1723), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n1739), .Y(n1715) );
INVX2TS U2698 ( .A(n1715), .Y(n875) );
AOI222X1TS U2699 ( .A0(n1724), .A1(d_ff2_Z[17]), .B0(n1723), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n1819), .Y(n1716) );
INVX2TS U2700 ( .A(n1716), .Y(n872) );
AOI222X1TS U2701 ( .A0(n1833), .A1(d_ff2_Z[16]), .B0(n1723), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n1819), .Y(n1718) );
INVX2TS U2702 ( .A(n1718), .Y(n873) );
AOI222X1TS U2703 ( .A0(n1844), .A1(d_ff2_Z[46]), .B0(n1719), .B1(d_ff1_Z[46]), .C0(d_ff_Zn[46]), .C1(n1835), .Y(n1720) );
INVX2TS U2704 ( .A(n1720), .Y(n843) );
AOI222X1TS U2705 ( .A0(n1724), .A1(d_ff2_Z[22]), .B0(n1723), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n1819), .Y(n1721) );
INVX2TS U2706 ( .A(n1721), .Y(n867) );
AOI222X1TS U2707 ( .A0(n1724), .A1(d_ff2_Z[18]), .B0(n1723), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n1819), .Y(n1722) );
INVX2TS U2708 ( .A(n1722), .Y(n871) );
AOI222X1TS U2709 ( .A0(n1724), .A1(d_ff2_Z[20]), .B0(n1723), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n1819), .Y(n1725) );
INVX2TS U2710 ( .A(n1725), .Y(n869) );
BUFX3TS U2711 ( .A(n1730), .Y(n1752) );
INVX2TS U2712 ( .A(n1726), .Y(add_subt_dataA[22]) );
INVX2TS U2713 ( .A(n1728), .Y(add_subt_dataA[23]) );
INVX2TS U2714 ( .A(n1729), .Y(add_subt_dataA[18]) );
BUFX3TS U2715 ( .A(n1877), .Y(n1880) );
INVX2TS U2716 ( .A(n1731), .Y(add_subt_dataA[27]) );
INVX2TS U2717 ( .A(n1732), .Y(add_subt_dataA[21]) );
INVX2TS U2718 ( .A(n1733), .Y(add_subt_dataA[17]) );
INVX2TS U2719 ( .A(n1735), .Y(add_subt_dataA[19]) );
BUFX3TS U2720 ( .A(n1736), .Y(n1821) );
INVX2TS U2721 ( .A(n1737), .Y(n886) );
AOI222X1TS U2722 ( .A0(n2187), .A1(d_ff2_Z[1]), .B0(n1821), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n1840), .Y(n1738) );
INVX2TS U2723 ( .A(n1738), .Y(n888) );
AOI222X1TS U2724 ( .A0(n2187), .A1(d_ff2_Z[2]), .B0(n1821), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n1739), .Y(n1740) );
INVX2TS U2725 ( .A(n1740), .Y(n887) );
INVX2TS U2726 ( .A(n1741), .Y(n885) );
BUFX3TS U2727 ( .A(n1792), .Y(n1773) );
INVX2TS U2728 ( .A(n1742), .Y(add_subt_dataA[25]) );
INVX2TS U2729 ( .A(n1743), .Y(add_subt_dataA[33]) );
INVX2TS U2730 ( .A(n1744), .Y(add_subt_dataA[20]) );
INVX2TS U2731 ( .A(n1745), .Y(add_subt_dataA[30]) );
INVX2TS U2732 ( .A(n1877), .Y(n1782) );
INVX2TS U2733 ( .A(n1746), .Y(add_subt_dataA[36]) );
INVX2TS U2734 ( .A(n1747), .Y(add_subt_dataA[29]) );
INVX2TS U2735 ( .A(n1748), .Y(add_subt_dataA[32]) );
INVX2TS U2736 ( .A(n1749), .Y(add_subt_dataA[35]) );
INVX2TS U2737 ( .A(n1750), .Y(add_subt_dataA[26]) );
INVX2TS U2738 ( .A(n1751), .Y(add_subt_dataA[34]) );
INVX2TS U2739 ( .A(n1754), .Y(add_subt_dataA[24]) );
INVX2TS U2740 ( .A(n1755), .Y(add_subt_dataA[31]) );
INVX2TS U2741 ( .A(n1756), .Y(add_subt_dataA[28]) );
INVX2TS U2742 ( .A(n1757), .Y(n889) );
INVX2TS U2743 ( .A(n1880), .Y(n1887) );
BUFX3TS U2744 ( .A(n1910), .Y(n1886) );
INVX2TS U2745 ( .A(n1758), .Y(add_subt_dataB[46]) );
BUFX3TS U2746 ( .A(n1910), .Y(n1851) );
AOI222X1TS U2747 ( .A0(d_ff3_LUT_out[36]), .A1(n1792), .B0(n1852), .B1(
d_ff3_sh_x_out[36]), .C0(n1851), .C1(d_ff3_sh_y_out[36]), .Y(n1759) );
INVX2TS U2748 ( .A(n1759), .Y(add_subt_dataB[36]) );
INVX2TS U2749 ( .A(n1760), .Y(add_subt_dataB[49]) );
INVX2TS U2750 ( .A(n1761), .Y(add_subt_dataB[52]) );
AOI222X1TS U2751 ( .A0(d_ff3_LUT_out[35]), .A1(n1792), .B0(n1813), .B1(
d_ff3_sh_x_out[35]), .C0(n1851), .C1(d_ff3_sh_y_out[35]), .Y(n1762) );
INVX2TS U2752 ( .A(n1762), .Y(add_subt_dataB[35]) );
AOI222X1TS U2753 ( .A0(n1911), .A1(d_ff3_LUT_out[37]), .B0(n1852), .B1(
d_ff3_sh_x_out[37]), .C0(n1851), .C1(d_ff3_sh_y_out[37]), .Y(n1763) );
INVX2TS U2754 ( .A(n1763), .Y(add_subt_dataB[37]) );
INVX2TS U2755 ( .A(n1764), .Y(add_subt_dataB[44]) );
AOI222X1TS U2756 ( .A0(d_ff3_LUT_out[34]), .A1(n1792), .B0(n1852), .B1(
d_ff3_sh_x_out[34]), .C0(n1851), .C1(d_ff3_sh_y_out[34]), .Y(n1765) );
INVX2TS U2757 ( .A(n1765), .Y(add_subt_dataB[34]) );
BUFX3TS U2758 ( .A(n1792), .Y(n1814) );
AOI222X1TS U2759 ( .A0(d_ff3_LUT_out[30]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[30]), .C0(n1851), .C1(d_ff3_sh_y_out[30]), .Y(n1766) );
INVX2TS U2760 ( .A(n1766), .Y(add_subt_dataB[30]) );
INVX2TS U2761 ( .A(n1767), .Y(add_subt_dataB[29]) );
BUFX3TS U2762 ( .A(n1909), .Y(n1780) );
INVX2TS U2763 ( .A(n1768), .Y(add_subt_dataA[41]) );
INVX2TS U2764 ( .A(n1769), .Y(add_subt_dataA[46]) );
BUFX3TS U2765 ( .A(n1770), .Y(n1789) );
INVX2TS U2766 ( .A(n1771), .Y(add_subt_dataA[44]) );
INVX2TS U2767 ( .A(n1877), .Y(n1893) );
INVX2TS U2768 ( .A(n1772), .Y(add_subt_dataA[42]) );
INVX2TS U2769 ( .A(n1774), .Y(add_subt_dataA[38]) );
INVX2TS U2770 ( .A(n1775), .Y(add_subt_dataA[40]) );
INVX2TS U2771 ( .A(n1777), .Y(add_subt_dataA[37]) );
INVX2TS U2772 ( .A(n1778), .Y(add_subt_dataA[45]) );
INVX2TS U2773 ( .A(n1779), .Y(add_subt_dataA[43]) );
INVX2TS U2774 ( .A(n1781), .Y(add_subt_dataA[39]) );
BUFX3TS U2775 ( .A(n1909), .Y(n1889) );
INVX2TS U2776 ( .A(n1783), .Y(add_subt_dataA[47]) );
INVX2TS U2777 ( .A(n1784), .Y(add_subt_dataA[49]) );
INVX2TS U2778 ( .A(n1785), .Y(add_subt_dataA[0]) );
INVX2TS U2779 ( .A(n1786), .Y(add_subt_dataA[50]) );
INVX2TS U2780 ( .A(n1787), .Y(add_subt_dataA[48]) );
INVX2TS U2781 ( .A(n1788), .Y(add_subt_dataA[51]) );
INVX2TS U2782 ( .A(n1790), .Y(add_subt_dataA[54]) );
BUFX3TS U2783 ( .A(n1694), .Y(n1812) );
AOI222X1TS U2784 ( .A0(n1911), .A1(d_ff3_LUT_out[20]), .B0(n1497), .B1(
d_ff3_sh_x_out[20]), .C0(n1812), .C1(d_ff3_sh_y_out[20]), .Y(n1791) );
INVX2TS U2785 ( .A(n1791), .Y(add_subt_dataB[20]) );
BUFX3TS U2786 ( .A(n1792), .Y(n1810) );
BUFX3TS U2787 ( .A(n1694), .Y(n1867) );
AOI222X1TS U2788 ( .A0(d_ff3_LUT_out[18]), .A1(n1810), .B0(n1497), .B1(
d_ff3_sh_x_out[18]), .C0(n1867), .C1(d_ff3_sh_y_out[18]), .Y(n1793) );
INVX2TS U2789 ( .A(n1793), .Y(add_subt_dataB[18]) );
AOI222X1TS U2790 ( .A0(d_ff3_LUT_out[22]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[22]), .C0(n1812), .C1(d_ff3_sh_y_out[22]), .Y(n1794) );
INVX2TS U2791 ( .A(n1794), .Y(add_subt_dataB[22]) );
AOI222X1TS U2792 ( .A0(d_ff3_LUT_out[16]), .A1(n1810), .B0(n1782), .B1(
d_ff3_sh_x_out[16]), .C0(n1867), .C1(d_ff3_sh_y_out[16]), .Y(n1795) );
INVX2TS U2793 ( .A(n1795), .Y(add_subt_dataB[16]) );
INVX2TS U2794 ( .A(n1796), .Y(add_subt_dataB[14]) );
AOI222X1TS U2795 ( .A0(d_ff3_LUT_out[21]), .A1(n1810), .B0(n1893), .B1(
d_ff3_sh_x_out[21]), .C0(n1812), .C1(d_ff3_sh_y_out[21]), .Y(n1797) );
INVX2TS U2796 ( .A(n1797), .Y(add_subt_dataB[21]) );
AOI222X1TS U2797 ( .A0(d_ff3_LUT_out[12]), .A1(n1810), .B0(n1498), .B1(
d_ff3_sh_x_out[12]), .C0(n1867), .C1(d_ff3_sh_y_out[12]), .Y(n1798) );
INVX2TS U2798 ( .A(n1798), .Y(add_subt_dataB[12]) );
AOI222X1TS U2799 ( .A0(d_ff3_LUT_out[10]), .A1(n1810), .B0(n1498), .B1(
d_ff3_sh_x_out[10]), .C0(n1867), .C1(d_ff3_sh_y_out[10]), .Y(n1799) );
INVX2TS U2800 ( .A(n1799), .Y(add_subt_dataB[10]) );
AOI222X1TS U2801 ( .A0(d_ff3_LUT_out[28]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[28]), .C0(n1812), .C1(d_ff3_sh_y_out[28]), .Y(n1800) );
INVX2TS U2802 ( .A(n1800), .Y(add_subt_dataB[28]) );
AOI222X1TS U2803 ( .A0(d_ff3_LUT_out[13]), .A1(n1810), .B0(n1782), .B1(
d_ff3_sh_x_out[13]), .C0(n1867), .C1(d_ff3_sh_y_out[13]), .Y(n1801) );
INVX2TS U2804 ( .A(n1801), .Y(add_subt_dataB[13]) );
AOI222X1TS U2805 ( .A0(d_ff3_LUT_out[24]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[24]), .C0(n1812), .C1(d_ff3_sh_y_out[24]), .Y(n1802) );
INVX2TS U2806 ( .A(n1802), .Y(add_subt_dataB[24]) );
INVX2TS U2807 ( .A(n1803), .Y(add_subt_dataB[15]) );
AOI222X1TS U2808 ( .A0(d_ff3_LUT_out[31]), .A1(n1814), .B0(n1852), .B1(
d_ff3_sh_x_out[31]), .C0(n1812), .C1(d_ff3_sh_y_out[31]), .Y(n1804) );
INVX2TS U2809 ( .A(n1804), .Y(add_subt_dataB[31]) );
INVX2TS U2810 ( .A(n1805), .Y(add_subt_dataB[26]) );
AOI222X1TS U2811 ( .A0(d_ff3_LUT_out[17]), .A1(n1810), .B0(n1893), .B1(
d_ff3_sh_x_out[17]), .C0(n1867), .C1(d_ff3_sh_y_out[17]), .Y(n1807) );
INVX2TS U2812 ( .A(n1807), .Y(add_subt_dataB[17]) );
INVX2TS U2813 ( .A(n1808), .Y(add_subt_dataB[25]) );
AOI222X1TS U2814 ( .A0(d_ff3_LUT_out[23]), .A1(n1814), .B0(n1813), .B1(
d_ff3_sh_x_out[23]), .C0(n1812), .C1(d_ff3_sh_y_out[23]), .Y(n1809) );
INVX2TS U2815 ( .A(n1809), .Y(add_subt_dataB[23]) );
INVX2TS U2816 ( .A(n1877), .Y(n1871) );
INVX2TS U2817 ( .A(n1811), .Y(add_subt_dataB[11]) );
INVX2TS U2818 ( .A(n1815), .Y(add_subt_dataB[27]) );
BUFX3TS U2819 ( .A(n1821), .Y(n1843) );
AOI222X1TS U2820 ( .A0(n2183), .A1(d_ff2_Z[41]), .B0(n1843), .B1(d_ff1_Z[41]), .C0(d_ff_Zn[41]), .C1(n1842), .Y(n1816) );
INVX2TS U2821 ( .A(n1816), .Y(n848) );
AOI222X1TS U2822 ( .A0(n1833), .A1(d_ff2_Z[34]), .B0(n1843), .B1(d_ff1_Z[34]), .C0(d_ff_Zn[34]), .C1(n1835), .Y(n1818) );
INVX2TS U2823 ( .A(n1818), .Y(n855) );
AOI222X1TS U2824 ( .A0(n1717), .A1(d_ff2_Z[35]), .B0(n1843), .B1(d_ff1_Z[35]), .C0(d_ff_Zn[35]), .C1(n1819), .Y(n1820) );
INVX2TS U2825 ( .A(n1820), .Y(n854) );
INVX2TS U2826 ( .A(n1822), .Y(n826) );
AOI222X1TS U2827 ( .A0(n2105), .A1(d_ff2_Z[40]), .B0(n1843), .B1(d_ff1_Z[40]), .C0(d_ff_Zn[40]), .C1(n1840), .Y(n1823) );
INVX2TS U2828 ( .A(n1823), .Y(n849) );
AOI222X1TS U2829 ( .A0(n1844), .A1(d_ff2_Z[37]), .B0(n1843), .B1(d_ff1_Z[37]), .C0(d_ff_Zn[37]), .C1(n1842), .Y(n1824) );
INVX2TS U2830 ( .A(n1824), .Y(n852) );
AOI222X1TS U2831 ( .A0(n2105), .A1(d_ff2_Z[61]), .B0(n1736), .B1(d_ff1_Z[61]), .C0(d_ff_Zn[61]), .C1(n1842), .Y(n1825) );
INVX2TS U2832 ( .A(n1825), .Y(n828) );
INVX2TS U2833 ( .A(n1826), .Y(n829) );
AOI222X1TS U2834 ( .A0(n2183), .A1(d_ff2_Z[57]), .B0(n1683), .B1(d_ff1_Z[57]), .C0(d_ff_Zn[57]), .C1(n1840), .Y(n1827) );
INVX2TS U2835 ( .A(n1827), .Y(n832) );
AOI222X1TS U2836 ( .A0(n2105), .A1(d_ff2_Z[62]), .B0(n1683), .B1(d_ff1_Z[62]), .C0(d_ff_Zn[62]), .C1(n1842), .Y(n1828) );
INVX2TS U2837 ( .A(n1828), .Y(n827) );
AOI222X1TS U2838 ( .A0(n2183), .A1(d_ff2_Z[38]), .B0(n1843), .B1(d_ff1_Z[38]), .C0(d_ff_Zn[38]), .C1(n1840), .Y(n1829) );
INVX2TS U2839 ( .A(n1829), .Y(n851) );
INVX2TS U2840 ( .A(n1830), .Y(n831) );
AOI222X1TS U2841 ( .A0(n2105), .A1(d_ff2_Z[43]), .B0(n1843), .B1(d_ff1_Z[43]), .C0(d_ff_Zn[43]), .C1(n1842), .Y(n1831) );
INVX2TS U2842 ( .A(n1831), .Y(n846) );
INVX2TS U2843 ( .A(n1832), .Y(n833) );
AOI222X1TS U2844 ( .A0(n2108), .A1(d_ff2_Z[36]), .B0(n1843), .B1(d_ff1_Z[36]), .C0(d_ff_Zn[36]), .C1(n1840), .Y(n1834) );
INVX2TS U2845 ( .A(n1834), .Y(n853) );
INVX2TS U2846 ( .A(n1836), .Y(n835) );
INVX2TS U2847 ( .A(n1838), .Y(n834) );
AOI222X1TS U2848 ( .A0(n1844), .A1(d_ff2_Z[42]), .B0(n1843), .B1(d_ff1_Z[42]), .C0(d_ff_Zn[42]), .C1(n1842), .Y(n1839) );
INVX2TS U2849 ( .A(n1839), .Y(n847) );
AOI222X1TS U2850 ( .A0(n2183), .A1(d_ff2_Z[59]), .B0(n1821), .B1(d_ff1_Z[59]), .C0(d_ff_Zn[59]), .C1(n1842), .Y(n1841) );
INVX2TS U2851 ( .A(n1841), .Y(n830) );
AOI222X1TS U2852 ( .A0(n2183), .A1(d_ff2_Z[39]), .B0(n1843), .B1(d_ff1_Z[39]), .C0(d_ff_Zn[39]), .C1(n1840), .Y(n1845) );
INVX2TS U2853 ( .A(n1845), .Y(n850) );
AOI222X1TS U2854 ( .A0(d_ff3_LUT_out[38]), .A1(n1881), .B0(n1852), .B1(
d_ff3_sh_x_out[38]), .C0(n1851), .C1(d_ff3_sh_y_out[38]), .Y(n1846) );
INVX2TS U2855 ( .A(n1846), .Y(add_subt_dataB[38]) );
AOI222X1TS U2856 ( .A0(d_ff3_LUT_out[42]), .A1(n1881), .B0(n1852), .B1(
d_ff3_sh_x_out[42]), .C0(n1886), .C1(d_ff3_sh_y_out[42]), .Y(n1847) );
INVX2TS U2857 ( .A(n1847), .Y(add_subt_dataB[42]) );
AOI222X1TS U2858 ( .A0(d_ff3_LUT_out[32]), .A1(n1881), .B0(n1852), .B1(
d_ff3_sh_x_out[32]), .C0(n1851), .C1(d_ff3_sh_y_out[32]), .Y(n1848) );
INVX2TS U2859 ( .A(n1848), .Y(add_subt_dataB[32]) );
INVX2TS U2860 ( .A(n1849), .Y(add_subt_dataB[39]) );
AOI222X1TS U2861 ( .A0(d_ff3_LUT_out[40]), .A1(n1881), .B0(n1852), .B1(
d_ff3_sh_x_out[40]), .C0(n1851), .C1(d_ff3_sh_y_out[40]), .Y(n1850) );
INVX2TS U2862 ( .A(n1850), .Y(add_subt_dataB[40]) );
INVX2TS U2863 ( .A(n1853), .Y(add_subt_dataB[33]) );
INVX2TS U2864 ( .A(n1855), .Y(add_subt_dataA[9]) );
AOI22X1TS U2865 ( .A0(n1878), .A1(d_ff2_Z[53]), .B0(d_ff2_X[53]), .B1(n1919),
.Y(n1856) );
AOI22X1TS U2866 ( .A0(d_ff2_X[58]), .A1(n1916), .B0(d_ff2_Z[58]), .B1(n1878),
.Y(n1857) );
AOI22X1TS U2867 ( .A0(d_ff2_X[60]), .A1(n1919), .B0(d_ff2_Z[60]), .B1(n1878),
.Y(n1858) );
AOI22X1TS U2868 ( .A0(d_ff2_X[56]), .A1(n1916), .B0(d_ff2_Z[56]), .B1(n1878),
.Y(n1859) );
AOI22X1TS U2869 ( .A0(d_ff2_X[62]), .A1(n1919), .B0(d_ff2_Z[62]), .B1(n1878),
.Y(n1861) );
BUFX3TS U2870 ( .A(n1881), .Y(n1873) );
BUFX3TS U2871 ( .A(n1916), .Y(n1894) );
INVX2TS U2872 ( .A(n1862), .Y(add_subt_dataB[0]) );
AOI222X1TS U2873 ( .A0(d_ff3_LUT_out[4]), .A1(n1873), .B0(n1871), .B1(
d_ff3_sh_x_out[4]), .C0(n1894), .C1(d_ff3_sh_y_out[4]), .Y(n1863) );
INVX2TS U2874 ( .A(n1863), .Y(add_subt_dataB[4]) );
INVX2TS U2875 ( .A(n1864), .Y(add_subt_dataB[1]) );
INVX2TS U2876 ( .A(n1865), .Y(add_subt_dataB[3]) );
AOI222X1TS U2877 ( .A0(d_ff3_LUT_out[2]), .A1(n1873), .B0(n1871), .B1(
d_ff3_sh_x_out[2]), .C0(n1894), .C1(d_ff3_sh_y_out[2]), .Y(n1866) );
INVX2TS U2878 ( .A(n1866), .Y(add_subt_dataB[2]) );
INVX2TS U2879 ( .A(n1868), .Y(add_subt_dataB[9]) );
INVX2TS U2880 ( .A(n1869), .Y(add_subt_dataB[6]) );
INVX2TS U2881 ( .A(n1870), .Y(add_subt_dataB[5]) );
INVX2TS U2882 ( .A(n1872), .Y(add_subt_dataB[7]) );
INVX2TS U2883 ( .A(n1874), .Y(add_subt_dataA[63]) );
AOI22X1TS U2884 ( .A0(d_ff2_X[57]), .A1(n1916), .B0(d_ff2_Z[57]), .B1(n1878),
.Y(n1875) );
AOI22X1TS U2885 ( .A0(d_ff2_X[61]), .A1(n1916), .B0(d_ff2_Z[61]), .B1(n1878),
.Y(n1876) );
AOI22X1TS U2886 ( .A0(d_ff2_X[59]), .A1(n1919), .B0(d_ff2_Z[59]), .B1(n1878),
.Y(n1879) );
BUFX3TS U2887 ( .A(n1881), .Y(n1892) );
INVX2TS U2888 ( .A(n1882), .Y(add_subt_dataB[45]) );
INVX2TS U2889 ( .A(n1883), .Y(add_subt_dataB[43]) );
INVX2TS U2890 ( .A(n1884), .Y(add_subt_dataB[47]) );
INVX2TS U2891 ( .A(n1885), .Y(add_subt_dataB[54]) );
INVX2TS U2892 ( .A(n1888), .Y(add_subt_dataB[50]) );
INVX2TS U2893 ( .A(n1890), .Y(add_subt_dataB[55]) );
AOI222X1TS U2894 ( .A0(d_ff3_sh_y_out[53]), .A1(n1894), .B0(
d_ff3_sh_x_out[53]), .B1(n1871), .C0(n1892), .C1(d_ff3_LUT_out[53]),
.Y(n1891) );
INVX2TS U2895 ( .A(n1891), .Y(add_subt_dataB[53]) );
AOI222X1TS U2896 ( .A0(d_ff3_sh_y_out[56]), .A1(n1894), .B0(
d_ff3_sh_x_out[56]), .B1(n1871), .C0(n1892), .C1(d_ff3_LUT_out[56]),
.Y(n1895) );
INVX2TS U2897 ( .A(n1895), .Y(add_subt_dataB[56]) );
OAI211XLTS U2898 ( .A0(n1898), .A1(n2229), .B0(n1897), .C0(n1934), .Y(n1345)
);
AOI22X1TS U2899 ( .A0(n1806), .A1(d_ff3_sh_x_out[8]), .B0(n1919), .B1(
d_ff3_sh_y_out[8]), .Y(n1903) );
OAI21XLTS U2900 ( .A0(n1517), .A1(n1906), .B0(n1903), .Y(add_subt_dataB[8])
);
AOI22X1TS U2901 ( .A0(n1753), .A1(d_ff3_sh_x_out[19]), .B0(n1919), .B1(
d_ff3_sh_y_out[19]), .Y(n1904) );
OAI21XLTS U2902 ( .A0(n1515), .A1(n1906), .B0(n1904), .Y(add_subt_dataB[19])
);
AOI22X1TS U2903 ( .A0(n1806), .A1(d_ff3_sh_x_out[41]), .B0(n1919), .B1(
d_ff3_sh_y_out[41]), .Y(n1905) );
OAI21XLTS U2904 ( .A0(n1516), .A1(n1906), .B0(n1905), .Y(add_subt_dataB[41])
);
INVX2TS U2905 ( .A(n1908), .Y(n1907) );
AOI221XLTS U2906 ( .A0(cont_var_out[1]), .A1(n1908), .B0(n1482), .B1(n1907),
.C0(n2089), .Y(n1342) );
AO22XLTS U2907 ( .A0(n1753), .A1(d_ff3_sh_x_out[63]), .B0(n1909), .B1(
d_ff3_sh_y_out[63]), .Y(add_subt_dataB[63]) );
AO22XLTS U2908 ( .A0(d_ff3_sh_y_out[62]), .A1(n1910), .B0(d_ff3_sh_x_out[62]), .B1(n1806), .Y(add_subt_dataB[62]) );
AOI22X1TS U2909 ( .A0(d_ff3_sh_y_out[61]), .A1(n1694), .B0(
d_ff3_sh_x_out[61]), .B1(n1806), .Y(n1912) );
NAND2X2TS U2910 ( .A(d_ff3_LUT_out[48]), .B(n1911), .Y(n1921) );
NAND2X1TS U2911 ( .A(n1912), .B(n1921), .Y(add_subt_dataB[61]) );
AOI22X1TS U2912 ( .A0(d_ff3_sh_y_out[60]), .A1(n1916), .B0(
d_ff3_sh_x_out[60]), .B1(n1753), .Y(n1913) );
NAND2X1TS U2913 ( .A(n1913), .B(n1921), .Y(add_subt_dataB[60]) );
AOI22X1TS U2914 ( .A0(d_ff3_sh_y_out[59]), .A1(n1916), .B0(
d_ff3_sh_x_out[59]), .B1(n1806), .Y(n1914) );
NAND2X1TS U2915 ( .A(n1914), .B(n1921), .Y(add_subt_dataB[59]) );
AOI22X1TS U2916 ( .A0(d_ff3_sh_y_out[58]), .A1(n1916), .B0(
d_ff3_sh_x_out[58]), .B1(n1753), .Y(n1915) );
NAND2X1TS U2917 ( .A(n1915), .B(n1921), .Y(add_subt_dataB[58]) );
AOI22X1TS U2918 ( .A0(d_ff3_sh_y_out[57]), .A1(n1916), .B0(
d_ff3_sh_x_out[57]), .B1(n1753), .Y(n1917) );
NAND2X1TS U2919 ( .A(n1917), .B(n1921), .Y(add_subt_dataB[57]) );
AOI22X1TS U2920 ( .A0(n1753), .A1(d_ff3_sh_x_out[51]), .B0(n1919), .B1(
d_ff3_sh_y_out[51]), .Y(n1918) );
NAND2X1TS U2921 ( .A(n1918), .B(n1921), .Y(add_subt_dataB[51]) );
AOI22X1TS U2922 ( .A0(n1806), .A1(d_ff3_sh_x_out[48]), .B0(n1919), .B1(
d_ff3_sh_y_out[48]), .Y(n1922) );
NAND2X1TS U2923 ( .A(n1922), .B(n1921), .Y(add_subt_dataB[48]) );
AOI2BB2XLTS U2924 ( .B0(d_ff3_sign_out), .B1(n2231), .A0N(n2231), .A1N(
d_ff3_sign_out), .Y(op_add_subt) );
INVX2TS U2925 ( .A(n1932), .Y(n1928) );
NOR2XLTS U2926 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[3]),
.Y(n1924) );
AOI31XLTS U2927 ( .A0(cordic_FSM_state_reg[0]), .A1(cordic_FSM_state_reg[3]),
.A2(ack_cordic), .B0(cordic_FSM_state_reg[1]), .Y(n1923) );
OAI21X1TS U2928 ( .A0(n1924), .A1(n1923), .B0(cordic_FSM_state_reg[2]), .Y(
n1927) );
CLKAND2X2TS U2929 ( .A(ready_add_subt), .B(n2225), .Y(n1931) );
NAND2X1TS U2930 ( .A(n1952), .B(n1938), .Y(n1936) );
AOI22X1TS U2931 ( .A0(cont_iter_out[0]), .A1(n1936), .B0(n1938), .B1(n1490),
.Y(n1341) );
INVX2TS U2932 ( .A(n1952), .Y(n1942) );
INVX2TS U2933 ( .A(n1937), .Y(n2057) );
OAI22X1TS U2934 ( .A0(n1942), .A1(n1503), .B0(n1938), .B1(n2057), .Y(n1338)
);
INVX2TS U2935 ( .A(n1950), .Y(n1955) );
CLKBUFX2TS U2936 ( .A(n1950), .Y(n1944) );
CLKBUFX2TS U2937 ( .A(n1940), .Y(n1939) );
INVX2TS U2938 ( .A(n1944), .Y(n1948) );
INVX2TS U2939 ( .A(n1944), .Y(n1953) );
BUFX3TS U2940 ( .A(n1940), .Y(n1941) );
INVX2TS U2941 ( .A(n1944), .Y(n1943) );
INVX2TS U2942 ( .A(n1950), .Y(n1946) );
BUFX3TS U2943 ( .A(n1940), .Y(n1954) );
BUFX3TS U2944 ( .A(n1944), .Y(n1945) );
INVX2TS U2945 ( .A(n1944), .Y(n1949) );
BUFX3TS U2946 ( .A(n1950), .Y(n1947) );
NOR2BX1TS U2947 ( .AN(n1956), .B(n1990), .Y(n1957) );
BUFX3TS U2948 ( .A(n1966), .Y(n1958) );
INVX2TS U2949 ( .A(n1958), .Y(n1959) );
BUFX3TS U2950 ( .A(n1966), .Y(n1971) );
BUFX3TS U2951 ( .A(n1971), .Y(n1960) );
INVX2TS U2952 ( .A(n1971), .Y(n1961) );
BUFX3TS U2953 ( .A(n1971), .Y(n1962) );
INVX2TS U2954 ( .A(n1971), .Y(n1963) );
CLKBUFX2TS U2955 ( .A(n1966), .Y(n1967) );
BUFX3TS U2956 ( .A(n1967), .Y(n1964) );
INVX2TS U2957 ( .A(n1971), .Y(n1965) );
INVX2TS U2958 ( .A(n1966), .Y(n1968) );
CLKBUFX2TS U2959 ( .A(n1967), .Y(n1972) );
BUFX3TS U2960 ( .A(n1967), .Y(n1969) );
INVX2TS U2961 ( .A(n1971), .Y(n1970) );
INVX2TS U2962 ( .A(n1971), .Y(n1973) );
BUFX3TS U2963 ( .A(n1974), .Y(n1977) );
OAI2BB2XLTS U2964 ( .B0(n1977), .B1(n2239), .A0N(n1979), .A1N(
result_add_subt[0]), .Y(n1201) );
BUFX3TS U2965 ( .A(n1979), .Y(n1975) );
OAI2BB2XLTS U2966 ( .B0(n1975), .B1(n2240), .A0N(n1979), .A1N(
result_add_subt[1]), .Y(n1200) );
OAI2BB2XLTS U2967 ( .B0(n1977), .B1(n2241), .A0N(n1979), .A1N(
result_add_subt[2]), .Y(n1199) );
BUFX3TS U2968 ( .A(n1979), .Y(n1986) );
OAI2BB2XLTS U2969 ( .B0(n1975), .B1(n2242), .A0N(n1986), .A1N(
result_add_subt[3]), .Y(n1198) );
OAI2BB2XLTS U2970 ( .B0(n1975), .B1(n2243), .A0N(n1986), .A1N(
result_add_subt[4]), .Y(n1197) );
BUFX3TS U2971 ( .A(n1974), .Y(n1984) );
OAI2BB2XLTS U2972 ( .B0(n1977), .B1(n2244), .A0N(n1984), .A1N(
result_add_subt[5]), .Y(n1196) );
OAI2BB2XLTS U2973 ( .B0(n1977), .B1(n2245), .A0N(n1986), .A1N(
result_add_subt[6]), .Y(n1195) );
OAI2BB2XLTS U2974 ( .B0(n1975), .B1(n2246), .A0N(n1986), .A1N(
result_add_subt[7]), .Y(n1194) );
BUFX3TS U2975 ( .A(n1979), .Y(n1983) );
OAI2BB2XLTS U2976 ( .B0(n1975), .B1(n2247), .A0N(n1983), .A1N(
result_add_subt[8]), .Y(n1193) );
CLKBUFX2TS U2977 ( .A(n1979), .Y(n1976) );
BUFX3TS U2978 ( .A(n1976), .Y(n1978) );
OAI2BB2XLTS U2979 ( .B0(n1978), .B1(n2248), .A0N(n1984), .A1N(
result_add_subt[9]), .Y(n1192) );
OAI2BB2XLTS U2980 ( .B0(n1978), .B1(n2249), .A0N(n1983), .A1N(
result_add_subt[10]), .Y(n1191) );
BUFX3TS U2981 ( .A(n1974), .Y(n1981) );
OAI2BB2XLTS U2982 ( .B0(n1975), .B1(n2250), .A0N(n1981), .A1N(
result_add_subt[11]), .Y(n1190) );
OAI2BB2XLTS U2983 ( .B0(n1975), .B1(n2251), .A0N(n1983), .A1N(
result_add_subt[12]), .Y(n1189) );
OAI2BB2XLTS U2984 ( .B0(n1978), .B1(n2252), .A0N(n1981), .A1N(
result_add_subt[13]), .Y(n1188) );
OAI2BB2XLTS U2985 ( .B0(n1975), .B1(n2253), .A0N(n1983), .A1N(
result_add_subt[14]), .Y(n1187) );
OAI2BB2XLTS U2986 ( .B0(n1975), .B1(n2254), .A0N(n1981), .A1N(
result_add_subt[15]), .Y(n1186) );
BUFX3TS U2987 ( .A(n1974), .Y(n1980) );
OAI2BB2XLTS U2988 ( .B0(n1978), .B1(n2255), .A0N(n1980), .A1N(
result_add_subt[16]), .Y(n1185) );
OAI2BB2XLTS U2989 ( .B0(n1978), .B1(n2256), .A0N(n1981), .A1N(
result_add_subt[17]), .Y(n1184) );
OAI2BB2XLTS U2990 ( .B0(n1975), .B1(n2257), .A0N(n1980), .A1N(
result_add_subt[18]), .Y(n1183) );
OAI2BB2XLTS U2991 ( .B0(n1978), .B1(n2258), .A0N(n1983), .A1N(
result_add_subt[19]), .Y(n1182) );
OAI2BB2XLTS U2992 ( .B0(n1978), .B1(n2259), .A0N(n1977), .A1N(
result_add_subt[20]), .Y(n1181) );
OAI2BB2XLTS U2993 ( .B0(n1978), .B1(n2260), .A0N(n1981), .A1N(
result_add_subt[21]), .Y(n1180) );
OAI2BB2XLTS U2994 ( .B0(n1978), .B1(n2261), .A0N(n1977), .A1N(
result_add_subt[22]), .Y(n1179) );
BUFX3TS U2995 ( .A(n1976), .Y(n1988) );
OAI2BB2XLTS U2996 ( .B0(n1988), .B1(n2262), .A0N(n1980), .A1N(
result_add_subt[23]), .Y(n1178) );
OAI2BB2XLTS U2997 ( .B0(n1988), .B1(n2263), .A0N(n1977), .A1N(
result_add_subt[24]), .Y(n1177) );
OAI2BB2XLTS U2998 ( .B0(n1988), .B1(n2264), .A0N(n1980), .A1N(
result_add_subt[25]), .Y(n1176) );
OAI2BB2XLTS U2999 ( .B0(n1988), .B1(n2265), .A0N(n1980), .A1N(
result_add_subt[26]), .Y(n1175) );
OAI2BB2XLTS U3000 ( .B0(n1988), .B1(n2266), .A0N(n1977), .A1N(
result_add_subt[27]), .Y(n1174) );
OAI2BB2XLTS U3001 ( .B0(n1988), .B1(n2267), .A0N(n1977), .A1N(
result_add_subt[28]), .Y(n1173) );
OAI2BB2XLTS U3002 ( .B0(n1988), .B1(n2268), .A0N(n1980), .A1N(
result_add_subt[29]), .Y(n1172) );
OAI2BB2XLTS U3003 ( .B0(n1988), .B1(n2269), .A0N(n1977), .A1N(
result_add_subt[30]), .Y(n1171) );
OAI2BB2XLTS U3004 ( .B0(n1978), .B1(n2270), .A0N(n1980), .A1N(
result_add_subt[31]), .Y(n1170) );
OAI2BB2XLTS U3005 ( .B0(n1988), .B1(n2271), .A0N(n1981), .A1N(
result_add_subt[32]), .Y(n1169) );
BUFX3TS U3006 ( .A(n1976), .Y(n1982) );
OAI2BB2XLTS U3007 ( .B0(n1982), .B1(n2272), .A0N(n1980), .A1N(
result_add_subt[33]), .Y(n1168) );
OAI2BB2XLTS U3008 ( .B0(n1982), .B1(n2273), .A0N(n1980), .A1N(
result_add_subt[34]), .Y(n1167) );
OAI2BB2XLTS U3009 ( .B0(n1982), .B1(n2274), .A0N(n1981), .A1N(
result_add_subt[35]), .Y(n1166) );
OAI2BB2XLTS U3010 ( .B0(n1982), .B1(n2275), .A0N(n1980), .A1N(
result_add_subt[36]), .Y(n1165) );
OAI2BB2XLTS U3011 ( .B0(n1982), .B1(n2276), .A0N(n1981), .A1N(
result_add_subt[37]), .Y(n1164) );
OAI2BB2XLTS U3012 ( .B0(n1982), .B1(n2277), .A0N(n1983), .A1N(
result_add_subt[38]), .Y(n1163) );
OAI2BB2XLTS U3013 ( .B0(n1982), .B1(n2278), .A0N(n1983), .A1N(
result_add_subt[39]), .Y(n1162) );
OAI2BB2XLTS U3014 ( .B0(n1982), .B1(n2279), .A0N(n1981), .A1N(
result_add_subt[40]), .Y(n1161) );
OAI2BB2XLTS U3015 ( .B0(n1982), .B1(n2280), .A0N(n1983), .A1N(
result_add_subt[41]), .Y(n1160) );
OAI2BB2XLTS U3016 ( .B0(n1982), .B1(n2281), .A0N(n1981), .A1N(
result_add_subt[42]), .Y(n1159) );
BUFX3TS U3017 ( .A(n1976), .Y(n1985) );
OAI2BB2XLTS U3018 ( .B0(n1985), .B1(n2282), .A0N(n1983), .A1N(
result_add_subt[43]), .Y(n1158) );
OAI2BB2XLTS U3019 ( .B0(n1985), .B1(n2283), .A0N(n1984), .A1N(
result_add_subt[44]), .Y(n1157) );
OAI2BB2XLTS U3020 ( .B0(n1985), .B1(n2284), .A0N(n1983), .A1N(
result_add_subt[45]), .Y(n1156) );
OAI2BB2XLTS U3021 ( .B0(n1985), .B1(n2285), .A0N(n1984), .A1N(
result_add_subt[46]), .Y(n1155) );
OAI2BB2XLTS U3022 ( .B0(n1985), .B1(n2286), .A0N(n1984), .A1N(
result_add_subt[47]), .Y(n1154) );
OAI2BB2XLTS U3023 ( .B0(n1985), .B1(n2287), .A0N(n1984), .A1N(
result_add_subt[48]), .Y(n1153) );
OAI2BB2XLTS U3024 ( .B0(n1985), .B1(n2288), .A0N(n1984), .A1N(
result_add_subt[49]), .Y(n1152) );
OAI2BB2XLTS U3025 ( .B0(n1985), .B1(n2289), .A0N(n1984), .A1N(
result_add_subt[50]), .Y(n1151) );
OAI2BB2XLTS U3026 ( .B0(n1985), .B1(n2290), .A0N(n1984), .A1N(
result_add_subt[51]), .Y(n1150) );
OAI2BB2XLTS U3027 ( .B0(n1985), .B1(n2121), .A0N(n1984), .A1N(
result_add_subt[52]), .Y(n1149) );
OAI2BB2XLTS U3028 ( .B0(n1987), .B1(n2122), .A0N(n1986), .A1N(
result_add_subt[53]), .Y(n1148) );
OAI2BB2XLTS U3029 ( .B0(n1987), .B1(n2291), .A0N(n1986), .A1N(
result_add_subt[54]), .Y(n1147) );
OAI2BB2XLTS U3030 ( .B0(n1987), .B1(n2123), .A0N(n1986), .A1N(
result_add_subt[55]), .Y(n1146) );
OAI2BB2XLTS U3031 ( .B0(n1987), .B1(n2124), .A0N(n1986), .A1N(
result_add_subt[56]), .Y(n1145) );
OAI2BB2XLTS U3032 ( .B0(n1987), .B1(n2125), .A0N(n1986), .A1N(
result_add_subt[57]), .Y(n1144) );
OAI2BB2XLTS U3033 ( .B0(n1987), .B1(n2126), .A0N(n1986), .A1N(
result_add_subt[58]), .Y(n1143) );
OAI2BB2XLTS U3034 ( .B0(n1988), .B1(n2292), .A0N(n1979), .A1N(
result_add_subt[63]), .Y(n1138) );
BUFX3TS U3035 ( .A(n2004), .Y(n2000) );
INVX2TS U3036 ( .A(n2000), .Y(n1992) );
BUFX3TS U3037 ( .A(n2004), .Y(n2005) );
BUFX3TS U3038 ( .A(n2005), .Y(n1993) );
INVX2TS U3039 ( .A(n2004), .Y(n1994) );
BUFX3TS U3040 ( .A(n2000), .Y(n1995) );
INVX2TS U3041 ( .A(n2004), .Y(n1996) );
BUFX3TS U3042 ( .A(n2004), .Y(n1997) );
INVX2TS U3043 ( .A(n2004), .Y(n1998) );
BUFX3TS U3044 ( .A(n2005), .Y(n1999) );
INVX2TS U3045 ( .A(n2005), .Y(n2001) );
BUFX3TS U3046 ( .A(n2000), .Y(n2002) );
INVX2TS U3047 ( .A(n2005), .Y(n2003) );
INVX2TS U3048 ( .A(n2004), .Y(n2006) );
BUFX3TS U3049 ( .A(n2008), .Y(n2010) );
INVX2TS U3050 ( .A(n2010), .Y(n2007) );
BUFX3TS U3051 ( .A(n2008), .Y(n2012) );
INVX2TS U3052 ( .A(n2012), .Y(n2009) );
INVX2TS U3053 ( .A(n2012), .Y(n2011) );
BUFX3TS U3054 ( .A(n2016), .Y(n2013) );
INVX2TS U3055 ( .A(n2012), .Y(n2014) );
BUFX3TS U3056 ( .A(n2016), .Y(n2015) );
INVX2TS U3057 ( .A(n2018), .Y(n2017) );
BUFX3TS U3058 ( .A(n2016), .Y(n2019) );
INVX2TS U3059 ( .A(n2018), .Y(n2020) );
NAND3X1TS U3060 ( .A(cont_iter_out[2]), .B(n1499), .C(n2027), .Y(n2068) );
BUFX3TS U3061 ( .A(n2156), .Y(n2095) );
AOI21X2TS U3062 ( .A0(cont_iter_out[2]), .A1(n1499), .B0(n1505), .Y(n2090)
);
AOI31X1TS U3063 ( .A0(n2090), .A1(n2088), .A2(n2037), .B0(n2091), .Y(n2074)
);
AOI22X1TS U3064 ( .A0(n2027), .A1(n2227), .B0(n2091), .B1(d_ff3_LUT_out[5]),
.Y(n2028) );
NAND2X1TS U3065 ( .A(n2028), .B(n2062), .Y(n940) );
NAND2X1TS U3066 ( .A(n2065), .B(n2051), .Y(n2072) );
AOI22X1TS U3067 ( .A0(n1517), .A1(n2087), .B0(n2053), .B1(n2031), .Y(n937)
);
INVX2TS U3068 ( .A(n2032), .Y(n2043) );
AOI211X1TS U3069 ( .A0(n1505), .A1(n2036), .B0(n2153), .C0(n2038), .Y(n2075)
);
INVX2TS U3070 ( .A(n2215), .Y(n2097) );
AOI211X1TS U3071 ( .A0(n2100), .A1(n1496), .B0(n1505), .C0(cont_iter_out[2]),
.Y(n2059) );
NAND2X1TS U3072 ( .A(n2097), .B(n2059), .Y(n2098) );
OA21XLTS U3073 ( .A0(n2211), .A1(d_ff3_LUT_out[12]), .B0(n2098), .Y(n933) );
NOR3X1TS U3074 ( .A(n2043), .B(n2039), .C(n2038), .Y(n2041) );
NOR2X2TS U3075 ( .A(n2040), .B(n2152), .Y(n2096) );
OAI32X1TS U3076 ( .A0(n2044), .A1(n2043), .A2(n2042), .B0(d_ff3_LUT_out[15]),
.B1(n2213), .Y(n2045) );
AOI21X1TS U3077 ( .A0(n2090), .A1(n2078), .B0(n2091), .Y(n2046) );
BUFX3TS U3078 ( .A(n2156), .Y(n2158) );
OAI2BB1X1TS U3079 ( .A0N(d_ff3_LUT_out[17]), .A1N(n2158), .B0(n2047), .Y(
n928) );
AOI211X1TS U3080 ( .A0(cont_iter_out[2]), .A1(n2049), .B0(n2093), .C0(n2048),
.Y(n2083) );
OA22X1TS U3081 ( .A0(n2051), .A1(n2079), .B0(n2097), .B1(d_ff3_LUT_out[18]),
.Y(n927) );
OAI2BB1X1TS U3082 ( .A0N(d_ff3_LUT_out[22]), .A1N(n2158), .B0(n2053), .Y(
n923) );
AOI211X1TS U3083 ( .A0(n2055), .A1(n2064), .B0(n2060), .C0(n2054), .Y(n2056)
);
INVX2TS U3084 ( .A(n2056), .Y(n2066) );
INVX2TS U3085 ( .A(n2156), .Y(n2104) );
NAND2X1TS U3086 ( .A(n2059), .B(n2088), .Y(n2077) );
CLKBUFX2TS U3087 ( .A(n2154), .Y(n2163) );
CLKBUFX2TS U3088 ( .A(n2163), .Y(n2167) );
BUFX3TS U3089 ( .A(n2167), .Y(n2103) );
NAND2X1TS U3090 ( .A(n2064), .B(n2063), .Y(n2069) );
OAI22X1TS U3091 ( .A0(n1476), .A1(n2066), .B0(n2213), .B1(d_ff3_LUT_out[27]),
.Y(n2067) );
OAI2BB1X1TS U3092 ( .A0N(d_ff3_LUT_out[28]), .A1N(n2158), .B0(n2086), .Y(
n917) );
NAND2X1TS U3093 ( .A(d_ff3_LUT_out[29]), .B(n2091), .Y(n2070) );
OAI21X1TS U3094 ( .A0(n2093), .A1(n2077), .B0(n2213), .Y(n2081) );
OAI2BB1X1TS U3095 ( .A0N(d_ff3_LUT_out[32]), .A1N(n2158), .B0(n2081), .Y(
n913) );
AOI31X1TS U3096 ( .A0(n2090), .A1(n2078), .A2(n2088), .B0(n2091), .Y(n2092)
);
OA21XLTS U3097 ( .A0(n2211), .A1(d_ff3_LUT_out[35]), .B0(n2079), .Y(n910) );
OAI2BB1X1TS U3098 ( .A0N(d_ff3_LUT_out[36]), .A1N(n2158), .B0(n2086), .Y(
n909) );
INVX2TS U3099 ( .A(n2044), .Y(n2206) );
OAI2BB1X1TS U3100 ( .A0N(d_ff3_LUT_out[38]), .A1N(n2158), .B0(n2081), .Y(
n907) );
OAI2BB2XLTS U3101 ( .B0(n2097), .B1(d_ff3_LUT_out[39]), .A0N(n2083), .A1N(
n2082), .Y(n2084) );
OAI2BB1X1TS U3102 ( .A0N(d_ff3_LUT_out[40]), .A1N(n2158), .B0(n2086), .Y(
n905) );
AOI32X1TS U3103 ( .A0(n2090), .A1(n2076), .A2(n2088), .B0(n1516), .B1(n2087),
.Y(n904) );
AOI31X1TS U3104 ( .A0(n2195), .A1(n1484), .A2(n2227), .B0(n2091), .Y(n2094)
);
OA22X1TS U3105 ( .A0(n2093), .A1(n2098), .B0(n2097), .B1(d_ff3_LUT_out[45]),
.Y(n900) );
OA22X1TS U3106 ( .A0(n2099), .A1(n2098), .B0(n2097), .B1(d_ff3_LUT_out[50]),
.Y(n895) );
INVX2TS U3107 ( .A(n2180), .Y(n2175) );
INVX2TS U3108 ( .A(n2180), .Y(n2112) );
INVX2TS U3109 ( .A(n2171), .Y(n2107) );
BUFX3TS U3110 ( .A(n2167), .Y(n2109) );
INVX2TS U3111 ( .A(n2182), .Y(n2114) );
INVX2TS U3112 ( .A(n2171), .Y(n2115) );
INVX2TS U3113 ( .A(n2171), .Y(n2110) );
INVX2TS U3114 ( .A(n2178), .Y(n2111) );
INVX2TS U3115 ( .A(n2182), .Y(n2172) );
BUFX3TS U3116 ( .A(n2171), .Y(n2113) );
INVX2TS U3117 ( .A(n2171), .Y(n2119) );
INVX2TS U3118 ( .A(n2178), .Y(n2116) );
BUFX3TS U3119 ( .A(n2167), .Y(n2117) );
CLKBUFX2TS U3120 ( .A(n2180), .Y(n2179) );
INVX2TS U3121 ( .A(n2179), .Y(n2219) );
INVX2TS U3122 ( .A(n2178), .Y(n2218) );
INVX2TS U3123 ( .A(n2179), .Y(n2164) );
INVX2TS U3124 ( .A(n2176), .Y(n2174) );
BUFX3TS U3125 ( .A(n2167), .Y(n2220) );
INVX2TS U3126 ( .A(n2179), .Y(n2186) );
BUFX3TS U3127 ( .A(n2163), .Y(n2161) );
INVX2TS U3128 ( .A(n2178), .Y(n2155) );
BUFX3TS U3129 ( .A(n2120), .Y(n2184) );
BUFX3TS U3130 ( .A(n2184), .Y(n2133) );
OAI22X1TS U3131 ( .A0(n2133), .A1(n2234), .B0(n2121), .B1(n2180), .Y(n720)
);
OAI22X1TS U3132 ( .A0(n2133), .A1(n1480), .B0(n2122), .B1(n2185), .Y(n719)
);
OAI22X1TS U3133 ( .A0(n2133), .A1(n2232), .B0(n2123), .B1(n2185), .Y(n717)
);
OAI22X1TS U3134 ( .A0(n2133), .A1(n2138), .B0(n2124), .B1(n2182), .Y(n716)
);
OAI22X1TS U3135 ( .A0(n2133), .A1(n2233), .B0(n2125), .B1(n2131), .Y(n715)
);
OAI22X1TS U3136 ( .A0(n2133), .A1(n2127), .B0(n2126), .B1(n2131), .Y(n714)
);
OAI22X1TS U3137 ( .A0(n2133), .A1(n2235), .B0(n2128), .B1(n2131), .Y(n713)
);
OAI22X1TS U3138 ( .A0(n2133), .A1(n2146), .B0(n2129), .B1(n2131), .Y(n712)
);
OAI22X1TS U3139 ( .A0(n2133), .A1(n2236), .B0(n2130), .B1(n2131), .Y(n711)
);
OAI22X1TS U3140 ( .A0(n2133), .A1(n2237), .B0(n2132), .B1(n2131), .Y(n710)
);
AOI21X1TS U3141 ( .A0(d_ff2_Y[52]), .A1(n2188), .B0(n2136), .Y(n2134) );
AOI22X1TS U3142 ( .A0(n1477), .A1(n1480), .B0(d_ff2_Y[53]), .B1(n1496), .Y(
n2135) );
XNOR2X1TS U3143 ( .A(n2136), .B(n2135), .Y(n2137) );
AOI21X1TS U3144 ( .A0(d_ff2_Y[57]), .A1(n2142), .B0(n2141), .Y(n2143) );
AOI21X1TS U3145 ( .A0(d_ff2_Y[59]), .A1(n2144), .B0(n2147), .Y(n2145) );
AOI21X1TS U3146 ( .A0(d_ff2_Y[61]), .A1(n2150), .B0(n2149), .Y(n2151) );
INVX2TS U3147 ( .A(n2182), .Y(n2168) );
OA22X1TS U3148 ( .A0(n2184), .A1(d_ff2_X[3]), .B0(d_ff_Xn[3]), .B1(n2180),
.Y(n690) );
OA22X1TS U3149 ( .A0(n2184), .A1(d_ff2_X[6]), .B0(d_ff_Xn[6]), .B1(n2182),
.Y(n684) );
INVX2TS U3150 ( .A(n2215), .Y(n2157) );
OA22X1TS U3151 ( .A0(n2184), .A1(d_ff2_X[7]), .B0(d_ff_Xn[7]), .B1(n2180),
.Y(n682) );
OA22X1TS U3152 ( .A0(n2184), .A1(d_ff2_X[8]), .B0(d_ff_Xn[8]), .B1(n2182),
.Y(n680) );
OA22X1TS U3153 ( .A0(n2184), .A1(d_ff2_X[9]), .B0(d_ff_Xn[9]), .B1(n2179),
.Y(n678) );
OA22X1TS U3154 ( .A0(n2102), .A1(d_ff2_X[11]), .B0(d_ff_Xn[11]), .B1(n2179),
.Y(n674) );
INVX2TS U3155 ( .A(n2163), .Y(n2159) );
INVX2TS U3156 ( .A(n2176), .Y(n2160) );
INVX2TS U3157 ( .A(n2163), .Y(n2162) );
OA22X1TS U3158 ( .A0(n2170), .A1(d_ff2_X[32]), .B0(d_ff_Xn[32]), .B1(n2166),
.Y(n632) );
BUFX3TS U3159 ( .A(n2167), .Y(n2165) );
OA22X1TS U3160 ( .A0(n2170), .A1(d_ff2_X[34]), .B0(d_ff_Xn[34]), .B1(n2166),
.Y(n628) );
OA22X1TS U3161 ( .A0(n2170), .A1(d_ff2_X[35]), .B0(d_ff_Xn[35]), .B1(n2166),
.Y(n626) );
INVX2TS U3162 ( .A(n2163), .Y(n2169) );
OA22X1TS U3163 ( .A0(n2170), .A1(d_ff2_X[39]), .B0(d_ff_Xn[39]), .B1(n2177),
.Y(n618) );
OA22X1TS U3164 ( .A0(n2170), .A1(d_ff2_X[41]), .B0(d_ff_Xn[41]), .B1(n2177),
.Y(n614) );
OA22X1TS U3165 ( .A0(n2170), .A1(d_ff2_X[42]), .B0(d_ff_Xn[42]), .B1(n2166),
.Y(n612) );
BUFX3TS U3166 ( .A(n2167), .Y(n2173) );
OA22X1TS U3167 ( .A0(n2170), .A1(d_ff2_X[43]), .B0(d_ff_Xn[43]), .B1(n2177),
.Y(n610) );
OA22X1TS U3168 ( .A0(n2170), .A1(d_ff2_X[45]), .B0(d_ff_Xn[45]), .B1(n2177),
.Y(n606) );
OA22X1TS U3169 ( .A0(n2170), .A1(d_ff2_X[46]), .B0(d_ff_Xn[46]), .B1(n2177),
.Y(n604) );
INVX2TS U3170 ( .A(n2171), .Y(n2204) );
OA22X1TS U3171 ( .A0(n2176), .A1(d_ff2_X[53]), .B0(d_ff_Xn[53]), .B1(n2177),
.Y(n591) );
OA22X1TS U3172 ( .A0(n2178), .A1(d_ff2_X[54]), .B0(d_ff_Xn[54]), .B1(n2177),
.Y(n590) );
OA22X1TS U3173 ( .A0(d_ff_Xn[55]), .A1(n2179), .B0(d_ff2_X[55]), .B1(n2184),
.Y(n589) );
OA22X1TS U3174 ( .A0(d_ff_Xn[57]), .A1(n2180), .B0(d_ff2_X[57]), .B1(n2184),
.Y(n587) );
OA22X1TS U3175 ( .A0(d_ff_Xn[59]), .A1(n2182), .B0(d_ff2_X[59]), .B1(n2184),
.Y(n585) );
OA22X1TS U3176 ( .A0(d_ff_Xn[61]), .A1(n2185), .B0(d_ff2_X[61]), .B1(n2184),
.Y(n583) );
AOI21X1TS U3177 ( .A0(d_ff2_X[52]), .A1(n1484), .B0(n2191), .Y(n2189) );
AOI22X1TS U3178 ( .A0(n1500), .A1(n2228), .B0(d_ff2_X[53]), .B1(n1496), .Y(
n2190) );
XNOR2X1TS U3179 ( .A(n2191), .B(n2190), .Y(n2192) );
OAI22X1TS U3180 ( .A0(n2197), .A1(d_ff2_X[55]), .B0(n2196), .B1(n2195), .Y(
n2198) );
OAI21XLTS U3181 ( .A0(n2198), .A1(n1481), .B0(n2200), .Y(n2199) );
NOR2X2TS U3182 ( .A(d_ff2_X[57]), .B(n2200), .Y(n2202) );
AOI21X1TS U3183 ( .A0(d_ff2_X[57]), .A1(n2200), .B0(n2202), .Y(n2201) );
NOR2X2TS U3184 ( .A(d_ff2_X[59]), .B(n2205), .Y(n2208) );
AOI21X1TS U3185 ( .A0(d_ff2_X[59]), .A1(n2205), .B0(n2208), .Y(n2207) );
NOR2X1TS U3186 ( .A(d_ff2_X[61]), .B(n2210), .Y(n2214) );
AOI21X1TS U3187 ( .A0(d_ff2_X[61]), .A1(n2210), .B0(n2214), .Y(n2212) );
XOR2X1TS U3188 ( .A(d_ff2_X[62]), .B(n2214), .Y(n2216) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk10.tcl_syn.sdf");
endmodule
|
// MBT 9/6/2014
//
// BSG Front Side Bus
//
// This is a *full duplex* front side bus
// that allows output and input traffic
// to proceed independently, from nodes
// into the bsg out assembler; and from
// bsg in assembler to nodes.
//
// It is designed to interoperate with
// the "MURN ring protocol" and nodes,
// per UCSC's rnswitch, but without
// research features and implementing
// full duplex channels instead of a ring
// for performance reasons.
//
// The parameter nodes_p indicates how
// many items are to be chained on the fsb.
//
// bsg_fsb itself does not limit the maximum number
// of nodes; however the bsg_fsb_murn_gateway uses
// the RingPacketType data structure, which currently
// limits us to 4 bits of id's, or 16 nodes.
//
`ifndef FSB_LEGACY
`include "bsg_defines.v"
module bsg_fsb #(parameter `BSG_INV_PARAM( width_p )
,parameter `BSG_INV_PARAM(nodes_p )
// bit vector of master nodes
, parameter enabled_at_start_vec_p = (nodes_p) ' (0)
, parameter snoop_vec_p = (nodes_p) ' (0)
, parameter id_width_p = `BSG_SAFE_CLOG2(nodes_p)
)
(input clk_i
, input reset_i
// from assembler
, input asm_v_i
, input [width_p-1:0] asm_data_i
, output asm_yumi_o
// to asm
, output asm_v_o
, output [width_p-1:0] asm_data_o
, input asm_ready_i
// into nodes
, output [nodes_p-1:0] node_v_o
, output [width_p-1:0] node_data_o [nodes_p-1:0]
, input [nodes_p-1:0] node_ready_i
// into nodes (control)
, output [nodes_p-1:0] node_en_r_o
, output [nodes_p-1:0] node_reset_r_o
// unsupported
// , output [nodes_p-1:0] node_powerup_o
// out of nodes
, input [nodes_p-1:0] node_v_i
, input [width_p-1:0] node_data_i [nodes_p-1:0]
, output [nodes_p-1:0] node_yumi_o
);
genvar i;
// index is node this channel goes out of
wire [nodes_p-1:0] in_hop_v;
wire [width_p-1:0] in_hop_data [nodes_p-1:0];
wire [nodes_p-1:0] in_hop_ready;
// index is node this channel goes in to
wire [nodes_p-1:0] out_hop_v;
wire [width_p-1:0] out_hop_data [nodes_p-1:0];
wire [nodes_p-1:0] out_hop_ready;
assign out_hop_v [nodes_p-1] = 1'b0;
assign out_hop_data[nodes_p-1] = { (width_p) {1'b0} };
wire to_asm_ready;
assign asm_yumi_o = to_asm_ready & asm_v_i;
// make sure packets fall off of the end.
assign in_hop_ready[nodes_p-1] = 1'b1;
for (i = 0; i < nodes_p; i++)
begin : fsb_node
wire node_ready_int, node_v_int, node_en_r_int;
wire [width_p-1:0] node_data_o_int;
// m1 = minus 1
wire [width_p-1:0] out_hop_data_m1;
wire in_hop_ready_m1, out_hop_v_m1;
if (i == 0)
begin
assign to_asm_ready = in_hop_ready_m1;
assign asm_v_o = out_hop_v_m1;
assign asm_data_o = out_hop_data_m1;
end
else
begin
assign in_hop_ready[i-1] = in_hop_ready_m1;
assign out_hop_v[i-1] = out_hop_v_m1;
assign out_hop_data[i-1] = out_hop_data_m1;
end
// note: for critical path optimization, these hops
// can be wrapped in an additional loop that
// instantiates multiple of these nodes, each of which
// handles a subset of data bus.
// create a chain of hops going in from assembler
bsg_front_side_bus_hop_in
#(.width_p(width_p)
,. fan_out_p(2)
) hopin
(.clk_i(clk_i)
,.reset_i(reset_i)
// (i==0) ? 0: avoid vcs complaint of negative index.
,.ready_o(in_hop_ready_m1)
,.v_i ((i==0) ? asm_v_i : in_hop_v [(i==0) ? i: i-1])
,.data_i ((i==0) ? asm_data_i : in_hop_data [(i==0) ? i: i-1])
,.v_o ({node_v_int , in_hop_v [i]})
,.data_o ({node_data_o_int , in_hop_data [i]}) // 1=local node, 0 is next node
// note: the node does valid->ready
// but should be located nearby so it's okay
,.ready_i({node_ready_int, in_hop_ready[i]})
);
// create a chain of hops going out to assembler
bsg_front_side_bus_hop_out #(.width_p(width_p)) hopout
(.clk_i(clk_i)
,.reset_i(reset_i)
// we can't transmit data unless the node is enabled
,.v_i ({node_en_r_int & node_v_i [i], out_hop_v [i]})
,.data_i ({node_data_i [i], out_hop_data[i]})
,.ready_o(out_hop_ready[i])
,.yumi_o (node_yumi_o [i])
// (i==0) ? 0: avoid vcs complaint of negative index.
,.v_o (out_hop_v_m1)
,.data_o (out_hop_data_m1)
,.ready_i((i==0) ? asm_ready_i : out_hop_ready[(i==0) ? 0:i-1])
);
bsg_fsb_murn_gateway #(.width_p(width_p)
,.id_width_p( id_width_p )
,.id_p(i)
,.enabled_at_start_p(enabled_at_start_vec_p[i])
,.snoop_p(snoop_vec_p[i])
) murn_gateway
(.clk_i (clk_i)
,.reset_i (reset_i)
// from gateway
,.v_i (node_v_int)
,.data_i (node_data_o_int)
,.ready_o (node_ready_int)
// to node
// updated valid bit based on enable
// and filtering out switch command packets
,.ready_i (node_ready_i [i])
,.v_o (node_v_o [i])
,.node_en_r_o (node_en_r_int )
,.node_reset_r_o(node_reset_r_o[i])
);
// avoid lint warnings
assign node_data_o[i] = node_data_o_int;
assign node_en_r_o[i] = node_en_r_int;
// synopsys translate_off
always @(negedge node_reset_r_o[i])
begin
$display(" __ _ _");
$display(" / _| | | | | ");
$display(" | |_ ___ | |__ _ __ ___ ___ ___ | |_ ");
$display(" | _| / __| | '_ \\ | '__| / _ \\ / __| / _ \\ | __|");
$display(" | | \\__ \\ | |_) | | | | __/ \\__ \\ | __/ | |_ ");
$display(" |_| |___/ |_.__/ |_| \\___| |___/ \\___| \\__|");
$display("## reset low on FSB in module %m, node %2d, time = ",i,$stime);
end
always @(posedge node_en_r_o[i])
begin
$display(" __ _ _ _ ");
$display(" / _| | | | | | | ");
$display(" | |_ ___ | |__ ___ _ __ __ _ | |__ | | ___ ");
$display(" | _| / __| | '_ \\ / _ \\ | '_ \\ / _` | | '_ \\ | | / _ \\ ");
$display(" | | \\__ \\ | |_) | | __/ | | | | | (_| | | |_) | | | | __/ ");
$display(" |_| |___/ |_.__/ \\___| |_| |_| \\__,_| |_.__/ |_| \\___| ");
$display("## enable high on FSB in module %m, node %2d, time = ",i, $stime);
end
// synopsys translate_on
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_fsb)
`else
module bsg_fsb #(parameter `BSG_INV_PARAM( width_p )
,parameter `BSG_INV_PARAM(nodes_p )
// bit vector of master nodes
, parameter enabled_at_start_vec_p = (nodes_p) ' (0)
, parameter snoop_vec_p = (nodes_p) ' (0)
)
(input clk_i
, input reset_i
// from assembler
, input asm_v_i
, input [width_p-1:0] asm_data_i
, output asm_yumi_o
// to asm
, output asm_v_o
, output [width_p-1:0] asm_data_o
, input asm_ready_i
// into nodes
, output [nodes_p-1:0] node_v_o
, output [width_p-1:0] node_data_o [nodes_p-1:0]
, input [nodes_p-1:0] node_ready_i
// into nodes (control)
, output [nodes_p-1:0] node_en_r_o
, output [nodes_p-1:0] node_reset_r_o
// unsupported
// , output [nodes_p-1:0] node_powerup_o
// out of nodes
, input [nodes_p-1:0] node_v_i
, input [width_p-1:0] node_data_i [nodes_p-1:0]
, output [nodes_p-1:0] node_yumi_o
);
genvar i;
// index is node this channel goes out of
wire [nodes_p-1:0] in_hop_v;
wire [width_p-1:0] in_hop_data [nodes_p-1:0];
wire [nodes_p-1:0] in_hop_ready;
// index is node this channel goes in to
wire [nodes_p-1:0] out_hop_v;
wire [width_p-1:0] out_hop_data [nodes_p-1:0];
wire [nodes_p-1:0] out_hop_ready;
assign out_hop_v [nodes_p-1] = 1'b0;
assign out_hop_data[nodes_p-1] = { (width_p) {1'b0} };
wire to_asm_ready;
assign asm_yumi_o = to_asm_ready & asm_v_i;
// make sure packets fall off of the end.
assign in_hop_ready[nodes_p-1] = 1'b1;
for (i = 0; i < nodes_p; i++)
begin : fsb_node
wire node_ready_int, node_v_int, node_en_r_int;
wire [width_p-1:0] node_data_o_int;
// m1 = minus 1
wire [width_p-1:0] out_hop_data_m1;
wire in_hop_ready_m1, out_hop_v_m1;
if (i == 0)
begin
assign to_asm_ready = in_hop_ready_m1;
assign asm_v_o = out_hop_v_m1;
assign asm_data_o = out_hop_data_m1;
end
else
begin
assign in_hop_ready[i-1] = in_hop_ready_m1;
assign out_hop_v[i-1] = out_hop_v_m1;
assign out_hop_data[i-1] = out_hop_data_m1;
end
// note: for critical path optimization, these hops
// can be wrapped in an additional loop that
// instantiates multiple of these nodes, each of which
// handles a subset of data bus.
// create a chain of hops going in from assembler
bsg_front_side_bus_hop_in
#(.width_p(width_p)
,. fan_out_p(2)
) hopin
(.clk_i(clk_i)
,.reset_i(reset_i)
// (i==0) ? 0: avoid vcs complaint of negative index.
,.ready_o(in_hop_ready_m1)
,.v_i ((i==0) ? asm_v_i : in_hop_v [(i==0) ? i: i-1])
,.data_i ((i==0) ? asm_data_i : in_hop_data [(i==0) ? i: i-1])
,.v_o ({node_v_int , in_hop_v [i]})
,.data_o ({node_data_o_int , in_hop_data [i]}) // 1=local node, 0 is next node
// note: the node does valid->ready
// but should be located nearby so it's okay
,.ready_i({node_ready_int, in_hop_ready[i]})
);
// create a chain of hops going out to assembler
bsg_front_side_bus_hop_out #(.width_p(width_p)) hopout
(.clk_i(clk_i)
,.reset_i(reset_i)
// we can't transmit data unless the node is enabled
,.v_i ({node_en_r_int & node_v_i [i], out_hop_v [i]})
,.data_i ({node_data_i [i], out_hop_data[i]})
,.ready_o(out_hop_ready[i])
,.yumi_o (node_yumi_o [i])
// (i==0) ? 0: avoid vcs complaint of negative index.
,.v_o (out_hop_v_m1)
,.data_o (out_hop_data_m1)
,.ready_i((i==0) ? asm_ready_i : out_hop_ready[(i==0) ? 0:i-1])
);
bsg_fsb_murn_gateway #(.width_p(width_p)
,.id_p(i)
,.enabled_at_start_p(enabled_at_start_vec_p[i])
,.snoop_p(snoop_vec_p[i])
) murn_gateway
(.clk_i (clk_i)
,.reset_i (reset_i)
// from gateway
,.v_i (node_v_int)
,.data_i (node_data_o_int)
,.ready_o (node_ready_int)
// to node
// updated valid bit based on enable
// and filtering out switch command packets
,.ready_i (node_ready_i [i])
,.v_o (node_v_o [i])
,.node_en_r_o (node_en_r_int )
,.node_reset_r_o(node_reset_r_o[i])
);
// avoid lint warnings
assign node_data_o[i] = node_data_o_int;
assign node_en_r_o[i] = node_en_r_int;
// synopsys translate_off
always @(negedge node_reset_r_o[i])
begin
$display(" __ _ _");
$display(" / _| | | | | ");
$display(" | |_ ___ | |__ _ __ ___ ___ ___ | |_ ");
$display(" | _| / __| | '_ \\ | '__| / _ \\ / __| / _ \\ | __|");
$display(" | | \\__ \\ | |_) | | | | __/ \\__ \\ | __/ | |_ ");
$display(" |_| |___/ |_.__/ |_| \\___| |___/ \\___| \\__|");
$display("## reset low on FSB in module %m, node %2d, time = ",i,$stime);
end
always @(posedge node_en_r_o[i])
begin
$display(" __ _ _ _ ");
$display(" / _| | | | | | | ");
$display(" | |_ ___ | |__ ___ _ __ __ _ | |__ | | ___ ");
$display(" | _| / __| | '_ \\ / _ \\ | '_ \\ / _` | | '_ \\ | | / _ \\ ");
$display(" | | \\__ \\ | |_) | | __/ | | | | | (_| | | |_) | | | | __/ ");
$display(" |_| |___/ |_.__/ \\___| |_| |_| \\__,_| |_.__/ |_| \\___| ");
$display("## enable high on FSB in module %m, node %2d, time = ",i, $stime);
end
// synopsys translate_on
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_fsb)
`endif
|
module HeadFieldExtractor (
input wire[63:0] din_data,
input wire din_last,
output wire din_ready,
input wire din_valid,
output wire[63:0] dout_data,
output wire dout_last,
input wire dout_ready,
output wire dout_valid,
output wire[63:0] headers_data,
output wire headers_last,
input wire headers_ready,
output wire headers_valid
);
assign din_ready = 1'bx;
assign dout_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
assign dout_last = 1'bx;
assign dout_valid = 1'bx;
assign headers_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
assign headers_last = 1'bx;
assign headers_valid = 1'bx;
endmodule
module PatternMatch (
input wire[63:0] din_data,
input wire din_last,
output wire din_ready,
input wire din_valid,
output wire[63:0] match_data,
output wire match_last,
input wire match_ready,
output wire match_valid
);
assign din_ready = 1'bx;
assign match_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
assign match_last = 1'bx;
assign match_valid = 1'bx;
endmodule
module Filter (
input wire[31:0] cfg_ar_addr,
input wire[2:0] cfg_ar_prot,
output wire cfg_ar_ready,
input wire cfg_ar_valid,
input wire[31:0] cfg_aw_addr,
input wire[2:0] cfg_aw_prot,
output wire cfg_aw_ready,
input wire cfg_aw_valid,
input wire cfg_b_ready,
output wire[1:0] cfg_b_resp,
output wire cfg_b_valid,
output wire[63:0] cfg_r_data,
input wire cfg_r_ready,
output wire[1:0] cfg_r_resp,
output wire cfg_r_valid,
input wire[63:0] cfg_w_data,
output wire cfg_w_ready,
input wire[7:0] cfg_w_strb,
input wire cfg_w_valid,
input wire[63:0] din_data,
input wire din_last,
output wire din_ready,
input wire din_valid,
output wire[63:0] dout_data,
output wire dout_last,
input wire dout_ready,
output wire dout_valid,
input wire[63:0] headers_data,
input wire headers_last,
output wire headers_ready,
input wire headers_valid,
input wire[63:0] patternMatch_data,
input wire patternMatch_last,
output wire patternMatch_ready,
input wire patternMatch_valid
);
assign cfg_ar_ready = 1'bx;
assign cfg_aw_ready = 1'bx;
assign cfg_b_resp = 2'bxx;
assign cfg_b_valid = 1'bx;
assign cfg_r_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
assign cfg_r_resp = 2'bxx;
assign cfg_r_valid = 1'bx;
assign cfg_w_ready = 1'bx;
assign din_ready = 1'bx;
assign dout_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
assign dout_last = 1'bx;
assign dout_valid = 1'bx;
assign headers_ready = 1'bx;
assign patternMatch_ready = 1'bx;
endmodule
module Exporter (
input wire[63:0] din_data,
input wire din_last,
output wire din_ready,
input wire din_valid,
output wire[63:0] dout_data,
output wire dout_last,
input wire dout_ready,
output wire dout_valid
);
assign din_ready = 1'bx;
assign dout_data = 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
assign dout_last = 1'bx;
assign dout_valid = 1'bx;
endmodule
//
// Stream duplicator for AxiStream interfaces
//
// :see: :class:`hwtLib.handshaked.splitCopy.HsSplitCopy`
//
// .. hwt-autodoc::
//
module AxiSSplitCopy #(
parameter DATA_WIDTH = 64,
parameter DEST_WIDTH = 0,
parameter ID_WIDTH = 0,
parameter INTF_CLS = "<class 'hwtLib.amba.axis.AxiStream'>",
parameter IS_BIGENDIAN = 0,
parameter OUTPUTS = 2,
parameter USER_WIDTH = 0,
parameter USE_KEEP = 0,
parameter USE_STRB = 0
) (
input wire[63:0] dataIn_data,
input wire dataIn_last,
output reg dataIn_ready,
input wire dataIn_valid,
output wire[63:0] dataOut_0_data,
output wire dataOut_0_last,
input wire dataOut_0_ready,
output reg dataOut_0_valid,
output wire[63:0] dataOut_1_data,
output wire dataOut_1_last,
input wire dataOut_1_ready,
output reg dataOut_1_valid
);
always @(dataOut_0_ready, dataOut_1_ready) begin: assig_process_dataIn_ready
dataIn_ready = dataOut_0_ready & dataOut_1_ready;
end
assign dataOut_0_data = dataIn_data;
assign dataOut_0_last = dataIn_last;
always @(dataIn_valid, dataOut_1_ready) begin: assig_process_dataOut_0_valid
dataOut_0_valid = dataIn_valid & dataOut_1_ready;
end
assign dataOut_1_data = dataIn_data;
assign dataOut_1_last = dataIn_last;
always @(dataIn_valid, dataOut_0_ready) begin: assig_process_dataOut_1_valid
dataOut_1_valid = dataIn_valid & dataOut_0_ready;
end
generate if (DATA_WIDTH != 64)
$error("%m Generated only for this param value");
endgenerate
generate if (DEST_WIDTH != 0)
$error("%m Generated only for this param value");
endgenerate
generate if (ID_WIDTH != 0)
$error("%m Generated only for this param value");
endgenerate
generate if (INTF_CLS != "<class 'hwtLib.amba.axis.AxiStream'>")
$error("%m Generated only for this param value");
endgenerate
generate if (IS_BIGENDIAN != 0)
$error("%m Generated only for this param value");
endgenerate
generate if (OUTPUTS != 2)
$error("%m Generated only for this param value");
endgenerate
generate if (USER_WIDTH != 0)
$error("%m Generated only for this param value");
endgenerate
generate if (USE_KEEP != 0)
$error("%m Generated only for this param value");
endgenerate
generate if (USE_STRB != 0)
$error("%m Generated only for this param value");
endgenerate
endmodule
//
// This unit has actually no functionality it is just example
// of hierarchical design.
//
// .. hwt-autodoc::
//
module NetFilter #(
parameter DATA_WIDTH = 64
) (
input wire[31:0] cfg_ar_addr,
input wire[2:0] cfg_ar_prot,
output wire cfg_ar_ready,
input wire cfg_ar_valid,
input wire[31:0] cfg_aw_addr,
input wire[2:0] cfg_aw_prot,
output wire cfg_aw_ready,
input wire cfg_aw_valid,
input wire cfg_b_ready,
output wire[1:0] cfg_b_resp,
output wire cfg_b_valid,
output wire[63:0] cfg_r_data,
input wire cfg_r_ready,
output wire[1:0] cfg_r_resp,
output wire cfg_r_valid,
input wire[63:0] cfg_w_data,
output wire cfg_w_ready,
input wire[7:0] cfg_w_strb,
input wire cfg_w_valid,
input wire clk,
input wire[63:0] din_data,
input wire din_last,
output wire din_ready,
input wire din_valid,
output wire[63:0] export_data,
output wire export_last,
input wire export_ready,
output wire export_valid,
input wire rst_n
);
wire[63:0] sig_exporter_din_data;
wire sig_exporter_din_last;
wire sig_exporter_din_ready;
wire sig_exporter_din_valid;
wire[63:0] sig_exporter_dout_data;
wire sig_exporter_dout_last;
wire sig_exporter_dout_ready;
wire sig_exporter_dout_valid;
wire[31:0] sig_filter_cfg_ar_addr;
wire[2:0] sig_filter_cfg_ar_prot;
wire sig_filter_cfg_ar_ready;
wire sig_filter_cfg_ar_valid;
wire[31:0] sig_filter_cfg_aw_addr;
wire[2:0] sig_filter_cfg_aw_prot;
wire sig_filter_cfg_aw_ready;
wire sig_filter_cfg_aw_valid;
wire sig_filter_cfg_b_ready;
wire[1:0] sig_filter_cfg_b_resp;
wire sig_filter_cfg_b_valid;
wire[63:0] sig_filter_cfg_r_data;
wire sig_filter_cfg_r_ready;
wire[1:0] sig_filter_cfg_r_resp;
wire sig_filter_cfg_r_valid;
wire[63:0] sig_filter_cfg_w_data;
wire sig_filter_cfg_w_ready;
wire[7:0] sig_filter_cfg_w_strb;
wire sig_filter_cfg_w_valid;
wire[63:0] sig_filter_din_data;
wire sig_filter_din_last;
wire sig_filter_din_ready;
wire sig_filter_din_valid;
wire[63:0] sig_filter_dout_data;
wire sig_filter_dout_last;
wire sig_filter_dout_ready;
wire sig_filter_dout_valid;
wire[63:0] sig_filter_headers_data;
wire sig_filter_headers_last;
wire sig_filter_headers_ready;
wire sig_filter_headers_valid;
wire[63:0] sig_filter_patternMatch_data;
wire sig_filter_patternMatch_last;
wire sig_filter_patternMatch_ready;
wire sig_filter_patternMatch_valid;
wire[63:0] sig_gen_dout_splitCopy_0_dataIn_data;
wire sig_gen_dout_splitCopy_0_dataIn_last;
wire sig_gen_dout_splitCopy_0_dataIn_ready;
wire sig_gen_dout_splitCopy_0_dataIn_valid;
wire[63:0] sig_gen_dout_splitCopy_0_dataOut_0_data;
wire sig_gen_dout_splitCopy_0_dataOut_0_last;
wire sig_gen_dout_splitCopy_0_dataOut_0_ready;
wire sig_gen_dout_splitCopy_0_dataOut_0_valid;
wire[63:0] sig_gen_dout_splitCopy_0_dataOut_1_data;
wire sig_gen_dout_splitCopy_0_dataOut_1_last;
wire sig_gen_dout_splitCopy_0_dataOut_1_ready;
wire sig_gen_dout_splitCopy_0_dataOut_1_valid;
wire[63:0] sig_hfe_din_data;
wire sig_hfe_din_last;
wire sig_hfe_din_ready;
wire sig_hfe_din_valid;
wire[63:0] sig_hfe_dout_data;
wire sig_hfe_dout_last;
wire sig_hfe_dout_ready;
wire sig_hfe_dout_valid;
wire[63:0] sig_hfe_headers_data;
wire sig_hfe_headers_last;
wire sig_hfe_headers_ready;
wire sig_hfe_headers_valid;
wire[63:0] sig_patternMatch_din_data;
wire sig_patternMatch_din_last;
wire sig_patternMatch_din_ready;
wire sig_patternMatch_din_valid;
wire[63:0] sig_patternMatch_match_data;
wire sig_patternMatch_match_last;
wire sig_patternMatch_match_ready;
wire sig_patternMatch_match_valid;
Exporter exporter_inst (
.din_data(sig_exporter_din_data),
.din_last(sig_exporter_din_last),
.din_ready(sig_exporter_din_ready),
.din_valid(sig_exporter_din_valid),
.dout_data(sig_exporter_dout_data),
.dout_last(sig_exporter_dout_last),
.dout_ready(sig_exporter_dout_ready),
.dout_valid(sig_exporter_dout_valid)
);
Filter filter_inst (
.cfg_ar_addr(sig_filter_cfg_ar_addr),
.cfg_ar_prot(sig_filter_cfg_ar_prot),
.cfg_ar_ready(sig_filter_cfg_ar_ready),
.cfg_ar_valid(sig_filter_cfg_ar_valid),
.cfg_aw_addr(sig_filter_cfg_aw_addr),
.cfg_aw_prot(sig_filter_cfg_aw_prot),
.cfg_aw_ready(sig_filter_cfg_aw_ready),
.cfg_aw_valid(sig_filter_cfg_aw_valid),
.cfg_b_ready(sig_filter_cfg_b_ready),
.cfg_b_resp(sig_filter_cfg_b_resp),
.cfg_b_valid(sig_filter_cfg_b_valid),
.cfg_r_data(sig_filter_cfg_r_data),
.cfg_r_ready(sig_filter_cfg_r_ready),
.cfg_r_resp(sig_filter_cfg_r_resp),
.cfg_r_valid(sig_filter_cfg_r_valid),
.cfg_w_data(sig_filter_cfg_w_data),
.cfg_w_ready(sig_filter_cfg_w_ready),
.cfg_w_strb(sig_filter_cfg_w_strb),
.cfg_w_valid(sig_filter_cfg_w_valid),
.din_data(sig_filter_din_data),
.din_last(sig_filter_din_last),
.din_ready(sig_filter_din_ready),
.din_valid(sig_filter_din_valid),
.dout_data(sig_filter_dout_data),
.dout_last(sig_filter_dout_last),
.dout_ready(sig_filter_dout_ready),
.dout_valid(sig_filter_dout_valid),
.headers_data(sig_filter_headers_data),
.headers_last(sig_filter_headers_last),
.headers_ready(sig_filter_headers_ready),
.headers_valid(sig_filter_headers_valid),
.patternMatch_data(sig_filter_patternMatch_data),
.patternMatch_last(sig_filter_patternMatch_last),
.patternMatch_ready(sig_filter_patternMatch_ready),
.patternMatch_valid(sig_filter_patternMatch_valid)
);
AxiSSplitCopy #(
.DATA_WIDTH(64),
.DEST_WIDTH(0),
.ID_WIDTH(0),
.INTF_CLS("<class 'hwtLib.amba.axis.AxiStream'>"),
.IS_BIGENDIAN(0),
.OUTPUTS(2),
.USER_WIDTH(0),
.USE_KEEP(0),
.USE_STRB(0)
) gen_dout_splitCopy_0_inst (
.dataIn_data(sig_gen_dout_splitCopy_0_dataIn_data),
.dataIn_last(sig_gen_dout_splitCopy_0_dataIn_last),
.dataIn_ready(sig_gen_dout_splitCopy_0_dataIn_ready),
.dataIn_valid(sig_gen_dout_splitCopy_0_dataIn_valid),
.dataOut_0_data(sig_gen_dout_splitCopy_0_dataOut_0_data),
.dataOut_0_last(sig_gen_dout_splitCopy_0_dataOut_0_last),
.dataOut_0_ready(sig_gen_dout_splitCopy_0_dataOut_0_ready),
.dataOut_0_valid(sig_gen_dout_splitCopy_0_dataOut_0_valid),
.dataOut_1_data(sig_gen_dout_splitCopy_0_dataOut_1_data),
.dataOut_1_last(sig_gen_dout_splitCopy_0_dataOut_1_last),
.dataOut_1_ready(sig_gen_dout_splitCopy_0_dataOut_1_ready),
.dataOut_1_valid(sig_gen_dout_splitCopy_0_dataOut_1_valid)
);
HeadFieldExtractor hfe_inst (
.din_data(sig_hfe_din_data),
.din_last(sig_hfe_din_last),
.din_ready(sig_hfe_din_ready),
.din_valid(sig_hfe_din_valid),
.dout_data(sig_hfe_dout_data),
.dout_last(sig_hfe_dout_last),
.dout_ready(sig_hfe_dout_ready),
.dout_valid(sig_hfe_dout_valid),
.headers_data(sig_hfe_headers_data),
.headers_last(sig_hfe_headers_last),
.headers_ready(sig_hfe_headers_ready),
.headers_valid(sig_hfe_headers_valid)
);
PatternMatch patternMatch_inst (
.din_data(sig_patternMatch_din_data),
.din_last(sig_patternMatch_din_last),
.din_ready(sig_patternMatch_din_ready),
.din_valid(sig_patternMatch_din_valid),
.match_data(sig_patternMatch_match_data),
.match_last(sig_patternMatch_match_last),
.match_ready(sig_patternMatch_match_ready),
.match_valid(sig_patternMatch_match_valid)
);
assign cfg_ar_ready = sig_filter_cfg_ar_ready;
assign cfg_aw_ready = sig_filter_cfg_aw_ready;
assign cfg_b_resp = sig_filter_cfg_b_resp;
assign cfg_b_valid = sig_filter_cfg_b_valid;
assign cfg_r_data = sig_filter_cfg_r_data;
assign cfg_r_resp = sig_filter_cfg_r_resp;
assign cfg_r_valid = sig_filter_cfg_r_valid;
assign cfg_w_ready = sig_filter_cfg_w_ready;
assign din_ready = sig_hfe_din_ready;
assign export_data = sig_exporter_dout_data;
assign export_last = sig_exporter_dout_last;
assign export_valid = sig_exporter_dout_valid;
assign sig_exporter_din_data = sig_filter_dout_data;
assign sig_exporter_din_last = sig_filter_dout_last;
assign sig_exporter_din_valid = sig_filter_dout_valid;
assign sig_exporter_dout_ready = export_ready;
assign sig_filter_cfg_ar_addr = cfg_ar_addr;
assign sig_filter_cfg_ar_prot = cfg_ar_prot;
assign sig_filter_cfg_ar_valid = cfg_ar_valid;
assign sig_filter_cfg_aw_addr = cfg_aw_addr;
assign sig_filter_cfg_aw_prot = cfg_aw_prot;
assign sig_filter_cfg_aw_valid = cfg_aw_valid;
assign sig_filter_cfg_b_ready = cfg_b_ready;
assign sig_filter_cfg_r_ready = cfg_r_ready;
assign sig_filter_cfg_w_data = cfg_w_data;
assign sig_filter_cfg_w_strb = cfg_w_strb;
assign sig_filter_cfg_w_valid = cfg_w_valid;
assign sig_filter_din_data = sig_gen_dout_splitCopy_0_dataOut_1_data;
assign sig_filter_din_last = sig_gen_dout_splitCopy_0_dataOut_1_last;
assign sig_filter_din_valid = sig_gen_dout_splitCopy_0_dataOut_1_valid;
assign sig_filter_dout_ready = sig_exporter_din_ready;
assign sig_filter_headers_data = sig_hfe_headers_data;
assign sig_filter_headers_last = sig_hfe_headers_last;
assign sig_filter_headers_valid = sig_hfe_headers_valid;
assign sig_filter_patternMatch_data = sig_patternMatch_match_data;
assign sig_filter_patternMatch_last = sig_patternMatch_match_last;
assign sig_filter_patternMatch_valid = sig_patternMatch_match_valid;
assign sig_gen_dout_splitCopy_0_dataIn_data = sig_hfe_dout_data;
assign sig_gen_dout_splitCopy_0_dataIn_last = sig_hfe_dout_last;
assign sig_gen_dout_splitCopy_0_dataIn_valid = sig_hfe_dout_valid;
assign sig_gen_dout_splitCopy_0_dataOut_0_ready = sig_patternMatch_din_ready;
assign sig_gen_dout_splitCopy_0_dataOut_1_ready = sig_filter_din_ready;
assign sig_hfe_din_data = din_data;
assign sig_hfe_din_last = din_last;
assign sig_hfe_din_valid = din_valid;
assign sig_hfe_dout_ready = sig_gen_dout_splitCopy_0_dataIn_ready;
assign sig_hfe_headers_ready = sig_filter_headers_ready;
assign sig_patternMatch_din_data = sig_gen_dout_splitCopy_0_dataOut_0_data;
assign sig_patternMatch_din_last = sig_gen_dout_splitCopy_0_dataOut_0_last;
assign sig_patternMatch_din_valid = sig_gen_dout_splitCopy_0_dataOut_0_valid;
assign sig_patternMatch_match_ready = sig_filter_patternMatch_ready;
generate if (DATA_WIDTH != 64)
$error("%m Generated only for this param value");
endgenerate
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2019 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * MSetRBT : Implementation of MSetInterface via Red-Black trees *)
(** Initial author: Andrew W. Appel, 2011.
Extra modifications by: Pierre Letouzey
The design decisions behind this implementation are described here:
- Efficient Verified Red-Black Trees, by Andrew W. Appel, September 2011.
http://www.cs.princeton.edu/~appel/papers/redblack.pdf
Additional suggested reading:
- Red-Black Trees in a Functional Setting by Chris Okasaki.
Journal of Functional Programming, 9(4):471-477, July 1999.
http://www.eecs.usma.edu/webs/people/okasaki/jfp99redblack.pdf
- Red-black trees with types, by Stefan Kahrs.
Journal of Functional Programming, 11(4), 425-432, 2001.
- Functors for Proofs and Programs, by J.-C. Filliatre and P. Letouzey.
ESOP'04: European Symposium on Programming, pp. 370-384, 2004.
http://www.lri.fr/~filliatr/ftp/publis/fpp.ps.gz
*)
Require MSetGenTree.
Require Import Bool List BinPos Pnat Setoid SetoidList PeanoNat.
Local Open Scope list_scope.
(* For nicer extraction, we create induction principles
only when needed *)
Local Unset Elimination Schemes.
(** An extra function not (yet?) in MSetInterface.S *)
Module Type MSetRemoveMin (Import M:MSetInterface.S).
Parameter remove_min : t -> option (elt * t).
Axiom remove_min_spec1 : forall s k s',
remove_min s = Some (k,s') ->
min_elt s = Some k /\ remove k s [=] s'.
Axiom remove_min_spec2 : forall s, remove_min s = None -> Empty s.
End MSetRemoveMin.
(** The type of color annotation. *)
Inductive color := Red | Black.
Module Color.
Definition t := color.
End Color.
(** * Ops : the pure functions *)
Module Ops (X:Orders.OrderedType) <: MSetInterface.Ops X.
(** ** Generic trees instantiated with color *)
(** We reuse a generic definition of trees where the information
parameter is a color. Functions like mem or fold are also
provided by this generic functor. *)
Include MSetGenTree.Ops X Color.
Definition t := tree.
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
(** ** Basic tree *)
Definition singleton (k: elt) : tree := Bk Leaf k Leaf.
(** ** Changing root color *)
Definition makeBlack t :=
match t with
| Leaf => Leaf
| Node _ a x b => Bk a x b
end.
Definition makeRed t :=
match t with
| Leaf => Leaf
| Node _ a x b => Rd a x b
end.
(** ** Balancing *)
(** We adapt when one side is not a true red-black tree.
Both sides have the same black depth. *)
Definition lbal l k r :=
match l with
| Rd (Rd a x b) y c => Rd (Bk a x b) y (Bk c k r)
| Rd a x (Rd b y c) => Rd (Bk a x b) y (Bk c k r)
| _ => Bk l k r
end.
Definition rbal l k r :=
match r with
| Rd (Rd b y c) z d => Rd (Bk l k b) y (Bk c z d)
| Rd b y (Rd c z d) => Rd (Bk l k b) y (Bk c z d)
| _ => Bk l k r
end.
(** A variant of [rbal], with reverse pattern order.
Is it really useful ? Should we always use it ? *)
Definition rbal' l k r :=
match r with
| Rd b y (Rd c z d) => Rd (Bk l k b) y (Bk c z d)
| Rd (Rd b y c) z d => Rd (Bk l k b) y (Bk c z d)
| _ => Bk l k r
end.
(** Balancing with different black depth.
One side is almost a red-black tree, while the other is
a true red-black tree, but with black depth + 1.
Used in deletion. *)
Definition lbalS l k r :=
match l with
| Rd a x b => Rd (Bk a x b) k r
| _ =>
match r with
| Bk a y b => rbal' l k (Rd a y b)
| Rd (Bk a y b) z c => Rd (Bk l k a) y (rbal' b z (makeRed c))
| _ => Rd l k r (* impossible *)
end
end.
Definition rbalS l k r :=
match r with
| Rd b y c => Rd l k (Bk b y c)
| _ =>
match l with
| Bk a x b => lbal (Rd a x b) k r
| Rd a x (Bk b y c) => Rd (lbal (makeRed a) x b) y (Bk c k r)
| _ => Rd l k r (* impossible *)
end
end.
(** ** Insertion *)
Fixpoint ins x s :=
match s with
| Leaf => Rd Leaf x Leaf
| Node c l y r =>
match X.compare x y with
| Eq => s
| Lt =>
match c with
| Red => Rd (ins x l) y r
| Black => lbal (ins x l) y r
end
| Gt =>
match c with
| Red => Rd l y (ins x r)
| Black => rbal l y (ins x r)
end
end
end.
Definition add x s := makeBlack (ins x s).
(** ** Deletion *)
Fixpoint append (l:tree) : tree -> tree :=
match l with
| Leaf => fun r => r
| Node lc ll lx lr =>
fix append_l (r:tree) : tree :=
match r with
| Leaf => l
| Node rc rl rx rr =>
match lc, rc with
| Red, Red =>
let lrl := append lr rl in
match lrl with
| Rd lr' x rl' => Rd (Rd ll lx lr') x (Rd rl' rx rr)
| _ => Rd ll lx (Rd lrl rx rr)
end
| Black, Black =>
let lrl := append lr rl in
match lrl with
| Rd lr' x rl' => Rd (Bk ll lx lr') x (Bk rl' rx rr)
| _ => lbalS ll lx (Bk lrl rx rr)
end
| Black, Red => Rd (append_l rl) rx rr
| Red, Black => Rd ll lx (append lr r)
end
end
end.
Fixpoint del x t :=
match t with
| Leaf => Leaf
| Node _ a y b =>
match X.compare x y with
| Eq => append a b
| Lt =>
match a with
| Bk _ _ _ => lbalS (del x a) y b
| _ => Rd (del x a) y b
end
| Gt =>
match b with
| Bk _ _ _ => rbalS a y (del x b)
| _ => Rd a y (del x b)
end
end
end.
Definition remove x t := makeBlack (del x t).
(** ** Removing minimal element *)
Fixpoint delmin l x r : (elt * tree) :=
match l with
| Leaf => (x,r)
| Node lc ll lx lr =>
let (k,l') := delmin ll lx lr in
match lc with
| Black => (k, lbalS l' x r)
| Red => (k, Rd l' x r)
end
end.
Definition remove_min t : option (elt * tree) :=
match t with
| Leaf => None
| Node _ l x r =>
let (k,t) := delmin l x r in
Some (k, makeBlack t)
end.
(** ** Tree-ification
We rebuild a tree of size [if pred then n-1 else n] as soon
as the list [l] has enough elements *)
Definition bogus : tree * list elt := (Leaf, nil).
Notation treeify_t := (list elt -> tree * list elt).
Definition treeify_zero : treeify_t :=
fun acc => (Leaf,acc).
Definition treeify_one : treeify_t :=
fun acc => match acc with
| x::acc => (Rd Leaf x Leaf, acc)
| _ => bogus
end.
Definition treeify_cont (f g : treeify_t) : treeify_t :=
fun acc =>
match f acc with
| (l, x::acc) =>
match g acc with
| (r, acc) => (Bk l x r, acc)
end
| _ => bogus
end.
Fixpoint treeify_aux (pred:bool)(n: positive) : treeify_t :=
match n with
| xH => if pred then treeify_zero else treeify_one
| xO n => treeify_cont (treeify_aux pred n) (treeify_aux true n)
| xI n => treeify_cont (treeify_aux false n) (treeify_aux pred n)
end.
Fixpoint plength_aux (l:list elt)(p:positive) := match l with
| nil => p
| _::l => plength_aux l (Pos.succ p)
end.
Definition plength l := plength_aux l 1.
Definition treeify (l:list elt) :=
fst (treeify_aux true (plength l) l).
(** ** Filtering *)
Fixpoint filter_aux (f: elt -> bool) s acc :=
match s with
| Leaf => acc
| Node _ l k r =>
let acc := filter_aux f r acc in
if f k then filter_aux f l (k::acc)
else filter_aux f l acc
end.
Definition filter (f: elt -> bool) (s: t) : t :=
treeify (filter_aux f s nil).
Fixpoint partition_aux (f: elt -> bool) s acc1 acc2 :=
match s with
| Leaf => (acc1,acc2)
| Node _ sl k sr =>
let (acc1, acc2) := partition_aux f sr acc1 acc2 in
if f k then partition_aux f sl (k::acc1) acc2
else partition_aux f sl acc1 (k::acc2)
end.
Definition partition (f: elt -> bool) (s:t) : t*t :=
let (ok,ko) := partition_aux f s nil nil in
(treeify ok, treeify ko).
(** ** Union, intersection, difference *)
(** union of the elements of [l1] and [l2] into a third [acc] list. *)
Fixpoint union_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => @rev_append _
| x::l1' =>
fix union_l1 l2 acc :=
match l2 with
| nil => rev_append l1 acc
| y::l2' =>
match X.compare x y with
| Eq => union_list l1' l2' (x::acc)
| Lt => union_l1 l2' (y::acc)
| Gt => union_list l1' l2 (x::acc)
end
end
end.
Definition linear_union s1 s2 :=
treeify (union_list (rev_elements s1) (rev_elements s2) nil).
Fixpoint inter_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => fun _ acc => acc
| x::l1' =>
fix inter_l1 l2 acc :=
match l2 with
| nil => acc
| y::l2' =>
match X.compare x y with
| Eq => inter_list l1' l2' (x::acc)
| Lt => inter_l1 l2' acc
| Gt => inter_list l1' l2 acc
end
end
end.
Definition linear_inter s1 s2 :=
treeify (inter_list (rev_elements s1) (rev_elements s2) nil).
Fixpoint diff_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => fun _ acc => acc
| x::l1' =>
fix diff_l1 l2 acc :=
match l2 with
| nil => rev_append l1 acc
| y::l2' =>
match X.compare x y with
| Eq => diff_list l1' l2' acc
| Lt => diff_l1 l2' acc
| Gt => diff_list l1' l2 (x::acc)
end
end
end.
Definition linear_diff s1 s2 :=
treeify (diff_list (rev_elements s1) (rev_elements s2) nil).
(** [compare_height] returns:
- [Lt] if [height s2] is at least twice [height s1];
- [Gt] if [height s1] is at least twice [height s2];
- [Eq] if heights are approximately equal.
Warning: this is not an equivalence relation! but who cares.... *)
Definition skip_red t :=
match t with
| Rd t' _ _ => t'
| _ => t
end.
Definition skip_black t :=
match skip_red t with
| Bk t' _ _ => t'
| t' => t'
end.
Fixpoint compare_height (s1x s1 s2 s2x: tree) : comparison :=
match skip_red s1x, skip_red s1, skip_red s2, skip_red s2x with
| Node _ s1x' _ _, Node _ s1' _ _, Node _ s2' _ _, Node _ s2x' _ _ =>
compare_height (skip_black s1x') s1' s2' (skip_black s2x')
| _, Leaf, _, Node _ _ _ _ => Lt
| Node _ _ _ _, _, Leaf, _ => Gt
| Node _ s1x' _ _, Node _ s1' _ _, Node _ s2' _ _, Leaf =>
compare_height (skip_black s1x') s1' s2' Leaf
| Leaf, Node _ s1' _ _, Node _ s2' _ _, Node _ s2x' _ _ =>
compare_height Leaf s1' s2' (skip_black s2x')
| _, _, _, _ => Eq
end.
(** When one tree is quite smaller than the other, we simply
adds repeatively all its elements in the big one.
For trees of comparable height, we rather use [linear_union]. *)
Definition union (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => fold add t1 t2
| Gt => fold add t2 t1
| Eq => linear_union t1 t2
end.
Definition diff (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => filter (fun k => negb (mem k t2)) t1
| Gt => fold remove t2 t1
| Eq => linear_diff t1 t2
end.
Definition inter (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => filter (fun k => mem k t2) t1
| Gt => filter (fun k => mem k t1) t2
| Eq => linear_inter t1 t2
end.
End Ops.
(** * MakeRaw : the pure functions and their specifications *)
Module Type MakeRaw (X:Orders.OrderedType) <: MSetInterface.RawSets X.
Include Ops X.
(** Generic definition of binary-search-trees and proofs of
specifications for generic functions such as mem or fold. *)
Include MSetGenTree.Props X Color.
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
Local Hint Immediate MX.eq_sym : core.
Local Hint Unfold In lt_tree gt_tree Ok : core.
Local Hint Constructors InT bst : core.
Local Hint Resolve MX.eq_refl MX.eq_trans MX.lt_trans ok : core.
Local Hint Resolve lt_leaf gt_leaf lt_tree_node gt_tree_node : core.
Local Hint Resolve lt_tree_not_in lt_tree_trans gt_tree_not_in gt_tree_trans : core.
Local Hint Resolve elements_spec2 : core.
(** ** Singleton set *)
Lemma singleton_spec x y : InT y (singleton x) <-> X.eq y x.
Proof.
unfold singleton; intuition_in.
Qed.
Instance singleton_ok x : Ok (singleton x).
Proof.
unfold singleton; auto.
Qed.
(** ** makeBlack, MakeRed *)
Lemma makeBlack_spec s x : InT x (makeBlack s) <-> InT x s.
Proof.
destruct s; simpl; intuition_in.
Qed.
Lemma makeRed_spec s x : InT x (makeRed s) <-> InT x s.
Proof.
destruct s; simpl; intuition_in.
Qed.
Instance makeBlack_ok s `{Ok s} : Ok (makeBlack s).
Proof.
destruct s; simpl; ok.
Qed.
Instance makeRed_ok s `{Ok s} : Ok (makeRed s).
Proof.
destruct s; simpl; ok.
Qed.
(** ** Generic handling for red-matching and red-red-matching *)
Definition isblack t :=
match t with Bk _ _ _ => True | _ => False end.
Definition notblack t :=
match t with Bk _ _ _ => False | _ => True end.
Definition notred t :=
match t with Rd _ _ _ => False | _ => True end.
Definition rcase {A} f g t : A :=
match t with
| Rd a x b => f a x b
| _ => g t
end.
Inductive rspec {A} f g : tree -> A -> Prop :=
| rred a x b : rspec f g (Rd a x b) (f a x b)
| relse t : notred t -> rspec f g t (g t).
Fact rmatch {A} f g t : rspec (A:=A) f g t (rcase f g t).
Proof.
destruct t as [|[|] l x r]; simpl; now constructor.
Qed.
Definition rrcase {A} f g t : A :=
match t with
| Rd (Rd a x b) y c => f a x b y c
| Rd a x (Rd b y c) => f a x b y c
| _ => g t
end.
Notation notredred := (rrcase (fun _ _ _ _ _ => False) (fun _ => True)).
Inductive rrspec {A} f g : tree -> A -> Prop :=
| rrleft a x b y c : rrspec f g (Rd (Rd a x b) y c) (f a x b y c)
| rrright a x b y c : rrspec f g (Rd a x (Rd b y c)) (f a x b y c)
| rrelse t : notredred t -> rrspec f g t (g t).
Fact rrmatch {A} f g t : rrspec (A:=A) f g t (rrcase f g t).
Proof.
destruct t as [|[|] l x r]; simpl; try now constructor.
destruct l as [|[|] ll lx lr], r as [|[|] rl rx rr]; now constructor.
Qed.
Definition rrcase' {A} f g t : A :=
match t with
| Rd a x (Rd b y c) => f a x b y c
| Rd (Rd a x b) y c => f a x b y c
| _ => g t
end.
Fact rrmatch' {A} f g t : rrspec (A:=A) f g t (rrcase' f g t).
Proof.
destruct t as [|[|] l x r]; simpl; try now constructor.
destruct l as [|[|] ll lx lr], r as [|[|] rl rx rr]; now constructor.
Qed.
(** Balancing operations are instances of generic match *)
Fact lbal_match l k r :
rrspec
(fun a x b y c => Rd (Bk a x b) y (Bk c k r))
(fun l => Bk l k r)
l
(lbal l k r).
Proof.
exact (rrmatch _ _ _).
Qed.
Fact rbal_match l k r :
rrspec
(fun a x b y c => Rd (Bk l k a) x (Bk b y c))
(fun r => Bk l k r)
r
(rbal l k r).
Proof.
exact (rrmatch _ _ _).
Qed.
Fact rbal'_match l k r :
rrspec
(fun a x b y c => Rd (Bk l k a) x (Bk b y c))
(fun r => Bk l k r)
r
(rbal' l k r).
Proof.
exact (rrmatch' _ _ _).
Qed.
Fact lbalS_match l x r :
rspec
(fun a y b => Rd (Bk a y b) x r)
(fun l =>
match r with
| Bk a y b => rbal' l x (Rd a y b)
| Rd (Bk a y b) z c => Rd (Bk l x a) y (rbal' b z (makeRed c))
| _ => Rd l x r
end)
l
(lbalS l x r).
Proof.
exact (rmatch _ _ _).
Qed.
Fact rbalS_match l x r :
rspec
(fun a y b => Rd l x (Bk a y b))
(fun r =>
match l with
| Bk a y b => lbal (Rd a y b) x r
| Rd a y (Bk b z c) => Rd (lbal (makeRed a) y b) z (Bk c x r)
| _ => Rd l x r
end)
r
(rbalS l x r).
Proof.
exact (rmatch _ _ _).
Qed.
(** ** Balancing for insertion *)
Lemma lbal_spec l x r y :
InT y (lbal l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case lbal_match; intuition_in.
Qed.
Instance lbal_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (lbal l x r).
Proof.
destruct (lbal_match l x r); ok.
Qed.
Lemma rbal_spec l x r y :
InT y (rbal l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbal_match; intuition_in.
Qed.
Instance rbal_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (rbal l x r).
Proof.
destruct (rbal_match l x r); ok.
Qed.
Lemma rbal'_spec l x r y :
InT y (rbal' l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbal'_match; intuition_in.
Qed.
Instance rbal'_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (rbal' l x r).
Proof.
destruct (rbal'_match l x r); ok.
Qed.
Hint Rewrite In_node_iff In_leaf_iff
makeRed_spec makeBlack_spec lbal_spec rbal_spec rbal'_spec : rb.
Ltac descolor := destruct_all Color.t.
Ltac destree t := destruct t as [|[|] ? ? ?].
Ltac autorew := autorewrite with rb.
Tactic Notation "autorew" "in" ident(H) := autorewrite with rb in H.
(** ** Insertion *)
Lemma ins_spec : forall s x y,
InT y (ins x s) <-> X.eq y x \/ InT y s.
Proof.
induct s x.
- intuition_in.
- intuition_in. setoid_replace y with x; eauto.
- descolor; autorew; rewrite IHl; intuition_in.
- descolor; autorew; rewrite IHr; intuition_in.
Qed.
Hint Rewrite ins_spec : rb.
Instance ins_ok s x `{Ok s} : Ok (ins x s).
Proof.
induct s x; auto; descolor;
(apply lbal_ok || apply rbal_ok || ok); auto;
intros y; autorew; intuition; order.
Qed.
Lemma add_spec' s x y :
InT y (add x s) <-> X.eq y x \/ InT y s.
Proof.
unfold add. now autorew.
Qed.
Hint Rewrite add_spec' : rb.
Lemma add_spec s x y `{Ok s} :
InT y (add x s) <-> X.eq y x \/ InT y s.
Proof.
apply add_spec'.
Qed.
Instance add_ok s x `{Ok s} : Ok (add x s).
Proof.
unfold add; auto_tc.
Qed.
(** ** Balancing for deletion *)
Lemma lbalS_spec l x r y :
InT y (lbalS l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case lbalS_match.
- intros; autorew; intuition_in.
- clear l. intros l _.
destruct r as [|[|] rl rx rr].
* autorew. intuition_in.
* destree rl; autorew; intuition_in.
* autorew. intuition_in.
Qed.
Instance lbalS_ok l x r :
forall `(Ok l, Ok r, lt_tree x l, gt_tree x r), Ok (lbalS l x r).
Proof.
case lbalS_match; intros.
- ok.
- destruct r as [|[|] rl rx rr].
* ok.
* destruct rl as [|[|] rll rlx rlr]; intros; ok.
+ apply rbal'_ok; ok.
intros w; autorew; auto.
+ intros w; autorew.
destruct 1 as [Hw|[Hw|Hw]]; try rewrite Hw; eauto.
* ok. autorew. apply rbal'_ok; ok.
Qed.
Lemma rbalS_spec l x r y :
InT y (rbalS l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbalS_match.
- intros; autorew; intuition_in.
- intros t _.
destruct l as [|[|] ll lx lr].
* autorew. intuition_in.
* destruct lr as [|[|] lrl lrx lrr]; autorew; intuition_in.
* autorew. intuition_in.
Qed.
Instance rbalS_ok l x r :
forall `(Ok l, Ok r, lt_tree x l, gt_tree x r), Ok (rbalS l x r).
Proof.
case rbalS_match; intros.
- ok.
- destruct l as [|[|] ll lx lr].
* ok.
* destruct lr as [|[|] lrl lrx lrr]; intros; ok.
+ apply lbal_ok; ok.
intros w; autorew; auto.
+ intros w; autorew.
destruct 1 as [Hw|[Hw|Hw]]; try rewrite Hw; eauto.
* ok. apply lbal_ok; ok.
Qed.
Hint Rewrite lbalS_spec rbalS_spec : rb.
(** ** Append for deletion *)
Ltac append_tac l r :=
induction l as [| lc ll _ lx lr IHlr];
[intro r; simpl
|induction r as [| rc rl IHrl rx rr _];
[simpl
|destruct lc, rc;
[specialize (IHlr rl); clear IHrl
|simpl;
assert (Hr:notred (Bk rl rx rr)) by (simpl; trivial);
set (r:=Bk rl rx rr) in *; clearbody r; clear IHrl rl rx rr;
specialize (IHlr r)
|change (append _ _) with (Rd (append (Bk ll lx lr) rl) rx rr);
assert (Hl:notred (Bk ll lx lr)) by (simpl; trivial);
set (l:=Bk ll lx lr) in *; clearbody l; clear IHlr ll lx lr
|specialize (IHlr rl); clear IHrl]]].
Fact append_rr_match ll lx lr rl rx rr :
rspec
(fun a x b => Rd (Rd ll lx a) x (Rd b rx rr))
(fun t => Rd ll lx (Rd t rx rr))
(append lr rl)
(append (Rd ll lx lr) (Rd rl rx rr)).
Proof.
exact (rmatch _ _ _).
Qed.
Fact append_bb_match ll lx lr rl rx rr :
rspec
(fun a x b => Rd (Bk ll lx a) x (Bk b rx rr))
(fun t => lbalS ll lx (Bk t rx rr))
(append lr rl)
(append (Bk ll lx lr) (Bk rl rx rr)).
Proof.
exact (rmatch _ _ _).
Qed.
Lemma append_spec l r x :
InT x (append l r) <-> InT x l \/ InT x r.
Proof.
revert r.
append_tac l r; autorew; try tauto.
- (* Red / Red *)
revert IHlr; case append_rr_match;
[intros a y b | intros t Ht]; autorew; tauto.
- (* Black / Black *)
revert IHlr; case append_bb_match;
[intros a y b | intros t Ht]; autorew; tauto.
Qed.
Hint Rewrite append_spec : rb.
Lemma append_ok : forall x l r `{Ok l, Ok r},
lt_tree x l -> gt_tree x r -> Ok (append l r).
Proof.
append_tac l r.
- (* Leaf / _ *)
trivial.
- (* _ / Leaf *)
trivial.
- (* Red / Red *)
intros; inv.
assert (IH : Ok (append lr rl)) by (apply IHlr; eauto). clear IHlr.
assert (X.lt lx rx) by (transitivity x; eauto).
assert (G : gt_tree lx (append lr rl)).
{ intros w. autorew. destruct 1; [|transitivity x]; eauto. }
assert (L : lt_tree rx (append lr rl)).
{ intros w. autorew. destruct 1; [transitivity x|]; eauto. }
revert IH G L; case append_rr_match; intros; ok.
- (* Red / Black *)
intros; ok.
intros w; autorew; destruct 1; eauto.
- (* Black / Red *)
intros; ok.
intros w; autorew; destruct 1; eauto.
- (* Black / Black *)
intros; inv.
assert (IH : Ok (append lr rl)) by (apply IHlr; eauto). clear IHlr.
assert (X.lt lx rx) by (transitivity x; eauto).
assert (G : gt_tree lx (append lr rl)).
{ intros w. autorew. destruct 1; [|transitivity x]; eauto. }
assert (L : lt_tree rx (append lr rl)).
{ intros w. autorew. destruct 1; [transitivity x|]; eauto. }
revert IH G L; case append_bb_match; intros; ok.
apply lbalS_ok; ok.
Qed.
(** ** Deletion *)
Lemma del_spec : forall s x y `{Ok s},
InT y (del x s) <-> InT y s /\ ~X.eq y x.
Proof.
induct s x.
- intuition_in.
- autorew; intuition_in.
assert (X.lt y x') by eauto. order.
assert (X.lt x' y) by eauto. order.
order.
- destruct l as [|[|] ll lx lr]; autorew;
rewrite ?IHl by trivial; intuition_in; order.
- destruct r as [|[|] rl rx rr]; autorew;
rewrite ?IHr by trivial; intuition_in; order.
Qed.
Hint Rewrite del_spec : rb.
Instance del_ok s x `{Ok s} : Ok (del x s).
Proof.
induct s x.
- trivial.
- eapply append_ok; eauto.
- assert (lt_tree x' (del x l)).
{ intro w. autorew; trivial. destruct 1. eauto. }
destruct l as [|[|] ll lx lr]; auto_tc.
- assert (gt_tree x' (del x r)).
{ intro w. autorew; trivial. destruct 1. eauto. }
destruct r as [|[|] rl rx rr]; auto_tc.
Qed.
Lemma remove_spec s x y `{Ok s} :
InT y (remove x s) <-> InT y s /\ ~X.eq y x.
Proof.
unfold remove. now autorew.
Qed.
Hint Rewrite remove_spec : rb.
Instance remove_ok s x `{Ok s} : Ok (remove x s).
Proof.
unfold remove; auto_tc.
Qed.
(** ** Removing the minimal element *)
Lemma delmin_spec l y r c x s' `{O : Ok (Node c l y r)} :
delmin l y r = (x,s') ->
min_elt (Node c l y r) = Some x /\ del x (Node c l y r) = s'.
Proof.
revert y r c x s' O.
induction l as [|lc ll IH ly lr _].
- simpl. intros y r _ x s' _. injection 1; intros; subst.
now rewrite MX.compare_refl.
- intros y r c x s' O.
simpl delmin.
specialize (IH ly lr). destruct delmin as (x0,s0).
destruct (IH lc x0 s0); clear IH; [ok|trivial|].
remember (Node lc ll ly lr) as l.
simpl min_elt in *.
intros E.
replace x0 with x in * by (destruct lc; now injection E).
split.
* subst l; intuition.
* assert (X.lt x y).
{ inversion_clear O.
assert (InT x l) by now apply min_elt_spec1. auto. }
simpl. case X.compare_spec; try order.
destruct lc; injection E; subst l s0; auto.
Qed.
Lemma remove_min_spec1 s x s' `{Ok s}:
remove_min s = Some (x,s') ->
min_elt s = Some x /\ remove x s = s'.
Proof.
unfold remove_min.
destruct s as [|c l y r]; try easy.
generalize (delmin_spec l y r c).
destruct delmin as (x0,s0). intros D.
destruct (D x0 s0) as (->,<-); auto.
fold (remove x0 (Node c l y r)).
inversion_clear 1; auto.
Qed.
Lemma remove_min_spec2 s : remove_min s = None -> Empty s.
Proof.
unfold remove_min.
destruct s as [|c l y r].
- easy.
- now destruct delmin.
Qed.
Lemma remove_min_ok (s:t) `{Ok s}:
match remove_min s with
| Some (_,s') => Ok s'
| None => True
end.
Proof.
generalize (remove_min_spec1 s).
destruct remove_min as [(x0,s0)|]; auto.
intros R. destruct (R x0 s0); auto. subst s0. auto_tc.
Qed.
(** ** Treeify *)
Notation ifpred p n := (if p then pred n else n%nat).
Definition treeify_invariant size (f:treeify_t) :=
forall acc,
size <= length acc ->
let (t,acc') := f acc in
cardinal t = size /\ acc = elements t ++ acc'.
Lemma treeify_zero_spec : treeify_invariant 0 treeify_zero.
Proof.
intro. simpl. auto.
Qed.
Lemma treeify_one_spec : treeify_invariant 1 treeify_one.
Proof.
intros [|x acc]; simpl; auto; inversion 1.
Qed.
Lemma treeify_cont_spec f g size1 size2 size :
treeify_invariant size1 f ->
treeify_invariant size2 g ->
size = S (size1 + size2) ->
treeify_invariant size (treeify_cont f g).
Proof.
intros Hf Hg EQ acc LE. unfold treeify_cont.
specialize (Hf acc).
destruct (f acc) as (t1,acc1).
destruct Hf as (Hf1,Hf2).
{ transitivity size; trivial. subst. auto with arith. }
destruct acc1 as [|x acc1].
{ exfalso. revert LE. apply Nat.lt_nge. subst.
rewrite app_nil_r, <- elements_cardinal; auto with arith. }
specialize (Hg acc1).
destruct (g acc1) as (t2,acc2).
destruct Hg as (Hg1,Hg2).
{ revert LE. subst.
rewrite app_length, <- elements_cardinal. simpl.
rewrite Nat.add_succ_r, <- Nat.succ_le_mono.
apply Nat.add_le_mono_l. }
rewrite elements_node, app_ass. now subst.
Qed.
Lemma treeify_aux_spec n (p:bool) :
treeify_invariant (ifpred p (Pos.to_nat n)) (treeify_aux p n).
Proof.
revert p.
induction n as [n|n|]; intros p; simpl treeify_aux.
- eapply treeify_cont_spec; [ apply (IHn false) | apply (IHn p) | ].
rewrite Pos2Nat.inj_xI.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
destruct p; simpl; intros; rewrite Nat.add_0_r; trivial.
now rewrite <- Nat.add_succ_r, Nat.succ_pred; trivial.
- eapply treeify_cont_spec; [ apply (IHn p) | apply (IHn true) | ].
rewrite Pos2Nat.inj_xO.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
rewrite <- Nat.add_succ_r, Nat.succ_pred by trivial.
destruct p; simpl; intros; rewrite Nat.add_0_r; trivial.
symmetry. now apply Nat.add_pred_l.
- destruct p; [ apply treeify_zero_spec | apply treeify_one_spec ].
Qed.
Lemma plength_aux_spec l p :
Pos.to_nat (plength_aux l p) = length l + Pos.to_nat p.
Proof.
revert p. induction l; trivial. simpl plength_aux.
intros. now rewrite IHl, Pos2Nat.inj_succ, Nat.add_succ_r.
Qed.
Lemma plength_spec l : Pos.to_nat (plength l) = S (length l).
Proof.
unfold plength. rewrite plength_aux_spec. apply Nat.add_1_r.
Qed.
Lemma treeify_elements l : elements (treeify l) = l.
Proof.
assert (H := treeify_aux_spec (plength l) true l).
unfold treeify. destruct treeify_aux as (t,acc); simpl in *.
destruct H as (H,H'). { now rewrite plength_spec. }
subst l. rewrite plength_spec, app_length, <- elements_cardinal in *.
destruct acc.
* now rewrite app_nil_r.
* exfalso. revert H. simpl.
rewrite Nat.add_succ_r, Nat.add_comm.
apply Nat.succ_add_discr.
Qed.
Lemma treeify_spec x l : InT x (treeify l) <-> InA X.eq x l.
Proof.
intros. now rewrite <- elements_spec1, treeify_elements.
Qed.
Lemma treeify_ok l : sort X.lt l -> Ok (treeify l).
Proof.
intros. apply elements_sort_ok. rewrite treeify_elements; auto.
Qed.
(** ** Filter *)
#[deprecated(since="8.11",note="Lemma filter_app has been moved to module List.")]
Notation filter_app := List.filter_app.
Lemma filter_aux_elements s f acc :
filter_aux f s acc = List.filter f (elements s) ++ acc.
Proof.
revert acc.
induction s as [|c l IHl x r IHr]; trivial.
intros acc.
rewrite elements_node, List.filter_app. simpl.
destruct (f x); now rewrite IHl, IHr, app_ass.
Qed.
Lemma filter_elements s f :
elements (filter f s) = List.filter f (elements s).
Proof.
unfold filter.
now rewrite treeify_elements, filter_aux_elements, app_nil_r.
Qed.
Lemma filter_spec s x f :
Proper (X.eq==>Logic.eq) f ->
(InT x (filter f s) <-> InT x s /\ f x = true).
Proof.
intros Hf.
rewrite <- elements_spec1, filter_elements, filter_InA, elements_spec1;
now auto_tc.
Qed.
Instance filter_ok s f `(Ok s) : Ok (filter f s).
Proof.
apply elements_sort_ok.
rewrite filter_elements.
apply filter_sort with X.eq; auto_tc.
Qed.
(** ** Partition *)
Lemma partition_aux_spec s f acc1 acc2 :
partition_aux f s acc1 acc2 =
(filter_aux f s acc1, filter_aux (fun x => negb (f x)) s acc2).
Proof.
revert acc1 acc2.
induction s as [ | c l Hl x r Hr ]; simpl.
- trivial.
- intros acc1 acc2.
destruct (f x); simpl; now rewrite Hr, Hl.
Qed.
Lemma partition_spec s f :
partition f s = (filter f s, filter (fun x => negb (f x)) s).
Proof.
unfold partition, filter. now rewrite partition_aux_spec.
Qed.
Lemma partition_spec1 s f :
Proper (X.eq==>Logic.eq) f ->
Equal (fst (partition f s)) (filter f s).
Proof. now rewrite partition_spec. Qed.
Lemma partition_spec2 s f :
Proper (X.eq==>Logic.eq) f ->
Equal (snd (partition f s)) (filter (fun x => negb (f x)) s).
Proof. now rewrite partition_spec. Qed.
Instance partition_ok1 s f `(Ok s) : Ok (fst (partition f s)).
Proof. rewrite partition_spec; now apply filter_ok. Qed.
Instance partition_ok2 s f `(Ok s) : Ok (snd (partition f s)).
Proof. rewrite partition_spec; now apply filter_ok. Qed.
(** ** An invariant for binary list functions with accumulator. *)
Ltac inA :=
rewrite ?InA_app_iff, ?InA_cons, ?InA_nil, ?InA_rev in *; auto_tc.
Record INV l1 l2 acc : Prop := {
l1_sorted : sort X.lt (rev l1);
l2_sorted : sort X.lt (rev l2);
acc_sorted : sort X.lt acc;
l1_lt_acc x y : InA X.eq x l1 -> InA X.eq y acc -> X.lt x y;
l2_lt_acc x y : InA X.eq x l2 -> InA X.eq y acc -> X.lt x y}.
Local Hint Resolve l1_sorted l2_sorted acc_sorted : core.
Lemma INV_init s1 s2 `(Ok s1, Ok s2) :
INV (rev_elements s1) (rev_elements s2) nil.
Proof.
rewrite !rev_elements_rev.
split; rewrite ?rev_involutive; auto; intros; now inA.
Qed.
Lemma INV_sym l1 l2 acc : INV l1 l2 acc -> INV l2 l1 acc.
Proof.
destruct 1; now split.
Qed.
Lemma INV_drop x1 l1 l2 acc :
INV (x1 :: l1) l2 acc -> INV l1 l2 acc.
Proof.
intros (l1s,l2s,accs,l1a,l2a). simpl in *.
destruct (sorted_app_inv _ _ l1s) as (U & V & W); auto.
split; auto.
Qed.
Lemma INV_eq x1 x2 l1 l2 acc :
INV (x1 :: l1) (x2 :: l2) acc -> X.eq x1 x2 ->
INV l1 l2 (x1 :: acc).
Proof.
intros (U,V,W,X,Y) EQ. simpl in *.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
split; auto.
- constructor; auto. apply InA_InfA with X.eq; auto_tc.
- intros x y; inA; intros Hx [Hy|Hy].
+ apply U3; inA.
+ apply X; inA.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy, EQ; apply V3; inA.
+ apply Y; inA.
Qed.
Lemma INV_lt x1 x2 l1 l2 acc :
INV (x1 :: l1) (x2 :: l2) acc -> X.lt x1 x2 ->
INV (x1 :: l1) l2 (x2 :: acc).
Proof.
intros (U,V,W,X,Y) EQ. simpl in *.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
split; auto.
- constructor; auto. apply InA_InfA with X.eq; auto_tc.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy; clear Hy. destruct Hx; [order|].
transitivity x1; auto. apply U3; inA.
+ apply X; inA.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy. apply V3; inA.
+ apply Y; inA.
Qed.
Lemma INV_rev l1 l2 acc :
INV l1 l2 acc -> Sorted X.lt (rev_append l1 acc).
Proof.
intros. rewrite rev_append_rev.
apply SortA_app with X.eq; eauto with *.
intros x y. inA. eapply @l1_lt_acc; eauto.
Qed.
(** ** union *)
Lemma union_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (union_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1];
[intro l2|induction l2 as [|x2 l2 IH2]];
intros acc inv.
- eapply INV_rev, INV_sym; eauto.
- eapply INV_rev; eauto.
- simpl. case X.compare_spec; intro C.
* apply IH1. eapply INV_eq; eauto.
* apply (IH2 (x2::acc)). eapply INV_lt; eauto.
* apply IH1. eapply INV_sym, INV_lt; eauto. now apply INV_sym.
Qed.
Instance linear_union_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_union s1 s2).
Proof.
unfold linear_union. now apply treeify_ok, union_list_ok, INV_init.
Qed.
Instance fold_add_ok s1 s2 `(Ok s1, Ok s2) :
Ok (fold add s1 s2).
Proof.
rewrite fold_spec, <- fold_left_rev_right.
unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance union_ok s1 s2 `(Ok s1, Ok s2) : Ok (union s1 s2).
Proof.
unfold union. destruct compare_height; auto_tc.
Qed.
Lemma union_list_spec x l1 l2 acc :
InA X.eq x (union_list l1 l2 acc) <->
InA X.eq x l1 \/ InA X.eq x l2 \/ InA X.eq x acc.
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. rewrite rev_append_rev. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc; simpl.
* rewrite rev_append_rev. inA. tauto.
* case X.compare_spec; intro C.
+ rewrite IH1, !InA_cons, C; tauto.
+ rewrite (IH2 (x2::acc)), !InA_cons. tauto.
+ rewrite IH1, !InA_cons; tauto.
Qed.
Lemma linear_union_spec s1 s2 x :
InT x (linear_union s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
unfold linear_union.
rewrite treeify_spec, union_list_spec, !rev_elements_rev.
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc.
tauto.
Qed.
Lemma fold_add_spec s1 s2 x :
InT x (fold add s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
rewrite fold_spec, <- fold_left_rev_right.
rewrite <- (elements_spec1 s1), <- InA_rev by auto_tc.
unfold elt in *.
induction (rev (elements s1)); simpl.
- rewrite InA_nil. tauto.
- unfold flip. rewrite add_spec', IHl, InA_cons. tauto.
Qed.
Lemma union_spec' s1 s2 x :
InT x (union s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
unfold union. destruct compare_height.
- apply linear_union_spec.
- apply fold_add_spec.
- rewrite fold_add_spec. tauto.
Qed.
Lemma union_spec : forall s1 s2 y `{Ok s1, Ok s2},
(InT y (union s1 s2) <-> InT y s1 \/ InT y s2).
Proof.
intros; apply union_spec'.
Qed.
(** ** inter *)
Lemma inter_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (inter_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1]; [|induction l2 as [|x2 l2 IH2]]; simpl.
- eauto.
- eauto.
- intros acc inv.
case X.compare_spec; intro C.
* apply IH1. eapply INV_eq; eauto.
* apply (IH2 acc). eapply INV_sym, INV_drop, INV_sym; eauto.
* apply IH1. eapply INV_drop; eauto.
Qed.
Instance linear_inter_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_inter s1 s2).
Proof.
unfold linear_inter. now apply treeify_ok, inter_list_ok, INV_init.
Qed.
Instance inter_ok s1 s2 `(Ok s1, Ok s2) : Ok (inter s1 s2).
Proof.
unfold inter. destruct compare_height; auto_tc.
Qed.
Lemma inter_list_spec x l1 l2 acc :
sort X.lt (rev l1) ->
sort X.lt (rev l2) ->
(InA X.eq x (inter_list l1 l2 acc) <->
(InA X.eq x l1 /\ InA X.eq x l2) \/ InA X.eq x acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc.
* simpl. inA. tauto.
* simpl. intros U V.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
case X.compare_spec; intro C.
+ rewrite IH1, !InA_cons, C; tauto.
+ rewrite (IH2 acc); auto. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite IH1; auto. inA. intuition; try order.
assert (X.lt x x2) by (apply V3; inA). order.
Qed.
Lemma linear_inter_spec s1 s2 x `(Ok s1, Ok s2) :
InT x (linear_inter s1 s2) <-> InT x s1 /\ InT x s2.
Proof.
unfold linear_inter.
rewrite !rev_elements_rev, treeify_spec, inter_list_spec
by (rewrite rev_involutive; auto_tc).
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc. tauto.
Qed.
Local Instance mem_proper s `(Ok s) :
Proper (X.eq ==> Logic.eq) (fun k => mem k s).
Proof.
intros x y EQ. apply Bool.eq_iff_eq_true; rewrite !mem_spec; auto.
now rewrite EQ.
Qed.
Lemma inter_spec s1 s2 y `{Ok s1, Ok s2} :
InT y (inter s1 s2) <-> InT y s1 /\ InT y s2.
Proof.
unfold inter. destruct compare_height.
- now apply linear_inter_spec.
- rewrite filter_spec, mem_spec by auto_tc; tauto.
- rewrite filter_spec, mem_spec by auto_tc; tauto.
Qed.
(** ** difference *)
Lemma diff_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (diff_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1];
[intro l2|induction l2 as [|x2 l2 IH2]];
intros acc inv.
- eauto.
- unfold diff_list. eapply INV_rev; eauto.
- simpl. case X.compare_spec; intro C.
* apply IH1. eapply INV_drop, INV_sym, INV_drop, INV_sym; eauto.
* apply (IH2 acc). eapply INV_sym, INV_drop, INV_sym; eauto.
* apply IH1. eapply INV_sym, INV_lt; eauto. now apply INV_sym.
Qed.
Instance diff_inter_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_diff s1 s2).
Proof.
unfold linear_inter. now apply treeify_ok, diff_list_ok, INV_init.
Qed.
Instance fold_remove_ok s1 s2 `(Ok s2) :
Ok (fold remove s1 s2).
Proof.
rewrite fold_spec, <- fold_left_rev_right.
unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance diff_ok s1 s2 `(Ok s1, Ok s2) : Ok (diff s1 s2).
Proof.
unfold diff. destruct compare_height; auto_tc.
Qed.
Lemma diff_list_spec x l1 l2 acc :
sort X.lt (rev l1) ->
sort X.lt (rev l2) ->
(InA X.eq x (diff_list l1 l2 acc) <->
(InA X.eq x l1 /\ ~InA X.eq x l2) \/ InA X.eq x acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc.
* intros; simpl. rewrite rev_append_rev. inA. tauto.
* simpl. intros U V.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
case X.compare_spec; intro C.
+ rewrite IH1; auto. f_equiv. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite (IH2 acc); auto. f_equiv. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite IH1; auto. inA. intuition; try order.
left; split; auto. destruct 1. order.
assert (X.lt x x2) by (apply V3; inA). order.
Qed.
Lemma linear_diff_spec s1 s2 x `(Ok s1, Ok s2) :
InT x (linear_diff s1 s2) <-> InT x s1 /\ ~InT x s2.
Proof.
unfold linear_diff.
rewrite !rev_elements_rev, treeify_spec, diff_list_spec
by (rewrite rev_involutive; auto_tc).
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc. tauto.
Qed.
Lemma fold_remove_spec s1 s2 x `(Ok s2) :
InT x (fold remove s1 s2) <-> InT x s2 /\ ~InT x s1.
Proof.
rewrite fold_spec, <- fold_left_rev_right.
rewrite <- (elements_spec1 s1), <- InA_rev by auto_tc.
unfold elt in *.
induction (rev (elements s1)); simpl; intros.
- rewrite InA_nil. intuition.
- unfold flip in *. rewrite remove_spec, IHl, InA_cons. tauto.
clear IHl. induction l; simpl; auto_tc.
Qed.
Lemma diff_spec s1 s2 y `{Ok s1, Ok s2} :
InT y (diff s1 s2) <-> InT y s1 /\ ~InT y s2.
Proof.
unfold diff. destruct compare_height.
- now apply linear_diff_spec.
- rewrite filter_spec, Bool.negb_true_iff,
<- Bool.not_true_iff_false, mem_spec;
intuition.
intros x1 x2 EQ. f_equal. now apply mem_proper.
- now apply fold_remove_spec.
Qed.
End MakeRaw.
(** * Balancing properties
We now prove that all operations preserve a red-black invariant,
and that trees have hence a logarithmic depth.
*)
Module BalanceProps(X:Orders.OrderedType)(Import M : MakeRaw X).
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
Import M.MX.
(** ** Red-Black invariants *)
(** In a red-black tree :
- a red node has no red children
- the black depth at each node is the same along all paths.
The black depth is here an argument of the predicate. *)
Inductive rbt : nat -> tree -> Prop :=
| RB_Leaf : rbt 0 Leaf
| RB_Rd n l k r :
notred l -> notred r -> rbt n l -> rbt n r -> rbt n (Rd l k r)
| RB_Bk n l k r : rbt n l -> rbt n r -> rbt (S n) (Bk l k r).
(** A red-red tree is almost a red-black tree, except that it has
a _red_ root node which _may_ have red children. Note that a
red-red tree is hence non-empty, and all its strict subtrees
are red-black. *)
Inductive rrt (n:nat) : tree -> Prop :=
| RR_Rd l k r : rbt n l -> rbt n r -> rrt n (Rd l k r).
(** An almost-red-black tree is almost a red-black tree, except that
it's permitted to have two red nodes in a row at the very root (only).
We implement this notion by saying that a quasi-red-black tree
is either a red-black tree or a red-red tree. *)
Inductive arbt (n:nat)(t:tree) : Prop :=
| ARB_RB : rbt n t -> arbt n t
| ARB_RR : rrt n t -> arbt n t.
(** The main exported invariant : being a red-black tree for some
black depth. *)
Class Rbt (t:tree) := RBT : exists d, rbt d t.
(** ** Basic tactics and results about red-black *)
Scheme rbt_ind := Induction for rbt Sort Prop.
Local Hint Constructors rbt rrt arbt : core.
Local Hint Extern 0 (notred _) => (exact I) : core.
Ltac invrb := intros; invtree rrt; invtree rbt; try contradiction.
Ltac desarb := match goal with H:arbt _ _ |- _ => destruct H end.
Ltac nonzero n := destruct n as [|n]; [try split; invrb|].
Lemma rr_nrr_rb n t :
rrt n t -> notredred t -> rbt n t.
Proof.
destruct 1 as [l x r Hl Hr].
destruct l, r; descolor; invrb; auto.
Qed.
Local Hint Resolve rr_nrr_rb : core.
Lemma arb_nrr_rb n t :
arbt n t -> notredred t -> rbt n t.
Proof.
destruct 1; auto.
Qed.
Lemma arb_nr_rb n t :
arbt n t -> notred t -> rbt n t.
Proof.
destruct 1; destruct t; descolor; invrb; auto.
Qed.
Local Hint Resolve arb_nrr_rb arb_nr_rb : core.
(** ** A Red-Black tree has indeed a logarithmic depth *)
Definition redcarac s := rcase (fun _ _ _ => 1) (fun _ => 0) s.
Lemma rb_maxdepth s n : rbt n s -> maxdepth s <= 2*n + redcarac s.
Proof.
induction 1.
- simpl; auto.
- replace (redcarac l) with 0 in * by now destree l.
replace (redcarac r) with 0 in * by now destree r.
simpl maxdepth. simpl redcarac.
rewrite Nat.add_succ_r, <- Nat.succ_le_mono.
now apply Nat.max_lub.
- simpl. rewrite <- Nat.succ_le_mono.
apply Nat.max_lub; eapply Nat.le_trans; eauto;
[destree l | destree r]; simpl;
rewrite !Nat.add_0_r, ?Nat.add_1_r; auto with arith.
Qed.
Lemma rb_mindepth s n : rbt n s -> n + redcarac s <= mindepth s.
Proof.
induction 1; simpl.
- trivial.
- rewrite Nat.add_succ_r.
apply -> Nat.succ_le_mono.
replace (redcarac l) with 0 in * by now destree l.
replace (redcarac r) with 0 in * by now destree r.
now apply Nat.min_glb.
- apply -> Nat.succ_le_mono. rewrite Nat.add_0_r.
apply Nat.min_glb; eauto with arith.
Qed.
Lemma maxdepth_upperbound s : Rbt s ->
maxdepth s <= 2 * Nat.log2 (S (cardinal s)).
Proof.
intros (n,H).
eapply Nat.le_trans; [eapply rb_maxdepth; eauto|].
transitivity (2*(n+redcarac s)).
- rewrite Nat.mul_add_distr_l. apply Nat.add_le_mono_l.
rewrite <- Nat.mul_1_l at 1. apply Nat.mul_le_mono_r.
auto with arith.
- apply Nat.mul_le_mono_l.
transitivity (mindepth s).
+ now apply rb_mindepth.
+ apply mindepth_log_cardinal.
Qed.
Lemma maxdepth_lowerbound s : s<>Leaf ->
Nat.log2 (cardinal s) < maxdepth s.
Proof.
apply maxdepth_log_cardinal.
Qed.
(** ** Singleton *)
Lemma singleton_rb x : Rbt (singleton x).
Proof.
unfold singleton. exists 1; auto.
Qed.
(** ** [makeBlack] and [makeRed] *)
Lemma makeBlack_rb n t : arbt n t -> Rbt (makeBlack t).
Proof.
destruct t as [|[|] l x r].
- exists 0; auto.
- destruct 1; invrb; exists (S n); simpl; auto.
- exists n; auto.
Qed.
Lemma makeRed_rr t n :
rbt (S n) t -> notred t -> rrt n (makeRed t).
Proof.
destruct t as [|[|] l x r]; invrb; simpl; auto.
Qed.
(** ** Balancing *)
Lemma lbal_rb n l k r :
arbt n l -> rbt n r -> rbt (S n) (lbal l k r).
Proof.
case lbal_match; intros; desarb; invrb; auto.
Qed.
Lemma rbal_rb n l k r :
rbt n l -> arbt n r -> rbt (S n) (rbal l k r).
Proof.
case rbal_match; intros; desarb; invrb; auto.
Qed.
Lemma rbal'_rb n l k r :
rbt n l -> arbt n r -> rbt (S n) (rbal' l k r).
Proof.
case rbal'_match; intros; desarb; invrb; auto.
Qed.
Lemma lbalS_rb n l x r :
arbt n l -> rbt (S n) r -> notred r -> rbt (S n) (lbalS l x r).
Proof.
intros Hl Hr Hr'.
destruct r as [|[|] rl rx rr]; invrb. clear Hr'.
revert Hl.
case lbalS_match.
- destruct 1; invrb; auto.
- intros. apply rbal'_rb; auto.
Qed.
Lemma lbalS_arb n l x r :
arbt n l -> rbt (S n) r -> arbt (S n) (lbalS l x r).
Proof.
case lbalS_match.
- destruct 1; invrb; auto.
- clear l. intros l Hl Hl' Hr.
destruct r as [|[|] rl rx rr]; invrb.
* destruct rl as [|[|] rll rlx rlr]; invrb.
right; auto using rbal'_rb, makeRed_rr.
* left; apply rbal'_rb; auto.
Qed.
Lemma rbalS_rb n l x r :
rbt (S n) l -> notred l -> arbt n r -> rbt (S n) (rbalS l x r).
Proof.
intros Hl Hl' Hr.
destruct l as [|[|] ll lx lr]; invrb. clear Hl'.
revert Hr.
case rbalS_match.
- destruct 1; invrb; auto.
- intros. apply lbal_rb; auto.
Qed.
Lemma rbalS_arb n l x r :
rbt (S n) l -> arbt n r -> arbt (S n) (rbalS l x r).
Proof.
case rbalS_match.
- destruct 2; invrb; auto.
- clear r. intros r Hr Hr' Hl.
destruct l as [|[|] ll lx lr]; invrb.
* destruct lr as [|[|] lrl lrx lrr]; invrb.
right; auto using lbal_rb, makeRed_rr.
* left; apply lbal_rb; auto.
Qed.
(** ** Insertion *)
(** The next lemmas combine simultaneous results about rbt and arbt.
A first solution here: statement with [if ... then ... else] *)
Definition ifred s (A B:Prop) := rcase (fun _ _ _ => A) (fun _ => B) s.
Lemma ifred_notred s A B : notred s -> (ifred s A B <-> B).
Proof.
destruct s; descolor; simpl; intuition.
Qed.
Lemma ifred_or s A B : ifred s A B -> A\/B.
Proof.
destruct s; descolor; simpl; intuition.
Qed.
Lemma ins_rr_rb x s n : rbt n s ->
ifred s (rrt n (ins x s)) (rbt n (ins x s)).
Proof.
induction 1 as [ | n l k r | n l k r Hl IHl Hr IHr ].
- simpl; auto.
- simpl. rewrite ifred_notred in * by trivial.
elim_compare x k; auto.
- rewrite ifred_notred by trivial.
unfold ins; fold ins. (* simpl is too much here ... *)
elim_compare x k.
* auto.
* apply lbal_rb; trivial. apply ifred_or in IHl; intuition.
* apply rbal_rb; trivial. apply ifred_or in IHr; intuition.
Qed.
Lemma ins_arb x s n : rbt n s -> arbt n (ins x s).
Proof.
intros H. apply (ins_rr_rb x), ifred_or in H. intuition.
Qed.
Instance add_rb x s : Rbt s -> Rbt (add x s).
Proof.
intros (n,H). unfold add. now apply (makeBlack_rb n), ins_arb.
Qed.
(** ** Deletion *)
(** A second approach here: statement with ... /\ ... *)
Lemma append_arb_rb n l r : rbt n l -> rbt n r ->
(arbt n (append l r)) /\
(notred l -> notred r -> rbt n (append l r)).
Proof.
revert r n.
append_tac l r.
- split; auto.
- split; auto.
- (* Red / Red *)
intros n. invrb.
case (IHlr n); auto; clear IHlr.
case append_rr_match.
+ intros a x b _ H; split; invrb.
assert (rbt n (Rd a x b)) by auto. invrb. auto.
+ split; invrb; auto.
- (* Red / Black *)
split; invrb. destruct (IHlr n) as (_,IH); auto.
- (* Black / Red *)
split; invrb. destruct (IHrl n) as (_,IH); auto.
- (* Black / Black *)
nonzero n.
invrb.
destruct (IHlr n) as (IH,_); auto; clear IHlr.
revert IH.
case append_bb_match.
+ intros a x b IH; split; destruct IH; invrb; auto.
+ split; [left | invrb]; auto using lbalS_rb.
Qed.
(** A third approach : Lemma ... with ... *)
Lemma del_arb s x n : rbt (S n) s -> isblack s -> arbt n (del x s)
with del_rb s x n : rbt n s -> notblack s -> rbt n (del x s).
Proof.
{ revert n.
induct s x; try destruct c; try contradiction; invrb.
- apply append_arb_rb; assumption.
- assert (IHl' := del_rb l x). clear IHr del_arb del_rb.
destruct l as [|[|] ll lx lr]; auto.
nonzero n. apply lbalS_arb; auto.
- assert (IHr' := del_rb r x). clear IHl del_arb del_rb.
destruct r as [|[|] rl rx rr]; auto.
nonzero n. apply rbalS_arb; auto. }
{ revert n.
induct s x; try assumption; try destruct c; try contradiction; invrb.
- apply append_arb_rb; assumption.
- assert (IHl' := del_arb l x). clear IHr del_arb del_rb.
destruct l as [|[|] ll lx lr]; auto.
nonzero n. destruct n as [|n]; [invrb|]; apply lbalS_rb; auto.
- assert (IHr' := del_arb r x). clear IHl del_arb del_rb.
destruct r as [|[|] rl rx rr]; auto.
nonzero n. apply rbalS_rb; auto. }
Qed.
Instance remove_rb s x : Rbt s -> Rbt (remove x s).
Proof.
intros (n,H). unfold remove.
destruct s as [|[|] l y r].
- apply (makeBlack_rb n). auto.
- apply (makeBlack_rb n). left. apply del_rb; simpl; auto.
- nonzero n. apply (makeBlack_rb n). apply del_arb; simpl; auto.
Qed.
(** ** Treeify *)
Definition treeify_rb_invariant size depth (f:treeify_t) :=
forall acc,
size <= length acc ->
rbt depth (fst (f acc)) /\
size + length (snd (f acc)) = length acc.
Lemma treeify_zero_rb : treeify_rb_invariant 0 0 treeify_zero.
Proof.
intros acc _; simpl; auto.
Qed.
Lemma treeify_one_rb : treeify_rb_invariant 1 0 treeify_one.
Proof.
intros [|x acc]; simpl; auto; inversion 1.
Qed.
Lemma treeify_cont_rb f g size1 size2 size d :
treeify_rb_invariant size1 d f ->
treeify_rb_invariant size2 d g ->
size = S (size1 + size2) ->
treeify_rb_invariant size (S d) (treeify_cont f g).
Proof.
intros Hf Hg H acc Hacc.
unfold treeify_cont.
specialize (Hf acc).
destruct (f acc) as (l, acc1). simpl in *.
destruct Hf as (Hf1, Hf2). { subst. eauto with arith. }
destruct acc1 as [|x acc2]; simpl in *.
- exfalso. revert Hacc. apply Nat.lt_nge. rewrite H, <- Hf2.
auto with arith.
- specialize (Hg acc2).
destruct (g acc2) as (r, acc3). simpl in *.
destruct Hg as (Hg1, Hg2).
{ revert Hacc.
rewrite H, <- Hf2, Nat.add_succ_r, <- Nat.succ_le_mono.
apply Nat.add_le_mono_l. }
split; auto.
now rewrite H, <- Hf2, <- Hg2, Nat.add_succ_r, Nat.add_assoc.
Qed.
Lemma treeify_aux_rb n :
exists d, forall (b:bool),
treeify_rb_invariant (ifpred b (Pos.to_nat n)) d (treeify_aux b n).
Proof.
induction n as [n (d,IHn)|n (d,IHn)| ].
- exists (S d). intros b.
eapply treeify_cont_rb; [ apply (IHn false) | apply (IHn b) | ].
rewrite Pos2Nat.inj_xI.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
destruct b; simpl; intros; rewrite Nat.add_0_r; trivial.
now rewrite <- Nat.add_succ_r, Nat.succ_pred; trivial.
- exists (S d). intros b.
eapply treeify_cont_rb; [ apply (IHn b) | apply (IHn true) | ].
rewrite Pos2Nat.inj_xO.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
rewrite <- Nat.add_succ_r, Nat.succ_pred by trivial.
destruct b; simpl; intros; rewrite Nat.add_0_r; trivial.
symmetry. now apply Nat.add_pred_l.
- exists 0; destruct b;
[ apply treeify_zero_rb | apply treeify_one_rb ].
Qed.
(** The black depth of [treeify l] is actually a log2, but
we don't need to mention that. *)
Instance treeify_rb l : Rbt (treeify l).
Proof.
unfold treeify.
destruct (treeify_aux_rb (plength l)) as (d,H).
exists d.
apply H.
now rewrite plength_spec.
Qed.
(** ** Filtering *)
Instance filter_rb f s : Rbt (filter f s).
Proof.
unfold filter; auto_tc.
Qed.
Instance partition_rb1 f s : Rbt (fst (partition f s)).
Proof.
unfold partition. destruct partition_aux. simpl. auto_tc.
Qed.
Instance partition_rb2 f s : Rbt (snd (partition f s)).
Proof.
unfold partition. destruct partition_aux. simpl. auto_tc.
Qed.
(** ** Union, intersection, difference *)
Instance fold_add_rb s1 s2 : Rbt s2 -> Rbt (fold add s1 s2).
Proof.
intros. rewrite fold_spec, <- fold_left_rev_right. unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance fold_remove_rb s1 s2 : Rbt s2 -> Rbt (fold remove s1 s2).
Proof.
intros. rewrite fold_spec, <- fold_left_rev_right. unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Lemma union_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (union s1 s2).
Proof.
intros. unfold union, linear_union. destruct compare_height; auto_tc.
Qed.
Lemma inter_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (inter s1 s2).
Proof.
intros. unfold inter, linear_inter. destruct compare_height; auto_tc.
Qed.
Lemma diff_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (diff s1 s2).
Proof.
intros. unfold diff, linear_diff. destruct compare_height; auto_tc.
Qed.
End BalanceProps.
(** * Final Encapsulation
Now, in order to really provide a functor implementing [S], we
need to encapsulate everything into a type of binary search trees.
They also happen to be well-balanced, but this has no influence
on the correctness of operations, so we won't state this here,
see [BalanceProps] if you need more than just the MSet interface.
*)
Module Type MSetInterface_S_Ext := MSetInterface.S <+ MSetRemoveMin.
Module Make (X: Orders.OrderedType) <:
MSetInterface_S_Ext with Module E := X.
Module Raw. Include MakeRaw X. End Raw.
Include MSetInterface.Raw2Sets X Raw.
Definition opt_ok (x:option (elt * Raw.t)) :=
match x with Some (_,s) => Raw.Ok s | None => True end.
Definition mk_opt_t (x: option (elt * Raw.t))(P: opt_ok x) :
option (elt * t) :=
match x as o return opt_ok o -> option (elt * t) with
| Some (k,s') => fun P : Raw.Ok s' => Some (k, Mkt s')
| None => fun _ => None
end P.
Definition remove_min s : option (elt * t) :=
mk_opt_t (Raw.remove_min (this s)) (Raw.remove_min_ok s).
Lemma remove_min_spec1 s x s' :
remove_min s = Some (x,s') ->
min_elt s = Some x /\ Equal (remove x s) s'.
Proof.
destruct s as (s,Hs).
unfold remove_min, mk_opt_t, min_elt, remove, Equal, In; simpl.
generalize (fun x s' => @Raw.remove_min_spec1 s x s' Hs).
set (P := Raw.remove_min_ok s). clearbody P.
destruct (Raw.remove_min s) as [(x0,s0)|]; try easy.
intros H [= -> <-]. simpl.
destruct (H x s0); auto. subst; intuition.
Qed.
Lemma remove_min_spec2 s : remove_min s = None -> Empty s.
Proof.
destruct s as (s,Hs).
unfold remove_min, mk_opt_t, Empty, In; simpl.
generalize (Raw.remove_min_spec2 s).
set (P := Raw.remove_min_ok s). clearbody P.
destruct (Raw.remove_min s) as [(x0,s0)|]; now intuition.
Qed.
End Make.
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: barrel_shifter_synthesis.v
// /___/ /\ Timestamp: Sun May 03 00:34:43 2015
// \ \ / \
// \___\/\___\
//
// Command : -intstyle ise -tm barrel_shifter_synthesis -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim barrel_shifter.ngc barrel_shifter_synthesis.v
// Device : xc6slx16-2-csg324
// Input file : barrel_shifter.ngc
// Output file : D:\Projects\Xilinx\Shifter\netgen\synthesis\barrel_shifter_synthesis.v
// # of Modules : 1
// Design Name : barrel_shifter
// Xilinx : D:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module barrel_shifter_synthesis (
rotate, sra, ain, bin, yout
);
input rotate;
input sra;
input [15 : 0] ain;
input [4 : 0] bin;
output [15 : 0] yout;
wire ain_0_IBUF_0;
wire ain_14_IBUF_1;
wire ain_1_IBUF_2;
wire ain_13_IBUF_3;
wire ain_2_IBUF_4;
wire ain_12_IBUF_5;
wire ain_3_IBUF_6;
wire ain_11_IBUF_7;
wire ain_4_IBUF_8;
wire ain_10_IBUF_9;
wire ain_5_IBUF_10;
wire ain_9_IBUF_11;
wire ain_6_IBUF_12;
wire ain_8_IBUF_13;
wire ain_7_IBUF_14;
wire ain_15_IBUF_15;
wire bin_4_IBUF_16;
wire bin_3_IBUF_17;
wire bin_2_IBUF_18;
wire bin_1_IBUF_19;
wire bin_0_IBUF_20;
wire rotate_IBUF_21;
wire sra_IBUF_22;
wire yout_15_OBUF_25;
wire yout_14_OBUF_26;
wire yout_13_OBUF_27;
wire yout_12_OBUF_28;
wire yout_11_OBUF_29;
wire yout_10_OBUF_30;
wire yout_9_OBUF_31;
wire yout_8_OBUF_32;
wire yout_7_OBUF_33;
wire yout_6_OBUF_34;
wire yout_5_OBUF_35;
wire yout_4_OBUF_36;
wire yout_3_OBUF_37;
wire yout_2_OBUF_38;
wire yout_1_OBUF_39;
wire yout_0_OBUF_40;
wire \b<3>_mmx_out29 ;
wire \b<3>_mmx_out27 ;
wire \b<3>_mmx_out25 ;
wire \b<3>_mmx_out24 ;
wire \b<3>_mmx_out23 ;
wire \b<3>_mmx_out22 ;
wire \b<2>_mmx_out15 ;
wire \b<3>_mmx_out14 ;
wire \b<2>_mmx_out14 ;
wire \b<2>_mmx_out13 ;
wire \b<3>_mmx_out12 ;
wire \b<2>_mmx_out12 ;
wire \b<3>_mmx_out11 ;
wire \b<2>_mmx_out11 ;
wire \b<2>_mmx_out10 ;
wire \b<2>_mmx_out9 ;
wire \b<3>_mmx_out7 ;
wire \b<2>_mmx_out8 ;
wire \b<3>_mmx_out5 ;
wire \b<3>_mmx_out3 ;
wire \b<2>_mmx_out ;
wire \b<2>111 ;
wire Mmux_yout201;
wire Mmux_yout141;
wire Mmux_yout121;
wire Mmux_yout111_66;
wire Mmux_yout61;
wire Mmux_yout122_68;
wire Mmux_yout191_69;
wire Mmux_yout71;
wire Mmux_yout1221;
wire Mmux_yout51;
wire Mmux_yout1811;
wire Mmux_yout1411;
wire Mmux_yout1311;
wire Mmux_yout1711;
wire Mmux_yout1222;
wire Mmux_yout52;
wire Mmux_yout1511;
wire Mmux_yout1611_80;
wire Mmux_yout114_81;
wire \b<2>151 ;
wire Mmux_yout1112;
wire Mmux_yout1224;
wire Mmux_yout911;
wire Mmux_yout14111_86;
wire Mmux_yout14112_87;
wire Mmux_yout13111_88;
wire Mmux_yout13112_89;
wire Mmux_yout15111_90;
wire Mmux_yout15112_91;
wire Mmux_yout3;
wire Mmux_yout31_93;
wire Mmux_yout32_94;
wire N2;
wire Mmux_yout1141_96;
wire Mmux_yout1211_97;
wire Mmux_yout1212_98;
wire Mmux_yout1213_99;
wire \b<2>2 ;
wire Mmux_yout17111_101;
wire Mmux_yout17112_102;
wire N4;
wire Mmux_yout18111_104;
wire Mmux_yout18112_105;
wire N6;
wire Mmux_yout11;
wire Mmux_yout112_108;
wire Mmux_yout113_109;
wire N8;
wire N10;
wire N12;
wire N14;
wire N15;
wire N16;
wire N17;
wire [3 : 2] b;
LUT2 #(
.INIT ( 4'h6 ))
\Mmux_b<3>11 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.O(b[3])
);
LUT2 #(
.INIT ( 4'h6 ))
\Mmux_b<2>11 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.O(b[2])
);
LUT3 #(
.INIT ( 8'hE4 ))
Mmux_yout202 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout191_69),
.I2(Mmux_yout201),
.O(yout_9_OBUF_31)
);
LUT3 #(
.INIT ( 8'hE4 ))
Mmux_yout72 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout61),
.I2(Mmux_yout71),
.O(yout_13_OBUF_27)
);
LUT3 #(
.INIT ( 8'hE4 ))
Mmux_yout81 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout71),
.I2(Mmux_yout111_66),
.O(yout_14_OBUF_26)
);
LUT3 #(
.INIT ( 8'hE4 ))
Mmux_yout41 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout201),
.I2(Mmux_yout51),
.O(yout_10_OBUF_30)
);
LUT3 #(
.INIT ( 8'hE4 ))
Mmux_yout62 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout52),
.I2(Mmux_yout61),
.O(yout_12_OBUF_28)
);
LUT3 #(
.INIT ( 8'hE4 ))
Mmux_yout53 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout51),
.I2(Mmux_yout52),
.O(yout_11_OBUF_29)
);
LUT5 #(
.INIT ( 32'hFD5DA808 ))
Mmux_yout1911 (
.I0(bin_1_IBUF_19),
.I1(\b<2>_mmx_out8 ),
.I2(bin_4_IBUF_16),
.I3(\b<2>_mmx_out9 ),
.I4(Mmux_yout1711),
.O(Mmux_yout191_69)
);
LUT5 #(
.INIT ( 32'hFD5DA808 ))
Mmux_yout2011 (
.I0(bin_1_IBUF_19),
.I1(\b<2>_mmx_out10 ),
.I2(bin_4_IBUF_16),
.I3(\b<2>_mmx_out11 ),
.I4(Mmux_yout1811),
.O(Mmux_yout201)
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
Mmux_yout711 (
.I0(bin_1_IBUF_19),
.I1(bin_4_IBUF_16),
.I2(\b<2>_mmx_out15 ),
.I3(\b<2>_mmx_out14 ),
.I4(Mmux_yout114_81),
.O(Mmux_yout71)
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
Mmux_yout611 (
.I0(bin_1_IBUF_19),
.I1(bin_4_IBUF_16),
.I2(\b<2>_mmx_out13 ),
.I3(\b<2>_mmx_out12 ),
.I4(Mmux_yout1112),
.O(Mmux_yout61)
);
LUT3 #(
.INIT ( 8'h40 ))
Mmux_yout9111 (
.I0(rotate_IBUF_21),
.I1(ain_15_IBUF_15),
.I2(sra_IBUF_22),
.O(Mmux_yout911)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\b<2>311 (
.I0(b[2]),
.I1(b[3]),
.I2(ain_6_IBUF_12),
.I3(ain_14_IBUF_1),
.I4(ain_10_IBUF_9),
.I5(ain_2_IBUF_4),
.O(\b<2>_mmx_out )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
Mmux_yout12211 (
.I0(b[3]),
.I1(bin_2_IBUF_18),
.I2(ain_1_IBUF_2),
.I3(ain_5_IBUF_10),
.I4(ain_13_IBUF_3),
.I5(ain_9_IBUF_11),
.O(Mmux_yout1221)
);
LUT5 #(
.INIT ( 32'hFD5DA808 ))
Mmux_yout131 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout1224),
.I2(bin_1_IBUF_19),
.I3(Mmux_yout1311),
.I4(Mmux_yout121),
.O(yout_2_OBUF_38)
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
Mmux_yout142 (
.I0(bin_0_IBUF_20),
.I1(bin_1_IBUF_19),
.I2(Mmux_yout1311),
.I3(Mmux_yout1224),
.I4(Mmux_yout141),
.O(yout_3_OBUF_37)
);
LUT5 #(
.INIT ( 32'hFD5DA808 ))
Mmux_yout151 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout1311),
.I2(bin_1_IBUF_19),
.I3(Mmux_yout1511),
.I4(Mmux_yout141),
.O(yout_4_OBUF_36)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
Mmux_yout161 (
.I0(bin_0_IBUF_20),
.I1(bin_1_IBUF_19),
.I2(Mmux_yout1411),
.I3(Mmux_yout1611_80),
.I4(Mmux_yout1511),
.I5(Mmux_yout1311),
.O(yout_5_OBUF_35)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
Mmux_yout171 (
.I0(bin_0_IBUF_20),
.I1(bin_1_IBUF_19),
.I2(Mmux_yout1511),
.I3(Mmux_yout1711),
.I4(Mmux_yout1611_80),
.I5(Mmux_yout1411),
.O(yout_6_OBUF_34)
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
Mmux_yout191 (
.I0(bin_0_IBUF_20),
.I1(bin_1_IBUF_19),
.I2(Mmux_yout1811),
.I3(Mmux_yout1611_80),
.I4(Mmux_yout191_69),
.O(yout_8_OBUF_32)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
Mmux_yout181 (
.I0(bin_0_IBUF_20),
.I1(bin_1_IBUF_19),
.I2(Mmux_yout1611_80),
.I3(Mmux_yout1811),
.I4(Mmux_yout1711),
.I5(Mmux_yout1511),
.O(yout_7_OBUF_33)
);
LUT6 #(
.INIT ( 64'hFD5D5D5DA8080808 ))
\b<2>31 (
.I0(b[2]),
.I1(ain_4_IBUF_8),
.I2(b[3]),
.I3(ain_12_IBUF_5),
.I4(rotate_IBUF_21),
.I5(\b<3>_mmx_out11 ),
.O(\b<2>_mmx_out11 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\b<2>1511 (
.I0(b[2]),
.I1(b[3]),
.I2(ain_10_IBUF_9),
.I3(ain_2_IBUF_4),
.I4(ain_6_IBUF_12),
.I5(ain_14_IBUF_1),
.O(\b<2>151 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
Mmux_yout511 (
.I0(bin_1_IBUF_19),
.I1(bin_4_IBUF_16),
.I2(\b<2>_mmx_out12 ),
.I3(\b<2>_mmx_out13 ),
.I4(\b<2>_mmx_out9 ),
.I5(\b<2>_mmx_out8 ),
.O(Mmux_yout51)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
Mmux_yout521 (
.I0(bin_1_IBUF_19),
.I1(bin_4_IBUF_16),
.I2(\b<2>_mmx_out14 ),
.I3(\b<2>_mmx_out15 ),
.I4(\b<2>_mmx_out11 ),
.I5(\b<2>_mmx_out10 ),
.O(Mmux_yout52)
);
LUT5 #(
.INIT ( 32'hA8202020 ))
Mmux_yout31 (
.I0(bin_1_IBUF_19),
.I1(bin_4_IBUF_16),
.I2(\b<2>_mmx_out ),
.I3(\b<2>151 ),
.I4(rotate_IBUF_21),
.O(Mmux_yout3)
);
LUT6 #(
.INIT ( 64'hFD5D5D5DA8080808 ))
Mmux_yout33 (
.I0(bin_2_IBUF_18),
.I1(\b<3>_mmx_out23 ),
.I2(bin_4_IBUF_16),
.I3(\b<2>111 ),
.I4(rotate_IBUF_21),
.I5(Mmux_yout31_93),
.O(Mmux_yout32_94)
);
LUT5 #(
.INIT ( 32'hEEFE4454 ))
Mmux_yout34 (
.I0(bin_0_IBUF_20),
.I1(Mmux_yout3),
.I2(Mmux_yout32_94),
.I3(bin_1_IBUF_19),
.I4(Mmux_yout122_68),
.O(yout_0_OBUF_40)
);
LUT6 #(
.INIT ( 64'hEFABABAB45010101 ))
Mmux_yout122 (
.I0(bin_1_IBUF_19),
.I1(bin_4_IBUF_16),
.I2(N2),
.I3(rotate_IBUF_21),
.I4(Mmux_yout1221),
.I5(Mmux_yout1224),
.O(Mmux_yout122_68)
);
LUT6 #(
.INIT ( 64'hA8AAA88820222000 ))
Mmux_yout1141 (
.I0(rotate_IBUF_21),
.I1(b[2]),
.I2(ain_8_IBUF_13),
.I3(b[3]),
.I4(ain_0_IBUF_0),
.I5(\b<3>_mmx_out23 ),
.O(Mmux_yout1141_96)
);
LUT4 #(
.INIT ( 16'hE444 ))
Mmux_yout1213 (
.I0(bin_4_IBUF_16),
.I1(\b<2>_mmx_out ),
.I2(\b<2>151 ),
.I3(rotate_IBUF_21),
.O(Mmux_yout1213_99)
);
LUT4 #(
.INIT ( 16'hFDA8 ))
Mmux_yout1214 (
.I0(bin_1_IBUF_19),
.I1(Mmux_yout1211_97),
.I2(Mmux_yout1212_98),
.I3(Mmux_yout1213_99),
.O(Mmux_yout121)
);
LUT4 #(
.INIT ( 16'hFE54 ))
Mmux_yout1413 (
.I0(bin_1_IBUF_19),
.I1(Mmux_yout1211_97),
.I2(Mmux_yout1212_98),
.I3(Mmux_yout1411),
.O(Mmux_yout141)
);
LUT6 #(
.INIT ( 64'hA8A0282088800800 ))
\b<2>21 (
.I0(rotate_IBUF_21),
.I1(b[2]),
.I2(b[3]),
.I3(ain_0_IBUF_0),
.I4(ain_8_IBUF_13),
.I5(ain_4_IBUF_8),
.O(\b<2>2 )
);
LUT6 #(
.INIT ( 64'hDDD55D5588800800 ))
Mmux_yout17112 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(b[2]),
.I3(ain_13_IBUF_3),
.I4(ain_9_IBUF_11),
.I5(Mmux_yout17111_101),
.O(Mmux_yout17112_102)
);
LUT2 #(
.INIT ( 4'h8 ))
\b<2>5_SW0 (
.I0(rotate_IBUF_21),
.I1(ain_13_IBUF_3),
.O(N4)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\b<2>5 (
.I0(b[3]),
.I1(b[2]),
.I2(ain_1_IBUF_2),
.I3(N4),
.I4(ain_5_IBUF_10),
.I5(ain_9_IBUF_11),
.O(\b<2>_mmx_out13 )
);
LUT6 #(
.INIT ( 64'hDDD55D5588800800 ))
Mmux_yout18112 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(b[2]),
.I3(ain_14_IBUF_1),
.I4(ain_10_IBUF_9),
.I5(Mmux_yout18111_104),
.O(Mmux_yout18112_105)
);
LUT6 #(
.INIT ( 64'hEFEA454045404540 ))
\b<2>29 (
.I0(b[3]),
.I1(ain_3_IBUF_6),
.I2(b[2]),
.I3(ain_7_IBUF_14),
.I4(N6),
.I5(rotate_IBUF_21),
.O(\b<2>_mmx_out9 )
);
LUT6 #(
.INIT ( 64'hFFF7DDD5AAA28880 ))
Mmux_yout115 (
.I0(bin_0_IBUF_20),
.I1(bin_1_IBUF_19),
.I2(Mmux_yout112_108),
.I3(Mmux_yout113_109),
.I4(Mmux_yout114_81),
.I5(Mmux_yout111_66),
.O(yout_15_OBUF_25)
);
LUT2 #(
.INIT ( 4'h8 ))
\b<2>7_SW0 (
.I0(rotate_IBUF_21),
.I1(ain_14_IBUF_1),
.O(N8)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\b<2>7 (
.I0(b[3]),
.I1(b[2]),
.I2(ain_2_IBUF_4),
.I3(N8),
.I4(ain_6_IBUF_12),
.I5(ain_10_IBUF_9),
.O(\b<2>_mmx_out15 )
);
LUT5 #(
.INIT ( 32'hFD5DA808 ))
Mmux_yout111 (
.I0(bin_1_IBUF_19),
.I1(N10),
.I2(bin_4_IBUF_16),
.I3(Mmux_yout1221),
.I4(Mmux_yout1112),
.O(Mmux_yout111_66)
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
Mmux_yout1611 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(\b<3>_mmx_out24 ),
.I3(\b<3>_mmx_out22 ),
.I4(N12),
.O(Mmux_yout1611_80)
);
IBUF ain_15_IBUF (
.I(ain[15]),
.O(ain_15_IBUF_15)
);
IBUF ain_14_IBUF (
.I(ain[14]),
.O(ain_14_IBUF_1)
);
IBUF ain_13_IBUF (
.I(ain[13]),
.O(ain_13_IBUF_3)
);
IBUF ain_12_IBUF (
.I(ain[12]),
.O(ain_12_IBUF_5)
);
IBUF ain_11_IBUF (
.I(ain[11]),
.O(ain_11_IBUF_7)
);
IBUF ain_10_IBUF (
.I(ain[10]),
.O(ain_10_IBUF_9)
);
IBUF ain_9_IBUF (
.I(ain[9]),
.O(ain_9_IBUF_11)
);
IBUF ain_8_IBUF (
.I(ain[8]),
.O(ain_8_IBUF_13)
);
IBUF ain_7_IBUF (
.I(ain[7]),
.O(ain_7_IBUF_14)
);
IBUF ain_6_IBUF (
.I(ain[6]),
.O(ain_6_IBUF_12)
);
IBUF ain_5_IBUF (
.I(ain[5]),
.O(ain_5_IBUF_10)
);
IBUF ain_4_IBUF (
.I(ain[4]),
.O(ain_4_IBUF_8)
);
IBUF ain_3_IBUF (
.I(ain[3]),
.O(ain_3_IBUF_6)
);
IBUF ain_2_IBUF (
.I(ain[2]),
.O(ain_2_IBUF_4)
);
IBUF ain_1_IBUF (
.I(ain[1]),
.O(ain_1_IBUF_2)
);
IBUF ain_0_IBUF (
.I(ain[0]),
.O(ain_0_IBUF_0)
);
IBUF bin_4_IBUF (
.I(bin[4]),
.O(bin_4_IBUF_16)
);
IBUF bin_3_IBUF (
.I(bin[3]),
.O(bin_3_IBUF_17)
);
IBUF bin_2_IBUF (
.I(bin[2]),
.O(bin_2_IBUF_18)
);
IBUF bin_1_IBUF (
.I(bin[1]),
.O(bin_1_IBUF_19)
);
IBUF bin_0_IBUF (
.I(bin[0]),
.O(bin_0_IBUF_20)
);
IBUF rotate_IBUF (
.I(rotate),
.O(rotate_IBUF_21)
);
IBUF sra_IBUF (
.I(sra),
.O(sra_IBUF_22)
);
OBUF yout_15_OBUF (
.I(yout_15_OBUF_25),
.O(yout[15])
);
OBUF yout_14_OBUF (
.I(yout_14_OBUF_26),
.O(yout[14])
);
OBUF yout_13_OBUF (
.I(yout_13_OBUF_27),
.O(yout[13])
);
OBUF yout_12_OBUF (
.I(yout_12_OBUF_28),
.O(yout[12])
);
OBUF yout_11_OBUF (
.I(yout_11_OBUF_29),
.O(yout[11])
);
OBUF yout_10_OBUF (
.I(yout_10_OBUF_30),
.O(yout[10])
);
OBUF yout_9_OBUF (
.I(yout_9_OBUF_31),
.O(yout[9])
);
OBUF yout_8_OBUF (
.I(yout_8_OBUF_32),
.O(yout[8])
);
OBUF yout_7_OBUF (
.I(yout_7_OBUF_33),
.O(yout[7])
);
OBUF yout_6_OBUF (
.I(yout_6_OBUF_34),
.O(yout[6])
);
OBUF yout_5_OBUF (
.I(yout_5_OBUF_35),
.O(yout[5])
);
OBUF yout_4_OBUF (
.I(yout_4_OBUF_36),
.O(yout[4])
);
OBUF yout_3_OBUF (
.I(yout_3_OBUF_37),
.O(yout[3])
);
OBUF yout_2_OBUF (
.I(yout_2_OBUF_38),
.O(yout[2])
);
OBUF yout_1_OBUF (
.I(yout_1_OBUF_39),
.O(yout[1])
);
OBUF yout_0_OBUF (
.I(yout_0_OBUF_40),
.O(yout[0])
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
\b<3>151 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(ain_0_IBUF_0),
.I3(ain_15_IBUF_15),
.I4(sra_IBUF_22),
.I5(ain_8_IBUF_13),
.O(\b<3>_mmx_out22 )
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
\b<3>181 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(ain_1_IBUF_2),
.I3(ain_15_IBUF_15),
.I4(sra_IBUF_22),
.I5(ain_9_IBUF_11),
.O(\b<3>_mmx_out25 )
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
\b<3>201 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(ain_2_IBUF_4),
.I3(ain_15_IBUF_15),
.I4(sra_IBUF_22),
.I5(ain_10_IBUF_9),
.O(\b<3>_mmx_out27 )
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
\b<3>221 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(ain_3_IBUF_6),
.I3(ain_15_IBUF_15),
.I4(sra_IBUF_22),
.I5(ain_11_IBUF_7),
.O(\b<3>_mmx_out29 )
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
\b<3>231 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(ain_5_IBUF_10),
.I3(ain_15_IBUF_15),
.I4(sra_IBUF_22),
.I5(ain_13_IBUF_3),
.O(\b<3>_mmx_out3 )
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
\b<3>251 (
.I0(b[3]),
.I1(rotate_IBUF_21),
.I2(ain_6_IBUF_12),
.I3(ain_15_IBUF_15),
.I4(sra_IBUF_22),
.I5(ain_14_IBUF_1),
.O(\b<3>_mmx_out5 )
);
LUT6 #(
.INIT ( 64'hF7D5A280A280A280 ))
\b<3>41 (
.I0(rotate_IBUF_21),
.I1(b[3]),
.I2(ain_9_IBUF_11),
.I3(ain_1_IBUF_2),
.I4(ain_15_IBUF_15),
.I5(sra_IBUF_22),
.O(\b<3>_mmx_out12 )
);
LUT6 #(
.INIT ( 64'hF7D5A280A280A280 ))
\b<3>61 (
.I0(rotate_IBUF_21),
.I1(b[3]),
.I2(ain_10_IBUF_9),
.I3(ain_2_IBUF_4),
.I4(ain_15_IBUF_15),
.I5(sra_IBUF_22),
.O(\b<3>_mmx_out14 )
);
LUT5 #(
.INIT ( 32'hB391A280 ))
Mmux_yout14112 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_2_IBUF_4),
.I3(ain_14_IBUF_1),
.I4(ain_6_IBUF_12),
.O(Mmux_yout14112_87)
);
LUT6 #(
.INIT ( 64'hFED4D4D4BA909090 ))
Mmux_yout14113 (
.I0(bin_4_IBUF_16),
.I1(bin_2_IBUF_18),
.I2(Mmux_yout14112_87),
.I3(rotate_IBUF_21),
.I4(Mmux_yout14111_86),
.I5(\b<3>_mmx_out27 ),
.O(Mmux_yout1411)
);
LUT5 #(
.INIT ( 32'hB391A280 ))
Mmux_yout13112 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_1_IBUF_2),
.I3(ain_13_IBUF_3),
.I4(ain_5_IBUF_10),
.O(Mmux_yout13112_89)
);
LUT6 #(
.INIT ( 64'hFED4D4D4BA909090 ))
Mmux_yout13113 (
.I0(bin_4_IBUF_16),
.I1(bin_2_IBUF_18),
.I2(Mmux_yout13112_89),
.I3(rotate_IBUF_21),
.I4(Mmux_yout13111_88),
.I5(\b<3>_mmx_out25 ),
.O(Mmux_yout1311)
);
LUT5 #(
.INIT ( 32'hB391A280 ))
Mmux_yout15112 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_3_IBUF_6),
.I3(ain_15_IBUF_15),
.I4(ain_7_IBUF_14),
.O(Mmux_yout15112_91)
);
LUT6 #(
.INIT ( 64'hFED4D4D4BA909090 ))
Mmux_yout15113 (
.I0(bin_4_IBUF_16),
.I1(bin_2_IBUF_18),
.I2(Mmux_yout15112_91),
.I3(rotate_IBUF_21),
.I4(Mmux_yout15111_90),
.I5(\b<3>_mmx_out29 ),
.O(Mmux_yout1511)
);
LUT6 #(
.INIT ( 64'h082A193B4C6E5D7F ))
Mmux_yout122_SW0 (
.I0(bin_2_IBUF_18),
.I1(b[3]),
.I2(ain_13_IBUF_3),
.I3(ain_5_IBUF_10),
.I4(ain_1_IBUF_2),
.I5(ain_9_IBUF_11),
.O(N2)
);
LUT6 #(
.INIT ( 64'hFD75FD75FD75A820 ))
Mmux_yout1142 (
.I0(bin_4_IBUF_16),
.I1(bin_2_IBUF_18),
.I2(\b<3>_mmx_out11 ),
.I3(\b<2>111 ),
.I4(Mmux_yout911),
.I5(Mmux_yout1141_96),
.O(Mmux_yout114_81)
);
LUT5 #(
.INIT ( 32'h62224000 ))
Mmux_yout1211 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(\b<2>111 ),
.I3(rotate_IBUF_21),
.I4(\b<3>_mmx_out22 ),
.O(Mmux_yout1211_97)
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
Mmux_yout17113 (
.I0(bin_4_IBUF_16),
.I1(bin_2_IBUF_18),
.I2(\b<3>_mmx_out3 ),
.I3(\b<3>_mmx_out25 ),
.I4(Mmux_yout17112_102),
.O(Mmux_yout1711)
);
LUT5 #(
.INIT ( 32'hFBEA5140 ))
Mmux_yout18113 (
.I0(bin_4_IBUF_16),
.I1(bin_2_IBUF_18),
.I2(\b<3>_mmx_out5 ),
.I3(\b<3>_mmx_out27 ),
.I4(Mmux_yout18112_105),
.O(Mmux_yout1811)
);
LUT6 #(
.INIT ( 64'hAAA00A0088800800 ))
Mmux_yout112 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(bin_3_IBUF_17),
.I3(ain_6_IBUF_12),
.I4(ain_14_IBUF_1),
.I5(rotate_IBUF_21),
.O(Mmux_yout11)
);
LUT6 #(
.INIT ( 64'h5551151144400400 ))
Mmux_yout114 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(bin_3_IBUF_17),
.I3(ain_2_IBUF_4),
.I4(ain_10_IBUF_9),
.I5(\b<3>_mmx_out14 ),
.O(Mmux_yout113_109)
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
Mmux_yout111_SW0 (
.I0(bin_2_IBUF_18),
.I1(rotate_IBUF_21),
.I2(Mmux_yout1222),
.I3(ain_15_IBUF_15),
.I4(sra_IBUF_22),
.I5(\b<3>_mmx_out12 ),
.O(N10)
);
LUT6 #(
.INIT ( 64'hDF8FDD858A8A8880 ))
Mmux_yout1611_SW0 (
.I0(bin_3_IBUF_17),
.I1(ain_4_IBUF_8),
.I2(bin_4_IBUF_16),
.I3(rotate_IBUF_21),
.I4(Mmux_yout911),
.I5(ain_12_IBUF_5),
.O(N12)
);
LUT5 #(
.INIT ( 32'hF6909090 ))
\b<3>171 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_0_IBUF_0),
.I3(rotate_IBUF_21),
.I4(ain_8_IBUF_13),
.O(\b<3>_mmx_out24 )
);
LUT4 #(
.INIT ( 16'hF690 ))
\b<3>161 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_4_IBUF_8),
.I3(ain_12_IBUF_5),
.O(\b<3>_mmx_out23 )
);
LUT4 #(
.INIT ( 16'hF690 ))
\b<2>281 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(\b<3>_mmx_out29 ),
.I3(\b<3>_mmx_out7 ),
.O(\b<2>_mmx_out8 )
);
LUT4 #(
.INIT ( 16'hF690 ))
\b<2>61 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(\b<3>_mmx_out5 ),
.I3(\b<3>_mmx_out14 ),
.O(\b<2>_mmx_out14 )
);
LUT4 #(
.INIT ( 16'hF690 ))
\b<2>41 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(\b<3>_mmx_out3 ),
.I3(\b<3>_mmx_out12 ),
.O(\b<2>_mmx_out12 )
);
LUT4 #(
.INIT ( 16'hF690 ))
\b<2>1111 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_12_IBUF_5),
.I3(ain_4_IBUF_8),
.O(\b<2>111 )
);
LUT6 #(
.INIT ( 64'hFFF7DDD5AAA28880 ))
Mmux_yout123 (
.I0(bin_0_IBUF_20),
.I1(bin_1_IBUF_19),
.I2(Mmux_yout1211_97),
.I3(Mmux_yout1212_98),
.I4(Mmux_yout1213_99),
.I5(Mmux_yout122_68),
.O(yout_1_OBUF_39)
);
LUT6 #(
.INIT ( 64'hBEAABE8282AA8282 ))
\b<3>271 (
.I0(ain_15_IBUF_15),
.I1(bin_3_IBUF_17),
.I2(bin_4_IBUF_16),
.I3(rotate_IBUF_21),
.I4(sra_IBUF_22),
.I5(ain_7_IBUF_14),
.O(\b<3>_mmx_out7 )
);
LUT4 #(
.INIT ( 16'hF690 ))
Mmux_yout17111 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(ain_5_IBUF_10),
.I3(ain_1_IBUF_2),
.O(Mmux_yout17111_101)
);
LUT4 #(
.INIT ( 16'hF690 ))
Mmux_yout18111 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(ain_6_IBUF_12),
.I3(ain_2_IBUF_4),
.O(Mmux_yout18111_104)
);
LUT4 #(
.INIT ( 16'hF690 ))
\b<2>29_SW0 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(ain_15_IBUF_15),
.I3(ain_11_IBUF_7),
.O(N6)
);
LUT5 #(
.INIT ( 32'hE0EE2022 ))
Mmux_yout32 (
.I0(ain_0_IBUF_0),
.I1(bin_3_IBUF_17),
.I2(rotate_IBUF_21),
.I3(bin_4_IBUF_16),
.I4(ain_8_IBUF_13),
.O(Mmux_yout31_93)
);
LUT6 #(
.INIT ( 64'h9989988811011000 ))
Mmux_yout1212 (
.I0(bin_2_IBUF_18),
.I1(bin_4_IBUF_16),
.I2(bin_3_IBUF_17),
.I3(ain_12_IBUF_5),
.I4(ain_4_IBUF_8),
.I5(\b<3>_mmx_out24 ),
.O(Mmux_yout1212_98)
);
LUT6 #(
.INIT ( 64'h7E5A3C1866422400 ))
Mmux_yout14111 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(bin_2_IBUF_18),
.I3(ain_6_IBUF_12),
.I4(ain_10_IBUF_9),
.I5(ain_14_IBUF_1),
.O(Mmux_yout14111_86)
);
LUT6 #(
.INIT ( 64'h7E5A3C1866422400 ))
Mmux_yout13111 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(bin_2_IBUF_18),
.I3(ain_5_IBUF_10),
.I4(ain_9_IBUF_11),
.I5(ain_13_IBUF_3),
.O(Mmux_yout13111_88)
);
LUT6 #(
.INIT ( 64'h7E5A3C1866422400 ))
Mmux_yout15111 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(bin_2_IBUF_18),
.I3(ain_7_IBUF_14),
.I4(ain_11_IBUF_7),
.I5(ain_15_IBUF_15),
.O(Mmux_yout15111_90)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFEAAB2AA8 ))
\b<2>22 (
.I0(Mmux_yout911),
.I1(bin_2_IBUF_18),
.I2(bin_4_IBUF_16),
.I3(bin_3_IBUF_17),
.I4(ain_12_IBUF_5),
.I5(\b<2>2 ),
.O(\b<2>_mmx_out10 )
);
LUT4 #(
.INIT ( 16'hF690 ))
\b<3>31 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_8_IBUF_13),
.I3(ain_0_IBUF_0),
.O(\b<3>_mmx_out11 )
);
LUT4 #(
.INIT ( 16'hF690 ))
Mmux_yout12221 (
.I0(bin_3_IBUF_17),
.I1(bin_4_IBUF_16),
.I2(ain_5_IBUF_10),
.I3(ain_13_IBUF_3),
.O(Mmux_yout1222)
);
LUT6 #(
.INIT ( 64'hAABAAAAAAAAAAAAA ))
Mmux_yout113 (
.I0(Mmux_yout11),
.I1(bin_4_IBUF_16),
.I2(bin_2_IBUF_18),
.I3(rotate_IBUF_21),
.I4(ain_15_IBUF_15),
.I5(sra_IBUF_22),
.O(Mmux_yout112_108)
);
MUXF7 Mmux_yout12243 (
.I0(N14),
.I1(N15),
.S(bin_2_IBUF_18),
.O(Mmux_yout1224)
);
LUT5 #(
.INIT ( 32'hBE0E8202 ))
Mmux_yout12243_F (
.I0(ain_3_IBUF_6),
.I1(b[3]),
.I2(bin_4_IBUF_16),
.I3(rotate_IBUF_21),
.I4(ain_11_IBUF_7),
.O(N14)
);
LUT5 #(
.INIT ( 32'hBE0E8202 ))
Mmux_yout12243_G (
.I0(ain_7_IBUF_14),
.I1(b[3]),
.I2(bin_4_IBUF_16),
.I3(rotate_IBUF_21),
.I4(ain_15_IBUF_15),
.O(N15)
);
MUXF7 Mmux_yout11123 (
.I0(N16),
.I1(N17),
.S(bin_2_IBUF_18),
.O(Mmux_yout1112)
);
LUT6 #(
.INIT ( 64'hF7D5D5D5A2808080 ))
Mmux_yout11123_F (
.I0(bin_4_IBUF_16),
.I1(bin_3_IBUF_17),
.I2(ain_7_IBUF_14),
.I3(ain_15_IBUF_15),
.I4(rotate_IBUF_21),
.I5(\b<3>_mmx_out7 ),
.O(N16)
);
LUT6 #(
.INIT ( 64'hFD75FD75FC30A820 ))
Mmux_yout11123_G (
.I0(bin_4_IBUF_16),
.I1(bin_3_IBUF_17),
.I2(ain_3_IBUF_6),
.I3(ain_11_IBUF_7),
.I4(rotate_IBUF_21),
.I5(Mmux_yout911),
.O(N17)
);
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
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