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// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 18:54:09 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_led_controller_0_0_stub.v
// Design : ip_design_led_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "led_controller_v1_0,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(LEDs_out, s00_axi_awaddr, s00_axi_awprot,
s00_axi_awvalid, s00_axi_awready, s00_axi_wdata, s00_axi_wstrb, s00_axi_wvalid,
s00_axi_wready, s00_axi_bresp, s00_axi_bvalid, s00_axi_bready, s00_axi_araddr,
s00_axi_arprot, s00_axi_arvalid, s00_axi_arready, s00_axi_rdata, s00_axi_rresp,
s00_axi_rvalid, s00_axi_rready, s00_axi_aclk, s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output [7:0]LEDs_out;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
/*
=========================================================================================================================
| Verilog module for driving a half-bridge (HB) conveter topology in digital current mode control. |
| |
| Theory of operation: This module is very similar to a duty cycle mode controlled HB. |
| In a nutshell, the high side FET is turned on. The inductor current rises, and a comparator |
| on the board itself flips when the inductor current reaches a preset reference. This is accomplished |
| by using high-side current sense resistor and some isolation circuitry. When the comparator (cmp) flips high, |
| a flag is set. The high side is then turned off, a counter clocks the dead time, and the low side FET |
| is turned on for the remainder of the switching period. |
| |
| Inputs/Outputs: |
| clk: FPGA system clock input. |
| cmp: The high-side current sense comparator input. |
| DT: Dead time in sysclk ticks. |
| MaxCount: the length of a switching period in sysclk ticks. |
| High: Hide side MOSFET gate drive signal. |
| Low: Low side MOSFET gate drive signal. |
=========================================================================================================================
*/
`timescale 1ns/1ps
`define minDuty 10
`define offTime 5
module PeakCurrentHB(clk, cmp, DT, MaxCount, High, Low);
//Inputs and outputs
input clk, cmp;
input [7:0] DT, MaxCount;
output reg High, Low;
//Internal variables
reg [7:0] Counter = 0;
reg [7:0] DTCount = 0;
reg [7:0] MaxDuty = 0;
reg Flag;
//Wires
wire [7:0] Counter_Next, DTCount_Next, MaxDuty_Next;
wire High_Next, Low_Next, Flag_Next;
//For simulation purposes only
initial begin
High = 0;
Low = 1;
end
//Sequential Code
always @ (posedge(clk))
begin
Counter <= Counter_Next;
High <= High_Next;
Low <= Low_Next;
Flag <= Flag_Next;
MaxDuty <= MaxDuty_Next;
end
//Clock the dead time counter on the flag edge
always @ (negedge(High))
begin
DTCount <= DTCount_Next;
end
//Combinatorial Code
assign Flag_Next = (Counter == 8'b00000000)?0:(cmp || Flag);
assign Counter_Next = (Counter < MaxCount)?(Counter+1):0;
assign High_Next = (Counter >= DT) && (!Flag) && (Counter < MaxDuty);
assign Low_Next = ((Flag) && (Counter > DTCount)) || ((!High) && (Counter > MaxDuty) && (Counter >= DTCount));
assign DTCount_Next = Counter + DT;
assign MaxDuty_Next = (MaxCount >> 1) - 1;
endmodule
|
`include "mem_beh.v"
`include "regfile_beh.v"
`include "components.v"
`include "control_units.v"
`include "alu_beh.v"
`include "mux2to1_beh.v"
module kustar;
reg clock, clear;
wire [31:0] MuxtoPC, PCtoMux, MuxtoMem, MemtoInstReg, SigntoShift, ShifttoMux, MemdatatoMux, MuxtoWriteData;
wire [31:0] RegtoA, RegtoB, AtoMux, BtoMux, AMuxtoALU, BMuxtoALU, ALUtoALUOut, ALUOuttoMux , ShifttoConcat, ConcattoMux;
wire Zero;
wire [5:0] Op ;
wire [4:0] Rs, Rt, MuxtoWriteReg;
wire [15:0] AddrorConst ;
wire PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, ALUSrcA, RegWrite, RegDst;
wire [1:0] PCSource, ALUOp, ALUSrcB;
wire [2:0] ALUcontrol;
reg [31:0] four;
reg yesItAlwaysTure;
reg yesItAlwyasFalse;
reg [31:0] unused;
single_register PC (MuxtoPC, PCtoMux, clock, clear, (Zero&PCWriteCond)|PCWrite);
mux2to1 PostPCMux (PCtoMux, ALUOuttoMux, MuxtoMem, IorD);
mem Memory (MuxtoMem, RegtoB, MemtoInstReg, MemWrite, MemRead, clock);
single_register InstReg (MemtoInstReg, {Op[5:0], Rs[4:0], Rt[4:0], AddrorConst[15:0]}, clock, clear, IRWrite);
single_register MemDataReg (MemtoInstReg, MemdatatoMux, clock, clear, MemRead);
mux2to1for5bit WriteRegMux (Rt, AddrorConst[15:11], MuxtoWriteReg, RegDst);
mux2to1 PreWriteDataMux (ALUOuttoMux, MemdatatoMux, MuxtoWriteData, MemtoReg);
registerfile Registers (Rs, RegtoA, Rt, RegtoB, MuxtoWriteReg, MuxtoWriteData, clock, yesItAlwyasFalse, RegWrite);
signextd SignExtend (AddrorConst, SigntoShift);
shiftleft2 ShiftSign (SigntoShift, ShifttoMux);
mux2to1 AMux (PCtoMux, RegtoA, AMuxtoALU, ALUSrcA);
mux4to1 BMux (RegtoB, four, SigntoShift, ShifttoMux, BMuxtoALU, ALUSrcB);
ALU YesThisIsALU (AMuxtoALU, BMuxtoALU, ALUcontrol, ALUtoALUOut, Zero);
single_register ALUOut (ALUtoALUOut, ALUOuttoMux, clock, clear, yesItAlwaysTure);
shiftleft2 PCShift ({Op[5:0], Rs[4:0], Rt[4:0], AddrorConst[15:0]}, ShifttoConcat);
concatenate4to28 PCConcat (ShifttoConcat, PCtoMux, ConcattoMux);
mux4to1 PCMux (ALUtoALUOut, ALUOuttoMux, ConcattoMux, unused, MuxtoPC, PCSource);
mcu YesThisIsMCU (clock, clear, Op, PCWriteCond,
PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, PCSource, ALUOp, ALUSrcB, ALUSrcA, RegWrite, RegDst);
acu YesThisIsACU (AddrorConst[5:0], ALUOp, ALUcontrol);
/*
module acu(funct, ALUOp, ALUcontrol);
input [5:0] funct;
input [1:0] ALUOp;
output [2:0] ALUcontrol;
-------------------------------------------------------
module mcu(clk, clr, OP, PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, PCSource, ALUOp, ALUSrcB, ALUSrcA, RegWrite, RegDst);
input clk, clr;
input [5:0] OP;
output PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, ALUSrcA, RegWrite, RegDst;
output [1:0] PCSource, ALUOp, ALUSrcB;
-------------------------------------------------------------
// concatenate pcin[31-28] with datain[27-0] to form a jump address
module concatenate4to28(datain, pcin, pcout);
input [31:0] datain, pcin;
output [31:0] pcout;
-------------------------------------------------------------
module ALU(inputA, inputB, ALUop, result, zero);
input [31:0] inputA, inputB;
input [2:0] ALUop;
output [31:0] result;
output zero;
---------------------------------------------------------------
module mux4to1(datain0, datain1, datain2, datain3, dataout, select);
input [31:0] datain0, datain1, datain2, datain3;
input[1:0] select;
output [31:0] dataout;
-------------------------------------------
module shiftleft2(datain, dataout);
input [31:0] datain;
output [31:0] dataout;
-----------------------------------------------------------
module signextd(datain, dataout);
input [15:0] datain;
output [31:0] dataout;
------------------------------------------------------------
module registerfile(ADDA, DATAA, ADDB, DATAB, ADDC, DATAC, clk, clr, WE);
input [4:0] ADDA,ADDB, ADDC;
input [31:0] DATAC;
input clk, clr, WE;
output [31:0] DATAA, DATAB;
---------------------------------------------
module single_register(datain, dataout, clk, clr, WE);
input [31:0] datain;
output [31:0] dataout;
input clk, clr, WE;
----------------
module mem(addr,datain,dataout, MemWrite, MemRead, clk);
input clk;
input [31:0] addr, datain;
output [31:0] dataout;
input MemWrite, MemRead;
------------------------------
module mux2to1(datain0,datain1, dataout, select);
input [31:0] datain0, datain1;
input select;
output [31:0] dataout;
*/
initial
forever #50 clock = ~clock;
initial
begin
four = 4;
yesItAlwaysTure = 1;
yesItAlwyasFalse = 0;
clock = 0;
clear = 1;
/* we may not connect clear to register file and memory because we don't want our initial data get cleared*/
#10 clear = 0;
end
initial
#10000 $stop;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 07:03:52 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0_1/system_ov7670_controller_0_0_sim_netlist.v
// Design : system_ov7670_controller_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_ov7670_controller_0_0,ov7670_controller,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_controller,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_ov7670_controller_0_0
(clk,
resend,
config_finished,
sioc,
siod,
reset,
pwdn,
xclk);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input resend;
output config_finished;
output sioc;
inout siod;
(* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) output reset;
output pwdn;
output xclk;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire config_finished;
wire resend;
wire sioc;
wire siod;
wire xclk;
assign pwdn = \<const0> ;
assign reset = \<const1> ;
GND GND
(.G(\<const0> ));
system_ov7670_controller_0_0_ov7670_controller U0
(.clk(clk),
.config_finished(config_finished),
.resend(resend),
.sioc(sioc),
.siod(siod),
.xclk(xclk));
VCC VCC
(.P(\<const1> ));
endmodule
(* ORIG_REF_NAME = "i2c_sender" *)
module system_ov7670_controller_0_0_i2c_sender
(E,
sioc,
p_0_in,
\busy_sr_reg[1]_0 ,
siod,
\busy_sr_reg[31]_0 ,
clk,
p_1_in,
DOADO,
\busy_sr_reg[31]_1 );
output [0:0]E;
output sioc;
output p_0_in;
output \busy_sr_reg[1]_0 ;
output siod;
input \busy_sr_reg[31]_0 ;
input clk;
input [0:0]p_1_in;
input [15:0]DOADO;
input [0:0]\busy_sr_reg[31]_1 ;
wire [15:0]DOADO;
wire [0:0]E;
wire busy_sr0;
wire \busy_sr[0]_i_3_n_0 ;
wire \busy_sr[0]_i_5_n_0 ;
wire \busy_sr[10]_i_1_n_0 ;
wire \busy_sr[11]_i_1_n_0 ;
wire \busy_sr[12]_i_1_n_0 ;
wire \busy_sr[13]_i_1_n_0 ;
wire \busy_sr[14]_i_1_n_0 ;
wire \busy_sr[15]_i_1_n_0 ;
wire \busy_sr[16]_i_1_n_0 ;
wire \busy_sr[17]_i_1_n_0 ;
wire \busy_sr[18]_i_1_n_0 ;
wire \busy_sr[19]_i_1_n_0 ;
wire \busy_sr[1]_i_1_n_0 ;
wire \busy_sr[20]_i_1_n_0 ;
wire \busy_sr[21]_i_1_n_0 ;
wire \busy_sr[22]_i_1_n_0 ;
wire \busy_sr[23]_i_1_n_0 ;
wire \busy_sr[24]_i_1_n_0 ;
wire \busy_sr[25]_i_1_n_0 ;
wire \busy_sr[26]_i_1_n_0 ;
wire \busy_sr[27]_i_1_n_0 ;
wire \busy_sr[28]_i_1_n_0 ;
wire \busy_sr[29]_i_1_n_0 ;
wire \busy_sr[2]_i_1_n_0 ;
wire \busy_sr[30]_i_1_n_0 ;
wire \busy_sr[31]_i_1_n_0 ;
wire \busy_sr[31]_i_2_n_0 ;
wire \busy_sr[3]_i_1_n_0 ;
wire \busy_sr[4]_i_1_n_0 ;
wire \busy_sr[5]_i_1_n_0 ;
wire \busy_sr[6]_i_1_n_0 ;
wire \busy_sr[7]_i_1_n_0 ;
wire \busy_sr[8]_i_1_n_0 ;
wire \busy_sr[9]_i_1_n_0 ;
wire \busy_sr_reg[1]_0 ;
wire \busy_sr_reg[31]_0 ;
wire [0:0]\busy_sr_reg[31]_1 ;
wire \busy_sr_reg_n_0_[0] ;
wire \busy_sr_reg_n_0_[10] ;
wire \busy_sr_reg_n_0_[11] ;
wire \busy_sr_reg_n_0_[12] ;
wire \busy_sr_reg_n_0_[13] ;
wire \busy_sr_reg_n_0_[14] ;
wire \busy_sr_reg_n_0_[15] ;
wire \busy_sr_reg_n_0_[16] ;
wire \busy_sr_reg_n_0_[17] ;
wire \busy_sr_reg_n_0_[18] ;
wire \busy_sr_reg_n_0_[1] ;
wire \busy_sr_reg_n_0_[21] ;
wire \busy_sr_reg_n_0_[22] ;
wire \busy_sr_reg_n_0_[23] ;
wire \busy_sr_reg_n_0_[24] ;
wire \busy_sr_reg_n_0_[25] ;
wire \busy_sr_reg_n_0_[26] ;
wire \busy_sr_reg_n_0_[27] ;
wire \busy_sr_reg_n_0_[28] ;
wire \busy_sr_reg_n_0_[29] ;
wire \busy_sr_reg_n_0_[2] ;
wire \busy_sr_reg_n_0_[30] ;
wire \busy_sr_reg_n_0_[3] ;
wire \busy_sr_reg_n_0_[4] ;
wire \busy_sr_reg_n_0_[5] ;
wire \busy_sr_reg_n_0_[6] ;
wire \busy_sr_reg_n_0_[7] ;
wire \busy_sr_reg_n_0_[8] ;
wire \busy_sr_reg_n_0_[9] ;
wire clk;
wire \data_sr[10]_i_1_n_0 ;
wire \data_sr[12]_i_1_n_0 ;
wire \data_sr[13]_i_1_n_0 ;
wire \data_sr[14]_i_1_n_0 ;
wire \data_sr[15]_i_1_n_0 ;
wire \data_sr[16]_i_1_n_0 ;
wire \data_sr[17]_i_1_n_0 ;
wire \data_sr[18]_i_1_n_0 ;
wire \data_sr[19]_i_1_n_0 ;
wire \data_sr[22]_i_1_n_0 ;
wire \data_sr[27]_i_1_n_0 ;
wire \data_sr[30]_i_1_n_0 ;
wire \data_sr[31]_i_1_n_0 ;
wire \data_sr[31]_i_2_n_0 ;
wire \data_sr[3]_i_1_n_0 ;
wire \data_sr[4]_i_1_n_0 ;
wire \data_sr[5]_i_1_n_0 ;
wire \data_sr[6]_i_1_n_0 ;
wire \data_sr[7]_i_1_n_0 ;
wire \data_sr[8]_i_1_n_0 ;
wire \data_sr[9]_i_1_n_0 ;
wire \data_sr_reg_n_0_[10] ;
wire \data_sr_reg_n_0_[11] ;
wire \data_sr_reg_n_0_[12] ;
wire \data_sr_reg_n_0_[13] ;
wire \data_sr_reg_n_0_[14] ;
wire \data_sr_reg_n_0_[15] ;
wire \data_sr_reg_n_0_[16] ;
wire \data_sr_reg_n_0_[17] ;
wire \data_sr_reg_n_0_[18] ;
wire \data_sr_reg_n_0_[19] ;
wire \data_sr_reg_n_0_[1] ;
wire \data_sr_reg_n_0_[20] ;
wire \data_sr_reg_n_0_[21] ;
wire \data_sr_reg_n_0_[22] ;
wire \data_sr_reg_n_0_[23] ;
wire \data_sr_reg_n_0_[24] ;
wire \data_sr_reg_n_0_[25] ;
wire \data_sr_reg_n_0_[26] ;
wire \data_sr_reg_n_0_[27] ;
wire \data_sr_reg_n_0_[28] ;
wire \data_sr_reg_n_0_[29] ;
wire \data_sr_reg_n_0_[2] ;
wire \data_sr_reg_n_0_[30] ;
wire \data_sr_reg_n_0_[31] ;
wire \data_sr_reg_n_0_[3] ;
wire \data_sr_reg_n_0_[4] ;
wire \data_sr_reg_n_0_[5] ;
wire \data_sr_reg_n_0_[6] ;
wire \data_sr_reg_n_0_[7] ;
wire \data_sr_reg_n_0_[8] ;
wire \data_sr_reg_n_0_[9] ;
wire [7:6]divider_reg__0;
wire [5:0]divider_reg__1;
wire p_0_in;
wire [7:0]p_0_in__0;
wire [0:0]p_1_in;
wire [1:0]p_1_in_0;
wire sioc;
wire sioc_i_1_n_0;
wire sioc_i_2_n_0;
wire sioc_i_3_n_0;
wire sioc_i_4_n_0;
wire sioc_i_5_n_0;
wire siod;
wire siod_INST_0_i_1_n_0;
LUT6 #(
.INIT(64'h4000FFFF40004000))
\busy_sr[0]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.I2(divider_reg__0[7]),
.I3(p_0_in),
.I4(\busy_sr_reg[1]_0 ),
.I5(p_1_in),
.O(busy_sr0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\busy_sr[0]_i_3
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(\busy_sr[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\busy_sr[0]_i_4
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[3]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(\busy_sr[0]_i_5_n_0 ),
.O(\busy_sr_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFFFE))
\busy_sr[0]_i_5
(.I0(divider_reg__1[5]),
.I1(divider_reg__1[4]),
.I2(divider_reg__0[7]),
.I3(divider_reg__0[6]),
.O(\busy_sr[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[10]_i_1
(.I0(\busy_sr_reg_n_0_[9] ),
.I1(p_0_in),
.O(\busy_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[11]_i_1
(.I0(\busy_sr_reg_n_0_[10] ),
.I1(p_0_in),
.O(\busy_sr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[12]_i_1
(.I0(\busy_sr_reg_n_0_[11] ),
.I1(p_0_in),
.O(\busy_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[13]_i_1
(.I0(\busy_sr_reg_n_0_[12] ),
.I1(p_0_in),
.O(\busy_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[14]_i_1
(.I0(\busy_sr_reg_n_0_[13] ),
.I1(p_0_in),
.O(\busy_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[15]_i_1
(.I0(\busy_sr_reg_n_0_[14] ),
.I1(p_0_in),
.O(\busy_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[16]_i_1
(.I0(\busy_sr_reg_n_0_[15] ),
.I1(p_0_in),
.O(\busy_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[17]_i_1
(.I0(\busy_sr_reg_n_0_[16] ),
.I1(p_0_in),
.O(\busy_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[18]_i_1
(.I0(\busy_sr_reg_n_0_[17] ),
.I1(p_0_in),
.O(\busy_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[19]_i_1
(.I0(\busy_sr_reg_n_0_[18] ),
.I1(p_0_in),
.O(\busy_sr[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[1]_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(p_0_in),
.O(\busy_sr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[20]_i_1
(.I0(p_1_in_0[0]),
.I1(p_0_in),
.O(\busy_sr[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[21]_i_1
(.I0(p_1_in_0[1]),
.I1(p_0_in),
.O(\busy_sr[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[22]_i_1
(.I0(\busy_sr_reg_n_0_[21] ),
.I1(p_0_in),
.O(\busy_sr[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[23]_i_1
(.I0(\busy_sr_reg_n_0_[22] ),
.I1(p_0_in),
.O(\busy_sr[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[24]_i_1
(.I0(\busy_sr_reg_n_0_[23] ),
.I1(p_0_in),
.O(\busy_sr[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[25]_i_1
(.I0(\busy_sr_reg_n_0_[24] ),
.I1(p_0_in),
.O(\busy_sr[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[26]_i_1
(.I0(\busy_sr_reg_n_0_[25] ),
.I1(p_0_in),
.O(\busy_sr[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[27]_i_1
(.I0(\busy_sr_reg_n_0_[26] ),
.I1(p_0_in),
.O(\busy_sr[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[28]_i_1
(.I0(\busy_sr_reg_n_0_[27] ),
.I1(p_0_in),
.O(\busy_sr[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[29]_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(p_0_in),
.O(\busy_sr[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[2]_i_1
(.I0(\busy_sr_reg_n_0_[1] ),
.I1(p_0_in),
.O(\busy_sr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[30]_i_1
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(p_0_in),
.O(\busy_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h22222222A2222222))
\busy_sr[31]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.I3(divider_reg__0[7]),
.I4(divider_reg__0[6]),
.I5(\busy_sr[0]_i_3_n_0 ),
.O(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[31]_i_2
(.I0(p_0_in),
.I1(\busy_sr_reg_n_0_[30] ),
.O(\busy_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[3]_i_1
(.I0(\busy_sr_reg_n_0_[2] ),
.I1(p_0_in),
.O(\busy_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[4]_i_1
(.I0(\busy_sr_reg_n_0_[3] ),
.I1(p_0_in),
.O(\busy_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[5]_i_1
(.I0(\busy_sr_reg_n_0_[4] ),
.I1(p_0_in),
.O(\busy_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[6]_i_1
(.I0(\busy_sr_reg_n_0_[5] ),
.I1(p_0_in),
.O(\busy_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[7]_i_1
(.I0(\busy_sr_reg_n_0_[6] ),
.I1(p_0_in),
.O(\busy_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[8]_i_1
(.I0(\busy_sr_reg_n_0_[7] ),
.I1(p_0_in),
.O(\busy_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[9]_i_1
(.I0(\busy_sr_reg_n_0_[8] ),
.I1(p_0_in),
.O(\busy_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\busy_sr_reg[0]
(.C(clk),
.CE(busy_sr0),
.D(p_1_in),
.Q(\busy_sr_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[10]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[10] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[11]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[11] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[12]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[12] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[13]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[13] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[14]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[14] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[15]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[15] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[16]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[16] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[17]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[17] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[18]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[18] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[19]_i_1_n_0 ),
.Q(p_1_in_0[0]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[1]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[1] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[20]_i_1_n_0 ),
.Q(p_1_in_0[1]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[21]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[21] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[22]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[22]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[22] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[23]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[23] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[24]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[24] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[25]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[25] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[26]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[26] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[27]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[27]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[27] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[28]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[28] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[29]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[29] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[2]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[2] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[30]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[30] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[31]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[31]_i_2_n_0 ),
.Q(p_0_in),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[3]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[3] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[4]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[4] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[5]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[5] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[6]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[6] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[7]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[7] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[8]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[8] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[9]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[9] ),
.S(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[10]_i_1
(.I0(\data_sr_reg_n_0_[9] ),
.I1(p_0_in),
.I2(DOADO[7]),
.O(\data_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[12]_i_1
(.I0(\data_sr_reg_n_0_[11] ),
.I1(p_0_in),
.I2(DOADO[8]),
.O(\data_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[13]_i_1
(.I0(\data_sr_reg_n_0_[12] ),
.I1(p_0_in),
.I2(DOADO[9]),
.O(\data_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[14]_i_1
(.I0(\data_sr_reg_n_0_[13] ),
.I1(p_0_in),
.I2(DOADO[10]),
.O(\data_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[15]_i_1
(.I0(\data_sr_reg_n_0_[14] ),
.I1(p_0_in),
.I2(DOADO[11]),
.O(\data_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[16]_i_1
(.I0(\data_sr_reg_n_0_[15] ),
.I1(p_0_in),
.I2(DOADO[12]),
.O(\data_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[17]_i_1
(.I0(\data_sr_reg_n_0_[16] ),
.I1(p_0_in),
.I2(DOADO[13]),
.O(\data_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[18]_i_1
(.I0(\data_sr_reg_n_0_[17] ),
.I1(p_0_in),
.I2(DOADO[14]),
.O(\data_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[19]_i_1
(.I0(\data_sr_reg_n_0_[18] ),
.I1(p_0_in),
.I2(DOADO[15]),
.O(\data_sr[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[22]_i_1
(.I0(\data_sr_reg_n_0_[22] ),
.I1(\data_sr_reg_n_0_[21] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[27]_i_1
(.I0(\data_sr_reg_n_0_[27] ),
.I1(\data_sr_reg_n_0_[26] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[27]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\data_sr[30]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.O(\data_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[31]_i_1
(.I0(\data_sr_reg_n_0_[31] ),
.I1(\data_sr_reg_n_0_[30] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\data_sr[31]_i_2
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(\data_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[3]_i_1
(.I0(\data_sr_reg_n_0_[2] ),
.I1(p_0_in),
.I2(DOADO[0]),
.O(\data_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[4]_i_1
(.I0(\data_sr_reg_n_0_[3] ),
.I1(p_0_in),
.I2(DOADO[1]),
.O(\data_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[5]_i_1
(.I0(\data_sr_reg_n_0_[4] ),
.I1(p_0_in),
.I2(DOADO[2]),
.O(\data_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[6]_i_1
(.I0(\data_sr_reg_n_0_[5] ),
.I1(p_0_in),
.I2(DOADO[3]),
.O(\data_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[7]_i_1
(.I0(\data_sr_reg_n_0_[6] ),
.I1(p_0_in),
.I2(DOADO[4]),
.O(\data_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[8]_i_1
(.I0(\data_sr_reg_n_0_[7] ),
.I1(p_0_in),
.I2(DOADO[5]),
.O(\data_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[9]_i_1
(.I0(\data_sr_reg_n_0_[8] ),
.I1(p_0_in),
.I2(DOADO[6]),
.O(\data_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[10]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[10] ),
.Q(\data_sr_reg_n_0_[11] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[12]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[13]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[14]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[15]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[16]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[16] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[17]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[17] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[18]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[18] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[19]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[19] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(p_0_in),
.Q(\data_sr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[19] ),
.Q(\data_sr_reg_n_0_[20] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[20] ),
.Q(\data_sr_reg_n_0_[21] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[22]
(.C(clk),
.CE(1'b1),
.D(\data_sr[22]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[22] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[22] ),
.Q(\data_sr_reg_n_0_[23] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[23] ),
.Q(\data_sr_reg_n_0_[24] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[24] ),
.Q(\data_sr_reg_n_0_[25] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[25] ),
.Q(\data_sr_reg_n_0_[26] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[27]
(.C(clk),
.CE(1'b1),
.D(\data_sr[27]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[27] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[27] ),
.Q(\data_sr_reg_n_0_[28] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[28] ),
.Q(\data_sr_reg_n_0_[29] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[1] ),
.Q(\data_sr_reg_n_0_[2] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[29] ),
.Q(\data_sr_reg_n_0_[30] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[31]
(.C(clk),
.CE(1'b1),
.D(\data_sr[31]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[31] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[3]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[4]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[5]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[6]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[7]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[8]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[9]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT1 #(
.INIT(2'h1))
\divider[0]_i_1
(.I0(divider_reg__1[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\divider[1]_i_1
(.I0(divider_reg__1[0]),
.I1(divider_reg__1[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\divider[2]_i_1
(.I0(divider_reg__1[1]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[2]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\divider[3]_i_1
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[1]),
.I3(divider_reg__1[3]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\divider[4]_i_1
(.I0(divider_reg__1[3]),
.I1(divider_reg__1[1]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[2]),
.I4(divider_reg__1[4]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\divider[5]_i_1
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(p_0_in__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\divider[6]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hD2))
\divider[7]_i_2
(.I0(divider_reg__0[6]),
.I1(\busy_sr[0]_i_3_n_0 ),
.I2(divider_reg__0[7]),
.O(p_0_in__0[7]));
FDRE #(
.INIT(1'b1))
\divider_reg[0]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[0]),
.Q(divider_reg__1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[1]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[1]),
.Q(divider_reg__1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[2]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[2]),
.Q(divider_reg__1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[3]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[3]),
.Q(divider_reg__1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[4]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[4]),
.Q(divider_reg__1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[5]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[5]),
.Q(divider_reg__1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[6]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[6]),
.Q(divider_reg__0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[7]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[7]),
.Q(divider_reg__0[7]),
.R(1'b0));
LUT6 #(
.INIT(64'hFCFCFFF8FFFFFFFF))
sioc_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(sioc_i_2_n_0),
.I2(sioc_i_3_n_0),
.I3(\busy_sr_reg_n_0_[1] ),
.I4(sioc_i_4_n_0),
.I5(p_0_in),
.O(sioc_i_1_n_0));
LUT2 #(
.INIT(4'h6))
sioc_i_2
(.I0(divider_reg__0[6]),
.I1(divider_reg__0[7]),
.O(sioc_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hA222))
sioc_i_3
(.I0(sioc_i_5_n_0),
.I1(\busy_sr_reg_n_0_[30] ),
.I2(divider_reg__0[6]),
.I3(p_0_in),
.O(sioc_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7FFF))
sioc_i_4
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(\busy_sr_reg_n_0_[2] ),
.I2(p_0_in),
.I3(\busy_sr_reg_n_0_[30] ),
.O(sioc_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
sioc_i_5
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(\busy_sr_reg_n_0_[1] ),
.I2(\busy_sr_reg_n_0_[29] ),
.I3(\busy_sr_reg_n_0_[2] ),
.O(sioc_i_5_n_0));
FDRE sioc_reg
(.C(clk),
.CE(1'b1),
.D(sioc_i_1_n_0),
.Q(sioc),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
siod_INST_0
(.I0(\data_sr_reg_n_0_[31] ),
.I1(siod_INST_0_i_1_n_0),
.O(siod));
LUT6 #(
.INIT(64'hB0BBB0BB0000B0BB))
siod_INST_0_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(\busy_sr_reg_n_0_[29] ),
.I2(p_1_in_0[0]),
.I3(p_1_in_0[1]),
.I4(\busy_sr_reg_n_0_[11] ),
.I5(\busy_sr_reg_n_0_[10] ),
.O(siod_INST_0_i_1_n_0));
FDRE taken_reg
(.C(clk),
.CE(1'b1),
.D(\busy_sr_reg[31]_0 ),
.Q(E),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "ov7670_controller" *)
module system_ov7670_controller_0_0_ov7670_controller
(config_finished,
siod,
xclk,
sioc,
resend,
clk);
output config_finished;
output siod;
output xclk;
output sioc;
input resend;
input clk;
wire Inst_i2c_sender_n_3;
wire Inst_ov7670_registers_n_16;
wire Inst_ov7670_registers_n_18;
wire clk;
wire config_finished;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire sioc;
wire siod;
wire [15:0]sreg_reg;
wire sys_clk_i_1_n_0;
wire taken;
wire xclk;
system_ov7670_controller_0_0_i2c_sender Inst_i2c_sender
(.DOADO(sreg_reg),
.E(taken),
.\busy_sr_reg[1]_0 (Inst_i2c_sender_n_3),
.\busy_sr_reg[31]_0 (Inst_ov7670_registers_n_18),
.\busy_sr_reg[31]_1 (Inst_ov7670_registers_n_16),
.clk(clk),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.sioc(sioc),
.siod(siod));
system_ov7670_controller_0_0_ov7670_registers Inst_ov7670_registers
(.DOADO(sreg_reg),
.E(taken),
.clk(clk),
.config_finished(config_finished),
.\divider_reg[2] (Inst_i2c_sender_n_3),
.\divider_reg[7] (Inst_ov7670_registers_n_16),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.resend(resend),
.taken_reg(Inst_ov7670_registers_n_18));
LUT1 #(
.INIT(2'h1))
sys_clk_i_1
(.I0(xclk),
.O(sys_clk_i_1_n_0));
FDRE #(
.INIT(1'b0))
sys_clk_reg
(.C(clk),
.CE(1'b1),
.D(sys_clk_i_1_n_0),
.Q(xclk),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "ov7670_registers" *)
module system_ov7670_controller_0_0_ov7670_registers
(DOADO,
\divider_reg[7] ,
config_finished,
taken_reg,
p_1_in,
clk,
\divider_reg[2] ,
p_0_in,
resend,
E);
output [15:0]DOADO;
output [0:0]\divider_reg[7] ;
output config_finished;
output taken_reg;
output [0:0]p_1_in;
input clk;
input \divider_reg[2] ;
input p_0_in;
input resend;
input [0:0]E;
wire [15:0]DOADO;
wire [0:0]E;
wire [7:0]address;
wire [7:0]address_reg__0;
wire \address_rep[0]_i_1_n_0 ;
wire \address_rep[1]_i_1_n_0 ;
wire \address_rep[2]_i_1_n_0 ;
wire \address_rep[3]_i_1_n_0 ;
wire \address_rep[4]_i_1_n_0 ;
wire \address_rep[5]_i_1_n_0 ;
wire \address_rep[6]_i_1_n_0 ;
wire \address_rep[7]_i_1_n_0 ;
wire \address_rep[7]_i_2_n_0 ;
wire clk;
wire config_finished;
wire config_finished_INST_0_i_1_n_0;
wire config_finished_INST_0_i_2_n_0;
wire config_finished_INST_0_i_3_n_0;
wire config_finished_INST_0_i_4_n_0;
wire \divider_reg[2] ;
wire [0:0]\divider_reg[7] ;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire taken_reg;
wire [15:0]NLW_sreg_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPBDOP_UNCONNECTED;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address_reg__0[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address_reg__0[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address_reg__0[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address_reg__0[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address_reg__0[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address_reg__0[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address_reg__0[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address_reg__0[7]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address[7]),
.R(resend));
LUT1 #(
.INIT(2'h1))
\address_rep[0]_i_1
(.I0(address_reg__0[0]),
.O(\address_rep[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h6))
\address_rep[1]_i_1
(.I0(address_reg__0[0]),
.I1(address_reg__0[1]),
.O(\address_rep[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h78))
\address_rep[2]_i_1
(.I0(address_reg__0[1]),
.I1(address_reg__0[0]),
.I2(address_reg__0[2]),
.O(\address_rep[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h7F80))
\address_rep[3]_i_1
(.I0(address_reg__0[2]),
.I1(address_reg__0[0]),
.I2(address_reg__0[1]),
.I3(address_reg__0[3]),
.O(\address_rep[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h7FFF8000))
\address_rep[4]_i_1
(.I0(address_reg__0[3]),
.I1(address_reg__0[1]),
.I2(address_reg__0[0]),
.I3(address_reg__0[2]),
.I4(address_reg__0[4]),
.O(\address_rep[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\address_rep[5]_i_1
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h9))
\address_rep[6]_i_1
(.I0(\address_rep[7]_i_2_n_0 ),
.I1(address_reg__0[6]),
.O(\address_rep[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hD2))
\address_rep[7]_i_1
(.I0(address_reg__0[6]),
.I1(\address_rep[7]_i_2_n_0 ),
.I2(address_reg__0[7]),
.O(\address_rep[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\address_rep[7]_i_2
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h0000FFFE))
\busy_sr[0]_i_2
(.I0(config_finished_INST_0_i_4_n_0),
.I1(config_finished_INST_0_i_3_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_1_n_0),
.I4(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0001))
config_finished_INST_0
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.O(config_finished));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_1
(.I0(DOADO[5]),
.I1(DOADO[4]),
.I2(DOADO[7]),
.I3(DOADO[6]),
.O(config_finished_INST_0_i_1_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_2
(.I0(DOADO[1]),
.I1(DOADO[0]),
.I2(DOADO[3]),
.I3(DOADO[2]),
.O(config_finished_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_3
(.I0(DOADO[13]),
.I1(DOADO[12]),
.I2(DOADO[15]),
.I3(DOADO[14]),
.O(config_finished_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_4
(.I0(DOADO[9]),
.I1(DOADO[8]),
.I2(DOADO[11]),
.I3(DOADO[10]),
.O(config_finished_INST_0_i_4_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\divider[7]_i_1
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.I4(\divider_reg[2] ),
.I5(p_0_in),
.O(\divider_reg[7] ));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "4096" *)
(* RTL_RAM_NAME = "U0/Inst_ov7670_registers/sreg" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "1023" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "15" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h53295217510C50344F4014383A04401004008C003E000C001100120412801280),
.INIT_01(256'h229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440),
.INIT_02(256'h90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
sreg_reg
(.ADDRARDADDR({1'b0,1'b0,address,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(clk),
.CLKBWRCLK(1'b0),
.DIADI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO(DOADO),
.DOBDO(NLW_sreg_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_sreg_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_sreg_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000055555554))
taken_i_1
(.I0(p_0_in),
.I1(config_finished_INST_0_i_1_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_3_n_0),
.I4(config_finished_INST_0_i_4_n_0),
.I5(\divider_reg[2] ),
.O(taken_reg));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module fifo_tb();
// Declarations/*{{{*/
// Slave side
reg s_aclk;
reg s_aresetn;
reg s_axis_tvalid;
wire s_axis_tready;
reg [63:0] s_axis_tdata;
reg [7:0] s_axis_tkeep;
reg s_axis_tlast;
// Master side
reg m_aclk;
wire m_aresetn;
wire m_axis_tvalid;
reg m_axis_tready;
wire [63:0] m_axis_tdata;
wire [7:0] m_axis_tkeep;
wire m_axis_tlast;
wire axis_overflow;
wire axis_underflow;
/*}}}*/
// FIFO module/*{{{*/
FIFO F0 (
.m_aclk(m_aclk), // input m_aclk
.s_aclk(s_aclk), // input s_aclk
.s_aresetn(s_aresetn), // input s_aresetn
.s_axis_tvalid(s_axis_tvalid), // input s_axis_tvalid
.s_axis_tready(s_axis_tready), // output s_axis_tready
.s_axis_tdata(s_axis_tdata), // input [63 : 0] s_axis_tdata
.s_axis_tkeep(s_axis_tkeep), // input [7 : 0] s_axis_tkeep
.s_axis_tlast(s_axis_tlast), // input s_axis_tlast
.m_axis_tvalid(m_axis_tvalid), // output m_axis_tvalid
.m_axis_tready(m_axis_tready), // input m_axis_tready
.m_axis_tdata(m_axis_tdata), // output [63 : 0] m_axis_tdata
.m_axis_tkeep(m_axis_tkeep), // output [7 : 0] m_axis_tkeep
.m_axis_tlast(m_axis_tlast), // output m_axis_tlast
.axis_overflow(axis_overflow), // output axis_overflow
.axis_underflow(axis_underflow) // output axis_underflow
);
/*}}}*/
// This is to ensure we simulate our reads from the slave end of the FIFO only
// when there is valid data to be read from the queue to avoid underflows.
always @(m_axis_tvalid) begin
m_axis_tready <= m_axis_tvalid;
end
// Testbench initialization/*{{{*/
initial begin
s_aclk <= 1'b0;
m_aclk <= 1'b0;
s_aresetn <= 1'b0;
s_axis_tvalid <= 1'b0;
m_axis_tready <= 1'b0;
s_axis_tdata <= 64'b0;
s_axis_tkeep <= 8'b0;
s_axis_tlast <= 1'b0;
end
/*}}}*/
// Master domain clock
initial begin
forever begin
#10 s_aclk <= ~s_aclk;
end
end
// Slave domain clock
initial begin
forever begin
#5 m_aclk <= ~m_aclk;
end
end
// Test bench stimuli/*{{{*/
initial begin
#10 s_aresetn <= 1'b1; // Slave will be ready 3 s_aclk ticks after reset
// Test writing a single data slice to the slave specifying valid bytes with tkeep
#60 s_axis_tvalid <= 1'b1; // Wait until slave is ready to avoid overflow
s_axis_tdata <= 64'hFFFFFFFFFFFFFFFF;
s_axis_tkeep <= 8'hCF;
s_axis_tlast <= 1'b1;
#20 s_axis_tvalid <= 1'b0; // Keep the valid signal asserted for at least 1 clock
s_axis_tdata <= 64'b0;
s_axis_tkeep <= 8'b0;
s_axis_tlast <= 1'b0;
// Test writing multiple data slices to the slave specifying valid bytes with tkeep and last slice with tlast
#20 s_axis_tvalid <= 1'b1; // Wait until slave is ready to avoid overflow
s_axis_tdata <= 64'h1111111111111111;
s_axis_tkeep <= 8'hFF;
#20 s_axis_tdata <= 64'h2222222222222222;
s_axis_tkeep <= 8'hFF;
#20 s_axis_tdata <= 64'h3333333333333333;
s_axis_tkeep <= 8'hFF;
#20 s_axis_tdata <= 64'h4444444444444444;
s_axis_tkeep <= 8'hFF;
s_axis_tlast <= 1'b1;
#20 s_axis_tvalid <= 1'b0;
s_axis_tdata <= 64'b0;
s_axis_tkeep <= 8'b0;
s_axis_tlast <= 1'b0;
end
/*}}}*/
endmodule
|
`timescale 1ns / 1ps
/*
Group Members: Kevin Ingram and Warren Seto
Lab Name: Traffic Light Controller (Lab 3)
Project Name: eng312_proj3
Design Name: Traffic_Test_D_eng312_proj3.v
Design Description: Verilog Test Bench to Implement Test D (11 AM)
*/
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire[4:0] count1;
wire[3:0] count2;
wire[1:0] count3;
// Counter Modules
nsCounter clock1(clk, count1); // Count a total of 32 seconds
ewCounter clock2(clk, count2); // Counts a total of 16 seconds
yellowCounter clock3(clk, count3); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (count1, count2, count3, NS_VEHICLE_DETECT, EW_VEHICLE_DETECT, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
always @ (clk) begin
if ($time % 6 == 0) begin
NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT;
end
if ($time % 15 == 0) begin
EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT;
end
end
endmodule
|
// Code generated by Icestudio 0.8.1w202112300112
`default_nettype none
//---- Top entity
module main #(
parameter v771499 = "v771499.list"
) (
input vclk,
output [3:0] v894180,
output [0:0] vinit
);
localparam p0 = v771499;
wire [0:7] w1;
wire [0:3] w2;
wire [0:7] w3;
wire w4;
assign v894180 = w2;
assign w4 = vclk;
v6809d2 #(
.v9298ae(p0)
) v60d27e (
.v6d8c97(w1),
.vc4e0ba(w3),
.v6dda25(w4)
);
vda0861 vf2b781 (
.vffb58f(w1)
);
v6bdcd9 v78e5a8 (
.v2cc41f(w2),
.vcc8c7c(w3)
);
assign vinit = 1'b0;
endmodule
//---- Top entity
module v6809d2 #(
parameter v9298ae = "v9298ae.list"
) (
input v6dda25,
input [7:0] v6d8c97,
output [7:0] vc4e0ba
);
localparam p3 = v9298ae;
wire w0;
wire w1;
wire w2;
wire w4;
wire w5;
wire w6;
wire w7;
wire [0:7] w8;
wire [0:7] w9;
wire w10;
wire [0:31] w11;
wire [0:31] w12;
wire [0:31] w13;
wire [0:31] w14;
wire [0:31] w15;
wire [0:3] w16;
wire w17;
wire w18;
wire w19;
assign w4 = v6dda25;
assign w5 = v6dda25;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign vc4e0ba = w8;
assign w9 = v6d8c97;
assign w1 = w0;
assign w5 = w4;
assign w6 = w4;
assign w6 = w5;
assign w7 = w4;
assign w7 = w5;
assign w7 = w6;
assign w12 = w11;
vf1cffe v468719 (
.ve9ba68(w0),
.v79476f(w1),
.v6dda25(w4),
.v27dec4(w10),
.v9231ba(w11),
.vfc9252(w13),
.va0e119(w14),
.ve17e80(w16)
);
vd30ca9 v16f275 (
.v9fb85f(w0)
);
v893ac6 #(
.vba98fe(p3)
) vc59f55 (
.v6dda25(w5),
.v5d7e06(w11),
.v9a5b8a(w15)
);
ve4c3a8 v29c9ed (
.v5c832d(w12),
.v4642b6(w17),
.vd02149(w18),
.vafdfa0(w19)
);
vf68661 v66eb94 (
.v6dda25(w7),
.vfeb41a(w8),
.vf837fe(w13),
.ve9e5a1(w16),
.ve146f6(w19)
);
v145d1e v3f3e01 (
.vc74a9c(w9),
.vb76294(w14),
.vb79ed5(w15),
.v6287a6(w17),
.v19f646(w18)
);
v04e061 vb15d38 (
.v4642b6(w2),
.vd6bebe(w6)
);
v3676a0 vd1c5e9 (
.v0e28cb(w2),
.vcbab45(w10)
);
endmodule
//---------------------------------------------------
//-- Generic-comp-clk
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic component with clk input
//---------------------------------------------------
//---- Top entity
module vf1cffe (
input v6dda25,
input v27dec4,
input [31:0] va0e119,
input v79476f,
input ve9ba68,
output [31:0] v9231ba,
output [31:0] vfc9252,
output [3:0] ve17e80,
output v8d2eee
);
wire w0;
wire [0:31] w1;
wire w2;
wire w3;
wire [0:31] w4;
wire [0:31] w5;
wire [0:3] w6;
wire w7;
wire w8;
assign w0 = v27dec4;
assign w1 = va0e119;
assign w2 = v79476f;
assign w3 = ve9ba68;
assign v9231ba = w4;
assign vfc9252 = w5;
assign ve17e80 = w6;
assign v8d2eee = w7;
assign w8 = v6dda25;
vf1cffe_v172245 v172245 (
.reset(w0),
.mem_rdata(w1),
.mem_rbusy(w2),
.mem_wbusy(w3),
.mem_addr(w4),
.mem_wdata(w5),
.mem_wmask(w6),
.mem_rstrb(w7),
.clk(w8)
);
endmodule
//---------------------------------------------------
//-- RV32I
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- RV32I
//---------------------------------------------------
module vf1cffe_v172245 (
input clk,
input reset,
input [31:0] mem_rdata,
input mem_rbusy,
input mem_wbusy,
output [31:0] mem_addr,
output [31:0] mem_wdata,
output [3:0] mem_wmask,
output mem_rstrb
);
localparam RESET_ADDR = 0;
parameter ADDR_WIDTH = 24;
localparam ADDR_PAD = {(32-ADDR_WIDTH){1'b0}}; // 32-bits padding for addrs
/***************************************************************************/
// Instruction decoding.
/***************************************************************************/
// Extracts rd,rs1,rs2,funct3,imm and opcode from instruction.
// Reference: Table page 104 of:
// https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
// The destination register
wire [4:0] rdId = instr[11:7];
// The ALU function, decoded in 1-hot form (doing so reduces LUT count)
// It is used as follows: funct3Is[val] <=> funct3 == val
(* onehot *)
wire [7:0] funct3Is = 8'b00000001 << instr[14:12];
// The five immediate formats, see RiscV reference (link above), Fig. 2.4 p. 12
wire [31:0] Uimm = { instr[31], instr[30:12], {12{1'b0}}};
wire [31:0] Iimm = {{21{instr[31]}}, instr[30:20]};
/* verilator lint_off UNUSED */ // MSBs of SBJimms are not used by addr adder.
wire [31:0] Simm = {{21{instr[31]}}, instr[30:25],instr[11:7]};
wire [31:0] Bimm = {{20{instr[31]}}, instr[7],instr[30:25],instr[11:8],1'b0};
wire [31:0] Jimm = {{12{instr[31]}}, instr[19:12],instr[20],instr[30:21],1'b0};
/* verilator lint_on UNUSED */
// Base RISC-V (RV32I) has only 10 different instructions !
wire isLoad = (instr[6:2] == 5'b00000); // rd <- mem[rs1+Iimm]
wire isALUimm = (instr[6:2] == 5'b00100); // rd <- rs1 OP Iimm
wire isAUIPC = (instr[6:2] == 5'b00101); // rd <- PC + Uimm
wire isStore = (instr[6:2] == 5'b01000); // mem[rs1+Simm] <- rs2
wire isALUreg = (instr[6:2] == 5'b01100); // rd <- rs1 OP rs2
wire isLUI = (instr[6:2] == 5'b01101); // rd <- Uimm
wire isBranch = (instr[6:2] == 5'b11000); // if(rs1 OP rs2) PC<-PC+Bimm
wire isJALR = (instr[6:2] == 5'b11001); // rd <- PC+4; PC<-rs1+Iimm
wire isJAL = (instr[6:2] == 5'b11011); // rd <- PC+4; PC<-PC+Jimm
wire isSYSTEM = (instr[6:2] == 5'b11100); // rd <- cycles
wire isALU = isALUimm | isALUreg;
/***************************************************************************/
// The register file.
/***************************************************************************/
reg [31:0] rs1;
reg [31:0] rs2;
reg [31:0] registerFile [31:0];
always @(posedge clk) begin
if (writeBack)
if (rdId != 0)
registerFile[rdId] <= writeBackData;
end
/***************************************************************************/
// The ALU. Does operations and tests combinatorially, except shifts.
/***************************************************************************/
// First ALU source, always rs1
wire [31:0] aluIn1 = rs1;
// Second ALU source, depends on opcode:
// ALUreg, Branch: rs2
// ALUimm, Load, JALR: Iimm
wire [31:0] aluIn2 = isALUreg | isBranch ? rs2 : Iimm;
reg [31:0] aluReg; // The internal register of the ALU, used by shift.
reg [4:0] aluShamt; // Current shift amount.
wire aluBusy = |aluShamt; // ALU is busy if shift amount is non-zero.
wire aluWr; // ALU write strobe, starts shifting.
// The adder is used by both arithmetic instructions and JALR.
wire [31:0] aluPlus = aluIn1 + aluIn2;
// Use a single 33 bits subtract to do subtraction and all comparisons
// (trick borrowed from swapforth/J1)
wire [32:0] aluMinus = {1'b1, ~aluIn2} + {1'b0,aluIn1} + 33'b1;
wire LT = (aluIn1[31] ^ aluIn2[31]) ? aluIn1[31] : aluMinus[32];
wire LTU = aluMinus[32];
wire EQ = (aluMinus[31:0] == 0);
// Notes:
// - instr[30] is 1 for SUB and 0 for ADD
// - for SUB, need to test also instr[5] to discriminate ADDI:
// (1 for ADD/SUB, 0 for ADDI, and Iimm used by ADDI overlaps bit 30 !)
// - instr[30] is 1 for SRA (do sign extension) and 0 for SRL
wire [31:0] aluOut =
(funct3Is[0] ? instr[30] & instr[5] ? aluMinus[31:0] : aluPlus : 32'b0) |
(funct3Is[2] ? {31'b0, LT} : 32'b0) |
(funct3Is[3] ? {31'b0, LTU} : 32'b0) |
(funct3Is[4] ? aluIn1 ^ aluIn2 : 32'b0) |
(funct3Is[6] ? aluIn1 | aluIn2 : 32'b0) |
(funct3Is[7] ? aluIn1 & aluIn2 : 32'b0) |
(funct3IsShift ? aluReg : 32'b0) ;
wire funct3IsShift = funct3Is[1] | funct3Is[5];
always @(posedge clk) begin
if(aluWr) begin
if (funct3IsShift) begin // SLL, SRA, SRL
aluReg <= aluIn1;
aluShamt <= aluIn2[4:0];
end
end
// Compact form of:
// funct3=001 -> SLL (aluReg <= aluReg << 1)
// funct3=101 & instr[30] -> SRA (aluReg <= {aluReg[31], aluReg[31:1]})
// funct3=101 & !instr[30] -> SRL (aluReg <= {1'b0, aluReg[31:1]})
if (|aluShamt) begin
aluShamt <= aluShamt - 1;
aluReg <= funct3Is[1] ? aluReg << 1 : // SLL
{instr[30] & aluReg[31], aluReg[31:1]}; // SRA,SRL
end
end
/***************************************************************************/
// The predicate for conditional branches.
/***************************************************************************/
wire predicate =
funct3Is[0] & EQ | // BEQ
funct3Is[1] & !EQ | // BNE
funct3Is[4] & LT | // BLT
funct3Is[5] & !LT | // BGE
funct3Is[6] & LTU | // BLTU
funct3Is[7] & !LTU ; // BGEU
/***************************************************************************/
// Program counter and branch target computation.
/***************************************************************************/
reg [ADDR_WIDTH-1:0] PC; // The program counter.
reg [31:2] instr; // Latched instruction. Note that bits 0 and 1 are
// ignored (not used in RV32I base instr set).
wire [ADDR_WIDTH-1:0] PCplus4 = PC + 4;
// An adder used to compute branch address, JAL address and AUIPC.
// branch->PC+Bimm AUIPC->PC+Uimm JAL->PC+Jimm
// Equivalent to PCplusImm = PC + (isJAL ? Jimm : isAUIPC ? Uimm : Bimm)
wire [ADDR_WIDTH-1:0] PCplusImm = PC + ( instr[3] ? Jimm[ADDR_WIDTH-1:0] :
instr[4] ? Uimm[ADDR_WIDTH-1:0] :
Bimm[ADDR_WIDTH-1:0] );
// A separate adder to compute the destination of load/store.
// testing instr[5] is equivalent to testing isStore in this context.
wire [ADDR_WIDTH-1:0] loadstore_addr = rs1[ADDR_WIDTH-1:0] +
(instr[5] ? Simm[ADDR_WIDTH-1:0] : Iimm[ADDR_WIDTH-1:0]);
assign mem_addr = {ADDR_PAD,
state[WAIT_INSTR_bit] | state[FETCH_INSTR_bit] ?
PC : loadstore_addr
};
/***************************************************************************/
// The value written back to the register file.
/***************************************************************************/
wire [31:0] writeBackData =
/* verilator lint_off WIDTH */
(isSYSTEM ? cycles : 32'b0) | // SYSTEM
/* verilator lint_on WIDTH */
(isLUI ? Uimm : 32'b0) | // LUI
(isALU ? aluOut : 32'b0) | // ALUreg, ALUimm
(isAUIPC ? {ADDR_PAD,PCplusImm} : 32'b0) | // AUIPC
(isJALR | isJAL ? {ADDR_PAD,PCplus4 } : 32'b0) | // JAL, JALR
(isLoad ? LOAD_data : 32'b0); // Load
/***************************************************************************/
// LOAD/STORE
/***************************************************************************/
// All memory accesses are aligned on 32 bits boundary. For this
// reason, we need some circuitry that does unaligned halfword
// and byte load/store, based on:
// - funct3[1:0]: 00->byte 01->halfword 10->word
// - mem_addr[1:0]: indicates which byte/halfword is accessed
wire mem_byteAccess = instr[13:12] == 2'b00; // funct3[1:0] == 2'b00;
wire mem_halfwordAccess = instr[13:12] == 2'b01; // funct3[1:0] == 2'b01;
// LOAD, in addition to funct3[1:0], LOAD depends on:
// - funct3[2] (instr[14]): 0->do sign expansion 1->no sign expansion
wire LOAD_sign =
!instr[14] & (mem_byteAccess ? LOAD_byte[7] : LOAD_halfword[15]);
wire [31:0] LOAD_data =
mem_byteAccess ? {{24{LOAD_sign}}, LOAD_byte} :
mem_halfwordAccess ? {{16{LOAD_sign}}, LOAD_halfword} :
mem_rdata ;
wire [15:0] LOAD_halfword =
loadstore_addr[1] ? mem_rdata[31:16] : mem_rdata[15:0];
wire [7:0] LOAD_byte =
loadstore_addr[0] ? LOAD_halfword[15:8] : LOAD_halfword[7:0];
// STORE
assign mem_wdata[ 7: 0] = rs2[7:0];
assign mem_wdata[15: 8] = loadstore_addr[0] ? rs2[7:0] : rs2[15: 8];
assign mem_wdata[23:16] = loadstore_addr[1] ? rs2[7:0] : rs2[23:16];
assign mem_wdata[31:24] = loadstore_addr[0] ? rs2[7:0] :
loadstore_addr[1] ? rs2[15:8] : rs2[31:24];
// The memory write mask:
// 1111 if writing a word
// 0011 or 1100 if writing a halfword
// (depending on loadstore_addr[1])
// 0001, 0010, 0100 or 1000 if writing a byte
// (depending on loadstore_addr[1:0])
wire [3:0] STORE_wmask =
mem_byteAccess ?
(loadstore_addr[1] ?
(loadstore_addr[0] ? 4'b1000 : 4'b0100) :
(loadstore_addr[0] ? 4'b0010 : 4'b0001)
) :
mem_halfwordAccess ?
(loadstore_addr[1] ? 4'b1100 : 4'b0011) :
4'b1111;
/*************************************************************************/
// And, last but not least, the state machine.
/*************************************************************************/
localparam FETCH_INSTR_bit = 0;
localparam WAIT_INSTR_bit = 1;
localparam EXECUTE_bit = 2;
localparam WAIT_ALU_OR_MEM_bit = 3;
localparam NB_STATES = 4;
localparam FETCH_INSTR = 1 << FETCH_INSTR_bit;
localparam WAIT_INSTR = 1 << WAIT_INSTR_bit;
localparam EXECUTE = 1 << EXECUTE_bit;
localparam WAIT_ALU_OR_MEM = 1 << WAIT_ALU_OR_MEM_bit;
(* onehot *)
reg [NB_STATES-1:0] state;
// The signals (internal and external) that are determined
// combinatorially from state and other signals.
// register write-back enable.
wire writeBack = ~(isBranch | isStore ) &
(state[EXECUTE_bit] | state[WAIT_ALU_OR_MEM_bit]);
// The memory-read signal.
assign mem_rstrb = state[EXECUTE_bit] & isLoad | state[FETCH_INSTR_bit];
// The mask for memory-write.
assign mem_wmask = {4{state[EXECUTE_bit] & isStore}} & STORE_wmask;
// aluWr starts computation (shifts) in the ALU.
assign aluWr = state[EXECUTE_bit] & isALU;
wire jumpToPCplusImm = isJAL | (isBranch & predicate);
`ifdef NRV_IS_IO_ADDR
wire needToWait = isLoad |
isStore & `NRV_IS_IO_ADDR(mem_addr) |
isALU & funct3IsShift;
`else
wire needToWait = isLoad | isStore | isALU & funct3IsShift;
`endif
always @(posedge clk) begin
if(!reset) begin
state <= WAIT_ALU_OR_MEM; // Just waiting for !mem_wbusy
PC <= RESET_ADDR[ADDR_WIDTH-1:0];
end else
// See note [1] at the end of this file.
(* parallel_case *)
case(1'b1)
state[WAIT_INSTR_bit]: begin
if(!mem_rbusy) begin // may be high when executing from SPI flash
rs1 <= registerFile[mem_rdata[19:15]];
rs2 <= registerFile[mem_rdata[24:20]];
instr <= mem_rdata[31:2]; // Bits 0 and 1 are ignored (see
state <= EXECUTE; // also the declaration of instr).
end
end
state[EXECUTE_bit]: begin
PC <= isJALR ? {aluPlus[ADDR_WIDTH-1:1],1'b0} :
jumpToPCplusImm ? PCplusImm :
PCplus4;
state <= needToWait ? WAIT_ALU_OR_MEM : FETCH_INSTR;
end
state[WAIT_ALU_OR_MEM_bit]: begin
if(!aluBusy & !mem_rbusy & !mem_wbusy) state <= FETCH_INSTR;
end
default: begin // FETCH_INSTR
state <= WAIT_INSTR;
end
endcase
end
/***************************************************************************/
// Cycle counter
/***************************************************************************/
`ifdef NRV_COUNTER_WIDTH
reg [`NRV_COUNTER_WIDTH-1:0] cycles;
`else
reg [31:0] cycles;
`endif
always @(posedge clk) cycles <= cycles + 1;
`ifdef BENCH
initial begin
cycles = 0;
aluShamt = 0;
registerFile[0] = 0;
end
`endif
/*****************************************************************************/
// Notes:
//
// [1] About the "reverse case" statement, also used in Claire Wolf's picorv32:
// It is just a cleaner way of writing a series of cascaded if() statements,
// To understand it, think about the case statement *in general* as follows:
// case (expr)
// val_1: statement_1
// val_2: statement_2
// ... val_n: statement_n
// endcase
// The first statement_i such that expr == val_i is executed.
// Now if expr is 1'b1:
// case (1'b1)
// cond_1: statement_1
// cond_2: statement_2
// ... cond_n: statement_n
// endcase
// It is *exactly the same thing*, the first statement_i such that
// expr == cond_i is executed (that is, such that 1'b1 == cond_i,
// in other words, such that cond_i is true)
// More on this:
// https://stackoverflow.com/questions/15418636/case-statement-in-verilog
//
// [2] state uses 1-hot encoding (at any time, state has only one bit set to 1).
// It uses a larger number of bits (one bit per state), but often results in
// a both more compact (fewer LUTs) and faster state machine.
endmodule
//---- Top entity
module vd30ca9 (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vd30ca9_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 0
//---------------------------------------------------
module vd30ca9_vb2eccd (
output q
);
//-- Constant bit-0
assign q = 1'b0;
endmodule
//---- Top entity
module v893ac6 #(
parameter vba98fe = "vba98fe.list"
) (
input v6dda25,
input [31:0] v5d7e06,
output [31:0] v9a5b8a
);
localparam p6 = vba98fe;
wire w0;
wire [0:31] w1;
wire w2;
wire [0:31] w3;
wire [0:9] w4;
wire [0:31] w5;
wire w7;
wire [0:31] w8;
wire [0:31] w9;
assign w7 = v6dda25;
assign v9a5b8a = w8;
assign w9 = v5d7e06;
vd30ca9 vc98086 (
.v9fb85f(w0)
);
vd30ca9 v30628d (
.v9fb85f(w2)
);
v2c97f6 v773b48 (
.v7c9bd8(w3)
);
v675d07 #(
.v5a4ee6(p6)
) vdbacf7 (
.v23dc54(w2),
.v6f4b70(w3),
.vb261ad(w4),
.v922e3d(w7),
.vddff9f(w8)
);
v794b6d va8ea8d (
.vef1612(w4),
.ve841af(w5)
);
vaaf5c4 ve8e400 (
.v712289(w0),
.v51eedb(w1),
.v4f6beb(w9)
);
vaaf5c4 v677471 (
.v4f6beb(w1),
.v51eedb(w5)
);
endmodule
//---------------------------------------------------
//-- Generic-comp-clk
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic component with clk input
//---------------------------------------------------
//---- Top entity
module v2c97f6 #(
parameter vfffc23 = 0
) (
output [31:0] v7c9bd8
);
localparam p0 = vfffc23;
wire [0:31] w1;
assign v7c9bd8 = w1;
v959751 #(
.vc5c8ea(p0)
) v9f49e7 (
.vbc97e4(w1)
);
endmodule
//---------------------------------------------------
//-- 32bits-Value_0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 32bits constant value: 0
//---------------------------------------------------
//---- Top entity
module v959751 #(
parameter vc5c8ea = 0
) (
output [31:0] vbc97e4
);
localparam p0 = vc5c8ea;
wire [0:31] w1;
assign vbc97e4 = w1;
v959751_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 32-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 32-bits generic constant
//---------------------------------------------------
module v959751_v465065 #(
parameter VALUE = 0
) (
output [31:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v675d07 #(
parameter v5a4ee6 = "v5a4ee6.list"
) (
input v922e3d,
input [9:0] vb261ad,
input [31:0] v6f4b70,
input v23dc54,
output [31:0] vddff9f
);
localparam p2 = v5a4ee6;
wire w0;
wire w1;
wire [0:9] w3;
wire [0:31] w4;
wire [0:31] w5;
assign w0 = v922e3d;
assign w1 = v23dc54;
assign w3 = vb261ad;
assign vddff9f = w4;
assign w5 = v6f4b70;
v675d07_vbaa912 #(
.ROMF(p2)
) vbaa912 (
.clk(w0),
.wr(w1),
.addr(w3),
.data_out(w4),
.data_in(w5)
);
endmodule
//---------------------------------------------------
//-- Memory-1Kx32
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Smem 1kx32: Synchronous memory: 1024 words of 32 bits
//---------------------------------------------------
module v675d07_vbaa912 #(
parameter ROMF = 0
) (
input clk,
input [9:0] addr,
input [31:0] data_in,
input wr,
output [31:0] data_out
);
//-- Address with
localparam ADDR_WIDTH = 10;
//-- Data with
localparam DATA_WIDTH = 32;
//-- Size of the memory
localparam SIZE = 1 << ADDR_WIDTH;
//-- Memory itself
reg [DATA_WIDTH-1:0] mem[0:SIZE-1];
//-- The data_out is a registered output (not a wire)
reg data_out;
//-- Reading port: Synchronous
always @(posedge clk)
begin
data_out <= mem[addr];
end
//-- Writing port: Synchronous
always @(posedge clk)
begin
if (wr) mem[addr] <= data_in;
end
//-- Init the memory
initial begin
if (ROMF)
$readmemh(ROMF, mem, 0, SIZE-1);
end
endmodule
//---- Top entity
module v794b6d (
input [31:0] ve841af,
output [21:0] v51fb1f,
output [9:0] vef1612
);
wire [0:31] w0;
wire [0:9] w1;
wire [0:21] w2;
assign w0 = ve841af;
assign vef1612 = w1;
assign v51fb1f = w2;
v794b6d_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus32-Split-22-10
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus32-Split-22-10: Split the 32-bits bus into two buses of 22 and 10 wires
//---------------------------------------------------
module v794b6d_v9a2a06 (
input [31:0] i,
output [21:0] o1,
output [9:0] o0
);
assign o1 = i[31:10];
assign o0 = i[9:0];
endmodule
//---- Top entity
module vaaf5c4 (
input v712289,
input [31:0] v4f6beb,
output [31:0] v51eedb,
output v7e4f0f
);
wire [0:31] w0;
wire w1;
wire w2;
wire [0:30] w3;
wire [0:31] w4;
assign w0 = v4f6beb;
assign v7e4f0f = w1;
assign w2 = v712289;
assign v51eedb = w4;
vecd30a vd4273f (
.ve841af(w0),
.v8d1a42(w1),
.v11ef80(w3)
);
v51b3c0 v9b7810 (
.v411a12(w2),
.vd40455(w3),
.v7d0a31(w4)
);
endmodule
//---------------------------------------------------
//-- SR1-32bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- SR1-32bits: Shift a 32-bit value one bit right. MSB is filled with the input in
//---------------------------------------------------
//---- Top entity
module vecd30a (
input [31:0] ve841af,
output [30:0] v11ef80,
output v8d1a42
);
wire [0:31] w0;
wire w1;
wire [0:30] w2;
assign w0 = ve841af;
assign v8d1a42 = w1;
assign v11ef80 = w2;
vecd30a_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus32-Split-31-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus32-Split-31-1: Split the 32-bits bus into two buses of 31 and 1 wires
//---------------------------------------------------
module vecd30a_v9a2a06 (
input [31:0] i,
output [30:0] o1,
output o0
);
assign o1 = i[31:1];
assign o0 = i[0];
endmodule
//---- Top entity
module v51b3c0 (
input v411a12,
input [30:0] vd40455,
output [31:0] v7d0a31
);
wire [0:31] w0;
wire [0:30] w1;
wire w2;
assign v7d0a31 = w0;
assign w1 = vd40455;
assign w2 = v411a12;
v51b3c0_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus32-Join-1-31
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus32-Join-1-31: Join the two buses into an 32-bits Bus
//---------------------------------------------------
module v51b3c0_v9a2a06 (
input i1,
input [30:0] i0,
output [31:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module ve4c3a8 #(
parameter v389bd1 = 5'h1F
) (
input [31:0] v5c832d,
output v4642b6,
output vafdfa0,
output vd02149
);
localparam p8 = v389bd1;
wire w0;
wire w1;
wire w2;
wire [0:14] w3;
wire [0:4] w4;
wire [0:4] w5;
wire [0:4] w6;
wire [0:4] w7;
wire [0:2] w9;
wire [0:31] w10;
wire [0:31] w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
assign w10 = v5c832d;
assign w11 = v5c832d;
assign v4642b6 = w12;
assign vafdfa0 = w13;
assign vd02149 = w14;
assign w2 = w1;
assign w6 = w4;
assign w11 = w10;
assign w16 = w15;
v3676a0 v8f98d9 (
.vcbab45(w0),
.v0e28cb(w1)
);
vba518e v72db53 (
.v0e28cb(w0),
.vcbab45(w13),
.v3ca442(w16)
);
vba518e v97a3cf (
.v3ca442(w2),
.vcbab45(w14),
.v0e28cb(w15)
);
v9a2795 v666bdb (
.vda577d(w1),
.vdee7c7(w9)
);
va7b832 ve316c5 (
.v29a212(w3),
.ve841af(w10)
);
vef0f91 v3ffece (
.vcbe66f(w3),
.vfa86aa(w4)
);
v1cc648 v736214 (
.vfad888(w4),
.vd80e4f(w5),
.v4642b6(w12)
);
v108a6d v2a89b0 (
.v6ece80(w5)
);
v1cc648 v01ba64 (
.vd80e4f(w6),
.vfad888(w7),
.v4642b6(w15)
);
v3693fc #(
.vc5c8ea(p8)
) v006a39 (
.vc8d3b9(w7)
);
ve500df vfe8608 (
.vbb2522(w9),
.ve841af(w11)
);
endmodule
//---------------------------------------------------
//-- Generic-comp
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Componente genérico
//---------------------------------------------------
//---- Top entity
module v3676a0 (
input v0e28cb,
output vcbab45
);
wire w0;
wire w1;
assign w0 = v0e28cb;
assign vcbab45 = w1;
v3676a0_vd54ca1 vd54ca1 (
.a(w0),
.q(w1)
);
endmodule
//---------------------------------------------------
//-- NOT
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- NOT gate (Verilog implementation)
//---------------------------------------------------
module v3676a0_vd54ca1 (
input a,
output q
);
//-- NOT Gate
assign q = ~a;
endmodule
//---- Top entity
module vba518e (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vba518e_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- AND2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Two bits input And gate
//---------------------------------------------------
module vba518e_vf4938a (
input a,
input b,
output c
);
//-- AND gate
//-- Verilog implementation
assign c = a & b;
endmodule
//---- Top entity
module v9a2795 (
input [2:0] vdee7c7,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire [0:2] w2;
wire w3;
assign v3f8943 = w0;
assign v64d863 = w1;
assign w2 = vdee7c7;
assign vda577d = w3;
v9a2795_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2),
.o2(w3)
);
endmodule
//---------------------------------------------------
//-- Bus3-Split-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus3-Split-all: Split the 3-bits bus into three wires
//---------------------------------------------------
module v9a2795_v9a2a06 (
input [2:0] i,
output o2,
output o1,
output o0
);
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module va7b832 (
input [31:0] ve841af,
output [16:0] v62a8c1,
output [14:0] v29a212
);
wire [0:31] w0;
wire [0:14] w1;
wire [0:16] w2;
assign w0 = ve841af;
assign v29a212 = w1;
assign v62a8c1 = w2;
va7b832_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus32-Split-17-15
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus32-Split-17-15: Split the 32-bits bus into two buses of 17 and 15 wires
//---------------------------------------------------
module va7b832_v9a2a06 (
input [31:0] i,
output [16:0] o1,
output [14:0] o0
);
assign o1 = i[31:15];
assign o0 = i[14:0];
endmodule
//---- Top entity
module vef0f91 (
input [14:0] vcbe66f,
output [4:0] vfa86aa,
output [9:0] vbdb2c8
);
wire [0:14] w0;
wire [0:9] w1;
wire [0:4] w2;
assign w0 = vcbe66f;
assign vbdb2c8 = w1;
assign vfa86aa = w2;
vef0f91_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus15-Split-7-8 CLONE
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus15-Split-7-8: Split the 15-bits bus into two buses of 7 and 8 bits
//---------------------------------------------------
module vef0f91_v9a2a06 (
input [14:0] i,
output [4:0] o1,
output [9:0] o0
);
assign o1 = i[14:10];
assign o0 = i[9:0];
endmodule
//---- Top entity
module v1cc648 (
input [4:0] vd80e4f,
input [4:0] vfad888,
output v4642b6
);
wire w0;
wire [0:4] w1;
wire [0:4] w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire w7;
wire [0:3] w8;
assign v4642b6 = w0;
assign w1 = vfad888;
assign w2 = vd80e4f;
v23b15b vc1b29d (
.v4642b6(w3),
.v27dec4(w5),
.v6848e9(w7)
);
v91f34c vf38386 (
.v427dd1(w1),
.v53baa6(w7),
.v479af4(w8)
);
v91f34c v83c3c9 (
.v427dd1(w2),
.v53baa6(w5),
.v479af4(w6)
);
v438230 v577a36 (
.v4642b6(w4),
.v693354(w6),
.v5369cd(w8)
);
vba518e v707c6e (
.vcbab45(w0),
.v0e28cb(w3),
.v3ca442(w4)
);
endmodule
//---------------------------------------------------
//-- comp2-5bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-5bit: Comparator of two 5-bit numbers
//---------------------------------------------------
//---- Top entity
module v23b15b (
input v27dec4,
input v6848e9,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire w3;
assign w1 = v27dec4;
assign v4642b6 = w2;
assign w3 = v6848e9;
vd12401 v955b2b (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v3676a0 vf92936 (
.v0e28cb(w0),
.vcbab45(w2)
);
endmodule
//---------------------------------------------------
//-- comp2-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-1bit: Comparator of two 1-bit numbers
//---------------------------------------------------
//---- Top entity
module vd12401 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vd12401_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- XOR2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- XOR gate: two bits input xor gate
//---------------------------------------------------
module vd12401_vf4938a (
input a,
input b,
output c
);
//-- XOR gate
//-- Verilog implementation
assign c = a ^ b;
endmodule
//---- Top entity
module v91f34c (
input [4:0] v427dd1,
output v53baa6,
output [3:0] v479af4
);
wire [0:3] w0;
wire [0:4] w1;
wire w2;
assign v479af4 = w0;
assign w1 = v427dd1;
assign v53baa6 = w2;
v91f34c_v9a2a06 v9a2a06 (
.o0(w0),
.i(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus5-Split-1-4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus5-Split-1-4: Split the 5-bits bus into two buses of 1 and 4 bits
//---------------------------------------------------
module v91f34c_v9a2a06 (
input [4:0] i,
output o1,
output [3:0] o0
);
assign o1 = i[4];
assign o0 = i[3:0];
endmodule
//---- Top entity
module v438230 (
input [3:0] v693354,
input [3:0] v5369cd,
output v4642b6
);
wire w0;
wire [0:3] w1;
wire [0:3] w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
assign v4642b6 = w0;
assign w1 = v693354;
assign w2 = v5369cd;
v23b15b v09a5a5 (
.v4642b6(w3),
.v27dec4(w12),
.v6848e9(w14)
);
v23b15b vc1b29d (
.v4642b6(w4),
.v27dec4(w11),
.v6848e9(w13)
);
v23b15b vcd27ce (
.v4642b6(w5),
.v27dec4(w9),
.v6848e9(w10)
);
vc4f23a vea9c80 (
.v985fcb(w1),
.v4f1fd3(w7),
.vda577d(w9),
.v3f8943(w11),
.v64d863(w12)
);
vc4f23a va7dcdc (
.v985fcb(w2),
.v4f1fd3(w8),
.vda577d(w10),
.v3f8943(w13),
.v64d863(w14)
);
v23b15b va0849c (
.v4642b6(w6),
.v27dec4(w7),
.v6848e9(w8)
);
veffd42 v6e3e65 (
.vcbab45(w0),
.v3ca442(w3),
.v0e28cb(w4),
.v033bf6(w5),
.v9eb652(w6)
);
endmodule
//---------------------------------------------------
//-- comp2-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-4bit: Comparator of two 4-bit numbers
//---------------------------------------------------
//---- Top entity
module vc4f23a (
input [3:0] v985fcb,
output v4f1fd3,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign v3f8943 = w0;
assign v64d863 = w1;
assign vda577d = w2;
assign v4f1fd3 = w3;
assign w4 = v985fcb;
vc4f23a_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.o2(w2),
.o3(w3),
.i(w4)
);
endmodule
//---------------------------------------------------
//-- Bus4-Split-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus4-Split-all: Split the 4-bits bus into its wires
//---------------------------------------------------
module vc4f23a_v9a2a06 (
input [3:0] i,
output o3,
output o2,
output o1,
output o0
);
assign o3 = i[3];
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module veffd42 (
input v9eb652,
input v033bf6,
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w0 = v3ca442;
assign w1 = v9eb652;
assign w2 = v033bf6;
assign w3 = v0e28cb;
assign vcbab45 = w4;
vba518e vf3ef0f (
.v3ca442(w0),
.v0e28cb(w3),
.vcbab45(w6)
);
vba518e vdcc53d (
.v0e28cb(w1),
.v3ca442(w2),
.vcbab45(w5)
);
vba518e v17ac22 (
.vcbab45(w4),
.v0e28cb(w5),
.v3ca442(w6)
);
endmodule
//---------------------------------------------------
//-- AND4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Three bits input And gate
//---------------------------------------------------
//---- Top entity
module v108a6d #(
parameter vfffc23 = 0
) (
output [4:0] v6ece80
);
localparam p0 = vfffc23;
wire [0:4] w1;
assign v6ece80 = w1;
v3693fc #(
.vc5c8ea(p0)
) ve88537 (
.vc8d3b9(w1)
);
endmodule
//---------------------------------------------------
//-- 5bits-Value_0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 5bits constant value: 0
//---------------------------------------------------
//---- Top entity
module v3693fc #(
parameter vc5c8ea = 0
) (
output [4:0] vc8d3b9
);
localparam p0 = vc5c8ea;
wire [0:4] w1;
assign vc8d3b9 = w1;
v3693fc_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 5-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 5-bits generic constant (0-31)
//---------------------------------------------------
module v3693fc_v465065 #(
parameter VALUE = 0
) (
output [4:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module ve500df (
input [31:0] ve841af,
output [28:0] vfc82fb,
output [2:0] vbb2522
);
wire [0:31] w0;
wire [0:2] w1;
wire [0:28] w2;
assign w0 = ve841af;
assign vbb2522 = w1;
assign vfc82fb = w2;
ve500df_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus32-Split-29-3
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus32-Split-29-3: Split the 29-bits bus into two buses of 29 and 3 wires
//---------------------------------------------------
module ve500df_v9a2a06 (
input [31:0] i,
output [28:0] o1,
output [2:0] o0
);
assign o1 = i[31:3];
assign o0 = i[2:0];
endmodule
//---- Top entity
module vf68661 (
input v6dda25,
input [31:0] vf837fe,
input [3:0] ve9e5a1,
input ve146f6,
output [7:0] vfeb41a
);
wire w0;
wire [0:7] w1;
wire w2;
wire [0:7] w3;
wire w4;
wire [0:31] w5;
wire [0:3] w6;
wire w7;
assign vfeb41a = w3;
assign w4 = v6dda25;
assign w5 = vf837fe;
assign w6 = ve9e5a1;
assign w7 = ve146f6;
vf61fa3 v8cf02b (
.vcbab45(w0),
.vaf45b8(w6)
);
vba518e v7c2c65 (
.v0e28cb(w0),
.vcbab45(w2),
.v3ca442(w7)
);
v468a05 v4dcb81 (
.vc6471a(w1),
.ve841af(w5)
);
v857d2e v415624 (
.vec26ff(w1),
.vccca56(w2),
.v19a59f(w3),
.v6dda25(w4)
);
endmodule
//---------------------------------------------------
//-- Generic-comp-clk
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic component with clk input
//---------------------------------------------------
//---- Top entity
module vf61fa3 (
input [3:0] vaf45b8,
output vcbab45
);
wire w0;
wire [0:3] w1;
wire w2;
wire w3;
wire w4;
wire w5;
assign vcbab45 = w0;
assign w1 = vaf45b8;
vc4f23a v5f4674 (
.v985fcb(w1),
.v4f1fd3(w2),
.vda577d(w3),
.v3f8943(w4),
.v64d863(w5)
);
vf49321 vea932e (
.vcbab45(w0),
.ve86251(w2),
.v0e28cb(w3),
.v3ca442(w4),
.v8b2684(w5)
);
endmodule
//---------------------------------------------------
//-- OR-BUS4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- OR-BUS4: OR gate with 4-bits bus input
//---------------------------------------------------
//---- Top entity
module vf49321 (
input ve86251,
input v0e28cb,
input v3ca442,
input v8b2684,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w0 = ve86251;
assign w1 = v0e28cb;
assign w3 = v3ca442;
assign vcbab45 = w5;
assign w6 = v8b2684;
v873425 v1edc96 (
.v0e28cb(w0),
.v3ca442(w1),
.vcbab45(w2)
);
v873425 v5591ec (
.v0e28cb(w2),
.v3ca442(w3),
.vcbab45(w4)
);
v873425 vdba9a4 (
.v0e28cb(w4),
.vcbab45(w5),
.v3ca442(w6)
);
endmodule
//---------------------------------------------------
//-- OR4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- OR4: Four bits input OR gate
//---------------------------------------------------
//---- Top entity
module v873425 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
v873425_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- OR2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- OR2: Two bits input OR gate
//---------------------------------------------------
module v873425_vf4938a (
input a,
input b,
output c
);
//-- OR Gate
//-- Verilog implementation
assign c = a | b;
endmodule
//---- Top entity
module v468a05 (
input [31:0] ve841af,
output [7:0] vdd0469,
output [7:0] v4ba85d,
output [7:0] vf93ecb,
output [7:0] vc6471a
);
wire [0:31] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
assign w0 = ve841af;
assign vc6471a = w1;
assign vf93ecb = w2;
assign v4ba85d = w3;
assign vdd0469 = w4;
v468a05_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2),
.o2(w3),
.o3(w4)
);
endmodule
//---------------------------------------------------
//-- Bus32-Split-quarter
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus32-Split-quarter: Split the 32-bits bus into four buses of 8 wires
//---------------------------------------------------
module v468a05_v9a2a06 (
input [31:0] i,
output [7:0] o3,
output [7:0] o2,
output [7:0] o1,
output [7:0] o0
);
assign o3 = i[32:24];
assign o2 = i[23:16];
assign o1 = i[15:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module v857d2e (
input v6dda25,
input [7:0] vec26ff,
input vccca56,
output [7:0] v19a59f
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:3] w4;
wire [0:3] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w0 = vec26ff;
assign v19a59f = w1;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 = vccca56;
assign w9 = vccca56;
assign w7 = w6;
assign w9 = w8;
v6bdcd9 v8e04d7 (
.vcc8c7c(w0),
.v651522(w2),
.v2cc41f(w4)
);
vafb28f vdbcc53 (
.va9ac17(w1),
.v515fe7(w3),
.v3c88fc(w5)
);
v370cd6 v732df5 (
.v2856c0(w2),
.v7891f9(w3),
.v6dda25(w6),
.vccca56(w8)
);
v370cd6 v21c6af (
.v2856c0(w4),
.v7891f9(w5),
.v6dda25(w7),
.vccca56(w9)
);
endmodule
//---------------------------------------------------
//-- Reg-x08
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg-x08: 8-bits register
//---------------------------------------------------
//---- Top entity
module v6bdcd9 (
input [7:0] vcc8c7c,
output [3:0] v651522,
output [3:0] v2cc41f
);
wire [0:3] w0;
wire [0:3] w1;
wire [0:7] w2;
assign v651522 = w0;
assign v2cc41f = w1;
assign w2 = vcc8c7c;
v6bdcd9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Split-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Split-half: Split the 8-bits bus into two buses of the same size
//---------------------------------------------------
module v6bdcd9_v9a2a06 (
input [7:0] i,
output [3:0] o1,
output [3:0] o0
);
assign o1 = i[7:4];
assign o0 = i[3:0];
endmodule
//---- Top entity
module vafb28f (
input [3:0] v515fe7,
input [3:0] v3c88fc,
output [7:0] va9ac17
);
wire [0:7] w0;
wire [0:3] w1;
wire [0:3] w2;
assign va9ac17 = w0;
assign w1 = v515fe7;
assign w2 = v3c88fc;
vafb28f_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Join-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Join-half: Join the two same halves into an 8-bits Bus
//---------------------------------------------------
module vafb28f_v9a2a06 (
input [3:0] i1,
input [3:0] i0,
output [7:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v370cd6 (
input v6dda25,
input [3:0] v2856c0,
input vccca56,
output [3:0] v7891f9
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v2856c0;
assign v7891f9 = w7;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = vccca56;
assign w15 = vccca56;
assign w16 = vccca56;
assign w17 = vccca56;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
v22cb98 v1ba30c (
.v27dec4(w0),
.v4642b6(w2),
.ve4a668(w12),
.vd793aa(w16)
);
v22cb98 v38f79d (
.v27dec4(w1),
.v4642b6(w3),
.ve4a668(w13),
.vd793aa(w17)
);
v22cb98 v009467 (
.v27dec4(w4),
.v4642b6(w5),
.ve4a668(w11),
.vd793aa(w15)
);
vc4f23a vf2e2c0 (
.v3f8943(w0),
.v64d863(w1),
.vda577d(w4),
.v985fcb(w6),
.v4f1fd3(w8)
);
v84f0a1 v947047 (
.vee8a83(w2),
.v03aaf0(w3),
.vf8041d(w5),
.v11bca5(w7),
.vd84a57(w9)
);
v22cb98 v3a0f4c (
.v27dec4(w8),
.v4642b6(w9),
.ve4a668(w10),
.vd793aa(w14)
);
endmodule
//---------------------------------------------------
//-- Reg-x04
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg-x04: 4-bits register
//---------------------------------------------------
//---- Top entity
module v22cb98 #(
parameter v5462c0 = 0
) (
input ve4a668,
input v27dec4,
input vd793aa,
output v4642b6
);
localparam p1 = v5462c0;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w2 = ve4a668;
assign w3 = v27dec4;
assign v4642b6 = w5;
assign w6 = vd793aa;
assign w5 = w4;
va40d2f v9ff767 (
.v030ad0(w0),
.vb192d0(w3),
.v27dec4(w4),
.v2d3366(w6)
);
v053dc2 #(
.v71e305(p1)
) v89c757 (
.vf54559(w0),
.va4102a(w2),
.ve8318d(w4)
);
endmodule
//---------------------------------------------------
//-- 1-bit-reg
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg: 1-Bit register
//---------------------------------------------------
//---- Top entity
module va40d2f (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
assign v030ad0 = w0;
assign w1 = v2d3366;
assign w2 = v27dec4;
assign w3 = vb192d0;
vd0c4e5 v0f3fef (
.v030ad0(w0),
.v2d3366(w1),
.vb192d0(w2),
.v27dec4(w3)
);
endmodule
//---------------------------------------------------
//-- MuxF-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (1-bit channels). Fippled version
//---------------------------------------------------
//---- Top entity
module vd0c4e5 (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
assign v030ad0 = w0;
assign w2 = v2d3366;
assign w3 = v2d3366;
assign w6 = v27dec4;
assign w7 = vb192d0;
assign w3 = w2;
v873425 vaaee1f (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w4)
);
vba518e v569873 (
.vcbab45(w1),
.v3ca442(w2),
.v0e28cb(w6)
);
v3676a0 v1f00ae (
.v0e28cb(w3),
.vcbab45(w5)
);
vba518e vc8527f (
.vcbab45(w4),
.v3ca442(w5),
.v0e28cb(w7)
);
endmodule
//---------------------------------------------------
//-- Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (1-bit channels)
//---------------------------------------------------
//---- Top entity
module v053dc2 #(
parameter v71e305 = 0
) (
input va4102a,
input vf54559,
output ve8318d
);
localparam p2 = v71e305;
wire w0;
wire w1;
wire w3;
assign w0 = va4102a;
assign ve8318d = w1;
assign w3 = vf54559;
v053dc2_vb8adf8 #(
.INI(p2)
) vb8adf8 (
.clk(w0),
.q(w1),
.d(w3)
);
endmodule
//---------------------------------------------------
//-- DFF
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- D Flip-flop (verilog implementation)
//---------------------------------------------------
module v053dc2_vb8adf8 #(
parameter INI = 0
) (
input clk,
input d,
output q
);
//-- Initial value
reg q = INI;
//-- Capture the input data
//-- on the rising edge of
//-- the system clock
always @(posedge clk)
q <= d;
endmodule
//---- Top entity
module v84f0a1 (
input vd84a57,
input vf8041d,
input vee8a83,
input v03aaf0,
output [3:0] v11bca5
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign w2 = vf8041d;
assign w3 = vd84a57;
assign v11bca5 = w4;
v84f0a1_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.i2(w2),
.i3(w3),
.o(w4)
);
endmodule
//---------------------------------------------------
//-- Bus4-Join-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus4-Join-all: Join all the wires into a 4-bits Bus
//---------------------------------------------------
module v84f0a1_v9a2a06 (
input i3,
input i2,
input i1,
input i0,
output [3:0] o
);
assign o = {i3, i2, i1, i0};
endmodule
//---- Top entity
module v145d1e (
input [31:0] vb79ed5,
input [7:0] vc74a9c,
input v6287a6,
input v19f646,
output [31:0] vb76294
);
wire [0:31] w0;
wire [0:31] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:31] w5;
wire [0:31] w6;
wire [0:31] w7;
wire [0:7] w8;
wire w9;
wire w10;
assign w6 = vb79ed5;
assign vb76294 = w7;
assign w8 = vc74a9c;
assign w9 = v6287a6;
assign w10 = v19f646;
assign w3 = w2;
assign w4 = w2;
assign w4 = w3;
v15006c v7f618a (
.v3d79e8(w0),
.v53354a(w6),
.vd99bd0(w7),
.v2d3366(w9)
);
v15006c vf576d8 (
.vd99bd0(w0),
.v53354a(w1),
.v3d79e8(w5),
.v2d3366(w10)
);
v78e0a3 v9e8b5c (
.v7d0a31(w1),
.v6127ee(w2),
.v12d067(w3),
.vea9d11(w4),
.v29bdec(w8)
);
vda0861 vfb1ecd (
.vffb58f(w2)
);
v2c97f6 v1dbb84 (
.v7c9bd8(w5)
);
endmodule
//---------------------------------------------------
//-- Generic-comp
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Componente genérico
//---------------------------------------------------
//---- Top entity
module v15006c (
input [31:0] v53354a,
input [31:0] v3d79e8,
input v2d3366,
output [31:0] vd99bd0
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:31] w3;
wire [0:31] w4;
wire [0:31] w5;
wire [0:7] w6;
wire [0:7] w7;
wire [0:7] w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire [0:7] w13;
wire [0:7] w14;
wire [0:7] w15;
wire [0:7] w16;
wire [0:7] w17;
wire [0:7] w18;
assign vd99bd0 = w3;
assign w4 = v3d79e8;
assign w5 = v53354a;
assign w9 = v2d3366;
assign w10 = v2d3366;
assign w11 = v2d3366;
assign w12 = v2d3366;
assign w10 = w9;
assign w11 = w9;
assign w11 = w10;
assign w12 = w9;
assign w12 = w10;
assign w12 = w11;
v1bbb5b v41cfb0 (
.v9d2a6a(w0),
.v2d3366(w12),
.v2a1cbe(w17),
.v9d7ae8(w18)
);
v1bbb5b vf7893e (
.v9d2a6a(w1),
.v2d3366(w11),
.v2a1cbe(w15),
.v9d7ae8(w16)
);
v1bbb5b v40a6d4 (
.v9d2a6a(w2),
.v2d3366(w10),
.v2a1cbe(w13),
.v9d7ae8(w14)
);
v78e0a3 v2e8dfc (
.v29bdec(w0),
.vea9d11(w1),
.v6127ee(w2),
.v7d0a31(w3),
.v12d067(w6)
);
v468a05 v95e147 (
.ve841af(w5),
.vdd0469(w7),
.v4ba85d(w13),
.vf93ecb(w15),
.vc6471a(w17)
);
v468a05 v44f594 (
.ve841af(w4),
.vdd0469(w8),
.v4ba85d(w14),
.vf93ecb(w16),
.vc6471a(w18)
);
v1bbb5b v68fd67 (
.v9d2a6a(w6),
.v2a1cbe(w7),
.v9d7ae8(w8),
.v2d3366(w9)
);
endmodule
//---------------------------------------------------
//-- 32-bits-Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (32-bit channels)
//---------------------------------------------------
//---- Top entity
module v1bbb5b (
input [7:0] v2a1cbe,
input [7:0] v9d7ae8,
input v2d3366,
output [7:0] v9d2a6a
);
wire [0:3] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:3] w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire [0:3] w10;
assign v9d2a6a = w1;
assign w2 = v2a1cbe;
assign w3 = v9d7ae8;
assign w8 = v2d3366;
assign w9 = v2d3366;
assign w9 = w8;
v952eda v54aed2 (
.v6833fd(w0),
.v54ac99(w7),
.v2d3366(w9),
.ve2616d(w10)
);
vafb28f v117a88 (
.v3c88fc(w0),
.va9ac17(w1),
.v515fe7(w4)
);
v6bdcd9 v9f32ae (
.vcc8c7c(w2),
.v651522(w5),
.v2cc41f(w7)
);
v6bdcd9 v9881c7 (
.vcc8c7c(w3),
.v651522(w6),
.v2cc41f(w10)
);
v952eda v34a43a (
.v6833fd(w4),
.v54ac99(w5),
.ve2616d(w6),
.v2d3366(w8)
);
endmodule
//---------------------------------------------------
//-- 8-bits-Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (8-bit channels)
//---------------------------------------------------
//---- Top entity
module v952eda (
input [3:0] v54ac99,
input [3:0] ve2616d,
input v2d3366,
output [3:0] v6833fd
);
wire w0;
wire w1;
wire w2;
wire [0:3] w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign v6833fd = w3;
assign w5 = ve2616d;
assign w6 = v54ac99;
assign w9 = v2d3366;
assign w10 = v2d3366;
assign w11 = v2d3366;
assign w12 = v2d3366;
assign w10 = w9;
assign w11 = w9;
assign w11 = w10;
assign w12 = w9;
assign w12 = w10;
assign w12 = w11;
vd0c4e5 v6d94c9 (
.v030ad0(w0),
.v2d3366(w11),
.v27dec4(w15),
.vb192d0(w17)
);
vd0c4e5 vebe465 (
.v030ad0(w1),
.v2d3366(w12),
.v27dec4(w16),
.vb192d0(w18)
);
vd0c4e5 ve1c21f (
.v030ad0(w2),
.v2d3366(w10),
.v27dec4(w13),
.vb192d0(w14)
);
v84f0a1 va44bdf (
.vee8a83(w0),
.v03aaf0(w1),
.vf8041d(w2),
.v11bca5(w3),
.vd84a57(w4)
);
vd0c4e5 v2ebff3 (
.v030ad0(w4),
.v27dec4(w7),
.vb192d0(w8),
.v2d3366(w9)
);
vc4f23a v3c3a57 (
.v985fcb(w5),
.v4f1fd3(w8),
.vda577d(w14),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a vd6d480 (
.v985fcb(w6),
.v4f1fd3(w7),
.vda577d(w13),
.v3f8943(w15),
.v64d863(w16)
);
endmodule
//---------------------------------------------------
//-- 4-bits-Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (4-bit channels)
//---------------------------------------------------
//---- Top entity
module v78e0a3 (
input [7:0] v12d067,
input [7:0] v6127ee,
input [7:0] vea9d11,
input [7:0] v29bdec,
output [31:0] v7d0a31
);
wire [0:31] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
assign v7d0a31 = w0;
assign w1 = v29bdec;
assign w2 = vea9d11;
assign w3 = v6127ee;
assign w4 = v12d067;
v78e0a3_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2),
.i2(w3),
.i3(w4)
);
endmodule
//---------------------------------------------------
//-- Bus32-Join-quarter
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus32-Join-quarter: Join the four buses into an 32-bits Bus
//---------------------------------------------------
module v78e0a3_v9a2a06 (
input [7:0] i3,
input [7:0] i2,
input [7:0] i1,
input [7:0] i0,
output [31:0] o
);
assign o = {i3, i2, i1, i0};
endmodule
//---- Top entity
module vda0861 #(
parameter vfffc23 = 0
) (
output [7:0] vffb58f
);
localparam p0 = vfffc23;
wire [0:7] w1;
assign vffb58f = w1;
vffc517 #(
.vc5c8ea(p0)
) v778577 (
.va0aeac(w1)
);
endmodule
//---------------------------------------------------
//-- 8bits-Value_0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 8bits constant value: 0
//---------------------------------------------------
//---- Top entity
module vffc517 #(
parameter vc5c8ea = 0
) (
output [7:0] va0aeac
);
localparam p0 = vc5c8ea;
wire [0:7] w1;
assign va0aeac = w1;
vffc517_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 8-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 8-bits generic constant (0-255)
//---------------------------------------------------
module vffc517_v465065 #(
parameter VALUE = 0
) (
output [7:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v04e061 #(
parameter v001ed5 = 1
) (
input vd6bebe,
output v4642b6,
output [4:0] vb385cd,
output vd9f5b6
);
localparam p1 = v001ed5;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire [0:4] w8;
wire w9;
wire w10;
wire w11;
wire [0:4] w12;
assign v4642b6 = w2;
assign vd9f5b6 = w6;
assign vb385cd = w8;
assign w9 = vd6bebe;
assign w10 = vd6bebe;
assign w4 = w2;
assign w5 = w3;
assign w10 = w9;
assign w11 = w2;
assign w11 = w4;
v144728 #(
.v573b2a(p1)
) v04fe70 (
.v27dec4(w0),
.v4642b6(w2),
.v92a149(w3),
.v6dda25(w9)
);
vd30ca9 v8af589 (
.v9fb85f(w0)
);
vba518e ve66489 (
.v0e28cb(w5),
.vcbab45(w6),
.v3ca442(w11)
);
vaf1249 ve31e7c (
.ve37344(w3),
.ve556f1(w7),
.v6dda25(w10),
.va1c800(w12)
);
vd30ca9 va31481 (
.v9fb85f(w7)
);
v51353d vabd391 (
.v427380(w4),
.v81cd93(w8),
.v083523(w12)
);
endmodule
//---------------------------------------------------
//-- start-5-bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- start-5-bit: 32 cycles width pulse
//---------------------------------------------------
//---- Top entity
module v144728 #(
parameter v573b2a = 0
) (
input v6dda25,
input v27dec4,
input v92a149,
output v4642b6
);
localparam p0 = v573b2a;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w5 = v6dda25;
assign v4642b6 = w6;
assign w8 = v27dec4;
assign w9 = v92a149;
assign w7 = w6;
v053dc2 #(
.v71e305(p0)
) v24b497 (
.vf54559(w1),
.va4102a(w5),
.ve8318d(w6)
);
vd0c4e5 vda4b54 (
.v030ad0(w1),
.v27dec4(w2),
.vb192d0(w3),
.v2d3366(w8)
);
vfebcfe v2141a0 (
.v9fb85f(w2)
);
vd0c4e5 v75d8ff (
.v030ad0(w3),
.v27dec4(w4),
.vb192d0(w7),
.v2d3366(w9)
);
vd30ca9 va595cf (
.v9fb85f(w4)
);
endmodule
//---------------------------------------------------
//-- RS-FF-set
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- RS-FF-set. RS Flip-flop with priority set
//---------------------------------------------------
//---- Top entity
module vfebcfe (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vfebcfe_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 1
//---------------------------------------------------
module vfebcfe_vb2eccd (
output q
);
//-- Constant bit-1
assign q = 1'b1;
endmodule
//---- Top entity
module vaf1249 (
input v6dda25,
input ve556f1,
output [4:0] va1c800,
output ve37344
);
wire w0;
wire [0:4] w1;
wire [0:4] w2;
wire w3;
wire [0:4] w4;
wire w5;
assign w0 = ve556f1;
assign w3 = v6dda25;
assign va1c800 = w4;
assign ve37344 = w5;
assign w4 = w1;
v6ed669 vad9b51 (
.v782748(w0),
.vcc30ea(w1),
.v35dd11(w2),
.v6dda25(w3)
);
vd0bb30 v1e9706 (
.vd03823(w1),
.vb4c454(w2),
.v4642b6(w5)
);
endmodule
//---------------------------------------------------
//-- syscounter-rst-5bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 5-bits Syscounter with reset
//---------------------------------------------------
//---- Top entity
module v6ed669 (
input v6dda25,
input v782748,
input [4:0] v35dd11,
output [4:0] vcc30ea
);
wire [0:4] w0;
wire [0:3] w1;
wire w2;
wire [0:3] w3;
wire w4;
wire [0:4] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w0 = v35dd11;
assign vcc30ea = w5;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 = v782748;
assign w9 = v782748;
assign w7 = w6;
assign w9 = w8;
v2be0f8 v8aa818 (
.vf354ee(w2),
.v4642b6(w4),
.vd53b77(w6),
.v27dec4(w8)
);
v5c75f6 vbdef88 (
.v4de61b(w1),
.v50034e(w3),
.v6dda25(w7),
.v782748(w9)
);
v91f34c v122992 (
.v427dd1(w0),
.v479af4(w1),
.v53baa6(w2)
);
vcdce79 v93fefd (
.v167ed7(w3),
.vee8a83(w4),
.v6a2e9e(w5)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x05
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x05: Five D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v2be0f8 #(
parameter vbd3217 = 0
) (
input vd53b77,
input v27dec4,
input vf354ee,
output v4642b6
);
localparam p5 = vbd3217;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w6;
assign w2 = v27dec4;
assign w3 = vf354ee;
assign v4642b6 = w4;
assign w6 = vd53b77;
v3676a0 v7539bf (
.vcbab45(w1),
.v0e28cb(w2)
);
vba518e vfe8158 (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v053dc2 #(
.v71e305(p5)
) vd104a4 (
.vf54559(w0),
.ve8318d(w4),
.va4102a(w6)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x01: D Flip flop with reset input. When rst=1, the DFF is 0
//---------------------------------------------------
//---- Top entity
module v5c75f6 (
input v6dda25,
input v782748,
input [3:0] v4de61b,
output [3:0] v50034e
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v4de61b;
assign v50034e = w7;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = v782748;
assign w15 = v782748;
assign w16 = v782748;
assign w17 = v782748;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
vc4f23a v4b1225 (
.v3f8943(w2),
.v64d863(w3),
.vda577d(w4),
.v985fcb(w6),
.v4f1fd3(w8)
);
v84f0a1 v6491fd (
.v03aaf0(w0),
.vee8a83(w1),
.vf8041d(w5),
.v11bca5(w7),
.vd84a57(w9)
);
v2be0f8 v10a04f (
.v4642b6(w0),
.vf354ee(w3),
.vd53b77(w13),
.v27dec4(w17)
);
v2be0f8 v7d9648 (
.v4642b6(w1),
.vf354ee(w2),
.vd53b77(w12),
.v27dec4(w16)
);
v2be0f8 v004b14 (
.vf354ee(w4),
.v4642b6(w5),
.vd53b77(w11),
.v27dec4(w15)
);
v2be0f8 v8aa818 (
.vf354ee(w8),
.v4642b6(w9),
.vd53b77(w10),
.v27dec4(w14)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x04
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x04: Three D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module vcdce79 (
input vee8a83,
input [3:0] v167ed7,
output [4:0] v6a2e9e
);
wire [0:4] w0;
wire w1;
wire [0:3] w2;
assign v6a2e9e = w0;
assign w1 = vee8a83;
assign w2 = v167ed7;
vcdce79_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus5-Join-1-4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus5-Join-1-4: Join the two buses of 1 and 4 bits into a 5-bits Bus
//---------------------------------------------------
module vcdce79_v9a2a06 (
input i1,
input [3:0] i0,
output [4:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module vd0bb30 #(
parameter v6c5139 = 1
) (
input [4:0] vd03823,
output v4642b6,
output [4:0] vb4c454
);
localparam p1 = v6c5139;
wire w0;
wire [0:4] w2;
wire [0:4] w3;
assign v4642b6 = w0;
assign w2 = vd03823;
assign vb4c454 = w3;
va17f79 #(
.vd73390(p1)
) vc288d0 (
.v4642b6(w0),
.va6f14e(w2),
.v919f01(w3)
);
endmodule
//---------------------------------------------------
//-- Inc1-5bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Inc1-5bit: Increment a 5-bits number by one
//---------------------------------------------------
//---- Top entity
module va17f79 #(
parameter vd73390 = 0
) (
input [4:0] va6f14e,
output v4642b6,
output [4:0] v919f01
);
localparam p1 = vd73390;
wire w0;
wire [0:4] w2;
wire [0:4] w3;
wire [0:4] w4;
assign v4642b6 = w0;
assign w3 = va6f14e;
assign v919f01 = w4;
v0cfc7a v530cb5 (
.v4642b6(w0),
.v225d34(w2),
.vbb6b94(w3),
.vae8b91(w4)
);
v3693fc #(
.vc5c8ea(p1)
) v809c3c (
.vc8d3b9(w2)
);
endmodule
//---------------------------------------------------
//-- AdderK-5bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderK-5bit: Adder of 5-bit operand and 5-bit constant
//---------------------------------------------------
//---- Top entity
module v0cfc7a (
input [4:0] v225d34,
input [4:0] vbb6b94,
output v4642b6,
output [4:0] vae8b91
);
wire w0;
wire w1;
wire [0:4] w2;
wire [0:4] w3;
wire [0:4] w4;
wire w5;
wire [0:3] w6;
wire w7;
wire [0:3] w8;
wire w9;
wire [0:3] w10;
assign w2 = vbb6b94;
assign w3 = v225d34;
assign vae8b91 = w4;
assign v4642b6 = w5;
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w5),
.v27dec4(w7),
.v82de4f(w9)
);
v91f34c v144430 (
.v427dd1(w2),
.v53baa6(w9),
.v479af4(w10)
);
v91f34c v09d2c7 (
.v427dd1(w3),
.v53baa6(w7),
.v479af4(w8)
);
v25966b vd35762 (
.v4642b6(w0),
.v817794(w6),
.v0550b6(w8),
.v24708e(w10)
);
vcdce79 v758283 (
.vee8a83(w1),
.v6a2e9e(w4),
.v167ed7(w6)
);
endmodule
//---------------------------------------------------
//-- Adder-5bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-5bits: Adder of two operands of 5 bits
//---------------------------------------------------
//---- Top entity
module vad119b (
input v27dec4,
input v82de4f,
input v0ef266,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
assign v8e8a67 = w1;
assign v4642b6 = w5;
assign w6 = v27dec4;
assign w7 = v27dec4;
assign w8 = v82de4f;
assign w9 = v82de4f;
assign w10 = v0ef266;
assign w11 = v0ef266;
assign w2 = w0;
assign w7 = w6;
assign w9 = w8;
assign w11 = w10;
vd12401 v2e3d9f (
.vcbab45(w0),
.v0e28cb(w7),
.v3ca442(w9)
);
vd12401 vb50462 (
.v0e28cb(w0),
.vcbab45(w1),
.v3ca442(w11)
);
vba518e v4882f4 (
.v3ca442(w2),
.vcbab45(w3),
.v0e28cb(w10)
);
vba518e v8fcf41 (
.vcbab45(w4),
.v0e28cb(w6),
.v3ca442(w8)
);
v873425 vc5b8b9 (
.v3ca442(w3),
.v0e28cb(w4),
.vcbab45(w5)
);
endmodule
//---------------------------------------------------
//-- AdderC-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-1bit: Adder of two operands of 1 bit plus the carry in
//---------------------------------------------------
//---- Top entity
module v25966b (
input [3:0] v0550b6,
input [3:0] v24708e,
output v4642b6,
output [3:0] v817794
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign w5 = v24708e;
assign w6 = v0550b6;
assign v817794 = w7;
assign v4642b6 = w9;
v1ea21d vdbe125 (
.v4642b6(w0),
.v8e8a67(w2),
.v27dec4(w15),
.v82de4f(w18)
);
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w3),
.v27dec4(w14),
.v82de4f(w17)
);
vad119b v5d29b2 (
.v0ef266(w3),
.v8e8a67(w4),
.v4642b6(w8),
.v27dec4(w12),
.v82de4f(w16)
);
vc4f23a vf4a6ff (
.v985fcb(w5),
.v4f1fd3(w13),
.vda577d(w16),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a v9d4632 (
.v985fcb(w6),
.v4f1fd3(w11),
.vda577d(w12),
.v3f8943(w14),
.v64d863(w15)
);
v84f0a1 v140dbf (
.vee8a83(w1),
.v03aaf0(w2),
.vf8041d(w4),
.v11bca5(w7),
.vd84a57(w10)
);
vad119b v5c5937 (
.v0ef266(w8),
.v4642b6(w9),
.v8e8a67(w10),
.v27dec4(w11),
.v82de4f(w13)
);
endmodule
//---------------------------------------------------
//-- Adder-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-4bits: Adder of two operands of 4 bits
//---------------------------------------------------
//---- Top entity
module v1ea21d (
input v27dec4,
input v82de4f,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = v82de4f;
assign w1 = v27dec4;
assign v4642b6 = w3;
assign v8e8a67 = w4;
vad119b vb820a1 (
.v82de4f(w0),
.v27dec4(w1),
.v0ef266(w2),
.v4642b6(w3),
.v8e8a67(w4)
);
vd30ca9 v23ebb6 (
.v9fb85f(w2)
);
endmodule
//---------------------------------------------------
//-- Adder-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-1bit: Adder of two operands of 1 bit
//---------------------------------------------------
//---- Top entity
module v51353d (
input [4:0] v083523,
input v427380,
output [4:0] v81cd93
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire [0:4] w8;
wire w9;
wire [0:4] w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
assign w1 = v427380;
assign w2 = v427380;
assign w6 = v427380;
assign w8 = v083523;
assign v81cd93 = w10;
assign w13 = v427380;
assign w14 = v427380;
assign w2 = w1;
assign w6 = w1;
assign w6 = w2;
assign w13 = w1;
assign w13 = w2;
assign w13 = w6;
assign w14 = w1;
assign w14 = w2;
assign w14 = w6;
assign w14 = w13;
vba518e v984c00 (
.v0e28cb(w0),
.v3ca442(w2),
.vcbab45(w3)
);
vba518e v63c547 (
.v3ca442(w1),
.vcbab45(w4),
.v0e28cb(w9)
);
vba518e v017827 (
.v0e28cb(w5),
.v3ca442(w6),
.vcbab45(w7)
);
v60f5a9 v3aadcd (
.v3f8943(w0),
.vda577d(w5),
.v427dd1(w8),
.v64d863(w9),
.v53baa6(w11),
.v4f1fd3(w12)
);
v36cddd v6e87bf (
.vee8a83(w3),
.v03aaf0(w4),
.vf8041d(w7),
.v6a2e9e(w10),
.vd84a57(w15),
.v684b0d(w16)
);
vba518e vd994d2 (
.v0e28cb(w12),
.v3ca442(w13),
.vcbab45(w15)
);
vba518e v0bd924 (
.v0e28cb(w11),
.v3ca442(w14),
.vcbab45(w16)
);
endmodule
//---------------------------------------------------
//-- AND-Busen-5
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AND-Busen-5: Enable a 5-bits bus. When the enable signal is 0, the output is 0
//---------------------------------------------------
//---- Top entity
module v60f5a9 (
input [4:0] v427dd1,
output v53baa6,
output v4f1fd3,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:4] w5;
assign v3f8943 = w0;
assign v64d863 = w1;
assign vda577d = w2;
assign v4f1fd3 = w3;
assign v53baa6 = w4;
assign w5 = v427dd1;
v60f5a9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.o2(w2),
.o3(w3),
.o4(w4),
.i(w5)
);
endmodule
//---------------------------------------------------
//-- Bus5-Split-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus5-Split-all: Split the 5-bits bus into its wires
//---------------------------------------------------
module v60f5a9_v9a2a06 (
input [4:0] i,
output o4,
output o3,
output o2,
output o1,
output o0
);
assign o4 = i[4];
assign o3 = i[3];
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module v36cddd (
input v684b0d,
input vd84a57,
input vf8041d,
input vee8a83,
input v03aaf0,
output [4:0] v6a2e9e
);
wire w0;
wire w1;
wire [0:4] w2;
wire w3;
wire w4;
wire w5;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign v6a2e9e = w2;
assign w3 = vf8041d;
assign w4 = vd84a57;
assign w5 = v684b0d;
v36cddd_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.o(w2),
.i2(w3),
.i3(w4),
.i4(w5)
);
endmodule
//---------------------------------------------------
//-- Bus5-Join-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus5-Join-all: Join all the wires into a 5-bits Bus
//---------------------------------------------------
module v36cddd_v9a2a06 (
input i4,
input i3,
input i2,
input i1,
input i0,
output [4:0] o
);
assign o = {i4, i3, i2, i1, i0};
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
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* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module read and write data to the 16x2 Character LCD on the DE2 *
* Board. *
* *
******************************************************************************/
module altera_up_character_lcd_communication (
// Inputs
clk,
reset,
data_in,
enable,
rs,
rw,
display_on,
back_light_on,
// Bidirectionals
LCD_DATA,
// Outputs
LCD_ON,
LCD_BLON,
LCD_EN,
LCD_RS,
LCD_RW,
data_out,
transfer_complete
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Timing info for minimum wait between consecutive communications
// if using a 50MHz Clk
parameter CLOCK_CYCLES_FOR_IDLE_STATE = 7'h7F; // Minimum 2500 ns
parameter IC = 7; // Number of bits for idle counter
parameter IDLE_COUNTER_INCREMENT = 7'h01;
parameter CLOCK_CYCLES_FOR_OPERATION_STATE = 3; // Minimum 40 ns
parameter CLOCK_CYCLES_FOR_ENABLE_STATE = 15; // Minimum 230 ns
parameter CLOCK_CYCLES_FOR_HOLD_STATE = 1; // Minimum 10 ns
parameter SC = 4; // Number of bits for states counter
parameter COUNTER_INCREMENT = 4'h1;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 7: 0] data_in;
input rs;
input rw;
input enable;
input display_on;
input back_light_on;
// Bidirectionals
inout [ 7: 0] LCD_DATA;
// Outputs
output reg LCD_ON;
output reg LCD_BLON;
output reg LCD_EN;
output reg LCD_RS;
output reg LCD_RW;
output reg [ 7: 0] data_out; // Stores data read from the LCD
output reg transfer_complete; // Indicates the end of the transfer
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
parameter LCD_STATE_4_IDLE = 3'h4,
LCD_STATE_0_OPERATION = 3'h0,
LCD_STATE_1_ENABLE = 3'h1,
LCD_STATE_2_HOLD = 3'h2,
LCD_STATE_3_END = 3'h3;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [ 7: 0] data_to_lcd;
reg [IC: 1] idle_counter;
reg [SC: 1] state_0_counter;
reg [SC: 1] state_1_counter;
reg [SC: 1] state_2_counter;
// State Machine Registers
reg [ 2: 0] ns_lcd;
reg [ 2: 0] s_lcd;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_lcd <= LCD_STATE_4_IDLE;
else
s_lcd <= ns_lcd;
end
always @(*)
begin
ns_lcd = LCD_STATE_4_IDLE;
case (s_lcd)
LCD_STATE_4_IDLE:
begin
if ((idle_counter == CLOCK_CYCLES_FOR_IDLE_STATE) & enable)
ns_lcd = LCD_STATE_0_OPERATION;
else
ns_lcd = LCD_STATE_4_IDLE;
end
LCD_STATE_0_OPERATION:
begin
if (state_0_counter == CLOCK_CYCLES_FOR_OPERATION_STATE)
ns_lcd = LCD_STATE_1_ENABLE;
else
ns_lcd = LCD_STATE_0_OPERATION;
end
LCD_STATE_1_ENABLE:
begin
if (state_1_counter == CLOCK_CYCLES_FOR_ENABLE_STATE)
ns_lcd = LCD_STATE_2_HOLD;
else
ns_lcd = LCD_STATE_1_ENABLE;
end
LCD_STATE_2_HOLD:
begin
if (state_2_counter == CLOCK_CYCLES_FOR_HOLD_STATE)
ns_lcd = LCD_STATE_3_END;
else
ns_lcd = LCD_STATE_2_HOLD;
end
LCD_STATE_3_END:
begin
if (enable == 1'b0)
ns_lcd = LCD_STATE_4_IDLE;
else
ns_lcd = LCD_STATE_3_END;
end
default:
begin
ns_lcd = LCD_STATE_4_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
begin
LCD_ON <= 1'b0;
LCD_BLON <= 1'b0;
end
else
begin
LCD_ON <= display_on;
LCD_BLON <= back_light_on;
end
end
always @(posedge clk)
begin
if (reset)
begin
LCD_EN <= 1'b0;
LCD_RS <= 1'b0;
LCD_RW <= 1'b0;
data_out <= 8'h00;
transfer_complete <= 1'b0;
end
else
begin
if (s_lcd == LCD_STATE_1_ENABLE)
LCD_EN <= 1'b1;
else
LCD_EN <= 1'b0;
if (s_lcd == LCD_STATE_4_IDLE)
begin
LCD_RS <= rs;
LCD_RW <= rw;
data_to_lcd <= data_in;
end
if (s_lcd == LCD_STATE_1_ENABLE)
data_out <= LCD_DATA;
if (s_lcd == LCD_STATE_3_END)
transfer_complete <= 1'b1;
else
transfer_complete <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
idle_counter <= {IC{1'b0}};
else if (s_lcd == LCD_STATE_4_IDLE)
idle_counter <= idle_counter + IDLE_COUNTER_INCREMENT;
else
idle_counter <= {IC{1'b0}};
end
always @(posedge clk)
begin
if (reset)
begin
state_0_counter <= {SC{1'b0}};
state_1_counter <= {SC{1'b0}};
state_2_counter <= {SC{1'b0}};
end
else
begin
if (s_lcd == LCD_STATE_0_OPERATION)
state_0_counter <= state_0_counter + COUNTER_INCREMENT;
else
state_0_counter <= {SC{1'b0}};
if (s_lcd == LCD_STATE_1_ENABLE)
state_1_counter <= state_1_counter + COUNTER_INCREMENT;
else
state_1_counter <= {SC{1'b0}};
if (s_lcd == LCD_STATE_2_HOLD)
state_2_counter <= state_2_counter + COUNTER_INCREMENT;
else
state_2_counter <= {SC{1'b0}};
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign LCD_DATA =
(((s_lcd == LCD_STATE_1_ENABLE) ||
(s_lcd == LCD_STATE_2_HOLD)) &&
(LCD_RW == 1'b0)) ? data_to_lcd : 8'hzz;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
//-----------------------------------------------------------------
//
// The original verilog code provided by Clifford E. Cummings,
// Sunburst Design, Inc.
//
// Email: <[email protected]>
// Web: www.sunburst-design.com
//
//----------------------------------------------------------------
module small_async_fifo
#(
parameter DSIZE = 8,
parameter ASIZE = 3,
parameter ALMOST_FULL_SIZE = 5,
parameter ALMOST_EMPTY_SIZE = 3
)
(
//wr interface
output wfull,
output w_almost_full,
input [DSIZE-1:0] wdata,
input winc, wclk, wrst_n,
//rd interface
output [DSIZE-1:0] rdata,
output rempty,
output r_almost_empty,
input rinc, rclk, rrst_n
);
wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
sync_r2w #(ASIZE) sync_r2w (.wq2_rptr(wq2_rptr), .rptr(rptr),
.wclk(wclk), .wrst_n(wrst_n));
sync_w2r #(ASIZE) sync_w2r (.rq2_wptr(rq2_wptr), .wptr(wptr),
.rclk(rclk), .rrst_n(rrst_n));
fifo_mem #(DSIZE, ASIZE) fifo_mem
(.rdata(rdata), .wdata(wdata),
.waddr(waddr), .raddr(raddr),
.wclken(winc), .wfull(wfull),
.wclk(wclk));
rptr_empty #(.ADDRSIZE(ASIZE), .ALMOST_EMPTY_SIZE(ALMOST_EMPTY_SIZE))
rptr_empty
(.rempty(rempty),
.r_almost_empty(r_almost_empty),
.raddr(raddr),
.rptr(rptr),
.rq2_wptr(rq2_wptr),
.rinc(rinc),
.rclk(rclk),
.rrst_n(rrst_n));
wptr_full #(.ADDRSIZE(ASIZE), .ALMOST_FULL_SIZE(ALMOST_FULL_SIZE))
wptr_full
(.wfull(wfull),
.w_almost_full(w_almost_full),
.waddr(waddr),
.wptr(wptr),
.wq2_rptr(wq2_rptr),
.winc(winc),
.wclk(wclk),
.wrst_n(wrst_n));
endmodule // small_async_fifo
module sync_r2w #(parameter ADDRSIZE = 3)
(output reg [ADDRSIZE:0] wq2_rptr,
input [ADDRSIZE:0] rptr,
input wclk, wrst_n);
reg [ADDRSIZE:0] wq1_rptr;
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0;
else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};
endmodule // sync_r2w
module sync_w2r #(parameter ADDRSIZE = 3)
(output reg [ADDRSIZE:0] rq2_wptr,
input [ADDRSIZE:0] wptr,
input rclk, rrst_n);
reg [ADDRSIZE:0] rq1_wptr;
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rq2_wptr,rq1_wptr} <= 0;
else {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};
endmodule // sync_w2r
module rptr_empty
#(parameter ADDRSIZE = 3,
parameter ALMOST_EMPTY_SIZE=3)
(output reg rempty,
output reg r_almost_empty,
output [ADDRSIZE-1:0] raddr,
output reg [ADDRSIZE :0] rptr,
input [ADDRSIZE :0] rq2_wptr,
input rinc, rclk, rrst_n);
reg [ADDRSIZE:0] rbin;
wire [ADDRSIZE:0] rgraynext, rbinnext;
reg [ADDRSIZE :0] rq2_wptr_bin;
integer i;
//------------------
// GRAYSTYLE2 pointer
//------------------
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rbin, rptr} <= 0;
else {rbin, rptr} <= {rbinnext, rgraynext};
// Memory read-address pointer (okay to use binary to address memory)
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + (rinc & ~rempty);
assign rgraynext = (rbinnext>>1) ^ rbinnext;
//--------------------------------------------------------------
// FIFO empty when the next rptr == synchronized wptr or on reset
//--------------------------------------------------------------
wire rempty_val = (rgraynext == rq2_wptr);
// Gray code to Binary code conversion
always @(rq2_wptr)
for (i=0; i<(ADDRSIZE+1); i=i+1)
rq2_wptr_bin[i] = ^ (rq2_wptr >> i);
wire [ADDRSIZE:0] subtract = (rbinnext + ALMOST_EMPTY_SIZE)-rq2_wptr_bin;
wire r_almost_empty_val = ~subtract[ADDRSIZE];
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) begin
rempty <= 1'b1;
r_almost_empty <= 1'b 1;
end
else begin
rempty <= rempty_val;
r_almost_empty <= r_almost_empty_val;
end
endmodule // rptr_empty
module wptr_full
#(parameter ADDRSIZE = 3,
parameter ALMOST_FULL_SIZE=5
)
(output reg wfull,
output reg w_almost_full,
output [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE :0] wptr,
input [ADDRSIZE :0] wq2_rptr,
input winc, wclk, wrst_n);
reg [ADDRSIZE:0] wbin;
wire [ADDRSIZE:0] wgraynext, wbinnext;
reg [ADDRSIZE :0] wq2_rptr_bin;
integer i;
// GRAYSTYLE2 pointer
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wbin, wptr} <= 0;
else {wbin, wptr} <= {wbinnext, wgraynext};
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + (winc & ~wfull);
assign wgraynext = (wbinnext>>1) ^ wbinnext;
//-----------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//-----------------------------------------------------------------
wire wfull_val = (wgraynext ==
{~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
// Gray code to Binary code conversion
always @(wq2_rptr)
for (i=0; i<(ADDRSIZE+1); i=i+1)
wq2_rptr_bin[i] = ^ (wq2_rptr >> i);
wire [ADDRSIZE :0] subtract = wbinnext - wq2_rptr_bin - ALMOST_FULL_SIZE;
wire w_almost_full_val = ~subtract[ADDRSIZE];
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) begin
wfull <= 1'b0;
w_almost_full <= 1'b 0;
end
else begin
wfull <= wfull_val;
w_almost_full <= w_almost_full_val;
end
endmodule // wptr_full
module fifo_mem #(parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 3) // Number of mem address bits
(output [DATASIZE-1:0] rdata,
input [DATASIZE-1:0] wdata,
input [ADDRSIZE-1:0] waddr, raddr,
input wclken, wfull, wclk);
// RTL Verilog memory model
localparam DEPTH = 1<<ADDRSIZE;
reg [DATASIZE-1:0] mem [0:DEPTH-1];
assign rdata = mem[raddr];
always @(posedge wclk)
if (wclken && !wfull) mem[waddr] <= wdata;
endmodule // fifo_mem
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 9
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module block_design_m01_regslice_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_9_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(7),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(7)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H1),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H1),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Drawing Engine Data Path
// File : ded_top.v
// Author : Frank Bruno
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This is the Drawing Engine Data path 2D only
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module ded_top
#(parameter BYTES = 16)
(
// Global Signals
input de_clk, // Drawing Engine Clock
de_rstn, // Drawing Engine Reset
// Host/ XY Windows
input hb_clk, // host bus clock
hb_rstn, // host bus reset
input [12:2] hb_adr, // host bus lower address bits
input hb_we, // host bus write strobe
input hb_xyw_csn, // chip select for XY window
// DEX related
input dx_mem_req, // memory request
dx_mem_rd, // memory read
dx_line_actv_2, // line command active signal
dx_blt_actv_2, // bit blt active signal
input dx_pc_ld, // load pixel cache
input [31:0] dx_clpx_bus_2, // clipping X values
input dx_rstn_wad, // load cache write address
input dx_ld_rad, // load cache read address
input dx_ld_rad_e, // load cache read address
input dx_sol_2, // start of line flag
dx_eol_2, // end of line flag
input dx_ld_msk, // load mask.{ld_start,ld_end,
// ld_lftclp,ld_rhtclp}
input [9:0] dx_xalu, // lower four bits of the X alu.
input [15:0] srcx, // lower five bits from the destination X
input [15:0] srcy, // lower five bits from the destination X
input [15:0] dsty, // lower five bits from the destination Y
input [15:0] dx_dstx, // Current X for blts and xfers.
input dx_fg_bgn, // fore/back ground bit for line pat.
input clip, // Clip indicator. PIPED SIGNAL
input [4:0] xpat_ofs, // X off set for patterns.
input [4:0] ypat_ofs, // Y off set for patterns.
input [15:0] real_dstx, // X destination.
input [15:0] real_dsty, // Y destination.
input ld_initial, // load the initial color value.
input pc_msk_last, // Mask the last pixel for nolast
input last_pixel, // Last Pixel from Jim (Not Clean)
input ld_wcnt,
input [3:0] fx_1,
input rmw,
// Memory Controller Inputs
input mclock, // memory controller clock
input mc_popen, // memory controller pop enable
input mc_push, // push data into fifo from MC.
mc_eop, // end of page cycle pulse, from MC
mc_eop4, // end of page cycle pulse, from MC
input de_pc_pop, // Pop from PC
// Level 2 Registers
input [3:0] de_pln_msk_2, // Plane mask bits
input dr_solid_2, // solid mode bit
dr_trnsp_2, // transparent mode bit
input [1:0] stpl_2, // stipple mode bit 01 = planar, 10 = packed
input [1:0] dr_apat_2, // area mode bits 01 = 8x8, 10 = 32x32
input [1:0] dr_clp_2, // lower two bits of the clipping register
input [31:0] fore_2, // foreground register output
input [31:0] back_2, // background register output
input dr_sen_2, // Source enable bits
input y_clip_2, // Inside the Y clipping boundries
input ps8_2, // pixel size equals eight
ps16_2, // pixel size equals sixteen
ps32_2, // pixel size equals thirty-two
input [1:0] bc_lvl_2, // Y page request limit
input hb_write,
input [27:0] dorg_2, // Destination origin.
input [27:0] sorg_2, // Source origin.
input [27:0] z_org, // Z origin
input [11:0] dptch_2, // destination pitch.
input [11:0] sptch_2, // source pitch.
input [11:0] z_ptch, // Z pitch
input [1:0] ps_2, // Pixel size to MC
input [3:0] bsrcr_2, // Source blending function.
input [2:0] bdstr_2, // Destination blending function.
input blend_en_2, // Blending enable.
input [1:0] blend_reg_en_2,// Select blending registers or alpha from FB
input [7:0] bsrc_alpha_2, // Source alpha data.
input [7:0] bdst_alpha_2, // Destination alpha data.
input [3:0] rop_2, // Raster operation.
input [31:0] kcol_2, // Key Color.
input [2:0] key_ctrl_2, // Key control.
input [2:0] frst8_2, // used to be in dex
// Memory Controller Outputs
output [BYTES-1:0] mc_pixel_msk, // pixel mask data output
output [(BYTES<<3)-1:0] mc_fb_out, // frame buffer data output
output [(BYTES<<2)-1:0] mc_fb_a, // frame buffer data output
output pc_mc_busy, // gated MC busy for Jim
output [31:0] de_mc_address, // Line/ Blt linear address
output de_mc_read,
output de_mc_rmw,
output [3:0] de_mc_wcnt,
output de_pc_empty,
output pc_empty,
// Host Bus
output [31:0] hb_dout, // Host read back data.
// ded_ca_top memory interface
`ifdef BYTE16 output [3:0] ca_enable,
`elsif BYTE8 output [1:0] ca_enable,
`else output ca_enable, `endif
output [4:0] hb_ram_addr,
output [4:0] ca_ram_addr0,
output [4:0] ca_ram_addr1,
input [(BYTES*8)-1:0] hb_dout_ram,
input [(BYTES<<3)-1:0] ca_dout0,
input [(BYTES<<3)-1:0] ca_dout1,
// Drawing Engine
output pc_dirty, // data is left in the pixel cache
output clip_ind, // Clipping indicator.
output stpl_pk_4, // packed stipple bit, level four
output pc_mc_rdy, // Ready signal from PC to DX
output pipe_pending, // There is something in the PC or pipe
output line_actv_4,
output [1:0] ps_4,
output [3:0] bsrcr_4, // Source blending function.
output [2:0] bdstr_4, // Destination blending function.
output blend_en_4, // Blending enable.
output [1:0] blend_reg_en_4, // Blending register enables
output [7:0] bsrc_alpha_4, // Source alpha data.
output [7:0] bdst_alpha_4, // Destination alpha data.
output [3:0] rop_4, // Raster operation.
output [31:0] kcol_4, // Key Color.
output [2:0] key_ctrl_4, // Key control.
////////////////////////////////////////////////////////
// 3D Interface.
output pc_busy_3d,
input valid_3d,
input fg_bgn_3d,
input msk_last_3d,
input [15:0] x_out_3d,
input [15:0] y_out_3d,
input last_3d,
input [31:0] pixel_3d,
input [31:0] z_3d,
input [4:0] z_ctrl,
input active_3d_2,
input [7:0] alpha_3d,
output pc_last,
output [4:0] z_ctrl_4,
output [31:0] z_address_4,
output [(BYTES*8)-1:0] z_out
);
wire [(BYTES<<3)-1:0] de_pc_data;
wire [(BYTES<<2)-1:0] de_pc_a;
wire [BYTES-1:0] de_pc_mask;
wire [1:0] clp_4;
wire [31:0] fore_4; // foreground register output
wire [31:0] back_4; // foreground register output
/************************************************************************/
/* CREATE INTERNAL WIRE BUSSES */
/************************************************************************/
wire [(BYTES<<3)-1:0] ca_din; /* Data into cache. */
wire [BYTES-1:0] cx_sel; /* color expand selector. */
wire [BYTES-1:0] trns_msk; /* transparentcy mask. */
wire [9:0] ca_rad; /* Cache read address. */
wire [7:0] ca_wr_en; /* Cache write enables. */
wire [1:0] apat_4;
wire [2:0] psize_4;
wire [1:0] stpl_4;
wire [8:0] x_bitmask; /* muxed input bitmask to texel cache */
wire [8:0] y_bitmask; /* muxed input bitmask to texel cache */
wire ca_src_2 = dr_sen_2;
reg xyw_csn_d;
`ifdef BYTE16 wire [2:0] ca_mc_addr;
`elsif BYTE8 wire [3:0] ca_mc_addr;
`else wire [4:0] ca_mc_addr;
`endif
wire sol_3;
wire ps32_4;
wire ps16_4;
wire ps8_4;
wire solid_4;
wire blt_actv_4;
wire trnsp_4;
wire eol_4;
wire pc_busy;
wire [3:0] mask_4;
wire rad_flg_2, rad_flg_3;
wire [2:0] strt_wrd_2;
wire [3:0] strt_byt_2;
wire [2:0] strt_bit_2;
wire [2:0] strt_wrd_3;
wire [3:0] strt_byt_3;
wire [2:0] strt_bit_3;
wire [2:0] strt_wrd_4;
wire [3:0] strt_byt_4;
wire [2:0] strt_bit_4;
wire [6:0] lft_enc_2;
wire [6:0] rht_enc_2;
wire [11:0] clp_min_2; // left clipping pointer
wire [11:0] clp_max_2; // right clipping pointer
wire [3:0] cmin_enc_2;
wire [3:0] cmax_enc_2;
wire [6:0] lft_enc_4;
wire [6:0] rht_enc_4;
wire [11:0] clp_min_4; // left clipping pointer
wire [11:0] clp_max_4; // right clipping pointer
wire [3:0] cmin_enc_4;
wire [3:0] cmax_enc_4;
wire y_clip_4;
wire sol_4;
wire [13:0] x_bus_4;
wire mc_read_3;
wire rst_wad_flg_2, rst_wad_flg_3;
wire [2:0] frst8_4;
wire mc_acken;
assign stpl_pk_4 = stpl_4[1];
assign pc_mc_rdy = ~pc_busy;
/****************************************************************/
/* DATAPATH CACHE CONTROLLER */
/****************************************************************/
ded_cactrl
#(.BYTES (BYTES)) U_CACTRL
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.mc_read_4 (mc_read_3),
.mc_push (mc_push),
.mclock (mclock),
//.mc_popen (mc_popen & blt_actv_4 & ~solid_4),
.mc_popen (mc_popen),
.mc_acken (mc_acken),
.irst_wad (dx_rstn_wad),
.ld_rad (dx_ld_rad),
.ld_rad_e (dx_ld_rad_e),
.x_adr (dx_xalu),
.srcx (srcx[8:0]),
.dsty (dsty[4:0]),
.dstx (dx_dstx[6:0]),
.lt_actv_4 (line_actv_4),
.stpl_2 (stpl_2),
.stpl_4 (stpl_4),
.apat_2 (dr_apat_2),
.apat_4 (apat_4),
.ps8_2 (ps8_2),
.ps16_2 (ps16_2),
.ps32_2 (ps32_2),
.psize_4 (psize_4),
//.mc_eop (mc_eop & blt_actv_4 & ~solid_4),
.mc_eop (mc_eop),
.eol_4 (eol_4),
.ofset (srcx[2:0]),
.frst8_4 (frst8_4),
.sol_3 (sol_3),
//.mem_req (dx_mem_req & dx_blt_actv_2),
.mem_req (dx_mem_req),
.mem_rd (dx_mem_rd),
.xpat_ofs (xpat_ofs),
.ypat_ofs (ypat_ofs),
.ca_src_2 (ca_src_2),
.rad_flg_2 (rad_flg_2),
.strt_wrd_3 (strt_wrd_3),
.strt_byt_3 (strt_byt_3),
.strt_bit_3 (strt_bit_3),
.strt_wrd_4 (strt_wrd_4),
.strt_byt_4 (strt_byt_4),
.strt_bit_4 (strt_bit_4),
.rst_wad_flg_3 (rst_wad_flg_3),
.rad_flg_3 (rad_flg_3),
.strt_wrd_2 (strt_wrd_2),
.strt_byt_2 (strt_byt_2),
.strt_bit_2 (strt_bit_2),
.rst_wad_flg_2 (rst_wad_flg_2),
.ca_rad (ca_rad),
.ca_mc_addr (ca_mc_addr)
);
/****************************************************************/
/* DATAPATH DATA CACHE */
/****************************************************************/
ded_ca_top
#(.BYTES (BYTES)) U_CA_TOP
(
.mclock (mclock),
.mc_push (mc_push),
.mc_addr (ca_mc_addr),
.hclock (hb_clk),
.hb_we (hb_we & ~hb_xyw_csn), // fixme??? is this needed
.hb_addr (hb_adr[6:2]),
.hb_dout_ram (hb_dout_ram),
`ifdef BYTE16 .rad (ca_rad[9:7]),
`elsif BYTE8 .rad (ca_rad[9:6]),
`else .rad (ca_rad[9:5]), `endif
.ca_enable (ca_enable),
.hb_dout (hb_dout),
.hb_ram_addr (hb_ram_addr),
.ca_ram_addr0 (ca_ram_addr0),
.ca_ram_addr1 (ca_ram_addr1)
);
// always @ (posedge hb_clk) xyw_csn_d <= hb_xyw_csn;
/****************************************************************/
/* DATAPATH FUNNEL SHIFTER */
/* DATAPATH COLOR SELECTOR */
/* (grouped for synthesis) */
/****************************************************************/
ded_funcol
#(.BYTES (BYTES)) U_FUNCOL
(
.mclock (mclock),
.stpl_4 (stpl_4),
.apat_4 (apat_4),
.ps32_4 (ps32_4),
.ps16_4 (ps16_4),
.ps8_4 (ps8_4),
.lt_actv_4 (line_actv_4),
.fore_4 (fore_4),
.back_4 (back_4),
.solid_4 (solid_4),
.pc_col (de_pc_data),
`ifdef BYTE16 .rad (ca_rad[6:0]),
`elsif BYTE8 .rad (ca_rad[5:0]),
`else .rad (ca_rad[4:0]), `endif
.bsd0 (ca_dout0),
.bsd1 (ca_dout1),
.col_dat (mc_fb_out),
.trns_msk (trns_msk),
.cx_sel (cx_sel)
);
/****************************************************************/
/* MASK GENERATOR */
/****************************************************************/
ded_mskgen
#(.BYTES (BYTES)) U_MSKGEN
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.mclock (mclock),
.mc_acken (mc_acken),
.mc_popen (mc_popen),
.ld_msk (dx_ld_msk),
.line_actv_4 (line_actv_4),
.blt_actv_4 (blt_actv_4),
.clp_4 (clp_4),
.mem_req (dx_mem_req),
.mem_rd (dx_mem_rd),
.pc_msk_in (de_pc_mask),
.clpx_bus_2 (dx_clpx_bus_2),
.x_bus (dx_dstx),
.xalu_bus (dx_xalu[6:0]),
.trnsp_4 (trnsp_4),
.trns_msk_in (trns_msk),
.ps16_2 (ps16_2),
.ps32_2 (ps32_2),
.mc_eop (mc_eop),
.mask_4 (mask_4),
.lft_enc_4 (lft_enc_4),
.rht_enc_4 (rht_enc_4),
.clp_min_4 (clp_min_4),
.clp_max_4 (clp_max_4),
.cmin_enc_4 (cmin_enc_4),
.cmax_enc_4 (cmax_enc_4),
.y_clip_4 (y_clip_4),
.sol_4 (sol_4),
.eol_4 (eol_4),
.x_count_4 (x_bus_4),
.mc_eop4 (mc_eop4),
.pixel_msk (mc_pixel_msk),
.clip_ind (clip_ind),
.lft_enc_2 (lft_enc_2),
.rht_enc_2 (rht_enc_2),
.clp_min_2 (clp_min_2),
.clp_max_2 (clp_max_2),
.cmin_enc_2 (cmin_enc_2),
.cmax_enc_2 (cmax_enc_2)
);
/****************************************************************/
/* LINE PIXEL CACHE */
/****************************************************************/
ded_pix_cache
#(.BYTES (BYTES)) U_PIX
(
.de_clk (de_clk),
.mc_clk (mclock),
// .de_rstn (de_rstn),
.de_rstn (hb_rstn),
.dorg_2 (dorg_2),
.sorg_2 (sorg_2),
.dptch_2 (dptch_2),
.sptch_2 (sptch_2),
.ld_wcnt (ld_wcnt),
.fx_1 (fx_1),
.rmw (rmw),
.ps8_2 (ps8_2),
.ps16_2 (ps16_2),
.ps32_2 (ps32_2),
.fore_2 (fore_2),
.back_2 (back_2),
.solid_2 (dr_solid_2),
.dr_trnsp_2 (dr_trnsp_2),
// 2D Interface.
.dx_pc_ld (dx_pc_ld),
.dx_clip (clip),
.dx_real_dstx (real_dstx),
.dx_real_dsty (real_dsty),
.dx_pc_msk_last (pc_msk_last),
.dx_fg_bgn (dx_fg_bgn),
.dx_last_pixel (last_pixel),
// 3D Interface.
`ifdef CORE_3D
.valid_3d (valid_3d),
.fg_bgn_3d (fg_bgn_3d),
.x_out_3d (x_out_3d),
.y_out_3d (y_out_3d),
.pc_msk_last_3d (msk_last_3d),
.pc_last_3d (last_3d),
.pixel_3d (pixel_3d),
.z_3d (z_3d),
.alpha_3d (alpha_3d),
.z_op (z_ctrl[2:0]),
.z_en (z_ctrl[3]),
.z_ro (z_ctrl[4]),
.zorg_2 (z_org),
.zptch_2 (z_ptch),
.active_3d_2 (active_3d_2),
`else
.valid_3d (1'b0),
.fg_bgn_3d (1'b0),
.x_out_3d (16'h0),
.y_out_3d (16'h0),
.pc_msk_last_3d (1'b0),
.pc_last_3d (1'b0),
.pixel_3d (32'h0),
.alpha_3d (8'h0),
.z_op (3'b0),
.z_en (1'b0),
.z_ro (1'b0),
.zorg_2 (28'b0),
.zptch_2 (12'b0),
.active_3d_2 (1'b0),
`endif
//
.de_pc_pop (de_pc_pop),
.mc_popen (mc_popen),
.srcx (srcx),
.srcy (srcy),
.dstx (dx_dstx),
.dsty (dsty),
.imem_rd (dx_mem_rd),
.dx_mem_req (dx_mem_req),
.mask_2 (de_pln_msk_2),
.stpl_2 (stpl_2),
.dr_apat_2 (dr_apat_2),
.dr_clp_2 (dr_clp_2),
.rad_flg_2 (rad_flg_2),
.strt_wrd_2 (strt_wrd_2),
.strt_byt_2 (strt_byt_2),
.strt_bit_2 (strt_bit_2),
.ps_2 (ps_2),
.bsrcr_2 (bsrcr_2),
.bdstr_2 (bdstr_2),
.blend_en_2 (blend_en_2),
.blend_reg_en_2 (blend_reg_en_2),
.bsrc_alpha_2 (bsrc_alpha_2),
.bdst_alpha_2 (bdst_alpha_2),
.rop_2 (rop_2),
.kcol_2 (kcol_2),
.key_ctrl_2 (key_ctrl_2),
.lft_enc_2 (lft_enc_2),
.rht_enc_2 (rht_enc_2),
.clp_min_2 (clp_min_2),
.clp_max_2 (clp_max_2),
.cmin_enc_2 (cmin_enc_2),
.cmax_enc_2 (cmax_enc_2),
.y_clip_2 (y_clip_2),
.sol_2 (dx_sol_2),
.eol_2 (dx_eol_2),
.rst_wad_flg_2 (rst_wad_flg_2),
.frst8_2 (frst8_2),
.rad_flg_3 (rad_flg_3),
.strt_wrd_3 (strt_wrd_3),
.strt_byt_3 (strt_byt_3),
.strt_bit_3 (strt_bit_3),
.strt_wrd_4 (strt_wrd_4),
.strt_byt_4 (strt_byt_4),
.strt_bit_4 (strt_bit_4),
.px_a (mc_fb_a),
.px_col (de_pc_data),
.px_msk_color (de_pc_mask),
.de_mc_address (de_mc_address),
.de_mc_read (de_mc_read),
.de_mc_rmw (de_mc_rmw),
.de_mc_wcnt (de_mc_wcnt),
.pc_dirty (pc_dirty),
.de_pc_empty (de_pc_empty),
.pc_pending (pipe_pending),
.pc_busy (pc_busy),
.pc_busy_3d (pc_busy_3d),
.fore_4 (fore_4),
.back_4 (back_4),
.blt_actv_4 (blt_actv_4),
.stpl_4 (stpl_4),
.ps8_4 (ps8_4),
.ps16_4 (ps16_4),
.ps32_4 (ps32_4),
.trnsp_4 (trnsp_4),
.solid_4 (solid_4),
.clp_4 (clp_4),
.line_actv_4 (line_actv_4),
.apat_4 (apat_4),
.mask_4 (mask_4),
.ps_4 (ps_4),
.bsrcr_4 (bsrcr_4),
.bdstr_4 (bdstr_4),
.blend_en_4 (blend_en_4),
.blend_reg_en_4 (blend_reg_en_4),
.bsrc_alpha_4 (bsrc_alpha_4),
.bdst_alpha_4 (bdst_alpha_4),
.rop_4 (rop_4),
.kcol_4 (kcol_4),
.key_ctrl_4 (key_ctrl_4),
.lft_enc_4 (lft_enc_4),
.rht_enc_4 (rht_enc_4),
.clp_min_4 (clp_min_4),
.clp_max_4 (clp_max_4),
.cmin_enc_4 (cmin_enc_4),
.cmax_enc_4 (cmax_enc_4),
.y_clip_4 (y_clip_4),
.sol_4 (sol_4),
.eol_4 (eol_4),
.x_bus_4 (x_bus_4),
.rst_wad_flg_3 (rst_wad_flg_3),
.mc_read_3 (mc_read_3),
.sol_3 (sol_3),
.mc_acken (mc_acken),
.frst8_4 (frst8_4),
.pc_empty (pc_empty),
.pc_last (pc_last),
.z_en_4 (z_ctrl_4[3]),
.z_ro_4 (z_ctrl_4[4]),
.z_op_4 (z_ctrl_4[2:0]),
.z_address_4 (z_address_4),
.z_out (z_out)
);
assign pc_mc_busy = pc_busy;
assign psize_4 = {ps32_4,ps16_4,ps8_4}; // Needed for cactrl
endmodule
|
/**************************************************************************
*
* File Name: MT48LC4M16A2.V
* Version: 2.1
* Date: June 6th, 2002
* Model: BUS Functional
* Simulator: Model Technology
*
* Dependencies: None
*
* Email: [email protected]
* Company: Micron Technology, Inc.
* Model: MT48LC4M16A2 (1Meg x 16 x 4 Banks)
*
* Description: Micron 64Mb SDRAM Verilog model
*
* Limitation: - Doesn't check for 4096 cycle refresh
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
*
* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
* Copyright © 2001 Micron Semiconductor Products, Inc.
* All rights researved
*
* Rev Author Date Changes
* --- -------------------------- ---------------------------------------
* 2.1 SH 06/06/2002 - Typo in bank multiplex
* Micron Technology Inc.
*
* 2.0 SH 04/30/2002 - Second release
* Micron Technology Inc.
*
**************************************************************************/
`timescale 1ns / 1ps
module mt48lc4m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
parameter addr_bits = 12;
parameter data_bits = 16;
parameter col_bits = 8;
parameter mem_sizes = 1048575;
inout [data_bits - 1 : 0] Dq;
input [addr_bits - 1 : 0] Addr;
input [1 : 0] Ba;
input Clk;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [1 : 0] Dqm;
reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
reg [1 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline
reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
reg [addr_bits - 1 : 0] Mode_reg;
reg [data_bits - 1 : 0] Dq_reg, Dq_dqm;
reg [col_bits - 1 : 0] Col_temp, Burst_counter;
reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge
reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command
reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks)
reg Auto_precharge [0 : 3]; // RW Auto Precharge (Bank)
reg Read_precharge [0 : 3]; // R Auto Precharge
reg Write_precharge [0 : 3]; // W Auto Precharge
reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge
reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge
reg [1 : 0] RW_interrupt_bank; // RW Interrupt Bank
integer RW_interrupt_counter [0 : 3]; // RW Interrupt Counter
integer Count_precharge [0 : 3]; // RW Auto Precharge Counter
reg Data_in_enable;
reg Data_out_enable;
reg [1 : 0] Bank, Prev_bank;
reg [addr_bits - 1 : 0] Row;
reg [col_bits - 1 : 0] Col, Col_brst;
// Internal system clock
reg CkeZ, Sys_clk;
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
// Burst Length Decode
wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0];
wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
wire Burst_length_f = Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
// CAS Latency Decode
wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
// Write Burst Mode
wire Write_burst_mode = Mode_reg[9];
wire Debug = 1'b1; // Debug messages : 1 = On
wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
assign Dq = Dq_reg; // DQ buffer
// Commands Operation
`define ACT 0
`define NOP 1
`define READ 2
`define WRITE 3
`define PRECH 4
`define A_REF 5
`define BST 6
`define LMR 7
// Timing Parameters for -7E PC133 CL2
parameter tAC = 5.4;
parameter tHZ = 5.4;
parameter tOH = 3.0;
parameter tMRD = 2.0; // 2 Clk Cycles
parameter tRAS = 37.0;
parameter tRC = 60.0;
parameter tRCD = 15.0;
parameter tRFC = 66.0;
parameter tRP = 15.0;
parameter tRRD = 14.0;
parameter tWRa = 7.0; // A2 Version - Auto precharge mode (1 Clk + 7 ns)
parameter tWRm = 14.0; // A2 Version - Manual precharge mode (14 ns)
// Timing Check variable
time MRD_chk;
time WR_chkm [0 : 3];
time RFC_chk, RRD_chk;
time RC_chk0, RC_chk1, RC_chk2, RC_chk3;
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
initial begin
Dq_reg = {data_bits{1'bz}};
Data_in_enable = 0; Data_out_enable = 0;
Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
WR_chkm[0] = 0; WR_chkm[1] = 0; WR_chkm[2] = 0; WR_chkm[3] = 0;
RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0;
RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0;
MRD_chk = 0; RFC_chk = 0; RRD_chk = 0;
RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
$timeformat (-9, 1, " ns", 12);
end
// System clock generator
always begin
@ (posedge Clk) begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@ (negedge Clk) begin
Sys_clk = 1'b0;
end
end
always @ (posedge Sys_clk) begin
// Internal Commamd Pipelined
Command[0] = Command[1];
Command[1] = Command[2];
Command[2] = Command[3];
Command[3] = `NOP;
Col_addr[0] = Col_addr[1];
Col_addr[1] = Col_addr[2];
Col_addr[2] = Col_addr[3];
Col_addr[3] = {col_bits{1'b0}};
Bank_addr[0] = Bank_addr[1];
Bank_addr[1] = Bank_addr[2];
Bank_addr[2] = Bank_addr[3];
Bank_addr[3] = 2'b0;
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = 2'b0;
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = 1'b0;
// Dqm pipeline for Read
Dqm_reg0 = Dqm_reg1;
Dqm_reg1 = Dqm;
// Read or Write with Auto Precharge Counter
if (Auto_precharge[0] === 1'b1) begin
Count_precharge[0] = Count_precharge[0] + 1;
end
if (Auto_precharge[1] === 1'b1) begin
Count_precharge[1] = Count_precharge[1] + 1;
end
if (Auto_precharge[2] === 1'b1) begin
Count_precharge[2] = Count_precharge[2] + 1;
end
if (Auto_precharge[3] === 1'b1) begin
Count_precharge[3] = Count_precharge[3] + 1;
end
// Read or Write Interrupt Counter
if (RW_interrupt_write[0] === 1'b1) begin
RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1;
end
if (RW_interrupt_write[1] === 1'b1) begin
RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1;
end
if (RW_interrupt_write[2] === 1'b1) begin
RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1;
end
if (RW_interrupt_write[3] === 1'b1) begin
RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1;
end
// tMRD Counter
MRD_chk = MRD_chk + 1;
// Auto Refresh
if (Aref_enable === 1'b1) begin
if (Debug) begin
$display ("%m : at time %t AREF : Auto Refresh", $time);
end
// Auto Refresh to Auto Refresh
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time);
end
// Precharge to Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
end
// Load Mode Register to Auto Refresh
if (MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time);
end
// Record Current tRFC time
RFC_chk = $time;
end
// Load Mode Register
if (Mode_reg_enable === 1'b1) begin
// Register Mode
Mode_reg = Addr;
// Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode
if (Debug) begin
$display ("%m : at time %t LMR : Load Mode Register", $time);
// CAS Latency
case (Addr[6 : 4])
3'b010 : $display ("%m : CAS Latency = 2");
3'b011 : $display ("%m : CAS Latency = 3");
default : $display ("%m : CAS Latency = Reserved");
endcase
// Burst Length
case (Addr[2 : 0])
3'b000 : $display ("%m : Burst Length = 1");
3'b001 : $display ("%m : Burst Length = 2");
3'b010 : $display ("%m : Burst Length = 4");
3'b011 : $display ("%m : Burst Length = 8");
3'b111 : $display ("%m : Burst Length = Full");
default : $display ("%m : Burst Length = Reserved");
endcase
// Burst Type
if (Addr[3] === 1'b0) begin
$display ("%m : Burst Type = Sequential");
end else if (Addr[3] === 1'b1) begin
$display ("%m : Burst Type = Interleaved");
end else begin
$display ("%m : Burst Type = Reserved");
end
// Write Burst Mode
if (Addr[9] === 1'b0) begin
$display ("%m : Write Burst Mode = Programmed Burst Length");
end else if (Addr[9] === 1'b1) begin
$display ("%m : Write Burst Mode = Single Location Access");
end else begin
$display ("%m : Write Burst Mode = Reserved");
end
end
// Precharge to Load Mode Register
if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin
$display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
end
// Precharge to Load Mode Register
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time);
end
// Auto Refresh to Load Mode Register
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $time);
end
// Load Mode Register to Load Mode Register
if (MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time);
end
// Reset MRD Counter
MRD_chk = 0;
end
// Active Block (Latch Bank Address and Row Address)
if (Active_enable === 1'b1) begin
// Activate an open bank can corrupt data
if ((Ba === 2'b00 && Act_b0 === 1'b1) || (Ba === 2'b01 && Act_b1 === 1'b1) ||
(Ba === 2'b10 && Act_b2 === 1'b1) || (Ba === 2'b11 && Act_b3 === 1'b1)) begin
$display ("%m : at time %t ERROR: Bank already activated -- data can be corrupted", $time);
end
// Activate Bank 0
if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 0 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk0 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time);
end
// Precharge to Activate Bank 0
if ($time - RP_chk0 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time);
end
// Record variables
Act_b0 = 1'b1;
Pc_b0 = 1'b0;
B0_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk0 = $time;
RC_chk0 = $time;
RCD_chk0 = $time;
end
if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 1 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk1 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time);
end
// Precharge to Activate Bank 1
if ($time - RP_chk1 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time);
end
// Record variables
Act_b1 = 1'b1;
Pc_b1 = 1'b0;
B1_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk1 = $time;
RC_chk1 = $time;
RCD_chk1 = $time;
end
if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 2 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk2 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time);
end
// Precharge to Activate Bank 2
if ($time - RP_chk2 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time);
end
// Record variables
Act_b2 = 1'b1;
Pc_b2 = 1'b0;
B2_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk2 = $time;
RC_chk2 = $time;
RCD_chk2 = $time;
end
if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
// Debug Message
if (Debug) begin
$display ("%m : at time %t ACT : Bank = 3 Row = %d", $time, Addr);
end
// ACTIVE to ACTIVE command period
if ($time - RC_chk3 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time);
end
// Precharge to Activate Bank 3
if ($time - RP_chk3 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time);
end
// Record variables
Act_b3 = 1'b1;
Pc_b3 = 1'b0;
B3_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk3 = $time;
RC_chk3 = $time;
RCD_chk3 = $time;
end
// Active Bank A to Active Bank B
if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
end
// Auto Refresh to Activate
if ($time - RFC_chk < tRFC) begin
$display ("%m : at time %t ERROR: tRFC violation during Activate bank = %d", $time, Ba);
end
// Load Mode Register to Active
if (MRD_chk < tMRD ) begin
$display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
end
// Record variables for checking violation
RRD_chk = $time;
Prev_bank = Ba;
end
// Precharge Block
if (Prech_enable == 1'b1) begin
// Load Mode Register to Precharge
if ($time - MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time);
end
// Precharge Bank 0
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
Act_b0 = 1'b0;
Pc_b0 = 1'b1;
RP_chk0 = $time;
// Activate to Precharge
if ($time - RAS_chk0 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[0] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 1
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
Act_b1 = 1'b0;
Pc_b1 = 1'b1;
RP_chk1 = $time;
// Activate to Precharge
if ($time - RAS_chk1 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[1] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 2
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
Act_b2 = 1'b0;
Pc_b2 = 1'b1;
RP_chk2 = $time;
// Activate to Precharge
if ($time - RAS_chk2 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[2] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge Bank 3
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
Act_b3 = 1'b0;
Pc_b3 = 1'b1;
RP_chk3 = $time;
// Activate to Precharge
if ($time - RAS_chk3 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for write
if ($time - WR_chkm[3] < tWRm) begin
$display ("%m : at time %t ERROR: tWR violation during Precharge", $time);
end
end
// Terminate a Write Immediately (if same bank or all banks)
if (Data_in_enable === 1'b1 && (Bank === Ba || Addr[10] === 1'b1)) begin
Data_in_enable = 1'b0;
end
// Precharge Command Pipeline for Read
if (Cas_latency_3 === 1'b1) begin
Command[2] = `PRECH;
Bank_precharge[2] = Ba;
A10_precharge[2] = Addr[10];
end else if (Cas_latency_2 === 1'b1) begin
Command[1] = `PRECH;
Bank_precharge[1] = Ba;
A10_precharge[1] = Addr[10];
end
end
// Burst terminate
if (Burst_term === 1'b1) begin
// Terminate a Write Immediately
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Terminate a Read Depend on CAS Latency
if (Cas_latency_3 === 1'b1) begin
Command[2] = `BST;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `BST;
end
// Display debug message
if (Debug) begin
$display ("%m : at time %t BST : Burst Terminate",$time);
end
end
// Read, Write, Column Latch
if (Read_enable === 1'b1) begin
// Check to see if bank is open (ACT)
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("%m : at time %t ERROR: Bank is not Activated for Read", $time);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
(Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
end
// CAS Latency pipeline
if (Cas_latency_3 == 1'b1) begin
Command[2] = `READ;
Col_addr[2] = Addr;
Bank_addr[2] = Ba;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `READ;
Col_addr[1] = Addr;
Bank_addr[1] = Ba;
end
// Read interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1'b1;
RW_interrupt_counter[RW_interrupt_bank] = 0;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $time);
end
end
end
// Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
RW_interrupt_bank = Ba;
Read_precharge[Ba] = 1'b1;
end
end
// Write Command
if (Write_enable == 1'b1) begin
// Activate to Write
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("%m : at time %t ERROR: Bank is not Activated for Write", $time);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
(Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
end
// Latch Write command, Bank, and Column
Command[0] = `WRITE;
Col_addr[0] = Addr;
Bank_addr[0] = Ba;
// Write interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1'b1;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Read Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
end
end
end
// Write interrupt Read (terminate Read immediately)
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
// Interrupting a Read with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_read[RW_interrupt_bank] = 1'b1;
// Display debug message
if (Debug) begin
$display ("%m : at time %t NOTE : Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, RW_interrupt_bank);
end
end
end
// Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
RW_interrupt_bank = Ba;
Write_precharge[Ba] = 1'b1;
end
end
/*
Write with Auto Precharge Calculation
The device start internal precharge when:
1. Meet minimum tRAS requirement
and 2. tWR cycle(s) after last valid data
or 3. Interrupt by a Read or Write (with or without Auto Precharge)
Note: Model is starting the internal precharge 1 cycle after they meet all the
requirement but tRP will be compensate for the time after the 1 cycle.
*/
if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) ||
(RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin // Case 3
Auto_precharge[0] = 1'b0;
Write_precharge[0] = 1'b0;
RW_interrupt_write[0] = 1'b0;
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
end
if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) ||
(RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin // Case 3
Auto_precharge[1] = 1'b0;
Write_precharge[1] = 1'b0;
RW_interrupt_write[1] = 1'b0;
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
end
if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) ||
(RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin // Case 3
Auto_precharge[2] = 1'b0;
Write_precharge[2] = 1'b0;
RW_interrupt_write[2] = 1'b0;
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
end
if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) && // Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) ||
(RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin // Case 3
Auto_precharge[3] = 1'b0;
Write_precharge[3] = 1'b0;
RW_interrupt_write[3] = 1'b0;
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time + tWRa;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
end
// Read with Auto Precharge Calculation
// The device start internal precharge:
// 1. Meet minimum tRAS requirement
// and 2. CAS Latency - 1 cycles before last burst
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin
if ((($time - RAS_chk0 >= tRAS) && // Case 1
((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
(RW_interrupt_read[0] == 1'b1)) begin // Case 3
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Auto_precharge[0] = 1'b0;
Read_precharge[0] = 1'b0;
RW_interrupt_read[0] = 1'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time);
end
end
end
if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin
if ((($time - RAS_chk1 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
(RW_interrupt_read[1] == 1'b1)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Auto_precharge[1] = 1'b0;
Read_precharge[1] = 1'b0;
RW_interrupt_read[1] = 1'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time);
end
end
end
if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin
if ((($time - RAS_chk2 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
(RW_interrupt_read[2] == 1'b1)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Auto_precharge[2] = 1'b0;
Read_precharge[2] = 1'b0;
RW_interrupt_read[2] = 1'b0;
if (Debug) begin
$display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time);
end
end
end
if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin
if ((($time - RAS_chk3 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
(RW_interrupt_read[3] == 1'b1)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Auto_precharge[3] = 1'b0;
Read_precharge[3] = 1'b0;
RW_interrupt_read[3] = 1'b0;
if (Debug) begin
$display("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time);
end
end
end
// Internal Precharge or Bst
if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks
if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
end else if (Command[0] == `BST) begin // BST terminate a read to current bank
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
if (Data_out_enable == 1'b0) begin
Dq_reg <= #tOH {data_bits{1'bz}};
end
// Detect Read or Write command
if (Command[0] == `READ) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (Bank_addr[0])
2'b00 : Row = B0_row_addr;
2'b01 : Row = B1_row_addr;
2'b10 : Row = B2_row_addr;
2'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1'b0;
Data_out_enable = 1'b1;
end else if (Command[0] == `WRITE) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (Bank_addr[0])
2'b00 : Row = B0_row_addr;
2'b01 : Row = B1_row_addr;
2'b10 : Row = B2_row_addr;
2'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1'b1;
Data_out_enable = 1'b0;
end
// DQ buffer (Driver/Receiver)
if (Data_in_enable == 1'b1) begin // Writing Data to Memory
// Array buffer
case (Bank)
2'b00 : Dq_dqm = Bank0 [{Row, Col}];
2'b01 : Dq_dqm = Bank1 [{Row, Col}];
2'b10 : Dq_dqm = Bank2 [{Row, Col}];
2'b11 : Dq_dqm = Bank3 [{Row, Col}];
endcase
// Dqm operation
if (Dqm[0] == 1'b0) begin
Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
end
if (Dqm[1] == 1'b0) begin
Dq_dqm [15 : 8] = Dq [15 : 8];
end
// Write to memory
case (Bank)
2'b00 : Bank0 [{Row, Col}] = Dq_dqm;
2'b01 : Bank1 [{Row, Col}] = Dq_dqm;
2'b10 : Bank2 [{Row, Col}] = Dq_dqm;
2'b11 : Bank3 [{Row, Col}] = Dq_dqm;
endcase
// Display debug message
if (Dqm !== 2'b11) begin
// Record tWR for manual precharge
WR_chkm [Bank] = $time;
if (Debug) begin
$display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d", $time, Bank, Row, Col, Dq_dqm);
end
end else begin
if (Debug) begin
$display("%m : at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end
end
// Advance burst counter subroutine
#tHZ Burst_decode;
end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory
// Array buffer
case (Bank)
2'b00 : Dq_dqm = Bank0[{Row, Col}];
2'b01 : Dq_dqm = Bank1[{Row, Col}];
2'b10 : Dq_dqm = Bank2[{Row, Col}];
2'b11 : Dq_dqm = Bank3[{Row, Col}];
endcase
// Dqm operation
if (Dqm_reg0 [0] == 1'b1) begin
Dq_dqm [ 7 : 0] = 8'bz;
end
if (Dqm_reg0 [1] == 1'b1) begin
Dq_dqm [15 : 8] = 8'bz;
end
// Display debug message
if (Dqm_reg0 !== 2'b11) begin
Dq_reg = #tAC Dq_dqm;
if (Debug) begin
$display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d", $time, Bank, Row, Col, Dq_reg);
end
end else begin
Dq_reg = #tHZ {data_bits{1'bz}};
if (Debug) begin
$display("%m : at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
end
end
// Advance burst counter subroutine
Burst_decode;
end
end
// Burst counter decode
task Burst_decode;
begin
// Advance Burst Counter
Burst_counter = Burst_counter + 1;
// Burst Type
if (Mode_reg[3] == 1'b0) begin // Sequential Burst
Col_temp = Col + 1;
end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst
Col_temp[2] = Burst_counter[2] ^ Col_brst[2];
Col_temp[1] = Burst_counter[1] ^ Col_brst[1];
Col_temp[0] = Burst_counter[0] ^ Col_brst[0];
end
// Burst Length
if (Burst_length_2) begin // Burst Length = 2
Col [0] = Col_temp [0];
end else if (Burst_length_4) begin // Burst Length = 4
Col [1 : 0] = Col_temp [1 : 0];
end else if (Burst_length_8) begin // Burst Length = 8
Col [2 : 0] = Col_temp [2 : 0];
end else begin // Burst Length = FULL
Col = Col_temp;
end
// Burst Read Single Write
if (Write_burst_mode == 1'b1) begin
Data_in_enable = 1'b0;
end
// Data Counter
if (Burst_length_1 == 1'b1) begin
if (Burst_counter >= 1) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_2 == 1'b1) begin
if (Burst_counter >= 2) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_4 == 1'b1) begin
if (Burst_counter >= 4) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_8 == 1'b1) begin
if (Burst_counter >= 8) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end
end
endtask
// Timing Parameters for -7E (133 MHz @ CL2)
specify
specparam
tAH = 0.8, // Addr, Ba Hold Time
tAS = 1.5, // Addr, Ba Setup Time
tCH = 2.5, // Clock High-Level Width
tCL = 2.5, // Clock Low-Level Width
tCK = 7.0, // Clock Cycle Time
tDH = 0.8, // Data-in Hold Time
tDS = 1.5, // Data-in Setup Time
tCKH = 0.8, // CKE Hold Time
tCKS = 1.5, // CKE Setup Time
tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time
tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time
$width (posedge Clk, tCH);
$width (negedge Clk, tCL);
$period (negedge Clk, tCK);
$period (posedge Clk, tCK);
$setuphold(posedge Clk, Cke, tCKS, tCKH);
$setuphold(posedge Clk, Cs_n, tCMS, tCMH);
$setuphold(posedge Clk, Cas_n, tCMS, tCMH);
$setuphold(posedge Clk, Ras_n, tCMS, tCMH);
$setuphold(posedge Clk, We_n, tCMS, tCMH);
$setuphold(posedge Clk, Addr, tAS, tAH);
$setuphold(posedge Clk, Ba, tAS, tAH);
$setuphold(posedge Clk, Dqm, tCMS, tCMH);
$setuphold(posedge Dq_chk, Dq, tDS, tDH);
endspecify
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pipe_sync.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_pipe_sync.v
// Description : PIPE Sync Module for 7 Series Transceiver
// Version : 20.1
//------------------------------------------------------------------------------
// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default).
// : 1 = Auto TX sync.
// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default).
// : 1 = Auto RX sync.
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Sync Module --------------------------------------------------
module pcie3_7x_0_pipe_sync #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe TX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_LANE = 1, // PCIe lane
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
parameter BYPASS_TXDELAY_ALIGN = 0, // Bypass TX delay align
parameter BYPASS_RXDELAY_ALIGN = 0 // Bypass RX delay align
)
(
//---------- Input -------------------------------------
input SYNC_CLK,
input SYNC_RST_N,
input SYNC_SLAVE,
input SYNC_GEN3,
input SYNC_RATE_IDLE,
input SYNC_MMCM_LOCK,
input SYNC_RXELECIDLE,
input SYNC_RXCDRLOCK,
input SYNC_ACTIVE_LANE,
input SYNC_TXSYNC_START,
input SYNC_TXPHINITDONE,
input SYNC_TXDLYSRESETDONE,
input SYNC_TXPHALIGNDONE,
input SYNC_TXSYNCDONE,
input SYNC_RXSYNC_START,
input SYNC_RXDLYSRESETDONE,
input SYNC_RXPHALIGNDONE_M,
input SYNC_RXPHALIGNDONE_S,
input SYNC_RXSYNC_DONEM_IN,
input SYNC_RXSYNCDONE,
//---------- Output ------------------------------------
output SYNC_TXPHDLYRESET,
output SYNC_TXPHALIGN,
output SYNC_TXPHALIGNEN,
output SYNC_TXPHINIT,
output SYNC_TXDLYBYPASS,
output SYNC_TXDLYSRESET,
output SYNC_TXDLYEN,
output SYNC_TXSYNC_DONE,
output [ 5:0] SYNC_FSM_TX,
output SYNC_RXPHALIGN,
output SYNC_RXPHALIGNEN,
output SYNC_RXDLYBYPASS,
output SYNC_RXDLYSRESET,
output SYNC_RXDLYEN,
output SYNC_RXDDIEN,
output SYNC_RXSYNC_DONEM_OUT,
output SYNC_RXSYNC_DONE,
output [ 6:0] SYNC_FSM_RX
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg2;
//---------- Output Register ---------------------------
reg txdlyen = 1'd0;
reg txsync_done = 1'd0;
reg [ 5:0] fsm_tx = 6'd0;
reg rxdlyen = 1'd0;
reg rxsync_done = 1'd0;
reg [ 6:0] fsm_rx = 7'd0;
//---------- FSM ---------------------------------------
localparam FSM_TXSYNC_IDLE = 6'b000001;
localparam FSM_MMCM_LOCK = 6'b000010;
localparam FSM_TXSYNC_START = 6'b000100;
localparam FSM_TXPHINITDONE = 6'b001000; // Manual TX sync only
localparam FSM_TXSYNC_DONE1 = 6'b010000;
localparam FSM_TXSYNC_DONE2 = 6'b100000;
localparam FSM_RXSYNC_IDLE = 7'b0000001;
localparam FSM_RXCDRLOCK = 7'b0000010;
localparam FSM_RXSYNC_START = 7'b0000100;
localparam FSM_RXSYNC_DONE1 = 7'b0001000;
localparam FSM_RXSYNC_DONE2 = 7'b0010000;
localparam FSM_RXSYNC_DONES = 7'b0100000;
localparam FSM_RXSYNC_DONEM = 7'b1000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= 1'd0;
rate_idle_reg1 <= 1'd0;
mmcm_lock_reg1 <= 1'd0;
rxelecidle_reg1 <= 1'd0;
rxcdrlock_reg1 <= 1'd0;
txsync_start_reg1 <= 1'd0;
txphinitdone_reg1 <= 1'd0;
txdlysresetdone_reg1 <= 1'd0;
txphaligndone_reg1 <= 1'd0;
txsyncdone_reg1 <= 1'd0;
rxsync_start_reg1 <= 1'd0;
rxdlysresetdone_reg1 <= 1'd0;
rxphaligndone_m_reg1 <= 1'd0;
rxphaligndone_s_reg1 <= 1'd0;
rxsync_donem_reg1 <= 1'd0;
rxsyncdone_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= 1'd0;
rate_idle_reg2 <= 1'd0;
mmcm_lock_reg2 <= 1'd0;
rxelecidle_reg2 <= 1'd0;
rxcdrlock_reg2 <= 1'd0;
txsync_start_reg2 <= 1'd0;
txphinitdone_reg2 <= 1'd0;
txdlysresetdone_reg2 <= 1'd0;
txphaligndone_reg2 <= 1'd0;
txsyncdone_reg2 <= 1'd0;
rxsync_start_reg2 <= 1'd0;
rxdlysresetdone_reg2 <= 1'd0;
rxphaligndone_m_reg2 <= 1'd0;
rxphaligndone_s_reg2 <= 1'd0;
rxsync_donem_reg2 <= 1'd0;
rxsyncdone_reg2 <= 1'd0;
//---------- 3rd Stage FF --------------------------
txsync_start_reg3 <= 1'd0;
txphinitdone_reg3 <= 1'd0;
txdlysresetdone_reg3 <= 1'd0;
txphaligndone_reg3 <= 1'd0;
txsyncdone_reg3 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= SYNC_GEN3;
rate_idle_reg1 <= SYNC_RATE_IDLE;
mmcm_lock_reg1 <= SYNC_MMCM_LOCK;
rxelecidle_reg1 <= SYNC_RXELECIDLE;
rxcdrlock_reg1 <= SYNC_RXCDRLOCK;
txsync_start_reg1 <= SYNC_TXSYNC_START;
txphinitdone_reg1 <= SYNC_TXPHINITDONE;
txdlysresetdone_reg1 <= SYNC_TXDLYSRESETDONE;
txphaligndone_reg1 <= SYNC_TXPHALIGNDONE;
txsyncdone_reg1 <= SYNC_TXSYNCDONE;
rxsync_start_reg1 <= SYNC_RXSYNC_START;
rxdlysresetdone_reg1 <= SYNC_RXDLYSRESETDONE;
rxphaligndone_m_reg1 <= SYNC_RXPHALIGNDONE_M;
rxphaligndone_s_reg1 <= SYNC_RXPHALIGNDONE_S;
rxsync_donem_reg1 <= SYNC_RXSYNC_DONEM_IN;
rxsyncdone_reg1 <= SYNC_RXSYNCDONE;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= gen3_reg1;
rate_idle_reg2 <= rate_idle_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
rxelecidle_reg2 <= rxelecidle_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
txsync_start_reg2 <= txsync_start_reg1;
txphinitdone_reg2 <= txphinitdone_reg1;
txdlysresetdone_reg2 <= txdlysresetdone_reg1;
txphaligndone_reg2 <= txphaligndone_reg1;
txsyncdone_reg2 <= txsyncdone_reg1;
rxsync_start_reg2 <= rxsync_start_reg1;
rxdlysresetdone_reg2 <= rxdlysresetdone_reg1;
rxphaligndone_m_reg2 <= rxphaligndone_m_reg1;
rxphaligndone_s_reg2 <= rxphaligndone_s_reg1;
rxsync_donem_reg2 <= rxsync_donem_reg1;
rxsyncdone_reg2 <= rxsyncdone_reg1;
//---------- 3rd Stage FF --------------------------
txsync_start_reg3 <= txsync_start_reg2;
txphinitdone_reg3 <= txphinitdone_reg2;
txdlysresetdone_reg3 <= txdlysresetdone_reg2;
txphaligndone_reg3 <= txphaligndone_reg2;
txsyncdone_reg3 <= txsyncdone_reg2;
end
end
//---------- Generate TX Sync FSM ----------------------------------------------
generate if ((PCIE_LINK_SPEED == 3) || (PCIE_TXBUF_EN == "FALSE"))
begin : txsync_fsm
//---------- PIPE TX Sync FSM ----------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
else
begin
case (fsm_tx)
//---------- Idle State ------------------------
FSM_TXSYNC_IDLE :
begin
//---------- Exiting Reset or Rate Change --
if (txsync_start_reg2)
begin
fsm_tx <= FSM_MMCM_LOCK;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
else
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= txdlyen;
txsync_done <= txsync_done;
end
end
//---------- Check MMCM Lock -------------------
FSM_MMCM_LOCK :
begin
fsm_tx <= (mmcm_lock_reg2 ? FSM_TXSYNC_START : FSM_MMCM_LOCK);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- TX Delay Soft Reset ---------------
FSM_TXSYNC_START :
begin
fsm_tx <= (((!txdlysresetdone_reg3 && txdlysresetdone_reg2) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for TX Phase Init Done (Manual Mode Only)
FSM_TXPHINITDONE :
begin
fsm_tx <= (((!txphinitdone_reg3 && txphinitdone_reg2) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for TX Phase Alignment Done --
FSM_TXSYNC_DONE1 :
begin
if (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE)
fsm_tx <= ((!txsyncdone_reg3 && txsyncdone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
else
fsm_tx <= ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for Master TX Delay Alignment Done
FSM_TXSYNC_DONE2 :
begin
if ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1))
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= !SYNC_SLAVE;
txsync_done <= 1'd1;
end
else
begin
fsm_tx <= FSM_TXSYNC_DONE2;
txdlyen <= !SYNC_SLAVE;
txsync_done <= 1'd0;
end
end
//---------- Default State ---------------------
default :
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
endcase
end
end
end
//---------- TX Sync FSM Default------------------------------------------------
else
begin : txsync_fsm_disable
//---------- Default -------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
end
endgenerate
//---------- Generate RX Sync FSM ----------------------------------------------
generate if ((PCIE_LINK_SPEED == 3) && (PCIE_RXBUF_EN == "FALSE"))
begin : rxsync_fsm
//---------- PIPE RX Sync FSM ----------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
else
begin
case (fsm_rx)
//---------- Idle State ------------------------
FSM_RXSYNC_IDLE :
begin
//---------- Exiting Rate Change -----------
if (rxsync_start_reg2)
begin
fsm_rx <= FSM_RXCDRLOCK;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Exiting Electrical Idle without Rate Change
else if (gen3_reg2 && rate_idle_reg2 && ((rxelecidle_reg2 == 1'd1) && (rxelecidle_reg1 == 1'd0)))
begin
fsm_rx <= FSM_RXCDRLOCK;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Idle --------------------------
else
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= rxelecidle_reg2 ? 1'd0 : rxdlyen;
rxsync_done <= rxelecidle_reg2 ? 1'd0 : rxsync_done;
end
end
//---------- Wait for RX Electrical Idle Exit and RX CDR Lock
FSM_RXCDRLOCK :
begin
fsm_rx <= ((!rxelecidle_reg2 && rxcdrlock_reg2) ? FSM_RXSYNC_START : FSM_RXCDRLOCK);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Start RX Sync with RX Delay Soft Reset
FSM_RXSYNC_START :
begin
fsm_rx <= ((!rxdlysresetdone_reg2 && rxdlysresetdone_reg1) ? FSM_RXSYNC_DONE1 : FSM_RXSYNC_START);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Wait for RX Phase Alignment Done --
FSM_RXSYNC_DONE1 :
begin
if (SYNC_SLAVE)
begin
fsm_rx <= ((!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
else
begin
fsm_rx <= ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Master RX Delay Alignment Done
FSM_RXSYNC_DONE2 :
begin
if (SYNC_SLAVE)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd1;
end
else if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
begin
fsm_rx <= ((PCIE_LANE == 1) ? FSM_RXSYNC_IDLE : FSM_RXSYNC_DONES);
rxdlyen <= (PCIE_LANE == 1);
rxsync_done <= (PCIE_LANE == 1);
end
else
begin
fsm_rx <= FSM_RXSYNC_DONE2;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Slave RX Phase Alignment Done
FSM_RXSYNC_DONES :
begin
if (!rxphaligndone_s_reg2 && rxphaligndone_s_reg1)
begin
fsm_rx <= FSM_RXSYNC_DONEM;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
else
begin
fsm_rx <= FSM_RXSYNC_DONES;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Master RX Delay Alignment Done
FSM_RXSYNC_DONEM :
begin
if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd1;
rxsync_done <= 1'd1;
end
else
begin
fsm_rx <= FSM_RXSYNC_DONEM;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
end
//---------- Default State ---------------------
default :
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
endcase
end
end
end
//---------- RX Sync FSM Default -----------------------------------------------
else
begin : rxsync_fsm_disable
//---------- Default -------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
endgenerate
//---------- PIPE Sync Output --------------------------------------------------
assign SYNC_TXPHALIGNEN = ((PCIE_TXSYNC_MODE == 1) || (!gen3_reg2 && (PCIE_TXBUF_EN == "TRUE"))) ? 1'd0 : 1'd1;
assign SYNC_TXDLYBYPASS = 1'd0;
//assign SYNC_TXDLYSRESET = !(((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
assign SYNC_TXDLYSRESET = (fsm_tx == FSM_TXSYNC_START);
assign SYNC_TXPHDLYRESET = (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
assign SYNC_TXPHINIT = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXPHINITDONE);
assign SYNC_TXPHALIGN = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXSYNC_DONE1);
assign SYNC_TXDLYEN = PCIE_TXSYNC_MODE ? 1'd0 : txdlyen;
assign SYNC_TXSYNC_DONE = txsync_done;
assign SYNC_FSM_TX = fsm_tx;
assign SYNC_RXPHALIGNEN = ((PCIE_RXSYNC_MODE == 1) || (!gen3_reg2) || (PCIE_RXBUF_EN == "TRUE")) ? 1'd0 : 1'd1;
assign SYNC_RXDLYBYPASS = !gen3_reg2 || (PCIE_RXBUF_EN == "TRUE");
assign SYNC_RXDLYSRESET = (fsm_rx == FSM_RXSYNC_START);
assign SYNC_RXPHALIGN = PCIE_RXSYNC_MODE ? 1'd0 : (!SYNC_SLAVE ? (fsm_rx == FSM_RXSYNC_DONE1) : (rxsync_donem_reg2 && (fsm_rx == FSM_RXSYNC_DONE1)));
assign SYNC_RXDLYEN = PCIE_RXSYNC_MODE ? 1'd0 : rxdlyen;
assign SYNC_RXDDIEN = gen3_reg2 && (PCIE_RXBUF_EN == "FALSE");
assign SYNC_RXSYNC_DONE = rxsync_done;
assign SYNC_RXSYNC_DONEM_OUT = (fsm_rx == FSM_RXSYNC_DONES);
assign SYNC_FSM_RX = fsm_rx;
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2000-2001 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised
// by a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement
// from Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================
// FILE DETAILS
// Project : USERNAME
// File : USERNAME.v
// Title :
// Dependencies :
// Description : Top level for core.
// =============================================================================
module pcie (
input wire sys_clk_250, // 250 Mhz Clock
input wire sys_clk_125, // 125 Mhz Clock
input wire rst_n, // asynchronous system reset.
input wire inta_n,
input wire [7:0] msi,
input wire [15:0] vendor_id ,
input wire [15:0] device_id ,
input wire [7:0] rev_id ,
input wire [23:0] class_code ,
input wire [15:0] subsys_ven_id ,
input wire [15:0] subsys_id ,
input wire load_id ,
input wire force_lsm_active, // Force LSM Status Active
input wire force_rec_ei, // Force Received Electrical Idle
input wire force_phy_status, // Force PHY Connection Status
input wire force_disable_scr,// Force Disable Scrambler to PCS
input wire hl_snd_beacon, // HL req. to Send Beacon
input wire hl_disable_scr, // HL req. to Disable Scrambling bit in TS1/TS2
input wire hl_gto_dis, // HL req a jump to Disable
input wire hl_gto_det, // HL req a jump to detect
input wire hl_gto_hrst, // HL req a jump to Hot reset
input wire hl_gto_l0stx, // HL req a jump to TX L0s
input wire hl_gto_l1, // HL req a jump to L1
input wire hl_gto_l2, // HL req a jump to L2
input wire hl_gto_l0stxfts, // HL req a jump to L0s TX FTS
input wire hl_gto_lbk, // HL req a jump to Loopback
input wire hl_gto_rcvry, // HL req a jump to recovery
input wire hl_gto_cfg, // HL req a jump to CFG
input wire no_pcie_train, // Disable the training process
// Power Management Interface
input wire [1:0] tx_dllp_val, // Req for Sending PM/Vendor type DLLP
input wire [2:0] tx_pmtype, // Power Management Type
input wire [23:0] tx_vsd_data, // Vendor Type DLLP contents
// For VC Inputs
input wire tx_req_vc0, // VC0 Request from User
input wire [15:0] tx_data_vc0, // VC0 Input data from user logic
input wire tx_st_vc0, // VC0 start of pkt from user logic.
input wire tx_end_vc0, // VC0 End of pkt from user logic.
input wire tx_nlfy_vc0, // VC0 End of nullified pkt from user logic.
input wire ph_buf_status_vc0, // VC0 Indicate the Full/alm.Full status of the PH buffers
input wire pd_buf_status_vc0, // VC0 Indicate PD Buffer has got space less than Max Pkt size
input wire nph_buf_status_vc0, // VC0 For NPH
input wire npd_buf_status_vc0, // VC0 For NPD
input wire ph_processed_vc0, // VC0 TL has processed one TLP Header - PH Type
input wire pd_processed_vc0, // VC0 TL has processed one TLP Data - PD TYPE
input wire nph_processed_vc0, // VC0 For NPH
input wire npd_processed_vc0, // VC0 For NPD
input wire [7:0] pd_num_vc0, // VC0 For PD -- No. of Data processed
input wire [7:0] npd_num_vc0, // VC0 For PD
input wire [7:0] rxp_data, // CH0:PCI Express data from External Phy
input wire rxp_data_k, // CH0:PCI Express Control from External Phy
input wire rxp_valid, // CH0:Indicates a symbol lock and valid data on rx_data /rx_data_k
input wire rxp_elec_idle, // CH0:Inidicates receiver detection of an electrical signal
input wire [2:0] rxp_status, // CH0:Indicates receiver Staus/Error codes
input wire phy_status, // Indicates PHY status info
// From User logic
// From User logic
input wire cmpln_tout , // Completion time out.
input wire cmpltr_abort_np , // Completor abort.
input wire cmpltr_abort_p , // Completor abort.
input wire unexp_cmpln , // Unexpexted completion.
input wire ur_np_ext , // UR for NP type.
input wire ur_p_ext , // UR for P type.
input wire np_req_pend , // Non posted request is pending.
input wire pme_status , // PME status to reg 044h.
// User Loop back data
input wire [15:0] tx_lbk_data, // TX User Master Loopback data
input wire [1:0] tx_lbk_kcntl, // TX User Master Loopback control
output wire tx_lbk_rdy, // TX loop back is ready to accept data
output wire [15:0] rx_lbk_data, // RX User Master Loopback data
output wire [1:0] rx_lbk_kcntl, // RX User Master Loopback control
// Power Management/ Vendor specific DLLP
output wire tx_dllp_sent, // Requested PM DLLP is sent
output wire [2:0] rxdp_pmd_type, // PM DLLP type bits.
output wire [23:0] rxdp_vsd_data , // Vendor specific DLLP data.
output wire [1:0] rxdp_dllp_val, // PM/Vendor specific DLLP valid.
output wire [7:0] txp_data, // CH0:PCI Express data to External Phy
output wire txp_data_k, // CH0:PCI Express control to External Phy
output wire txp_elec_idle, // CH0:Tells PHY to output Electrical Idle
output wire txp_compliance, // CH0:Sets the PHY running disparity to -ve
output wire rxp_polarity, // CH0:Tells PHY to do polarity inversion on the received data
output wire txp_detect_rx_lb, // Tells PHY to begin receiver detection or begin Loopback
output wire reset_n, // Async reset to the PHY
output wire [1:0] power_down, // Tell sthe PHY to power Up or Down
output wire phy_pol_compliance, // Polling compliance
output wire [3:0] phy_ltssm_state, // Indicates the states of the ltssm
output wire [2:0] phy_ltssm_substate, // sub-states of the ltssm_state
output wire tx_rdy_vc0, // VC0 TX ready indicating signal
output wire [8:0] tx_ca_ph_vc0, // VC0 Available credit for Posted Type Headers
output wire [12:0] tx_ca_pd_vc0, // VC0 For Posted - Data
output wire [8:0] tx_ca_nph_vc0, // VC0 For Non-posted - Header
output wire [12:0] tx_ca_npd_vc0, // VC0 For Non-posted - Data
output wire [8:0] tx_ca_cplh_vc0, // VC0 For Completion - Header
output wire [12:0] tx_ca_cpld_vc0, // VC0 For Completion - Data
output wire tx_ca_p_recheck_vc0, //
output wire tx_ca_cpl_recheck_vc0, //
output wire [15:0] rx_data_vc0, // VC0 Receive data
output wire rx_st_vc0, // VC0 Receive data start
output wire rx_end_vc0, // VC0 Receive data end
output wire rx_us_req_vc0 , // VC0 unsupported req received
output wire rx_malf_tlp_vc0 ,// VC0 malformed TLP in received data
output wire [6:0] rx_bar_hit , // Bar hit
output wire [2:0] mm_enable , // Multiple message enable bits of Register
output wire msi_enable , // MSI enable bit of Register
// From Config Registers
output wire [7:0] bus_num , // Bus number
output wire [4:0] dev_num , // Device number
output wire [2:0] func_num , // Function number
output wire [1:0] pm_power_state , // Power state bits of Register at 044h
output wire pme_en , // PME_En at 044h
output wire [5:0] cmd_reg_out , // Bits 10,8,6,2,1,0 From register 004h
output wire [14:0] dev_cntl_out , // Divice control register at 060h
output wire [7:0] lnk_cntl_out , // Link control register at 068h
// To ASPM implementation outside the IP
output wire tx_rbuf_empty, // Transmit retry buffer is empty
output wire tx_dllp_pend, // DLPP is pending to be transmitted
output wire rx_tlp_rcvd, // Received a TLP
// Datal Link Control SM Status
output wire dl_inactive, // Data Link Control SM is in INACTIVE state
output wire dl_init, // INIT state
output wire dl_active, // ACTIVE state
output wire dl_up // Data Link Layer is UP
);
pci_exp_x1_core_wrap u1_dut(
// Clock and Reset
.sys_clk_250 ( sys_clk_250 ) ,
.sys_clk_125 ( sys_clk_125 ) ,
.rst_n ( rst_n ),
.inta_n ( inta_n ),
.msi ( msi ),
.vendor_id ( vendor_id ),
.device_id ( device_id ),
.rev_id ( rev_id ),
.class_code ( class_code ),
.subsys_ven_id ( subsys_ven_id ),
.subsys_id ( subsys_id ),
.load_id ( load_id ),
// Inputs
.force_lsm_active ( force_lsm_active ),
.force_rec_ei ( force_rec_ei ),
.force_phy_status ( force_phy_status ),
.force_disable_scr ( force_disable_scr ),
.hl_snd_beacon ( hl_snd_beacon ),
.hl_disable_scr ( hl_disable_scr ),
.hl_gto_dis ( hl_gto_dis ),
.hl_gto_det ( hl_gto_det ),
.hl_gto_hrst ( hl_gto_hrst ),
.hl_gto_l0stx ( hl_gto_l0stx ),
.hl_gto_l1 ( hl_gto_l1 ),
.hl_gto_l2 ( hl_gto_l2 ),
.hl_gto_l0stxfts ( hl_gto_l0stxfts ),
.hl_gto_lbk ( hl_gto_lbk ),
.hl_gto_rcvry ( hl_gto_rcvry ),
.hl_gto_cfg ( hl_gto_cfg ),
.no_pcie_train ( no_pcie_train ),
// Power Management Interface
.tx_dllp_val ( tx_dllp_val ),
.tx_pmtype ( tx_pmtype ),
.tx_vsd_data ( tx_vsd_data ),
.tx_req_vc0 ( tx_req_vc0 ),
.tx_data_vc0 ( tx_data_vc0 ),
.tx_st_vc0 ( tx_st_vc0 ),
.tx_end_vc0 ( tx_end_vc0 ),
.tx_nlfy_vc0 ( tx_nlfy_vc0 ),
.ph_buf_status_vc0 ( ph_buf_status_vc0 ),
.pd_buf_status_vc0 ( pd_buf_status_vc0 ),
.nph_buf_status_vc0 ( nph_buf_status_vc0 ),
.npd_buf_status_vc0 ( npd_buf_status_vc0 ),
.ph_processed_vc0 ( ph_processed_vc0 ),
.pd_processed_vc0 ( pd_processed_vc0 ),
.nph_processed_vc0 ( nph_processed_vc0 ),
.npd_processed_vc0 ( npd_processed_vc0 ),
.pd_num_vc0 ( pd_num_vc0 ),
.npd_num_vc0 ( npd_num_vc0 ),
// From External PHY (PIPE I/F)
.rxp_data ( rxp_data ),
.rxp_data_k ( rxp_data_k ),
.rxp_valid ( rxp_valid ),
.rxp_elec_idle ( rxp_elec_idle ),
.rxp_status ( rxp_status ),
.phy_status ( phy_status),
// From User logic
.cmpln_tout ( cmpln_tout ),
.cmpltr_abort_np ( cmpltr_abort_np ),
.cmpltr_abort_p ( cmpltr_abort_p ),
.unexp_cmpln ( unexp_cmpln ),
.ur_np_ext ( ur_np_ext ),
.ur_p_ext ( ur_p_ext ),
.np_req_pend ( np_req_pend ),
.pme_status ( pme_status ),
.tx_lbk_data ( tx_lbk_data ),
.tx_lbk_kcntl ( tx_lbk_kcntl ),
.tx_lbk_rdy ( tx_lbk_rdy ),
.rx_lbk_data ( rx_lbk_data ),
.rx_lbk_kcntl ( rx_lbk_kcntl ),
// Power Management
.tx_dllp_sent ( tx_dllp_sent ),
.rxdp_pmd_type ( rxdp_pmd_type ),
.rxdp_vsd_data ( rxdp_vsd_data ),
.rxdp_dllp_val ( rxdp_dllp_val ),
//-------- Outputs
// To External PHY (PIPE I/F)
.txp_data ( txp_data ),
.txp_data_k ( txp_data_k ),
.txp_elec_idle ( txp_elec_idle ),
.txp_compliance ( txp_compliance ),
.rxp_polarity ( rxp_polarity ),
.txp_detect_rx_lb ( txp_detect_rx_lb ),
.reset_n ( reset_n ),
.power_down ( power_down ),
// From TX User Interface
.phy_pol_compliance ( phy_pol_compliance ),
.phy_ltssm_state ( phy_ltssm_state ),
.phy_ltssm_substate ( phy_ltssm_substate ),
.tx_rdy_vc0 ( tx_rdy_vc0),
.tx_ca_ph_vc0 ( tx_ca_ph_vc0),
.tx_ca_pd_vc0 ( tx_ca_pd_vc0),
.tx_ca_nph_vc0 ( tx_ca_nph_vc0),
.tx_ca_npd_vc0 ( tx_ca_npd_vc0),
.tx_ca_cplh_vc0 ( tx_ca_cplh_vc0),
.tx_ca_cpld_vc0 ( tx_ca_cpld_vc0),
.tx_ca_p_recheck_vc0 ( tx_ca_p_recheck_vc0 ),
.tx_ca_cpl_recheck_vc0 ( tx_ca_cpl_recheck_vc0 ),
.rx_data_vc0 ( rx_data_vc0),
.rx_st_vc0 ( rx_st_vc0),
.rx_end_vc0 ( rx_end_vc0),
.rx_us_req_vc0 ( rx_us_req_vc0 ),
.rx_malf_tlp_vc0 ( rx_malf_tlp_vc0 ),
.rx_bar_hit ( rx_bar_hit ),
.mm_enable ( mm_enable ),
.msi_enable ( msi_enable ),
// From Config Registers
.bus_num ( bus_num ) ,
.dev_num ( dev_num ) ,
.func_num ( func_num ) ,
.pm_power_state ( pm_power_state ) ,
.pme_en ( pme_en ) ,
.cmd_reg_out ( cmd_reg_out ),
.dev_cntl_out ( dev_cntl_out ),
.lnk_cntl_out ( lnk_cntl_out ),
// To ASPM implementation outside the IP
.tx_rbuf_empty ( tx_rbuf_empty ),
.tx_dllp_pend ( tx_dllp_pend ),
.rx_tlp_rcvd ( rx_tlp_rcvd ),
// Datal Link Control SM Status
.dl_inactive ( dl_inactive ),
.dl_init ( dl_init ),
.dl_active ( dl_active ),
.dl_up ( dl_up )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2AI_BLACKBOX_V
`define SKY130_FD_SC_LS__O2BB2AI_BLACKBOX_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2AI_BLACKBOX_V
|
// `include "define.v"
// `include "regfile.v"
// `include "hilo_reg.v"
// `include "BranchControl.v"
// `include "HazardControl.v"
// `include "ForwardControl.v"
// `include "IF.v"
// `include "IF_ID.v"
// `include "ID.v"
// `include "ID_EX.v"
// `include "EX.v"
// `include "ALU.v"
// `include "decoder.v"
// `include "EX_MEM.v"
// `include "MEM.v"
// `include "RM_ctrl.v"
// `include "WM_ctrl.v"
// `include "MEM_WB.v"
// `include "utilities/dffe.v"
// `include "utilities/mux2x1.v"
// `include "utilities/mux4x1.v"
module pipeline_CPU (
input clk,
input rst,
input[`RegDataWidth-1:0] data_from_mem,
output[`MemAddrWidth-1:0] mem_addr,
output[3:0] mem_byte_slct,
output[`RegDataWidth-1:0] data_to_write_mem,
output mem_we,
output mem_re,
input[`InstDataWidth-1:0] inst_from_rom,
output[`InstAddrWidth-1:0] rom_addr,
output rom_ce
);
supply1 vcc;
supply0 gnd;
// Forwarding wire
wire[1:0] FWA;
wire[1:0] FWB;
wire[1:0] FWhi;
wire[1:0] FWlo;
wire FWLS;
wire[1:0] FW_br_A;
wire[1:0] FW_br_B;
// branch control wire
wire[`InstAddrWidth-1:0] branch_address;
wire is_branch;
wire is_rst_IF_ID;
// Hazard Control wire
wire is_hold_IF;
wire is_hold_IF_ID;
wire is_zeros_ID_EX;
wire[`InstAddrWidth-1:0] pc_plus4_IF;
wire[`InstDataWidth-1:0] inst_ID;
wire[`InstAddrWidth-1:0] pc_plus4_ID;
IF inst_fetch(.clk (clk),
.rst (rst),
.is_hold (is_hold_IF),
.is_branch(is_branch),
.branch_address(branch_address),
.ce(rom_ce),
.pc(rom_addr),
.pc_plus4(pc_plus4_IF)
);
wire IF_ID_controlor;
mux2x1 IF_ID_control(
.in_0(rst),
.in_1(vcc),
.slct(is_rst_IF_ID),
.out(IF_ID_controlor)
);
IF_ID if_id_reg(
.clk (clk),
.rst (IF_ID_controlor),
.is_hold (is_hold_IF_ID),
.pc_plus4_IF(pc_plus4_IF),
.inst_IF (inst_from_rom),
.pc_plus4_ID(pc_plus4_ID),
.inst_ID (inst_ID)
);
wire[`RegAddrWidth-1:0] raddr_1_ID;
wire[`RegDataWidth-1:0] rdata_1_ID;
wire[`RegAddrWidth-1:0] raddr_2_ID;
wire[`RegDataWidth-1:0] rdata_2_ID;
wire[`RegDataWidth-1:0] shamt_ID;
wire WriteReg_ID;
wire MemOrAlu_ID;
wire WriteMem_ID;
wire ReadMem_ID;
wire[`ALUTypeWidth-1:0] AluType_ID;
wire[`ALUOpWidth-1:0] AluOp_ID;
wire AluSrcA_ID;
wire AluSrcB_ID;
wire RegDes_ID;
wire ImmSigned_ID;
wire is_jal_ID;
wire[`RegAddrWidth-1:0] rt_ID;
wire[`RegAddrWidth-1:0] rd_ID;
wire[`RegDataWidth-1:0] imm_signed_ID;
wire[`RegDataWidth-1:0] imm_unsigned_ID;
wire[`OpcodeWidth-1:0] opcode_ID;
ID inst_decode(
.rst(rst),
.pc_plus4(pc_plus4_ID),
.inst(inst_ID),
.reg1_addr(raddr_1_ID),
.reg2_addr(raddr_2_ID),
.WriteReg(WriteReg_ID),
.MemOrAlu(MemOrAlu_ID),
.WriteMem(WriteMem_ID),
.ReadMem(ReadMem_ID),
.AluType(AluType_ID),
.AluOp(AluOp_ID),
.AluSrcA(AluSrcA_ID),
.AluSrcB(AluSrcB_ID),
.RegDes(RegDes_ID),
.ImmSigned(ImmSigned_ID),
.opcode(opcode_ID),
.rt(rt_ID),
.rd(rd_ID),
.imm_signed(imm_signed_ID),
.imm_unsigned(imm_unsigned_ID),
.shamt(shamt_ID),
.is_jal(is_jal_ID)
);
wire[`RegAddrWidth-1:0] reg_write_addr;
wire[`RegDataWidth-1:0] reg_write_data;
wire reg_we;
wire we_hi;
wire[`RegDataWidth-1:0] hi_data_in;
wire we_lo;
wire[`RegDataWidth-1:0] lo_data_in;
wire[`RegDataWidth-1:0] hi_data_out_ID;
wire[`RegDataWidth-1:0] lo_data_out_ID;
wire[`RegDataWidth-1:0] hi_data_to_EX;
wire[`RegDataWidth-1:0] lo_data_to_EX;
// force read regfile
regfile regs(
.clk(clk),
.rst(rst),
.waddr(reg_write_addr),
.wdata(reg_write_data),
.we(reg_we),
.re1(vcc),
.raddr_1(raddr_1_ID),
.rdata_1(rdata_1_ID),
.re2(vcc),
.raddr_2(raddr_2_ID),
.rdata_2(rdata_2_ID)
);
hilo_reg hilo_regs(
.clk(clk),
.rst(rst),
.we_hi(we_hi),
.hi_data_in(hi_data_in),
.we_lo(we_lo),
.lo_data_in(lo_data_in),
.hi_data_out(hi_data_out_ID),
.lo_data_out(lo_data_out_ID)
);
wire WriteReg_EX;
wire MemOrAlu_EX;
wire WriteMem_EX;
wire ReadMem_EX;
wire[`ALUTypeWidth-1:0] AluType_EX;
wire[`ALUOpWidth-1:0] AluOp_EX;
wire AluSrcA_EX;
wire AluSrcB_EX;
wire RegDes_EX;
wire ImmSigned_EX;
wire is_jal_EX;
wire[`RegAddrWidth-1:0] rt_EX;
wire[`RegAddrWidth-1:0] rd_EX;
wire[`RegDataWidth-1:0] imm_signed_EX;
wire[`RegDataWidth-1:0] imm_unsigned_EX;
wire[`OpcodeWidth-1:0] opcode_EX;
wire[`RegDataWidth-1:0] rdata_1_EX;
wire[`RegDataWidth-1:0] rdata_2_EX;
wire[`RegAddrWidth-1:0] raddr_1_EX;
wire[`RegAddrWidth-1:0] raddr_2_EX;
wire[`RegDataWidth-1:0] shamt_EX;
wire[`InstAddrWidth-1:0] pc_plus4_EX;
wire ID_EX_controlor;
mux2x1 ID_EX_control(
.in_0(rst),
.in_1(vcc),
.slct(is_zeros_ID_EX),
.out(ID_EX_controlor)
);
ID_EX id_ex_reg(
.clk(clk),
.rst(ID_EX_controlor),
.is_hold(gnd),
.rdata_1_ID(rdata_1_ID),
.rdata_2_ID(rdata_2_ID),
.raddr_1_ID(raddr_1_ID),
.raddr_2_ID(raddr_2_ID),
.shamt_ID(shamt_ID),
.WriteReg_ID(WriteReg_ID),
.MemOrAlu_ID(MemOrAlu_ID),
.WriteMem_ID(WriteMem_ID),
.ReadMem_ID(ReadMem_ID),
.AluType_ID(AluType_ID),
.AluOp_ID(AluOp_ID),
.AluSrcA_ID(AluSrcA_ID),
.AluSrcB_ID(AluSrcB_ID),
.RegDes_ID(RegDes_ID),
.ImmSigned_ID(ImmSigned_ID),
.is_jal_ID(is_jal_ID),
.rt_ID(rt_ID),
.rd_ID(rd_ID),
.imm_signed_ID(imm_signed_ID),
.imm_unsigned_ID(imm_unsigned_ID),
.opcode_ID(opcode_ID),
.hi_ID(hi_data_out_ID),
.lo_ID(lo_data_out_ID),
.pc_plus4_ID(pc_plus4_ID),
.rdata_1_EX(rdata_1_EX),
.rdata_2_EX(rdata_2_EX),
.raddr_1_EX(raddr_1_EX),
.raddr_2_EX(raddr_2_EX),
.shamt_EX(shamt_EX),
.WriteReg_EX(WriteReg_EX),
.MemOrAlu_EX(MemOrAlu_EX),
.ReadMem_EX(ReadMem_EX),
.WriteMem_EX(WriteMem_EX),
.AluType_EX(AluType_EX),
.AluOp_EX(AluOp_EX),
.AluSrcA_EX(AluSrcA_EX),
.AluSrcB_EX(AluSrcB_EX),
.RegDes_EX(RegDes_EX),
.ImmSigned_EX(ImmSigned_EX),
.is_jal_EX(is_jal_EX),
.rt_EX(rt_EX),
.rd_EX(rd_EX),
.imm_signed_EX(imm_signed_EX),
.imm_unsigned_EX(imm_unsigned_EX),
.opcode_EX(opcode_EX),
.hi_EX(hi_data_to_EX),
.lo_EX(lo_data_to_EX),
.pc_plus4_EX(pc_plus4_EX)
);
wire[`RegAddrWidth-1:0] target_EX;
wire is_Overflow;
wire[`RegDataWidth-1:0] data_out_EX;
wire we_hi_EX;
wire we_lo_EX;
wire[`RegDataWidth-1:0] hi_EX;
wire[`RegDataWidth-1:0] lo_EX;
wire[`RegDataWidth-1:0] rdata_2_EX_out;
wire[`RegDataWidth-1:0] hi_MEM;
wire[`RegDataWidth-1:0] lo_MEM;
wire[`RegDataWidth-1:0] data_from_ALU_MEM;
EX execution(
.rst(rst),
.shamt(shamt_EX),
.AluType_EX(AluType_EX),
.AluOp_EX(AluOp_EX),
.AluSrcA_EX(AluSrcA_EX),
.AluSrcB_EX(AluSrcB_EX),
.RegDes_EX(RegDes_EX),
.ImmSigned_EX(ImmSigned_EX),
.is_jal_EX(is_jal_EX),
.rt_EX(rt_EX),
.rd_EX(rd_EX),
.imm_signed_EX(imm_signed_EX),
.imm_unsigned_EX(imm_unsigned_EX),
.hi(hi_data_to_EX),
.lo(lo_data_to_EX),
.rdata_1(rdata_1_EX),
.rdata_2(rdata_2_EX),
.pc_plus4_EX(pc_plus4_EX),
// forwarding data in
.data_out_MEM(data_from_ALU_MEM),
.data_out_WB(reg_write_data),
.hi_MEM(hi_MEM),
.hi_WB(hi_data_in),
.lo_MEM(lo_MEM),
.lo_WB(lo_data_in),
.FWA(FWA),
.FWB(FWB),
.FWhi(FWhi),
.FWlo(FWlo),
.target_EX(target_EX),
.is_Overflow(is_Overflow),
.data_out_EX(data_out_EX),
.rdata_2_EX(rdata_2_EX_out),
.hi_EX(hi_EX),
.lo_EX(lo_EX),
.we_hi(we_hi_EX),
.we_lo(we_lo_EX)
);
wire[`RegAddrWidth-1:0] target_MEM;
wire we_hi_MEM;
wire we_lo_MEM;
wire[`RegDataWidth-1:0] rdata_2_MEM;
wire[`RegAddrWidth-1:0] raddr_2_MEM;
wire WriteReg_MEM;
wire MemOrAlu_MEM;
wire WriteMem_MEM;
wire ReadMem_MEM;
wire[`OpcodeWidth-1:0] opcode_MEM;
EX_MEM ex_mem_reg(
.clk(clk),
.rst(rst),
// set gnd temporarily
.is_hold(gnd),
.target_EX(target_EX),
.data_out_EX(data_out_EX),
.we_hi_EX(we_hi_EX),
.we_lo_EX(we_lo_EX),
.hi_EX(hi_EX),
.lo_EX(lo_EX),
.raddr_2_EX(raddr_2_EX),
.rdata_2_EX(rdata_2_EX_out),
.WriteReg_EX(WriteReg_EX),
.MemOrAlu_EX(MemOrAlu_EX),
.WriteMem_EX(WriteMem_EX),
.ReadMem_EX(ReadMem_EX),
.opcode_EX(opcode_EX),
.target_MEM(target_MEM),
.data_from_ALU_MEM(data_from_ALU_MEM),
.we_hi_MEM(we_hi_MEM),
.we_lo_MEM(we_lo_MEM),
.hi_MEM(hi_MEM),
.lo_MEM(lo_MEM),
.raddr_2_MEM(raddr_2_MEM),
.rdata_2_MEM(rdata_2_MEM),
.WriteReg_MEM(WriteReg_MEM),
.MemOrAlu_MEM(MemOrAlu_MEM),
.WriteMem_MEM(WriteMem_MEM),
.ReadMem_MEM(ReadMem_MEM),
.opcode_MEM(opcode_MEM)
);
wire[`RegDataWidth-1:0] MEM_data_MEM;
// memory read/write
MEM mem(
.rst(rst),
.FWLS(FWLS),
.reg_data_2(rdata_2_MEM),
.WB_data(reg_write_data),
.raw_mem_data(data_from_mem),
.ReadMem(ReadMem_MEM),
.WriteMem(WriteMem_MEM),
.mem_addr(data_from_ALU_MEM),
.opcode(opcode_MEM),
.data_to_write_mem(data_to_write_mem),
.data_to_reg(MEM_data_MEM),
.byte_slct(mem_byte_slct)
);
assign mem_addr = data_from_ALU_MEM;
assign mem_re = ReadMem_MEM;
assign mem_we = WriteMem_MEM;
wire[`RegDataWidth-1:0] ALU_data_WB;
wire[`RegDataWidth-1:0] MEM_data_WB;
MEM_WB mem_wb_reg(
.clk(clk),
.rst(rst),
// set gnd temporarily
.is_hold(gnd),
.target_MEM(target_MEM),
.ALU_data_MEM(data_from_ALU_MEM),
.MEM_data_MEM(MEM_data_MEM),
.we_hi_MEM(we_hi_MEM),
.we_lo_MEM(we_lo_MEM),
.hi_MEM(hi_MEM),
.lo_MEM(lo_MEM),
.WriteReg_MEM(WriteReg_MEM),
.MemOrAlu_MEM(MemOrAlu_MEM),
.target_WB(reg_write_addr),
.ALU_data_WB(ALU_data_WB),
.MEM_data_WB(MEM_data_WB),
.we_hi_WB(we_hi),
.we_lo_WB(we_lo),
.hi_WB(hi_data_in),
.lo_WB(lo_data_in),
.WriteReg_WB(reg_we),
.MemOrAlu_WB(MemOrAlu_WB)
);
// See define.v
// MemOrAlu
// `define ALU 1'b1
// `define Mem 1'b0
mux2x1 #(.data_width(`RegDataWidth)) result_mux(
.in_0(MEM_data_WB),
.in_1(ALU_data_WB),
.slct(MemOrAlu_WB),
.out(reg_write_data)
);
// Control center
ForwardControl forwarding_handler(
.rst(rst),
.reg_data_1_addr_ID(raddr_1_ID),
.reg_data_2_addr_ID(raddr_2_ID),
.reg_data_1_addr_EX(raddr_1_EX),
.reg_data_2_addr_EX(raddr_2_EX),
.target_EX(target_EX),
.WriteReg_EX(WriteReg_EX),
.reg_data_2_addr_MEM(raddr_2_MEM),
.target_MEM(target_MEM),
.WriteReg_MEM(WriteReg_MEM),
.MemOrAlu_MEM(MemOrAlu_MEM),
.we_hi_MEM(we_hi_MEM),
.we_lo_MEM(we_lo_MEM),
.target_WB(reg_write_addr),
.WriteReg_WB(reg_we),
.we_hi_WB(we_hi),
.we_lo_WB(we_lo),
.FWA(FWA),
.FWB(FWB),
.FWhi(FWhi),
.FWlo(FWlo),
.FWLS(FWLS),
.FW_br_A(FW_br_A),
.FW_br_B(FW_br_B)
);
BranchControl branch_handler(
.rst(rst),
.pc_plus4_ID(pc_plus4_ID),
.inst_ID(inst_ID),
.FW_br_A(FW_br_A),
.FW_br_B(FW_br_B),
.rdata_1_ID(rdata_1_ID),
.rdata_2_ID(rdata_2_ID),
.data_out_EX(data_out_EX),
.data_from_ALU_MEM(data_from_ALU_MEM),
.MEM_data_MEM(MEM_data_MEM),
.branch_address(branch_address),
.is_branch(is_branch),
.is_rst_IF_ID(is_rst_IF_ID)
);
HazardControl hazard_handler(
.rst(rst),
.ReadMem_EX(ReadMem_EX),
.WriteMem_ID(WriteMem_ID),
.raddr_1_ID(raddr_1_ID),
.raddr_2_ID(raddr_2_ID),
.target_EX(target_EX),
.is_hold_IF(is_hold_IF),
.is_hold_IF_ID(is_hold_IF_ID),
.is_zeros_ID_EX(is_zeros_ID_EX)
);
endmodule
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
module
mulAddRecF16_add (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags,
output [15:0] out_imul
);
wire [16:0] recF16_1 = 'h08000;
mulAddRecFN#(5, 11)
mulAddRecFN(
control, {int_mul, 2'b0}, a, recF16_1, b, roundingMode, out, exceptionFlags, out_imul);
endmodule
module
mulAddRecF32_add (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags,
output [31:0] out_imul
);
wire [32:0] recF32_1 = 33'h080000000;
mulAddRecFN#(8, 24)
mulAddRecFN(
control, {int_mul, 2'b0}, a, recF32_1, b, roundingMode, out, exceptionFlags, out_imul);
endmodule
module
mulAddRecF64_add (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags,
output [63:0] out_imul
);
wire [64:0] recF64_1 = 65'h08000000000000000;
mulAddRecFN#(11, 53)
mulAddRecFN(
control, {int_mul, 2'b0}, a, recF64_1, b, roundingMode, out, exceptionFlags, out_imul);
endmodule
module
mulAddRecF128_add (
input [(`floatControlWidth - 1):0] control,
input [128:0] a,
input [128:0] b,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
wire [127:0] out_imul;
wire [128:0] recF128_1 = 129'h080000000000000000000000000000000;
mulAddRecFN#(15, 113, 0)
mulAddRecFN(
control, 3'b0, a, recF128_1, b, roundingMode, out, exceptionFlags, out_imul
);
endmodule
module
mulAddRecF16_mul (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags,
output [15:0] out_imul
);
wire [16:0] zeroAddend = {a[16] ^ b[16], 16'b0};
mulAddRecFN#(5, 11)
mulAddRecFN(
control, {int_mul, 2'b0}, a, b, zeroAddend, roundingMode, out, exceptionFlags, out_imul
);
endmodule
module
mulAddRecF32_mul (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags,
output [31:0] out_imul
);
wire [32:0] zeroAddend = {a[32] ^ b[32], 32'b0};
mulAddRecFN#(8, 24)
mulAddRecFN(
control, {int_mul, 2'b0}, a, b, zeroAddend, roundingMode, out, exceptionFlags, out_imul
);
endmodule
module
mulAddRecF64_mul (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags,
output [63:0] out_imul
);
wire [64:0] zeroAddend = {a[64] ^ b[64], 64'b0};
mulAddRecFN#(11, 53)
mulAddRecFN(
control, {int_mul, 2'b0}, a, b, zeroAddend, roundingMode, out, exceptionFlags, out_imul
);
endmodule
module
mulAddRecF128_mul (
input [(`floatControlWidth - 1):0] control,
input [128:0] a,
input [128:0] b,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
wire [128:0] zeroAddend = {a[128] ^ b[128], 128'b0};
wire [127:0] out_imul;
mulAddRecFN#(15, 113, 0)
mulAddRecFN(
control, 3'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags,out_imul
);
endmodule
module
mulAddRecF16 (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [2:0] op,
input [16:0] a,
input [16:0] b,
input [16:0] c,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags,
output [15:0] out_imul
);
mulAddRecFN#(5, 11)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags, out_imul);
endmodule
module
mulAddRecF32 (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [2:0] op,
input [32:0] a,
input [32:0] b,
input [32:0] c,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags,
output [31:0] out_imul
);
mulAddRecFN#(8, 24)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags, out_imul);
endmodule
module
mulAddRecF64 (
input [(`floatControlWidth - 1):0] control,
input int_mul,
input [2:0] op,
input [64:0] a,
input [64:0] b,
input [64:0] c,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags,
output [63:0] out_imul
);
mulAddRecFN#(11, 53)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags, out_imul);
endmodule
module
mulAddRecF128 (
input [(`floatControlWidth - 1):0] control,
input [2:0] op,
input [128:0] a,
input [128:0] b,
input [128:0] c,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
wire [127:0] out_imul;
mulAddRecFN#(15, 113)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags, out_imul);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S50_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLYGATE4S50_PP_SYMBOL_V
/**
* dlygate4s50: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlygate4s50 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S50_PP_SYMBOL_V
|
//=============================================================
//
// Copyright (c) 2017 Simon Southwell. All rights reserved.
//
// Date: 11th August 2017
//
// This code is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// The code is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this code. If not, see <http://www.gnu.org/licenses/>.
//
// $Id: wb_mux.v,v 1.1 2017/08/22 09:16:05 simon Exp $
// $Source: /home/simon/CVS/src/cpu/mico32/HDL/rtl/wb_mux.v,v $
//
//=============================================================
`include "regs.vh"
// Wishbone bus multiplexer, with high priority and low priority
// bus master interfaces, muxed to a single interface. High
// priority interface always wins when bus is inactive, but low
// priority access is not interrupted if already started when
// high prirority request asserted.
module wb_mux (sys_clk,
resetcpu,
// High priority bus
h_cyc,
h_stb,
h_we,
h_sel,
h_ack,
h_adr,
h_dat_o,
h_dat_i,
// Low priority bus
l_cyc,
l_stb,
l_we,
l_sel,
l_ack,
l_adr,
l_dat_o,
l_dat_i,
// Muxed bus
m_cyc,
m_stb,
m_we,
m_sel,
m_ack,
m_adr,
m_dat_o,
m_dat_i
);
input sys_clk;
input resetcpu;
input h_cyc;
input h_stb;
input h_we;
input [3:0] h_sel;
input [31:0] h_adr;
input [31:0] h_dat_o; // An input, but matches name of LM32 interface
output [31:0] h_dat_i; // An output, but matches name of LM32 interface
output h_ack;
input l_cyc;
input l_stb;
input l_we;
input [3:0] l_sel;
input [31:0] l_adr;
input [31:0] l_dat_o; // An input, but matches name of LM32 interface
output [31:0] l_dat_i; // An output, but matches name of LM32 interface
output l_ack;
output m_cyc;
output m_stb;
output m_we;
output [3:0] m_sel;
output [31:0] m_adr;
output [31:0] m_dat_o;
input [31:0] m_dat_i;
input m_ack;
reg active;
reg h_owns_bus_reg;
// Select high priority bus, if bus inactive and high priority bus
// requesting, or (when active), it is the selected bus.
wire sel_h = (h_cyc & ~active) | (h_owns_bus_reg & active);
// Mux the outputs from the two busses
assign m_cyc = h_cyc | l_cyc;
assign m_stb = sel_h ? h_stb : l_stb;
assign m_we = sel_h ? h_we : l_we;
assign m_sel = sel_h ? h_sel : l_sel;
assign m_adr = sel_h ? h_adr : l_adr;
assign m_dat_o = sel_h ? h_dat_o : l_dat_o;
// Route read data back to sources (regardless of bus selection)
assign h_dat_i = m_dat_i;
assign l_dat_i = m_dat_i;
// Route ACK back to selected bus.
// Using h_owns_bus_reg assumes there can be no ACK earlier than the
// next cycle. If ACK can be in the same cycle as assertion of m_cyc,
// then sel_h should be used, but this has slow timing and could, potentially,
// create a timing loop, as ack would then be dependant on <x>_cyc.
assign h_ack = h_owns_bus_reg & m_ack;
assign l_ack = ~h_owns_bus_reg & m_ack;
always @(posedge sys_clk or posedge resetcpu)
begin
if (resetcpu == 1'b1)
begin
active <= 1'b0;
h_owns_bus_reg <= 1'b0;
end
else
begin
// Go active (and hold) if either bus requesting, clearing state on the returned ACK
active <= (active | h_cyc | l_cyc) & ~m_ack;
// Flag high priority bus ownership, and hold, or if that bus requesting and inactive.
h_owns_bus_reg <= (active & h_owns_bus_reg) | (~active & h_cyc);
end
end
endmodule
|
//-------------------------------------------------------------------------
// COPYRIGHT (C) 2016 Univ. of Nebraska - Lincoln
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//-------------------------------------------------------------------------
// Title : okWireIn_sync
// Author : Caleb Fangmeier
// Description : This is a simple wrapper of the okWireIn that syncronizes
// the signals with another clock by means of a shallow fifo buffer.
//
// $Id$
//-------------------------------------------------------------------------
`default_nettype none
`timescale 1ns / 1ps
module okWireIn_sync (
input wire clk,
input wire okClk,
input wire [112:0] okHE,
input wire [7:0] ep_addr,
output reg [31:0] ep_dataout
);
wire [31:0] control_bus;
wire [31:0] q_buff;
wire rdempty;
reg rdreq;
always @( posedge clk ) begin
if ( rdreq ) begin
ep_dataout <= q_buff;
end
rdreq <= ~rdempty;
end
fifo32_shallow fifo32_shallow_inst (
.data ( control_bus ),
.rdclk ( clk ),
.rdreq ( rdreq ),
.wrclk ( okClk ),
.wrreq ( 1'b1 ),
.q ( q_buff ),
.rdempty ( rdempty ),
.wrfull ( )
);
okWireIn control_wires(
.okHE(okHE),
.ep_addr(ep_addr),
.ep_dataout(control_bus)
);
endmodule
|
module pipeline(
input Clk,
output [31:0] PC_in,PC_out,
output [2:0]PCSrc,
//1
/*output[5:0] Op_IF,
output[4:0] Rs_IF,Rt_IF,Rd_IF,Shamt_IF,
output[5:0] Func_IF,
*/
//3
/*output[31:0] Branch_addr_EX,PC_Add_EX,
output[2:0] Condition_EX,
output Branch_EX,
output[2:0]PC_write_EX,
output[3:0]Mem_Write_Byte_en_EX,Rd_Write_Byte_en_EX,
output MemWBSrc_EX,OverflowEn_EX,
output[31:0] MemData_EX,WBData_EX,
output Less_EX,Zero_EX,Overflow_EX,
output[4:0]Rd_EX,
output flash_ID,flash_EX,
//4
output[31:0] MemData_Mem,Data_out,
output[31:0] WBData_Mem,
output MemWBSrc_Mem,
output[3:0] Rd_Write_Byte_en_Mem,
output[4:0] Rd_Mem,
output [31:0] Immediate32_IF,ALU_OpA,ALU_OpB,ALU_out,RegShift,
output [1:0] Rs_EX_Forward,Rt_EX_Forward,
output [4:0]ShiftAmount
*/
output flash_ID,flash_EX,
output [31:0] OperandA_ID,OperandB_ID,
output [4:0] Rs_ID,Rt_ID,Rd_ID,Rd_EX,Rd_Mem,
output [31:0] Immediate32_ID,
output [2:0] MemDataSrc_ID,
output ALUSrcA_ID,ALUSrcB_ID,Jump_ID,
output [3:0] ALUOp_ID,Rd_Write_Byte_en_Mem,MemWriteEn,RdWriteEn,
output [31:0] IR_IF,Shifter_out,Rd_in,MemData_EX,Data_out,WBData_EX,
output [4:0]ShiftAmount,
output [1:0] Rs_EX_Forward,Rt_EX_Forward,
output [31:0] Immediate32_IF,ALU_OpA,ALU_OpB,ALU_out,RegShift
);
//--------Harzard----------------------------------
//wire[2:0] PCSrc;
//--------PC---------------------------------------
//wire[31:0] PC_in,PC_out;
//--------PC+4-------------------------------------
wire[31:0] PC_Add_IF;
//--------InstruMemory-----------------------------
wire[31:0] ins_data;//,IR_IF;
//--------IF_ID Seg1-------------------------------
wire stall_IF;
wire flash_IF;
wire[5:0] Op_IF;
wire[4:0] Rs_IF,Rt_IF,Rd_IF,Shamt_IF;
wire[5:0] Func_IF;
//--------Controller-------------------------------
wire RegDt0_IF,ID_RsRead_IF,ID_RtRead_IF;
wire[1:0] Ex_top_IF;
wire BranchSel_IF;
wire OverflowEn_IF;
wire[2:0] Condition_IF;
wire Branch_IF;
wire[2:0] PC_write_IF;
wire[3:0] Mem_Write_Byte_en_IF,Rd_Write_Byte_en_IF,ALUOp_IF;
wire MemWBSrc_IF;
wire Jump_IF;
wire ALUShiftSel_IF;
wire[2:0] MemDataSrc_IF;
wire ALUSrcA_IF,ALUSrcB_IF;
//wire[3:0] ALUOp_IF;
wire[1:0] RegDst_IF;
wire ShiftAmountSrc_IF;
wire[1:0] Shift_Op_IF;
//---------Registers-------------------------------
wire[31:0] Rs_out,Rt_out;//Rd_in
//---------expansion-------------------------------
//wire[31:0] Immediate32_IF;
//---------ID_EX Seg2------------------------------
wire stall_ID;//flash_ID,
wire[31:0]PC_Add_ID;
wire OverflowEn_ID;
wire[2:0] Condition_ID;
wire Branch_ID,EX_RsRead_ID,EX_RtRead_ID;
wire[2:0] PC_write_ID;
wire[3:0] Mem_Write_Byte_en_ID,Rd_Write_Byte_en_ID;
wire MemWBSrc_ID,ALUShiftSel_ID;
//wire[2:0] MemDataSrc_ID;
//wire ALUSrcA_ID,ALUSrcB_ID;
//wire[3:0] ALUOp_ID;
wire[1:0] RegDst_ID;
wire ShiftAmountSrc_ID;
wire[1:0] Shift_Op_ID;
//wire[31:0] OperandA_ID,OperandB_ID;
//wire[4:0] Rs_ID,Rt_ID,Rd_ID;
//wire[31:0] Immediate32_ID;
wire[4:0]Shamt_ID;
//----------JUMP branch---------------------------
wire[31:0] Branch_addr_ID,Jump_Done;
//----------Forward-------------------------------
//wire[1:0] Rs_EX_Forward,Rt_EX_Forward;
wire Rs_LoudUse_Forward,Rt_LoudUse_Forward;
//----------After ALU and ID/EX mux---------------
wire[31:0] mux4one,mux4two,mux4three,mux8one;
wire Zero,Less,Overflow,BranchSel_ID;
//wire[31:0] ALU_out;
//----------Shifter-------------------------------
//wire[31:0] Shifter_out;
//wire [4:0]ShiftAmount;
//----------Ex_MEM Seg3--------------------------
wire stall_EX;//flash_EX
wire OverflowEn_EX;
wire[31:0] Branch_addr_EX,PC_Add_EX;
wire[2:0] Condition_EX;
wire Branch_EX,MemWBSrc_EX;
wire[2:0]PC_write_EX;
wire[3:0]Mem_Write_Byte_en_EX,Rd_Write_Byte_en_EX;
//wire[31:0] WBData_EX;//MemData_EX,
wire Less_EX,Zero_EX,Overflow_EX;
//wire[4:0]Rd_EX;
//----------Condition------------------------------
wire BranchValid;
//wire[3:0] RdWriteEn;//,MemWriteEn;
//----------DataMemory-----------------------------
wire [31:0]Mem_data_shift;
//----------MEM_WB Seg4---------------------------
wire stall_Mem,flash_Mem;
wire[31:0] MemData_Mem;
wire[31:0] WBData_Mem;
wire MemWBSrc_Mem;
//wire[3:0] Rd_Write_Byte_en_Mem;
//wire[4:0] Rd_Mem;
//-----------------------------------------------Hazard-------------------------------------------------------
HazardControl hazard(BranchValid,Jump_ID,MemWBSrc_ID,ID_RsRead_IF,ID_RtRead_IF,Rs_IF,Rt_IF,Rt_ID,
//output
stall_IF,stall_ID,stall_EX,stall_Mem,flash_IF,flash_ID,flash_EX,flash_Mem,PCSrc);
//-------------------------------------------------PC---------------------------------------------------------
wire[31:0] PC_Add_IF_in;
Mux4_1 PC_selcet(PC_Add_IF,Jump_Done,Branch_addr_EX,mux4one,PCSrc,PC_in);
PC pc(Clk,PC_in,PC_out);
//------------------------------------------------PC+4---------------------------------------------------------
assign PC_Add_IF_in = PC_out + 4;
//---------------------------------------------InstructMemory--------------------------------------------------
parameter ins_we = 4'b0000;
assign ins_data = 0;
InstruMemory instruct(ins_data,PC_out,ins_we,Clk,IR_IF);
//----------------------------------------------IF_ID_Seg Seg1-------------------------------------------------
IF_ID_Seg Seg1(Clk,stall_IF,flash_IF,PC_Add_IF_in,IR_IF,PC_Add_IF,Op_IF,Rs_IF,Rt_IF,Rd_IF,Shamt_IF,Func_IF);
//----------------------------------------------Controller-----------------------------------------------------
Controller controller(Op_IF,Rs_IF,Rt_IF,Rd_IF,Shamt_IF,Func_IF,RegDt0_IF,ID_RsRead_IF,ID_RtRead_IF,Ex_top_IF,BranchSel_IF,
OverflowEn_IF,Condition_IF,Branch_IF,PC_write_IF,Mem_Write_Byte_en_IF,Rd_Write_Byte_en_IF,MemWBSrc_IF,Jump_IF,
ALUShiftSel_IF,MemDataSrc_IF,ALUSrcA_IF,ALUSrcB_IF,ALUOp_IF,RegDst_IF,ShiftAmountSrc_IF,Shift_Op_IF);
//----------------------------------------------Registers------------------------------------------------------
assign Rd_in = (MemWBSrc_Mem == 0)?WBData_Mem:MemData_Mem;
MIPS_Register mipsregister(Rs_IF,((RegDt0_IF == 1'b1)?Rt_IF:5'b00000),Rd_Mem,Clk,Rd_Write_Byte_en_Mem,Rd_in,Rs_out,Rt_out);
//--------------------------------------------expansion--------------------------------------------------------
NumExpansion expansion({Rd_IF[4:0],Shamt_IF[4:0],Func_IF[5:0]},Ex_top_IF,Immediate32_IF);
//------------------------------------------ID_EX Seg2-------------------------------------------------------
ID_EX_Seg seg2(Clk,stall_ID,flash_ID,PC_Add_IF,OverflowEn_IF,Condition_IF,Branch_IF,PC_write_IF,
Mem_Write_Byte_en_IF,Rd_Write_Byte_en_IF,MemWBSrc_IF,Jump_IF,ALUShiftSel_IF,MemDataSrc_IF,ALUSrcA_IF,ALUSrcB_IF,
ALUOp_IF,RegDst_IF,ShiftAmountSrc_IF,Shift_Op_IF,(Rs_LoudUse_Forward == 0)?Rs_out:Rd_in,
(Rt_LoudUse_Forward == 0)?Rt_out:Rd_in,Rs_IF,Rt_IF,Rd_IF,Immediate32_IF,Shamt_IF,BranchSel_IF,
{ID_RsRead_IF,ID_RtRead_IF},
//output
PC_Add_ID,OverflowEn_ID,Condition_ID,Branch_ID,PC_write_ID,Mem_Write_Byte_en_ID,Rd_Write_Byte_en_ID,
MemWBSrc_ID,Jump_ID,ALUShiftSel_ID,MemDataSrc_ID,ALUSrcA_ID,ALUSrcB_ID,
ALUOp_ID,RegDst_ID,ShiftAmountSrc_ID,Shift_Op_ID,OperandA_ID,OperandB_ID,Rs_ID,Rt_ID,Rd_ID,Immediate32_ID,Shamt_ID,
BranchSel_ID,{EX_RsRead_ID,EX_RtRead_ID}
);
//----------------------------------------JUMP branch Module---------------------------------------------------
assign Branch_addr_ID = PC_Add_ID + {Immediate32_ID[29:0],2'b00};
assign Jump_Done = {PC_Add_ID[31:28],Rs_ID,Rt_ID,Immediate32_ID[15:0],2'b00};
//-----------------------------------------forward-------------------------------------------------------------
Forward forward({EX_RsRead_ID,EX_RtRead_ID},Rt_ID,Rs_ID,Rd_EX,RdWriteEn,Rd_Mem,Rd_Write_Byte_en_Mem,
//output
Rs_EX_Forward,Rt_EX_Forward,
//input
Rt_IF,Rs_IF,{ID_RsRead_IF,ID_RtRead_IF},
//output
Rs_LoudUse_Forward,Rt_LoudUse_Forward);
//--------------------------------------after ALU and ID/EX Mux------------------------------------------------
Mux4_1 mux4_one(OperandA_ID,WBData_EX,Rd_in,0,Rs_EX_Forward,mux4one);
Mux4_1 mux4_two(OperandB_ID,WBData_EX,Rd_in,0,Rt_EX_Forward,mux4two);
Mux4_1 mux4_three(Rd_ID,Rt_ID,5'b11111,0,RegDst_ID,mux4three);
MUX8_1_ALU mux8_one(MemDataSrc_ID,32'b0,mux4two,PC_Add_ID + 4,0,0,0,0,0,mux8one); //rt
assign ALU_OpA = (ALUSrcA_ID == 0)?mux4one:0;
assign ALU_OpB = (ALUSrcB_ID == 0)?mux4two:Immediate32_ID;
ALU alu(ALU_OpA,ALU_OpB,ALUOp_ID,Zero,Less,Overflow,ALU_out);
assign ShiftAmount = (ShiftAmountSrc_ID == 1)?mux4one[4:0]:Shamt_ID;
//--------------------------------------------shifter-----------------------------------------------------------
MIPS_Shifter shifter(mux4two,ShiftAmount,Shift_Op_ID,Shifter_out);
//-----------------------------------------EX_MEM---Seg3--------------------------------------------------------
EX_MEM_Seg seg3(Clk,stall_EX,flash_EX,Branch_addr_ID,PC_Add_ID,Condition_ID,Branch_ID,PC_write_ID,
Mem_Write_Byte_en_ID,Rd_Write_Byte_en_ID,MemWBSrc_ID,OverflowEn_ID,
mux8one,((BranchSel_ID == 1'b0) ? ((ALUShiftSel_ID == 1'b0)?Shifter_out:ALU_out): mux8one),Less,Zero,Overflow,mux4three,
//output
Branch_addr_EX,PC_Add_EX,Condition_EX,Branch_EX,PC_write_EX,Mem_Write_Byte_en_EX,
Rd_Write_Byte_en_EX,MemWBSrc_EX,OverflowEn_EX,
MemData_EX,WBData_EX,Less_EX,Zero_EX,Overflow_EX,Rd_EX
);
//----------------------------------------Condition--------------------------------------------------------------
Condition_Check condition_check(Condition_EX,PC_write_EX,WBData_EX[1:0],MemWBSrc_EX,OverflowEn_EX,Branch_EX,Overflow_EX,Mem_Write_Byte_en_EX,Rd_Write_Byte_en_EX,Less_EX,Zero_EX,
//output
BranchValid,RdWriteEn,MemWriteEn);
//---------------------------------------DataMemory--------------------------------------------------------------
//wire [31:0] RegShift;
Register_ShiftOutput regshift(MemData_EX,WBData_EX[1:0],{3'b101,PC_write_EX[2:0]},RegShift);
DataMemory datamemory(RegShift,WBData_EX,MemWriteEn,Clk,Data_out);
Memory_ShiftOutput memshift(Data_out,WBData_EX[1:0],{3'b100,PC_write_EX[2:0]},Mem_data_shift);
//---------------------------------------DataMemoryWithCache-----------------------------------------------------
//------------------------------You can choose one section from DataMemory or DataMemory with cache--------------
/*wire hit;
wire [63:0] ReadRam;
wire writeback;
wire [7:0] readramn,writeramn;
Register_ShiftOutput regshift(MemData_EX,WBData_EX[1:0],{3'b101,PC_write_EX[2:0]},RegShift);
Cache DataMemorywithCache(RegShift,WBData_EX,MemWriteEn,Clk,Data_out,hit,ReadRam,writeback,readramn,writeramn);
Memory_ShiftOutput memshift(Data_out,WBData_EX[1:0],{3'b100,PC_write_EX[2:0]},Mem_data_shift);
*/
//--------------------------------------MEM_WB---Seg4------------------------------------------------------------
MEM_WB_Seg seg4(Clk,stall_Mem,flash_Mem,Mem_data_shift,WBData_EX,MemWBSrc_EX,RdWriteEn,Rd_EX,
//output
MemData_Mem,WBData_Mem,MemWBSrc_Mem,Rd_Write_Byte_en_Mem,Rd_Mem);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__XNOR2_PP_SYMBOL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__xnor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_PP_SYMBOL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:25:47 05/08/2012
// Design Name: cls_spi
// Module Name: G:/Projects/s6atlystest/cls_spi_tb.v
// Project Name: s6atlystest
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cls_spi
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cls_spi_tb;
// Inputs
reg clock;
reg reset;
reg [31:0] data;
reg miso;
// Outputs
wire ss;
wire mosi;
wire sclk;
// Instantiate the Unit Under Test (UUT)
cls_spi uut (
.clock(clock),
.reset(reset),
.data(data),
.ss(ss),
.mosi(mosi),
.miso(miso),
.sclk(sclk)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 1;
data = 32'h89ABCDEF;
miso = 0;
// Wait 100 ns for global reset to finish
#100 reset = 0;
end
always begin
#10 clock = !clock;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXBP_TB_V
`define SKY130_FD_SC_LS__DFXBP_TB_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfxbp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__dfxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXBP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2OI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A2BB2OI_BEHAVIORAL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2OI_BEHAVIORAL_V
|
// Single-bit clock-domain crossing synchronizer
//
// Notes:
// A synchronizer is a device that takes an asynchronous
// input and produces an output signal that transitions
// synchronous to a sample clock
//
// The single-bit clock domain synchronizer safely
// transfers the output from clock domain A to
// clock domain B. Without the synchronizer, the
// input of the receiving clock domain can go
// metastable at the first register stage of the
// sampling domain. A good synchronizer
// removes the probability of input going metastable
// by moving the input through register stages in
// the target clock domain
//
// Mean Time Between Failures defines the probability
// of the o/p of the sampling domain going metastable.
// MTBF = 1/(freq of sampling * freq of data change *X)
// Higher MTBF, the better
// As freq of sampling increases, probability of metastability
// is higher (lower MTBF)
//
// It is generally recommended that the output of the
// launching clock domain is registered before synchronizing.
// Consider the case where a signal is derived through some
// combinational logic before getting transfered from clock
// domain A to B. The probability of glitching after the
// combinational logic is very high, which in turn increases
// probability of metastability at the latching clock domain.
//
// The synchronizer may be used in different scenarios
// - Case 1: Transfer from slow clock domain to fast
// - Case 2: Transfer from fast clock domain to slow
// - Case 3: Transfer b/w unrelated clocks with same frequency,
//
// Case 1 is the most straightforward. A CDC with >=2 stages is
// sufficient. Case 2 is tricky because the launch data can
// change multiple times before capturing in the latching domain.
// In this situation, it is recommended that either the launch clock
// hold the data for at-least 3 clock cycles of the latch
// clock domain (open-loop solution) or hold the data until
// the latch domain sends back an acknowledgment (closed-loop
// solution).
//
module single_bit_cdc_synchronizer #(
parameter NUM_STAGES = 3 // minimum 2 stages, recommended 3 stages
// probability of metastability decreases
// exponentially with #stages
) (
input clk, //latch clock
input d_in,
output q_out;
);
reg[NUM_STAGES-1:0] r;
assign q_out=r[NUM_STAGES-1];
integer i;
always@(posedge latch_clk)
begin
for(i=1; i<NUM_STAGES; i=i+1) begin
r[i] <= r[i-1];
end
end
endmodule
|
// Copyright (c) 2013, Simon Que
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
`timescale 1ns/1ps
`include "spi_memory.vh"
module SPIMemoryTest;
// SPI interface.
reg _select, sck, mosi;
wire miso;
// Memory interface.
wire [`SPI_MEM_ADDR_WIDTH-1:0] addr;
wire [`SPI_MEM_DATA_WIDTH-1:0] data_in;
wire [`SPI_MEM_DATA_WIDTH-1:0] data_out;
wire rd, wr;
// Instantiate the Unit Under Test (UUT).
SPIMemory spi_memory(
._select(_select), .sck(sck), .mosi(mosi), .miso(miso),
.addr(addr), .data_in(data_in), .data_out(data_out), .rd(rd), .wr(wr)
);
// Don't have actual memory, so just use the lower byte of address as the data
// read from memory.
assign data_in = rd ? addr[`SPI_MEM_DATA_WIDTH-1:0] : 'bx;
initial begin
_select = 0;
sck = 0;
mosi = 0;
#1 _select = 1;
// Perform some writes.
#10
_select = 0;
spi_transmit(8'hde); // Write to address 0x5ead.
spi_transmit(8'had);
spi_transmit(8'h01); // These are the data bytes written.
spi_transmit(8'h02);
spi_transmit(8'h04);
spi_transmit(8'h08);
_select = 1;
#10
_select = 0;
spi_transmit(8'hbe); // Write to address 0x3eef.
spi_transmit(8'hef);
spi_transmit(8'h11); // These are the data bytes written.
spi_transmit(8'h22);
spi_transmit(8'h44);
spi_transmit(8'h88);
_select = 1;
// Perform some reads.
#10
_select = 0;
spi_transmit(8'h5a); // Read from address 0x5afe.
spi_transmit(8'hfe);
spi_transmit(8'h01); // These dummy data bytes should not show up.
spi_transmit(8'h02);
spi_transmit(8'h04);
spi_transmit(8'h08);
_select = 1;
#10
_select = 0;
spi_transmit(8'h7f); // Test wraparound during read.
spi_transmit(8'hfe);
spi_transmit(8'h11); // These dummy data bytes should not show up.
spi_transmit(8'h22);
spi_transmit(8'h44);
spi_transmit(8'h88);
_select = 1;
#10
_select = 0;
spi_transmit(8'hff); // Test wraparound during write.
spi_transmit(8'hfe);
spi_transmit(8'h11); // These dummy data bytes should not show up.
spi_transmit(8'h22);
spi_transmit(8'h44);
spi_transmit(8'h88);
_select = 1;
end
// Task to send a byte over SPI.
task spi_transmit;
input [`BYTE_WIDTH-1:0] data;
integer i;
begin
sck = 0;
#2
sck = 0;
for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin
mosi = data[`BYTE_WIDTH - 1 - i];
#1
sck = 1;
#1
sck = 0;
end
#2
sck = 0;
end
endtask
endmodule
|
(** * Auto: More Automation *)
Require Import Coq.omega.Omega.
Require Import Maps.
Require Import Imp.
(** Up to now, we've used the more manual part of Coq's tactic
facilities. In this chapter, we'll learn more about some of Coq's
powerful automation features: proof search via the [auto] tactic,
automated forward reasoning via the [Ltac] hypothesis matching
machinery, and deferred instantiation of existential variables
using [eapply] and [eauto]. Using these features together with
Ltac's scripting facilities will enable us to make our proofs
startlingly short! Used properly, they can also make proofs more
maintainable and robust to changes in underlying definitions. A
deeper treatment of [auto] and [eauto] can be found in the
[UseAuto] chapter.
There's another major category of automation we haven't discussed
much yet, namely built-in decision procedures for specific kinds
of problems: [omega] is one example, but there are others. This
topic will be deferred for a while longer.
Our motivating example will be this proof, repeated with just a
few small changes from the [Imp] chapter. We will simplify
this proof in several stages. *)
Ltac inv H := inversion H; subst; clear H.
Theorem ceval_deterministic: forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
induction E1; intros st2 E2; inv E2.
- (* E_Skip *) reflexivity.
- (* E_Ass *) reflexivity.
- (* E_Seq *)
assert (st' = st'0) as EQ1.
{ (* Proof of assertion *) apply IHE1_1; assumption. }
subst st'0.
apply IHE1_2. assumption.
(* E_IfTrue *)
- (* b evaluates to true *)
apply IHE1. assumption.
- (* b evaluates to false (contradiction) *)
rewrite H in H5. inversion H5.
(* E_IfFalse *)
- (* b evaluates to true (contradiction) *)
rewrite H in H5. inversion H5.
- (* b evaluates to false *)
apply IHE1. assumption.
(* E_WhileEnd *)
- (* b evaluates to false *)
reflexivity.
- (* b evaluates to true (contradiction) *)
rewrite H in H2. inversion H2.
(* E_WhileLoop *)
- (* b evaluates to false (contradiction) *)
rewrite H in H4. inversion H4.
- (* b evaluates to true *)
assert (st' = st'0) as EQ1.
{ (* Proof of assertion *) apply IHE1_1; assumption. }
subst st'0.
apply IHE1_2. assumption. Qed.
(* ################################################################# *)
(** * The [auto] Tactic *)
(** Thus far, our proof scripts mostly apply relevant hypotheses or
lemmas by name, and one at a time. *)
Example auto_example_1 : forall (P Q R: Prop),
(P -> Q) -> (Q -> R) -> P -> R.
Proof.
intros P Q R H1 H2 H3.
apply H2. apply H1. assumption.
Qed.
(** The [auto] tactic frees us from this drudgery by _searching_ for a
sequence of applications that will prove the goal *)
Example auto_example_1' : forall (P Q R: Prop),
(P -> Q) -> (Q -> R) -> P -> R.
Proof.
intros P Q R H1 H2 H3.
auto.
Qed.
(** The [auto] tactic solves goals that are solvable by any combination of
- [intros] and
- [apply] (of hypotheses from the local context, by default). *)
(** Using [auto] is always "safe" in the sense that it will never fail
and will never change the proof state: either it completely solves
the current goal, or it does nothing. *)
(** Here is a more interesting example showing [auto]'s power: *)
Example auto_example_2 : forall P Q R S T U : Prop,
(P -> Q) ->
(P -> R) ->
(T -> R) ->
(S -> T -> U) ->
((P->Q) -> (P->S)) ->
T ->
P ->
U.
Proof. auto. Qed.
(** Proof search could, in principle, take an arbitrarily long time,
so there are limits to how far [auto] will search by default. *)
Example auto_example_3 : forall (P Q R S T U: Prop),
(P -> Q) ->
(Q -> R) ->
(R -> S) ->
(S -> T) ->
(T -> U) ->
P ->
U.
Proof.
(* When it cannot solve the goal, [auto] does nothing *)
auto.
(* Optional argument says how deep to search (default is 5) *)
auto 6.
Qed.
(** When searching for potential proofs of the current goal,
[auto] considers the hypotheses in the current context together
with a _hint database_ of other lemmas and constructors. Some
common lemmas about equality and logical operators are installed
in this hint database by default. *)
Example auto_example_4 : forall P Q R : Prop,
Q ->
(Q -> R) ->
P \/ (Q /\ R).
Proof. auto. Qed.
(** We can extend the hint database just for the purposes of one
application of [auto] by writing [auto using ...]. *)
Lemma le_antisym : forall n m: nat, (n <= m /\ m <= n) -> n = m.
Proof. intros. omega. Qed.
Example auto_example_6 : forall n m p : nat,
(n <= p -> (n <= m /\ m <= n)) ->
n <= p ->
n = m.
Proof.
intros.
auto. (* does nothing: auto doesn't destruct hypotheses! *)
auto using le_antisym.
Qed.
(** Of course, in any given development there will probably be
some specific constructors and lemmas that are used very often in
proofs. We can add these to the global hint database by writing
Hint Resolve T.
at the top level, where [T] is a top-level theorem or a
constructor of an inductively defined proposition (i.e., anything
whose type is an implication). As a shorthand, we can write
Hint Constructors c.
to tell Coq to do a [Hint Resolve] for _all_ of the constructors
from the inductive definition of [c].
It is also sometimes necessary to add
Hint Unfold d.
where [d] is a defined symbol, so that [auto] knows to expand uses
of [d], thus enabling further possibilities for applying lemmas that
it knows about. *)
Hint Resolve le_antisym.
Example auto_example_6' : forall n m p : nat,
(n<= p -> (n <= m /\ m <= n)) ->
n <= p ->
n = m.
Proof.
intros.
auto. (* picks up hint from database *)
Qed.
Definition is_fortytwo x := x = 42.
Example auto_example_7: forall x, (x <= 42 /\ 42 <= x) -> is_fortytwo x.
Proof.
auto. (* does nothing *)
Abort.
Hint Unfold is_fortytwo.
Example auto_example_7' : forall x, (x <= 42 /\ 42 <= x) -> is_fortytwo x.
Proof. auto. Qed.
(** Now let's take a first pass over [ceval_deterministic] to simplify
the proof script.
*)
Theorem ceval_deterministic': forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2;
induction E1; intros st2 E2; inv E2; auto.
- (* E_Seq *)
assert (st' = st'0) as EQ1 by auto.
subst st'0.
auto.
- (* E_IfTrue *)
+ (* b evaluates to false (contradiction) *)
rewrite H in H5. inversion H5.
- (* E_IfFalse *)
+ (* b evaluates to true (contradiction) *)
rewrite H in H5. inversion H5.
- (* E_WhileEnd *)
+ (* b evaluates to true (contradiction) *)
rewrite H in H2. inversion H2.
(* E_WhileLoop *)
- (* b evaluates to false (contradiction) *)
rewrite H in H4. inversion H4.
- (* b evaluates to true *)
assert (st' = st'0) as EQ1 by auto.
subst st'0.
auto.
Qed.
(** When we are using a particular tactic many times in a proof, we
can use a variant of the [Proof] command to make that tactic into
a default within the proof. Saying [Proof with t] (where [t] is
an arbitrary tactic) allows us to use [t1...] as a shorthand for
[t1;t] within the proof. As an illustration, here is an alternate
version of the previous proof, using [Proof with auto]. *)
Theorem ceval_deterministic'_alt: forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof with auto.
intros c st st1 st2 E1 E2;
generalize dependent st2;
induction E1;
intros st2 E2; inv E2...
- (* E_Seq *)
assert (st' = st'0) as EQ1...
subst st'0...
- (* E_IfTrue *)
+ (* b evaluates to false (contradiction) *)
rewrite H in H5. inversion H5.
- (* E_IfFalse *)
+ (* b evaluates to true (contradiction) *)
rewrite H in H5. inversion H5.
- (* E_WhileEnd *)
+ (* b evaluates to true (contradiction) *)
rewrite H in H2. inversion H2.
(* E_WhileLoop *)
- (* b evaluates to false (contradiction) *)
rewrite H in H4. inversion H4.
- (* b evaluates to true *)
assert (st' = st'0) as EQ1...
subst st'0...
Qed.
(* ################################################################# *)
(** * Searching For Hypotheses *)
(** The proof has become simpler, but there is still an annoying
amount of repetition. Let's start by tackling the contradiction
cases. Each of them occurs in a situation where we have both
H1: beval st b = false
and
H2: beval st b = true
as hypotheses. The contradiction is evident, but demonstrating it
is a little complicated: we have to locate the two hypotheses [H1]
and [H2] and do a [rewrite] following by an [inversion]. We'd
like to automate this process.
(In fact, Coq has a built-in tactic [congruence] that will do the
job in this case. But we'll ignore the existence of this tactic
for now, in order to demonstrate how to build forward search
tactics by hand.)
As a first step, we can abstract out the piece of script in
question by writing a little function in Coq's tactic programming
language, Ltac. *)
Ltac rwinv H1 H2 := rewrite H1 in H2; inv H2.
Theorem ceval_deterministic'': forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2;
induction E1; intros st2 E2; inv E2; auto.
- (* E_Seq *)
assert (st' = st'0) as EQ1 by auto.
subst st'0.
auto.
- (* E_IfTrue *)
+ (* b evaluates to false (contradiction) *)
rwinv H H5.
- (* E_IfFalse *)
+ (* b evaluates to true (contradiction) *)
rwinv H H5.
- (* E_WhileEnd *)
+ (* b evaluates to true (contradiction) *)
rwinv H H2.
(* E_WhileLoop *)
- (* b evaluates to false (contradiction) *)
rwinv H H4.
- (* b evaluates to true *)
assert (st' = st'0) as EQ1 by auto.
subst st'0.
auto. Qed.
(** That was is a bit better, but not much. We really want Coq to
discover the relevant hypotheses for us. We can do this by using
the [match goal] facility of Ltac. *)
Ltac find_rwinv :=
match goal with
H1: ?E = true,
H2: ?E = false
|- _ => rwinv H1 H2
end.
(** The [match goal] tactic looks for two distinct hypotheses that
have the form of equalities, with the same arbitrary expression
[E] on the left and with conflicting boolean values on the right.
If such hypotheses are found, it binds [H1] and [H2] to their
names and applies the [rwinv] tactic to [H1] and [H2].
Adding this tactic to the ones that we invoke in each case of the
induction handles all of the contradictory cases. *)
Theorem ceval_deterministic''': forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2;
induction E1; intros st2 E2; inv E2; try find_rwinv; auto.
- (* E_Seq *)
assert (st' = st'0) as EQ1 by auto.
subst st'0.
auto.
- (* E_WhileLoop *)
+ (* b evaluates to true *)
assert (st' = st'0) as EQ1 by auto.
subst st'0.
auto. Qed.
(** Let's see about the remaining cases. Each of them involves
applying a conditional hypothesis to extract an equality.
Currently we have phrased these as assertions, so that we have to
predict what the resulting equality will be (although we can then
use [auto] to prove it). An alternative is to pick the relevant
hypotheses to use and then rewrite with them, as follows: *)
Theorem ceval_deterministic'''': forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2;
induction E1; intros st2 E2; inv E2; try find_rwinv; auto.
- (* E_Seq *)
rewrite (IHE1_1 st'0 H1) in *. auto.
- (* E_WhileLoop *)
+ (* b evaluates to true *)
rewrite (IHE1_1 st'0 H3) in *. auto. Qed.
(** Now we can automate the task of finding the relevant hypotheses to
rewrite with. *)
Ltac find_eqn :=
match goal with
H1: forall x, ?P x -> ?L = ?R,
H2: ?P ?X
|- _ => rewrite (H1 X H2) in *
end.
(** The pattern [forall x, ?P x -> ?L = ?R] matches any hypothesis of
the form "for all [x], _some property of [x]_ implies _some
equality_." The property of [x] is bound to the pattern variable
[P], and the left- and right-hand sides of the equality are bound
to [L] and [R]. The name of this hypothesis is bound to [H1].
Then the pattern [?P ?X] matches any hypothesis that provides
evidence that [P] holds for some concrete [X]. If both patterns
succeed, we apply the [rewrite] tactic (instantiating the
quantified [x] with [X] and providing [H2] as the required
evidence for [P X]) in all hypotheses and the goal.
One problem remains: in general, there may be several pairs of
hypotheses that have the right general form, and it seems tricky
to pick out the ones we actually need. A key trick is to realize
that we can _try them all_! Here's how this works:
- each execution of [match goal] will keep trying to find a valid
pair of hypotheses until the tactic on the RHS of the match
succeeds; if there are no such pairs, it fails;
- [rewrite] will fail given a trivial equation of the form [X = X];
- we can wrap the whole thing in a [repeat], which will keep doing
useful rewrites until only trivial ones are left. *)
Theorem ceval_deterministic''''': forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2;
induction E1; intros st2 E2; inv E2; try find_rwinv;
repeat find_eqn; auto.
Qed.
(** The big payoff in this approach is that our proof script
should be robust in the face of modest changes to our language.
For example, we can add a [REPEAT] command to the language. *)
Module Repeat.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Notation "'SKIP'" :=
CSkip.
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (t_update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
| E_RepeatEnd : forall st st' b1 c1,
ceval st c1 st' ->
beval st' b1 = true ->
ceval st (CRepeat c1 b1) st'
| E_RepeatLoop : forall st st' st'' b1 c1,
ceval st c1 st' ->
beval st' b1 = false ->
ceval st' (CRepeat c1 b1) st'' ->
ceval st (CRepeat c1 b1) st''.
Notation "c1 '/' st '\\' st'" := (ceval st c1 st')
(at level 40, st at level 39).
(** Our first attempt at the proof is disappointing: the [E_RepeatEnd]
and [E_RepeatLoop] cases are not handled by our previous
automation. *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2;
induction E1;
intros st2 E2; inv E2; try find_rwinv; repeat find_eqn; auto.
- (* E_RepeatEnd *)
+ (* b evaluates to false (contradiction) *)
find_rwinv.
(* oops: why didn't [find_rwinv] solve this for us already?
answer: we did things in the wrong order. *)
- (* E_RepeatLoop *)
+ (* b evaluates to true (contradiction) *)
find_rwinv.
Qed.
(** To fix this, we just have to swap the invocations of [find_eqn]
and [find_rwinv]. *)
Theorem ceval_deterministic': forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2;
induction E1;
intros st2 E2; inv E2; repeat find_eqn; try find_rwinv; auto.
Qed.
End Repeat.
(** These examples just give a flavor of what "hyper-automation" can
achieve in Coq. The details of [match goal] are a bit tricky, and
debugging scripts using it is, frankly, not very pleasant. But it
is well worth adding at least simple uses to your proofs, both to
avoid tedium and to "future proof" them. *)
(* ----------------------------------------------------------------- *)
(** *** [eapply] and [eauto] *)
(** To close the chapter, we'll introduce one more convenient feature
of Coq: its ability to delay instantiation of quantifiers. To
motivate this feature, recall this example from the [Imp]
chapter: *)
Example ceval_example1:
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
\\ (t_update (t_update empty_state X 2) Z 4).
Proof.
(* We supply the intermediate state [st']... *)
apply E_Seq with (t_update empty_state X 2).
- apply E_Ass. reflexivity.
- apply E_IfFalse. reflexivity. apply E_Ass. reflexivity.
Qed.
(** In the first step of the proof, we had to explicitly provide a
longish expression to help Coq instantiate a "hidden" argument to
the [E_Seq] constructor. This was needed because the definition
of [E_Seq]...
E_Seq : forall c1 c2 st st' st'',
c1 / st \\ st' ->
c2 / st' \\ st'' ->
(c1 ;; c2) / st \\ st''
is quantified over a variable, [st'], that does not appear in its
conclusion, so unifying its conclusion with the goal state doesn't
help Coq find a suitable value for this variable. If we leave
out the [with], this step fails ("Error: Unable to find an
instance for the variable [st']").
What's silly about this error is that the appropriate value for [st']
will actually become obvious in the very next step, where we apply
[E_Ass]. If Coq could just wait until we get to this step, there
would be no need to give the value explicitly. This is exactly what
the [eapply] tactic gives us:
*)
Example ceval'_example1:
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
\\ (t_update (t_update empty_state X 2) Z 4).
Proof.
eapply E_Seq. (* 1 *)
- apply E_Ass. (* 2 *)
reflexivity. (* 3 *)
- (* 4 *) apply E_IfFalse. reflexivity. apply E_Ass. reflexivity.
Qed.
(** The tactic [eapply H] tactic behaves just like [apply H] except
that, after it finishes unifying the goal state with the
conclusion of [H], it does not bother to check whether all the
variables that were introduced in the process have been given
concrete values during unification.
If you step through the proof above, you'll see that the goal
state at position [1] mentions the _existential variable_ [?st']
in both of the generated subgoals. The next step (which gets us
to position [2]) replaces [?st'] with a concrete value. This new
value contains a new existential variable [?n], which is
instantiated in its turn by the following [reflexivity] step,
position [3]. When we start working on the second
subgoal (position [4]), we observe that the occurrence of [?st']
in this subgoal has been replaced by the value that it was given
during the first subgoal. *)
(** Several of the tactics that we've seen so far, including [exists],
[constructor], and [auto], have [e...] variants. For example,
here's a proof using [eauto]: *)
Hint Constructors ceval.
Hint Transparent state.
Hint Transparent total_map.
Definition st12 := t_update (t_update empty_state X 1) Y 2.
Definition st21 := t_update (t_update empty_state X 2) Y 1.
Example auto_example_8 : exists s',
(IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI) / st21 \\ s'.
Proof. eauto. Qed.
(** The [eauto] tactic works just like [auto], except that it uses
[eapply] instead of [apply]. *)
(** $Date: 2016-10-18 15:42:43 -0400 (Tue, 18 Oct 2016) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_TB_V
`define SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_TB_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_pwrgood_pp_pg_s.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
reg VGND;
reg SLEEP;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
SLEEP = 1'bX;
UDP_IN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 SLEEP = 1'b0;
#40 UDP_IN = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 SLEEP = 1'b1;
#120 UDP_IN = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 SLEEP = 1'b0;
#200 UDP_IN = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 UDP_IN = 1'b1;
#320 SLEEP = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 UDP_IN = 1'bx;
#400 SLEEP = 1'bx;
end
sky130_fd_sc_lp__udp_pwrgood_pp$PG$S dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .SLEEP(SLEEP), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_TB_V
|
//-------------------------------------------------------------------
//-- counter_tb.v
//-- Banco de pruebas para el contador
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
module counter_tb();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Datos de salida del contador
wire [26:0] data;
//-- Registro para comprobar si el contador cuenta correctamente
reg [26:0] counter_check = 1;
//-- Instanciar el contador
counter C1(
.clk(clk),
.data(data)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk = ~clk;
//-- Comprobacion del valor del contador
//-- En cada flanco de bajada se comprueba la salida del contador
//-- y se incrementa el valor esperado
always @(negedge clk) begin
if (counter_check != data)
$display("-->ERROR!. Esperado: %d. Leido: %d",counter_check, data);
counter_check <= counter_check + 1;
end
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("counter_tb.vcd");
$dumpvars(0, counter_tb);
//-- Comprobación del reset.
# 0.5 if (data != 0)
$display("ERROR! Contador NO está a 0!");
else
$display("Contador inicializado. OK.");
# 99 $display("FIN de la simulacion");
# 100 $finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41AI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O41AI_FUNCTIONAL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o41ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
// Local signals
wire A4 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41AI_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLXTP_FUNCTIONAL_PP_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTP_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__NAND4_FUNCTIONAL_PP_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , D, C, B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4_FUNCTIONAL_PP_V
|
// MBT 7/7/16
//
// bsg_channel_tunnel
//
// This module allows you to multiplex multiple streams over a shared
// interconnect without having deadlock occur because of stream interleaving.
//
// There are three models for interleaving streams:
//
// a. Your stream is guaranteed to be sunk by the remote node without
// dependence on external factors, and does not rely upon back pressure.
// In this case you avoid deadlock but may have fairness issues. Here, you
// attach directly to the shared interconnect (e.g. bsg_fsb).
//
// b. Your streams rely upon back pressure from the remote node. Here, you
// can use multiple bsg_channel_tunnel modules, one for each stream.
// This ensures that you do not deadlock, but it does not address unfairness
// in the interconnect that may lead to starvation.
//
// c. Your stream rely upon back pressure from the remote node. In this
// scenario, you use one bsg_channel_tunnel across multiple streams.
// Within this group of streams, you will have round-robin fairness.
//
// Channel tunneling is like virtual channels except that it includes
// credits as part of the channels, and it does not
// require the virtual channels to demultiplex at every step.
//
// Finally, especially when crossing chip boundaries (and using case c),
// we can aggregrate the FIFO space into a single
// large FIFO which is more efficient per bit than many smaller FIFOs.
//
// 1. remote_credits_p typical set to 2X bandwidth delay product of link
//
// ASIC<->ASIC
//
// e.g. if the core frequency is 1000 MHz, and the off-chip frequency
// is 300 MHz, and the off-chip link is 0.4 word/cycle, and the 1-way latency
// in the core domain is 5 cycles, and the latency in the off-chip
// domain is 10 cycles, then:
//
// one-way chip latency = 5 * 1 ns + 10 * 3.3 ns = 38.3 ns
// bandwidth = 0.4 words / 3.33 ns = .133 words / ns
// bandwidth * delay = .133 * 35 = 4.6 words
//
// * 2 ASICS = 9.2 words
// * 2 (roundtrip) = 18.4 words
//
// ASIC<->FPGA
//
// note, if there is an FPGA in the loop, then latencies blow up.
// suppose the FPGA runs at 300*.4 = 120 Mhz=8.3ns, and so the on-FPGA latency
// is 38.3 * (8.3) = 314 ns. then one way latency is 352 ns, and buffering is
// (.133 * (352))*2 = 93 words.
//
// 2. area grows as num_in_p * remote_credits_p
//
//
// 3. area for all channels can be stored in a single place when using alternate
// implementations of virtual fifos
//
`include "bsg_defines.v"
module bsg_channel_tunnel #(parameter width_p = 1
, parameter `BSG_INV_PARAM(num_in_p)
, parameter `BSG_INV_PARAM(remote_credits_p)
, use_pseudo_large_fifo_p = 0
, harden_small_fifo_p = 0
, lg_remote_credits_lp = $clog2(remote_credits_p+1)
, lg_credit_decimation_p = `BSG_MIN(lg_remote_credits_lp,4)
, tag_width_lp = $clog2(num_in_p+1)
, tagged_width_lp = tag_width_lp + width_p
)
(input clk_i
,input reset_i
// incoming multiplexed data
,input [tagged_width_lp-1:0] multi_data_i
,input multi_v_i
,output multi_yumi_o
// outgoing multiplexed data
, output [tagged_width_lp-1:0] multi_data_o
, output multi_v_o
, input multi_yumi_i
// incoming demultiplexed data
, input [num_in_p-1:0][width_p-1:0] data_i
, input [num_in_p-1:0] v_i
, output [num_in_p-1:0] yumi_o
// outgoing demultiplexed data
, output [num_in_p-1:0][width_p-1:0] data_o
, output [num_in_p-1:0] v_o
, input [num_in_p-1:0] yumi_i
);
// synopsys translate_off
initial
assert(lg_credit_decimation_p <= lg_remote_credits_lp)
else
begin
$error("%m bad params; insufficient remote credits 2^%d to allow for decimation factor 2^%d"
,lg_remote_credits_lp,lg_credit_decimation_p);
$finish;
end
initial
assert(width_p >= num_in_p*lg_remote_credits_lp)
else
begin
$error("%m bad params; channel width (%d) must be at least wide enough to route back credits (%d)"
,width_p
,num_in_p*lg_remote_credits_lp);
$finish;
end
// synopsys translate_on
wire [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_local_return_data_oi;
wire credit_local_return_v_oi;
wire [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_remote_return_data_oi;
wire credit_remote_return_yumi_io;
bsg_channel_tunnel_out #(.width_p (width_p)
,.num_in_p (num_in_p)
,.remote_credits_p (remote_credits_p)
,.lg_credit_decimation_p(lg_credit_decimation_p)
) bcto
(.clk_i
,.reset_i
,.data_i
,.v_i
,.yumi_o
,.data_o (multi_data_o )
,.v_o(multi_v_o)
,.yumi_i (multi_yumi_i )
,.credit_local_return_data_i (credit_local_return_data_oi )
,.credit_local_return_v_i (credit_local_return_v_oi )
,.credit_remote_return_data_i(credit_remote_return_data_oi)
,.credit_remote_return_yumi_o(credit_remote_return_yumi_io)
);
bsg_channel_tunnel_in #(.width_p (width_p )
,.num_in_p (num_in_p )
,.remote_credits_p (remote_credits_p)
,.use_pseudo_large_fifo_p(use_pseudo_large_fifo_p)
,.harden_small_fifo_p (harden_small_fifo_p)
,.lg_credit_decimation_p(lg_credit_decimation_p)
) bcti
(.clk_i
,.reset_i
,.data_i (multi_data_i )
,.v_i (multi_v_i)
,.yumi_o (multi_yumi_o )
,.data_o
,.v_o
,.yumi_i
,.credit_local_return_data_o (credit_local_return_data_oi )
,.credit_local_return_v_o (credit_local_return_v_oi )
,.credit_remote_return_data_o(credit_remote_return_data_oi)
,.credit_remote_return_yumi_i(credit_remote_return_yumi_io)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_channel_tunnel)
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:58:40 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36,
n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50,
n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64,
n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78,
n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92,
n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127,
n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149,
n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160,
n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182,
n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193,
n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204,
n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215,
n216, n217, n218, n219, n220, n221, n222, n223, n224, n225, n226,
n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237,
n238, n239, n240, n241, n242, n243, n244, n246, n247, n248, n249,
n250, n251, n252, n253, n254, n255, n256, n257, n258, n259, n260,
n261, n262, n263, n264, n265, n266, n267, n268, n269, n270, n271,
n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282,
n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n369, n370;
OAI2BB1X2TS U43 ( .A0N(n264), .A1N(n274), .B0(n19), .Y(res[32]) );
XOR2X2TS U44 ( .A(n204), .B(n203), .Y(res[26]) );
XOR2X2TS U45 ( .A(n239), .B(n238), .Y(res[27]) );
XOR2X2TS U46 ( .A(n244), .B(n243), .Y(res[25]) );
XOR2X2TS U47 ( .A(n248), .B(n247), .Y(res[28]) );
NAND2X1TS U48 ( .A(n237), .B(n89), .Y(n238) );
NAND2X1TS U49 ( .A(n242), .B(n241), .Y(n243) );
NAND2X1TS U50 ( .A(n246), .B(n257), .Y(n247) );
NAND2X1TS U51 ( .A(n228), .B(n256), .Y(n229) );
NAND2X1TS U52 ( .A(n272), .B(n271), .Y(n273) );
NAND2XLTS U53 ( .A(n83), .B(n294), .Y(n295) );
NAND2XLTS U54 ( .A(n86), .B(n291), .Y(n292) );
NAND2XLTS U55 ( .A(n311), .B(n310), .Y(n313) );
NAND2XLTS U56 ( .A(n87), .B(n275), .Y(n276) );
NAND2X1TS U57 ( .A(n285), .B(n284), .Y(n286) );
NAND2X1TS U58 ( .A(n306), .B(n305), .Y(n307) );
NAND2XLTS U59 ( .A(n326), .B(n325), .Y(n327) );
NAND2XLTS U60 ( .A(n301), .B(n300), .Y(n302) );
NAND2X4TS U61 ( .A(n274), .B(n22), .Y(n77) );
OA21XLTS U62 ( .A0(n267), .A1(n271), .B0(n268), .Y(n19) );
OAI21X1TS U63 ( .A0(n308), .A1(n304), .B0(n305), .Y(n303) );
INVX6TS U64 ( .A(n45), .Y(n287) );
NOR2X1TS U65 ( .A(n231), .B(n233), .Y(n236) );
INVX2TS U66 ( .A(n289), .Y(n296) );
CLKBUFX2TS U67 ( .A(n297), .Y(n298) );
OR2X2TS U68 ( .A(n270), .B(n266), .Y(n79) );
NOR2X2TS U69 ( .A(n262), .B(in1[30]), .Y(n265) );
NAND2X2TS U70 ( .A(n263), .B(in1[31]), .Y(n268) );
NAND2X1TS U71 ( .A(n227), .B(in1[29]), .Y(n256) );
CLKMX2X2TS U72 ( .A(in2[30]), .B(n253), .S0(n252), .Y(n262) );
NAND2X2TS U73 ( .A(n219), .B(in1[28]), .Y(n257) );
NAND2X2TS U74 ( .A(n180), .B(in1[22]), .Y(n284) );
NAND2X1TS U75 ( .A(n181), .B(in1[23]), .Y(n280) );
OR2X2TS U76 ( .A(n168), .B(in1[20]), .Y(n83) );
NOR2X2TS U77 ( .A(n299), .B(n304), .Y(n160) );
NAND2X2TS U78 ( .A(n193), .B(in1[24]), .Y(n275) );
CLKMX2X4TS U79 ( .A(in2[29]), .B(n226), .S0(n225), .Y(n227) );
INVX2TS U80 ( .A(n291), .Y(n170) );
OR2X4TS U81 ( .A(n214), .B(in1[27]), .Y(n89) );
NAND2X2TS U82 ( .A(n157), .B(in1[18]), .Y(n305) );
NAND2X2TS U83 ( .A(n158), .B(in1[19]), .Y(n300) );
NOR2X2TS U84 ( .A(n251), .B(in2[30]), .Y(n249) );
CLKMX2X3TS U85 ( .A(in2[23]), .B(n175), .S0(n225), .Y(n181) );
OR2X2TS U86 ( .A(n142), .B(in1[16]), .Y(n82) );
NAND2X2TS U87 ( .A(n169), .B(in1[21]), .Y(n291) );
NOR2X1TS U88 ( .A(n224), .B(n223), .Y(n211) );
MX2X2TS U89 ( .A(in2[25]), .B(n189), .S0(add_sub), .Y(n194) );
MXI2X2TS U90 ( .A(n167), .B(n166), .S0(n225), .Y(n168) );
XOR2X1TS U91 ( .A(n174), .B(n173), .Y(n175) );
OR2X1TS U92 ( .A(n210), .B(in2[27]), .Y(n223) );
INVX4TS U93 ( .A(add_sub), .Y(n353) );
NOR3X2TS U94 ( .A(n176), .B(in2[22]), .C(n184), .Y(n174) );
INVX2TS U95 ( .A(n187), .Y(n153) );
NAND2X1TS U96 ( .A(n206), .B(n205), .Y(n210) );
INVX4TS U97 ( .A(n63), .Y(n61) );
INVX2TS U98 ( .A(in2[20]), .Y(n167) );
NOR2X2TS U99 ( .A(n176), .B(in2[20]), .Y(n163) );
CLKINVX2TS U100 ( .A(n128), .Y(n67) );
INVX2TS U101 ( .A(in2[26]), .Y(n205) );
NAND2X2TS U102 ( .A(n131), .B(in1[14]), .Y(n321) );
NAND2X4TS U103 ( .A(n127), .B(in1[12]), .Y(n330) );
NAND2X2TS U104 ( .A(n18), .B(in1[13]), .Y(n325) );
OR2X2TS U105 ( .A(in2[21]), .B(in2[20]), .Y(n184) );
NOR2X4TS U106 ( .A(in2[17]), .B(in2[16]), .Y(n162) );
XNOR2X2TS U107 ( .A(n112), .B(in2[11]), .Y(n113) );
NOR2X1TS U108 ( .A(in2[19]), .B(in2[18]), .Y(n161) );
OR2X6TS U109 ( .A(n104), .B(in1[8]), .Y(n84) );
CLKINVX6TS U110 ( .A(n346), .Y(n105) );
BUFX4TS U111 ( .A(add_sub), .Y(n252) );
NOR2X2TS U112 ( .A(in2[13]), .B(in2[12]), .Y(n133) );
XNOR2X2TS U113 ( .A(n111), .B(in2[10]), .Y(n93) );
OR2X4TS U114 ( .A(n115), .B(n116), .Y(n111) );
NAND2X6TS U115 ( .A(n52), .B(n350), .Y(n101) );
INVX4TS U116 ( .A(n54), .Y(n97) );
BUFX8TS U117 ( .A(add_sub), .Y(n225) );
INVX8TS U118 ( .A(add_sub), .Y(n94) );
INVX12TS U119 ( .A(in2[3]), .Y(n90) );
CLKINVX6TS U120 ( .A(in2[8]), .Y(n103) );
AND2X2TS U121 ( .A(n118), .B(n117), .Y(n119) );
NAND2X2TS U122 ( .A(in2[6]), .B(add_sub), .Y(n96) );
NOR2X1TS U123 ( .A(n176), .B(n184), .Y(n177) );
AOI21X2TS U124 ( .A0(n89), .A1(n216), .B0(n215), .Y(n217) );
NOR2X4TS U125 ( .A(n219), .B(in1[28]), .Y(n254) );
NOR2XLTS U126 ( .A(n11), .B(in2[2]), .Y(n364) );
OR2X2TS U127 ( .A(n193), .B(in1[24]), .Y(n87) );
OAI21X2TS U128 ( .A0(n220), .A1(n254), .B0(n257), .Y(n221) );
OA21XLTS U129 ( .A0(n336), .A1(n333), .B0(n334), .Y(n20) );
INVX2TS U130 ( .A(n298), .Y(n308) );
NAND2X1TS U131 ( .A(n209), .B(n232), .Y(n203) );
AND2X4TS U132 ( .A(n261), .B(n255), .Y(n9) );
AND2X2TS U133 ( .A(n94), .B(n95), .Y(n10) );
NAND2X2TS U134 ( .A(n92), .B(n352), .Y(n11) );
INVX2TS U135 ( .A(n275), .Y(n240) );
NOR2X4TS U136 ( .A(n227), .B(in1[29]), .Y(n258) );
NOR2X4TS U137 ( .A(n16), .B(n27), .Y(n29) );
INVX2TS U138 ( .A(n260), .Y(n220) );
NOR2X6TS U139 ( .A(n218), .B(n231), .Y(n255) );
INVX3TS U140 ( .A(n267), .Y(n269) );
INVX4TS U141 ( .A(n182), .Y(n46) );
INVX2TS U142 ( .A(n232), .Y(n216) );
NOR2X4TS U143 ( .A(n202), .B(in1[26]), .Y(n233) );
INVX2TS U144 ( .A(n254), .Y(n246) );
NOR2X4TS U145 ( .A(n258), .B(n254), .Y(n261) );
XNOR2X2TS U146 ( .A(n200), .B(in2[26]), .Y(n201) );
XOR2X2TS U147 ( .A(n177), .B(in2[22]), .Y(n178) );
MXI2X4TS U148 ( .A(n192), .B(n191), .S0(n225), .Y(n193) );
NAND2BX2TS U149 ( .AN(n153), .B(n162), .Y(n154) );
NAND2X4TS U150 ( .A(n269), .B(n268), .Y(n270) );
NAND2X4TS U151 ( .A(n209), .B(n89), .Y(n218) );
INVX2TS U152 ( .A(n183), .Y(n42) );
NOR2X4TS U153 ( .A(n196), .B(n195), .Y(n234) );
INVX4TS U154 ( .A(n233), .Y(n209) );
INVX2TS U155 ( .A(n36), .Y(n69) );
OAI21X2TS U156 ( .A0(n258), .A1(n257), .B0(n256), .Y(n259) );
INVX2TS U157 ( .A(n299), .Y(n301) );
INVX4TS U158 ( .A(n190), .Y(n242) );
INVX2TS U159 ( .A(n237), .Y(n215) );
MXI2X4TS U160 ( .A(n205), .B(n201), .S0(n252), .Y(n202) );
NAND2X4TS U161 ( .A(n147), .B(in1[17]), .Y(n310) );
INVX4TS U162 ( .A(n294), .Y(n290) );
MXI2X4TS U163 ( .A(n179), .B(n178), .S0(n252), .Y(n180) );
MX2X4TS U164 ( .A(in2[28]), .B(n212), .S0(n225), .Y(n219) );
NAND2X2TS U165 ( .A(n199), .B(n206), .Y(n200) );
NAND2X2TS U166 ( .A(n142), .B(in1[16]), .Y(n314) );
NOR2X4TS U167 ( .A(n149), .B(n153), .Y(n151) );
OR2X4TS U168 ( .A(n110), .B(in1[10]), .Y(n85) );
INVX6TS U169 ( .A(in2[10]), .Y(n117) );
INVX2TS U170 ( .A(in2[17]), .Y(n144) );
XNOR2X1TS U171 ( .A(n303), .B(n302), .Y(res[19]) );
NAND2X6TS U172 ( .A(n43), .B(n41), .Y(n47) );
XOR2X1TS U173 ( .A(n308), .B(n307), .Y(res[18]) );
NAND2X4TS U174 ( .A(n182), .B(n9), .Y(n71) );
OR2X4TS U175 ( .A(n213), .B(n254), .Y(n222) );
NOR2X4TS U176 ( .A(n16), .B(n79), .Y(n72) );
AND2X2TS U177 ( .A(n63), .B(n25), .Y(n24) );
AND2X2TS U178 ( .A(n270), .B(n272), .Y(n22) );
NOR2X1TS U179 ( .A(n267), .B(n265), .Y(n264) );
XOR2X1TS U180 ( .A(n20), .B(n332), .Y(res[12]) );
INVX2TS U181 ( .A(n231), .Y(n198) );
AND2X2TS U182 ( .A(n281), .B(n280), .Y(n23) );
XOR2X1TS U183 ( .A(n337), .B(n336), .Y(res[11]) );
NOR2X6TS U184 ( .A(n263), .B(in1[31]), .Y(n267) );
CLKAND2X2TS U185 ( .A(n271), .B(n265), .Y(n76) );
XNOR2X2TS U186 ( .A(n249), .B(in2[31]), .Y(n250) );
NOR2X4TS U187 ( .A(n194), .B(in1[25]), .Y(n190) );
NAND2X4TS U188 ( .A(n340), .B(n85), .Y(n37) );
MX2X2TS U189 ( .A(in2[27]), .B(n208), .S0(add_sub), .Y(n214) );
XOR2X1TS U190 ( .A(n345), .B(n13), .Y(res[9]) );
XNOR2X1TS U191 ( .A(n81), .B(in2[29]), .Y(n226) );
NAND2X4TS U192 ( .A(n320), .B(n321), .Y(n63) );
INVX4TS U193 ( .A(n333), .Y(n335) );
NAND2X4TS U194 ( .A(n114), .B(in1[11]), .Y(n334) );
NAND2X4TS U195 ( .A(n104), .B(in1[8]), .Y(n346) );
OAI21XLTS U196 ( .A0(n358), .A1(n353), .B0(n357), .Y(res[6]) );
OAI21XLTS U197 ( .A0(n366), .A1(n353), .B0(n365), .Y(res[3]) );
NAND3X6TS U198 ( .A(n35), .B(n32), .C(n30), .Y(n350) );
OAI21XLTS U199 ( .A0(n361), .A1(n353), .B0(n360), .Y(res[5]) );
OAI21XLTS U200 ( .A0(n363), .A1(n353), .B0(n362), .Y(res[2]) );
OAI21XLTS U201 ( .A0(n370), .A1(n353), .B0(n369), .Y(res[4]) );
OAI21XLTS U202 ( .A0(n355), .A1(n353), .B0(n354), .Y(res[1]) );
OR2X2TS U203 ( .A(in2[18]), .B(n148), .Y(n149) );
CLKINVX6TS U204 ( .A(n11), .Y(n12) );
OR2X1TS U205 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
OAI21X4TS U206 ( .A0(n279), .A1(n284), .B0(n280), .Y(n182) );
NOR2X4TS U207 ( .A(n181), .B(in1[23]), .Y(n279) );
NAND3X4TS U208 ( .A(n78), .B(n77), .C(n74), .Y(res[31]) );
MX2X6TS U209 ( .A(in2[13]), .B(n124), .S0(n225), .Y(n18) );
NOR2X4TS U210 ( .A(n61), .B(n60), .Y(n62) );
NAND4X4TS U211 ( .A(n352), .B(n92), .C(n91), .D(n90), .Y(n48) );
XNOR2X2TS U212 ( .A(n154), .B(in2[18]), .Y(n155) );
INVX12TS U213 ( .A(in2[7]), .Y(n49) );
XNOR2X4TS U214 ( .A(n115), .B(in2[8]), .Y(n102) );
AOI21X1TS U215 ( .A0(n347), .A1(n84), .B0(n105), .Y(n13) );
XOR2X2TS U216 ( .A(n134), .B(in2[12]), .Y(n125) );
NOR2X4TS U217 ( .A(n147), .B(in1[17]), .Y(n309) );
MX2X4TS U218 ( .A(in2[17]), .B(n146), .S0(n225), .Y(n147) );
AND4X8TS U219 ( .A(n90), .B(n95), .C(n91), .D(n92), .Y(n14) );
INVX12TS U220 ( .A(in2[6]), .Y(n95) );
INVX12TS U221 ( .A(n277), .Y(n40) );
NAND2X8TS U222 ( .A(n187), .B(n186), .Y(n224) );
NOR4X2TS U223 ( .A(n185), .B(n184), .C(in2[23]), .D(in2[22]), .Y(n186) );
AND2X4TS U224 ( .A(n183), .B(n9), .Y(n80) );
XOR2X1TS U225 ( .A(n176), .B(n167), .Y(n166) );
NOR2X4TS U226 ( .A(n10), .B(n59), .Y(n58) );
NAND2BX4TS U227 ( .AN(in2[29]), .B(n81), .Y(n251) );
NOR3X4TS U228 ( .A(n224), .B(in2[28]), .C(n223), .Y(n81) );
NOR2X2TS U229 ( .A(n99), .B(in2[7]), .Y(n31) );
NAND2X4TS U230 ( .A(n90), .B(n91), .Y(n99) );
XOR2X1TS U231 ( .A(n293), .B(n292), .Y(res[21]) );
AOI21X4TS U232 ( .A0(n296), .A1(n83), .B0(n290), .Y(n293) );
NAND2X4TS U233 ( .A(n168), .B(in1[20]), .Y(n294) );
NAND2BX4TS U234 ( .AN(n185), .B(n187), .Y(n176) );
NOR2X4TS U235 ( .A(in2[25]), .B(in2[24]), .Y(n206) );
OAI21X4TS U236 ( .A0(n234), .A1(n218), .B0(n217), .Y(n260) );
XOR2X2TS U237 ( .A(n163), .B(in2[21]), .Y(n165) );
MXI2X4TS U238 ( .A(n165), .B(n164), .S0(n353), .Y(n169) );
NAND2X4TS U239 ( .A(n86), .B(n83), .Y(n172) );
MX2X4TS U240 ( .A(in2[19]), .B(n152), .S0(add_sub), .Y(n158) );
NAND2X8TS U241 ( .A(n134), .B(n133), .Y(n139) );
NAND2X8TS U242 ( .A(n103), .B(n108), .Y(n116) );
NOR2X4TS U243 ( .A(n224), .B(n210), .Y(n207) );
XNOR2X4TS U244 ( .A(n188), .B(in2[25]), .Y(n189) );
NOR2X4TS U245 ( .A(n224), .B(in2[24]), .Y(n188) );
MXI2X4TS U246 ( .A(n103), .B(n102), .S0(n225), .Y(n104) );
NOR2X6TS U247 ( .A(n70), .B(n334), .Y(n68) );
NAND2X4TS U248 ( .A(n134), .B(n126), .Y(n123) );
INVX2TS U249 ( .A(in2[16]), .Y(n141) );
INVX2TS U250 ( .A(in2[18]), .Y(n156) );
INVX2TS U251 ( .A(in1[7]), .Y(n53) );
NAND2X2TS U252 ( .A(n109), .B(in1[9]), .Y(n342) );
NAND2X4TS U253 ( .A(n110), .B(in1[10]), .Y(n338) );
NOR2X2TS U254 ( .A(n131), .B(in1[14]), .Y(n320) );
NOR2X4TS U255 ( .A(n180), .B(in1[22]), .Y(n283) );
INVX4TS U256 ( .A(n71), .Y(n27) );
INVX2TS U257 ( .A(n116), .Y(n120) );
INVX2TS U258 ( .A(in2[11]), .Y(n118) );
INVX2TS U259 ( .A(n96), .Y(n57) );
OAI21X2TS U260 ( .A0(n96), .A1(n17), .B0(in1[6]), .Y(n59) );
INVX6TS U261 ( .A(in2[9]), .Y(n108) );
INVX2TS U262 ( .A(in2[12]), .Y(n126) );
INVX12TS U263 ( .A(in2[5]), .Y(n51) );
INVX8TS U264 ( .A(in2[4]), .Y(n50) );
CLKAND2X2TS U265 ( .A(n49), .B(add_sub), .Y(n15) );
NAND2X1TS U266 ( .A(n34), .B(in2[7]), .Y(n33) );
INVX2TS U267 ( .A(n99), .Y(n34) );
CLKINVX6TS U268 ( .A(n68), .Y(n28) );
INVX2TS U269 ( .A(n88), .Y(n60) );
XOR2X1TS U270 ( .A(n151), .B(n150), .Y(n152) );
INVX2TS U271 ( .A(in2[19]), .Y(n150) );
INVX2TS U272 ( .A(in2[21]), .Y(n164) );
INVX2TS U273 ( .A(n224), .Y(n199) );
INVX2TS U274 ( .A(n241), .Y(n195) );
NOR2X2TS U275 ( .A(n275), .B(n190), .Y(n196) );
INVX2TS U276 ( .A(n171), .Y(n44) );
INVX2TS U277 ( .A(n255), .Y(n213) );
NOR2X4TS U278 ( .A(n279), .B(n283), .Y(n183) );
INVX2TS U279 ( .A(n314), .Y(n143) );
NOR2X4TS U280 ( .A(n158), .B(in1[19]), .Y(n299) );
OR2X4TS U281 ( .A(n169), .B(in1[21]), .Y(n86) );
CLKBUFX2TS U282 ( .A(n288), .Y(n289) );
NAND2X2TS U283 ( .A(n194), .B(in1[25]), .Y(n241) );
NAND2X4TS U284 ( .A(n202), .B(in1[26]), .Y(n232) );
INVX2TS U285 ( .A(n234), .Y(n197) );
NAND2X2TS U286 ( .A(n214), .B(in1[27]), .Y(n237) );
NAND2X2TS U287 ( .A(n242), .B(n87), .Y(n231) );
OAI21X1TS U288 ( .A0(n234), .A1(n233), .B0(n232), .Y(n235) );
NAND2X1TS U289 ( .A(n270), .B(n271), .Y(n75) );
NOR2XLTS U290 ( .A(n48), .B(in2[4]), .Y(n359) );
NAND2X1TS U291 ( .A(n349), .B(n52), .Y(n351) );
NAND2X1TS U292 ( .A(n84), .B(n346), .Y(n348) );
NAND2X1TS U293 ( .A(n343), .B(n342), .Y(n345) );
INVX2TS U294 ( .A(n341), .Y(n343) );
NAND2X1TS U295 ( .A(n85), .B(n338), .Y(n339) );
NAND2X1TS U296 ( .A(n335), .B(n334), .Y(n337) );
NAND2X1TS U297 ( .A(n331), .B(n330), .Y(n332) );
INVX2TS U298 ( .A(n329), .Y(n331) );
OAI21XLTS U299 ( .A0(n20), .A1(n329), .B0(n330), .Y(n328) );
INVX2TS U300 ( .A(n324), .Y(n326) );
NAND2X1TS U301 ( .A(n322), .B(n321), .Y(n323) );
INVX2TS U302 ( .A(n320), .Y(n322) );
NAND2X1TS U303 ( .A(n88), .B(n317), .Y(n318) );
CLKBUFX2TS U304 ( .A(n64), .Y(n25) );
NAND2X1TS U305 ( .A(n82), .B(n314), .Y(n315) );
XOR2XLTS U306 ( .A(n313), .B(n312), .Y(res[17]) );
INVX2TS U307 ( .A(n309), .Y(n311) );
XNOR2X1TS U308 ( .A(n296), .B(n295), .Y(res[20]) );
XOR2X1TS U309 ( .A(n287), .B(n286), .Y(res[22]) );
INVX2TS U310 ( .A(n283), .Y(n285) );
XOR2X2TS U311 ( .A(n282), .B(n23), .Y(res[23]) );
INVX2TS U312 ( .A(n279), .Y(n281) );
INVX2TS U313 ( .A(n258), .Y(n228) );
OAI21X1TS U314 ( .A0(n270), .A1(n76), .B0(n75), .Y(n74) );
NAND3X2TS U315 ( .A(n73), .B(n72), .C(n71), .Y(n78) );
NAND2X4TS U316 ( .A(n100), .B(n367), .Y(n55) );
NAND3X6TS U317 ( .A(n335), .B(n38), .C(n129), .Y(n36) );
CLKINVX12TS U318 ( .A(n26), .Y(n134) );
XNOR2X2TS U319 ( .A(n139), .B(in2[14]), .Y(n130) );
BUFX8TS U320 ( .A(n278), .Y(n45) );
NOR2X4TS U321 ( .A(in2[8]), .B(n115), .Y(n106) );
INVX8TS U322 ( .A(n115), .Y(n122) );
XNOR2X1TS U323 ( .A(n277), .B(n276), .Y(res[24]) );
NOR2X4TS U324 ( .A(n109), .B(in1[9]), .Y(n341) );
INVX16TS U325 ( .A(in2[0]), .Y(n352) );
NAND2X4TS U326 ( .A(n262), .B(in1[30]), .Y(n271) );
NOR2X4TS U327 ( .A(n157), .B(in1[18]), .Y(n304) );
AO21X4TS U328 ( .A0(n260), .A1(n261), .B0(n259), .Y(n16) );
AND2X8TS U329 ( .A(n50), .B(n51), .Y(n17) );
INVX2TS U330 ( .A(n271), .Y(n266) );
AND4X8TS U331 ( .A(n50), .B(n352), .C(n51), .D(n49), .Y(n21) );
INVX2TS U332 ( .A(n265), .Y(n272) );
INVX2TS U333 ( .A(n38), .Y(n336) );
CLKINVX6TS U334 ( .A(n48), .Y(n367) );
NOR2X4TS U335 ( .A(n114), .B(in1[11]), .Y(n333) );
XOR2X2TS U336 ( .A(n187), .B(in2[16]), .Y(n140) );
NAND2X8TS U337 ( .A(n14), .B(n21), .Y(n115) );
INVX8TS U338 ( .A(n129), .Y(n70) );
NAND2X8TS U339 ( .A(n122), .B(n121), .Y(n26) );
NAND3X8TS U340 ( .A(n55), .B(n58), .C(n56), .Y(n54) );
NOR2X8TS U341 ( .A(n39), .B(n221), .Y(n230) );
AND2X8TS U342 ( .A(n36), .B(n28), .Y(n65) );
AOI21X4TS U343 ( .A0(n347), .A1(n84), .B0(n105), .Y(n344) );
NAND2X8TS U344 ( .A(n101), .B(n349), .Y(n347) );
NAND2X8TS U345 ( .A(n73), .B(n29), .Y(n274) );
NAND2X8TS U346 ( .A(n45), .B(n80), .Y(n73) );
OAI2BB1X4TS U347 ( .A0N(n31), .A1N(n12), .B0(n98), .Y(n30) );
NAND3BX4TS U348 ( .AN(n33), .B(n12), .C(n100), .Y(n32) );
NAND2BX4TS U349 ( .AN(n100), .B(n15), .Y(n35) );
NAND2X8TS U350 ( .A(n64), .B(n62), .Y(n138) );
NAND2X8TS U351 ( .A(n65), .B(n66), .Y(n64) );
NAND2X8TS U352 ( .A(n37), .B(n338), .Y(n38) );
OAI21X4TS U353 ( .A0(n344), .A1(n341), .B0(n342), .Y(n340) );
NOR2X8TS U354 ( .A(n40), .B(n222), .Y(n39) );
AOI21X4TS U355 ( .A0(n171), .A1(n172), .B0(n42), .Y(n41) );
NAND2BX4TS U356 ( .AN(n44), .B(n288), .Y(n43) );
OAI21X2TS U357 ( .A0(n288), .A1(n172), .B0(n171), .Y(n278) );
NAND2X8TS U358 ( .A(n47), .B(n46), .Y(n277) );
XOR2X4TS U359 ( .A(n123), .B(in2[13]), .Y(n124) );
MXI2X8TS U360 ( .A(n126), .B(n125), .S0(n225), .Y(n127) );
MXI2X4TS U361 ( .A(n132), .B(n130), .S0(n252), .Y(n131) );
NAND2X8TS U362 ( .A(n54), .B(n53), .Y(n52) );
NAND2BX4TS U363 ( .AN(n367), .B(n57), .Y(n56) );
NOR3XLTS U364 ( .A(n68), .B(n69), .C(n128), .Y(n319) );
AND2X8TS U365 ( .A(n67), .B(n321), .Y(n66) );
INVX16TS U366 ( .A(in2[1]), .Y(n92) );
INVX16TS U367 ( .A(in2[2]), .Y(n91) );
XNOR2X1TS U368 ( .A(n315), .B(n316), .Y(res[16]) );
XNOR2X1TS U369 ( .A(n348), .B(n347), .Y(res[8]) );
XNOR2X1TS U370 ( .A(n340), .B(n339), .Y(res[10]) );
XNOR2X2TS U371 ( .A(n274), .B(n273), .Y(res[30]) );
OR2X8TS U372 ( .A(n137), .B(in1[15]), .Y(n88) );
MX2X4TS U373 ( .A(in2[11]), .B(n113), .S0(n252), .Y(n114) );
MXI2X4TS U374 ( .A(n117), .B(n93), .S0(n252), .Y(n110) );
AND2X4TS U375 ( .A(n17), .B(n95), .Y(n100) );
NAND2X8TS U376 ( .A(n97), .B(in1[7]), .Y(n349) );
XOR2X1TS U377 ( .A(add_sub), .B(in2[7]), .Y(n98) );
XNOR2X4TS U378 ( .A(n106), .B(n108), .Y(n107) );
MXI2X4TS U379 ( .A(n108), .B(n107), .S0(n225), .Y(n109) );
NOR2X4TS U380 ( .A(n111), .B(in2[10]), .Y(n112) );
AND2X8TS U381 ( .A(n120), .B(n119), .Y(n121) );
NOR2X8TS U382 ( .A(n18), .B(in1[13]), .Y(n324) );
NOR2X8TS U383 ( .A(n127), .B(in1[12]), .Y(n329) );
NOR2X8TS U384 ( .A(n324), .B(n329), .Y(n129) );
OAI21X4TS U385 ( .A0(n324), .A1(n330), .B0(n325), .Y(n128) );
INVX2TS U386 ( .A(in2[14]), .Y(n132) );
NAND3X1TS U387 ( .A(n134), .B(n133), .C(n132), .Y(n135) );
XOR2X1TS U388 ( .A(n135), .B(in2[15]), .Y(n136) );
MX2X4TS U389 ( .A(in2[15]), .B(n136), .S0(n252), .Y(n137) );
NAND2X6TS U390 ( .A(n137), .B(in1[15]), .Y(n317) );
NAND2X8TS U391 ( .A(n138), .B(n317), .Y(n316) );
NOR3X8TS U392 ( .A(n139), .B(in2[15]), .C(in2[14]), .Y(n187) );
MXI2X2TS U393 ( .A(n141), .B(n140), .S0(n252), .Y(n142) );
AOI21X4TS U394 ( .A0(n316), .A1(n82), .B0(n143), .Y(n312) );
NOR2X2TS U395 ( .A(n153), .B(in2[16]), .Y(n145) );
XOR2X1TS U396 ( .A(n145), .B(n144), .Y(n146) );
OAI21X4TS U397 ( .A0(n312), .A1(n309), .B0(n310), .Y(n297) );
INVX2TS U398 ( .A(n162), .Y(n148) );
MXI2X4TS U399 ( .A(n156), .B(n155), .S0(n252), .Y(n157) );
OAI21X4TS U400 ( .A0(n299), .A1(n305), .B0(n300), .Y(n159) );
AOI21X4TS U401 ( .A0(n297), .A1(n160), .B0(n159), .Y(n288) );
NAND2X2TS U402 ( .A(n162), .B(n161), .Y(n185) );
AOI21X4TS U403 ( .A0(n86), .A1(n290), .B0(n170), .Y(n171) );
INVX2TS U404 ( .A(in2[23]), .Y(n173) );
INVX2TS U405 ( .A(in2[22]), .Y(n179) );
INVX2TS U406 ( .A(in2[24]), .Y(n192) );
XNOR2X4TS U407 ( .A(n224), .B(in2[24]), .Y(n191) );
AOI21X4TS U408 ( .A0(n277), .A1(n198), .B0(n197), .Y(n204) );
XNOR2X1TS U409 ( .A(n207), .B(in2[27]), .Y(n208) );
XNOR2X1TS U410 ( .A(n211), .B(in2[28]), .Y(n212) );
XOR2X4TS U411 ( .A(n230), .B(n229), .Y(res[29]) );
AOI21X4TS U412 ( .A0(n277), .A1(n236), .B0(n235), .Y(n239) );
AOI21X4TS U413 ( .A0(n277), .A1(n87), .B0(n240), .Y(n244) );
AOI21X4TS U414 ( .A0(n277), .A1(n255), .B0(n260), .Y(n248) );
MX2X4TS U415 ( .A(in2[31]), .B(n250), .S0(n252), .Y(n263) );
XOR2X1TS U416 ( .A(n251), .B(in2[30]), .Y(n253) );
OAI21X4TS U417 ( .A0(n287), .A1(n283), .B0(n284), .Y(n282) );
INVX2TS U418 ( .A(n304), .Y(n306) );
XNOR2X1TS U419 ( .A(n24), .B(n318), .Y(res[15]) );
XOR2XLTS U420 ( .A(n319), .B(n323), .Y(res[14]) );
XNOR2X1TS U421 ( .A(n328), .B(n327), .Y(res[13]) );
XNOR2X1TS U422 ( .A(n351), .B(n350), .Y(res[7]) );
XOR2X1TS U423 ( .A(n352), .B(in2[1]), .Y(n355) );
AOI21X1TS U424 ( .A0(n94), .A1(in2[1]), .B0(in1[1]), .Y(n354) );
NAND2X1TS U425 ( .A(n367), .B(n17), .Y(n356) );
XNOR2X1TS U426 ( .A(n356), .B(in2[6]), .Y(n358) );
AOI21X1TS U427 ( .A0(n94), .A1(in2[6]), .B0(in1[6]), .Y(n357) );
XOR2X1TS U428 ( .A(n359), .B(in2[5]), .Y(n361) );
AOI21X1TS U429 ( .A0(n94), .A1(in2[5]), .B0(in1[5]), .Y(n360) );
XNOR2X1TS U430 ( .A(n11), .B(in2[2]), .Y(n363) );
AOI21X1TS U431 ( .A0(n353), .A1(in2[2]), .B0(in1[2]), .Y(n362) );
XNOR2X1TS U432 ( .A(n364), .B(n90), .Y(n366) );
AOI21X1TS U433 ( .A0(n94), .A1(in2[3]), .B0(in1[3]), .Y(n365) );
XOR2X1TS U434 ( .A(n367), .B(in2[4]), .Y(n370) );
AOI21X1TS U435 ( .A0(n94), .A1(in2[4]), .B0(in1[4]), .Y(n369) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_LOALPL7_syn.sdf");
endmodule
|
// Copyright 2008, 2009 by Jakub Bednarski
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Minimig is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
//
// -- JB --
//
// 2008-10-06 - initial version
// 2008-10-08 - interrupt controller implemented, kickstart boots
// 2008-10-09 - working identify device command implemented (hdtoolbox detects our drive)
// - read command reads data from hardfile (fixed size and name, only one sector read size supported, workbench sees hardfile partition)
// 2008-10-10 - multiple sector transfer supported: works ok, sequential transfers with direct spi read and 28MHz CPU from 400 to 520 KB/s
// - arm firmare seekfile function very slow: seeking from start to 20MB takes 144 ms (some software improvements required)
// 2008-10-30 - write support added
// 2008-12-31 - added hdd enable
// 2009-05-24 - clean-up & renaming
// 2009-08-11 - hdd_ena enables Master & Slave drives
// 2009-11-18 - changed sector buffer size
// 2010-04-13 - changed sector buffer size
// 2010-08-10 - improved BSY signal handling
module gayle
(
input clk,
input clk7_en,
input reset,
input [23:1] address_in,
input [15:0] data_in,
output [15:0] data_out,
input rd,
input hwr,
input lwr,
input sel_ide, // $DAxxxx
input sel_gayle, // $DExxxx
output irq,
output nrdy, // fifo is not ready for reading
input [1:0] hdd_ena, // enables Master & Slave drives
output hdd_cmd_req,
output hdd_dat_req,
input [2:0] hdd_addr,
input [15:0] hdd_data_out,
output [15:0] hdd_data_in,
input hdd_wr,
input hdd_status_wr,
input hdd_data_wr,
input hdd_data_rd,
output hd_fwr,
output hd_frd
);
localparam VCC = 1'b1;
localparam GND = 1'b0;
//0xda2000 Data
//0xda2004 Error | Feature
//0xda2008 SectorCount
//0xda200c SectorNumber
//0xda2010 CylinderLow
//0xda2014 CylinderHigh
//0xda2018 Device/Head
//0xda201c Status | Command
//0xda3018 Control
/*
memory map:
$DA0000 - $DA0FFFF : CS1 16-bit speed
$DA1000 - $DA1FFFF : CS2 16-bit speed
$DA2000 - $DA2FFFF : CS1 8-bit speed
$DA3000 - $DA3FFFF : CS2 8-bit speed
$DA4000 - $DA7FFFF : reserved
$DA8000 - $DA8FFFF : IDE INTREQ state status register (not implemented as scsi.device doesn't use it)
$DA9000 - $DA9FFFF : IDE INTREQ change status register (writing zeros resets selected bits, writing ones doesn't change anything)
$DAA000 - $DAAFFFF : IDE INTENA register (r/w, only MSB matters)
command class:
PI (PIO In)
PO (PIO Out)
ND (No Data)
Status:
#6 - DRDY - Drive Ready
#7 - BSY - Busy
#3 - DRQ - Data Request
#0 - ERR - Error
INTRQ - Interrupt Request
*/
// address decoding signals
wire sel_gayleid; // Gayle ID register select
wire sel_tfr; // HDD task file registers select
wire sel_fifo; // HDD data port select (FIFO buffer)
wire sel_status; // HDD status register select
wire sel_command; // HDD command register select
wire sel_cs; // Gayle IDE CS
wire sel_intreq; // Gayle interrupt request status register select
wire sel_intena; // Gayle interrupt enable register select
wire sel_cfg; // Gayle CFG
// internal registers
reg intena; // Gayle IDE interrupt enable bit
reg intreq; // Gayle IDE interrupt request bit
reg busy; // busy status (command processing state)
reg pio_in; // pio in command type is being processed
reg pio_out; // pio out command type is being processed
reg error; // error status (command processing failed)
reg [3:0] cfg;
reg [1:0] cs;
reg [5:0] cs_mask;
reg dev; // drive select (Master/Slave)
wire bsy; // busy
wire drdy; // drive ready
wire drq; // data request
wire err; // error
wire [7:0] status; // HDD status
// FIFO control
wire fifo_reset;
wire [15:0] fifo_data_in;
wire [15:0] fifo_data_out;
wire fifo_rd;
wire fifo_wr;
wire fifo_full;
wire fifo_empty;
wire fifo_last; // last word of a sector is being read
// gayle id reg
reg [1:0] gayleid_cnt; // sequence counter
wire gayleid; // output data (one bit wide)
// hd leds
assign hd_fwr = fifo_wr;
assign hd_frd = fifo_rd;
// HDD status register
assign status = {bsy,drdy,2'b00,drq,2'b00,err};
// status debug
reg [7:0] status_dbg /* synthesis syn_noprune */;
always @ (posedge clk) status_dbg <= #1 status;
// HDD status register bits
assign bsy = busy & ~drq;
assign drdy = ~(bsy|drq);
assign err = error;
// address decoding
assign sel_gayleid = sel_gayle && address_in[15:12]==4'b0001 ? VCC : GND; // GAYLEID, $DE1xxx
assign sel_tfr = sel_ide && address_in[15:14]==2'b00 && !address_in[12] ? VCC : GND; // $DA0xxx, $DA2xxx
assign sel_status = rd && sel_tfr && address_in[4:2]==3'b111 ? VCC : GND;
assign sel_command = hwr && sel_tfr && address_in[4:2]==3'b111 ? VCC : GND;
assign sel_fifo = sel_tfr && address_in[4:2]==3'b000 ? VCC : GND;
assign sel_cs = sel_ide && address_in[15:12]==4'b1000 ? VCC : GND; // GAYLE_CS_1200, $DA8xxx
assign sel_intreq = sel_ide && address_in[15:12]==4'b1001 ? VCC : GND; // GAYLE_IRQ_1200, $DA9xxx
assign sel_intena = sel_ide && address_in[15:12]==4'b1010 ? VCC : GND; // GAYLE_INT_1200, $DAAxxx
assign sel_cfg = sel_ide && address_in[15:12]==4'b1011 ? VCC : GND; // GAYLE_CFG_1200, $DABxxx
//===============================================================================================//
// gayle cs
always @ (posedge clk) begin
if (clk7_en) begin
if (reset) begin
cs_mask <= #1 6'd0;
cs <= #1 2'd0;
end else if (hwr && sel_cs) begin
cs_mask <= #1 data_in[15:10];
cs <= #1 data_in[9:8];
end
end
end
// gayle cfg
always @ (posedge clk) begin
if (clk7_en) begin
if (reset)
cfg <= #1 4'd0;
if (hwr && sel_cfg) begin
cfg <= #1 data_in[15:12];
end
end
end
// task file registers
reg [7:0] tfr [7:0];
wire [2:0] tfr_sel;
wire [7:0] tfr_in;
wire [7:0] tfr_out;
wire tfr_we;
reg [7:0] sector_count; // sector counter
wire sector_count_dec; // decrease sector counter
always @(posedge clk)
if (clk7_en) begin
if (hwr && sel_tfr && address_in[4:2] == 3'b010) // sector count register loaded by the host
sector_count <= data_in[15:8];
else if (sector_count_dec)
sector_count <= sector_count - 8'd1;
end
assign sector_count_dec = pio_in & fifo_last & sel_fifo & rd;
// task file register control
assign tfr_we = busy ? hdd_wr : sel_tfr & hwr;
assign tfr_sel = busy ? hdd_addr : address_in[4:2];
assign tfr_in = busy ? hdd_data_out[7:0] : data_in[15:8];
// input multiplexer for SPI host
assign hdd_data_in = tfr_sel==0 ? fifo_data_out : {8'h00,tfr_out};
// task file registers
always @(posedge clk)
if (clk7_en) begin
if (tfr_we)
tfr[tfr_sel] <= tfr_in;
end
assign tfr_out = tfr[tfr_sel];
// master/slave drive select
always @(posedge clk)
if (clk7_en) begin
if (reset)
dev <= 0;
else if (sel_tfr && address_in[4:2]==6 && hwr)
dev <= data_in[12];
end
// IDE interrupt enable register
always @(posedge clk)
if (clk7_en) begin
if (reset)
intena <= GND;
else if (sel_intena && hwr)
intena <= data_in[15];
end
// gayle id register: reads 1->1->0->1 on MSB
always @(posedge clk)
if (clk7_en) begin
if (sel_gayleid)
if (hwr) // a write resets sequence counter
gayleid_cnt <= 2'd0;
else if (rd)
gayleid_cnt <= gayleid_cnt + 2'd1;
end
assign gayleid = ~gayleid_cnt[1] | gayleid_cnt[0]; // Gayle ID output data
// status register (write only from SPI host)
// 7 - busy status (write zero to finish command processing: allow host access to task file registers)
// 6
// 5
// 4 - intreq
// 3 - drq enable for pio in (PI) command type
// 2 - drq enable for pio out (PO) command type
// 1
// 0 - error flag (remember about setting error task file register)
// command busy status
always @(posedge clk)
if (clk7_en) begin
if (reset)
busy <= GND;
else if (hdd_status_wr && hdd_data_out[7] || (sector_count_dec && sector_count == 8'h01)) // reset by SPI host (by clearing BSY status bit)
busy <= GND;
else if (sel_command) // set when the CPU writes command register
busy <= VCC;
end
// IDE interrupt request register
always @(posedge clk)
if (clk7_en) begin
if (reset)
intreq <= GND;
else if (busy && hdd_status_wr && hdd_data_out[4] && intena) // set by SPI host
intreq <= VCC;
else if (sel_intreq && hwr && !data_in[15]) // cleared by the CPU
intreq <= GND;
end
assign irq = (~pio_in | drq) & intreq; // interrupt request line (INT2)
// pio in command type
always @(posedge clk)
if (clk7_en) begin
if (reset)
pio_in <= GND;
else if (drdy) // reset when processing of the current command ends
pio_in <= GND;
else if (busy && hdd_status_wr && hdd_data_out[3]) // set by SPI host
pio_in <= VCC;
end
// pio out command type
always @(posedge clk)
if (clk7_en) begin
if (reset)
pio_out <= GND;
else if (busy && hdd_status_wr && hdd_data_out[7]) // reset by SPI host when command processing completes
pio_out <= GND;
else if (busy && hdd_status_wr && hdd_data_out[2]) // set by SPI host
pio_out <= VCC;
end
assign drq = (fifo_full & pio_in) | (~fifo_full & pio_out); // HDD data request status bit
// error status
always @(posedge clk)
if (clk7_en) begin
if (reset)
error <= GND;
else if (sel_command) // reset by the CPU when command register is written
error <= GND;
else if (busy && hdd_status_wr && hdd_data_out[0]) // set by SPI host
error <= VCC;
end
assign hdd_cmd_req = bsy; // bsy is set when command register is written, tells the SPI host about new command
assign hdd_dat_req = (fifo_full & pio_out); // the FIFO is full so SPI host may read it
// FIFO in/out multiplexer
assign fifo_reset = reset | sel_command;
assign fifo_data_in = pio_in ? hdd_data_out : data_in;
assign fifo_rd = pio_out ? hdd_data_rd : sel_fifo & rd;
assign fifo_wr = pio_in ? hdd_data_wr : sel_fifo & hwr & lwr;
//sector data buffer (FIFO)
gayle_fifo SECBUF1
(
.clk(clk),
.clk7_en(clk7_en),
.reset(fifo_reset),
.data_in(fifo_data_in),
.data_out(fifo_data_out),
.rd(fifo_rd),
.wr(fifo_wr),
.full(fifo_full),
.empty(fifo_empty),
.last(fifo_last)
);
// fifo is not ready for reading
assign nrdy = pio_in & sel_fifo & fifo_empty;
//data_out multiplexer
assign data_out = (sel_fifo && rd ? fifo_data_out : sel_status ? (!dev && hdd_ena[0]) || (dev && hdd_ena[1]) ? {status,8'h00} : 16'h00_00 : sel_tfr && rd ? {tfr_out,8'h00} : 16'h00_00)
| (sel_cs && rd ? {(cs_mask[5] || intreq), cs_mask[4:0], cs, 8'h0} : 16'h00_00)
| (sel_intreq && rd ? {intreq, 15'b000_0000_0000_0000} : 16'h00_00)
| (sel_intena && rd ? {intena, 15'b000_0000_0000_0000} : 16'h00_00)
| (sel_gayleid && rd ? {gayleid,15'b000_0000_0000_0000} : 16'h00_00)
| (sel_cfg && rd ? {cfg, 12'b0000_0000_0000} : 16'h00_00);
//===============================================================================================//
endmodule
|
module qsys_serial_device#(
parameter address_size=8)(
// Qsys bus interface
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output reg[31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input [7:0] avs_ctrl_address,
input avs_ctrl_write,
input avs_ctrl_read,
input avs_ctrl_chipselect,
output reg avs_ctrl_waitrequest,
output reg avs_ctrl_readdatavalid,
// Qsys serial interface
output reg sdo,
input sdi,
output clk,
output reg sle,
input srdy
);
reg [64:0] data_buffer;
assign clk = csi_MCLK_clk;
parameter initial_state = 8'd0;
parameter bus_data_wait = initial_state+8'd1;
parameter bus_data_ready = bus_data_wait+8'd1;
parameter bus_transmit_start = bus_data_ready + 8'd1;
parameter bus_transmit_ready = bus_transmit_start + 8'd64;
parameter bus_transmit_finish = bus_transmit_ready + 8'd1;
parameter bus_ready_wait = bus_transmit_finish + 8'd1;
parameter bus_transmit_back = bus_ready_wait + 8'd1;
parameter bus_data_read = bus_transmit_back + 8'd1;
parameter bus_data_read_finish = bus_data_read + 8'd2;
reg [7:0] state;
reg [7:0] nextstate;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if (rsi_MRST_reset)
state <= initial_state;
else
state <= nextstate;
end
always@(state or srdy or avs_ctrl_write or avs_ctrl_read)
begin
case(state)
initial_state: nextstate <= bus_data_wait;
bus_data_wait: begin
if(avs_ctrl_write == 1'b1 || avs_ctrl_read == 1'b1)
begin
if(avs_ctrl_chipselect == 1'b1)
nextstate <= bus_data_ready;
else
nextstate <= bus_data_wait;
end
else
nextstate <= bus_data_wait;
end
bus_data_ready: nextstate <= bus_transmit_start;
bus_transmit_start: nextstate <= state + 1;
bus_transmit_ready: nextstate <= bus_transmit_finish;
bus_transmit_finish: nextstate <= bus_ready_wait;
bus_ready_wait:
begin
if(srdy == 1'b1)
nextstate <= bus_transmit_back;
else
nextstate <= bus_ready_wait;
end
bus_transmit_back:
begin
if(srdy == 1'b0)
nextstate <= bus_data_read;
else
nextstate <= bus_transmit_back;
end
bus_data_read: nextstate <= state +1;
bus_data_read_finish: nextstate <= bus_data_wait;
default: nextstate <= state + 1;
endcase
end
always@(posedge csi_MCLK_clk)
begin
if (state == bus_data_wait)
begin
data_buffer[63:32] <= avs_ctrl_address;
if (avs_ctrl_write == 1'b1)
begin
data_buffer[64] <= 1'b1; //write
data_buffer[31:0] <= avs_ctrl_writedata;
end
else if (avs_ctrl_read == 1'b1)
begin
data_buffer[64] <= 1'b0; //read
data_buffer[31:0] <= 32'd0;
end
end
else if (state >= bus_transmit_start && state <= bus_transmit_ready)
begin
integer i;
for(i=0;i<64;i=i+1)
data_buffer[i+1] <= data_buffer[i];
sdo <= data_buffer[64];
end
else if (state == bus_transmit_back)
begin
integer i;
for(i=0;i<64;i=i+1)
data_buffer[i+1] <= data_buffer[i];
data_buffer[0]<= sdi;
end
end
always@(posedge csi_MCLK_clk)
begin
if (state >= bus_data_ready && state < bus_transmit_ready)
sle <= 1;
else
sle <= 0;
end
always@(state)
begin
if (state >= bus_data_ready && state <= bus_data_read)
avs_ctrl_waitrequest = 1'b1;
else
avs_ctrl_waitrequest = 1'b0;
end
always@(posedge csi_MCLK_clk)
begin
if (state == bus_data_read )
avs_ctrl_readdatavalid <= 1'b1;
else
avs_ctrl_readdatavalid <= 1'b0;
end
always@(posedge csi_MCLK_clk)
begin
if (state == bus_data_read)
begin
avs_ctrl_readdata <= data_buffer[31:0];
end
end
endmodule
|
// DESCRIPTION: Verilator: Test symbol table scope map and general public
// signal reflection
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Todd Strader.
module t (
input wire CLK
);
foo #(.WIDTH (1)) foo1 (.*);
foo #(.WIDTH (7)) foo7 (.*);
foo #(.WIDTH (8)) foo8 (.*);
foo #(.WIDTH (32)) foo32 (.*);
foo #(.WIDTH (33)) foo33 (.*);
foo #(.WIDTH (40)) foo40 (.*);
foo #(.WIDTH (41)) foo41 (.*);
foo #(.WIDTH (64)) foo64 (.*);
foo #(.WIDTH (65)) foo65 (.*);
foo #(.WIDTH (96)) foo96 (.*);
foo #(.WIDTH (97)) foo97 (.*);
foo #(.WIDTH (128)) foo128 (.*);
foo #(.WIDTH (256)) foo256 (.*);
foo #(.WIDTH (1024)) foo1024 (.*);
bar #(.WIDTH (1024)) bar1024 (.*);
endmodule
module foo
#(
parameter WIDTH = 32
)
(
input CLK
);
logic [ ( ( WIDTH + 7 ) / 8 ) * 8 - 1 : 0 ] initial_value;
logic [ WIDTH - 1 : 0 ] value_q /* verilator public */;
integer i;
initial begin
initial_value = '1;
for (i = 0; i < WIDTH / 8; i++)
initial_value[ i * 8 +: 8 ] = i[ 7 : 0 ];
value_q = initial_value[ WIDTH - 1 : 0 ];
end
always @(posedge CLK)
value_q <= ~value_q;
endmodule
module bar
#(
parameter WIDTH = 32
)
(
input CLK
);
foo #(.WIDTH (WIDTH)) foo (.*);
endmodule
|
`timescale 1ns / 1ps
/*******************************************************************************
* Engineer: Robin zhang
* Create Date: 2016.09.10
* Module Name: spi_slave
*******************************************************************************/
module spi_slave_0_base(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_status;
reg[2:0] sckr;
reg[2:0] sselr;
reg[1:0] mosir;
reg[2:0] bitcnt;
reg[7:0] bytecnt;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
reg[7:0] received_memory;
reg [7:0] byte_data_sent;
reg [7:0] cnt;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire ssel_startmessage;
wire ssel_endmessage;
wire mosi_data;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sckr <= 3'h0;
else
sckr <= {sckr[1:0],sck};
end
assign sck_risingedge = (sckr[2:1] == 2'b01) ? 1'b1 : 1'b0;
assign sck_fallingedge = (sckr[2:1] == 2'b10) ? 1'b1 : 1'b0;
/*******************************************************************************
*detect starts at falling edge and stops at rising edge of ssel
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sselr <= 3'h0;
else
sselr <= {sselr[1:0],ssel};
end
assign ssel_active = (~sselr[1]) ? 1'b1 : 1'b0; // SSEL is active low
assign ssel_startmessage = (sselr[2:1]==2'b10) ? 1'b1 : 1'b0; // message starts at falling edge
assign ssel_endmessage = (sselr[2:1]==2'b01) ? 1'b1 : 1'b0; // message stops at rising edge
/*******************************************************************************
*read from mosi
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
mosir <= 2'h0;
else
mosir <={mosir[0],mosi};
end
assign mosi_data = mosir[1];
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
bitcnt <= 3'b000;
byte_data_received <= 8'h0;
end
else begin
if(~ssel_active)
bitcnt <= 3'b000;
else begin
if(sck_risingedge)begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], mosi_data};
end
else begin
bitcnt <= bitcnt;
byte_data_received <= byte_data_received;
end
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_received <= 1'b0;
else
byte_received <= ssel_active && sck_risingedge && (bitcnt==3'b111);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
bytecnt <= 8'h0;
received_memory <= 8'h0;
end
else begin
if(byte_received) begin
bytecnt <= bytecnt + 1'b1;
received_memory <= (byte_data_received == bytecnt) ? (received_memory + 1'b1) : received_memory;
end
else begin
bytecnt <= bytecnt;
received_memory <= received_memory;
end
end
end
/*******************************************************************************
*SPI slave send date
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt<= 8'h0;
else begin
if(byte_received)
cnt<=cnt+8'h1; // count the messages
else
cnt<=cnt;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_data_sent <= 8'h0;
else begin
if(ssel_active && sck_fallingedge) begin
if(bitcnt==3'b000)
byte_data_sent <= cnt; // after that, we send 0s
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
else
byte_data_sent <= byte_data_sent;
end
end
assign miso = byte_data_sent[7]; // send MSB first
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
recived_status <= 1'b0;
else
recived_status <= (received_memory == 8'd64) ? 1'b1 : 1'b0;
end
endmodule
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
simple, everyday mathematics: If a procedure or method has no side
effects, then pretty much all you need to understand about it is
how it maps inputs to outputs -- that is, you can think of it as
just a concrete method for computing a mathematical function.
This is one sense of the word "functional" in "functional
programming." The direct connection between programs and simple
mathematical objects supports both formal proofs of correctness
and sound informal reasoning about program behavior.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful and powerful idioms.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
The first half of this chapter introduces the most essential
elements of Coq's functional programming language. The second
half introduces some basic _tactics_ that can be used to prove
simple properties of Coq programs.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code. To illustrate this, we will explicitly
recapitulate all the definitions we need in this course, rather
than just getting them implicitly from the library.
To see how this mechanism works, let's start with a very simple
example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second and following lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often figure out these types for
itself when they are not given explicitly -- i.e., it performs
some _type inference_ -- but we'll always include them to make
reading easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq.
First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, this would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to _extract_, from our [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters. More
information can also be found in the Coq'Art book by Bertot and
Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the standard type [bool] of
booleans, with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] automatically performs
simplification.) *)
(** _A note on notation_: In .v files, we use square brackets to
delimit fragments of Coq code within comments; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
negb (andb b1 b2).
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
andb (andb b1 b2) b3.
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => 1
| S n' => mult n (factorial n')
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Advanced Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function. *)
Definition blt_nat (n m : nat) : bool :=
ble_nat (S n) m.
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** We could try to prove a similar theorem about [plus] *)
Theorem plus_n_O : forall n, n + 0 = n.
(** However, unlike the previous proof, [simpl] doesn't do anything in
this case *)
Proof.
simpl. (* Doesn't do anything! *)
Abort.
(** (Can you explain why this happens? Step through both proofs with
Coq and notice how the goal and context change.) *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the/ left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o H1 H2.
rewrite H1. rewrite <- H2.
reflexivity.
Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m H. simpl. rewrite <- H.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n.
destruct n as [| n'].
simpl. reflexivity.
simpl. reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean_functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H b.
rewrite H. rewrite H. reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H b.
rewrite H. rewrite H.
rewrite negb_involutive.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Lemma andb_true :
forall (b : bool),
andb b true = true -> b = true.
Proof.
intros b H.
destruct b. reflexivity.
inversion H.
Qed.
Lemma orb_true :
forall (b : bool),
orb b true = true.
Proof.
intros b. destruct b; reflexivity.
Qed.
Lemma andb_true_b :
forall (b : bool),
andb b true = b.
Proof.
intros b.
destruct b; reflexivity.
Qed.
Lemma orb_false_b :
forall (b : bool),
orb b false = b.
Proof.
intros b. destruct b; reflexivity.
Qed.
Theorem andb_false :
forall (b : bool),
andb b false = false.
Proof.
intros b. destruct b ; reflexivity.
Qed.
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c H.
destruct c.
rewrite <- orb_true with (b := b).
rewrite <- H. rewrite andb_true_b. reflexivity.
rewrite <- andb_false with (b := b).
rewrite H. rewrite orb_false_b. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function [incr] for binary numbers,
and a function [bin_to_nat] to convert binary numbers to unary numbers.
(c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc.
for your increment and binary-to-unary functions. Notice that
incrementing a binary number and then converting it to unary
should yield the same result as first converting it to unary and
then incrementing.
*)
Inductive bin : Type :=
| Ob : bin
| Tb : bin -> bin
| STb : bin -> bin.
Fixpoint incr (n: bin) : bin :=
match n with
| Ob => STb Ob
| Tb n => STb n
| STb n => Tb (incr n)
end.
Fixpoint bin_to_nat (n : bin) : nat :=
match n with
| Ob => O
| Tb n => 2 * (bin_to_nat n)
| STb n => 2 * (bin_to_nat n) + 1
end.
Lemma plus_1_S : forall n : nat, n + 1 = S n.
Proof.
intros n.
induction n. simpl. reflexivity.
simpl. rewrite IHn. reflexivity.
Qed.
Lemma plus_O : forall n : nat, n + 0 = n.
intros n. induction n. reflexivity. simpl. rewrite IHn. reflexivity.
Qed.
Lemma S_equal : forall n m : nat, S n = S m <-> n = m.
Proof.
intros n m.
split. intros H. inversion H. reflexivity.
intros H. rewrite H. reflexivity.
Qed.
Lemma S_equal_l : forall n m : nat, S n = S m -> n = m.
Proof.
intros n m H. inversion H. reflexivity.
Qed.
Lemma S_equal_r : forall n m : nat, n = m -> S n = S m.
intros n m H. rewrite H. reflexivity.
Qed.
Lemma plus_SS : forall n m : nat, S n + S m = S (S (n + m)).
Proof.
intros n. induction n as [|n'].
intros m. simpl. reflexivity.
intros m. simpl. apply S_equal. rewrite <- IHn'. simpl. reflexivity.
Qed.
Theorem incr_bin_nat :
forall n : bin,
bin_to_nat (incr n) = S (bin_to_nat n).
Proof.
intros n.
induction n as [| n' | n'].
(* n = Ob *) simpl. reflexivity.
(* n = Tb n' *) simpl. rewrite plus_1_S. reflexivity.
(* n = STb n' *)
simpl. rewrite IHn'.
rewrite plus_1_S. rewrite plus_O. rewrite plus_O. rewrite plus_SS. reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More on Notation (Advanced) *)
(** In general, sections marked Advanced are not needed to follow the
rest of the book, except possibly other Advanced sections. On a
first reading, you might want to skim these sections so that you
know what's there for future reference. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** * [Fixpoint] and Structural Recursion (Advanced) *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will reject because
of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
|
/* -*- tab-width: 4 -*-
*
* Electric(tm) VLSI Design System
*
* File: jtagController.v
*
* Copyright (c) 2005 Sun Microsystems and Static Free Software
*
* Electric(tm) is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* Electric(tm) is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Electric(tm); see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, Mass 02111-1307, USA.
*/
/* Verilog for cell testCell{sch} from Library jtag */
/* Created on Tue April 26, 2005 11:27:36 */
/* Last revised on Tue April 26, 2005 11:29:37 */
/* Written on Tue April 26, 2005 11:30:54 by Electric VLSI Design System, version 8.02l */
module redFour__NMOSwk_X_1_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
rtranif1 #(100) NMOSfwk_0 (d, s, g);
endmodule /* redFour__NMOSwk_X_1_Delay_100 */
module redFour__PMOSwk_X_0_833_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
rtranif0 #(100) PMOSfwk_0 (d, s, g);
endmodule /* redFour__PMOSwk_X_0_833_Delay_100 */
module scanChainFive__scanL(in, out);
input in;
output out;
supply1 vdd;
supply0 gnd;
wire net_4, net_7;
redFour__NMOSwk_X_1_Delay_100 NMOSwk_0(.g(out), .d(in), .s(net_7));
redFour__NMOSwk_X_1_Delay_100 NMOSwk_1(.g(out), .d(net_7), .s(gnd));
redFour__PMOSwk_X_0_833_Delay_100 PMOSwk_0(.g(out), .d(net_4), .s(vdd));
redFour__PMOSwk_X_0_833_Delay_100 PMOSwk_1(.g(out), .d(in), .s(net_4));
not (strong0, strong1) #(100) invV_0 (out, in);
endmodule /* scanChainFive__scanL */
module redFour__NMOS_X_6_667_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule /* redFour__NMOS_X_6_667_Delay_100 */
module redFour__PMOS_X_3_333_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule /* redFour__PMOS_X_3_333_Delay_100 */
module scanChainFive__scanP(in, src, drn);
input in;
input src;
output drn;
supply1 vdd;
supply0 gnd;
wire net_1;
redFour__NMOS_X_6_667_Delay_100 NMOS_0(.g(in), .d(drn), .s(src));
redFour__PMOS_X_3_333_Delay_100 PMOS_0(.g(net_1), .d(drn), .s(src));
not (strong0, strong1) #(0) inv_0 (net_1, in);
endmodule /* scanChainFive__scanP */
module scanChainFive__scanRL(phi1, phi2, rd, sin, sout);
input phi1;
input phi2;
input rd;
input sin;
output sout;
supply1 vdd;
supply0 gnd;
wire net_0, net_2, net_3;
scanChainFive__scanL foo1(.in(net_2), .out(net_3));
scanChainFive__scanL foo2(.in(net_0), .out(sout));
scanChainFive__scanP scanP_0(.in(rd), .src(vdd), .drn(net_0));
scanChainFive__scanP scanP_1(.in(phi1), .src(net_3), .drn(net_0));
scanChainFive__scanP scanP_2(.in(phi2), .src(sin), .drn(net_2));
endmodule /* scanChainFive__scanRL */
module jtag__BR(SDI, phi1, phi2, read, SDO);
input SDI;
input phi1;
input phi2;
input read;
output SDO;
supply1 vdd;
supply0 gnd;
scanChainFive__scanRL scanRL_0(.phi1(phi1), .phi2(phi2), .rd(read),
.sin(SDI), .sout(SDO));
endmodule /* jtag__BR */
module scanChainFive__scanIRH(mclr, phi1, phi2, rd, sin, wr, dout, doutb,
sout);
input mclr;
input phi1;
input phi2;
input rd;
input sin;
input wr;
output dout;
output doutb;
output sout;
supply1 vdd;
supply0 gnd;
wire net_2, net_4, net_6, net_7;
scanChainFive__scanL foo1(.in(net_6), .out(net_7));
scanChainFive__scanL foo2(.in(net_2), .out(sout));
scanChainFive__scanL foo3(.in(net_4), .out(doutb));
not (strong0, strong1) #(100) invLT_0 (dout, doutb);
scanChainFive__scanP scanP_0(.in(wr), .src(sout), .drn(net_4));
scanChainFive__scanP scanP_1(.in(rd), .src(gnd), .drn(net_2));
scanChainFive__scanP scanP_2(.in(mclr), .src(vdd), .drn(net_4));
scanChainFive__scanP scanP_3(.in(phi1), .src(net_7), .drn(net_2));
scanChainFive__scanP scanP_4(.in(phi2), .src(sin), .drn(net_6));
endmodule /* scanChainFive__scanIRH */
module scanChainFive__scanIRL(mclr, phi1, phi2, rd, sin, wr, dout, doutb,
sout);
input mclr;
input phi1;
input phi2;
input rd;
input sin;
input wr;
output dout;
output doutb;
output sout;
supply1 vdd;
supply0 gnd;
wire net_2, net_3, net_4, net_6;
scanChainFive__scanL foo1(.in(net_2), .out(net_3));
scanChainFive__scanL foo2(.in(net_4), .out(sout));
scanChainFive__scanL foo3(.in(net_6), .out(doutb));
not (strong0, strong1) #(100) invLT_0 (dout, doutb);
scanChainFive__scanP scanP_0(.in(rd), .src(vdd), .drn(net_4));
scanChainFive__scanP scanP_1(.in(mclr), .src(vdd), .drn(net_6));
scanChainFive__scanP scanP_2(.in(wr), .src(sout), .drn(net_6));
scanChainFive__scanP scanP_3(.in(phi1), .src(net_3), .drn(net_4));
scanChainFive__scanP scanP_4(.in(phi2), .src(sin), .drn(net_2));
endmodule /* scanChainFive__scanIRL */
module jtag__IR(SDI, phi1, phi2, read, reset, write, IR, IRb, SDO);
input SDI;
input phi1;
input phi2;
input read;
input reset;
input write;
output [8:1] IR;
output [8:1] IRb;
output SDO;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_4, net_5, net_6, net_7;
scanChainFive__scanIRH scanIRH_0(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_1), .wr(write), .dout(IR[1]), .doutb(IRb[1]),
.sout(SDO));
scanChainFive__scanIRL scanIRL_0(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_3), .wr(write), .dout(IR[7]), .doutb(IRb[7]),
.sout(net_2));
scanChainFive__scanIRL scanIRL_1(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_5), .wr(write), .dout(IR[5]), .doutb(IRb[5]),
.sout(net_4));
scanChainFive__scanIRL scanIRL_2(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_2), .wr(write), .dout(IR[6]), .doutb(IRb[6]),
.sout(net_5));
scanChainFive__scanIRL scanIRL_3(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_7), .wr(write), .dout(IR[3]), .doutb(IRb[3]),
.sout(net_6));
scanChainFive__scanIRL scanIRL_4(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_6), .wr(write), .dout(IR[2]), .doutb(IRb[2]),
.sout(net_1));
scanChainFive__scanIRL scanIRL_5(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_4), .wr(write), .dout(IR[4]), .doutb(IRb[4]),
.sout(net_7));
scanChainFive__scanIRL scanIRL_6(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(SDI), .wr(write), .dout(IR[8]), .doutb(IRb[8]),
.sout(net_3));
endmodule /* jtag__IR */
module redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nor (strong0, strong1) #(100) nor2_0 (out, ina, inb);
endmodule /* redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1 */
module jtag__IRdecode(IR, IRb, Bypass, ExTest, SamplePreload, ScanPath);
input [4:1] IR;
input [4:1] IRb;
output Bypass;
output ExTest;
output SamplePreload;
output [12:0] ScanPath;
supply1 vdd;
supply0 gnd;
wire H00, H01, H10, H11, L00, L01, L10, L11, net_19, net_21, net_23, net_25;
wire net_26, net_27, net_28, net_29, net_30, net_31, net_32, net_33, net_34;
wire net_35, net_36, net_37;
not (strong0, strong1) #(100) inv_0 (Bypass, net_19);
not (strong0, strong1) #(100) inv_1 (SamplePreload, net_21);
not (strong0, strong1) #(100) inv_2 (ExTest, net_23);
not (strong0, strong1) #(100) inv_3 (ScanPath[12], net_25);
not (strong0, strong1) #(100) inv_4 (ScanPath[11], net_26);
not (strong0, strong1) #(100) inv_5 (ScanPath[10], net_27);
not (strong0, strong1) #(100) inv_6 (ScanPath[9], net_28);
not (strong0, strong1) #(100) inv_7 (ScanPath[8], net_29);
not (strong0, strong1) #(100) inv_8 (ScanPath[7], net_30);
not (strong0, strong1) #(100) inv_9 (ScanPath[6], net_31);
not (strong0, strong1) #(100) inv_10 (ScanPath[5], net_32);
not (strong0, strong1) #(100) inv_11 (ScanPath[4], net_33);
not (strong0, strong1) #(100) inv_12 (ScanPath[3], net_34);
not (strong0, strong1) #(100) inv_13 (ScanPath[2], net_35);
not (strong0, strong1) #(100) inv_14 (ScanPath[1], net_36);
not (strong0, strong1) #(100) inv_15 (ScanPath[0], net_37);
nand (strong0, strong1) #(100) nand2_0 (net_19, L11, H11);
nand (strong0, strong1) #(100) nand2_1 (net_21, L10, H11);
nand (strong0, strong1) #(100) nand2_2 (net_23, L01, H11);
nand (strong0, strong1) #(100) nand2_3 (net_25, L00, H11);
nand (strong0, strong1) #(100) nand2_4 (net_26, L11, H10);
nand (strong0, strong1) #(100) nand2_5 (net_27, L10, H10);
nand (strong0, strong1) #(100) nand2_6 (net_28, L01, H10);
nand (strong0, strong1) #(100) nand2_7 (net_29, L00, H10);
nand (strong0, strong1) #(100) nand2_8 (net_30, L11, H01);
nand (strong0, strong1) #(100) nand2_9 (net_31, L10, H01);
nand (strong0, strong1) #(100) nand2_10 (net_32, L01, H01);
nand (strong0, strong1) #(100) nand2_11 (net_33, L00, H01);
nand (strong0, strong1) #(100) nand2_12 (net_34, L11, H00);
nand (strong0, strong1) #(100) nand2_13 (net_35, L10, H00);
nand (strong0, strong1) #(100) nand2_14 (net_36, L01, H00);
nand (strong0, strong1) #(100) nand2_15 (net_37, L00, H00);
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_0(.ina(IR[1]), .inb(IR[2]), .out(L00));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_1(.ina(IRb[1]), .inb(IR[2]), .out(L01));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_2(.ina(IR[1]), .inb(IRb[2]), .out(L10));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_3(.ina(IRb[1]), .inb(IRb[2]), .out(L11));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_4(.ina(IR[3]), .inb(IR[4]), .out(H00));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_5(.ina(IRb[3]), .inb(IR[4]), .out(H01));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_6(.ina(IR[3]), .inb(IRb[4]), .out(H10));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_7(.ina(IRb[3]), .inb(IRb[4]), .out(H11));
endmodule /* jtag__IRdecode */
module redFour__PMOSwk_X_0_222_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
rtranif0 #(100) PMOSfwk_0 (d, s, g);
endmodule /* redFour__PMOSwk_X_0_222_Delay_100 */
module jtag__clockGen(clk, phi1_fb, phi2_fb, phi1_out, phi2_out);
input clk;
input phi1_fb;
input phi2_fb;
output phi1_out;
output phi2_out;
supply1 vdd;
supply0 gnd;
wire net_0, net_1, net_3, net_4, net_6;
not (strong0, strong1) #(100) inv_0 (phi2_out, net_3);
not (strong0, strong1) #(100) inv_1 (phi1_out, net_6);
not (strong0, strong1) #(100) inv_2 (net_4, clk);
not (strong0, strong1) #(100) invLT_0 (net_0, phi1_fb);
not (strong0, strong1) #(100) invLT_1 (net_1, phi2_fb);
nand (strong0, strong1) #(100) nand2_0 (net_3, net_0, net_4);
nand (strong0, strong1) #(100) nand2_1 (net_6, net_1, clk);
endmodule /* jtag__clockGen */
module jtag__capture_ctl(capture, phi2, sel, out, phi1);
input capture;
input phi2;
input sel;
output out;
input phi1;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_4;
scanChainFive__scanL foo(.in(net_2), .out(net_3));
not (strong0, strong1) #(100) inv_0 (net_1, capture);
not (strong0, strong1) #(100) inv_1 (out, net_4);
nand (strong0, strong1) #(100) nand3_0 (net_4, sel, net_3, phi1);
scanChainFive__scanP scanP_0(.in(phi2), .src(net_1), .drn(net_2));
endmodule /* jtag__capture_ctl */
module jtag__shift_ctl(phi1_fb, phi2_fb, sel, shift, phi1_out, phi2_out,
phi1_in, phi2_in);
input phi1_fb;
input phi2_fb;
input sel;
input shift;
output phi1_out;
output phi2_out;
input phi1_in;
input phi2_in;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_4, net_7;
jtag__clockGen clockGen_0(.clk(net_7), .phi1_fb(phi1_fb), .phi2_fb(phi2_fb),
.phi1_out(phi1_out), .phi2_out(phi2_out));
scanChainFive__scanL foo(.in(net_2), .out(net_3));
not (strong0, strong1) #(100) inv_0 (net_7, net_4);
not (strong0, strong1) #(100) inv_1 (net_1, shift);
nand (strong0, strong1) #(100) nand3_0 (net_4, sel, net_3, phi1_in);
scanChainFive__scanP scanP_0(.in(phi2_in), .src(net_1), .drn(net_2));
endmodule /* jtag__shift_ctl */
module jtag__update_ctl(sel, update, out, phi2);
input sel;
input update;
output out;
input phi2;
supply1 vdd;
supply0 gnd;
wire net_1;
not (strong0, strong1) #(100) inv_0 (out, net_1);
nand (strong0, strong1) #(100) nand3_0 (net_1, sel, update, phi2);
endmodule /* jtag__update_ctl */
module jtag__jtagIRControl(capture, phi1_fb, phi1_in, phi2_fb, phi2_in, shift,
update, phi1_out, phi2_out, read, write);
input capture;
input phi1_fb;
input phi1_in;
input phi2_fb;
input phi2_in;
input shift;
input update;
output phi1_out;
output phi2_out;
output read;
output write;
supply1 vdd;
supply0 gnd;
jtag__capture_ctl capture__0(.capture(capture), .phi2(phi2_in), .sel(vdd),
.out(read), .phi1(phi1_in));
jtag__shift_ctl shift_ct_0(.phi1_fb(phi1_fb), .phi2_fb(phi2_fb), .sel(vdd),
.shift(shift), .phi1_out(phi1_out), .phi2_out(phi2_out),
.phi1_in(phi1_in), .phi2_in(phi2_in));
jtag__update_ctl update_c_0(.sel(vdd), .update(update), .out(write),
.phi2(phi2_in));
endmodule /* jtag__jtagIRControl */
module redFour__NMOS_X_8_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule /* redFour__NMOS_X_8_Delay_100 */
module redFour__PMOS_X_4_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule /* redFour__PMOS_X_4_Delay_100 */
module jtag__tsinvBig(Din, en, enb, Dout);
input Din;
input en;
input enb;
output Dout;
supply1 vdd;
supply0 gnd;
wire net_13, net_14, net_22, net_23;
redFour__NMOS_X_8_Delay_100 NMOS_0(.g(Din), .d(net_13), .s(gnd));
redFour__NMOS_X_8_Delay_100 NMOS_1(.g(en), .d(Dout), .s(net_13));
redFour__NMOS_X_8_Delay_100 NMOS_2(.g(en), .d(Dout), .s(net_23));
redFour__NMOS_X_8_Delay_100 NMOS_3(.g(Din), .d(net_23), .s(gnd));
redFour__PMOS_X_4_Delay_100 PMOS_0(.g(enb), .d(Dout), .s(net_14));
redFour__PMOS_X_4_Delay_100 PMOS_1(.g(Din), .d(net_14), .s(vdd));
redFour__PMOS_X_4_Delay_100 PMOS_2(.g(enb), .d(Dout), .s(net_22));
redFour__PMOS_X_4_Delay_100 PMOS_3(.g(Din), .d(net_22), .s(vdd));
endmodule /* jtag__tsinvBig */
module jtag__jtagScanControl(TDI, capture, phi1_fb, phi1_in, phi2_fb, phi2_in,
sel, shift, update, TDO, phi1_out, phi2_out, read, write);
input TDI;
input capture;
input phi1_fb;
input phi1_in;
input phi2_fb;
input phi2_in;
input sel;
input shift;
input update;
output TDO;
output phi1_out;
output phi2_out;
output read;
output write;
supply1 vdd;
supply0 gnd;
wire net_0, net_2;
jtag__capture_ctl capture__0(.capture(capture), .phi2(phi2_in), .sel(sel),
.out(read), .phi1(phi1_in));
not (strong0, strong1) #(100) inv_0 (net_2, sel);
not (strong0, strong1) #(100) inv_1 (net_0, TDI);
jtag__shift_ctl shift_ct_0(.phi1_fb(phi1_fb), .phi2_fb(phi2_fb), .sel(sel),
.shift(shift), .phi1_out(phi1_out), .phi2_out(phi2_out),
.phi1_in(phi1_in), .phi2_in(phi2_in));
jtag__tsinvBig tsinvBig_0(.Din(net_0), .en(sel), .enb(net_2), .Dout(TDO));
jtag__update_ctl update_c_0(.sel(sel), .update(update), .out(write),
.phi2(phi2_in));
endmodule /* jtag__jtagScanControl */
module redFour__NMOS_X_5_667_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule /* redFour__NMOS_X_5_667_Delay_100 */
module redFour__PMOS_X_2_833_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule /* redFour__PMOS_X_2_833_Delay_100 */
module jtag__tsinv(Din, Dout, en, enb);
input Din;
input Dout;
input en;
input enb;
supply1 vdd;
supply0 gnd;
wire net_1, net_2;
redFour__NMOS_X_5_667_Delay_100 NMOS_0(.g(Din), .d(net_1), .s(gnd));
redFour__NMOS_X_5_667_Delay_100 NMOS_1(.g(en), .d(Dout), .s(net_1));
redFour__PMOS_X_2_833_Delay_100 PMOS_0(.g(Din), .d(net_2), .s(vdd));
redFour__PMOS_X_2_833_Delay_100 PMOS_1(.g(enb), .d(Dout), .s(net_2));
endmodule /* jtag__tsinv */
module jtag__mux2_phi2(Din0, Din1, phi2, sel, Dout);
input Din0;
input Din1;
input phi2;
input sel;
output Dout;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_5, net_6;
not (strong0, strong1) #(100) inv_0 (net_5, sel);
not (strong0, strong1) #(100) inv_1 (net_1, net_6);
not (strong0, strong1) #(100) inv_2 (Dout, net_3);
scanChainFive__scanL scanL_0(.in(net_2), .out(net_3));
scanChainFive__scanP scanP_0(.in(phi2), .src(net_1), .drn(net_2));
jtag__tsinv tsinv_0(.Din(Din0), .Dout(net_6), .en(net_5), .enb(sel));
jtag__tsinv tsinv_1(.Din(Din1), .Dout(net_6), .en(sel), .enb(net_5));
endmodule /* jtag__mux2_phi2 */
module jtag__scanAmp1w1648(in, out);
input in;
output out;
supply1 vdd;
supply0 gnd;
wire net_0;
tranif1 nmos_0(gnd, net_0, in);
tranif1 nmos_1(gnd, out, net_0);
tranif0 pmos_0(net_0, vdd, in);
tranif0 pmos_1(out, vdd, net_0);
endmodule /* jtag__scanAmp1w1648 */
module redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nand (strong0, strong1) #(100) nand2_0 (out, ina, inb);
endmodule /* redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1 */
module redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nand (strong0, strong1) #(100) nand2_0 (out, ina, inb);
endmodule /* redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 */
module redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nor (strong0, strong1) #(100) nor2_0 (out, ina, inb);
endmodule /* redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 */
module orangeTSMC180nm__wire_R_26m_100_C_0_025f(a);
input a;
supply0 gnd;
endmodule /* orangeTSMC180nm__wire_R_26m_100_C_0_025f */
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_100_C_0_025f wire_0(.a(a));
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 */
module jtag__o2a(inAa, inAb, inOb, out);
input inAa;
input inAb;
input inOb;
output out;
supply1 vdd;
supply0 gnd;
wire net_0;
nor (strong0, strong1) #(100) nor2_0 (net_0, inAa, inAb);
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_0(.ina(inOb), .inb(net_0), .out(out));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_0(.a(net_0));
endmodule /* jtag__o2a */
module orangeTSMC180nm__wire_R_26m_500_C_0_025f(a);
input a;
supply0 gnd;
endmodule /* orangeTSMC180nm__wire_R_26m_500_C_0_025f */
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_500_C_0_025f wire_0(.a(a));
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500 */
module jtag__slaveBit(din, phi2, slave);
input din;
input phi2;
output slave;
supply1 vdd;
supply0 gnd;
wire net_6, net_7;
not (strong0, strong1) #(100) inv_0 (slave, net_7);
scanChainFive__scanL scanL_0(.in(net_6), .out(net_7));
scanChainFive__scanP scanP_0(.in(phi2), .src(din), .drn(net_6));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500 wire180_0(.a(slave));
endmodule /* jtag__slaveBit */
module redFour__NMOS_X_1_667_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule /* redFour__NMOS_X_1_667_Delay_100 */
module orangeTSMC180nm__wire_R_26m_750_C_0_025f(a);
input a;
supply0 gnd;
endmodule /* orangeTSMC180nm__wire_R_26m_750_C_0_025f */
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_750_C_0_025f wire_0(.a(a));
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750 */
module orangeTSMC180nm__wire_R_26m_1000_C_0_025f(a);
input a;
supply0 gnd;
endmodule /* orangeTSMC180nm__wire_R_26m_1000_C_0_025f */
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_1000_C_0_025f wire_0(.a(a));
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000 */
module jtag__stateBit(next, phi1, phi2, rst, master, slave, slaveBar);
input next;
input phi1;
input phi2;
input rst;
output master;
output slave;
output slaveBar;
supply1 vdd;
supply0 gnd;
wire net_12, net_13, net_14, net_17;
redFour__NMOS_X_1_667_Delay_100 NMOS_0(.g(rst), .d(net_12), .s(gnd));
not (strong0, strong1) #(100) inv_0 (slave, slaveBar);
not (strong0, strong1) #(100) inv_1 (slaveBar, net_17);
not (strong0, strong1) #(100) inv_2 (master, net_13);
scanChainFive__scanL scanL_0(.in(net_12), .out(net_13));
scanChainFive__scanL scanL_1(.in(net_14), .out(net_17));
scanChainFive__scanP scanP_0(.in(phi1), .src(next), .drn(net_12));
scanChainFive__scanP scanP_1(.in(phi2), .src(net_13), .drn(net_14));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750 wire180_0(.a(master));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000 wire180_1(.a(slave));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500
wire180_2(.a(slaveBar));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_3(.a(next));
endmodule /* jtag__stateBit */
module redFour__PMOS_X_1_5_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule /* redFour__PMOS_X_1_5_Delay_100 */
module jtag__stateBitHI(next, phi1, phi2, rstb, master, slave, slaveBar);
input next;
input phi1;
input phi2;
input rstb;
output master;
output slave;
output slaveBar;
supply1 vdd;
supply0 gnd;
wire net_10, net_11, net_12, net_15;
redFour__PMOS_X_1_5_Delay_100 PMOS_0(.g(rstb), .d(net_12), .s(vdd));
not (strong0, strong1) #(100) inv_0 (slave, slaveBar);
not (strong0, strong1) #(100) inv_1 (slaveBar, net_15);
not (strong0, strong1) #(100) inv_2 (master, net_10);
scanChainFive__scanL scanL_0(.in(net_12), .out(net_10));
scanChainFive__scanL scanL_1(.in(net_11), .out(net_15));
scanChainFive__scanP scanP_0(.in(phi1), .src(next), .drn(net_12));
scanChainFive__scanP scanP_1(.in(phi2), .src(net_10), .drn(net_11));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000 wire180_0(.a(slave));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500
wire180_1(.a(slaveBar));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_2(.a(next));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750 wire180_3(.a(master));
endmodule /* jtag__stateBitHI */
module orangeTSMC180nm__wire_R_26m_675_C_0_025f(a);
input a;
supply0 gnd;
endmodule /* orangeTSMC180nm__wire_R_26m_675_C_0_025f */
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_675_C_0_025f wire_0(.a(a));
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675 */
module orangeTSMC180nm__wire_R_26m_1500_C_0_025f(a);
input a;
supply0 gnd;
endmodule /* orangeTSMC180nm__wire_R_26m_1500_C_0_025f */
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_1500_C_0_025f wire_0(.a(a));
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500 */
module jtag__tapCtlJKL(TMS, TRSTb, phi1, phi2, CapDR, CapIR, Idle, PauseDR,
PauseIR, Reset, Reset_s, SelDR, SelIR, ShftDR, ShftIR, UpdDR, UpdIR,
X1DR, X1IR, X2DR, X2IR);
input TMS;
input TRSTb;
input phi1;
input phi2;
output CapDR;
output CapIR;
output Idle;
output PauseDR;
output PauseIR;
output Reset;
output Reset_s;
output SelDR;
output SelIR;
output ShftDR;
output ShftIR;
output UpdDR;
output UpdIR;
output X1DR;
output X1IR;
output X2DR;
output X2IR;
supply1 vdd;
supply0 gnd;
wire net_0, net_2, net_4, net_6, net_12, net_13, net_14, net_15, net_16;
wire net_17, net_18, net_19, net_20, net_22, net_23, net_24, net_25, net_26;
wire net_28, net_29, net_31, net_32, net_34, net_40, net_43, net_44, net_48;
wire net_50, net_52, net_54, net_55, net_56, net_58, net_59, net_60, net_64;
wire net_67, net_68, net_70, net_71, net_72, net_74, net_75, net_76, net_79;
wire net_80, rst, stateBit_1_slave, stateBit_5_slaveBar, stateBit_6_slaveBar;
wire stateBit_9_slaveBar, stateBit_10_slaveBar, stateBit_11_slave;
wire stateBit_12_slave;
not (strong0, strong1) #(100) inv_0 (rst, TRSTb);
not (strong0, strong1) #(100) inv_1 (net_24, net_12);
redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1
nand2n_0(.ina(net_13), .inb(net_14), .out(net_0));
redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nand2n_1(.ina(net_15), .inb(net_16), .out(net_4));
redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nand2n_2(.ina(net_17), .inb(net_18), .out(net_2));
redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nand2n_3(.ina(net_19), .inb(net_20), .out(net_6));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_0(.ina(net_12), .inb(net_23), .out(net_22));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_1(.ina(net_24), .inb(net_26), .out(net_25));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_2(.ina(net_24), .inb(net_29), .out(net_28));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_3(.ina(net_24), .inb(net_32), .out(net_31));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_4(.ina(net_12), .inb(net_26), .out(net_34));
jtag__o2a o2a_0(.inAa(net_2), .inAb(net_43), .inOb(net_12), .out(net_40));
jtag__o2a o2a_1(.inAa(net_6), .inAb(net_0), .inOb(net_12), .out(net_44));
jtag__o2a o2a_2(.inAa(net_50), .inAb(net_0), .inOb(net_24), .out(net_48));
jtag__o2a o2a_3(.inAa(net_54), .inAb(net_55), .inOb(net_12), .out(net_52));
jtag__o2a o2a_4(.inAa(net_58), .inAb(net_59), .inOb(net_12), .out(net_56));
jtag__o2a o2a_5(.inAa(net_58), .inAb(net_43), .inOb(net_24), .out(net_60));
jtag__o2a o2a_6(.inAa(net_54), .inAb(net_67), .inOb(net_24), .out(net_64));
jtag__o2a o2a_7(.inAa(net_70), .inAb(net_71), .inOb(net_24), .out(net_68));
jtag__o2a o2a_8(.inAa(net_74), .inAb(net_75), .inOb(net_24), .out(net_72));
jtag__o2a o2a_9(.inAa(Reset_s), .inAb(net_79), .inOb(net_24), .out(net_76));
jtag__o2a o2a_10(.inAa(net_4), .inAb(net_67), .inOb(net_12), .out(net_80));
jtag__slaveBit slaveBit_0(.din(TMS), .phi2(phi2), .slave(net_12));
jtag__stateBit stateBit_0(.next(net_25), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(SelIR), .slave(net_79), .slaveBar(net_23));
jtag__stateBit stateBit_1(.next(net_48), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(SelDR), .slave(stateBit_1_slave), .slaveBar(net_26));
jtag__stateBit stateBit_2(.next(net_34), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(CapDR), .slave(net_75), .slaveBar(net_16));
jtag__stateBit stateBit_3(.next(net_22), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(CapIR), .slave(net_71), .slaveBar(net_18));
jtag__stateBit stateBit_4(.next(net_44), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(Idle), .slave(net_50), .slaveBar(net_20));
jtag__stateBit stateBit_5(.next(net_68), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(X1IR), .slave(net_58), .slaveBar(stateBit_5_slaveBar));
jtag__stateBit stateBit_6(.next(net_72), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(X1DR), .slave(net_54), .slaveBar(stateBit_6_slaveBar));
jtag__stateBit stateBit_7(.next(net_80), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(ShftDR), .slave(net_74), .slaveBar(net_15));
jtag__stateBit stateBit_8(.next(net_40), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(ShftIR), .slave(net_70), .slaveBar(net_17));
jtag__stateBit stateBit_9(.next(net_28), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(X2IR), .slave(net_43), .slaveBar(stateBit_9_slaveBar));
jtag__stateBit stateBit_10(.next(net_31), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(X2DR), .slave(net_67),
.slaveBar(stateBit_10_slaveBar));
jtag__stateBit stateBit_11(.next(net_64), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(UpdDR), .slave(stateBit_11_slave),
.slaveBar(net_14));
jtag__stateBit stateBit_12(.next(net_60), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(UpdIR), .slave(stateBit_12_slave),
.slaveBar(net_13));
jtag__stateBit stateBit_13(.next(net_56), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(PauseIR), .slave(net_59), .slaveBar(net_29));
jtag__stateBit stateBit_14(.next(net_52), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(PauseDR), .slave(net_55), .slaveBar(net_32));
jtag__stateBitHI stateBit_15(.next(net_76), .phi1(phi1), .phi2(phi2),
.rstb(TRSTb), .master(Reset), .slave(Reset_s), .slaveBar(net_19));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_0(.a(net_4));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_1(.a(net_2));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_2(.a(net_6));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675 wire180_3(.a(net_0));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500 wire180_4(.a(rst));
endmodule /* jtag__tapCtlJKL */
module jtag__jtagControl(TCK, TDI, TDIx, TMS, TRSTb, phi1_fb, phi2_fb, Cap,
ExTest, SelBS, SelDR, Shft, TDOb, Upd, phi1, phi2);
input TCK;
input TDI;
input TDIx;
input TMS;
input TRSTb;
input phi1_fb;
input phi2_fb;
output Cap;
output ExTest;
output SelBS;
output [12:0] SelDR;
output Shft;
output TDOb;
output Upd;
output phi1;
output phi2;
supply1 vdd;
supply0 gnd;
wire jtagScan_0_write, net_0, net_1, net_2, net_3, net_6, net_8, net_10;
wire net_33, net_35, net_37, net_38, net_41, net_47, net_48, net_50, net_51;
wire net_52, net_55, net_56, net_62, net_64, net_68, net_73, net_75, net_79;
wire net_97, net_99, net_103, net_128, tapCtlJK_0_Idle, tapCtlJK_0_PauseDR;
wire tapCtlJK_0_PauseIR, tapCtlJK_0_Reset, tapCtlJK_0_SelDR, tapCtlJK_0_SelIR;
wire tapCtlJK_0_X1DR, tapCtlJK_0_X2DR, tapCtlJK_0_X2IR;
wire [8:1] IR;
wire [8:1] IRb;
jtag__BR BR_0(.SDI(TDI), .phi1(net_68), .phi2(net_73), .read(net_99),
.SDO(net_97));
jtag__IR IR_0(.SDI(TDI), .phi1(net_79), .phi2(net_75), .read(net_55),
.reset(net_56), .write(net_103), .IR(IR[8:1]), .IRb(IRb[8:1]),
.SDO(net_128));
jtag__IRdecode IRdecode_0(.IR(IR[4:1]), .IRb(IRb[4:1]), .Bypass(net_41),
.ExTest(ExTest), .SamplePreload(net_47), .ScanPath(SelDR[12:0]));
redFour__PMOSwk_X_0_222_Delay_100 PMOSwk_0(.g(gnd), .d(TDIx), .s(vdd));
jtag__clockGen clockGen_0(.clk(TCK), .phi1_fb(phi1_fb), .phi2_fb(phi2_fb),
.phi1_out(net_10), .phi2_out(net_8));
not (strong0, strong1) #(100) inv_0 (net_0, net_3);
not (strong0, strong1) #(100) inv_1 (SelBS, net_48);
not (strong0, strong1) #(100) inv_2 (net_6, net_50);
not (strong0, strong1) #(100) inv_3 (Cap, net_37);
not (strong0, strong1) #(100) inv_4 (Shft, net_51);
not (strong0, strong1) #(100) inv_5 (net_51, net_52);
not (strong0, strong1) #(100) inv_6 (Upd, net_38);
jtag__jtagIRControl jtagIRCo_0(.capture(net_62), .phi1_fb(net_79),
.phi1_in(phi1), .phi2_fb(net_75), .phi2_in(phi2), .shift(net_2),
.update(net_64), .phi1_out(net_79), .phi2_out(net_75), .read(net_55),
.write(net_103));
jtag__jtagScanControl jtagScan_0(.TDI(net_97), .capture(Cap),
.phi1_fb(net_68), .phi1_in(phi1), .phi2_fb(net_73), .phi2_in(phi2),
.sel(net_41), .shift(Shft), .update(gnd), .TDO(TDIx), .phi1_out(net_68),
.phi2_out(net_73), .read(net_99), .write(jtagScan_0_write));
jtag__mux2_phi2 mux2_phi_0(.Din0(TDIx), .Din1(net_128), .phi2(phi2),
.sel(net_0), .Dout(net_50));
nand (strong0, strong1) #(100) nand2_0 (net_37, IR[8], net_35);
nand (strong0, strong1) #(100) nand2_1 (net_38, IR[7], net_33);
nor (strong0, strong1) #(100) nor2_0 (net_3, net_1, net_2);
nor (strong0, strong1) #(100) nor2_1 (net_48, net_47, ExTest);
jtag__scanAmp1w1648 scanAmp1_0(.in(net_6), .out(TDOb));
jtag__scanAmp1w1648 scanAmp1_1(.in(net_8), .out(phi2));
jtag__scanAmp1w1648 scanAmp1_2(.in(net_10), .out(phi1));
jtag__tapCtlJKL tapCtlJK_0(.TMS(TMS), .TRSTb(TRSTb), .phi1(phi1),
.phi2(phi2), .CapDR(net_35), .CapIR(net_62), .Idle(tapCtlJK_0_Idle),
.PauseDR(tapCtlJK_0_PauseDR), .PauseIR(tapCtlJK_0_PauseIR),
.Reset(tapCtlJK_0_Reset), .Reset_s(net_56), .SelDR(tapCtlJK_0_SelDR),
.SelIR(tapCtlJK_0_SelIR), .ShftDR(net_52), .ShftIR(net_2),
.UpdDR(net_33), .UpdIR(net_64), .X1DR(tapCtlJK_0_X1DR), .X1IR(net_1),
.X2DR(tapCtlJK_0_X2DR), .X2IR(tapCtlJK_0_X2IR));
endmodule /* jtag__jtagControl */
module jtag__JTAGamp(leaf, root);
input [8:1] leaf;
input [5:1] root;
supply1 vdd;
supply0 gnd;
jtag__scanAmp1w1648 toLeaf_5_(.in(root[5]), .out(leaf[5]));
jtag__scanAmp1w1648 toLeaf_4_(.in(root[4]), .out(leaf[4]));
jtag__scanAmp1w1648 toLeaf_3_(.in(root[3]), .out(leaf[3]));
jtag__scanAmp1w1648 toLeaf_2_(.in(root[2]), .out(leaf[2]));
jtag__scanAmp1w1648 toLeaf_1_(.in(root[1]), .out(leaf[1]));
endmodule /* jtag__JTAGamp */
module jtag__jtagScanCtlWBuf(TDI, cap, phi1, phi2, sel, shift, upd, TDO,
leaf);
input TDI;
input cap;
input phi1;
input phi2;
input sel;
input shift;
input upd;
output TDO;
input [8:1] leaf;
supply1 vdd;
supply0 gnd;
wire [5:2] a;
jtag__JTAGamp JTAGamp_0(.leaf(leaf[8:1]), .root({a[5], a[4], a[3], a[2],
TDI}));
jtag__jtagScanControl jtagScan_0(.TDI(leaf[8]), .capture(cap),
.phi1_fb(leaf[6]), .phi1_in(phi1), .phi2_fb(leaf[7]), .phi2_in(phi2),
.sel(sel), .shift(shift), .update(upd), .TDO(TDO), .phi1_out(a[3]),
.phi2_out(a[2]), .read(a[5]), .write(a[4]));
endmodule /* jtag__jtagScanCtlWBuf */
module jtag__jtagScanCtlGroup(TDI, capture, phi1_in, phi2_in, selBS, sel,
shift, update, TDO, BS, leaf0, leaf1, leaf2, leaf3, leaf4, leaf5, leaf6,
leaf7, leaf8, leaf9, leaf10, leaf11, leaf12);
input TDI;
input capture;
input phi1_in;
input phi2_in;
input selBS;
input [12:0] sel;
input shift;
input update;
output TDO;
input [8:1] BS;
input [8:1] leaf0;
input [8:1] leaf1;
input [8:1] leaf2;
input [8:1] leaf3;
input [8:1] leaf4;
input [8:1] leaf5;
input [8:1] leaf6;
input [8:1] leaf7;
input [8:1] leaf8;
input [8:1] leaf9;
input [8:1] leaf10;
input [8:1] leaf11;
input [8:1] leaf12;
supply1 vdd;
supply0 gnd;
jtag__jtagScanCtlWBuf jtagScan_1(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[0]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf0[8:1]));
jtag__jtagScanCtlWBuf jtagScan_2(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[10]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf10[8:1]));
jtag__jtagScanCtlWBuf jtagScan_3(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[12]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf12[8:1]));
jtag__jtagScanCtlWBuf jtagScan_4(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[11]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf11[8:1]));
jtag__jtagScanCtlWBuf jtagScan_5(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[9]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf9[8:1]));
jtag__jtagScanCtlWBuf jtagScan_6(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[8]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf8[8:1]));
jtag__jtagScanCtlWBuf jtagScan_7(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[6]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf6[8:1]));
jtag__jtagScanCtlWBuf jtagScan_8(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[5]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf5[8:1]));
jtag__jtagScanCtlWBuf jtagScan_9(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[4]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf4[8:1]));
jtag__jtagScanCtlWBuf jtagScan_10(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[3]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf3[8:1]));
jtag__jtagScanCtlWBuf jtagScan_11(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[2]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf2[8:1]));
jtag__jtagScanCtlWBuf jtagScan_12(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[1]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf1[8:1]));
jtag__jtagScanCtlWBuf jtagScan_13(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[7]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf7[8:1]));
jtag__jtagScanCtlWBuf jtagScan_16(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(selBS), .shift(shift), .upd(update), .TDO(TDO),
.leaf(BS[8:1]));
endmodule /* jtag__jtagScanCtlGroup */
module jtag__jtagCentral_LEIGNORE_1(TCK, TDI, TMS, TRSTb, ExTest, TDOb, BS,
leaf0, leaf1, leaf2, leaf3, leaf4, leaf5, leaf6, leaf7, leaf8, leaf9,
leaf10, leaf11, leaf12);
input TCK;
input TDI;
input TMS;
input TRSTb;
output ExTest;
output TDOb;
input [8:1] BS;
input [8:1] leaf0;
input [8:1] leaf1;
input [8:1] leaf2;
input [8:1] leaf3;
input [8:1] leaf4;
input [8:1] leaf5;
input [8:1] leaf6;
input [8:1] leaf7;
input [8:1] leaf8;
input [8:1] leaf9;
input [8:1] leaf10;
input [8:1] leaf11;
input [8:1] leaf12;
supply1 vdd;
supply0 gnd;
wire net_10, net_14, net_15, net_17, net_24, net_25, net_50;
wire [0:12] net_6;
jtag__jtagControl jtagCont_0(.TCK(TCK), .TDI(TDI), .TDIx(net_15), .TMS(TMS),
.TRSTb(TRSTb), .phi1_fb(net_24), .phi2_fb(net_10), .Cap(net_25),
.ExTest(ExTest), .SelBS(net_50), .SelDR({net_6[0], net_6[1], net_6[2],
net_6[3], net_6[4], net_6[5], net_6[6], net_6[7], net_6[8], net_6[9],
net_6[10], net_6[11], net_6[12]}), .Shft(net_17), .TDOb(TDOb),
.Upd(net_14), .phi1(net_24), .phi2(net_10));
jtag__jtagScanCtlGroup jtagScan_0(.TDI(TDI), .capture(net_25),
.phi1_in(net_24), .phi2_in(net_10), .selBS(net_50), .sel({net_6[0],
net_6[1], net_6[2], net_6[3], net_6[4], net_6[5], net_6[6], net_6[7],
net_6[8], net_6[9], net_6[10], net_6[11], net_6[12]}), .shift(net_17),
.update(net_14), .TDO(net_15), .BS(BS[8:1]), .leaf0(leaf0[8:1]),
.leaf1(leaf1[8:1]), .leaf2(leaf2[8:1]), .leaf3(leaf3[8:1]),
.leaf4(leaf4[8:1]), .leaf5(leaf5[8:1]), .leaf6(leaf6[8:1]),
.leaf7(leaf7[8:1]), .leaf8(leaf8[8:1]), .leaf9(leaf9[8:1]),
.leaf10(leaf10[8:1]), .leaf11(leaf11[8:1]), .leaf12(leaf12[8:1]));
endmodule /* jtag__jtagCentral_LEIGNORE_1 */
module scanFansFour__jtag_endcap(jtag);
input [8:4] jtag;
endmodule /* scanFansFour__jtag_endcap */
module testCell(TCK, TDI, TMS, TRSTb, TDOb);
input TCK;
input TDI;
input TMS;
input TRSTb;
output TDOb;
supply1 vdd;
supply0 gnd;
wire jtagCent_0_ExTest;
wire [4:0] net_5;
wire [4:0] net_6;
wire [4:0] net_7;
wire [4:0] net_8;
wire [4:0] net_9;
wire [4:0] net_10;
wire [4:0] net_11;
wire [4:0] net_12;
wire [4:0] net_13;
wire [4:0] net_14;
wire [4:0] net_15;
wire [4:0] net_16;
wire [4:0] net_17;
wire [4:0] net_18;
jtag__jtagCentral_LEIGNORE_1 jtagCent_0(.TCK(TCK), .TDI(TDI), .TMS(TMS),
.TRSTb(TRSTb), .ExTest(jtagCent_0_ExTest), .TDOb(TDOb), .BS({net_6[0],
net_6[1], net_6[2], net_6[3], net_6[4], net_6[2], net_6[1], net_6[0]}),
.leaf0({net_7[0], net_7[1], net_7[2], net_7[3], net_7[4], net_7[2],
net_7[1], net_7[0]}), .leaf1({net_18[0], net_18[1], net_18[2], net_18[3],
net_18[4], net_18[2], net_18[1], net_18[0]}), .leaf2({net_17[0],
net_17[1], net_17[2], net_17[3], net_17[4], net_17[2], net_17[1],
net_17[0]}), .leaf3({net_16[0], net_16[1], net_16[2], net_16[3],
net_16[4], net_16[2], net_16[1], net_16[0]}), .leaf4({net_15[0],
net_15[1], net_15[2], net_15[3], net_15[4], net_15[2], net_15[1],
net_15[0]}), .leaf5({net_14[0], net_14[1], net_14[2], net_14[3],
net_14[4], net_14[2], net_14[1], net_14[0]}), .leaf6({net_13[0],
net_13[1], net_13[2], net_13[3], net_13[4], net_13[2], net_13[1],
net_13[0]}), .leaf7({net_12[0], net_12[1], net_12[2], net_12[3],
net_12[4], net_12[2], net_12[1], net_12[0]}), .leaf8({net_11[0],
net_11[1], net_11[2], net_11[3], net_11[4], net_11[2], net_11[1],
net_11[0]}), .leaf9({net_10[0], net_10[1], net_10[2], net_10[3],
net_10[4], net_10[2], net_10[1], net_10[0]}), .leaf10({net_9[0],
net_9[1], net_9[2], net_9[3], net_9[4], net_9[2], net_9[1], net_9[0]}),
.leaf11({net_8[0], net_8[1], net_8[2], net_8[3], net_8[4], net_8[2],
net_8[1], net_8[0]}), .leaf12({net_5[0], net_5[1], net_5[2], net_5[3],
net_5[4], net_5[2], net_5[1], net_5[0]}));
scanFansFour__jtag_endcap jtag_end_0(.jtag({net_5[0], net_5[1], net_5[2],
net_5[4], net_5[3]}));
scanFansFour__jtag_endcap jtag_end_1(.jtag({net_8[0], net_8[1], net_8[2],
net_8[4], net_8[3]}));
scanFansFour__jtag_endcap jtag_end_2(.jtag({net_9[0], net_9[1], net_9[2],
net_9[4], net_9[3]}));
scanFansFour__jtag_endcap jtag_end_3(.jtag({net_10[0], net_10[1], net_10[2],
net_10[4], net_10[3]}));
scanFansFour__jtag_endcap jtag_end_4(.jtag({net_11[0], net_11[1], net_11[2],
net_11[4], net_11[3]}));
scanFansFour__jtag_endcap jtag_end_5(.jtag({net_12[0], net_12[1], net_12[2],
net_12[4], net_12[3]}));
scanFansFour__jtag_endcap jtag_end_6(.jtag({net_13[0], net_13[1], net_13[2],
net_13[4], net_13[3]}));
scanFansFour__jtag_endcap jtag_end_7(.jtag({net_14[0], net_14[1], net_14[2],
net_14[4], net_14[3]}));
scanFansFour__jtag_endcap jtag_end_8(.jtag({net_15[0], net_15[1], net_15[2],
net_15[4], net_15[3]}));
scanFansFour__jtag_endcap jtag_end_9(.jtag({net_16[0], net_16[1], net_16[2],
net_16[4], net_16[3]}));
scanFansFour__jtag_endcap jtag_end_10(.jtag({net_17[0], net_17[1], net_17[2],
net_17[4], net_17[3]}));
scanFansFour__jtag_endcap jtag_end_11(.jtag({net_18[0], net_18[1], net_18[2],
net_18[4], net_18[3]}));
scanFansFour__jtag_endcap jtag_end_12(.jtag({net_7[0], net_7[1], net_7[2],
net_7[4], net_7[3]}));
scanFansFour__jtag_endcap jtag_end_13(.jtag({net_6[0], net_6[1], net_6[2],
net_6[4], net_6[3]}));
endmodule /* testCell */
|
`timescale 1ns/1ps
`include "sata_defines.v"
module tb_cocotb (
//Parameters
//Registers/Wires
input rst, //reset
input clk,
output linkup, //link is finished
output sata_ready,
output sata_busy,
//input write_data_stb,
//input read_data_stb,
input [7:0] hard_drive_command,
input execute_command_stb,
input command_layer_reset,
input [15:0] sector_count,
input [47:0] sector_address,
output d2h_interrupt,
output d2h_notification,
output [3:0] d2h_port_mult,
output [7:0] d2h_device,
output [47:0] d2h_lba,
output [15:0] d2h_sector_count,
output [7:0] d2h_status,
output [7:0] d2h_error,
input u2h_write_enable,
output u2h_write_finished,
input [23:0] u2h_write_count,
input h2u_read_enable,
output [23:0] h2u_read_total_count,
output h2u_read_error,
output h2u_read_busy,
output u2h_read_error,
output transport_layer_ready,
output link_layer_ready,
output phy_ready,
input prim_scrambler_en,
input data_scrambler_en,
//Data Interface
output tx_set_elec_idle,
output rx_is_elec_idle,
output hd_ready,
input platform_ready,
//Debug
input hold,
input single_rdwr
);
reg [31:0] test_id = 0;
wire [31:0] tx_dout;
wire tx_is_k;
wire tx_comm_reset;
wire tx_comm_wake;
wire tx_elec_idle;
wire [31:0] rx_din;
wire [3:0] rx_is_k;
wire rx_elec_idle;
wire comm_init_detect;
wire comm_wake_detect;
reg r_rst;
reg r_write_data_stb;
reg r_read_data_stb;
reg r_command_layer_reset;
reg [15:0] r_sector_count;
reg [47:0] r_sector_address;
reg r_prim_scrambler_en;
reg r_data_scrambler_en;
reg r_platform_ready;
reg r_dout_count;
reg r_hold;
reg r_u2h_write_enable;
reg [23:0] r_u2h_write_count;
reg r_h2u_read_enable;
reg [7:0] r_hard_drive_command;
reg r_execute_command_stb;
wire hd_read_from_host;
wire [31:0] hd_data_from_host;
wire hd_write_to_host;
wire [31:0] hd_data_to_host;
wire [31:0] user_dout;
wire user_dout_ready;
wire user_dout_activate;
wire user_dout_stb;
wire [23:0] user_dout_size;
wire [31:0] user_din;
wire user_din_stb;
wire [1:0] user_din_ready;
wire [1:0] user_din_activate;
wire [23:0] user_din_size;
wire dma_activate_stb;
wire d2h_reg_stb;
wire pio_setup_stb;
wire d2h_data_stb;
wire dma_setup_stb;
wire set_device_bits_stb;
wire [7:0] d2h_fis;
wire i_rx_byte_is_aligned;
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
//always @ (*) r_write_data_stb = write_data_stb;
//always @ (*) r_read_data_stb = read_data_stb;
always @ (*) r_command_layer_reset= command_layer_reset;
always @ (*) r_sector_count = sector_count;
always @ (*) r_sector_address = sector_address;
always @ (*) r_prim_scrambler_en = prim_scrambler_en;
always @ (*) r_data_scrambler_en = data_scrambler_en;
always @ (*) r_platform_ready = platform_ready;
always @ (*) r_hold = hold;
always @ (*) r_u2h_write_enable = u2h_write_enable;
always @ (*) r_u2h_write_count = u2h_write_count;
always @ (*) r_h2u_read_enable = h2u_read_enable;
always @ (*) r_hard_drive_command = hard_drive_command;
always @ (*) r_execute_command_stb= execute_command_stb;
//Submodules
//User Generated Test Data
test_in user_2_hd_generator(
.clk (clk ),
.rst (rst ),
.enable (r_u2h_write_enable ),
.finished (u2h_write_finished ),
.write_count (r_u2h_write_count ),
.ready (user_din_ready ),
.activate (user_din_activate ),
.fifo_data (user_din ),
.fifo_size (user_din_size ),
.strobe (user_din_stb )
);
//Module to process data from Hard Drive to User
test_out hd_2_user_reader(
.clk (clk ),
.rst (rst ),
.busy (h2u_read_busy ),
.enable (r_h2u_read_enable ),
.error (h2u_read_error ),
.total_count (h2u_read_total_count ),
.ready (user_dout_ready ),
.activate (user_dout_activate ),
.size (user_dout_size ),
.data (user_dout ),
.strobe (user_dout_stb )
);
//hd data reader core
hd_data_reader user_2_hd_reader(
.clk (clk ),
.rst (rst ),
.enable (r_u2h_write_enable ),
.error (u2h_read_error ),
.hd_read_from_host (hd_read_from_host ),
.hd_data_from_host (hd_data_from_host )
);
//hd data writer core
hd_data_writer hd_2_user_generator(
.clk (clk ),
.rst (rst ),
.enable (r_h2u_read_enable ),
.data (hd_data_to_host ),
.strobe (hd_write_to_host )
);
sata_stack ss (
.rst (r_rst ), //reset
.clk (clk ), //clock used to run the stack
.command_layer_reset (r_command_layer_reset),
.platform_ready (platform_ready ), //the underlying physical platform is
.platform_error ( ),
.linkup (linkup ), //link is finished
.sata_ready (sata_ready ),
.sata_busy (sata_busy ),
.send_sync_escape (1'b0 ),
.hard_drive_error ( ),
.pio_data_ready ( ),
//Host to Device Control
// .write_data_stb (r_write_data_stb ),
// .read_data_stb (r_read_data_stb ),
.hard_drive_command (r_hard_drive_command ),
.execute_command_stb (r_execute_command_stb),
.user_features (16'h0000 ),
.sector_count (r_sector_count ),
.sector_address (r_sector_address ),
.dma_activate_stb (dma_activate_stb ),
.d2h_reg_stb (d2h_reg_stb ),
.pio_setup_stb (pio_setup_stb ),
.d2h_data_stb (d2h_data_stb ),
.dma_setup_stb (dma_setup_stb ),
.set_device_bits_stb (set_device_bits_stb ),
.d2h_fis (d2h_fis ),
.d2h_interrupt (d2h_interrupt ),
.d2h_notification (d2h_notification ),
.d2h_port_mult (d2h_port_mult ),
.d2h_device (d2h_device ),
.d2h_lba (d2h_lba ),
.d2h_sector_count (d2h_sector_count ),
.d2h_status (d2h_status ),
.d2h_error (d2h_error ),
//Data from host to the hard drive path
.data_in_clk (clk ),
.data_in_clk_valid (1'b1 ),
.user_din (user_din ), //User Data Here
.user_din_stb (user_din_stb ), //Strobe Each Data word in here
.user_din_ready (user_din_ready ), //Using PPFIFO Ready Signal
.user_din_activate (user_din_activate ), //Activate PPFIFO Channel
.user_din_size (user_din_size ), //Find the size of the data to write to the device
//Data from hard drive to host path
.data_out_clk (clk ),
.data_out_clk_valid (1'b1 ),
.user_dout (user_dout ),
.user_dout_ready (user_dout_ready ),
.user_dout_activate (user_dout_activate ),
.user_dout_stb (user_dout_stb ),
.user_dout_size (user_dout_size ),
.transport_layer_ready (transport_layer_ready),
.link_layer_ready (link_layer_ready ),
.phy_ready (phy_ready ),
.phy_error (1'b0 ),
.tx_dout (tx_dout ),
.tx_is_k (tx_is_k ),
.tx_comm_reset (tx_comm_reset ),
.tx_comm_wake (tx_comm_wake ),
.tx_elec_idle (tx_elec_idle ),
.tx_oob_complete (1'b1 ),
.rx_din (rx_din ),
.rx_is_k (rx_is_k ),
.rx_elec_idle (rx_elec_idle ),
.rx_byte_is_aligned (i_rx_byte_is_aligned ),
.comm_init_detect (comm_init_detect ),
.comm_wake_detect (comm_wake_detect ),
//.prim_scrambler_en (r_prim_scrambler_en ),
.prim_scrambler_en (1'b1 ),
//.data_scrambler_en (r_data_scrambler_en )
.data_scrambler_en (1'b1 )
);
faux_sata_hd fshd (
.rst (r_rst ),
.clk (clk ),
.tx_dout (rx_din ),
.tx_is_k (rx_is_k ),
.rx_din (tx_dout ),
.rx_is_k ({3'b000, tx_is_k} ),
.rx_is_elec_idle (tx_elec_idle ),
.rx_byte_is_aligned (i_rx_byte_is_aligned ),
.comm_reset_detect (tx_comm_reset ),
.comm_wake_detect (tx_comm_wake ),
.tx_comm_reset (comm_init_detect ),
.tx_comm_wake (comm_wake_detect ),
.hd_ready (hd_ready ),
// .phy_ready (phy_ready ),
//.dbg_data_scrambler_en (r_data_scrambler_en ),
.dbg_data_scrambler_en (1'b1 ),
.dbg_hold (r_hold ),
.dbg_ll_write_start (1'b0 ),
.dbg_ll_write_data (32'h0 ),
.dbg_ll_write_size (0 ),
.dbg_ll_write_hold (1'b0 ),
.dbg_ll_write_abort (1'b0 ),
.dbg_ll_read_ready (1'b0 ),
.dbg_t_en (1'b0 ),
.dbg_send_reg_stb (1'b0 ),
.dbg_send_dma_act_stb (1'b0 ),
.dbg_send_data_stb (1'b0 ),
.dbg_send_pio_stb (1'b0 ),
.dbg_send_dev_bits_stb (1'b0 ),
.dbg_pio_transfer_count(16'h0000 ),
.dbg_pio_direction (1'b0 ),
.dbg_pio_e_status (8'h00 ),
.dbg_d2h_interrupt (1'b0 ),
.dbg_d2h_notification (1'b0 ),
.dbg_d2h_status (8'b0 ),
.dbg_d2h_error (8'b0 ),
.dbg_d2h_port_mult (4'b0000 ),
.dbg_d2h_device (8'h00 ),
.dbg_d2h_lba (48'h000000000000 ),
.dbg_d2h_sector_count (16'h0000 ),
.dbg_cl_if_data (32'b0 ),
.dbg_cl_if_ready (1'b0 ),
.dbg_cl_if_size (24'h0 ),
.dbg_cl_of_ready (2'b0 ),
.dbg_cl_of_size (24'h0 ),
.hd_read_from_host (hd_read_from_host ),
.hd_data_from_host (hd_data_from_host ),
.hd_write_to_host (hd_write_to_host ),
.hd_data_to_host (hd_data_to_host )
);
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
/*
Copyright (c) 2014-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream ethernet frame receiver (AXI in, Ethernet frame out)
*/
module eth_axis_rx #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
/*
* Status signals
*/
output wire busy,
output wire error_header_early_termination
);
parameter CYCLE_COUNT = (14+KEEP_WIDTH-1)/KEEP_WIDTH;
parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
parameter OFFSET = 14 % KEEP_WIDTH;
// bus width assertions
initial begin
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end
/*
Ethernet frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype 2 octets
This module receives an Ethernet frame on an AXI stream interface, decodes
and strips the headers, then produces the header fields in parallel along
with the payload in a separate AXI stream.
*/
reg read_eth_header_reg = 1'b1, read_eth_header_next;
reg read_eth_payload_reg = 1'b0, read_eth_payload_next;
reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next;
reg flush_save;
reg transfer_in_save;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
reg busy_reg = 1'b0;
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
reg [DATA_WIDTH-1:0] save_axis_tdata_reg = 64'd0;
reg [KEEP_WIDTH-1:0] save_axis_tkeep_reg = 8'd0;
reg save_axis_tlast_reg = 1'b0;
reg save_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] shift_axis_tdata;
reg [KEEP_WIDTH-1:0] shift_axis_tkeep;
reg shift_axis_tvalid;
reg shift_axis_tlast;
reg shift_axis_tuser;
reg shift_axis_input_tready;
reg shift_axis_extra_cycle_reg = 1'b0;
// internal datapath
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
reg m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
always @* begin
if (OFFSET == 0) begin
// passthrough if no overlap
shift_axis_tdata = s_axis_tdata;
shift_axis_tkeep = s_axis_tkeep;
shift_axis_tvalid = s_axis_tvalid;
shift_axis_tlast = s_axis_tlast;
shift_axis_tuser = s_axis_tuser;
shift_axis_input_tready = 1'b1;
end else if (shift_axis_extra_cycle_reg) begin
shift_axis_tdata = {s_axis_tdata, save_axis_tdata_reg} >> (OFFSET*8);
shift_axis_tkeep = {{KEEP_WIDTH{1'b0}}, save_axis_tkeep_reg} >> OFFSET;
shift_axis_tvalid = 1'b1;
shift_axis_tlast = save_axis_tlast_reg;
shift_axis_tuser = save_axis_tuser_reg;
shift_axis_input_tready = flush_save;
end else begin
shift_axis_tdata = {s_axis_tdata, save_axis_tdata_reg} >> (OFFSET*8);
shift_axis_tkeep = {s_axis_tkeep, save_axis_tkeep_reg} >> OFFSET;
shift_axis_tvalid = s_axis_tvalid;
shift_axis_tlast = (s_axis_tlast && ((s_axis_tkeep & ({KEEP_WIDTH{1'b1}} << OFFSET)) == 0));
shift_axis_tuser = (s_axis_tuser && ((s_axis_tkeep & ({KEEP_WIDTH{1'b1}} << OFFSET)) == 0));
shift_axis_input_tready = !(s_axis_tlast && s_axis_tready && s_axis_tvalid);
end
end
always @* begin
read_eth_header_next = read_eth_header_reg;
read_eth_payload_next = read_eth_payload_reg;
ptr_next = ptr_reg;
s_axis_tready_next = m_eth_payload_axis_tready_int_early && shift_axis_input_tready && (!m_eth_hdr_valid || m_eth_hdr_ready);
flush_save = 1'b0;
transfer_in_save = 1'b0;
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
error_header_early_termination_next = 1'b0;
m_eth_payload_axis_tdata_int = shift_axis_tdata;
m_eth_payload_axis_tkeep_int = shift_axis_tkeep;
m_eth_payload_axis_tvalid_int = 1'b0;
m_eth_payload_axis_tlast_int = shift_axis_tlast;
m_eth_payload_axis_tuser_int = shift_axis_tuser;
if ((s_axis_tready && s_axis_tvalid) || (m_eth_payload_axis_tready_int_reg && shift_axis_extra_cycle_reg)) begin
transfer_in_save = 1'b1;
if (read_eth_header_reg) begin
// word transfer in - store it
ptr_next = ptr_reg + 1;
`define _HEADER_FIELD_(offset, field) \
if (ptr_reg == offset/KEEP_WIDTH && (!KEEP_ENABLE || s_axis_tkeep[offset%KEEP_WIDTH])) begin \
field = s_axis_tdata[(offset%KEEP_WIDTH)*8 +: 8]; \
end
`_HEADER_FIELD_(0, m_eth_dest_mac_next[5*8 +: 8])
`_HEADER_FIELD_(1, m_eth_dest_mac_next[4*8 +: 8])
`_HEADER_FIELD_(2, m_eth_dest_mac_next[3*8 +: 8])
`_HEADER_FIELD_(3, m_eth_dest_mac_next[2*8 +: 8])
`_HEADER_FIELD_(4, m_eth_dest_mac_next[1*8 +: 8])
`_HEADER_FIELD_(5, m_eth_dest_mac_next[0*8 +: 8])
`_HEADER_FIELD_(6, m_eth_src_mac_next[5*8 +: 8])
`_HEADER_FIELD_(7, m_eth_src_mac_next[4*8 +: 8])
`_HEADER_FIELD_(8, m_eth_src_mac_next[3*8 +: 8])
`_HEADER_FIELD_(9, m_eth_src_mac_next[2*8 +: 8])
`_HEADER_FIELD_(10, m_eth_src_mac_next[1*8 +: 8])
`_HEADER_FIELD_(11, m_eth_src_mac_next[0*8 +: 8])
`_HEADER_FIELD_(12, m_eth_type_next[1*8 +: 8])
`_HEADER_FIELD_(13, m_eth_type_next[0*8 +: 8])
if (ptr_reg == 13/KEEP_WIDTH && (!KEEP_ENABLE || s_axis_tkeep[13%KEEP_WIDTH])) begin
if (!shift_axis_tlast) begin
m_eth_hdr_valid_next = 1'b1;
read_eth_header_next = 1'b0;
read_eth_payload_next = 1'b1;
end
end
`undef _HEADER_FIELD_
end
if (read_eth_payload_reg) begin
// transfer payload
m_eth_payload_axis_tdata_int = shift_axis_tdata;
m_eth_payload_axis_tkeep_int = shift_axis_tkeep;
m_eth_payload_axis_tvalid_int = 1'b1;
m_eth_payload_axis_tlast_int = shift_axis_tlast;
m_eth_payload_axis_tuser_int = shift_axis_tuser;
end
if (shift_axis_tlast) begin
if (read_eth_header_next) begin
// don't have the whole header
error_header_early_termination_next = 1'b1;
end
flush_save = 1'b1;
ptr_next = 1'b0;
read_eth_header_next = 1'b1;
read_eth_payload_next = 1'b0;
end
end
end
always @(posedge clk) begin
read_eth_header_reg <= read_eth_header_next;
read_eth_payload_reg <= read_eth_payload_next;
ptr_reg <= ptr_next;
s_axis_tready_reg <= s_axis_tready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
error_header_early_termination_reg <= error_header_early_termination_next;
busy_reg <= (read_eth_payload_next || ptr_next != 0);
if (transfer_in_save) begin
save_axis_tdata_reg <= s_axis_tdata;
save_axis_tkeep_reg <= s_axis_tkeep;
save_axis_tuser_reg <= s_axis_tuser;
end
if (flush_save) begin
save_axis_tlast_reg <= 1'b0;
shift_axis_extra_cycle_reg <= 1'b0;
end else if (transfer_in_save) begin
save_axis_tlast_reg <= s_axis_tlast;
shift_axis_extra_cycle_reg <= OFFSET ? s_axis_tlast && ((s_axis_tkeep & ({KEEP_WIDTH{1'b1}} << OFFSET)) != 0) : 1'b0;
end
if (rst) begin
read_eth_header_reg <= 1'b1;
read_eth_payload_reg <= 1'b0;
ptr_reg <= 0;
s_axis_tready_reg <= 1'b0;
m_eth_hdr_valid_reg <= 1'b0;
save_axis_tlast_reg <= 1'b0;
shift_axis_extra_cycle_reg <= 1'b0;
busy_reg <= 1'b0;
error_header_early_termination_reg <= 1'b0;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg m_eth_payload_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg temp_m_eth_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_eth_payload_int_to_output;
reg store_eth_payload_int_to_temp;
reg store_eth_payload_axis_temp_to_output;
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? m_eth_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_eth_payload_int_to_output = 1'b0;
store_eth_payload_int_to_temp = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_eth_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_eth_payload_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_eth_payload_axis_tvalid_reg <= 1'b0;
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
end
// datapath
if (store_eth_payload_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_eth_payload_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_eth_payload_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__EDFXBP_BEHAVIORAL_PP_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_edf_p_no_pg/sky130_fd_sc_hs__u_edf_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_hs__u_edf_p_no_pg u_edf_p_no_pg0 (buf_Q , D_delayed, CLK_delayed, DE_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXBP_BEHAVIORAL_PP_V
|
`include "e200_defines.v"
module tb_top();
reg clk;
reg lfextclk;
reg rst_n;
wire hfclkrst;
wire hfclk = clk & (~hfclkrst);
`define CPU_TOP u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.u_e200_cpu_top
`define EXU `CPU_TOP.u_e200_cpu.u_e200_core.u_e200_exu
`define ITCM `CPU_TOP.u_e200_srams.u_e200_itcm_ram.u_e200_itcm_gnrl_ram.u_sirv_sim_ram
`define PC_WRITE_TOHOST `E200_PC_SIZE'h80000086
`define PC_EXT_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000a6
`define PC_SFT_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000be
`define PC_TMR_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000d6
`define PC_AFTER_SETMTVEC `E200_PC_SIZE'h80000148
wire [`E200_XLEN-1:0] x3 = `EXU.u_e200_exu_regfile.rf_r[3];
wire [`E200_PC_SIZE-1:0] pc = `EXU.u_e200_exu_commit.alu_cmt_i_pc;
reg [31:0] pc_write_to_host_cnt;
reg [31:0] pc_write_to_host_cycle;
reg [31:0] valid_ir_cycle;
reg [31:0] cycle_count;
reg pc_write_to_host_flag;
always @(posedge hfclk or negedge rst_n)
begin
if(rst_n == 1'b0) begin
pc_write_to_host_cnt <= 32'b0;
pc_write_to_host_flag <= 1'b0;
pc_write_to_host_cycle <= 32'b0;
end
else if (pc == `PC_WRITE_TOHOST) begin
pc_write_to_host_cnt <= pc_write_to_host_cnt + 1'b1;
pc_write_to_host_flag <= 1'b1;
if (pc_write_to_host_flag == 1'b0) begin
pc_write_to_host_cycle <= cycle_count;
end
end
end
always @(posedge hfclk or negedge rst_n)
begin
if(rst_n == 1'b0) begin
cycle_count <= 32'b0;
end
else begin
cycle_count <= cycle_count + 1'b1;
end
end
wire i_valid = `EXU.i_valid;
wire i_ready = `EXU.i_ready;
always @(posedge hfclk or negedge rst_n)
begin
if(rst_n == 1'b0) begin
valid_ir_cycle <= 32'b0;
end
else if(i_valid & i_ready & (pc_write_to_host_flag == 1'b0)) begin
valid_ir_cycle <= valid_ir_cycle + 1'b1;
end
end
// Randomly force the external interrupt
`define EXT_IRQ u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.plic_ext_irq
`define SFT_IRQ u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.clint_sft_irq
`define TMR_IRQ u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.clint_tmr_irq
`define U_CPU u_e200_fpga_soc_top.u_e200_subsys_top.u_e200_subsys_main.u_e200_cpu_top.u_e200_cpu
`define ITCM_BUS_ERR `U_CPU.u_e200_itcm_ctrl.chk_icb_rsp_err
`define ITCM_BUS_READ `U_CPU.u_e200_itcm_ctrl.e2_icb_read_r
`define STATUS_MIE `U_CPU.u_e200_core.u_e200_exu.u_e200_exu_commit.u_e200_exu_excp.status_mie_r
wire stop_assert_irq = (pc_write_to_host_cnt > 32);
reg tb_itcm_bus_err;
reg tb_ext_irq;
reg tb_tmr_irq;
reg tb_sft_irq;
initial begin
tb_ext_irq = 1'b0;
tb_tmr_irq = 1'b0;
tb_sft_irq = 1'b0;
end
`ifdef ENABLE_TB_FORCE
initial begin
tb_itcm_bus_err = 1'b0;
#100
@(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program
forever begin
repeat ($urandom_range(1, 20)) @(posedge clk) tb_itcm_bus_err = 1'b0; // Wait random times
repeat ($urandom_range(1, 200)) @(posedge clk) tb_itcm_bus_err = 1'b1; // Wait random times
if(stop_assert_irq) begin
break;
end
end
end
initial begin
force `EXT_IRQ = tb_ext_irq;
force `SFT_IRQ = tb_sft_irq;
force `TMR_IRQ = tb_tmr_irq;
// We force the bus-error only when:
// It is in common code, not in exception code, by checking MIE bit
// It is in read operation, not write, otherwise the test cannot recover
force `ITCM_BUS_ERR = tb_itcm_bus_err
& `STATUS_MIE
& `ITCM_BUS_READ
;
end
initial begin
#100
@(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program
forever begin
repeat ($urandom_range(1, 200)) @(posedge clk) tb_ext_irq = 1'b0; // Wait random times
tb_ext_irq = 1'b1; // assert the irq
@((pc == `PC_EXT_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values
tb_ext_irq = 1'b0;
if(stop_assert_irq) begin
break;
end
end
end
initial begin
#100
@(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program
forever begin
repeat ($urandom_range(1, 200)) @(posedge clk) tb_sft_irq = 1'b0; // Wait random times
tb_sft_irq = 1'b1; // assert the irq
@((pc == `PC_SFT_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values
tb_sft_irq = 1'b0;
if(stop_assert_irq) begin
break;
end
end
end
initial begin
#100
@(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program
forever begin
repeat ($urandom_range(1, 200)) @(posedge clk) tb_tmr_irq = 1'b0; // Wait random times
tb_tmr_irq = 1'b1; // assert the irq
@((pc == `PC_TMR_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values
tb_tmr_irq = 1'b0;
if(stop_assert_irq) begin
break;
end
end
end
`endif
reg[8*300:1] testcase;
integer dumpwave;
initial begin
$display("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
if($value$plusargs("TESTCASE=%s",testcase))begin
$display("TESTCASE=%s",testcase);
end
pc_write_to_host_flag <=0;
clk <=0;
lfextclk <=0;
rst_n <=0;
#120 rst_n <=1;
@(pc_write_to_host_cnt == 32'd8) #10 rst_n <=1;
`ifdef ENABLE_TB_FORCE
@((~tb_tmr_irq) & (~tb_sft_irq) & (~tb_ext_irq)) #10 rst_n <=1;// Wait the interrupt to complete
`endif
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~ Test Result Summary ~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~TESTCASE: %s ~~~~~~~~~~~~~", testcase);
$display("~~~~~~~~~~~~~~Total cycle_count value: %d ~~~~~~~~~~~~~", cycle_count);
$display("~~~~~~~~~~The valid Instruction Count: %d ~~~~~~~~~~~~~", valid_ir_cycle);
$display("~~~~~The test ending reached at cycle: %d ~~~~~~~~~~~~~", pc_write_to_host_cycle);
$display("~~~~~~~~~~~~~~~The final x3 Reg value: %d ~~~~~~~~~~~~~", x3);
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
if (x3 == 1) begin
$display("~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ ##### ## #### #### ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ # # # # # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ # # # # #### #### ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ ##### ###### # #~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ # # # # # # #~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ # # # #### #### ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
end
else begin
$display("~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~###### ## # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~# # # # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~##### # # # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~# ###### # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~# # # # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~# # # # ######~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
end
#10
$finish;
end
initial begin
#10000000
$display("Time Out !!!");
$finish;
end
always
begin
#2 clk <= ~clk;
end
always
begin
#33 lfextclk <= ~lfextclk;
end
//initial begin
// $value$plusargs("DUMPWAVE=%d",dumpwave);
// if(dumpwave != 0)begin
// // To add your waveform generation function
// end
//end
integer i;
reg [7:0] itcm_mem [0:(`E200_ITCM_RAM_DP*8)-1];
initial begin
$readmemh({testcase, ".verilog"}, itcm_mem);
for (i=0;i<(`E200_ITCM_RAM_DP);i=i+1) begin
`ITCM.mem_r[i][00+7:00] = itcm_mem[i*8+0];
`ITCM.mem_r[i][08+7:08] = itcm_mem[i*8+1];
`ITCM.mem_r[i][16+7:16] = itcm_mem[i*8+2];
`ITCM.mem_r[i][24+7:24] = itcm_mem[i*8+3];
`ITCM.mem_r[i][32+7:32] = itcm_mem[i*8+4];
`ITCM.mem_r[i][40+7:40] = itcm_mem[i*8+5];
`ITCM.mem_r[i][48+7:48] = itcm_mem[i*8+6];
`ITCM.mem_r[i][56+7:56] = itcm_mem[i*8+7];
end
$display("ITCM 0x00: %h", `ITCM.mem_r[8'h00]);
$display("ITCM 0x01: %h", `ITCM.mem_r[8'h01]);
$display("ITCM 0x02: %h", `ITCM.mem_r[8'h02]);
$display("ITCM 0x03: %h", `ITCM.mem_r[8'h03]);
$display("ITCM 0x04: %h", `ITCM.mem_r[8'h04]);
$display("ITCM 0x05: %h", `ITCM.mem_r[8'h05]);
$display("ITCM 0x06: %h", `ITCM.mem_r[8'h06]);
$display("ITCM 0x07: %h", `ITCM.mem_r[8'h07]);
$display("ITCM 0x16: %h", `ITCM.mem_r[8'h16]);
$display("ITCM 0x20: %h", `ITCM.mem_r[8'h20]);
end
wire jtag_TDI = 1'b0;
wire jtag_TDO;
wire jtag_TCK = 1'b0;
wire jtag_TMS = 1'b0;
wire jtag_TRST = 1'b0;
wire jtag_DRV_TDO = 1'b0;
e200_fpga_soc_top u_e200_fpga_soc_top(
.hfclk(hfclk),
.hfclkrst(hfclkrst),
.io_pads_jtag_TCK_i_ival (jtag_TCK),
.io_pads_jtag_TCK_o_oval (),
.io_pads_jtag_TCK_o_oe (),
.io_pads_jtag_TCK_o_ie (),
.io_pads_jtag_TCK_o_pue (),
.io_pads_jtag_TCK_o_ds (),
.io_pads_jtag_TMS_i_ival (jtag_TMS),
.io_pads_jtag_TMS_o_oval (),
.io_pads_jtag_TMS_o_oe (),
.io_pads_jtag_TMS_o_ie (),
.io_pads_jtag_TMS_o_pue (),
.io_pads_jtag_TMS_o_ds (),
.io_pads_jtag_TDI_i_ival (jtag_TDI),
.io_pads_jtag_TDI_o_oval (),
.io_pads_jtag_TDI_o_oe (),
.io_pads_jtag_TDI_o_ie (),
.io_pads_jtag_TDI_o_pue (),
.io_pads_jtag_TDI_o_ds (),
.io_pads_jtag_TDO_i_ival (1'b1),
.io_pads_jtag_TDO_o_oval (jtag_TDO),
.io_pads_jtag_TDO_o_oe (),
.io_pads_jtag_TDO_o_ie (),
.io_pads_jtag_TDO_o_pue (),
.io_pads_jtag_TDO_o_ds (),
.io_pads_jtag_TRST_n_i_ival (jtag_TRST),
.io_pads_jtag_TRST_n_o_oval (),
.io_pads_jtag_TRST_n_o_oe (),
.io_pads_jtag_TRST_n_o_ie (),
.io_pads_jtag_TRST_n_o_pue (),
.io_pads_jtag_TRST_n_o_ds (),
.io_pads_gpio_0_i_ival (1'b0),
.io_pads_gpio_0_o_oval (),
.io_pads_gpio_0_o_oe (),
.io_pads_gpio_0_o_ie (),
.io_pads_gpio_0_o_pue (),
.io_pads_gpio_0_o_ds (),
.io_pads_gpio_1_i_ival (1'b0),
.io_pads_gpio_1_o_oval (),
.io_pads_gpio_1_o_oe (),
.io_pads_gpio_1_o_ie (),
.io_pads_gpio_1_o_pue (),
.io_pads_gpio_1_o_ds (),
.io_pads_gpio_2_i_ival (1'b0),
.io_pads_gpio_2_o_oval (),
.io_pads_gpio_2_o_oe (),
.io_pads_gpio_2_o_ie (),
.io_pads_gpio_2_o_pue (),
.io_pads_gpio_2_o_ds (),
.io_pads_gpio_3_i_ival (1'b0),
.io_pads_gpio_3_o_oval (),
.io_pads_gpio_3_o_oe (),
.io_pads_gpio_3_o_ie (),
.io_pads_gpio_3_o_pue (),
.io_pads_gpio_3_o_ds (),
.io_pads_gpio_4_i_ival (1'b0),
.io_pads_gpio_4_o_oval (),
.io_pads_gpio_4_o_oe (),
.io_pads_gpio_4_o_ie (),
.io_pads_gpio_4_o_pue (),
.io_pads_gpio_4_o_ds (),
.io_pads_gpio_5_i_ival (1'b0),
.io_pads_gpio_5_o_oval (),
.io_pads_gpio_5_o_oe (),
.io_pads_gpio_5_o_ie (),
.io_pads_gpio_5_o_pue (),
.io_pads_gpio_5_o_ds (),
.io_pads_gpio_6_i_ival (1'b0),
.io_pads_gpio_6_o_oval (),
.io_pads_gpio_6_o_oe (),
.io_pads_gpio_6_o_ie (),
.io_pads_gpio_6_o_pue (),
.io_pads_gpio_6_o_ds (),
.io_pads_gpio_7_i_ival (1'b0),
.io_pads_gpio_7_o_oval (),
.io_pads_gpio_7_o_oe (),
.io_pads_gpio_7_o_ie (),
.io_pads_gpio_7_o_pue (),
.io_pads_gpio_7_o_ds (),
.io_pads_gpio_8_i_ival (1'b0),
.io_pads_gpio_8_o_oval (),
.io_pads_gpio_8_o_oe (),
.io_pads_gpio_8_o_ie (),
.io_pads_gpio_8_o_pue (),
.io_pads_gpio_8_o_ds (),
.io_pads_gpio_9_i_ival (1'b0),
.io_pads_gpio_9_o_oval (),
.io_pads_gpio_9_o_oe (),
.io_pads_gpio_9_o_ie (),
.io_pads_gpio_9_o_pue (),
.io_pads_gpio_9_o_ds (),
.io_pads_gpio_10_i_ival (1'b0),
.io_pads_gpio_10_o_oval (),
.io_pads_gpio_10_o_oe (),
.io_pads_gpio_10_o_ie (),
.io_pads_gpio_10_o_pue (),
.io_pads_gpio_10_o_ds (),
.io_pads_gpio_11_i_ival (1'b0),
.io_pads_gpio_11_o_oval (),
.io_pads_gpio_11_o_oe (),
.io_pads_gpio_11_o_ie (),
.io_pads_gpio_11_o_pue (),
.io_pads_gpio_11_o_ds (),
.io_pads_gpio_12_i_ival (1'b0),
.io_pads_gpio_12_o_oval (),
.io_pads_gpio_12_o_oe (),
.io_pads_gpio_12_o_ie (),
.io_pads_gpio_12_o_pue (),
.io_pads_gpio_12_o_ds (),
.io_pads_gpio_13_i_ival (1'b0),
.io_pads_gpio_13_o_oval (),
.io_pads_gpio_13_o_oe (),
.io_pads_gpio_13_o_ie (),
.io_pads_gpio_13_o_pue (),
.io_pads_gpio_13_o_ds (),
.io_pads_gpio_14_i_ival (1'b0),
.io_pads_gpio_14_o_oval (),
.io_pads_gpio_14_o_oe (),
.io_pads_gpio_14_o_ie (),
.io_pads_gpio_14_o_pue (),
.io_pads_gpio_14_o_ds (),
.io_pads_gpio_15_i_ival (1'b0),
.io_pads_gpio_15_o_oval (),
.io_pads_gpio_15_o_oe (),
.io_pads_gpio_15_o_ie (),
.io_pads_gpio_15_o_pue (),
.io_pads_gpio_15_o_ds (),
.io_pads_gpio_16_i_ival (1'b0),
.io_pads_gpio_16_o_oval (),
.io_pads_gpio_16_o_oe (),
.io_pads_gpio_16_o_ie (),
.io_pads_gpio_16_o_pue (),
.io_pads_gpio_16_o_ds (),
.io_pads_gpio_17_i_ival (1'b0),
.io_pads_gpio_17_o_oval (),
.io_pads_gpio_17_o_oe (),
.io_pads_gpio_17_o_ie (),
.io_pads_gpio_17_o_pue (),
.io_pads_gpio_17_o_ds (),
.io_pads_gpio_18_i_ival (1'b0),
.io_pads_gpio_18_o_oval (),
.io_pads_gpio_18_o_oe (),
.io_pads_gpio_18_o_ie (),
.io_pads_gpio_18_o_pue (),
.io_pads_gpio_18_o_ds (),
.io_pads_gpio_19_i_ival (1'b0),
.io_pads_gpio_19_o_oval (),
.io_pads_gpio_19_o_oe (),
.io_pads_gpio_19_o_ie (),
.io_pads_gpio_19_o_pue (),
.io_pads_gpio_19_o_ds (),
.io_pads_gpio_20_i_ival (1'b0),
.io_pads_gpio_20_o_oval (),
.io_pads_gpio_20_o_oe (),
.io_pads_gpio_20_o_ie (),
.io_pads_gpio_20_o_pue (),
.io_pads_gpio_20_o_ds (),
.io_pads_gpio_21_i_ival (1'b0),
.io_pads_gpio_21_o_oval (),
.io_pads_gpio_21_o_oe (),
.io_pads_gpio_21_o_ie (),
.io_pads_gpio_21_o_pue (),
.io_pads_gpio_21_o_ds (),
.io_pads_gpio_22_i_ival (1'b0),
.io_pads_gpio_22_o_oval (),
.io_pads_gpio_22_o_oe (),
.io_pads_gpio_22_o_ie (),
.io_pads_gpio_22_o_pue (),
.io_pads_gpio_22_o_ds (),
.io_pads_gpio_23_i_ival (1'b0),
.io_pads_gpio_23_o_oval (),
.io_pads_gpio_23_o_oe (),
.io_pads_gpio_23_o_ie (),
.io_pads_gpio_23_o_pue (),
.io_pads_gpio_23_o_ds (),
.io_pads_gpio_24_i_ival (1'b0),
.io_pads_gpio_24_o_oval (),
.io_pads_gpio_24_o_oe (),
.io_pads_gpio_24_o_ie (),
.io_pads_gpio_24_o_pue (),
.io_pads_gpio_24_o_ds (),
.io_pads_gpio_25_i_ival (1'b0),
.io_pads_gpio_25_o_oval (),
.io_pads_gpio_25_o_oe (),
.io_pads_gpio_25_o_ie (),
.io_pads_gpio_25_o_pue (),
.io_pads_gpio_25_o_ds (),
.io_pads_gpio_26_i_ival (1'b0),
.io_pads_gpio_26_o_oval (),
.io_pads_gpio_26_o_oe (),
.io_pads_gpio_26_o_ie (),
.io_pads_gpio_26_o_pue (),
.io_pads_gpio_26_o_ds (),
.io_pads_gpio_27_i_ival (1'b0),
.io_pads_gpio_27_o_oval (),
.io_pads_gpio_27_o_oe (),
.io_pads_gpio_27_o_ie (),
.io_pads_gpio_27_o_pue (),
.io_pads_gpio_27_o_ds (),
.io_pads_gpio_28_i_ival (1'b0),
.io_pads_gpio_28_o_oval (),
.io_pads_gpio_28_o_oe (),
.io_pads_gpio_28_o_ie (),
.io_pads_gpio_28_o_pue (),
.io_pads_gpio_28_o_ds (),
.io_pads_gpio_29_i_ival (1'b0),
.io_pads_gpio_29_o_oval (),
.io_pads_gpio_29_o_oe (),
.io_pads_gpio_29_o_ie (),
.io_pads_gpio_29_o_pue (),
.io_pads_gpio_29_o_ds (),
.io_pads_gpio_30_i_ival (1'b0),
.io_pads_gpio_30_o_oval (),
.io_pads_gpio_30_o_oe (),
.io_pads_gpio_30_o_ie (),
.io_pads_gpio_30_o_pue (),
.io_pads_gpio_30_o_ds (),
.io_pads_gpio_31_i_ival (1'b0),
.io_pads_gpio_31_o_oval (),
.io_pads_gpio_31_o_oe (),
.io_pads_gpio_31_o_ie (),
.io_pads_gpio_31_o_pue (),
.io_pads_gpio_31_o_ds (),
.io_pads_qspi_sck_i_ival (1'b1),
.io_pads_qspi_sck_o_oval (),
.io_pads_qspi_sck_o_oe (),
.io_pads_qspi_sck_o_ie (),
.io_pads_qspi_sck_o_pue (),
.io_pads_qspi_sck_o_ds (),
.io_pads_qspi_dq_0_i_ival (1'b1),
.io_pads_qspi_dq_0_o_oval (),
.io_pads_qspi_dq_0_o_oe (),
.io_pads_qspi_dq_0_o_ie (),
.io_pads_qspi_dq_0_o_pue (),
.io_pads_qspi_dq_0_o_ds (),
.io_pads_qspi_dq_1_i_ival (1'b1),
.io_pads_qspi_dq_1_o_oval (),
.io_pads_qspi_dq_1_o_oe (),
.io_pads_qspi_dq_1_o_ie (),
.io_pads_qspi_dq_1_o_pue (),
.io_pads_qspi_dq_1_o_ds (),
.io_pads_qspi_dq_2_i_ival (1'b1),
.io_pads_qspi_dq_2_o_oval (),
.io_pads_qspi_dq_2_o_oe (),
.io_pads_qspi_dq_2_o_ie (),
.io_pads_qspi_dq_2_o_pue (),
.io_pads_qspi_dq_2_o_ds (),
.io_pads_qspi_dq_3_i_ival (1'b1),
.io_pads_qspi_dq_3_o_oval (),
.io_pads_qspi_dq_3_o_oe (),
.io_pads_qspi_dq_3_o_ie (),
.io_pads_qspi_dq_3_o_pue (),
.io_pads_qspi_dq_3_o_ds (),
.io_pads_qspi_cs_0_i_ival (1'b1),
.io_pads_qspi_cs_0_o_oval (),
.io_pads_qspi_cs_0_o_oe (),
.io_pads_qspi_cs_0_o_ie (),
.io_pads_qspi_cs_0_o_pue (),
.io_pads_qspi_cs_0_o_ds (),
.io_pads_aon_erst_n_i_ival (rst_n),//This is the real reset, active low
.io_pads_aon_erst_n_o_oval (),
.io_pads_aon_erst_n_o_oe (),
.io_pads_aon_erst_n_o_ie (),
.io_pads_aon_erst_n_o_pue (),
.io_pads_aon_erst_n_o_ds (),
.io_pads_aon_lfextclk_i_ival (lfextclk),
.io_pads_aon_lfextclk_o_oval (),
.io_pads_aon_lfextclk_o_oe (),
.io_pads_aon_lfextclk_o_ie (),
.io_pads_aon_lfextclk_o_pue (),
.io_pads_aon_lfextclk_o_ds (),
.io_pads_aon_pmu_dwakeup_n_i_ival (1'b1),
.io_pads_aon_pmu_dwakeup_n_o_oval (),
.io_pads_aon_pmu_dwakeup_n_o_oe (),
.io_pads_aon_pmu_dwakeup_n_o_ie (),
.io_pads_aon_pmu_dwakeup_n_o_pue (),
.io_pads_aon_pmu_dwakeup_n_o_ds (),
.io_pads_aon_pmu_vddpaden_i_ival (1'b1),
.io_pads_aon_pmu_vddpaden_o_oval (),
.io_pads_aon_pmu_vddpaden_o_oe (),
.io_pads_aon_pmu_vddpaden_o_ie (),
.io_pads_aon_pmu_vddpaden_o_pue (),
.io_pads_aon_pmu_vddpaden_o_ds ()
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_byp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_byp
// Description: This block includes the muxes for the bypassing for all
// 3 register outputs. It also includes the pipeline registers
// for the output of the ALU. All other operands come from
// outside the bypass block. Rs1_data chooses between the normal
// bypassing paths and the PC. Rs2_data chooses between the normal
// bypassing paths and the immediate.
*/
//FPGA_SYN enables all FPGA related modifications
`ifdef FPGA_SYN
`define FPGA_SYN_CLK_EN
`define FPGA_SYN_CLK_DFF
`endif
module sparc_exu_byp
( /*AUTOARG*/
// Outputs
so, byp_alu_rs1_data_e, byp_alu_rs2_data_e_l, byp_alu_rs2_data_e,
exu_lsu_rs3_data_e, exu_spu_rs3_data_e, exu_lsu_rs2_data_e,
byp_alu_rcc_data_e, byp_irf_rd_data_w, exu_tlu_wsr_data_m,
byp_irf_rd_data_w2, byp_ecc_rs3_data_e, byp_ecc_rcc_data_e,
byp_ecl_rs2_31_e, byp_ecl_rs1_31_e, byp_ecl_rs1_63_e,
byp_ecl_rs1_2_0_e, byp_ecl_rs2_3_0_e, byp_ecc_rs1_synd_d,
byp_ecc_rs2_synd_d, byp_ecc_rs3_synd_d,
// Inputs
rclk, se, si, sehold, ecl_byp_rs1_mux2_sel_e,
ecl_byp_rs1_mux2_sel_rf, ecl_byp_rs1_mux2_sel_ld,
ecl_byp_rs1_mux2_sel_usemux1, ecl_byp_rs1_mux1_sel_m,
ecl_byp_rs1_mux1_sel_w, ecl_byp_rs1_mux1_sel_w2,
ecl_byp_rs1_mux1_sel_other, ecl_byp_rcc_mux2_sel_e,
ecl_byp_rcc_mux2_sel_rf, ecl_byp_rcc_mux2_sel_ld,
ecl_byp_rcc_mux2_sel_usemux1, ecl_byp_rcc_mux1_sel_m,
ecl_byp_rcc_mux1_sel_w, ecl_byp_rcc_mux1_sel_w2,
ecl_byp_rcc_mux1_sel_other, ecl_byp_rs2_mux2_sel_e,
ecl_byp_rs2_mux2_sel_rf, ecl_byp_rs2_mux2_sel_ld,
ecl_byp_rs2_mux2_sel_usemux1, ecl_byp_rs2_mux1_sel_m,
ecl_byp_rs2_mux1_sel_w, ecl_byp_rs2_mux1_sel_w2,
ecl_byp_rs2_mux1_sel_other, ecl_byp_rs3_mux2_sel_e,
ecl_byp_rs3_mux2_sel_rf, ecl_byp_rs3_mux2_sel_ld,
ecl_byp_rs3_mux2_sel_usemux1, ecl_byp_rs3_mux1_sel_m,
ecl_byp_rs3_mux1_sel_w, ecl_byp_rs3_mux1_sel_w2,
ecl_byp_rs3_mux1_sel_other, ecl_byp_rs3h_mux2_sel_e,
ecl_byp_rs3h_mux2_sel_rf, ecl_byp_rs3h_mux2_sel_ld,
ecl_byp_rs3h_mux2_sel_usemux1, ecl_byp_rs3h_mux1_sel_m,
ecl_byp_rs3h_mux1_sel_w, ecl_byp_rs3h_mux1_sel_w2,
ecl_byp_rs3h_mux1_sel_other, ecl_byp_rs1_longmux_sel_g2,
ecl_byp_rs1_longmux_sel_w2, ecl_byp_rs1_longmux_sel_ldxa,
ecl_byp_rs2_longmux_sel_g2, ecl_byp_rs2_longmux_sel_w2,
ecl_byp_rs2_longmux_sel_ldxa, ecl_byp_rs3_longmux_sel_g2,
ecl_byp_rs3_longmux_sel_w2, ecl_byp_rs3_longmux_sel_ldxa,
ecl_byp_rs3h_longmux_sel_g2, ecl_byp_rs3h_longmux_sel_w2,
ecl_byp_rs3h_longmux_sel_ldxa, ecl_byp_sel_load_m,
ecl_byp_sel_pipe_m, ecl_byp_sel_ecc_m, ecl_byp_sel_muldiv_g,
ecl_byp_sel_load_g, ecl_byp_sel_restore_g, ecl_byp_std_e_l,
ecl_byp_ldxa_g, alu_byp_rd_data_e, ifu_exu_imm_data_d,
irf_byp_rs1_data_d_l, irf_byp_rs2_data_d_l, irf_byp_rs3_data_d_l,
irf_byp_rs3h_data_d_l, lsu_exu_dfill_data_g, lsu_exu_ldxa_data_g,
div_byp_muldivout_g, ecc_byp_ecc_result_m, ecl_byp_ecc_mask_m_l,
ifu_exu_pc_d, ecl_byp_3lsb_m, ecl_byp_restore_m,
ecl_byp_sel_restore_m, ecl_byp_eclpr_e, div_byp_yreg_e,
ifu_exu_pcver_e, tlu_exu_rsr_data_m, ffu_exu_rsr_data_m,
ecl_byp_sel_yreg_e, ecl_byp_sel_eclpr_e, ecl_byp_sel_ifusr_e,
ecl_byp_sel_alu_e, ecl_byp_sel_ifex_m, ecl_byp_sel_ffusr_m,
ecl_byp_sel_tlusr_m
);
input rclk;
input se; // scan enable
input si;
input sehold;
input ecl_byp_rs1_mux2_sel_e;// select lines for bypass muxes for rs1
input ecl_byp_rs1_mux2_sel_rf;
input ecl_byp_rs1_mux2_sel_ld;
input ecl_byp_rs1_mux2_sel_usemux1;
input ecl_byp_rs1_mux1_sel_m;
input ecl_byp_rs1_mux1_sel_w;
input ecl_byp_rs1_mux1_sel_w2;
input ecl_byp_rs1_mux1_sel_other;
input ecl_byp_rcc_mux2_sel_e;// select lines for bypass muxes for reg condition code
input ecl_byp_rcc_mux2_sel_rf;
input ecl_byp_rcc_mux2_sel_ld;
input ecl_byp_rcc_mux2_sel_usemux1;
input ecl_byp_rcc_mux1_sel_m;
input ecl_byp_rcc_mux1_sel_w;
input ecl_byp_rcc_mux1_sel_w2;
input ecl_byp_rcc_mux1_sel_other;
input ecl_byp_rs2_mux2_sel_e;// select lines for bypass muxes for rs2
input ecl_byp_rs2_mux2_sel_rf;
input ecl_byp_rs2_mux2_sel_ld;
input ecl_byp_rs2_mux2_sel_usemux1;
input ecl_byp_rs2_mux1_sel_m;
input ecl_byp_rs2_mux1_sel_w;
input ecl_byp_rs2_mux1_sel_w2;
input ecl_byp_rs2_mux1_sel_other;
input ecl_byp_rs3_mux2_sel_e;// select lines for bypass muxes for rs3
input ecl_byp_rs3_mux2_sel_rf;
input ecl_byp_rs3_mux2_sel_ld;
input ecl_byp_rs3_mux2_sel_usemux1;
input ecl_byp_rs3_mux1_sel_m;
input ecl_byp_rs3_mux1_sel_w;
input ecl_byp_rs3_mux1_sel_w2;
input ecl_byp_rs3_mux1_sel_other;
input ecl_byp_rs3h_mux2_sel_e;// select lines for bypass muxes for rs3 double
input ecl_byp_rs3h_mux2_sel_rf;
input ecl_byp_rs3h_mux2_sel_ld;
input ecl_byp_rs3h_mux2_sel_usemux1;
input ecl_byp_rs3h_mux1_sel_m;
input ecl_byp_rs3h_mux1_sel_w;
input ecl_byp_rs3h_mux1_sel_w2;
input ecl_byp_rs3h_mux1_sel_other;
input ecl_byp_rs1_longmux_sel_g2;
input ecl_byp_rs1_longmux_sel_w2;
input ecl_byp_rs1_longmux_sel_ldxa;
input ecl_byp_rs2_longmux_sel_g2;
input ecl_byp_rs2_longmux_sel_w2;
input ecl_byp_rs2_longmux_sel_ldxa;
input ecl_byp_rs3_longmux_sel_g2;
input ecl_byp_rs3_longmux_sel_w2;
input ecl_byp_rs3_longmux_sel_ldxa;
input ecl_byp_rs3h_longmux_sel_g2;
input ecl_byp_rs3h_longmux_sel_w2;
input ecl_byp_rs3h_longmux_sel_ldxa;
input ecl_byp_sel_load_m; // m instruction uses load in w1 port
input ecl_byp_sel_pipe_m;
input ecl_byp_sel_ecc_m;
input ecl_byp_sel_muldiv_g;
input ecl_byp_sel_load_g;
input ecl_byp_sel_restore_g;
input ecl_byp_std_e_l;
input ecl_byp_ldxa_g;
input [63:0] alu_byp_rd_data_e; // data from alu for bypass
input [31:0] ifu_exu_imm_data_d; // immediate
input [71:0] irf_byp_rs1_data_d_l; // RF rs1_data
input [71:0] irf_byp_rs2_data_d_l; // RF rs2_data
input [71:0] irf_byp_rs3_data_d_l; // RF rs3_data
input [31:0] irf_byp_rs3h_data_d_l;// RF rs3 double data
input [63:0] lsu_exu_dfill_data_g; // load data
input [63:0] lsu_exu_ldxa_data_g;
input [63:0] div_byp_muldivout_g;
input [63:0] ecc_byp_ecc_result_m;// result from ecc
input [7:0] ecl_byp_ecc_mask_m_l;
input [47:0] ifu_exu_pc_d;
input [2:0] ecl_byp_3lsb_m;
input ecl_byp_restore_m;
input ecl_byp_sel_restore_m;
input [7:0] ecl_byp_eclpr_e;
input [31:0] div_byp_yreg_e;
input [63:0] ifu_exu_pcver_e;
input [63:0] tlu_exu_rsr_data_m;
input [63:0] ffu_exu_rsr_data_m;
input ecl_byp_sel_yreg_e;
input ecl_byp_sel_eclpr_e;
input ecl_byp_sel_ifusr_e;
input ecl_byp_sel_alu_e;
input ecl_byp_sel_ifex_m;
input ecl_byp_sel_ffusr_m;
input ecl_byp_sel_tlusr_m;
output so;
output [63:0] byp_alu_rs1_data_e; // rs1_data operand for alu
output [63:0] byp_alu_rs2_data_e_l; // rs2_data operand for alu
output [63:0] byp_alu_rs2_data_e;
output [63:0] exu_lsu_rs3_data_e; // rs3_data operand for lsu
output [63:0] exu_spu_rs3_data_e;// rs3 data for spu
output [63:0] exu_lsu_rs2_data_e;
output [63:0] byp_alu_rcc_data_e;// data for reg condition codes
output [71:0] byp_irf_rd_data_w;
output [63:0] exu_tlu_wsr_data_m; // data for writeback
output [71:0] byp_irf_rd_data_w2;
output [63:0] byp_ecc_rs3_data_e;
output [63:0] byp_ecc_rcc_data_e;
output byp_ecl_rs2_31_e;
output byp_ecl_rs1_31_e;
output byp_ecl_rs1_63_e;
output [2:0] byp_ecl_rs1_2_0_e;
output [3:0] byp_ecl_rs2_3_0_e;
output [7:0] byp_ecc_rs1_synd_d;
output [7:0] byp_ecc_rs2_synd_d;
output [7:0] byp_ecc_rs3_synd_d;
wire clk;
wire sehold_clk;
wire [63:0] irf_byp_rs1_data_d; // RF rs1_data
wire [63:0] irf_byp_rs2_data_d; // RF rs2_data
wire [63:0] irf_byp_rs3_data_d; // RF rs3_data
wire [31:0] irf_byp_rs3h_data_d; // RF rs3_data double
wire [63:0] byp_alu_rs1_data_d; // rs1 operand for alu
wire [63:0] byp_alu_rcc_data_d; // rcc operand for alu
wire [63:0] byp_alu_rs2_data_d; // rs2_data operand for alu
wire [63:0] rd_data_e; // e stage rd_data
wire [63:0] rd_data_m; // m stage non-load rd_data
wire [63:0] full_rd_data_m; // m stage non-load rd_data including rdsr
wire [63:0] rd_data_g;
wire [63:0] byp_irf_rd_data_m;// m stage rd_data
wire [63:0] rs1_data_btwn_mux; // intermediate net for rs1_data muxes
wire [63:0] rcc_data_btwn_mux; // intermediate net for rs1_data muxes
wire [63:0] rs2_data_btwn_mux; // intermediate net for rs2_data muxes
wire [63:0] rs3_data_btwn_mux; // intermediate net for rs3_data muxes
wire [31:0] rs3h_data_btwn_mux; // intermediate net for rs3h_data muxes
wire [63:0] rs3_data_d;
wire [63:0] rs3_data_e;
wire [31:0] rs3h_data_d;
wire [31:0] rs3h_data_e;
wire [63:0] restore_rd_data;
wire [63:0] restore_rd_data_next;
wire [63:0] dfill_data_g;
wire [63:0] dfill_data_g2;
wire ecl_byp_std_e;
wire [7:0] rd_synd_w_l;
wire [7:0] rd_synd_w2_l;
assign clk = rclk;
`ifdef FPGA_SYN_CLK_EN
`else
clken_buf irf_write_clkbuf (
.rclk (clk),
.enb_l (sehold),
.tmb_l (~se),
.clk (sehold_clk)
) ;
`endif
assign byp_ecc_rs1_synd_d[7:0] = ~irf_byp_rs1_data_d_l[71:64];
assign byp_ecc_rs2_synd_d[7:0] = ~irf_byp_rs2_data_d_l[71:64];
assign byp_ecc_rs3_synd_d[7:0] = ~irf_byp_rs3_data_d_l[71:64];
/////////////////////////////////////////
// Load returns go straight into a flop after mux with ldxa_data
/////////////////////////////////////////
dp_mux2es #(64) dfill_data_mux (.dout(dfill_data_g[63:0]),
.in0(lsu_exu_dfill_data_g[63:0]),
.in1(lsu_exu_ldxa_data_g[63:0]),
.sel(ecl_byp_ldxa_g));
dff_s #(64) dfill_data_dff (.din(dfill_data_g[63:0]), .clk(clk),
.q(dfill_data_g2[63:0]), .se(se), .si(), .so());
//////////////////////////////////////////////////
// RD of PR or SR
//////////////////////////////////////////////////
// Mux outputs for rdpr/rdsr
mux4ds #(64) ifu_exu_sr_mux(.dout(rd_data_e[63:0]),
.in0({32'b0, div_byp_yreg_e[31:0]}),
.in1({56'b0, ecl_byp_eclpr_e[7:0]}),
.in2(ifu_exu_pcver_e[63:0]),
.in3(alu_byp_rd_data_e[63:0]),
.sel0(ecl_byp_sel_yreg_e),
.sel1(ecl_byp_sel_eclpr_e),
.sel2(ecl_byp_sel_ifusr_e),
.sel3(ecl_byp_sel_alu_e));
// mux in the rdsr data from ffu and tlu
mux3ds #(64) sr_out_mux(.dout(full_rd_data_m[63:0]),
.in0({rd_data_m[63:3], ecl_byp_3lsb_m[2:0]}),
.in1(ffu_exu_rsr_data_m[63:0]),
.in2(tlu_exu_rsr_data_m[63:0]),
.sel0(ecl_byp_sel_ifex_m),
.sel1(ecl_byp_sel_ffusr_m),
.sel2(ecl_byp_sel_tlusr_m));
// Pipeline registers for rd_data
dff_s #(64) dff_rd_data_e2m(.din(rd_data_e[63:0]), .clk(clk), .q(rd_data_m[63:0]),
.se(se), .si(), .so());
dp_buffer #(64) wsr_data_buf(.dout(exu_tlu_wsr_data_m[63:0]), .in(rd_data_m[63:0]));
// Flop for storing result from restore
dp_mux2es #(64) restore_buf_mux(.dout(restore_rd_data_next[63:0]),
.in0(restore_rd_data[63:0]),
.in1(rd_data_m[63:0]),
.sel(ecl_byp_restore_m));
dff_s #(64) dff_restore_buf(.din(restore_rd_data_next[63:0]),
.q(restore_rd_data[63:0]), .clk(clk),
.se(se), .si(), .so());
// Mux for rd_data_m between ALU and load data and ECC result and restore result
mux4ds #(64) rd_data_m_mux(.dout(byp_irf_rd_data_m[63:0]),
.in0(full_rd_data_m[63:0]),
.in1(dfill_data_g2[63:0]),
.in2(ecc_byp_ecc_result_m[63:0]),
.in3(restore_rd_data[63:0]),
.sel0(ecl_byp_sel_pipe_m),
.sel1(ecl_byp_sel_load_m),
.sel2(ecl_byp_sel_ecc_m),
.sel3(ecl_byp_sel_restore_m));
`ifdef FPGA_SYN_CLK_DFF
dffe_s #(64) dff_rd_data_m2w(.din(byp_irf_rd_data_m[63:0]), .en (~(sehold)), .clk(clk), .q(byp_irf_rd_data_w[63:0]),
.se(se), .si(), .so());
`else
dff_s #(64) dff_rd_data_m2w(.din(byp_irf_rd_data_m[63:0]), .clk(sehold_clk), .q(byp_irf_rd_data_w[63:0]),
.se(se), .si(), .so());
`endif
// W2 flop
`ifdef FPGA_SYN_CLK_DFF
dffe_s #(64) dff_rd_data_g2w(.din(rd_data_g[63:0]), .en (~(sehold)), .clk(clk), .q(byp_irf_rd_data_w2[63:0]),
.se(se), .si(), .so());
`else
dff_s #(64) dff_rd_data_g2w(.din(rd_data_g[63:0]), .clk(sehold_clk), .q(byp_irf_rd_data_w2[63:0]),
.se(se), .si(), .so());
`endif
// D-E pipeline registers for rs_data
dff_s #(64) rs1_data_dff(.din(byp_alu_rs1_data_d[63:0]), .clk(clk),
.q(byp_alu_rs1_data_e[63:0]), .se(se),
.si(), .so());
dff_s #(64) rs2_data_dff(.din(byp_alu_rs2_data_d[63:0]), .clk(clk),
.q(byp_alu_rs2_data_e[63:0]), .se(se),
.si(), .so());
assign byp_alu_rs2_data_e_l[63:0] = ~byp_alu_rs2_data_e[63:0];
assign byp_ecl_rs2_31_e = byp_alu_rs2_data_e[31];
assign byp_ecl_rs1_63_e = byp_alu_rs1_data_e[63];
assign byp_ecl_rs1_31_e = byp_alu_rs1_data_e[31];
assign byp_ecl_rs1_2_0_e[2:0] = byp_alu_rs1_data_e[2:0];
assign byp_ecl_rs2_3_0_e[3:0] = byp_alu_rs2_data_e[3:0];
dff_s #(64) rs3_data_dff(.din(rs3_data_d[63:0]), .clk(clk),
.q(rs3_data_e[63:0]), .se(se),
.si(), .so());
dff_s #(32) rs3h_data_dff(.din(rs3h_data_d[31:0]), .clk(clk),
.q(rs3h_data_e[31:0]), .se(se),
.si(), .so());
dff_s #(64) rcc_data_dff(.din(byp_alu_rcc_data_d[63:0]), .clk(clk),
.q(byp_alu_rcc_data_e[63:0]), .se(se),
.si(), .so());
assign ecl_byp_std_e = ~ecl_byp_std_e_l;
dp_mux2es #(64) rs2_data_out_mux(.dout(exu_lsu_rs2_data_e[63:0]),
.in0(byp_alu_rs2_data_e[63:0]),
.in1(rs3_data_e[63:0]),
.sel(ecl_byp_std_e));
dp_mux2es #(64) rs3_data_out_mux(.dout(exu_lsu_rs3_data_e[63:0]),
.in0(rs3_data_e[63:0]),
.in1({32'b0,rs3h_data_e[31:0]}),
.sel(ecl_byp_std_e));
// part of rs3 goes to spu. Buffer off to help timing/loading
assign exu_spu_rs3_data_e[63:0] = rs3_data_e[63:0];
assign byp_ecc_rs3_data_e[63:0] = rs3_data_e[63:0];
assign byp_ecc_rcc_data_e[63:0] = byp_alu_rcc_data_e[63:0];
// Forwarding Muxes
// Select lines are as follows:
// mux1[M, W, W2, OTHER(optional)]
// mux2[mux1, RF, E, LD]
assign irf_byp_rs1_data_d[63:0] = ~irf_byp_rs1_data_d_l[63:0];
assign irf_byp_rs2_data_d[63:0] = ~irf_byp_rs2_data_d_l[63:0];
assign irf_byp_rs3_data_d[63:0] = ~irf_byp_rs3_data_d_l[63:0];
assign irf_byp_rs3h_data_d[31:0] = ~irf_byp_rs3h_data_d_l[31:0];
/* -----\/----- EXCLUDED -----\/-----
// the w2 bypass path is either what is being written that cycle
// or the load result that will be written next cycle.
-----/\----- EXCLUDED -----/\----- */
wire [63:0] rs1_data_w2;
wire [63:0] rs2_data_w2;
wire [63:0] rs3_data_w2;
wire [31:0] rs3h_data_w2;
mux3ds #(64) rs1_w2_mux(.dout(rs1_data_w2[63:0]),
.in0(byp_irf_rd_data_w2[63:0]),
.in1(dfill_data_g2[63:0]),
.in2(lsu_exu_ldxa_data_g[63:0]),
.sel0(ecl_byp_rs1_longmux_sel_w2),
.sel1(ecl_byp_rs1_longmux_sel_g2),
.sel2(ecl_byp_rs1_longmux_sel_ldxa));
mux3ds #(64) rs2_w2_mux(.dout(rs2_data_w2[63:0]),
.in0(byp_irf_rd_data_w2[63:0]),
.in1(dfill_data_g2[63:0]),
.in2(lsu_exu_ldxa_data_g[63:0]),
.sel0(ecl_byp_rs2_longmux_sel_w2),
.sel1(ecl_byp_rs2_longmux_sel_g2),
.sel2(ecl_byp_rs2_longmux_sel_ldxa));
mux3ds #(64) rs3_w2_mux(.dout(rs3_data_w2[63:0]),
.in0(byp_irf_rd_data_w2[63:0]),
.in1(dfill_data_g2[63:0]),
.in2(lsu_exu_ldxa_data_g[63:0]),
.sel0(ecl_byp_rs3_longmux_sel_w2),
.sel1(ecl_byp_rs3_longmux_sel_g2),
.sel2(ecl_byp_rs3_longmux_sel_ldxa));
mux3ds #(32) rs3h_w2_mux(.dout(rs3h_data_w2[31:0]),
.in0(byp_irf_rd_data_w2[31:0]),
.in1(dfill_data_g2[31:0]),
.in2(lsu_exu_ldxa_data_g[31:0]),
.sel0(ecl_byp_rs3h_longmux_sel_w2),
.sel1(ecl_byp_rs3h_longmux_sel_g2),
.sel2(ecl_byp_rs3h_longmux_sel_ldxa));
// rs1_data muxes: RF and E are critical paths
mux4ds #(64) mux_rs1_data_1(.dout(rs1_data_btwn_mux[63:0]),
.in0(rd_data_m[63:0]),
.in1(byp_irf_rd_data_w[63:0]),
.in2(rs1_data_w2[63:0]),
.in3({{16{ifu_exu_pc_d[47]}}, ifu_exu_pc_d[47:0]}),
.sel0(ecl_byp_rs1_mux1_sel_m),
.sel1(ecl_byp_rs1_mux1_sel_w),
.sel2(ecl_byp_rs1_mux1_sel_w2),
.sel3(ecl_byp_rs1_mux1_sel_other));
mux4ds #(64) mux_rs1_data_2(.dout(byp_alu_rs1_data_d[63:0]),
.in0(rs1_data_btwn_mux[63:0]),
.in1(irf_byp_rs1_data_d[63:0]),
.in2(alu_byp_rd_data_e[63:0]),
.in3(lsu_exu_dfill_data_g[63:0]),
.sel0(ecl_byp_rs1_mux2_sel_usemux1),
.sel1(ecl_byp_rs1_mux2_sel_rf),
.sel2(ecl_byp_rs1_mux2_sel_e),
.sel3(ecl_byp_rs1_mux2_sel_ld));
// rcc_data muxes: RF and E are critical paths
mux4ds #(64) mux_rcc_data_1(.dout(rcc_data_btwn_mux[63:0]),
.in0(rd_data_m[63:0]),
.in1(byp_irf_rd_data_w[63:0]),
.in2(rs1_data_w2[63:0]),
.in3({64{1'b0}}),
.sel0(ecl_byp_rcc_mux1_sel_m),
.sel1(ecl_byp_rcc_mux1_sel_w),
.sel2(ecl_byp_rcc_mux1_sel_w2),
.sel3(ecl_byp_rcc_mux1_sel_other));
mux4ds #(64) mux_rcc_data_2(.dout(byp_alu_rcc_data_d[63:0]),
.in0(rcc_data_btwn_mux[63:0]),
.in1(irf_byp_rs1_data_d[63:0]),
.in2(alu_byp_rd_data_e[63:0]),
.in3(lsu_exu_dfill_data_g[63:0]),
.sel0(ecl_byp_rcc_mux2_sel_usemux1),
.sel1(ecl_byp_rcc_mux2_sel_rf),
.sel2(ecl_byp_rcc_mux2_sel_e),
.sel3(ecl_byp_rcc_mux2_sel_ld));
// rs2_data muxes: RF and E are critical paths, optional is imm
mux4ds #(64) mux_rs2_data_1(.dout(rs2_data_btwn_mux[63:0]),
.in0(rd_data_m[63:0]),
.in1(byp_irf_rd_data_w[63:0]),
.in2(rs2_data_w2[63:0]),
.in3({{32{ifu_exu_imm_data_d[31]}},
ifu_exu_imm_data_d[31:0]}),
.sel0(ecl_byp_rs2_mux1_sel_m),
.sel1(ecl_byp_rs2_mux1_sel_w),
.sel2(ecl_byp_rs2_mux1_sel_w2),
.sel3(ecl_byp_rs2_mux1_sel_other));
mux4ds #(64) mux_rs2_data_2(.dout(byp_alu_rs2_data_d[63:0]),
.in0(rs2_data_btwn_mux[63:0]),
.in1(irf_byp_rs2_data_d[63:0]),
.in2(alu_byp_rd_data_e[63:0]),
.in3(lsu_exu_dfill_data_g[63:0]),
.sel0(ecl_byp_rs2_mux2_sel_usemux1),
.sel1(ecl_byp_rs2_mux2_sel_rf),
.sel2(ecl_byp_rs2_mux2_sel_e),
.sel3(ecl_byp_rs2_mux2_sel_ld));
// rs3_data muxes: RF and E are critical paths, no optional
mux4ds #(64) mux_rs3_data_1(.dout(rs3_data_btwn_mux[63:0]),
.in0(rd_data_m[63:0]),
.in1(byp_irf_rd_data_w[63:0]),
.in2(rs3_data_w2[63:0]), .in3({64{1'b0}}),
.sel0(ecl_byp_rs3_mux1_sel_m),
.sel1(ecl_byp_rs3_mux1_sel_w),
.sel2(ecl_byp_rs3_mux1_sel_w2),
.sel3(ecl_byp_rs3_mux1_sel_other));
mux4ds #(64) mux_rs3_data_2(.dout(rs3_data_d[63:0]),
.in0(rs3_data_btwn_mux[63:0]),
.in1(irf_byp_rs3_data_d[63:0]),
.in2(alu_byp_rd_data_e[63:0]),
.in3(lsu_exu_dfill_data_g[63:0]),
.sel0(ecl_byp_rs3_mux2_sel_usemux1),
.sel1(ecl_byp_rs3_mux2_sel_rf),
.sel2(ecl_byp_rs3_mux2_sel_e),
.sel3(ecl_byp_rs3_mux2_sel_ld));
// rs3_data muxes: RF and E are critical paths, no optional
mux4ds #(32) mux_rs3h_data_1(.dout(rs3h_data_btwn_mux[31:0]),
.in0(rd_data_m[31:0]),
.in1(byp_irf_rd_data_w[31:0]),
.in2(rs3h_data_w2[31:0]), .in3({32{1'b0}}),
.sel0(ecl_byp_rs3h_mux1_sel_m),
.sel1(ecl_byp_rs3h_mux1_sel_w),
.sel2(ecl_byp_rs3h_mux1_sel_w2),
.sel3(ecl_byp_rs3h_mux1_sel_other));
mux4ds #(32) mux_rs3h_data_2(.dout(rs3h_data_d[31:0]),
.in0(rs3h_data_btwn_mux[31:0]),
.in1(irf_byp_rs3h_data_d[31:0]),
.in2(alu_byp_rd_data_e[31:0]),
.in3(lsu_exu_dfill_data_g[31:0]),
.sel0(ecl_byp_rs3h_mux2_sel_usemux1),
.sel1(ecl_byp_rs3h_mux2_sel_rf),
.sel2(ecl_byp_rs3h_mux2_sel_e),
.sel3(ecl_byp_rs3h_mux2_sel_ld));
// ECC for W1
`ifdef FPGA_SYN_CLK_DFF
sparc_exu_byp_eccgen w1_eccgen(.d(byp_irf_rd_data_m[63:0]),
.msk(ecl_byp_ecc_mask_m_l[7:0]),
.p(rd_synd_w_l[7:0]),
.clk(clk), .se(se));
`else
sparc_exu_byp_eccgen w1_eccgen(.d(byp_irf_rd_data_m[63:0]),
.msk(ecl_byp_ecc_mask_m_l[7:0]),
.p(rd_synd_w_l[7:0]),
.clk(sehold_clk), .se(se));
`endif
assign byp_irf_rd_data_w[71:64] = ~rd_synd_w_l[7:0];
////////////////////////
// G arbitration muxes and W2 ECC
////////////////////////
mux3ds #(64) mux_w2_data(.dout(rd_data_g[63:0]),
.in0(div_byp_muldivout_g[63:0]),
.in1(dfill_data_g2[63:0]),
.in2(restore_rd_data[63:0]),
.sel0(ecl_byp_sel_muldiv_g),
.sel1(ecl_byp_sel_load_g),
.sel2(ecl_byp_sel_restore_g));
`ifdef FPGA_SYN_CLK_DFF
sparc_exu_byp_eccgen w2_eccgen(.d(rd_data_g[63:0]),
.msk(ecl_byp_ecc_mask_m_l[7:0]),
.p(rd_synd_w2_l[7:0]),
.clk(clk), .se(se));
`else
sparc_exu_byp_eccgen w2_eccgen(.d(rd_data_g[63:0]),
.msk(ecl_byp_ecc_mask_m_l[7:0]),
.p(rd_synd_w2_l[7:0]),
.clk(sehold_clk), .se(se));
`endif
assign byp_irf_rd_data_w2[71:64] = ~rd_synd_w2_l[7:0];
endmodule // sparc_exu_byp
|
/*
Copyright (c) 2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire clk90,
input wire rst,
/*
* GPIO
*/
input wire [3:0] btn,
input wire [17:0] sw,
output wire [8:0] ledg,
output wire [17:0] ledr,
output wire [6:0] hex0,
output wire [6:0] hex1,
output wire [6:0] hex2,
output wire [6:0] hex3,
output wire [6:0] hex4,
output wire [6:0] hex5,
output wire [6:0] hex6,
output wire [6:0] hex7,
output wire [35:0] gpio,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy0_rx_clk,
input wire [3:0] phy0_rxd,
input wire phy0_rx_ctl,
output wire phy0_tx_clk,
output wire [3:0] phy0_txd,
output wire phy0_tx_ctl,
output wire phy0_reset_n,
input wire phy0_int_n,
input wire phy1_rx_clk,
input wire [3:0] phy1_rxd,
input wire phy1_rx_ctl,
output wire phy1_tx_clk,
output wire [3:0] phy1_txd,
output wire phy1_tx_ctl,
output wire phy1_reset_n,
input wire phy1_int_n
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
if (rst) begin
led_reg <= 0;
end
end
// place dest IP onto 7 segment displays
reg [31:0] dest_ip_reg = 0;
always @(posedge clk) begin
if (tx_udp_hdr_valid) begin
dest_ip_reg <= tx_udp_ip_dest_ip;
end
if (rst) begin
dest_ip_reg <= 0;
end
end
hex_display #(
.INVERT(1)
)
hex_display_0 (
.in(dest_ip_reg[3:0]),
.enable(1),
.out(hex0)
);
hex_display #(
.INVERT(1)
)
hex_display_1 (
.in(dest_ip_reg[7:4]),
.enable(1),
.out(hex1)
);
hex_display #(
.INVERT(1)
)
hex_display_2 (
.in(dest_ip_reg[11:8]),
.enable(1),
.out(hex2)
);
hex_display #(
.INVERT(1)
)
hex_display_3 (
.in(dest_ip_reg[15:12]),
.enable(1),
.out(hex3)
);
hex_display #(
.INVERT(1)
)
hex_display_4 (
.in(dest_ip_reg[19:16]),
.enable(1),
.out(hex4)
);
hex_display #(
.INVERT(1)
)
hex_display_5 (
.in(dest_ip_reg[23:20]),
.enable(1),
.out(hex5)
);
hex_display #(
.INVERT(1)
)
hex_display_6 (
.in(dest_ip_reg[27:24]),
.enable(1),
.out(hex6)
);
hex_display #(
.INVERT(1)
)
hex_display_7 (
.in(dest_ip_reg[31:28]),
.enable(1),
.out(hex7)
);
//assign led = sw;
assign ledg = led_reg;
assign ledr = sw;
assign phy0_reset_n = ~rst;
assign phy1_reset_n = ~rst;
assign gpio = 0;
eth_mac_1g_rgmii_fifo #(
.TARGET(TARGET),
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_clk90(clk90),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(phy0_rx_clk),
.rgmii_rxd(phy0_rxd),
.rgmii_rx_ctl(phy0_rx_ctl),
.rgmii_tx_clk(phy0_tx_clk),
.rgmii_txd(phy0_txd),
.rgmii_tx_ctl(phy0_tx_ctl),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the dac physical interface (drives samples from the low speed clock to the
// dac clock domain.
`timescale 1ns/100ps
module axi_ad9144_if (
// jesd interface
// tx_clk is (line-rate/40)
tx_clk,
tx_data,
// dac interface
dac_clk,
dac_rst,
dac_data_0_0,
dac_data_0_1,
dac_data_0_2,
dac_data_0_3,
dac_data_1_0,
dac_data_1_1,
dac_data_1_2,
dac_data_1_3,
dac_data_2_0,
dac_data_2_1,
dac_data_2_2,
dac_data_2_3,
dac_data_3_0,
dac_data_3_1,
dac_data_3_2,
dac_data_3_3);
// jesd interface
// tx_clk is (line-rate/40)
input tx_clk;
output [255:0] tx_data;
// dac interface
output dac_clk;
input dac_rst;
input [15:0] dac_data_0_0;
input [15:0] dac_data_0_1;
input [15:0] dac_data_0_2;
input [15:0] dac_data_0_3;
input [15:0] dac_data_1_0;
input [15:0] dac_data_1_1;
input [15:0] dac_data_1_2;
input [15:0] dac_data_1_3;
input [15:0] dac_data_2_0;
input [15:0] dac_data_2_1;
input [15:0] dac_data_2_2;
input [15:0] dac_data_2_3;
input [15:0] dac_data_3_0;
input [15:0] dac_data_3_1;
input [15:0] dac_data_3_2;
input [15:0] dac_data_3_3;
// internal registers
reg [255:0] tx_data = 'd0;
// reorder data for the jesd links
assign dac_clk = tx_clk;
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
tx_data <= 256'd0;
end else begin
tx_data[255:248] <= dac_data_3_3[ 7: 0];
tx_data[247:240] <= dac_data_3_2[ 7: 0];
tx_data[239:232] <= dac_data_3_1[ 7: 0];
tx_data[231:224] <= dac_data_3_0[ 7: 0];
tx_data[223:216] <= dac_data_3_3[15: 8];
tx_data[215:208] <= dac_data_3_2[15: 8];
tx_data[207:200] <= dac_data_3_1[15: 8];
tx_data[199:192] <= dac_data_3_0[15: 8];
tx_data[191:184] <= dac_data_2_3[ 7: 0];
tx_data[183:176] <= dac_data_2_2[ 7: 0];
tx_data[175:168] <= dac_data_2_1[ 7: 0];
tx_data[167:160] <= dac_data_2_0[ 7: 0];
tx_data[159:152] <= dac_data_2_3[15: 8];
tx_data[151:144] <= dac_data_2_2[15: 8];
tx_data[143:136] <= dac_data_2_1[15: 8];
tx_data[135:128] <= dac_data_2_0[15: 8];
tx_data[127:120] <= dac_data_1_3[ 7: 0];
tx_data[119:112] <= dac_data_1_2[ 7: 0];
tx_data[111:104] <= dac_data_1_1[ 7: 0];
tx_data[103: 96] <= dac_data_1_0[ 7: 0];
tx_data[ 95: 88] <= dac_data_1_3[15: 8];
tx_data[ 87: 80] <= dac_data_1_2[15: 8];
tx_data[ 79: 72] <= dac_data_1_1[15: 8];
tx_data[ 71: 64] <= dac_data_1_0[15: 8];
tx_data[ 63: 56] <= dac_data_0_3[ 7: 0];
tx_data[ 55: 48] <= dac_data_0_2[ 7: 0];
tx_data[ 47: 40] <= dac_data_0_1[ 7: 0];
tx_data[ 39: 32] <= dac_data_0_0[ 7: 0];
tx_data[ 31: 24] <= dac_data_0_3[15: 8];
tx_data[ 23: 16] <= dac_data_0_2[15: 8];
tx_data[ 15: 8] <= dac_data_0_1[15: 8];
tx_data[ 7: 0] <= dac_data_0_0[15: 8];
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O21AI_FUNCTIONAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21AI_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 15:07:21 09/17/2015
// Design Name: Manual Keypad Scanner and Encoder
// Module Name: Lab2Part1Fall2015AJM
//////////////////////////////////////////////////////////////////////////////////
module Lab2Part1Fall2015AJM(Rows, ClockIn, Load, Reset, RotateOnce, Columns, KeyNumberLEDs, ClockLocked);
parameter LENGTH = 4;
input [LENGTH-1:0] Rows;
input ClockIn, Load, Reset, RotateOnce;
output [LENGTH-1:0] Columns;
output [LENGTH:0] KeyNumberLEDs;
output ClockLocked;
wire DebouncedShift, Rotate;
Clock50MHz KeypadScanClock(ClockIn, Clock, ClockLocked);
DebouncerWithoutLatch RotateOnceSwitch(RotateOnce, DebouncedRotate, Reset, Clock);
ClockedOneShot RotateOnceUnit(DebouncedRotate, Rotate, Reset, Clock);
ShiftReg4bits ColumnPattern(4'b1110, Clock, Load, Reset, Rotate, Columns);
KeyEncoderAJM KeyMapUnit(Columns, Rows, KeyNumberLEDs);
endmodule
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_set_verbosity O 1 const
// RDY_cpu_reset_server_request_put O 1 reg
// cpu_reset_server_response_get O 1 reg
// RDY_cpu_reset_server_response_get O 1 reg
// cpu_imem_master_awvalid O 1 reg
// cpu_imem_master_awid O 4 reg
// cpu_imem_master_awaddr O 64 reg
// cpu_imem_master_awlen O 8 reg
// cpu_imem_master_awsize O 3 reg
// cpu_imem_master_awburst O 2 reg
// cpu_imem_master_awlock O 1 reg
// cpu_imem_master_awcache O 4 reg
// cpu_imem_master_awprot O 3 reg
// cpu_imem_master_awqos O 4 reg
// cpu_imem_master_awregion O 4 reg
// cpu_imem_master_wvalid O 1 reg
// cpu_imem_master_wdata O 64 reg
// cpu_imem_master_wstrb O 8 reg
// cpu_imem_master_wlast O 1 reg
// cpu_imem_master_bready O 1 reg
// cpu_imem_master_arvalid O 1 reg
// cpu_imem_master_arid O 4 reg
// cpu_imem_master_araddr O 64 reg
// cpu_imem_master_arlen O 8 reg
// cpu_imem_master_arsize O 3 reg
// cpu_imem_master_arburst O 2 reg
// cpu_imem_master_arlock O 1 reg
// cpu_imem_master_arcache O 4 reg
// cpu_imem_master_arprot O 3 reg
// cpu_imem_master_arqos O 4 reg
// cpu_imem_master_arregion O 4 reg
// cpu_imem_master_rready O 1 reg
// cpu_dmem_master_awvalid O 1 reg
// cpu_dmem_master_awid O 4 reg
// cpu_dmem_master_awaddr O 64 reg
// cpu_dmem_master_awlen O 8 reg
// cpu_dmem_master_awsize O 3 reg
// cpu_dmem_master_awburst O 2 reg
// cpu_dmem_master_awlock O 1 reg
// cpu_dmem_master_awcache O 4 reg
// cpu_dmem_master_awprot O 3 reg
// cpu_dmem_master_awqos O 4 reg
// cpu_dmem_master_awregion O 4 reg
// cpu_dmem_master_wvalid O 1 reg
// cpu_dmem_master_wdata O 64 reg
// cpu_dmem_master_wstrb O 8 reg
// cpu_dmem_master_wlast O 1 reg
// cpu_dmem_master_bready O 1 reg
// cpu_dmem_master_arvalid O 1 reg
// cpu_dmem_master_arid O 4 reg
// cpu_dmem_master_araddr O 64 reg
// cpu_dmem_master_arlen O 8 reg
// cpu_dmem_master_arsize O 3 reg
// cpu_dmem_master_arburst O 2 reg
// cpu_dmem_master_arlock O 1 reg
// cpu_dmem_master_arcache O 4 reg
// cpu_dmem_master_arprot O 3 reg
// cpu_dmem_master_arqos O 4 reg
// cpu_dmem_master_arregion O 4 reg
// cpu_dmem_master_rready O 1 reg
// RDY_set_watch_tohost O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// set_verbosity_logdelay I 64 reg
// cpu_reset_server_request_put I 1 reg
// cpu_imem_master_awready I 1
// cpu_imem_master_wready I 1
// cpu_imem_master_bvalid I 1
// cpu_imem_master_bid I 4 reg
// cpu_imem_master_bresp I 2 reg
// cpu_imem_master_arready I 1
// cpu_imem_master_rvalid I 1
// cpu_imem_master_rid I 4 reg
// cpu_imem_master_rdata I 64 reg
// cpu_imem_master_rresp I 2 reg
// cpu_imem_master_rlast I 1 reg
// cpu_dmem_master_awready I 1
// cpu_dmem_master_wready I 1
// cpu_dmem_master_bvalid I 1
// cpu_dmem_master_bid I 4 reg
// cpu_dmem_master_bresp I 2 reg
// cpu_dmem_master_arready I 1
// cpu_dmem_master_rvalid I 1
// cpu_dmem_master_rid I 4 reg
// cpu_dmem_master_rdata I 64 reg
// cpu_dmem_master_rresp I 2 reg
// cpu_dmem_master_rlast I 1 reg
// core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1
// nmi_req_set_not_clear I 1
// set_watch_tohost_watch_tohost I 1 unused
// set_watch_tohost_tohost_addr I 64 unused
// EN_set_verbosity I 1
// EN_cpu_reset_server_request_put I 1
// EN_set_watch_tohost I 1 unused
// EN_cpu_reset_server_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCore(CLK,
RST_N,
set_verbosity_verbosity,
set_verbosity_logdelay,
EN_set_verbosity,
RDY_set_verbosity,
cpu_reset_server_request_put,
EN_cpu_reset_server_request_put,
RDY_cpu_reset_server_request_put,
EN_cpu_reset_server_response_get,
cpu_reset_server_response_get,
RDY_cpu_reset_server_response_get,
cpu_imem_master_awvalid,
cpu_imem_master_awid,
cpu_imem_master_awaddr,
cpu_imem_master_awlen,
cpu_imem_master_awsize,
cpu_imem_master_awburst,
cpu_imem_master_awlock,
cpu_imem_master_awcache,
cpu_imem_master_awprot,
cpu_imem_master_awqos,
cpu_imem_master_awregion,
cpu_imem_master_awready,
cpu_imem_master_wvalid,
cpu_imem_master_wdata,
cpu_imem_master_wstrb,
cpu_imem_master_wlast,
cpu_imem_master_wready,
cpu_imem_master_bvalid,
cpu_imem_master_bid,
cpu_imem_master_bresp,
cpu_imem_master_bready,
cpu_imem_master_arvalid,
cpu_imem_master_arid,
cpu_imem_master_araddr,
cpu_imem_master_arlen,
cpu_imem_master_arsize,
cpu_imem_master_arburst,
cpu_imem_master_arlock,
cpu_imem_master_arcache,
cpu_imem_master_arprot,
cpu_imem_master_arqos,
cpu_imem_master_arregion,
cpu_imem_master_arready,
cpu_imem_master_rvalid,
cpu_imem_master_rid,
cpu_imem_master_rdata,
cpu_imem_master_rresp,
cpu_imem_master_rlast,
cpu_imem_master_rready,
cpu_dmem_master_awvalid,
cpu_dmem_master_awid,
cpu_dmem_master_awaddr,
cpu_dmem_master_awlen,
cpu_dmem_master_awsize,
cpu_dmem_master_awburst,
cpu_dmem_master_awlock,
cpu_dmem_master_awcache,
cpu_dmem_master_awprot,
cpu_dmem_master_awqos,
cpu_dmem_master_awregion,
cpu_dmem_master_awready,
cpu_dmem_master_wvalid,
cpu_dmem_master_wdata,
cpu_dmem_master_wstrb,
cpu_dmem_master_wlast,
cpu_dmem_master_wready,
cpu_dmem_master_bvalid,
cpu_dmem_master_bid,
cpu_dmem_master_bresp,
cpu_dmem_master_bready,
cpu_dmem_master_arvalid,
cpu_dmem_master_arid,
cpu_dmem_master_araddr,
cpu_dmem_master_arlen,
cpu_dmem_master_arsize,
cpu_dmem_master_arburst,
cpu_dmem_master_arlock,
cpu_dmem_master_arcache,
cpu_dmem_master_arprot,
cpu_dmem_master_arqos,
cpu_dmem_master_arregion,
cpu_dmem_master_arready,
cpu_dmem_master_rvalid,
cpu_dmem_master_rid,
cpu_dmem_master_rdata,
cpu_dmem_master_rresp,
cpu_dmem_master_rlast,
cpu_dmem_master_rready,
core_external_interrupt_sources_0_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_1_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_2_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_3_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_4_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_5_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_6_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_7_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_8_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_9_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_10_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_11_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_12_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_13_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_14_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_15_m_interrupt_req_set_not_clear,
nmi_req_set_not_clear,
set_watch_tohost_watch_tohost,
set_watch_tohost_tohost_addr,
EN_set_watch_tohost,
RDY_set_watch_tohost);
input CLK;
input RST_N;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input [63 : 0] set_verbosity_logdelay;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method cpu_reset_server_request_put
input cpu_reset_server_request_put;
input EN_cpu_reset_server_request_put;
output RDY_cpu_reset_server_request_put;
// actionvalue method cpu_reset_server_response_get
input EN_cpu_reset_server_response_get;
output cpu_reset_server_response_get;
output RDY_cpu_reset_server_response_get;
// value method cpu_imem_master_m_awvalid
output cpu_imem_master_awvalid;
// value method cpu_imem_master_m_awid
output [3 : 0] cpu_imem_master_awid;
// value method cpu_imem_master_m_awaddr
output [63 : 0] cpu_imem_master_awaddr;
// value method cpu_imem_master_m_awlen
output [7 : 0] cpu_imem_master_awlen;
// value method cpu_imem_master_m_awsize
output [2 : 0] cpu_imem_master_awsize;
// value method cpu_imem_master_m_awburst
output [1 : 0] cpu_imem_master_awburst;
// value method cpu_imem_master_m_awlock
output cpu_imem_master_awlock;
// value method cpu_imem_master_m_awcache
output [3 : 0] cpu_imem_master_awcache;
// value method cpu_imem_master_m_awprot
output [2 : 0] cpu_imem_master_awprot;
// value method cpu_imem_master_m_awqos
output [3 : 0] cpu_imem_master_awqos;
// value method cpu_imem_master_m_awregion
output [3 : 0] cpu_imem_master_awregion;
// value method cpu_imem_master_m_awuser
// action method cpu_imem_master_m_awready
input cpu_imem_master_awready;
// value method cpu_imem_master_m_wvalid
output cpu_imem_master_wvalid;
// value method cpu_imem_master_m_wdata
output [63 : 0] cpu_imem_master_wdata;
// value method cpu_imem_master_m_wstrb
output [7 : 0] cpu_imem_master_wstrb;
// value method cpu_imem_master_m_wlast
output cpu_imem_master_wlast;
// value method cpu_imem_master_m_wuser
// action method cpu_imem_master_m_wready
input cpu_imem_master_wready;
// action method cpu_imem_master_m_bvalid
input cpu_imem_master_bvalid;
input [3 : 0] cpu_imem_master_bid;
input [1 : 0] cpu_imem_master_bresp;
// value method cpu_imem_master_m_bready
output cpu_imem_master_bready;
// value method cpu_imem_master_m_arvalid
output cpu_imem_master_arvalid;
// value method cpu_imem_master_m_arid
output [3 : 0] cpu_imem_master_arid;
// value method cpu_imem_master_m_araddr
output [63 : 0] cpu_imem_master_araddr;
// value method cpu_imem_master_m_arlen
output [7 : 0] cpu_imem_master_arlen;
// value method cpu_imem_master_m_arsize
output [2 : 0] cpu_imem_master_arsize;
// value method cpu_imem_master_m_arburst
output [1 : 0] cpu_imem_master_arburst;
// value method cpu_imem_master_m_arlock
output cpu_imem_master_arlock;
// value method cpu_imem_master_m_arcache
output [3 : 0] cpu_imem_master_arcache;
// value method cpu_imem_master_m_arprot
output [2 : 0] cpu_imem_master_arprot;
// value method cpu_imem_master_m_arqos
output [3 : 0] cpu_imem_master_arqos;
// value method cpu_imem_master_m_arregion
output [3 : 0] cpu_imem_master_arregion;
// value method cpu_imem_master_m_aruser
// action method cpu_imem_master_m_arready
input cpu_imem_master_arready;
// action method cpu_imem_master_m_rvalid
input cpu_imem_master_rvalid;
input [3 : 0] cpu_imem_master_rid;
input [63 : 0] cpu_imem_master_rdata;
input [1 : 0] cpu_imem_master_rresp;
input cpu_imem_master_rlast;
// value method cpu_imem_master_m_rready
output cpu_imem_master_rready;
// value method cpu_dmem_master_m_awvalid
output cpu_dmem_master_awvalid;
// value method cpu_dmem_master_m_awid
output [3 : 0] cpu_dmem_master_awid;
// value method cpu_dmem_master_m_awaddr
output [63 : 0] cpu_dmem_master_awaddr;
// value method cpu_dmem_master_m_awlen
output [7 : 0] cpu_dmem_master_awlen;
// value method cpu_dmem_master_m_awsize
output [2 : 0] cpu_dmem_master_awsize;
// value method cpu_dmem_master_m_awburst
output [1 : 0] cpu_dmem_master_awburst;
// value method cpu_dmem_master_m_awlock
output cpu_dmem_master_awlock;
// value method cpu_dmem_master_m_awcache
output [3 : 0] cpu_dmem_master_awcache;
// value method cpu_dmem_master_m_awprot
output [2 : 0] cpu_dmem_master_awprot;
// value method cpu_dmem_master_m_awqos
output [3 : 0] cpu_dmem_master_awqos;
// value method cpu_dmem_master_m_awregion
output [3 : 0] cpu_dmem_master_awregion;
// value method cpu_dmem_master_m_awuser
// action method cpu_dmem_master_m_awready
input cpu_dmem_master_awready;
// value method cpu_dmem_master_m_wvalid
output cpu_dmem_master_wvalid;
// value method cpu_dmem_master_m_wdata
output [63 : 0] cpu_dmem_master_wdata;
// value method cpu_dmem_master_m_wstrb
output [7 : 0] cpu_dmem_master_wstrb;
// value method cpu_dmem_master_m_wlast
output cpu_dmem_master_wlast;
// value method cpu_dmem_master_m_wuser
// action method cpu_dmem_master_m_wready
input cpu_dmem_master_wready;
// action method cpu_dmem_master_m_bvalid
input cpu_dmem_master_bvalid;
input [3 : 0] cpu_dmem_master_bid;
input [1 : 0] cpu_dmem_master_bresp;
// value method cpu_dmem_master_m_bready
output cpu_dmem_master_bready;
// value method cpu_dmem_master_m_arvalid
output cpu_dmem_master_arvalid;
// value method cpu_dmem_master_m_arid
output [3 : 0] cpu_dmem_master_arid;
// value method cpu_dmem_master_m_araddr
output [63 : 0] cpu_dmem_master_araddr;
// value method cpu_dmem_master_m_arlen
output [7 : 0] cpu_dmem_master_arlen;
// value method cpu_dmem_master_m_arsize
output [2 : 0] cpu_dmem_master_arsize;
// value method cpu_dmem_master_m_arburst
output [1 : 0] cpu_dmem_master_arburst;
// value method cpu_dmem_master_m_arlock
output cpu_dmem_master_arlock;
// value method cpu_dmem_master_m_arcache
output [3 : 0] cpu_dmem_master_arcache;
// value method cpu_dmem_master_m_arprot
output [2 : 0] cpu_dmem_master_arprot;
// value method cpu_dmem_master_m_arqos
output [3 : 0] cpu_dmem_master_arqos;
// value method cpu_dmem_master_m_arregion
output [3 : 0] cpu_dmem_master_arregion;
// value method cpu_dmem_master_m_aruser
// action method cpu_dmem_master_m_arready
input cpu_dmem_master_arready;
// action method cpu_dmem_master_m_rvalid
input cpu_dmem_master_rvalid;
input [3 : 0] cpu_dmem_master_rid;
input [63 : 0] cpu_dmem_master_rdata;
input [1 : 0] cpu_dmem_master_rresp;
input cpu_dmem_master_rlast;
// value method cpu_dmem_master_m_rready
output cpu_dmem_master_rready;
// action method core_external_interrupt_sources_0_m_interrupt_req
input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_1_m_interrupt_req
input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_2_m_interrupt_req
input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_3_m_interrupt_req
input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_4_m_interrupt_req
input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_5_m_interrupt_req
input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_6_m_interrupt_req
input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_7_m_interrupt_req
input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_8_m_interrupt_req
input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_9_m_interrupt_req
input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_10_m_interrupt_req
input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_11_m_interrupt_req
input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_12_m_interrupt_req
input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_13_m_interrupt_req
input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_14_m_interrupt_req
input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_15_m_interrupt_req
input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear;
// action method nmi_req
input nmi_req_set_not_clear;
// action method set_watch_tohost
input set_watch_tohost_watch_tohost;
input [63 : 0] set_watch_tohost_tohost_addr;
input EN_set_watch_tohost;
output RDY_set_watch_tohost;
// signals for module outputs
wire [63 : 0] cpu_dmem_master_araddr,
cpu_dmem_master_awaddr,
cpu_dmem_master_wdata,
cpu_imem_master_araddr,
cpu_imem_master_awaddr,
cpu_imem_master_wdata;
wire [7 : 0] cpu_dmem_master_arlen,
cpu_dmem_master_awlen,
cpu_dmem_master_wstrb,
cpu_imem_master_arlen,
cpu_imem_master_awlen,
cpu_imem_master_wstrb;
wire [3 : 0] cpu_dmem_master_arcache,
cpu_dmem_master_arid,
cpu_dmem_master_arqos,
cpu_dmem_master_arregion,
cpu_dmem_master_awcache,
cpu_dmem_master_awid,
cpu_dmem_master_awqos,
cpu_dmem_master_awregion,
cpu_imem_master_arcache,
cpu_imem_master_arid,
cpu_imem_master_arqos,
cpu_imem_master_arregion,
cpu_imem_master_awcache,
cpu_imem_master_awid,
cpu_imem_master_awqos,
cpu_imem_master_awregion;
wire [2 : 0] cpu_dmem_master_arprot,
cpu_dmem_master_arsize,
cpu_dmem_master_awprot,
cpu_dmem_master_awsize,
cpu_imem_master_arprot,
cpu_imem_master_arsize,
cpu_imem_master_awprot,
cpu_imem_master_awsize;
wire [1 : 0] cpu_dmem_master_arburst,
cpu_dmem_master_awburst,
cpu_imem_master_arburst,
cpu_imem_master_awburst;
wire RDY_cpu_reset_server_request_put,
RDY_cpu_reset_server_response_get,
RDY_set_verbosity,
RDY_set_watch_tohost,
cpu_dmem_master_arlock,
cpu_dmem_master_arvalid,
cpu_dmem_master_awlock,
cpu_dmem_master_awvalid,
cpu_dmem_master_bready,
cpu_dmem_master_rready,
cpu_dmem_master_wlast,
cpu_dmem_master_wvalid,
cpu_imem_master_arlock,
cpu_imem_master_arvalid,
cpu_imem_master_awlock,
cpu_imem_master_awvalid,
cpu_imem_master_bready,
cpu_imem_master_rready,
cpu_imem_master_wlast,
cpu_imem_master_wvalid,
cpu_reset_server_response_get;
// ports of submodule cpu
wire [63 : 0] cpu$dmem_master_araddr,
cpu$dmem_master_awaddr,
cpu$dmem_master_rdata,
cpu$dmem_master_wdata,
cpu$imem_master_araddr,
cpu$imem_master_awaddr,
cpu$imem_master_rdata,
cpu$imem_master_wdata,
cpu$set_verbosity_logdelay,
cpu$set_watch_tohost_tohost_addr;
wire [7 : 0] cpu$dmem_master_arlen,
cpu$dmem_master_awlen,
cpu$dmem_master_wstrb,
cpu$imem_master_arlen,
cpu$imem_master_awlen,
cpu$imem_master_wstrb;
wire [3 : 0] cpu$dmem_master_arcache,
cpu$dmem_master_arid,
cpu$dmem_master_arqos,
cpu$dmem_master_arregion,
cpu$dmem_master_awcache,
cpu$dmem_master_awid,
cpu$dmem_master_awqos,
cpu$dmem_master_awregion,
cpu$dmem_master_bid,
cpu$dmem_master_rid,
cpu$imem_master_arcache,
cpu$imem_master_arid,
cpu$imem_master_arqos,
cpu$imem_master_arregion,
cpu$imem_master_awcache,
cpu$imem_master_awid,
cpu$imem_master_awqos,
cpu$imem_master_awregion,
cpu$imem_master_bid,
cpu$imem_master_rid,
cpu$set_verbosity_verbosity;
wire [2 : 0] cpu$dmem_master_arprot,
cpu$dmem_master_arsize,
cpu$dmem_master_awprot,
cpu$dmem_master_awsize,
cpu$imem_master_arprot,
cpu$imem_master_arsize,
cpu$imem_master_awprot,
cpu$imem_master_awsize;
wire [1 : 0] cpu$dmem_master_arburst,
cpu$dmem_master_awburst,
cpu$dmem_master_bresp,
cpu$dmem_master_rresp,
cpu$imem_master_arburst,
cpu$imem_master_awburst,
cpu$imem_master_bresp,
cpu$imem_master_rresp;
wire cpu$EN_hart0_server_reset_request_put,
cpu$EN_hart0_server_reset_response_get,
cpu$EN_set_verbosity,
cpu$EN_set_watch_tohost,
cpu$RDY_hart0_server_reset_request_put,
cpu$RDY_hart0_server_reset_response_get,
cpu$dmem_master_arlock,
cpu$dmem_master_arready,
cpu$dmem_master_arvalid,
cpu$dmem_master_awlock,
cpu$dmem_master_awready,
cpu$dmem_master_awvalid,
cpu$dmem_master_bready,
cpu$dmem_master_bvalid,
cpu$dmem_master_rlast,
cpu$dmem_master_rready,
cpu$dmem_master_rvalid,
cpu$dmem_master_wlast,
cpu$dmem_master_wready,
cpu$dmem_master_wvalid,
cpu$hart0_server_reset_request_put,
cpu$hart0_server_reset_response_get,
cpu$imem_master_arlock,
cpu$imem_master_arready,
cpu$imem_master_arvalid,
cpu$imem_master_awlock,
cpu$imem_master_awready,
cpu$imem_master_awvalid,
cpu$imem_master_bready,
cpu$imem_master_bvalid,
cpu$imem_master_rlast,
cpu$imem_master_rready,
cpu$imem_master_rvalid,
cpu$imem_master_wlast,
cpu$imem_master_wready,
cpu$imem_master_wvalid,
cpu$m_external_interrupt_req_set_not_clear,
cpu$nmi_req_set_not_clear,
cpu$s_external_interrupt_req_set_not_clear,
cpu$set_watch_tohost_watch_tohost,
cpu$software_interrupt_req_set_not_clear,
cpu$timer_interrupt_req_set_not_clear;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule fabric_2x3
wire [63 : 0] fabric_2x3$v_from_masters_0_araddr,
fabric_2x3$v_from_masters_0_awaddr,
fabric_2x3$v_from_masters_0_rdata,
fabric_2x3$v_from_masters_0_wdata,
fabric_2x3$v_from_masters_1_araddr,
fabric_2x3$v_from_masters_1_awaddr,
fabric_2x3$v_from_masters_1_wdata,
fabric_2x3$v_to_slaves_0_araddr,
fabric_2x3$v_to_slaves_0_awaddr,
fabric_2x3$v_to_slaves_0_rdata,
fabric_2x3$v_to_slaves_0_wdata,
fabric_2x3$v_to_slaves_1_araddr,
fabric_2x3$v_to_slaves_1_awaddr,
fabric_2x3$v_to_slaves_1_rdata,
fabric_2x3$v_to_slaves_1_wdata,
fabric_2x3$v_to_slaves_2_araddr,
fabric_2x3$v_to_slaves_2_awaddr,
fabric_2x3$v_to_slaves_2_rdata,
fabric_2x3$v_to_slaves_2_wdata;
wire [7 : 0] fabric_2x3$v_from_masters_0_arlen,
fabric_2x3$v_from_masters_0_awlen,
fabric_2x3$v_from_masters_0_wstrb,
fabric_2x3$v_from_masters_1_arlen,
fabric_2x3$v_from_masters_1_awlen,
fabric_2x3$v_from_masters_1_wstrb,
fabric_2x3$v_to_slaves_0_arlen,
fabric_2x3$v_to_slaves_0_awlen,
fabric_2x3$v_to_slaves_0_wstrb,
fabric_2x3$v_to_slaves_1_arlen,
fabric_2x3$v_to_slaves_1_awlen,
fabric_2x3$v_to_slaves_1_wstrb,
fabric_2x3$v_to_slaves_2_arlen,
fabric_2x3$v_to_slaves_2_awlen,
fabric_2x3$v_to_slaves_2_wstrb;
wire [3 : 0] fabric_2x3$set_verbosity_verbosity,
fabric_2x3$v_from_masters_0_arcache,
fabric_2x3$v_from_masters_0_arid,
fabric_2x3$v_from_masters_0_arqos,
fabric_2x3$v_from_masters_0_arregion,
fabric_2x3$v_from_masters_0_awcache,
fabric_2x3$v_from_masters_0_awid,
fabric_2x3$v_from_masters_0_awqos,
fabric_2x3$v_from_masters_0_awregion,
fabric_2x3$v_from_masters_0_bid,
fabric_2x3$v_from_masters_0_rid,
fabric_2x3$v_from_masters_1_arcache,
fabric_2x3$v_from_masters_1_arid,
fabric_2x3$v_from_masters_1_arqos,
fabric_2x3$v_from_masters_1_arregion,
fabric_2x3$v_from_masters_1_awcache,
fabric_2x3$v_from_masters_1_awid,
fabric_2x3$v_from_masters_1_awqos,
fabric_2x3$v_from_masters_1_awregion,
fabric_2x3$v_to_slaves_0_arcache,
fabric_2x3$v_to_slaves_0_arid,
fabric_2x3$v_to_slaves_0_arqos,
fabric_2x3$v_to_slaves_0_arregion,
fabric_2x3$v_to_slaves_0_awcache,
fabric_2x3$v_to_slaves_0_awid,
fabric_2x3$v_to_slaves_0_awqos,
fabric_2x3$v_to_slaves_0_awregion,
fabric_2x3$v_to_slaves_0_bid,
fabric_2x3$v_to_slaves_0_rid,
fabric_2x3$v_to_slaves_1_arcache,
fabric_2x3$v_to_slaves_1_arid,
fabric_2x3$v_to_slaves_1_arqos,
fabric_2x3$v_to_slaves_1_arregion,
fabric_2x3$v_to_slaves_1_awcache,
fabric_2x3$v_to_slaves_1_awid,
fabric_2x3$v_to_slaves_1_awqos,
fabric_2x3$v_to_slaves_1_awregion,
fabric_2x3$v_to_slaves_1_bid,
fabric_2x3$v_to_slaves_1_rid,
fabric_2x3$v_to_slaves_2_arcache,
fabric_2x3$v_to_slaves_2_arid,
fabric_2x3$v_to_slaves_2_arqos,
fabric_2x3$v_to_slaves_2_arregion,
fabric_2x3$v_to_slaves_2_awcache,
fabric_2x3$v_to_slaves_2_awid,
fabric_2x3$v_to_slaves_2_awqos,
fabric_2x3$v_to_slaves_2_awregion,
fabric_2x3$v_to_slaves_2_bid,
fabric_2x3$v_to_slaves_2_rid;
wire [2 : 0] fabric_2x3$v_from_masters_0_arprot,
fabric_2x3$v_from_masters_0_arsize,
fabric_2x3$v_from_masters_0_awprot,
fabric_2x3$v_from_masters_0_awsize,
fabric_2x3$v_from_masters_1_arprot,
fabric_2x3$v_from_masters_1_arsize,
fabric_2x3$v_from_masters_1_awprot,
fabric_2x3$v_from_masters_1_awsize,
fabric_2x3$v_to_slaves_0_arprot,
fabric_2x3$v_to_slaves_0_arsize,
fabric_2x3$v_to_slaves_0_awprot,
fabric_2x3$v_to_slaves_0_awsize,
fabric_2x3$v_to_slaves_1_arprot,
fabric_2x3$v_to_slaves_1_arsize,
fabric_2x3$v_to_slaves_1_awprot,
fabric_2x3$v_to_slaves_1_awsize,
fabric_2x3$v_to_slaves_2_arprot,
fabric_2x3$v_to_slaves_2_arsize,
fabric_2x3$v_to_slaves_2_awprot,
fabric_2x3$v_to_slaves_2_awsize;
wire [1 : 0] fabric_2x3$v_from_masters_0_arburst,
fabric_2x3$v_from_masters_0_awburst,
fabric_2x3$v_from_masters_0_bresp,
fabric_2x3$v_from_masters_0_rresp,
fabric_2x3$v_from_masters_1_arburst,
fabric_2x3$v_from_masters_1_awburst,
fabric_2x3$v_to_slaves_0_arburst,
fabric_2x3$v_to_slaves_0_awburst,
fabric_2x3$v_to_slaves_0_bresp,
fabric_2x3$v_to_slaves_0_rresp,
fabric_2x3$v_to_slaves_1_arburst,
fabric_2x3$v_to_slaves_1_awburst,
fabric_2x3$v_to_slaves_1_bresp,
fabric_2x3$v_to_slaves_1_rresp,
fabric_2x3$v_to_slaves_2_arburst,
fabric_2x3$v_to_slaves_2_awburst,
fabric_2x3$v_to_slaves_2_bresp,
fabric_2x3$v_to_slaves_2_rresp;
wire fabric_2x3$EN_reset,
fabric_2x3$EN_set_verbosity,
fabric_2x3$RDY_reset,
fabric_2x3$v_from_masters_0_arlock,
fabric_2x3$v_from_masters_0_arready,
fabric_2x3$v_from_masters_0_arvalid,
fabric_2x3$v_from_masters_0_awlock,
fabric_2x3$v_from_masters_0_awready,
fabric_2x3$v_from_masters_0_awvalid,
fabric_2x3$v_from_masters_0_bready,
fabric_2x3$v_from_masters_0_bvalid,
fabric_2x3$v_from_masters_0_rlast,
fabric_2x3$v_from_masters_0_rready,
fabric_2x3$v_from_masters_0_rvalid,
fabric_2x3$v_from_masters_0_wlast,
fabric_2x3$v_from_masters_0_wready,
fabric_2x3$v_from_masters_0_wvalid,
fabric_2x3$v_from_masters_1_arlock,
fabric_2x3$v_from_masters_1_arvalid,
fabric_2x3$v_from_masters_1_awlock,
fabric_2x3$v_from_masters_1_awvalid,
fabric_2x3$v_from_masters_1_bready,
fabric_2x3$v_from_masters_1_rready,
fabric_2x3$v_from_masters_1_wlast,
fabric_2x3$v_from_masters_1_wvalid,
fabric_2x3$v_to_slaves_0_arlock,
fabric_2x3$v_to_slaves_0_arready,
fabric_2x3$v_to_slaves_0_arvalid,
fabric_2x3$v_to_slaves_0_awlock,
fabric_2x3$v_to_slaves_0_awready,
fabric_2x3$v_to_slaves_0_awvalid,
fabric_2x3$v_to_slaves_0_bready,
fabric_2x3$v_to_slaves_0_bvalid,
fabric_2x3$v_to_slaves_0_rlast,
fabric_2x3$v_to_slaves_0_rready,
fabric_2x3$v_to_slaves_0_rvalid,
fabric_2x3$v_to_slaves_0_wlast,
fabric_2x3$v_to_slaves_0_wready,
fabric_2x3$v_to_slaves_0_wvalid,
fabric_2x3$v_to_slaves_1_arlock,
fabric_2x3$v_to_slaves_1_arready,
fabric_2x3$v_to_slaves_1_arvalid,
fabric_2x3$v_to_slaves_1_awlock,
fabric_2x3$v_to_slaves_1_awready,
fabric_2x3$v_to_slaves_1_awvalid,
fabric_2x3$v_to_slaves_1_bready,
fabric_2x3$v_to_slaves_1_bvalid,
fabric_2x3$v_to_slaves_1_rlast,
fabric_2x3$v_to_slaves_1_rready,
fabric_2x3$v_to_slaves_1_rvalid,
fabric_2x3$v_to_slaves_1_wlast,
fabric_2x3$v_to_slaves_1_wready,
fabric_2x3$v_to_slaves_1_wvalid,
fabric_2x3$v_to_slaves_2_arlock,
fabric_2x3$v_to_slaves_2_arready,
fabric_2x3$v_to_slaves_2_arvalid,
fabric_2x3$v_to_slaves_2_awlock,
fabric_2x3$v_to_slaves_2_awready,
fabric_2x3$v_to_slaves_2_awvalid,
fabric_2x3$v_to_slaves_2_bready,
fabric_2x3$v_to_slaves_2_bvalid,
fabric_2x3$v_to_slaves_2_rlast,
fabric_2x3$v_to_slaves_2_rready,
fabric_2x3$v_to_slaves_2_rvalid,
fabric_2x3$v_to_slaves_2_wlast,
fabric_2x3$v_to_slaves_2_wready,
fabric_2x3$v_to_slaves_2_wvalid;
// ports of submodule near_mem_io
wire [63 : 0] near_mem_io$axi4_slave_araddr,
near_mem_io$axi4_slave_awaddr,
near_mem_io$axi4_slave_rdata,
near_mem_io$axi4_slave_wdata,
near_mem_io$set_addr_map_addr_base,
near_mem_io$set_addr_map_addr_lim;
wire [7 : 0] near_mem_io$axi4_slave_arlen,
near_mem_io$axi4_slave_awlen,
near_mem_io$axi4_slave_wstrb;
wire [3 : 0] near_mem_io$axi4_slave_arcache,
near_mem_io$axi4_slave_arid,
near_mem_io$axi4_slave_arqos,
near_mem_io$axi4_slave_arregion,
near_mem_io$axi4_slave_awcache,
near_mem_io$axi4_slave_awid,
near_mem_io$axi4_slave_awqos,
near_mem_io$axi4_slave_awregion,
near_mem_io$axi4_slave_bid,
near_mem_io$axi4_slave_rid;
wire [2 : 0] near_mem_io$axi4_slave_arprot,
near_mem_io$axi4_slave_arsize,
near_mem_io$axi4_slave_awprot,
near_mem_io$axi4_slave_awsize;
wire [1 : 0] near_mem_io$axi4_slave_arburst,
near_mem_io$axi4_slave_awburst,
near_mem_io$axi4_slave_bresp,
near_mem_io$axi4_slave_rresp;
wire near_mem_io$EN_get_sw_interrupt_req_get,
near_mem_io$EN_get_timer_interrupt_req_get,
near_mem_io$EN_server_reset_request_put,
near_mem_io$EN_server_reset_response_get,
near_mem_io$EN_set_addr_map,
near_mem_io$RDY_get_sw_interrupt_req_get,
near_mem_io$RDY_get_timer_interrupt_req_get,
near_mem_io$RDY_server_reset_request_put,
near_mem_io$RDY_server_reset_response_get,
near_mem_io$axi4_slave_arlock,
near_mem_io$axi4_slave_arready,
near_mem_io$axi4_slave_arvalid,
near_mem_io$axi4_slave_awlock,
near_mem_io$axi4_slave_awready,
near_mem_io$axi4_slave_awvalid,
near_mem_io$axi4_slave_bready,
near_mem_io$axi4_slave_bvalid,
near_mem_io$axi4_slave_rlast,
near_mem_io$axi4_slave_rready,
near_mem_io$axi4_slave_rvalid,
near_mem_io$axi4_slave_wlast,
near_mem_io$axi4_slave_wready,
near_mem_io$axi4_slave_wvalid,
near_mem_io$get_sw_interrupt_req_get,
near_mem_io$get_timer_interrupt_req_get;
// ports of submodule plic
wire [63 : 0] plic$axi4_slave_araddr,
plic$axi4_slave_awaddr,
plic$axi4_slave_rdata,
plic$axi4_slave_wdata,
plic$set_addr_map_addr_base,
plic$set_addr_map_addr_lim;
wire [7 : 0] plic$axi4_slave_arlen,
plic$axi4_slave_awlen,
plic$axi4_slave_wstrb;
wire [3 : 0] plic$axi4_slave_arcache,
plic$axi4_slave_arid,
plic$axi4_slave_arqos,
plic$axi4_slave_arregion,
plic$axi4_slave_awcache,
plic$axi4_slave_awid,
plic$axi4_slave_awqos,
plic$axi4_slave_awregion,
plic$axi4_slave_bid,
plic$axi4_slave_rid,
plic$set_verbosity_verbosity;
wire [2 : 0] plic$axi4_slave_arprot,
plic$axi4_slave_arsize,
plic$axi4_slave_awprot,
plic$axi4_slave_awsize;
wire [1 : 0] plic$axi4_slave_arburst,
plic$axi4_slave_awburst,
plic$axi4_slave_bresp,
plic$axi4_slave_rresp;
wire plic$EN_server_reset_request_put,
plic$EN_server_reset_response_get,
plic$EN_set_addr_map,
plic$EN_set_verbosity,
plic$EN_show_PLIC_state,
plic$RDY_server_reset_request_put,
plic$RDY_server_reset_response_get,
plic$axi4_slave_arlock,
plic$axi4_slave_arready,
plic$axi4_slave_arvalid,
plic$axi4_slave_awlock,
plic$axi4_slave_awready,
plic$axi4_slave_awvalid,
plic$axi4_slave_bready,
plic$axi4_slave_bvalid,
plic$axi4_slave_rlast,
plic$axi4_slave_rready,
plic$axi4_slave_rvalid,
plic$axi4_slave_wlast,
plic$axi4_slave_wready,
plic$axi4_slave_wvalid,
plic$v_sources_0_m_interrupt_req_set_not_clear,
plic$v_sources_10_m_interrupt_req_set_not_clear,
plic$v_sources_11_m_interrupt_req_set_not_clear,
plic$v_sources_12_m_interrupt_req_set_not_clear,
plic$v_sources_13_m_interrupt_req_set_not_clear,
plic$v_sources_14_m_interrupt_req_set_not_clear,
plic$v_sources_15_m_interrupt_req_set_not_clear,
plic$v_sources_1_m_interrupt_req_set_not_clear,
plic$v_sources_2_m_interrupt_req_set_not_clear,
plic$v_sources_3_m_interrupt_req_set_not_clear,
plic$v_sources_4_m_interrupt_req_set_not_clear,
plic$v_sources_5_m_interrupt_req_set_not_clear,
plic$v_sources_6_m_interrupt_req_set_not_clear,
plic$v_sources_7_m_interrupt_req_set_not_clear,
plic$v_sources_8_m_interrupt_req_set_not_clear,
plic$v_sources_9_m_interrupt_req_set_not_clear,
plic$v_targets_0_m_eip,
plic$v_targets_1_m_eip;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_near_mem_io_addr_base,
soc_map$m_near_mem_io_addr_lim,
soc_map$m_plic_addr_base,
soc_map$m_plic_addr_lim;
// rule scheduling signals
wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete,
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start,
CAN_FIRE_RL_rl_rd_addr_channel,
CAN_FIRE_RL_rl_rd_addr_channel_1,
CAN_FIRE_RL_rl_rd_addr_channel_2,
CAN_FIRE_RL_rl_rd_addr_channel_3,
CAN_FIRE_RL_rl_rd_data_channel,
CAN_FIRE_RL_rl_rd_data_channel_1,
CAN_FIRE_RL_rl_rd_data_channel_2,
CAN_FIRE_RL_rl_rd_data_channel_3,
CAN_FIRE_RL_rl_relay_external_interrupts,
CAN_FIRE_RL_rl_relay_sw_interrupts,
CAN_FIRE_RL_rl_relay_timer_interrupts,
CAN_FIRE_RL_rl_wr_addr_channel,
CAN_FIRE_RL_rl_wr_addr_channel_1,
CAN_FIRE_RL_rl_wr_addr_channel_2,
CAN_FIRE_RL_rl_wr_addr_channel_3,
CAN_FIRE_RL_rl_wr_data_channel,
CAN_FIRE_RL_rl_wr_data_channel_1,
CAN_FIRE_RL_rl_wr_data_channel_2,
CAN_FIRE_RL_rl_wr_data_channel_3,
CAN_FIRE_RL_rl_wr_response_channel,
CAN_FIRE_RL_rl_wr_response_channel_1,
CAN_FIRE_RL_rl_wr_response_channel_2,
CAN_FIRE_RL_rl_wr_response_channel_3,
CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req,
CAN_FIRE_cpu_dmem_master_m_arready,
CAN_FIRE_cpu_dmem_master_m_awready,
CAN_FIRE_cpu_dmem_master_m_bvalid,
CAN_FIRE_cpu_dmem_master_m_rvalid,
CAN_FIRE_cpu_dmem_master_m_wready,
CAN_FIRE_cpu_imem_master_m_arready,
CAN_FIRE_cpu_imem_master_m_awready,
CAN_FIRE_cpu_imem_master_m_bvalid,
CAN_FIRE_cpu_imem_master_m_rvalid,
CAN_FIRE_cpu_imem_master_m_wready,
CAN_FIRE_cpu_reset_server_request_put,
CAN_FIRE_cpu_reset_server_response_get,
CAN_FIRE_nmi_req,
CAN_FIRE_set_verbosity,
CAN_FIRE_set_watch_tohost,
WILL_FIRE_RL_rl_cpu_hart0_reset_complete,
WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start,
WILL_FIRE_RL_rl_rd_addr_channel,
WILL_FIRE_RL_rl_rd_addr_channel_1,
WILL_FIRE_RL_rl_rd_addr_channel_2,
WILL_FIRE_RL_rl_rd_addr_channel_3,
WILL_FIRE_RL_rl_rd_data_channel,
WILL_FIRE_RL_rl_rd_data_channel_1,
WILL_FIRE_RL_rl_rd_data_channel_2,
WILL_FIRE_RL_rl_rd_data_channel_3,
WILL_FIRE_RL_rl_relay_external_interrupts,
WILL_FIRE_RL_rl_relay_sw_interrupts,
WILL_FIRE_RL_rl_relay_timer_interrupts,
WILL_FIRE_RL_rl_wr_addr_channel,
WILL_FIRE_RL_rl_wr_addr_channel_1,
WILL_FIRE_RL_rl_wr_addr_channel_2,
WILL_FIRE_RL_rl_wr_addr_channel_3,
WILL_FIRE_RL_rl_wr_data_channel,
WILL_FIRE_RL_rl_wr_data_channel_1,
WILL_FIRE_RL_rl_wr_data_channel_2,
WILL_FIRE_RL_rl_wr_data_channel_3,
WILL_FIRE_RL_rl_wr_response_channel,
WILL_FIRE_RL_rl_wr_response_channel_1,
WILL_FIRE_RL_rl_wr_response_channel_2,
WILL_FIRE_RL_rl_wr_response_channel_3,
WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req,
WILL_FIRE_cpu_dmem_master_m_arready,
WILL_FIRE_cpu_dmem_master_m_awready,
WILL_FIRE_cpu_dmem_master_m_bvalid,
WILL_FIRE_cpu_dmem_master_m_rvalid,
WILL_FIRE_cpu_dmem_master_m_wready,
WILL_FIRE_cpu_imem_master_m_arready,
WILL_FIRE_cpu_imem_master_m_awready,
WILL_FIRE_cpu_imem_master_m_bvalid,
WILL_FIRE_cpu_imem_master_m_rvalid,
WILL_FIRE_cpu_imem_master_m_wready,
WILL_FIRE_cpu_reset_server_request_put,
WILL_FIRE_cpu_reset_server_response_get,
WILL_FIRE_nmi_req,
WILL_FIRE_set_verbosity,
WILL_FIRE_set_watch_tohost;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h4255;
reg [31 : 0] v__h4496;
reg [31 : 0] v__h4249;
reg [31 : 0] v__h4490;
// synopsys translate_on
// remaining internal signals
wire plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method cpu_reset_server_request_put
assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_cpu_reset_server_request_put =
EN_cpu_reset_server_request_put ;
// actionvalue method cpu_reset_server_response_get
assign cpu_reset_server_response_get = f_reset_rsps$D_OUT ;
assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_cpu_reset_server_response_get =
EN_cpu_reset_server_response_get ;
// value method cpu_imem_master_m_awvalid
assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ;
// value method cpu_imem_master_m_awid
assign cpu_imem_master_awid = cpu$imem_master_awid ;
// value method cpu_imem_master_m_awaddr
assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ;
// value method cpu_imem_master_m_awlen
assign cpu_imem_master_awlen = cpu$imem_master_awlen ;
// value method cpu_imem_master_m_awsize
assign cpu_imem_master_awsize = cpu$imem_master_awsize ;
// value method cpu_imem_master_m_awburst
assign cpu_imem_master_awburst = cpu$imem_master_awburst ;
// value method cpu_imem_master_m_awlock
assign cpu_imem_master_awlock = cpu$imem_master_awlock ;
// value method cpu_imem_master_m_awcache
assign cpu_imem_master_awcache = cpu$imem_master_awcache ;
// value method cpu_imem_master_m_awprot
assign cpu_imem_master_awprot = cpu$imem_master_awprot ;
// value method cpu_imem_master_m_awqos
assign cpu_imem_master_awqos = cpu$imem_master_awqos ;
// value method cpu_imem_master_m_awregion
assign cpu_imem_master_awregion = cpu$imem_master_awregion ;
// action method cpu_imem_master_m_awready
assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ;
// value method cpu_imem_master_m_wvalid
assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ;
// value method cpu_imem_master_m_wdata
assign cpu_imem_master_wdata = cpu$imem_master_wdata ;
// value method cpu_imem_master_m_wstrb
assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ;
// value method cpu_imem_master_m_wlast
assign cpu_imem_master_wlast = cpu$imem_master_wlast ;
// action method cpu_imem_master_m_wready
assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ;
// action method cpu_imem_master_m_bvalid
assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ;
// value method cpu_imem_master_m_bready
assign cpu_imem_master_bready = cpu$imem_master_bready ;
// value method cpu_imem_master_m_arvalid
assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ;
// value method cpu_imem_master_m_arid
assign cpu_imem_master_arid = cpu$imem_master_arid ;
// value method cpu_imem_master_m_araddr
assign cpu_imem_master_araddr = cpu$imem_master_araddr ;
// value method cpu_imem_master_m_arlen
assign cpu_imem_master_arlen = cpu$imem_master_arlen ;
// value method cpu_imem_master_m_arsize
assign cpu_imem_master_arsize = cpu$imem_master_arsize ;
// value method cpu_imem_master_m_arburst
assign cpu_imem_master_arburst = cpu$imem_master_arburst ;
// value method cpu_imem_master_m_arlock
assign cpu_imem_master_arlock = cpu$imem_master_arlock ;
// value method cpu_imem_master_m_arcache
assign cpu_imem_master_arcache = cpu$imem_master_arcache ;
// value method cpu_imem_master_m_arprot
assign cpu_imem_master_arprot = cpu$imem_master_arprot ;
// value method cpu_imem_master_m_arqos
assign cpu_imem_master_arqos = cpu$imem_master_arqos ;
// value method cpu_imem_master_m_arregion
assign cpu_imem_master_arregion = cpu$imem_master_arregion ;
// action method cpu_imem_master_m_arready
assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ;
// action method cpu_imem_master_m_rvalid
assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ;
// value method cpu_imem_master_m_rready
assign cpu_imem_master_rready = cpu$imem_master_rready ;
// value method cpu_dmem_master_m_awvalid
assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ;
// value method cpu_dmem_master_m_awid
assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ;
// value method cpu_dmem_master_m_awaddr
assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ;
// value method cpu_dmem_master_m_awlen
assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ;
// value method cpu_dmem_master_m_awsize
assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ;
// value method cpu_dmem_master_m_awburst
assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ;
// value method cpu_dmem_master_m_awlock
assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ;
// value method cpu_dmem_master_m_awcache
assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ;
// value method cpu_dmem_master_m_awprot
assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ;
// value method cpu_dmem_master_m_awqos
assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ;
// value method cpu_dmem_master_m_awregion
assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ;
// action method cpu_dmem_master_m_awready
assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ;
// value method cpu_dmem_master_m_wvalid
assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ;
// value method cpu_dmem_master_m_wdata
assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ;
// value method cpu_dmem_master_m_wstrb
assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ;
// value method cpu_dmem_master_m_wlast
assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ;
// action method cpu_dmem_master_m_wready
assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ;
// action method cpu_dmem_master_m_bvalid
assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ;
// value method cpu_dmem_master_m_bready
assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ;
// value method cpu_dmem_master_m_arvalid
assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ;
// value method cpu_dmem_master_m_arid
assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ;
// value method cpu_dmem_master_m_araddr
assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ;
// value method cpu_dmem_master_m_arlen
assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ;
// value method cpu_dmem_master_m_arsize
assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ;
// value method cpu_dmem_master_m_arburst
assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ;
// value method cpu_dmem_master_m_arlock
assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ;
// value method cpu_dmem_master_m_arcache
assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ;
// value method cpu_dmem_master_m_arprot
assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ;
// value method cpu_dmem_master_m_arqos
assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ;
// value method cpu_dmem_master_m_arregion
assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ;
// action method cpu_dmem_master_m_arready
assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ;
// action method cpu_dmem_master_m_rvalid
assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ;
// value method cpu_dmem_master_m_rready
assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ;
// action method core_external_interrupt_sources_0_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_1_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_2_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_3_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_4_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_5_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_6_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_7_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_8_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_9_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_10_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_11_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_12_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_13_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_14_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_15_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ;
// action method nmi_req
assign CAN_FIRE_nmi_req = 1'd1 ;
assign WILL_FIRE_nmi_req = 1'd1 ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// submodule cpu
mkCPU cpu(.CLK(CLK),
.RST_N(RST_N),
.dmem_master_arready(cpu$dmem_master_arready),
.dmem_master_awready(cpu$dmem_master_awready),
.dmem_master_bid(cpu$dmem_master_bid),
.dmem_master_bresp(cpu$dmem_master_bresp),
.dmem_master_bvalid(cpu$dmem_master_bvalid),
.dmem_master_rdata(cpu$dmem_master_rdata),
.dmem_master_rid(cpu$dmem_master_rid),
.dmem_master_rlast(cpu$dmem_master_rlast),
.dmem_master_rresp(cpu$dmem_master_rresp),
.dmem_master_rvalid(cpu$dmem_master_rvalid),
.dmem_master_wready(cpu$dmem_master_wready),
.hart0_server_reset_request_put(cpu$hart0_server_reset_request_put),
.imem_master_arready(cpu$imem_master_arready),
.imem_master_awready(cpu$imem_master_awready),
.imem_master_bid(cpu$imem_master_bid),
.imem_master_bresp(cpu$imem_master_bresp),
.imem_master_bvalid(cpu$imem_master_bvalid),
.imem_master_rdata(cpu$imem_master_rdata),
.imem_master_rid(cpu$imem_master_rid),
.imem_master_rlast(cpu$imem_master_rlast),
.imem_master_rresp(cpu$imem_master_rresp),
.imem_master_rvalid(cpu$imem_master_rvalid),
.imem_master_wready(cpu$imem_master_wready),
.m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear),
.nmi_req_set_not_clear(cpu$nmi_req_set_not_clear),
.s_external_interrupt_req_set_not_clear(cpu$s_external_interrupt_req_set_not_clear),
.set_verbosity_logdelay(cpu$set_verbosity_logdelay),
.set_verbosity_verbosity(cpu$set_verbosity_verbosity),
.set_watch_tohost_tohost_addr(cpu$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(cpu$set_watch_tohost_watch_tohost),
.software_interrupt_req_set_not_clear(cpu$software_interrupt_req_set_not_clear),
.timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear),
.EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put),
.EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get),
.EN_set_verbosity(cpu$EN_set_verbosity),
.EN_set_watch_tohost(cpu$EN_set_watch_tohost),
.RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put),
.hart0_server_reset_response_get(cpu$hart0_server_reset_response_get),
.RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get),
.imem_master_awvalid(cpu$imem_master_awvalid),
.imem_master_awid(cpu$imem_master_awid),
.imem_master_awaddr(cpu$imem_master_awaddr),
.imem_master_awlen(cpu$imem_master_awlen),
.imem_master_awsize(cpu$imem_master_awsize),
.imem_master_awburst(cpu$imem_master_awburst),
.imem_master_awlock(cpu$imem_master_awlock),
.imem_master_awcache(cpu$imem_master_awcache),
.imem_master_awprot(cpu$imem_master_awprot),
.imem_master_awqos(cpu$imem_master_awqos),
.imem_master_awregion(cpu$imem_master_awregion),
.imem_master_wvalid(cpu$imem_master_wvalid),
.imem_master_wdata(cpu$imem_master_wdata),
.imem_master_wstrb(cpu$imem_master_wstrb),
.imem_master_wlast(cpu$imem_master_wlast),
.imem_master_bready(cpu$imem_master_bready),
.imem_master_arvalid(cpu$imem_master_arvalid),
.imem_master_arid(cpu$imem_master_arid),
.imem_master_araddr(cpu$imem_master_araddr),
.imem_master_arlen(cpu$imem_master_arlen),
.imem_master_arsize(cpu$imem_master_arsize),
.imem_master_arburst(cpu$imem_master_arburst),
.imem_master_arlock(cpu$imem_master_arlock),
.imem_master_arcache(cpu$imem_master_arcache),
.imem_master_arprot(cpu$imem_master_arprot),
.imem_master_arqos(cpu$imem_master_arqos),
.imem_master_arregion(cpu$imem_master_arregion),
.imem_master_rready(cpu$imem_master_rready),
.dmem_master_awvalid(cpu$dmem_master_awvalid),
.dmem_master_awid(cpu$dmem_master_awid),
.dmem_master_awaddr(cpu$dmem_master_awaddr),
.dmem_master_awlen(cpu$dmem_master_awlen),
.dmem_master_awsize(cpu$dmem_master_awsize),
.dmem_master_awburst(cpu$dmem_master_awburst),
.dmem_master_awlock(cpu$dmem_master_awlock),
.dmem_master_awcache(cpu$dmem_master_awcache),
.dmem_master_awprot(cpu$dmem_master_awprot),
.dmem_master_awqos(cpu$dmem_master_awqos),
.dmem_master_awregion(cpu$dmem_master_awregion),
.dmem_master_wvalid(cpu$dmem_master_wvalid),
.dmem_master_wdata(cpu$dmem_master_wdata),
.dmem_master_wstrb(cpu$dmem_master_wstrb),
.dmem_master_wlast(cpu$dmem_master_wlast),
.dmem_master_bready(cpu$dmem_master_bready),
.dmem_master_arvalid(cpu$dmem_master_arvalid),
.dmem_master_arid(cpu$dmem_master_arid),
.dmem_master_araddr(cpu$dmem_master_araddr),
.dmem_master_arlen(cpu$dmem_master_arlen),
.dmem_master_arsize(cpu$dmem_master_arsize),
.dmem_master_arburst(cpu$dmem_master_arburst),
.dmem_master_arlock(cpu$dmem_master_arlock),
.dmem_master_arcache(cpu$dmem_master_arcache),
.dmem_master_arprot(cpu$dmem_master_arprot),
.dmem_master_arqos(cpu$dmem_master_arqos),
.dmem_master_arregion(cpu$dmem_master_arregion),
.dmem_master_rready(cpu$dmem_master_rready),
.RDY_set_verbosity(),
.RDY_set_watch_tohost());
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule fabric_2x3
mkFabric_2x3 fabric_2x3(.CLK(CLK),
.RST_N(RST_N),
.set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity),
.v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr),
.v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst),
.v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache),
.v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid),
.v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen),
.v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock),
.v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot),
.v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos),
.v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion),
.v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize),
.v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid),
.v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr),
.v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst),
.v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache),
.v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid),
.v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen),
.v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock),
.v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot),
.v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos),
.v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion),
.v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize),
.v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid),
.v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready),
.v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready),
.v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata),
.v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast),
.v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb),
.v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid),
.v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr),
.v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst),
.v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache),
.v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid),
.v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen),
.v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock),
.v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot),
.v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos),
.v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion),
.v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize),
.v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid),
.v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr),
.v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst),
.v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache),
.v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid),
.v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen),
.v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock),
.v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot),
.v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos),
.v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion),
.v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize),
.v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid),
.v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready),
.v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready),
.v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata),
.v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast),
.v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb),
.v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid),
.v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready),
.v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready),
.v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid),
.v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp),
.v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid),
.v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata),
.v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid),
.v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast),
.v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp),
.v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid),
.v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready),
.v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready),
.v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready),
.v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid),
.v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp),
.v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid),
.v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata),
.v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid),
.v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast),
.v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp),
.v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid),
.v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready),
.v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready),
.v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready),
.v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid),
.v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp),
.v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid),
.v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata),
.v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid),
.v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast),
.v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp),
.v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid),
.v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready),
.EN_reset(fabric_2x3$EN_reset),
.EN_set_verbosity(fabric_2x3$EN_set_verbosity),
.RDY_reset(fabric_2x3$RDY_reset),
.RDY_set_verbosity(),
.v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready),
.v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready),
.v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid),
.v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid),
.v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp),
.v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready),
.v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid),
.v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid),
.v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata),
.v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp),
.v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast),
.v_from_masters_1_awready(),
.v_from_masters_1_wready(),
.v_from_masters_1_bvalid(),
.v_from_masters_1_bid(),
.v_from_masters_1_bresp(),
.v_from_masters_1_arready(),
.v_from_masters_1_rvalid(),
.v_from_masters_1_rid(),
.v_from_masters_1_rdata(),
.v_from_masters_1_rresp(),
.v_from_masters_1_rlast(),
.v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid),
.v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid),
.v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr),
.v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen),
.v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize),
.v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst),
.v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock),
.v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache),
.v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot),
.v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos),
.v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion),
.v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid),
.v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata),
.v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb),
.v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast),
.v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready),
.v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid),
.v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid),
.v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr),
.v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen),
.v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize),
.v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst),
.v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock),
.v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache),
.v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot),
.v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos),
.v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion),
.v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready),
.v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid),
.v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid),
.v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr),
.v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen),
.v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize),
.v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst),
.v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock),
.v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache),
.v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot),
.v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos),
.v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion),
.v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid),
.v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata),
.v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb),
.v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast),
.v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready),
.v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid),
.v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid),
.v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr),
.v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen),
.v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize),
.v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst),
.v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock),
.v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache),
.v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot),
.v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos),
.v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion),
.v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready),
.v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid),
.v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid),
.v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr),
.v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen),
.v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize),
.v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst),
.v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock),
.v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache),
.v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot),
.v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos),
.v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion),
.v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid),
.v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata),
.v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb),
.v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast),
.v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready),
.v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid),
.v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid),
.v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr),
.v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen),
.v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize),
.v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst),
.v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock),
.v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache),
.v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot),
.v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos),
.v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion),
.v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready));
// submodule near_mem_io
mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK),
.RST_N(RST_N),
.axi4_slave_araddr(near_mem_io$axi4_slave_araddr),
.axi4_slave_arburst(near_mem_io$axi4_slave_arburst),
.axi4_slave_arcache(near_mem_io$axi4_slave_arcache),
.axi4_slave_arid(near_mem_io$axi4_slave_arid),
.axi4_slave_arlen(near_mem_io$axi4_slave_arlen),
.axi4_slave_arlock(near_mem_io$axi4_slave_arlock),
.axi4_slave_arprot(near_mem_io$axi4_slave_arprot),
.axi4_slave_arqos(near_mem_io$axi4_slave_arqos),
.axi4_slave_arregion(near_mem_io$axi4_slave_arregion),
.axi4_slave_arsize(near_mem_io$axi4_slave_arsize),
.axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid),
.axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr),
.axi4_slave_awburst(near_mem_io$axi4_slave_awburst),
.axi4_slave_awcache(near_mem_io$axi4_slave_awcache),
.axi4_slave_awid(near_mem_io$axi4_slave_awid),
.axi4_slave_awlen(near_mem_io$axi4_slave_awlen),
.axi4_slave_awlock(near_mem_io$axi4_slave_awlock),
.axi4_slave_awprot(near_mem_io$axi4_slave_awprot),
.axi4_slave_awqos(near_mem_io$axi4_slave_awqos),
.axi4_slave_awregion(near_mem_io$axi4_slave_awregion),
.axi4_slave_awsize(near_mem_io$axi4_slave_awsize),
.axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid),
.axi4_slave_bready(near_mem_io$axi4_slave_bready),
.axi4_slave_rready(near_mem_io$axi4_slave_rready),
.axi4_slave_wdata(near_mem_io$axi4_slave_wdata),
.axi4_slave_wlast(near_mem_io$axi4_slave_wlast),
.axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb),
.axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid),
.set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base),
.set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim),
.EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put),
.EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get),
.EN_set_addr_map(near_mem_io$EN_set_addr_map),
.EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get),
.EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get),
.RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put),
.RDY_server_reset_response_get(near_mem_io$RDY_server_reset_response_get),
.RDY_set_addr_map(),
.axi4_slave_awready(near_mem_io$axi4_slave_awready),
.axi4_slave_wready(near_mem_io$axi4_slave_wready),
.axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid),
.axi4_slave_bid(near_mem_io$axi4_slave_bid),
.axi4_slave_bresp(near_mem_io$axi4_slave_bresp),
.axi4_slave_arready(near_mem_io$axi4_slave_arready),
.axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid),
.axi4_slave_rid(near_mem_io$axi4_slave_rid),
.axi4_slave_rdata(near_mem_io$axi4_slave_rdata),
.axi4_slave_rresp(near_mem_io$axi4_slave_rresp),
.axi4_slave_rlast(near_mem_io$axi4_slave_rlast),
.get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get),
.RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get),
.get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get),
.RDY_get_sw_interrupt_req_get(near_mem_io$RDY_get_sw_interrupt_req_get));
// submodule plic
mkPLIC_16_2_7 plic(.CLK(CLK),
.RST_N(RST_N),
.axi4_slave_araddr(plic$axi4_slave_araddr),
.axi4_slave_arburst(plic$axi4_slave_arburst),
.axi4_slave_arcache(plic$axi4_slave_arcache),
.axi4_slave_arid(plic$axi4_slave_arid),
.axi4_slave_arlen(plic$axi4_slave_arlen),
.axi4_slave_arlock(plic$axi4_slave_arlock),
.axi4_slave_arprot(plic$axi4_slave_arprot),
.axi4_slave_arqos(plic$axi4_slave_arqos),
.axi4_slave_arregion(plic$axi4_slave_arregion),
.axi4_slave_arsize(plic$axi4_slave_arsize),
.axi4_slave_arvalid(plic$axi4_slave_arvalid),
.axi4_slave_awaddr(plic$axi4_slave_awaddr),
.axi4_slave_awburst(plic$axi4_slave_awburst),
.axi4_slave_awcache(plic$axi4_slave_awcache),
.axi4_slave_awid(plic$axi4_slave_awid),
.axi4_slave_awlen(plic$axi4_slave_awlen),
.axi4_slave_awlock(plic$axi4_slave_awlock),
.axi4_slave_awprot(plic$axi4_slave_awprot),
.axi4_slave_awqos(plic$axi4_slave_awqos),
.axi4_slave_awregion(plic$axi4_slave_awregion),
.axi4_slave_awsize(plic$axi4_slave_awsize),
.axi4_slave_awvalid(plic$axi4_slave_awvalid),
.axi4_slave_bready(plic$axi4_slave_bready),
.axi4_slave_rready(plic$axi4_slave_rready),
.axi4_slave_wdata(plic$axi4_slave_wdata),
.axi4_slave_wlast(plic$axi4_slave_wlast),
.axi4_slave_wstrb(plic$axi4_slave_wstrb),
.axi4_slave_wvalid(plic$axi4_slave_wvalid),
.set_addr_map_addr_base(plic$set_addr_map_addr_base),
.set_addr_map_addr_lim(plic$set_addr_map_addr_lim),
.set_verbosity_verbosity(plic$set_verbosity_verbosity),
.v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear),
.v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear),
.v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear),
.v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear),
.v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear),
.v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear),
.v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear),
.v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear),
.v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear),
.v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear),
.v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear),
.v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear),
.v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear),
.v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear),
.v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear),
.v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear),
.EN_set_verbosity(plic$EN_set_verbosity),
.EN_show_PLIC_state(plic$EN_show_PLIC_state),
.EN_server_reset_request_put(plic$EN_server_reset_request_put),
.EN_server_reset_response_get(plic$EN_server_reset_response_get),
.EN_set_addr_map(plic$EN_set_addr_map),
.RDY_set_verbosity(),
.RDY_show_PLIC_state(),
.RDY_server_reset_request_put(plic$RDY_server_reset_request_put),
.RDY_server_reset_response_get(plic$RDY_server_reset_response_get),
.RDY_set_addr_map(),
.axi4_slave_awready(plic$axi4_slave_awready),
.axi4_slave_wready(plic$axi4_slave_wready),
.axi4_slave_bvalid(plic$axi4_slave_bvalid),
.axi4_slave_bid(plic$axi4_slave_bid),
.axi4_slave_bresp(plic$axi4_slave_bresp),
.axi4_slave_arready(plic$axi4_slave_arready),
.axi4_slave_rvalid(plic$axi4_slave_rvalid),
.axi4_slave_rid(plic$axi4_slave_rid),
.axi4_slave_rdata(plic$axi4_slave_rdata),
.axi4_slave_rresp(plic$axi4_slave_rresp),
.axi4_slave_rlast(plic$axi4_slave_rlast),
.v_targets_0_m_eip(plic$v_targets_0_m_eip),
.v_targets_1_m_eip(plic$v_targets_1_m_eip));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim),
.m_plic_addr_base(soc_map$m_plic_addr_base),
.m_plic_addr_size(),
.m_plic_addr_lim(soc_map$m_plic_addr_lim),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_rl_wr_addr_channel
assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ;
// rule RL_rl_wr_data_channel
assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ;
// rule RL_rl_wr_response_channel
assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ;
// rule RL_rl_rd_addr_channel
assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ;
// rule RL_rl_rd_data_channel
assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ;
// rule RL_rl_wr_addr_channel_1
assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ;
// rule RL_rl_wr_data_channel_1
assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ;
// rule RL_rl_wr_response_channel_1
assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ;
// rule RL_rl_rd_addr_channel_1
assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ;
// rule RL_rl_rd_data_channel_1
assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ;
// rule RL_rl_wr_addr_channel_2
assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ;
// rule RL_rl_wr_data_channel_2
assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ;
// rule RL_rl_wr_response_channel_2
assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ;
// rule RL_rl_rd_addr_channel_2
assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ;
// rule RL_rl_rd_data_channel_2
assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ;
// rule RL_rl_wr_addr_channel_3
assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ;
// rule RL_rl_wr_data_channel_3
assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ;
// rule RL_rl_wr_response_channel_3
assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ;
// rule RL_rl_rd_addr_channel_3
assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ;
// rule RL_rl_rd_data_channel_3
assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ;
// rule RL_rl_relay_sw_interrupts
assign CAN_FIRE_RL_rl_relay_sw_interrupts =
near_mem_io$RDY_get_sw_interrupt_req_get ;
assign WILL_FIRE_RL_rl_relay_sw_interrupts =
near_mem_io$RDY_get_sw_interrupt_req_get ;
// rule RL_rl_relay_timer_interrupts
assign CAN_FIRE_RL_rl_relay_timer_interrupts =
near_mem_io$RDY_get_timer_interrupt_req_get ;
assign WILL_FIRE_RL_rl_relay_timer_interrupts =
near_mem_io$RDY_get_timer_interrupt_req_get ;
// rule RL_rl_relay_external_interrupts
assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ;
assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ;
// rule RL_rl_cpu_hart0_reset_from_soc_start
assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start =
near_mem_io$RDY_server_reset_request_put &&
plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ;
assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
// rule RL_rl_cpu_hart0_reset_complete
assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete =
near_mem_io$RDY_server_reset_response_get &&
plic$RDY_server_reset_response_get &&
cpu$RDY_hart0_server_reset_response_get &&
f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
// submodule cpu
assign cpu$dmem_master_arready = fabric_2x3$v_from_masters_0_arready ;
assign cpu$dmem_master_awready = fabric_2x3$v_from_masters_0_awready ;
assign cpu$dmem_master_bid = fabric_2x3$v_from_masters_0_bid ;
assign cpu$dmem_master_bresp = fabric_2x3$v_from_masters_0_bresp ;
assign cpu$dmem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ;
assign cpu$dmem_master_rdata = fabric_2x3$v_from_masters_0_rdata ;
assign cpu$dmem_master_rid = fabric_2x3$v_from_masters_0_rid ;
assign cpu$dmem_master_rlast = fabric_2x3$v_from_masters_0_rlast ;
assign cpu$dmem_master_rresp = fabric_2x3$v_from_masters_0_rresp ;
assign cpu$dmem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ;
assign cpu$dmem_master_wready = fabric_2x3$v_from_masters_0_wready ;
assign cpu$hart0_server_reset_request_put = f_reset_reqs$D_OUT ;
assign cpu$imem_master_arready = cpu_imem_master_arready ;
assign cpu$imem_master_awready = cpu_imem_master_awready ;
assign cpu$imem_master_bid = cpu_imem_master_bid ;
assign cpu$imem_master_bresp = cpu_imem_master_bresp ;
assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ;
assign cpu$imem_master_rdata = cpu_imem_master_rdata ;
assign cpu$imem_master_rid = cpu_imem_master_rid ;
assign cpu$imem_master_rlast = cpu_imem_master_rlast ;
assign cpu$imem_master_rresp = cpu_imem_master_rresp ;
assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ;
assign cpu$imem_master_wready = cpu_imem_master_wready ;
assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ;
assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ;
assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ;
assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ;
assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ;
assign cpu$set_watch_tohost_tohost_addr = set_watch_tohost_tohost_addr ;
assign cpu$set_watch_tohost_watch_tohost = set_watch_tohost_watch_tohost ;
assign cpu$software_interrupt_req_set_not_clear =
near_mem_io$get_sw_interrupt_req_get ;
assign cpu$timer_interrupt_req_set_not_clear =
near_mem_io$get_timer_interrupt_req_get ;
assign cpu$EN_hart0_server_reset_request_put =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign cpu$EN_hart0_server_reset_response_get =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign cpu$EN_set_verbosity = EN_set_verbosity ;
assign cpu$EN_set_watch_tohost = EN_set_watch_tohost ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = cpu_reset_server_request_put ;
assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ;
assign f_reset_reqs$DEQ =
near_mem_io$RDY_server_reset_request_put &&
plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = cpu$hart0_server_reset_response_get ;
assign f_reset_rsps$ENQ =
near_mem_io$RDY_server_reset_response_get &&
plic$RDY_server_reset_response_get &&
cpu$RDY_hart0_server_reset_response_get &&
f_reset_rsps$FULL_N ;
assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule fabric_2x3
assign fabric_2x3$set_verbosity_verbosity = 4'h0 ;
assign fabric_2x3$v_from_masters_0_araddr = cpu$dmem_master_araddr ;
assign fabric_2x3$v_from_masters_0_arburst = cpu$dmem_master_arburst ;
assign fabric_2x3$v_from_masters_0_arcache = cpu$dmem_master_arcache ;
assign fabric_2x3$v_from_masters_0_arid = cpu$dmem_master_arid ;
assign fabric_2x3$v_from_masters_0_arlen = cpu$dmem_master_arlen ;
assign fabric_2x3$v_from_masters_0_arlock = cpu$dmem_master_arlock ;
assign fabric_2x3$v_from_masters_0_arprot = cpu$dmem_master_arprot ;
assign fabric_2x3$v_from_masters_0_arqos = cpu$dmem_master_arqos ;
assign fabric_2x3$v_from_masters_0_arregion = cpu$dmem_master_arregion ;
assign fabric_2x3$v_from_masters_0_arsize = cpu$dmem_master_arsize ;
assign fabric_2x3$v_from_masters_0_arvalid = cpu$dmem_master_arvalid ;
assign fabric_2x3$v_from_masters_0_awaddr = cpu$dmem_master_awaddr ;
assign fabric_2x3$v_from_masters_0_awburst = cpu$dmem_master_awburst ;
assign fabric_2x3$v_from_masters_0_awcache = cpu$dmem_master_awcache ;
assign fabric_2x3$v_from_masters_0_awid = cpu$dmem_master_awid ;
assign fabric_2x3$v_from_masters_0_awlen = cpu$dmem_master_awlen ;
assign fabric_2x3$v_from_masters_0_awlock = cpu$dmem_master_awlock ;
assign fabric_2x3$v_from_masters_0_awprot = cpu$dmem_master_awprot ;
assign fabric_2x3$v_from_masters_0_awqos = cpu$dmem_master_awqos ;
assign fabric_2x3$v_from_masters_0_awregion = cpu$dmem_master_awregion ;
assign fabric_2x3$v_from_masters_0_awsize = cpu$dmem_master_awsize ;
assign fabric_2x3$v_from_masters_0_awvalid = cpu$dmem_master_awvalid ;
assign fabric_2x3$v_from_masters_0_bready = cpu$dmem_master_bready ;
assign fabric_2x3$v_from_masters_0_rready = cpu$dmem_master_rready ;
assign fabric_2x3$v_from_masters_0_wdata = cpu$dmem_master_wdata ;
assign fabric_2x3$v_from_masters_0_wlast = cpu$dmem_master_wlast ;
assign fabric_2x3$v_from_masters_0_wstrb = cpu$dmem_master_wstrb ;
assign fabric_2x3$v_from_masters_0_wvalid = cpu$dmem_master_wvalid ;
assign fabric_2x3$v_from_masters_1_araddr =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arburst =
2'b10 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arcache =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arid = 4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arlen =
8'b10101010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arlock = 1'b0 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arprot =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arqos =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arregion =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arsize =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arvalid = 1'd0 ;
assign fabric_2x3$v_from_masters_1_awaddr =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awburst =
2'b10 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awcache =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awid = 4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awlen =
8'b10101010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awlock = 1'b0 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awprot =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awqos =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awregion =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awsize =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awvalid = 1'd0 ;
assign fabric_2x3$v_from_masters_1_bready = 1'd0 ;
assign fabric_2x3$v_from_masters_1_rready = 1'd0 ;
assign fabric_2x3$v_from_masters_1_wdata =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_wstrb =
8'b10101010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_wvalid = 1'd0 ;
assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ;
assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ;
assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ;
assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ;
assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ;
assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ;
assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ;
assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ;
assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ;
assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ;
assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ;
assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ;
assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ;
assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ;
assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ;
assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ;
assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ;
assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ;
assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ;
assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ;
assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ;
assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ;
assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ;
assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ;
assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ;
assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ;
assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ;
assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ;
assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ;
assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ;
assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ;
assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ;
assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ;
assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign fabric_2x3$EN_set_verbosity = 1'b0 ;
// submodule near_mem_io
assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ;
assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ;
assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ;
assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ;
assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ;
assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ;
assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ;
assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ;
assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ;
assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ;
assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ;
assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ;
assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ;
assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ;
assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ;
assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ;
assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ;
assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ;
assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ;
assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ;
assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ;
assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ;
assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ;
assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ;
assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ;
assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ;
assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ;
assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ;
assign near_mem_io$set_addr_map_addr_base =
soc_map$m_near_mem_io_addr_base ;
assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ;
assign near_mem_io$EN_server_reset_request_put =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign near_mem_io$EN_server_reset_response_get =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign near_mem_io$EN_set_addr_map =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign near_mem_io$EN_get_timer_interrupt_req_get =
near_mem_io$RDY_get_timer_interrupt_req_get ;
assign near_mem_io$EN_get_sw_interrupt_req_get =
near_mem_io$RDY_get_sw_interrupt_req_get ;
// submodule plic
assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ;
assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ;
assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ;
assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ;
assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ;
assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ;
assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ;
assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ;
assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ;
assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ;
assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ;
assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ;
assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ;
assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ;
assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ;
assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ;
assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ;
assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ;
assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ;
assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ;
assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ;
assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ;
assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ;
assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ;
assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ;
assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ;
assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ;
assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ;
assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ;
assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ;
assign plic$set_verbosity_verbosity = 4'h0 ;
assign plic$v_sources_0_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ;
assign plic$v_sources_10_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ;
assign plic$v_sources_11_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ;
assign plic$v_sources_12_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ;
assign plic$v_sources_13_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ;
assign plic$v_sources_14_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ;
assign plic$v_sources_15_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ;
assign plic$v_sources_1_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ;
assign plic$v_sources_2_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ;
assign plic$v_sources_3_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ;
assign plic$v_sources_4_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ;
assign plic$v_sources_5_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ;
assign plic$v_sources_6_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ;
assign plic$v_sources_7_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ;
assign plic$v_sources_8_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ;
assign plic$v_sources_9_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ;
assign plic$EN_set_verbosity = 1'b0 ;
assign plic$EN_show_PLIC_state = 1'b0 ;
assign plic$EN_server_reset_request_put =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign plic$EN_server_reset_response_get =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 =
plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset &&
cpu$RDY_hart0_server_reset_request_put &&
f_reset_reqs$EMPTY_N ;
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start)
begin
v__h4255 = $stime;
#0;
end
v__h4249 = v__h4255 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start)
$display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4249);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete)
begin
v__h4496 = $stime;
#0;
end
v__h4490 = v__h4496 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete)
$display("%0d: Core.rl_cpu_hart0_reset_complete", v__h4490);
end
// synopsys translate_on
endmodule // mkCore
|
module antiDroopIIR_16 (
input clk,
input trig,
input signed [15:0] din,
input signed [6:0] tapWeight,
input accClr_en,
//input oflowClr,
(* shreg_extract = "no" *) output reg oflowDetect = 1'd0,
output reg signed [15:0] dout = 16'sd0);
parameter IIR_scale = 15; // define the scaling factor for the IIR multiplier, eg for 0.002 (din = 63, IIR_scale = 15).
//`define ADDPIPEREG
(* shreg_extract = "no" *) reg signed [15:0] din_del = 16'sd0;
`ifdef ADDPIPEREG (* shreg_extract = "no" *) reg signed [15:0] din_del_b = 16'sd0;
`endif
reg signed [47:0] tap = 48'sd0;
reg signed [22:0] multreg = 23'sd0;
(* equivalent_register_removal = "no" *) reg trig_a = 1'b0, trig_b = 1'b0;
wire trig_edge = trig_a & ~trig_b;
//reg trig_edge = 1'b0;
(* shreg_extract = "no" *) reg signed [6:0] tapWeight_a = 7'sd0, tapWeight_b = 7'sd0;
//wire oflow = (^tap[IIR_scale+16:IIR_scale+15]);
wire oflow = (~&tap[47:IIR_scale+15] && ~&(~tap[47:IIR_scale+15]));
always @(posedge clk) begin
//trig_edge <= trig_a & ~trig_b;
tapWeight_a <= tapWeight;
tapWeight_b <= tapWeight_a;
trig_a <= trig;
trig_b <= trig_a;
din_del <= din;
`ifdef ADDPIPEREG
din_del_b <= din_del;
multreg <= din_del*tapWeight_b;
//dout <= din_del_b + tap[IIR_scale+15:IIR_scale];
if (oflow) dout <= (tap[IIR_scale+16]) ? -16'sd32768 : 16'sd32767;
else dout <= din_del_b + tap[IIR_scale+15:IIR_scale];
`else
multreg <= din*tapWeight_b;
//dout <= din_del + tap[IIR_scale+15:IIR_scale];
if (oflow) dout <= (tap[IIR_scale+16]) ? -16'sd32768 : 16'sd32767;
else dout <= din_del + tap[IIR_scale+15:IIR_scale];
`endif
if (trig_edge && accClr_en) tap <= 48'sd0;
else tap <= multreg + tap;
//tap <= din*tapWeight + tap;
//if (oflowDetect && oflowClr) oflowDetect <= 1'b0;
//else if ((~& tap[47:IIR_scale+12]) || (& ~tap[47:IIR_scale+12])) oflowDetect <= 1'b1;
//else if ((~& tap[47:IIR_scale+12]) || (& tap[47:IIR_scale+12])) oflowDetect <= 1'b1;
//else if (^ tap[IIR_scale+16:IIR_scale+15]) oflowDetect <= 1'b1;
//else oflowDetect <= oflowDetect;
//oflowDetect <= (^tap[IIR_scale+16:IIR_scale+15]) ? 1'b1 : 1'b0;
oflowDetect <= oflow;
end
endmodule
|
/*
* Programing Notes:
1, there are four SPRs in uartlite, access using mtspr/mfspr instructions
2, the four register are:
control register
ctrl[0]: tx_start
ctrl[1]: rx_disenable
ctrl[2]: tx_interrupt_ebable - currently not in use
ctrl[3]: rx_interrupt_enable - currently not in use
ctrl[4]: interrupt status clear
Reset Status: 8'h00
bit[0]/[4] are auto-cleared when writing true-"1" into it.
status register - READ ONLY
sta[0]: transmitter status which 1 means transmitter is busy, 0 means transmitter is idle
sta[1]: receiver status which 1 means receiver is busy, 0 means receiver is idle
sta[2]: interrupt status which 1 mean interrupt status, 0 means normal status
sta[3]: transmitter interrupt status which means transmitter interrupt
sta[4]: receiver interrupt status which means receiver interrupt
receive data register
transmit data register
* Note:
1, there is no flow control, after received a byte, if second byte is coming, first byte is covered
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module dsu_uartlite(
clk, rst,
txd, rxd,
spr_dat_i,
reg_txdata, reg_txdata_we,
reg_ctrl, reg_ctrl_we,
reg_sta, reg_sta_we,
reg_rxdata, reg_rxdata_we,
sram_ce,
sram_we,
sram_addr,
sram_wdata,
download_enable
);
//
input clk;
input rst;
// uart inout
input rxd;
output txd;
// spr access interface
input [7:0] spr_dat_i;
input reg_txdata_we;
input reg_ctrl_we;
input reg_rxdata_we;
input reg_sta_we;
output [7:0] reg_txdata;
output [7:0] reg_ctrl;
output [7:0] reg_sta;
output [7:0] reg_rxdata;
// sram interface
output sram_ce;
output sram_we;
output [31:0] sram_wdata;
output [`IOCM_Word_BW-1:0] sram_addr;
// backdoor control
input download_enable;
//
// four internal SPRs for uartlite
//
reg [7:0] reg_ctrl;
reg [7:0] reg_sta;
reg [7:0] reg_txdata;
reg [7:0] reg_rxdata;
//
wire tx_start;
wire rx_enable;
reg tx_busy_d;
reg interrupt_tx;
reg interrupt_rx;
//
//
//
wire txd;
wire rxd;
wire [7:0] rx_data;
wire [7:0] rx_data_to_sram;
wire rx_data_rdy;
wire tx_busy;
wire rx_idle;
wire interrupt;
//
// SPR: control register
//
// [TBV]: coding style of auto-cleared
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_ctrl <= 8'h00;
else if(reg_ctrl[0]) // the tx_enable bit (ctrl[0]) will auto cleared after write 1
reg_ctrl[0] <= 1'b0;
else if(reg_ctrl_we)
reg_ctrl <= spr_dat_i;
else if(reg_ctrl[4]) // the int_clear bit (ctrl[4]) will auto cleared after write 1
reg_ctrl[4] <= 1'b0;
end
assign tx_start = reg_ctrl[0];
assign rx_enable = !reg_ctrl[1];
assign int_clear = reg_ctrl[4];
//
// SPR: status register
//
// tx interrupt detect
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
tx_busy_d <= 1'b0;
else
tx_busy_d <= tx_busy;
//when detect the negedge of tx_busy that means transmitter is finished
//if the tx_interrupt enable then generate interrupt of transmitter.
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
interrupt_tx <= 1'b0;
else if(!tx_busy && tx_busy_d)
interrupt_tx <= 1'b1;
else if(int_clear)
interrupt_tx <= 1'b0;
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
interrupt_rx <= 1'b0;
else if(rx_data_rdy && rx_enable)
interrupt_rx <= 1'b1;
else if(int_clear)
interrupt_rx <= 1'b0;
assign interrupt = interrupt_rx || interrupt_tx;
always@(posedge clk or `dsu_RST_EVENT rst)
if(rst==`dsu_RST_VALUE)
reg_sta <= 8'h00;
else if(reg_sta_we)
reg_sta <= spr_dat_i;
else
reg_sta <= {3'b000, interrupt_rx, interrupt_tx, interrupt, !rx_idle, tx_busy};
//
// SPR: receive data register
//
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_rxdata <= 8'h00;
else if(rx_data_rdy && rx_enable )
reg_rxdata <= rx_data;
end
//
// SPR: transmit data register
//
always@(posedge clk or `dsu_RST_EVENT rst) begin
if(rst==`dsu_RST_VALUE)
reg_txdata <= 8'h00;
else if(reg_txdata_we)
reg_txdata <= spr_dat_i;
end
//
// transmitter and receiver
//
dsu_Tx tx(
.clk(clk),
.rst(rst),
.TxD_start(tx_start),
.TxD_data(reg_txdata),
.TxD(txd),
.TxD_busy(tx_busy)
);
dsu_Rx rx(
.clk(clk),
.rst(rst),
.RxD(rxd),
.RxD_data_ready(rx_data_rdy),
.RxD_data(rx_data),
.RxD_endofpacket(),
.RxD_idle(rx_idle)
);
//
// back door mode: burn sram using received data
//
assign rx_data_to_sram = download_enable ? rx_data : 8'h00;
dsu_sram_ctrl sram_ctrl(
.clk(clk),
.rst(rst),
.rxd(rx_data_to_sram),
.rxd_ready(rx_data_rdy && download_enable),
.sram_ce(sram_ce),
.sram_we(sram_we),
.sram_addr(sram_addr),
.sram_wdata(sram_wdata),
.download_enable(download_enable)
);
endmodule
|
/****************************************
Mul Unit
- Booth Algorithm
- 32bit Adder
Make : 2010/12/07
Update :
****************************************/
`default_nettype none
module execute_mul_booth32(
//iDATA
input wire [31:0] iDATA_0,
input wire [31:0] iDATA_1,
//oDATA
output wire [63:0] oDATA,
output wire oHSF,
output wire oHOF,
output wire oHCF,
output wire oHPF,
output wire oHZF,
output wire oLSF,
output wire oLOF,
output wire oLCF,
output wire oLPF,
output wire oLZF
);
/****************************************
wire
****************************************/
wire [63:0] w_tmp_out;
wire [63:0] w0_tmp;
wire [63:0] w1_tmp;
wire [63:0] w2_tmp;
wire [63:0] w3_tmp;
wire [63:0] w4_tmp;
wire [63:0] w5_tmp;
wire [63:0] w6_tmp;
wire [63:0] w7_tmp;
wire [63:0] w8_tmp;
wire [63:0] w9_tmp;
wire [63:0] w10_tmp;
wire [63:0] w11_tmp;
wire [63:0] w12_tmp;
wire [63:0] w13_tmp;
wire [63:0] w14_tmp;
wire [63:0] w15_tmp;
wire [63:0] w16_tmp;
/****************************************
Booth - Encoder
****************************************/
assign w0_tmp = func_booth_algorithm(iDATA_0, iDATA_1[1], iDATA_1[0], 1'b0);
assign w1_tmp = func_booth_algorithm(iDATA_0, iDATA_1[3], iDATA_1[2], iDATA_1[1]);
assign w2_tmp = func_booth_algorithm(iDATA_0, iDATA_1[5], iDATA_1[4], iDATA_1[3]);
assign w3_tmp = func_booth_algorithm(iDATA_0, iDATA_1[7], iDATA_1[6], iDATA_1[5]);
assign w4_tmp = func_booth_algorithm(iDATA_0, iDATA_1[9], iDATA_1[8], iDATA_1[7]);
assign w5_tmp = func_booth_algorithm(iDATA_0, iDATA_1[11], iDATA_1[10], iDATA_1[9]);
assign w6_tmp = func_booth_algorithm(iDATA_0, iDATA_1[13], iDATA_1[12], iDATA_1[11]);
assign w7_tmp = func_booth_algorithm(iDATA_0, iDATA_1[15], iDATA_1[14], iDATA_1[13]);
assign w8_tmp = func_booth_algorithm(iDATA_0, iDATA_1[17], iDATA_1[16], iDATA_1[15]);
assign w9_tmp = func_booth_algorithm(iDATA_0, iDATA_1[19], iDATA_1[18], iDATA_1[17]);
assign w10_tmp = func_booth_algorithm(iDATA_0, iDATA_1[21], iDATA_1[20], iDATA_1[19]);
assign w11_tmp = func_booth_algorithm(iDATA_0, iDATA_1[23], iDATA_1[22], iDATA_1[21]);
assign w12_tmp = func_booth_algorithm(iDATA_0, iDATA_1[25], iDATA_1[24], iDATA_1[23]);
assign w13_tmp = func_booth_algorithm(iDATA_0, iDATA_1[27], iDATA_1[26], iDATA_1[25]);
assign w14_tmp = func_booth_algorithm(iDATA_0, iDATA_1[29], iDATA_1[28], iDATA_1[27]);
assign w15_tmp = func_booth_algorithm(iDATA_0, iDATA_1[31], iDATA_1[30], iDATA_1[29]);
assign w16_tmp = func_booth_algorithm(iDATA_0, 1'b0, 1'b0, iDATA_1[31]);
/****************************************
Booth - Exeout
****************************************/
assign w_tmp_out = w0_tmp + w1_tmp<<2 + w2_tmp<<4 + w3_tmp<<6 +
w4_tmp<<8 + w5_tmp<<10 + w6_tmp<<12 + w7_tmp<<14 +
w8_tmp<<16 + w9_tmp<<18 + w10_tmp<<20 + w11_tmp<<22 +
w12_tmp<<24 + w13_tmp<<26 + w14_tmp<<28 + w15_tmp<<30 + w16_tmp<<32;
function [63:0] func_booth_algorithm;
input [31:0] func_booth_algorithm_a;
input func_booth_algorithm_b2;
input func_booth_algorithm_b1;
input func_booth_algorithm_b0;
reg [2:0] reg_func_booth_algorithm_tmp;
reg [2:0] reg_func_booth_algorithm_cmd;
begin
reg_func_booth_algorithm_tmp = {func_booth_algorithm_b2, func_booth_algorithm_b1, func_booth_algorithm_b0};
case(reg_func_booth_algorithm_tmp)
3'h0 : reg_func_booth_algorithm_cmd = 3'h0;
3'h1 : reg_func_booth_algorithm_cmd = 3'h1;
3'h2 : reg_func_booth_algorithm_cmd = 3'h1;
3'h3 : reg_func_booth_algorithm_cmd = 3'h2;
3'h4 : reg_func_booth_algorithm_cmd = {1'b1, 2'h2};
3'h5 : reg_func_booth_algorithm_cmd = {1'b1, 2'h1};
3'h6 : reg_func_booth_algorithm_cmd = {1'b1, 2'h1};
default : reg_func_booth_algorithm_cmd = 3'h0;
endcase
if(reg_func_booth_algorithm_cmd[2] == 0)begin
//Plus
if(reg_func_booth_algorithm_cmd[1:0] == 2'h0)begin
func_booth_algorithm = {32{1'b0}};
end
else if(reg_func_booth_algorithm_cmd[1:0] == 2'h1)begin
func_booth_algorithm = {{32{1'b0}}, func_booth_algorithm_a};
end
else begin
func_booth_algorithm = {{32{1'b0}}, func_booth_algorithm_a} << 1;
end
end
else begin
if(reg_func_booth_algorithm_cmd[1:0] == 2'h0)begin
func_booth_algorithm = {32{1'b0}};
end
else if(reg_func_booth_algorithm_cmd[1:0] == 2'h1)begin
func_booth_algorithm = -{{32{1'b0}}, func_booth_algorithm_a};//(~{{32{1'b0}}, func_booth_algorithm_a}) + {{63{1'b0}}, 1'b1};
end
else begin
func_booth_algorithm = -({{32{1'b0}}, func_booth_algorithm_a} << 1);//(~({{32{1'b0}}, func_booth_algorithm_a} << 1)) + {{63{1'b0}}, 1'b1};
end
end
end
endfunction
/****************************************
Assign
****************************************/
assign oDATA = w_tmp_out;
assign oLSF = w_tmp_out[31];
assign oLCF = w_tmp_out[32];
assign oLOF = w_tmp_out[32] ^ w_tmp_out[31];
assign oLPF = w_tmp_out[0];
assign oLZF = (w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0; //(w_tmp_out[32:0] == {33{1'b0}})? 1'b1 : 1'b0;
assign oHSF = w_tmp_out[32];
assign oHCF = 1'b0;
assign oHOF = w_tmp_out[63];
assign oHPF = w_tmp_out[32];
assign oHZF = (w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0; //(w_tmp_out == {64{1'b0}})? 1'b1 : 1'b0;
endmodule
`default_nettype wire
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module daala_zynq_processing_system7_0_0 (
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB,
);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1 : 0] S_AXI_HP0_BRESP;
output [1 : 0] S_AXI_HP0_RRESP;
output [5 : 0] S_AXI_HP0_BID;
output [5 : 0] S_AXI_HP0_RID;
output [63 : 0] S_AXI_HP0_RDATA;
output [7 : 0] S_AXI_HP0_RCOUNT;
output [7 : 0] S_AXI_HP0_WCOUNT;
output [2 : 0] S_AXI_HP0_RACOUNT;
output [5 : 0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1 : 0] S_AXI_HP0_ARBURST;
input [1 : 0] S_AXI_HP0_ARLOCK;
input [2 : 0] S_AXI_HP0_ARSIZE;
input [1 : 0] S_AXI_HP0_AWBURST;
input [1 : 0] S_AXI_HP0_AWLOCK;
input [2 : 0] S_AXI_HP0_AWSIZE;
input [2 : 0] S_AXI_HP0_ARPROT;
input [2 : 0] S_AXI_HP0_AWPROT;
input [31 : 0] S_AXI_HP0_ARADDR;
input [31 : 0] S_AXI_HP0_AWADDR;
input [3 : 0] S_AXI_HP0_ARCACHE;
input [3 : 0] S_AXI_HP0_ARLEN;
input [3 : 0] S_AXI_HP0_ARQOS;
input [3 : 0] S_AXI_HP0_AWCACHE;
input [3 : 0] S_AXI_HP0_AWLEN;
input [3 : 0] S_AXI_HP0_AWQOS;
input [5 : 0] S_AXI_HP0_ARID;
input [5 : 0] S_AXI_HP0_AWID;
input [5 : 0] S_AXI_HP0_WID;
input [63 : 0] S_AXI_HP0_WDATA;
input [7 : 0] S_AXI_HP0_WSTRB;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(1),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(1),
.C_FCLK_CLK0_FREQ(100),
.C_FCLK_CLK1_FREQ(142),
.C_FCLK_CLK2_FREQ(50),
.C_FCLK_CLK3_FREQ(50)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/**
* bsg_cache_non_blocking_dma.v
*
* DMA engine
*
* @author tommy
*
*/
`include "bsg_defines.v"
module bsg_cache_non_blocking_dma
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter `BSG_INV_PARAM(ways_p)
, parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p)
, parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p)
, parameter lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p)
, parameter byte_sel_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)
, parameter tag_width_lp=(addr_width_p-lg_sets_lp-lg_block_size_in_words_lp-byte_sel_width_lp)
, parameter dma_cmd_width_lp=`bsg_cache_non_blocking_dma_cmd_width(ways_p,sets_p,tag_width_lp)
, parameter dma_pkt_width_lp=`bsg_cache_non_blocking_dma_pkt_width(addr_width_p)
, parameter data_mem_pkt_width_lp=
`bsg_cache_non_blocking_data_mem_pkt_width(ways_p,sets_p,block_size_in_words_p,data_width_p)
)
(
input clk_i
, input reset_i
// MHU
, input [dma_cmd_width_lp-1:0] dma_cmd_i
, input dma_cmd_v_i
, output logic [dma_cmd_width_lp-1:0] dma_cmd_return_o
, output logic done_o
, output logic pending_o
, input ack_i
, output logic [lg_ways_lp-1:0] curr_dma_way_id_o
, output logic [lg_sets_lp-1:0] curr_dma_index_o
, output logic curr_dma_v_o
// data_mem
, output logic data_mem_pkt_v_o
, output logic [data_mem_pkt_width_lp-1:0] data_mem_pkt_o
, input [data_width_p-1:0] data_mem_data_i
// DMA request
, output logic [dma_pkt_width_lp-1:0] dma_pkt_o
, output logic dma_pkt_v_o
, input dma_pkt_yumi_i
// DMA data in
, input [data_width_p-1:0] dma_data_i
, input dma_data_v_i
, output logic dma_data_ready_o
// DMA data out
, output logic [data_width_p-1:0] dma_data_o
, output logic dma_data_v_o
, input dma_data_yumi_i
);
// localparam
//
localparam counter_width_lp=`BSG_SAFE_CLOG2(block_size_in_words_p+1);
localparam block_offset_width_lp=byte_sel_width_lp+lg_block_size_in_words_lp;
localparam data_mask_width_lp=(data_width_p>>3);
// casting structs
//
`declare_bsg_cache_non_blocking_dma_cmd_s(ways_p,sets_p,tag_width_lp);
`declare_bsg_cache_non_blocking_dma_pkt_s(addr_width_p);
bsg_cache_non_blocking_dma_cmd_s dma_cmd_in;
bsg_cache_non_blocking_dma_cmd_s dma_cmd_r;
bsg_cache_non_blocking_dma_pkt_s dma_pkt;
assign dma_cmd_in = dma_cmd_i;
assign dma_cmd_return_o = dma_cmd_r;
assign dma_pkt_o = dma_pkt;
`declare_bsg_cache_non_blocking_data_mem_pkt_s(ways_p,sets_p,block_size_in_words_p,data_width_p);
bsg_cache_non_blocking_data_mem_pkt_s data_mem_pkt;
assign data_mem_pkt_o = data_mem_pkt;
// data_cmd dff
//
logic dma_cmd_dff_en;
bsg_dff_reset_en #(
.width_p(dma_cmd_width_lp)
) dma_cmd_dff (
.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(dma_cmd_dff_en)
,.data_i(dma_cmd_in)
,.data_o(dma_cmd_r)
);
// dma states
//
typedef enum logic [2:0] {
DMA_IDLE
,SEND_REFILL_ADDR
,SEND_EVICT_ADDR
,SEND_EVICT_DATA
,RECV_REFILL_DATA
,DMA_DONE
} dma_state_e;
dma_state_e dma_state_r;
dma_state_e dma_state_n;
// dma counter
//
logic counter_clear;
logic counter_up;
logic [counter_width_lp-1:0] counter_r;
bsg_counter_clear_up #(
.max_val_p(block_size_in_words_p)
,.init_val_p(0)
) dma_counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(counter_clear)
,.up_i(counter_up)
,.count_o(counter_r)
);
logic counter_fill_max;
logic counter_evict_max;
assign counter_fill_max = counter_r == (block_size_in_words_p-1);
assign counter_evict_max = counter_r == block_size_in_words_p;
// in fifo
//
logic in_fifo_v_lo;
logic [data_width_p-1:0] in_fifo_data_lo;
logic in_fifo_yumi_li;
bsg_fifo_1r1w_small #(
.width_p(data_width_p)
,.els_p(block_size_in_words_p)
) in_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(dma_data_i)
,.v_i(dma_data_v_i)
,.ready_o(dma_data_ready_o)
,.data_o(in_fifo_data_lo)
,.v_o(in_fifo_v_lo)
,.yumi_i(in_fifo_yumi_li)
);
// out fifo
//
logic out_fifo_v_li;
logic out_fifo_ready_lo;
logic [data_width_p-1:0] out_fifo_data_li;
bsg_two_fifo #(
.width_p(data_width_p)
) out_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(out_fifo_v_li)
,.data_i(out_fifo_data_li)
,.ready_o(out_fifo_ready_lo)
,.v_o(dma_data_v_o)
,.data_o(dma_data_o)
,.yumi_i(dma_data_yumi_i)
);
// comb logic
//
assign out_fifo_data_li = data_mem_data_i;
logic [addr_width_p-1:0] dma_pkt_refill_addr;
logic [addr_width_p-1:0] dma_pkt_evict_addr;
assign dma_pkt_refill_addr = {
dma_cmd_r.refill_tag,
dma_cmd_r.index,
{block_offset_width_lp{1'b0}}
};
assign dma_pkt_evict_addr = {
dma_cmd_r.evict_tag,
dma_cmd_r.index,
{block_offset_width_lp{1'b0}}
};
always_comb begin
done_o = 1'b0;
pending_o = 1'b0;
dma_cmd_dff_en = 1'b0;
counter_clear = 1'b0;
counter_up = 1'b0;
out_fifo_v_li = 1'b0;
in_fifo_yumi_li = 1'b0;
data_mem_pkt_v_o = 1'b0;
data_mem_pkt.write_not_read = 1'b0;
data_mem_pkt.way_id = dma_cmd_r.way_id;
data_mem_pkt.addr = {
dma_cmd_r.index,
counter_r[0+:lg_block_size_in_words_lp]
};
// for load
data_mem_pkt.sigext_op = 1'b0;
data_mem_pkt.size_op = (2)'($clog2(data_width_p>>3));
data_mem_pkt.byte_sel = (byte_sel_width_lp)'(0);
// for store
data_mem_pkt.mask_op = 1'b1;
data_mem_pkt.mask = {data_mask_width_lp{1'b1}};
data_mem_pkt.data = in_fifo_data_lo;
dma_pkt_v_o = 1'b0;
dma_pkt.write_not_read = 1'b0;
dma_pkt.addr = dma_pkt_refill_addr;
case (dma_state_r)
// Wait for dma_cmd from MHU.
DMA_IDLE: begin
dma_cmd_dff_en = dma_cmd_v_i;
dma_state_n = dma_cmd_v_i
? (dma_cmd_in.refill ? SEND_REFILL_ADDR : SEND_EVICT_ADDR)
: DMA_IDLE;
end
// Send refill address by dma_req channel.
SEND_REFILL_ADDR: begin
dma_pkt_v_o = 1'b1;
dma_pkt.write_not_read = 1'b0;
dma_pkt.addr = dma_pkt_refill_addr;
pending_o = 1'b1;
dma_state_n = dma_pkt_yumi_i
? (dma_cmd_r.evict ? SEND_EVICT_ADDR : RECV_REFILL_DATA)
: SEND_REFILL_ADDR;
end
// Send evict address by dma_req channel.
SEND_EVICT_ADDR: begin
data_mem_pkt_v_o = dma_pkt_yumi_i; // read the first word in block.
counter_up = dma_pkt_yumi_i;
counter_clear = dma_pkt_yumi_i;
dma_pkt_v_o = 1'b1;
dma_pkt.write_not_read = 1'b1;
dma_pkt.addr = dma_pkt_evict_addr;
pending_o = 1'b1;
dma_state_n = dma_pkt_yumi_i
? SEND_EVICT_DATA
: SEND_EVICT_ADDR;
end
// Read the cache block word by word, send it out by dma_data_o channel.
SEND_EVICT_DATA: begin
data_mem_pkt_v_o = out_fifo_ready_lo & ~counter_evict_max;
out_fifo_v_li = 1'b1;
counter_up = out_fifo_ready_lo & ~counter_evict_max;
counter_clear = out_fifo_ready_lo & counter_evict_max;
pending_o = 1'b1;
dma_state_n = (out_fifo_ready_lo & counter_evict_max)
? (dma_cmd_r.refill ? RECV_REFILL_DATA : DMA_DONE)
: SEND_EVICT_DATA;
end
// Receive the cache block word by word from dma_data_i channel,
// and write it to data_mem.
RECV_REFILL_DATA: begin
data_mem_pkt_v_o = in_fifo_v_lo;
data_mem_pkt.write_not_read = 1'b1;
in_fifo_yumi_li = in_fifo_v_lo;
counter_up = in_fifo_v_lo & ~counter_fill_max;
counter_clear = in_fifo_v_lo & counter_fill_max;
pending_o = 1'b1;
dma_state_n = in_fifo_v_lo & counter_fill_max
? DMA_DONE
: RECV_REFILL_DATA;
end
// DMA transaction is over, and wait for MHU to acknowledge it.
DMA_DONE: begin
done_o = 1'b1;
counter_clear = ack_i;
dma_state_n = ack_i
? DMA_IDLE
: DMA_DONE;
end
// this should never happen, but if it does, return to IDLE.
default: begin
dma_state_n = DMA_IDLE;
end
endcase
end
assign curr_dma_v_o = (dma_state_r != DMA_IDLE);
assign curr_dma_way_id_o = dma_cmd_r.way_id;
assign curr_dma_index_o = dma_cmd_r.index;
// synopsys sync_set_reset "reset_i"
always_ff @ (posedge clk_i) begin
if (reset_i) begin
dma_state_r <= DMA_IDLE;
end
else begin
dma_state_r <= dma_state_n;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_non_blocking_dma)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This test demonstrates an issue with sign extension.
// Assigning to localparms larger than 32 bits broke in 3.862
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Mike Thyer.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam [ 0:0] one1_lp = 1;
localparam [ 1:0] one2_lp = 1;
localparam [ 2:0] one3_lp = 1;
localparam [ 3:0] one4_lp = 1;
localparam [ 4:0] one5_lp = 1;
localparam [ 5:0] one6_lp = 1;
localparam [ 6:0] one7_lp = 1;
localparam [ 7:0] one8_lp = 1;
localparam [ 8:0] one9_lp = 1;
localparam [ 9:0] one10_lp = 1;
localparam [19:0] one20_lp = 1;
localparam [29:0] one30_lp = 1;
localparam [30:0] one31_lp = 1;
localparam [31:0] one32_lp = 1;
localparam [32:0] one33_lp = 1;
localparam [33:0] one34_lp = 1;
localparam [34:0] one35_lp = 1;
localparam [35:0] one36_lp = 1;
localparam [36:0] one37_lp = 1;
localparam [37:0] one38_lp = 1;
localparam [38:0] one39_lp = 1;
localparam [39:0] one40_lp = 1;
localparam [49:0] one50_lp = 1;
localparam [59:0] one60_lp = 1;
localparam [60:0] one61_lp = 1;
localparam [61:0] one62_lp = 1;
localparam [62:0] one63_lp = 1;
localparam [63:0] one64_lp = 1;
localparam [64:0] one65_lp = 1;
localparam [65:0] one66_lp = 1;
localparam [66:0] one67_lp = 1;
localparam [67:0] one68_lp = 1;
localparam [68:0] one69_lp = 1;
localparam [69:0] one70_lp = 1;
bit all_ok = 1;
initial begin
`ifdef TEST_VERBOSE
$display("one1_lp : %x %d", one1_lp, one1_lp==1);
$display("one2_lp : %x %d", one2_lp, one2_lp==1);
$display("one3_lp : %x %d", one3_lp, one3_lp==1);
$display("one4_lp : %x %d", one4_lp, one4_lp==1);
$display("one5_lp : %x %d", one5_lp, one5_lp==1);
$display("one6_lp : %x %d", one6_lp, one6_lp==1);
$display("one7_lp : %x %d", one7_lp, one7_lp==1);
$display("one8_lp : %x %d", one8_lp, one8_lp==1);
$display("one9_lp : %x %d", one9_lp, one9_lp==1);
$display("one10_lp: %x %d", one10_lp, one10_lp==1);
$display("one20_lp: %x %d", one20_lp, one20_lp==1);
$display("one30_lp: %x %d", one30_lp, one30_lp==1);
$display("one31_lp: %x %d", one31_lp, one31_lp==1);
$display("one32_lp: %x %d", one32_lp, one32_lp==1);
$display("one33_lp: %x %d", one33_lp, one33_lp==1);
$display("one34_lp: %x %d", one34_lp, one34_lp==1);
$display("one35_lp: %x %d", one35_lp, one35_lp==1);
$display("one36_lp: %x %d", one36_lp, one36_lp==1);
$display("one37_lp: %x %d", one37_lp, one37_lp==1);
$display("one38_lp: %x %d", one38_lp, one38_lp==1);
$display("one39_lp: %x %d", one39_lp, one39_lp==1);
$display("one40_lp: %x %d", one40_lp, one40_lp==1);
$display("one50_lp: %x %d", one50_lp, one50_lp==1);
$display("one60_lp: %x %d", one60_lp, one60_lp==1);
$display("one61_lp: %x %d", one61_lp, one61_lp==1);
$display("one62_lp: %x %d", one62_lp, one62_lp==1);
$display("one63_lp: %x %d", one63_lp, one63_lp==1);
$display("one64_lp: %x %d", one64_lp, one64_lp==1);
$display("one65_lp: %x %d", one65_lp, one65_lp==1);
$display("one66_lp: %x %d", one66_lp, one66_lp==1);
$display("one67_lp: %x %d", one67_lp, one67_lp==1);
$display("one68_lp: %x %d", one68_lp, one68_lp==1);
$display("one69_lp: %x %d", one69_lp, one69_lp==1);
$display("one70_lp: %x %d", one70_lp, one70_lp==1);
`endif
all_ok &= one1_lp == 1;
all_ok &= one2_lp == 1;
all_ok &= one3_lp == 1;
all_ok &= one4_lp == 1;
all_ok &= one5_lp == 1;
all_ok &= one6_lp == 1;
all_ok &= one7_lp == 1;
all_ok &= one8_lp == 1;
all_ok &= one9_lp == 1;
all_ok &= one10_lp == 1;
all_ok &= one20_lp == 1;
all_ok &= one30_lp == 1;
all_ok &= one31_lp == 1;
all_ok &= one32_lp == 1;
all_ok &= one33_lp == 1;
all_ok &= one34_lp == 1;
all_ok &= one35_lp == 1;
all_ok &= one36_lp == 1;
all_ok &= one37_lp == 1;
all_ok &= one38_lp == 1;
all_ok &= one39_lp == 1;
all_ok &= one40_lp == 1;
all_ok &= one50_lp == 1;
all_ok &= one60_lp == 1;
all_ok &= one61_lp == 1;
all_ok &= one62_lp == 1;
all_ok &= one63_lp == 1;
all_ok &= one64_lp == 1;
all_ok &= one65_lp == 1;
all_ok &= one66_lp == 1;
all_ok &= one67_lp == 1;
all_ok &= one68_lp == 1;
all_ok &= one69_lp == 1;
all_ok &= one70_lp == 1;
if (!all_ok) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// Library - static, Cell - th44w3, View - schematic
// LAST TIME SAVED: May 23 17:58:12 2014
// NETLIST TIME: May 23 17:58:31 2014
`timescale 1ns / 1ns
module th44w3 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th44w3";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N6 ( .d(net042), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net32), .g(a), .s(net44), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net042), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N10 ( .d(net32), .g(y), .s(net042), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net042), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N1 ( .d(net32), .g(a), .s(net042), .b(cds_globals.gnd_));
pfet_b P7 ( .b(cds_globals.vdd_), .g(b), .s(net027), .d(net34));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(net49), .d(net32));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net027));
pfet_b P3 ( .b(cds_globals.vdd_), .g(d), .s(net47), .d(net32));
pfet_b P2 ( .b(cds_globals.vdd_), .g(c), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net027));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net32);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
//
// Title : Bit BLT State Machine
// File : dex_smblt.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Included by dex_sm.v
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module dex_smblt
(
input de_clk,
input de_rstn,
input [1:0] dir,
input goblt,
input stpl_pk_1,
input mcrdy,
input cache_rdy,
input signx,
input signy,
input yeqz,
input xeqz,
input read_2,
input ps16_1,
input ps32_1,
input ps8_2,
input ps16_2,
input ps32_2,
input apat8_2,
input apat32_2,
input frst_pass,
input last_pass,
input multi,
input soc,
input rmw,
input eor,
input local_sol,
input frst8_1,
input mw_fip,
input eol_2,
input end_pass,
output reg [21:0] b_op,
output reg [4:0] b_ksel,
output reg b_set_busy,
output reg b_clr_busy,
output reg b_mem_req,
output reg b_mem_rd,
output reg b_ld_wcnt,
output reg b_dchgy,
output reg b_rstn_wad,
output reg b_ld_rad,
output reg b_set_sol,
output reg b_set_eol,
output reg b_set_eor,
output reg b_ld_msk,
output reg b_mul,
output reg b_mod8,
output reg b_mod32,
output reg b_rst_cr,
output reg b_set_soc,
output reg b_clr_soc,
output reg b_set_multi,
output reg b_clr_multi,
output reg b_set_frst_pass,
output reg b_clr_frst_pass,
output reg b_set_end,
output reg b_clr_end,
output reg b_set_last_pass,
output reg b_clr_last_pass,
output reg b_clr_ld_disab,
output reg b_cin,
output b_sdwn,
output b_ddwn
);
// The following are from de_param.h
//`include "de_param.h"
parameter one = 5'h1,
B_WAIT = 5'h0,
BS1 = 5'h1,
BS2 = 5'h2,
BS3 = 5'h3,
BS4 = 5'h4,
BS5 = 5'h5,
BS6 = 5'h6,
BS7 = 5'h7,
BS8 = 5'h8,
BS9 = 5'h9,
BS10 = 5'ha,
BS11 = 5'hb,
BS12 = 5'hc,
BS13 = 5'hd,
BR1 = 5'he,
BR2 = 5'hf,
BR3 = 5'h10,
BR4 = 5'h11,
BR5 = 5'h12,
BW1 = 5'h13,
BW2 = 5'h14,
BW3 = 5'h15,
BW4 = 5'h16,
BW5 = 5'h17,
BW6 = 5'h18,
BNL1 = 5'h19,
BNL2 = 5'h1a,
BNL3 = 5'h1b,
BNL4 = 5'h1c,
BNL5 = 5'h1d,
BNL6 = 5'h1e,
BNL7 = 5'h1f,
size = 5'h2, // wrk0x and wrk0y
wr_seg = 5'hd, // wrk7x
noop = 5'h0, // noop address.
pline = 5'h10,// pipeline address.
sorgl = 5'he, // src org address low nibble.
dorgl = 5'hf, // src org address low nibble.
amcn = 5'h4, // ax-k, ay-k
apcn_d = 5'h8, // {ax + const,ax + const}
amcn_d = 5'h14,// {ax - const,ax - const}
sub_d = 5'h17,// {ax - bx,ax - bx}
wrhl = 2'b00,// define write enables
wrhi = 2'b01,
wrlo = 2'b10,// define write enables
wrno = 2'b11,// define write enables
D24 = 5'hd, // not used
D48 = 5'he, // not used
D95 = 5'h10,
D94 = 5'h12,
D96 = 5'h13,
dst = 5'h1, // destination/end point
add = 5'h1, // ax + bx, ay + by
sub = 5'h12,// ax - bx, ay - by
addnib = 5'h2, // ax + bx(nibble)
movx = 5'hf, // bx--> fy, by--> fx
dst_sav = 5'h9, // dst & wrk1y
src = 5'h0, // source/start point register
src_sav = 5'ha, // src & wrk1x
mov = 5'hd, // bx--> fx, by--> fy
mov_k = 5'he, // move constant
rd_wrds = 5'h5, // wrk3x
rd_wrds_sav = 5'hb, // wrk3x & wrk5x
wr_wrds_sav = 5'hc, // wrk4x & wrk6x
div16 = 5'ha, // bx/16 + wadj.
two = 5'h2,
four = 5'h4,
eight = 5'h6,
movmod = 5'h5, // ay + by mod 8 or 32
adr_ofs = 5'h5,
mod_src = 5'h6,
apcn = 5'h6, // ax+k, ay+k
zoom = 5'h4, // wrk2x & wrk2y
nib = 5'h11,// nibble
sav_yzoom = 5'h5, // wrk3y
wr_wrds = 5'h6, // wrk4x
D16 = 5'h8,
seven = 5'h5,
D64 = 5'h11,
D112 = 5'h14,
D128 = 5'h15,
D256 = 5'h7,
sav_rd_wrds = 5'h7, // wrk5x
sav_wr_wrds = 5'h8, // wrk6x
sav_src_dst = 5'h3; // wrk1x & wrk1y
/****************************************************************/
/* DEFINE PARAMETERS */
/****************************************************************/
/* define internal wires and make assignments */
reg [4:0] b_cs;
reg [4:0] b_ns;
assign b_sdwn = ~dir[0];
assign b_ddwn = ~dir[0];
/* create the state register */
always @(posedge de_clk or negedge de_rstn) begin
if(!de_rstn) b_cs <= 5'b0;
else b_cs <= b_ns;
end
always @*
begin
b_op = 22'b00000_00000_00000_00000_11;
b_ksel = one;
b_set_busy = 1'b0;
b_clr_busy = 1'b0;
b_ld_wcnt = 1'b0;
b_mem_req = 1'b0;
b_mem_rd = 1'b0;
b_dchgy = 1'b0;
b_rstn_wad = 1'b0;
b_ld_rad = 1'b0;
b_set_sol = 1'b0;
b_set_eol = 1'b0;
b_mem_req = 1'b0;
b_mem_rd = 1'b0;
b_set_eor = 1'b0;
b_ld_msk = 1'b0;
b_mul = 1'b0;
b_mod32 = 1'b0;
b_mod8 = 1'b0;
b_rst_cr = 1'b0;
b_set_soc = 1'b0;
b_clr_soc = 1'b0;
b_set_multi = 1'b0;
b_clr_multi = 1'b0;
b_set_frst_pass = 1'b0;
b_clr_frst_pass = 1'b0;
b_set_end = 1'b0;
b_clr_end = 1'b0;
b_set_last_pass = 1'b0;
b_clr_last_pass = 1'b0;
b_clr_ld_disab = 1'b0;
b_cin = 1'b0;
case(b_cs) /* synopsys full_case parallel_case */
/* Wait for goblt. */
B_WAIT: if(goblt && !stpl_pk_1)
begin
b_ns=BS1;
b_set_busy = 1'b1;
b_set_frst_pass = 1'b1;
b_mul = 1'b1;
b_op={size,noop,amcn,noop,wrno};
if(ps32_1)b_ksel=D24;
else if(ps16_1)b_ksel=D48;
else b_ksel=D96;
end
else b_ns= B_WAIT;
/* multiply the src, dst, and size by 2 for 16BPP, or 4 for 32BPP. */
/* add org low nibble to destination point */
/* save the original destination X, to use on the next scan line. */
BS1: begin
if(frst_pass)
begin
// b_op={dst,noop,apcn_d,dst_sav,wrhl};
b_op={dorgl,dst,addnib,dst_sav,wrhl};
if(read_2)b_cin = 1'b1;
end
else b_op={wr_seg,noop,movx,size,wrlo};
if(!read_2)b_ns=BS5;
else b_ns=BS2;
b_set_sol=1'b1;
b_set_soc=1'b1;
b_clr_ld_disab = 1'b1;
// if(ps32_2) b_ksel=four;
// else if(ps16_2)b_ksel=two;
// else b_ksel=one;
end
BS2: begin
if(!read_2)b_ns=BS5;
else b_ns=BS3;
if(dir[1] & !signx & !xeqz)
begin
b_set_multi = 1'b1;
if(frst_pass)b_op={pline,noop,amcn_d,dst_sav,wrhl};
else b_op={dst,noop,amcn_d,dst_sav,wrhl};
end
else if (dir[1])
begin
b_set_last_pass = 1'b1;
if(frst_pass) b_op={pline,size,sub_d,dst_sav,wrhl};
else b_op={dst,size,sub_d,dst_sav,wrhl};
end
else b_op={pline,noop,amcn_d,dst_sav,wrhl};
if (dir[1] & frst_pass & ps32_2)b_ksel=D94;
else if(dir[1] & frst_pass & ps16_2)b_ksel=D95;
// if (dir[1] & frst_pass & ps32_2)b_ksel=D95;
// else if(dir[1] & frst_pass & ps16_2)b_ksel=D96;
else if(dir[1]) b_ksel=D96;
else b_ksel=one;
end
/* add org low nibble to source point */
/* save the original source X, to use on the next scan line. */
BS3: begin
if(frst_pass)
begin
b_op={sorgl,src,add,src_sav,wrhi};
b_cin = 1'b1;
// b_op={src,noop,apcn_d,dst_sav,wrhl};
end
// if(ps32_2) b_ksel=four;
// else if(ps16_2)b_ksel=two;
// else b_ksel=one;
b_ns=BS4;
end
BS4: begin
b_ns=BS5;
if (multi & frst_pass & !last_pass) b_op={pline,noop,amcn,src_sav,wrhi};
else if(multi & !frst_pass & !last_pass) b_op={src,noop,amcn,src_sav,wrhi};
else if(multi & frst_pass & last_pass) b_op={pline,size,sub,src_sav,wrhi};
else if(multi & !frst_pass & last_pass) b_op={src,size,sub,src_sav,wrhi};
else if(dir[1]) b_op={pline,size,sub,src_sav,wrhi};
else b_op={pline,noop,amcn,src_sav,wrhi};
if (dir[1] & frst_pass & ps32_2)b_ksel=D94;
else if(dir[1] & frst_pass & ps16_2)b_ksel=D95;
// if (dir[1] & frst_pass & ps32_2)b_ksel=D95;
// else if(dir[1] & frst_pass & ps16_2)b_ksel=D96;
else if(dir[1]) b_ksel=D96;
else b_ksel=one;
end
/* calculate the read words per line adjusted X size. */
BS5: begin
if(apat32_2 | apat8_2 | (multi & ~last_pass))b_ns=BS6;
else b_ns=BS8;
if(apat32_2 | apat8_2)b_op={noop,noop,mov_k,rd_wrds_sav,wrhi};
else if(multi & ~last_pass)b_op={size,noop,amcn,size,wrhi};
else b_op={pline,size,div16,rd_wrds_sav,wrhi};
if(multi)b_ksel=D96;
if(ps32_2 & apat32_2 & ~multi)b_ksel=eight;
if(ps16_2 & apat32_2 & ~multi)b_ksel=four;
if(ps8_2 & apat32_2 & ~multi) b_ksel=two;
if(ps32_2 & apat8_2 & ~multi)b_ksel=two;
if((ps16_2 | ps8_2) & apat8_2 & ~multi)b_ksel=one;
end
/* Calculate the offset between the source and destination. */
/* this code is exicuted for area patterns only.*/
BS6: begin
b_ns=BS7;
if(apat32_2)b_mod32 = 1'b1;
if(apat8_2)b_mod8 = 1'b1;
if(multi)b_op={noop,noop,mov_k,noop,wrno};
else b_op={noop,src,movmod,adr_ofs,wrlo};
b_ksel=D96;
end
/* this code is exicuted for area patterns only.*/
/* clear the lower 3 or 5 bits of the Y source.*/
BS7: begin
b_ns=BS8;
if(multi)b_op={src,pline,div16,rd_wrds_sav,wrhi};
else b_op={src,src,sub,mod_src,wrno};
if(apat32_2)b_mod32 = 1'b1;
if(apat8_2)b_mod8 = 1'b1;
end
/* this code is exicuted for area patterns only.*/
/* add the source offset to the source. */
BS8: begin
b_ns=BS9;
if(multi & ~last_pass)b_op={noop,noop,mov_k,noop,wrno};
else b_op={pline,dst,add,mod_src,wrlo};
if(apat32_2)b_mod32 = 1'b1;
if(apat8_2)b_mod8 = 1'b1;
b_ksel=D96;
end
/* calculate the write words per line adjusted X size. */
BS9: begin
b_ns=BS10;
if(multi & ~last_pass)b_op={dst,pline,div16,wr_wrds_sav,wrhi};
else b_op={dst,size,div16,wr_wrds_sav,wrhi};
end
/* generate the start and end mask to be loaded in BS10. */
BS10: begin
b_ns=BS11;
if(!dir[1] | last_pass)b_op={dst,size,add,noop,wrno};
else b_op={dst,size,apcn,noop,wrno};
b_rstn_wad = 1'b1;
b_ksel=D96;
end
BS11: begin
b_ld_msk=1'b1; /* load the mask. */
b_ns=BS12;
if(multi)b_op={noop,src,mov,zoom,wrlo};
end
/* source minus destination nibble mode. for FIFO ADDRESS read = write, read = write-1. */
/* this will set the first read 8 flag if source nibble is less than destination nibble.*/
BS12: begin
if(mcrdy) begin
b_ns=BS13;
b_ld_rad = 1'b1;
if(apat32_2 || apat8_2)b_op={mod_src,adr_ofs,add,src,wrlo};
else b_op={src,dst,nib,noop,wrno};
end
else b_ns=BS12;
end
BS13: begin
b_ns=BR1;
if(multi && soc)b_op={noop,dst,mov,sav_yzoom,wrlo};
b_clr_soc = 1'b1;
end
/* write words minus max page count of eight for no reads. */
/* or seven for commands with reads. */
BR1: begin
if(!read_2)
begin
b_ns=BW3;
b_op={wr_wrds,noop,amcn,noop,wrno};
if(!rmw)b_ksel=eight;
else b_ksel=four;
end
else if(eor && (apat32_2 || apat8_2))
begin
b_ns=BW3;
b_op={wr_wrds,noop,amcn,noop,wrno};
if(!rmw)b_ksel=eight;
else b_ksel=four;
end
else if(eor)
begin
b_ns=BW3;
b_ksel=seven;
b_op={wr_wrds,noop,amcn,noop,wrno};
end
else if(frst_pass)
begin
b_ns=BR2;
b_op={noop,size,movx,wr_seg,wrhi};
end
else b_ns=BR2;
b_clr_frst_pass = 1'b1;
end
/* read words minus max page count of eight reads. */
BR2: begin
b_op={rd_wrds,noop,amcn,noop,wrno};
b_ns=BR3;
if((local_sol & !frst8_1) | apat32_2 | apat8_2)b_ksel=eight;
else b_ksel=seven;
end
/* wait for the pipeline. */
/* subtract 7 or 8 from the read words. */
BR3: begin
b_ns=BR4;
b_op={rd_wrds,noop,amcn,rd_wrds,wrhi};
if((local_sol & !frst8_1) | apat32_2 | apat8_2)b_ksel=eight;
else b_ksel=seven;
end
BR4: begin
b_ld_wcnt=1'b1; /* this signal is externally delayed one clock. */
if(signx || xeqz) b_op={noop,rd_wrds,mov,noop,wrno};
if(!signx && !xeqz)b_op={noop,noop,mov_k,noop,wrno};
if(local_sol & !frst8_1)b_ksel=eight;
else b_ksel=seven;
b_ns=BR5;
end
BR5: begin
if(signx | xeqz) b_set_eor=1'b1;
b_ns=BW1;
end
/* Begin the write portion of the bit blt state machine. */
/* read words minus max page count of eight reads. */
BW1: if(mcrdy && !mw_fip)
begin
b_op={wr_wrds,noop,amcn,noop,wrno};
if(read_2 && apat32_2 && (ps8_2 || ps16_2))b_ns=BW2;
else if(read_2 && apat8_2)b_ns=BW2;
else b_ns=BW3;
if(read_2)begin
b_mem_req=1'b1;
b_mem_rd=1'b1;
end
if(read_2 && !(apat32_2 || apat8_2)) b_ksel=seven;
else if(!rmw)b_ksel=eight;
else b_ksel=four;
end
else b_ns=BW1;
BW2: if(mcrdy && !mw_fip)
begin
b_op={wr_wrds,noop,amcn,noop,wrno};
b_ns=BW3;
b_mem_req=1'b1;
b_mem_rd=1'b1;
if(read_2 && !(apat32_2 || apat8_2)) b_ksel=seven;
else if(!rmw)b_ksel=eight;
else b_ksel=four;
end
else b_ns=BW2;
/* add 128 or 112 to the source x pointer. */
BW3: begin
b_ns=BW4;
if(local_sol & !frst8_1)b_ksel=D128;
else b_ksel=D112;
if(!apat32_2)b_op={src,noop,apcn,src,wrhi};
end
/* test to see which is less and use that one. */
/* and wait if memory controller is busy. */
BW4: begin
b_ns=BW5;
if(read_2 && !(apat32_2 || apat8_2))b_ksel=seven;
else if(rmw)b_ksel=four;
else b_ksel=eight;
b_ld_wcnt=1'b1;
if(signx | xeqz)
begin
b_op={noop,wr_wrds,mov,noop,wrno};
b_set_eol=1'b1;
end
else begin
b_op={noop,noop,mov_k,noop,wrno};
end
end
/* subtract 7 from the write words. */
BW5: begin
b_ns=BW6;
b_op={wr_wrds,noop,amcn,wr_wrds,wrhi};
if(read_2 && !(apat32_2 || apat8_2))b_ksel=seven;
else if(rmw)b_ksel=four;
else b_ksel=eight;
end
/* add 128 to the destination x pointer. */
BW6: begin
if(mcrdy && !eol_2 && cache_rdy)
begin
b_mem_req=1'b1;
b_ns=BR1;
b_op={dst,noop,apcn,dst,wrhi};
if(read_2 && !(apat32_2 || apat8_2))b_ksel=D112;
else if(rmw)b_ksel=D64;
else b_ksel=D128;
end
else if(mcrdy && eol_2 && cache_rdy) /* decrement the Y size register. */
begin
b_mem_req=1'b1;
b_ns=BNL1;
b_op={size,noop,amcn,size,wrlo};
end
else b_ns=BW6;
end
/* restore the write words per line. */
BNL1: begin
b_dchgy = 1'b1;
b_op={noop,sav_wr_wrds,mov,wr_wrds,wrhi};
b_ns=BNL2;
end
/* If Y size register goes to zero the bit blt is all done. */
/* else go back and read more data. */
/* Restore the original X destination registers. */
BNL2: begin
if(yeqz & multi & ~last_pass)
begin
b_rst_cr = 1'b1;
b_ns=BNL4;
b_op={noop,sav_yzoom,mov,dst,wrlo}; // restore dst Y
b_set_end = 1'b1;
end
else if(yeqz)
begin
b_clr_last_pass = 1'b1;
b_clr_multi = 1'b1;
b_rst_cr = 1'b1;
b_clr_busy = 1'b1;
b_ns=B_WAIT;
end
else begin
if(read_2 && (apat32_2 || apat8_2))b_ns=BNL4;
else if(read_2)b_ns=BNL3;
else b_ns=BS13;
b_set_sol=1'b1;
b_op={noop,sav_src_dst,movx,dst,wrhi}; // restore dst Y
end
end
/* Increment or decrement the source Y registers. */
BNL3: begin
b_ns=BNL6;
if(dir[0])b_op={src,noop,amcn,src,wrlo};
else b_op={src,noop,apcn,src,wrlo};
end
/* increment the modulo source Y counter. */
BNL4: begin
b_ns=BNL5;
b_ksel=one;
// b_rstn_wad=1'b1;
if(apat32_2)b_mod32 = 1'b1;
if(apat8_2)b_mod8 = 1'b1;
if(multi)b_op={noop,zoom,mov,src,wrlo}; // restore src Y
else b_op={mod_src,noop,apcn,mod_src,wrlo};
end
/* add the source Y offset to the source Y. */
BNL5: begin
if(multi)
begin
b_op={noop,sav_src_dst,movx,dst,wrhi}; // restore dstx
b_ns=BNL6;
end
else
begin
b_op={pline,adr_ofs,add,src,wrlo};
b_ns=BNL6;
end
end
/* Restore the original X source registers. */
BNL6: begin
b_op={noop,sav_src_dst,mov,src,wrhi};
b_ns=BNL7;
end
/* restore the read words per line. */
BNL7: begin
if(multi & end_pass)
begin
b_op={size,noop,amcn,noop,wrno};
b_ns=BS1;
b_clr_end = 1'b1;
end
else begin
b_op={noop,sav_rd_wrds,mov,rd_wrds,wrhi};
b_ns=BS13;
end
b_ksel=D96;
end
endcase
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_buf_p3.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module cpx_buf_p3(/*AUTOARG*/
// Outputs
scache3_cpx_req_bufp3_cq, scache3_cpx_atom_bufp3_cq,
io_cpx_req_bufp3_cq, cpx_scache3_grant_bufp3_ca_l,
cpx_spc5_data_rdy_bufp3_cx, cpx_spc6_data_rdy_bufp3_cx,
cpx_spc7_data_rdy_bufp3_cx, arbcp0_cpxdp_grant_bufp3_ca_l_5,
arbcp0_cpxdp_q0_hold_bufp3_ca_5, arbcp0_cpxdp_qsel0_bufp3_ca_l_5,
arbcp0_cpxdp_qsel1_bufp3_ca_5, arbcp0_cpxdp_shift_bufp3_cx_l_5,
arbcp1_cpxdp_grant_bufp3_ca_l_5, arbcp1_cpxdp_q0_hold_bufp3_ca_5,
arbcp1_cpxdp_qsel0_bufp3_ca_l_5, arbcp1_cpxdp_qsel1_bufp3_ca_5,
arbcp1_cpxdp_shift_bufp3_cx_l_5, arbcp2_cpxdp_grant_bufp3_ca_l_5,
arbcp2_cpxdp_q0_hold_bufp3_ca_5, arbcp2_cpxdp_qsel0_bufp3_ca_l_5,
arbcp2_cpxdp_qsel1_bufp3_ca_5, arbcp2_cpxdp_shift_bufp3_cx_l_5,
arbcp3_cpxdp_grant_bufp3_ca_l_5, arbcp3_cpxdp_q0_hold_bufp3_ca_5,
arbcp3_cpxdp_qsel0_bufp3_ca_l_5, arbcp3_cpxdp_qsel1_bufp3_ca_5,
arbcp3_cpxdp_shift_bufp3_cx_l_5, arbcp4_cpxdp_grant_bufp3_ca_l_5,
arbcp4_cpxdp_q0_hold_bufp3_ca_5, arbcp4_cpxdp_qsel0_bufp3_ca_l_5,
arbcp4_cpxdp_qsel1_bufp3_ca_5, arbcp4_cpxdp_shift_bufp3_cx_l_5,
arbcp5_cpxdp_grant_bufp3_ca_l_5, arbcp5_cpxdp_q0_hold_bufp3_ca_5,
arbcp5_cpxdp_qsel0_bufp3_ca_l_5, arbcp5_cpxdp_qsel1_bufp3_ca_5,
arbcp5_cpxdp_shift_bufp3_cx_l_5, arbcp6_cpxdp_grant_bufp3_ca_l_5,
arbcp6_cpxdp_q0_hold_bufp3_ca_5, arbcp6_cpxdp_qsel0_bufp3_ca_l_5,
arbcp6_cpxdp_qsel1_bufp3_ca_5, arbcp6_cpxdp_shift_bufp3_cx_l_5,
arbcp7_cpxdp_grant_bufp3_ca_l_5, arbcp7_cpxdp_q0_hold_bufp3_ca_5,
arbcp7_cpxdp_qsel0_bufp3_ca_l_5, arbcp7_cpxdp_qsel1_bufp3_ca_5,
arbcp7_cpxdp_shift_bufp3_cx_l_5, arbcp0_cpxdp_grant_bufp3_ca_l_2,
arbcp0_cpxdp_q0_hold_bufp3_ca_2, arbcp0_cpxdp_qsel0_bufp3_ca_l_2,
arbcp0_cpxdp_qsel1_bufp3_ca_2, arbcp0_cpxdp_shift_bufp3_cx_l_2,
arbcp1_cpxdp_grant_bufp3_ca_l_2, arbcp1_cpxdp_q0_hold_bufp3_ca_2,
arbcp1_cpxdp_qsel0_bufp3_ca_l_2, arbcp1_cpxdp_qsel1_bufp3_ca_2,
arbcp1_cpxdp_shift_bufp3_cx_l_2, arbcp2_cpxdp_grant_bufp3_ca_l_2,
arbcp2_cpxdp_q0_hold_bufp3_ca_2, arbcp2_cpxdp_qsel0_bufp3_ca_l_2,
arbcp2_cpxdp_qsel1_bufp3_ca_2, arbcp2_cpxdp_shift_bufp3_cx_l_2,
arbcp3_cpxdp_grant_bufp3_ca_l_2, arbcp3_cpxdp_q0_hold_bufp3_ca_2,
arbcp3_cpxdp_qsel0_bufp3_ca_l_2, arbcp3_cpxdp_qsel1_bufp3_ca_2,
arbcp3_cpxdp_shift_bufp3_cx_l_2, arbcp4_cpxdp_grant_bufp3_ca_l_2,
arbcp4_cpxdp_q0_hold_bufp3_ca_2, arbcp4_cpxdp_qsel0_bufp3_ca_l_2,
arbcp4_cpxdp_qsel1_bufp3_ca_2, arbcp4_cpxdp_shift_bufp3_cx_l_2,
arbcp5_cpxdp_grant_bufp3_ca_l_2, arbcp5_cpxdp_q0_hold_bufp3_ca_2,
arbcp5_cpxdp_qsel0_bufp3_ca_l_2, arbcp5_cpxdp_qsel1_bufp3_ca_2,
arbcp5_cpxdp_shift_bufp3_cx_l_2, arbcp6_cpxdp_grant_bufp3_ca_l_2,
arbcp6_cpxdp_q0_hold_bufp3_ca_2, arbcp6_cpxdp_qsel0_bufp3_ca_l_2,
arbcp6_cpxdp_qsel1_bufp3_ca_2, arbcp6_cpxdp_shift_bufp3_cx_l_2,
arbcp7_cpxdp_grant_bufp3_ca_l_2, arbcp7_cpxdp_q0_hold_bufp3_ca_2,
arbcp7_cpxdp_qsel0_bufp3_ca_l_2, arbcp7_cpxdp_qsel1_bufp3_ca_2,
arbcp7_cpxdp_shift_bufp3_cx_l_2,
// Inputs
scache3_cpx_req_bufp4_cq, scache3_cpx_atom_bufp4_cq,
io_cpx_req_bufp4_cq, cpx_scache3_grant_ca, cpx_spc5_data_rdy_cx,
cpx_spc6_data_rdy_cx, cpx_spc7_data_rdy_cx,
arbcp0_cpxdp_grant_arbbf_ca_5, arbcp0_cpxdp_q0_hold_arbbf_ca_l_5,
arbcp0_cpxdp_qsel0_arbbf_ca_5, arbcp0_cpxdp_qsel1_arbbf_ca_l_5,
arbcp0_cpxdp_shift_arbbf_cx_5, arbcp1_cpxdp_grant_arbbf_ca_5,
arbcp1_cpxdp_q0_hold_arbbf_ca_l_5, arbcp1_cpxdp_qsel0_arbbf_ca_5,
arbcp1_cpxdp_qsel1_arbbf_ca_l_5, arbcp1_cpxdp_shift_arbbf_cx_5,
arbcp2_cpxdp_grant_arbbf_ca_5, arbcp2_cpxdp_q0_hold_arbbf_ca_l_5,
arbcp2_cpxdp_qsel0_arbbf_ca_5, arbcp2_cpxdp_qsel1_arbbf_ca_l_5,
arbcp2_cpxdp_shift_arbbf_cx_5, arbcp3_cpxdp_grant_arbbf_ca_5,
arbcp3_cpxdp_q0_hold_arbbf_ca_l_5, arbcp3_cpxdp_qsel0_arbbf_ca_5,
arbcp3_cpxdp_qsel1_arbbf_ca_l_5, arbcp3_cpxdp_shift_arbbf_cx_5,
arbcp4_cpxdp_grant_arbbf_ca_5, arbcp4_cpxdp_q0_hold_arbbf_ca_l_5,
arbcp4_cpxdp_qsel0_arbbf_ca_5, arbcp4_cpxdp_qsel1_arbbf_ca_l_5,
arbcp4_cpxdp_shift_arbbf_cx_5, arbcp5_cpxdp_grant_arbbf_ca_5,
arbcp5_cpxdp_q0_hold_arbbf_ca_l_5, arbcp5_cpxdp_qsel0_arbbf_ca_5,
arbcp5_cpxdp_qsel1_arbbf_ca_l_5, arbcp5_cpxdp_shift_arbbf_cx_5,
arbcp6_cpxdp_grant_arbbf_ca_5, arbcp6_cpxdp_q0_hold_arbbf_ca_l_5,
arbcp6_cpxdp_qsel0_arbbf_ca_5, arbcp6_cpxdp_qsel1_arbbf_ca_l_5,
arbcp6_cpxdp_shift_arbbf_cx_5, arbcp7_cpxdp_grant_arbbf_ca_5,
arbcp7_cpxdp_q0_hold_arbbf_ca_l_5, arbcp7_cpxdp_qsel0_arbbf_ca_5,
arbcp7_cpxdp_qsel1_arbbf_ca_l_5, arbcp7_cpxdp_shift_arbbf_cx_5,
arbcp0_cpxdp_grant_arbbf_ca_2, arbcp0_cpxdp_q0_hold_arbbf_ca_l_2,
arbcp0_cpxdp_qsel0_arbbf_ca_2, arbcp0_cpxdp_qsel1_arbbf_ca_l_2,
arbcp0_cpxdp_shift_arbbf_cx_2, arbcp1_cpxdp_grant_arbbf_ca_2,
arbcp1_cpxdp_q0_hold_arbbf_ca_l_2, arbcp1_cpxdp_qsel0_arbbf_ca_2,
arbcp1_cpxdp_qsel1_arbbf_ca_l_2, arbcp1_cpxdp_shift_arbbf_cx_2,
arbcp2_cpxdp_grant_arbbf_ca_2, arbcp2_cpxdp_q0_hold_arbbf_ca_l_2,
arbcp2_cpxdp_qsel0_arbbf_ca_2, arbcp2_cpxdp_qsel1_arbbf_ca_l_2,
arbcp2_cpxdp_shift_arbbf_cx_2, arbcp3_cpxdp_grant_arbbf_ca_2,
arbcp3_cpxdp_q0_hold_arbbf_ca_l_2, arbcp3_cpxdp_qsel0_arbbf_ca_2,
arbcp3_cpxdp_qsel1_arbbf_ca_l_2, arbcp3_cpxdp_shift_arbbf_cx_2,
arbcp4_cpxdp_grant_arbbf_ca_2, arbcp4_cpxdp_q0_hold_arbbf_ca_l_2,
arbcp4_cpxdp_qsel0_arbbf_ca_2, arbcp4_cpxdp_qsel1_arbbf_ca_l_2,
arbcp4_cpxdp_shift_arbbf_cx_2, arbcp5_cpxdp_grant_arbbf_ca_2,
arbcp5_cpxdp_q0_hold_arbbf_ca_l_2, arbcp5_cpxdp_qsel0_arbbf_ca_2,
arbcp5_cpxdp_qsel1_arbbf_ca_l_2, arbcp5_cpxdp_shift_arbbf_cx_2,
arbcp6_cpxdp_grant_arbbf_ca_2, arbcp6_cpxdp_q0_hold_arbbf_ca_l_2,
arbcp6_cpxdp_qsel0_arbbf_ca_2, arbcp6_cpxdp_qsel1_arbbf_ca_l_2,
arbcp6_cpxdp_shift_arbbf_cx_2, arbcp7_cpxdp_grant_arbbf_ca_2,
arbcp7_cpxdp_q0_hold_arbbf_ca_l_2, arbcp7_cpxdp_qsel0_arbbf_ca_2,
arbcp7_cpxdp_qsel1_arbbf_ca_l_2, arbcp7_cpxdp_shift_arbbf_cx_2
);
output [7:0] scache3_cpx_req_bufp3_cq ;
output scache3_cpx_atom_bufp3_cq ;
output [7:0] io_cpx_req_bufp3_cq ;
output [7:0] cpx_scache3_grant_bufp3_ca_l;
output cpx_spc5_data_rdy_bufp3_cx;
output cpx_spc6_data_rdy_bufp3_cx;
output cpx_spc7_data_rdy_bufp3_cx;
output arbcp0_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp0_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp0_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp0_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp0_cpxdp_shift_bufp3_cx_l_5 ;
output arbcp1_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp1_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp1_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp1_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp1_cpxdp_shift_bufp3_cx_l_5 ;
output arbcp2_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp2_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp2_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp2_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp2_cpxdp_shift_bufp3_cx_l_5 ;
output arbcp3_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp3_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp3_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp3_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp3_cpxdp_shift_bufp3_cx_l_5 ;
output arbcp4_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp4_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp4_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp4_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp4_cpxdp_shift_bufp3_cx_l_5 ;
output arbcp5_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp5_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp5_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp5_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp5_cpxdp_shift_bufp3_cx_l_5 ;
output arbcp6_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp6_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp6_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp6_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp6_cpxdp_shift_bufp3_cx_l_5 ;
output arbcp7_cpxdp_grant_bufp3_ca_l_5 ;
output arbcp7_cpxdp_q0_hold_bufp3_ca_5 ;
output arbcp7_cpxdp_qsel0_bufp3_ca_l_5 ;
output arbcp7_cpxdp_qsel1_bufp3_ca_5 ;
output arbcp7_cpxdp_shift_bufp3_cx_l_5 ;
input [7:0] scache3_cpx_req_bufp4_cq;
input scache3_cpx_atom_bufp4_cq;
input [7:0] io_cpx_req_bufp4_cq;
input [7:0] cpx_scache3_grant_ca;
input cpx_spc5_data_rdy_cx;
input cpx_spc6_data_rdy_cx;
input cpx_spc7_data_rdy_cx;
input arbcp0_cpxdp_grant_arbbf_ca_5;
input arbcp0_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp0_cpxdp_qsel0_arbbf_ca_5;
input arbcp0_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp0_cpxdp_shift_arbbf_cx_5;
input arbcp1_cpxdp_grant_arbbf_ca_5;
input arbcp1_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp1_cpxdp_qsel0_arbbf_ca_5;
input arbcp1_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp1_cpxdp_shift_arbbf_cx_5;
input arbcp2_cpxdp_grant_arbbf_ca_5;
input arbcp2_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp2_cpxdp_qsel0_arbbf_ca_5;
input arbcp2_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp2_cpxdp_shift_arbbf_cx_5;
input arbcp3_cpxdp_grant_arbbf_ca_5;
input arbcp3_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp3_cpxdp_qsel0_arbbf_ca_5;
input arbcp3_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp3_cpxdp_shift_arbbf_cx_5;
input arbcp4_cpxdp_grant_arbbf_ca_5;
input arbcp4_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp4_cpxdp_qsel0_arbbf_ca_5;
input arbcp4_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp4_cpxdp_shift_arbbf_cx_5;
input arbcp5_cpxdp_grant_arbbf_ca_5;
input arbcp5_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp5_cpxdp_qsel0_arbbf_ca_5;
input arbcp5_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp5_cpxdp_shift_arbbf_cx_5;
input arbcp6_cpxdp_grant_arbbf_ca_5;
input arbcp6_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp6_cpxdp_qsel0_arbbf_ca_5;
input arbcp6_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp6_cpxdp_shift_arbbf_cx_5;
input arbcp7_cpxdp_grant_arbbf_ca_5;
input arbcp7_cpxdp_q0_hold_arbbf_ca_l_5;
input arbcp7_cpxdp_qsel0_arbbf_ca_5;
input arbcp7_cpxdp_qsel1_arbbf_ca_l_5;
input arbcp7_cpxdp_shift_arbbf_cx_5;
output arbcp0_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp0_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp0_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp0_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp0_cpxdp_shift_bufp3_cx_l_2 ;
output arbcp1_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp1_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp1_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp1_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp1_cpxdp_shift_bufp3_cx_l_2 ;
output arbcp2_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp2_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp2_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp2_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp2_cpxdp_shift_bufp3_cx_l_2 ;
output arbcp3_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp3_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp3_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp3_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp3_cpxdp_shift_bufp3_cx_l_2 ;
output arbcp4_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp4_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp4_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp4_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp4_cpxdp_shift_bufp3_cx_l_2 ;
output arbcp5_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp5_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp5_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp5_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp5_cpxdp_shift_bufp3_cx_l_2 ;
output arbcp6_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp6_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp6_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp6_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp6_cpxdp_shift_bufp3_cx_l_2 ;
output arbcp7_cpxdp_grant_bufp3_ca_l_2 ;
output arbcp7_cpxdp_q0_hold_bufp3_ca_2 ;
output arbcp7_cpxdp_qsel0_bufp3_ca_l_2 ;
output arbcp7_cpxdp_qsel1_bufp3_ca_2 ;
output arbcp7_cpxdp_shift_bufp3_cx_l_2 ;
input arbcp0_cpxdp_grant_arbbf_ca_2;
input arbcp0_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp0_cpxdp_qsel0_arbbf_ca_2;
input arbcp0_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp0_cpxdp_shift_arbbf_cx_2;
input arbcp1_cpxdp_grant_arbbf_ca_2;
input arbcp1_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp1_cpxdp_qsel0_arbbf_ca_2;
input arbcp1_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp1_cpxdp_shift_arbbf_cx_2;
input arbcp2_cpxdp_grant_arbbf_ca_2;
input arbcp2_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp2_cpxdp_qsel0_arbbf_ca_2;
input arbcp2_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp2_cpxdp_shift_arbbf_cx_2;
input arbcp3_cpxdp_grant_arbbf_ca_2;
input arbcp3_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp3_cpxdp_qsel0_arbbf_ca_2;
input arbcp3_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp3_cpxdp_shift_arbbf_cx_2;
input arbcp4_cpxdp_grant_arbbf_ca_2;
input arbcp4_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp4_cpxdp_qsel0_arbbf_ca_2;
input arbcp4_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp4_cpxdp_shift_arbbf_cx_2;
input arbcp5_cpxdp_grant_arbbf_ca_2;
input arbcp5_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp5_cpxdp_qsel0_arbbf_ca_2;
input arbcp5_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp5_cpxdp_shift_arbbf_cx_2;
input arbcp6_cpxdp_grant_arbbf_ca_2;
input arbcp6_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp6_cpxdp_qsel0_arbbf_ca_2;
input arbcp6_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp6_cpxdp_shift_arbbf_cx_2;
input arbcp7_cpxdp_grant_arbbf_ca_2;
input arbcp7_cpxdp_q0_hold_arbbf_ca_l_2;
input arbcp7_cpxdp_qsel0_arbbf_ca_2;
input arbcp7_cpxdp_qsel1_arbbf_ca_l_2;
input arbcp7_cpxdp_shift_arbbf_cx_2;
assign scache3_cpx_req_bufp3_cq[7:0] = scache3_cpx_req_bufp4_cq[7:0];
assign scache3_cpx_atom_bufp3_cq = scache3_cpx_atom_bufp4_cq;
assign io_cpx_req_bufp3_cq[7:0] = io_cpx_req_bufp4_cq[7:0];
assign cpx_scache3_grant_bufp3_ca_l = ~cpx_scache3_grant_ca;
assign cpx_spc5_data_rdy_bufp3_cx = cpx_spc5_data_rdy_cx;
assign cpx_spc6_data_rdy_bufp3_cx = cpx_spc6_data_rdy_cx;
assign cpx_spc7_data_rdy_bufp3_cx = cpx_spc7_data_rdy_cx;
assign arbcp0_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp0_cpxdp_grant_arbbf_ca_5;
assign arbcp0_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp0_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp0_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp0_cpxdp_qsel0_arbbf_ca_5;
assign arbcp0_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp0_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp0_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp0_cpxdp_shift_arbbf_cx_5;
assign arbcp1_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp1_cpxdp_grant_arbbf_ca_5;
assign arbcp1_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp1_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp1_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp1_cpxdp_qsel0_arbbf_ca_5;
assign arbcp1_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp1_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp1_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp1_cpxdp_shift_arbbf_cx_5;
assign arbcp2_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp2_cpxdp_grant_arbbf_ca_5;
assign arbcp2_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp2_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp2_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp2_cpxdp_qsel0_arbbf_ca_5;
assign arbcp2_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp2_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp2_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp2_cpxdp_shift_arbbf_cx_5;
assign arbcp3_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp3_cpxdp_grant_arbbf_ca_5;
assign arbcp3_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp3_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp3_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp3_cpxdp_qsel0_arbbf_ca_5;
assign arbcp3_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp3_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp3_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp3_cpxdp_shift_arbbf_cx_5;
assign arbcp4_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp4_cpxdp_grant_arbbf_ca_5;
assign arbcp4_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp4_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp4_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp4_cpxdp_qsel0_arbbf_ca_5;
assign arbcp4_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp4_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp4_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp4_cpxdp_shift_arbbf_cx_5;
assign arbcp5_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp5_cpxdp_grant_arbbf_ca_5;
assign arbcp5_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp5_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp5_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp5_cpxdp_qsel0_arbbf_ca_5;
assign arbcp5_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp5_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp5_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp5_cpxdp_shift_arbbf_cx_5;
assign arbcp6_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp6_cpxdp_grant_arbbf_ca_5;
assign arbcp6_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp6_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp6_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp6_cpxdp_qsel0_arbbf_ca_5;
assign arbcp6_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp6_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp6_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp6_cpxdp_shift_arbbf_cx_5;
assign arbcp7_cpxdp_grant_bufp3_ca_l_5 = ~ arbcp7_cpxdp_grant_arbbf_ca_5;
assign arbcp7_cpxdp_q0_hold_bufp3_ca_5 = ~ arbcp7_cpxdp_q0_hold_arbbf_ca_l_5;
assign arbcp7_cpxdp_qsel0_bufp3_ca_l_5 = ~ arbcp7_cpxdp_qsel0_arbbf_ca_5;
assign arbcp7_cpxdp_qsel1_bufp3_ca_5 = ~ arbcp7_cpxdp_qsel1_arbbf_ca_l_5;
assign arbcp7_cpxdp_shift_bufp3_cx_l_5 = ~ arbcp7_cpxdp_shift_arbbf_cx_5;
assign arbcp0_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp0_cpxdp_grant_arbbf_ca_2;
assign arbcp0_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp0_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp0_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp0_cpxdp_qsel0_arbbf_ca_2;
assign arbcp0_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp0_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp0_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp0_cpxdp_shift_arbbf_cx_2;
assign arbcp1_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp1_cpxdp_grant_arbbf_ca_2;
assign arbcp1_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp1_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp1_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp1_cpxdp_qsel0_arbbf_ca_2;
assign arbcp1_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp1_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp1_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp1_cpxdp_shift_arbbf_cx_2;
assign arbcp2_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp2_cpxdp_grant_arbbf_ca_2;
assign arbcp2_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp2_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp2_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp2_cpxdp_qsel0_arbbf_ca_2;
assign arbcp2_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp2_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp2_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp2_cpxdp_shift_arbbf_cx_2;
assign arbcp3_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp3_cpxdp_grant_arbbf_ca_2;
assign arbcp3_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp3_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp3_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp3_cpxdp_qsel0_arbbf_ca_2;
assign arbcp3_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp3_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp3_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp3_cpxdp_shift_arbbf_cx_2;
assign arbcp4_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp4_cpxdp_grant_arbbf_ca_2;
assign arbcp4_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp4_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp4_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp4_cpxdp_qsel0_arbbf_ca_2;
assign arbcp4_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp4_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp4_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp4_cpxdp_shift_arbbf_cx_2;
assign arbcp5_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp5_cpxdp_grant_arbbf_ca_2;
assign arbcp5_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp5_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp5_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp5_cpxdp_qsel0_arbbf_ca_2;
assign arbcp5_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp5_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp5_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp5_cpxdp_shift_arbbf_cx_2;
assign arbcp6_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp6_cpxdp_grant_arbbf_ca_2;
assign arbcp6_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp6_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp6_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp6_cpxdp_qsel0_arbbf_ca_2;
assign arbcp6_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp6_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp6_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp6_cpxdp_shift_arbbf_cx_2;
assign arbcp7_cpxdp_grant_bufp3_ca_l_2 = ~ arbcp7_cpxdp_grant_arbbf_ca_2;
assign arbcp7_cpxdp_q0_hold_bufp3_ca_2 = ~ arbcp7_cpxdp_q0_hold_arbbf_ca_l_2;
assign arbcp7_cpxdp_qsel0_bufp3_ca_l_2 = ~ arbcp7_cpxdp_qsel0_arbbf_ca_2;
assign arbcp7_cpxdp_qsel1_bufp3_ca_2 = ~ arbcp7_cpxdp_qsel1_arbbf_ca_l_2;
assign arbcp7_cpxdp_shift_bufp3_cx_l_2 = ~ arbcp7_cpxdp_shift_arbbf_cx_2;
endmodule // cpx_grant_ff
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// bcam_tb.v: A Test-bench for Binary Content Addressasble Memories (BCAM) //
// //
// Author: Ameer M.S. Abdelhadi ([email protected], [email protected]) //
// SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 //
////////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`include "utils.vh"
// deine simulation mode
`define SIM
module bcam_tb;
// simulation parameter
localparam CAMD = `CAMD ; // memory depth
localparam CAMW = `CAMW ; // data width
localparam SEGW = `SEGW ; // segment width for Segmented Transposed-RAM implementation
localparam CYCC = `CYCC ; // simulation cycles count
localparam CYCT = 10 ; // cycle time
localparam RSTT = 5.2*CYCT ; // reset time
localparam VERBOSE = 2 ; // verbose logging (0: no; 1: level 1; 2: level 2)
localparam TERFAIL = 0 ; // terminate if fail?
localparam TIMEOUT = 2*CYCT*CYCC; // simulation time
localparam ADDRW = `log2(CAMD); // CAM address width = log2 (CAM depth)
// enumerate implementations
localparam REG = 3'b000; // register-based
localparam TRS = 3'b001; // transposed-RAM stage
localparam TRC = 3'b010; // transposed-RAM cascade
localparam STR = 3'b011; // segmented transposed-RAM
localparam ALL = 3'b100; // all implementations
reg clk = 1'b0; // global clock
reg rst = 1'b1; // global reset
reg wEnb= 1'b0; // write enable
reg [CAMW -1:0] wPatt, mPatt; // patterns
reg [ADDRW-1:0] wAddr ; // write address
wire [ADDRW-1:0] mAddrBhv, mAddrReg, mAddrTRS, mAddrTRC, mAddrSTR; // match addresses
wire matchBhv, matchReg, matchTRS, matchTRC, matchSTR; // match indicators
// registered outputs
reg [ADDRW-1:0] mAddrRegR; // addresses
reg matchRegR; // match indicator
integer cycc=0; // cycles count
// generate clock and reset
always #(CYCT/2) clk = !clk; // toggle clock
integer rep_fd, ferr;
initial begin
// lower reset
#(RSTT ) rst = 1'b0;
//////////////////////////////////////////////
// print header to results file
rep_fd = $fopen("sim.res","r"); // try to open report file for read
$ferror(rep_fd,ferr); // detect error
$fclose(rep_fd);
rep_fd = $fopen("sim.res","a+"); // open report file for append
if (ferr) begin // if file is new (can't open for read); write header
$fwrite(rep_fd,"* REG: Register-based Binary Content Addressasble Memory\n");
$fwrite(rep_fd,"* TRS: Transposed-RAM Binary Content Addressasble Memory stage\n");
$fwrite(rep_fd,"* TRC: Transposed-RAM Binary Content Addressasble Memory cascade\n");
$fwrite(rep_fd,"* STR: Segmented Transposed-RAM Binary Content Addressasble Memory\n\n");
$fwrite(rep_fd,"BCAM Architectural Parameters # Simulation Mismatches\n");
$fwrite(rep_fd,"=============================== =======================\n");
$fwrite(rep_fd,"CAM Pattern Segment Simula. REG TRS TRC STR \n");
$fwrite(rep_fd,"Depth Width Width Cycles \n");
$fwrite(rep_fd,"=========================================================\n");
end
// print header
$write("Simulating BAM with the following parameters:\n");
$write("CAM depth : %0d\n",CAMD);
$write("Pattern width : %0d\n",CAMW);
$write("Segment width (STRAM): %0d\n",SEGW);
$write("Simulation Cycles : %0d\n",CYCC);
// print header if no verbose
if (VERBOSE==1)
$write("\n 1k 2k 3k 4k 5k 6k 7k 8k 9k ");
end
reg [5:0] pass; // result for each implementation
integer failCntReg = 0; // failures count
integer failCntTRS = 0; // failures count
integer failCntTRC = 0; // failures count
integer failCntSTR = 0; // failures count
integer failCntAll = 0; // failures count
integer failCntTmp = 0; // failures count / temporal/ per few cycles
always @(negedge clk) begin
if (!rst) begin
// Generate random inputs
if ( !wEnb) begin
`GETRAND( wEnb,1 );
`GETRAND(wAddr,ADDRW);
`GETRAND(wPatt,CAMW );
end else wEnb = 1'b0;
`GETRAND(mPatt,CAMW );
// write input data
if (VERBOSE==2) $write("%-7d: ",cycc);
#(CYCT/10) // a little after falling edge
if (VERBOSE==2) $write("Before rise: wEnb=%h; wAddr=%h; wPatt=%h; mPatt=%h --- ",wEnb,wAddr,wPatt,mPatt);
#(CYCT/2) // a little after rising edge
if (VERBOSE==2) $write("After rise: match=(%b,%b,%b,%b,%b); mAddr=(%h,%h,%h,%h,%h) --- ",matchBhv,matchRegR,matchTRS,matchTRC,matchSTR,mAddrBhv,mAddrRegR,mAddrTRS,mAddrTRC,mAddrSTR);
pass[REG] = !(matchBhv || matchRegR) || (matchBhv && matchRegR && (mAddrBhv===mAddrRegR));
pass[TRS] = !(matchBhv || matchTRS ) || (matchBhv && matchTRS && (mAddrBhv===mAddrTRS ));
pass[TRC] = !(matchBhv || matchTRC ) || (matchBhv && matchTRC && (mAddrBhv===mAddrTRC ));
pass[STR] = !(matchBhv || matchSTR ) || (matchBhv && matchSTR && (mAddrBhv===mAddrSTR ));
pass[ALL] = pass[REG] && pass[TRS] && pass[TRC] && pass[STR];
if (!pass[REG]) failCntReg = failCntReg + 1;
if (!pass[TRS]) failCntTRS = failCntTRS + 1;
if (!pass[TRC]) failCntTRC = failCntTRC + 1;
if (!pass[STR]) failCntSTR = failCntSTR + 1;
if (!pass[ALL]) failCntAll = failCntAll + 1;
failCntTmp = failCntAll ;
if (VERBOSE==2) $write("%s\n",pass[ALL]?"Pass":"Fail");
if (VERBOSE==1) begin
if ((cycc%10000)==0) $write("\n%4d X 10k: ",cycc/10000);
else if ((cycc%1000 )==0) $write("|");
if ((cycc%100 )==0) begin
if (failCntTmp>0) $write("x"); else $write("-");
end
failCntTmp = 0;
end
// finish if terminate on any failure
if (TERFAIL && (!pass[ALL])) begin
$write("*** Simulation terminated due to output mismatch\n");
$fclose(rep_fd);
$finish;
end
if (cycc==CYCC) begin
// write to report file
$fwrite(rep_fd,"%-7d %-7d %-7d %-7d %-5d %-5d %-5d %-5d\n",CAMD,CAMW,SEGW,CYCC,failCntReg,failCntTRS,failCntTRC,failCntSTR);
// write to STDOUT
$write("\n*** Simulation terminated after %0d cycles with %0d failures. Results:\n",CYCC,failCntAll);
$write("REG = %-5d mismatches\n",failCntReg);
$write("TRS = %-5d mismatches\n",failCntTRS);
$write("TRC = %-5d mismatches\n",failCntTRC);
$write("STR = %-5d mismatches\n",failCntSTR);
$fclose(rep_fd);
$finish;
end
cycc=cycc+1;
end
end
// Behavioral BCAM
bcam #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE)
.REGW ( 1 ), // binary / register write inputs wEnb, wAddr, & wPatt?
.REGM ( 0 ), // binary / register match input mPatt?
.REGO ( 1 ), // binary / register outputs match & mAddr?
.TYPE ( "BHV" )) // implementation type: BHV, REG, TRAM, STRAM
bcam_bhv_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnb ), // write enable
.wAddr( wAddr ), // write address
.wPatt( wPatt ), // write pattern
.mPatt( mPatt ), // patern to match
.match( matchBhv ), // match indicator
.mAddr( mAddrBhv )); // matched address
// Register-based BCAM
bcam #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE)
.REGW ( 0 ), // binary / register write inputs wEnb, wAddr, & wPatt?
.REGM ( 0 ), // binary / register match input mPatt?
.REGO ( 1 ), // binary / register outputs match & mAddr?
.TYPE ( "REG" )) // implementation type: BHV, REG, TRAM, STRAM
bcam_reg_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnb ), // write enable
.wAddr( wAddr ), // write address / [`log2(CAMD)-1:0]
.wPatt( wPatt ), // write pattern / [ CAMW -1:0]
.mPatt( mPatt ), // patern to match / [ CAMW -1:0]
.match( matchReg ), // match indicator
.mAddr( mAddrReg )); // matched address / [`log2(CAMD)-1:0]
// Transposed-RAM stage (Brute-Force) BCAM
bcam #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE)
.REGW ( 0 ), // binary / register write inputs wEnb, wAddr, & wPatt?
.REGM ( 0 ), // binary / register match input mPatt?
.REGO ( 1 ), // binary / register outputs match & mAddr?
.BRAM ( "M20K" ), // BRAM type- "M20K":Altera's M20K; "GEN":generic
.TYPE ( "TRS" )) // implementation type: BHV, REG, TRAM, STRAM
bcam_trs_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnb ), // write enable
.wAddr( wAddr ), // write address / [`log2(CAMD)-1:0]
.wPatt( wPatt ), // write pattern / [ CAMW -1:0]
.mPatt( mPatt ), // patern to match / [ CAMW -1:0]
.match( matchTRS ), // match indicator
.mAddr( mAddrTRS )); // matched address / [`log2(CAMD)-1:0]
// Transposed-RAM cascade (Brute-Force) BCAM
bcam #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE)
.REGW ( 0 ), // binary / register write inputs wEnb, wAddr, & wPatt?
.REGM ( 0 ), // binary / register match input mPatt?
.REGO ( 1 ), // binary / register outputs match & mAddr?
.BRAM ( "M20K" ), // BRAM type- "M20K":Altera's M20K; "GEN":generic
.TYPE ( "TRC" )) // implementation type: BHV, REG, TRAM, STRAM
bcam_trc_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnb ), // write enable
.wAddr( wAddr ), // write address / [`log2(CAMD)-1:0]
.wPatt( wPatt ), // write pattern / [ CAMW -1:0]
.mPatt( mPatt ), // patern to match / [ CAMW -1:0]
.match( matchTRC ), // match indicator
.mAddr( mAddrTRC )); // matched address / [`log2(CAMD)-1:0]
// Segmented Transposed-RAM BCAM
bcam #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.SEGW ( SEGW ), // Segment width
.INOM ( 1 ), // binary / Initial CAM with no match (has priority over IFILE)
.REGW ( 0 ), // binary / register write inputs wEnb, wAddr, & wPatt?
.REGM ( 0 ), // binary / register match input mPatt?
.REGO ( 0 ), // binary / register outputs match & mAddr?
.BRAM ( "M20K" ), // BRAM type- "M20K":Altera's M20K; "GEN":generic
.TYPE ( "STRAM" )) // implementation type: BHV, REG, TRAM, STRAM
bcam_str_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnb ), // write enable
.wAddr( wAddr ), // write address / [`log2(CAMD)-1:0]
.wPatt( wPatt ), // write pattern / [ CAMW -1:0]
.mPatt( mPatt ), // patern to match / [ CAMW -1:0]
.match( matchSTR ), // match indicator
.mAddr( mAddrSTR )); // matched address / [`log2(CAMD)-1:0]
// Register outputs / second stage
always @(posedge clk, posedge rst)
if (rst) {mAddrRegR,matchRegR} <= {(ADDRW +1 ){1'b0}};
else {mAddrRegR,matchRegR} <= { mAddrReg,matchReg };
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_cpu_reset_server_request_put O 1 reg
// cpu_reset_server_response_get O 1 reg
// RDY_cpu_reset_server_response_get O 1 reg
// cpu_imem_master_awvalid O 1 reg
// cpu_imem_master_awid O 4 reg
// cpu_imem_master_awaddr O 64 reg
// cpu_imem_master_awlen O 8 reg
// cpu_imem_master_awsize O 3 reg
// cpu_imem_master_awburst O 2 reg
// cpu_imem_master_awlock O 1 reg
// cpu_imem_master_awcache O 4 reg
// cpu_imem_master_awprot O 3 reg
// cpu_imem_master_awqos O 4 reg
// cpu_imem_master_awregion O 4 reg
// cpu_imem_master_wvalid O 1 reg
// cpu_imem_master_wdata O 64 reg
// cpu_imem_master_wstrb O 8 reg
// cpu_imem_master_wlast O 1 reg
// cpu_imem_master_bready O 1 reg
// cpu_imem_master_arvalid O 1 reg
// cpu_imem_master_arid O 4 reg
// cpu_imem_master_araddr O 64 reg
// cpu_imem_master_arlen O 8 reg
// cpu_imem_master_arsize O 3 reg
// cpu_imem_master_arburst O 2 reg
// cpu_imem_master_arlock O 1 reg
// cpu_imem_master_arcache O 4 reg
// cpu_imem_master_arprot O 3 reg
// cpu_imem_master_arqos O 4 reg
// cpu_imem_master_arregion O 4 reg
// cpu_imem_master_rready O 1 reg
// core_mem_master_awvalid O 1 reg
// core_mem_master_awid O 4 reg
// core_mem_master_awaddr O 64 reg
// core_mem_master_awlen O 8 reg
// core_mem_master_awsize O 3 reg
// core_mem_master_awburst O 2 reg
// core_mem_master_awlock O 1 reg
// core_mem_master_awcache O 4 reg
// core_mem_master_awprot O 3 reg
// core_mem_master_awqos O 4 reg
// core_mem_master_awregion O 4 reg
// core_mem_master_wvalid O 1 reg
// core_mem_master_wdata O 64 reg
// core_mem_master_wstrb O 8 reg
// core_mem_master_wlast O 1 reg
// core_mem_master_bready O 1 reg
// core_mem_master_arvalid O 1 reg
// core_mem_master_arid O 4 reg
// core_mem_master_araddr O 64 reg
// core_mem_master_arlen O 8 reg
// core_mem_master_arsize O 3 reg
// core_mem_master_arburst O 2 reg
// core_mem_master_arlock O 1 reg
// core_mem_master_arcache O 4 reg
// core_mem_master_arprot O 3 reg
// core_mem_master_arqos O 4 reg
// core_mem_master_arregion O 4 reg
// core_mem_master_rready O 1 reg
// dma_server_awready O 1 const
// dma_server_wready O 1 const
// dma_server_bvalid O 1 const
// dma_server_bid O 16 const
// dma_server_bresp O 2 const
// dma_server_arready O 1 const
// dma_server_rvalid O 1 const
// dma_server_rid O 16 const
// dma_server_rdata O 512 const
// dma_server_rresp O 2 const
// dma_server_rlast O 1 const
// RDY_set_verbosity O 1 const
// RDY_set_watch_tohost O 1 const
// mv_tohost_value O 64 reg
// RDY_mv_tohost_value O 1 const
// RDY_ma_ddr4_ready O 1 const
// mv_status O 8
// RST_N_dm_power_on_reset I 1 unused
// CLK I 1 clock
// RST_N I 1 reset
// cpu_reset_server_request_put I 1 reg
// cpu_imem_master_awready I 1
// cpu_imem_master_wready I 1
// cpu_imem_master_bvalid I 1
// cpu_imem_master_bid I 4 reg
// cpu_imem_master_bresp I 2 reg
// cpu_imem_master_arready I 1
// cpu_imem_master_rvalid I 1
// cpu_imem_master_rid I 4 reg
// cpu_imem_master_rdata I 64 reg
// cpu_imem_master_rresp I 2 reg
// cpu_imem_master_rlast I 1 reg
// core_mem_master_awready I 1
// core_mem_master_wready I 1
// core_mem_master_bvalid I 1
// core_mem_master_bid I 4 reg
// core_mem_master_bresp I 2 reg
// core_mem_master_arready I 1
// core_mem_master_rvalid I 1
// core_mem_master_rid I 4 reg
// core_mem_master_rdata I 64 reg
// core_mem_master_rresp I 2 reg
// core_mem_master_rlast I 1 reg
// dma_server_awvalid I 1 unused
// dma_server_awid I 16 unused
// dma_server_awaddr I 64 unused
// dma_server_awlen I 8 unused
// dma_server_awsize I 3 unused
// dma_server_awburst I 2 unused
// dma_server_awlock I 1 unused
// dma_server_awcache I 4 unused
// dma_server_awprot I 3 unused
// dma_server_awqos I 4 unused
// dma_server_awregion I 4 unused
// dma_server_wvalid I 1 unused
// dma_server_wdata I 512 unused
// dma_server_wstrb I 64 unused
// dma_server_wlast I 1 unused
// dma_server_bready I 1 unused
// dma_server_arvalid I 1 unused
// dma_server_arid I 16 unused
// dma_server_araddr I 64 unused
// dma_server_arlen I 8 unused
// dma_server_arsize I 3 unused
// dma_server_arburst I 2 unused
// dma_server_arlock I 1 unused
// dma_server_arcache I 4 unused
// dma_server_arprot I 3 unused
// dma_server_arqos I 4 unused
// dma_server_arregion I 4 unused
// dma_server_rready I 1 unused
// core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1
// nmi_req_set_not_clear I 1
// set_verbosity_verbosity I 4 reg
// set_verbosity_logdelay I 64 reg
// set_watch_tohost_watch_tohost I 1 reg
// set_watch_tohost_tohost_addr I 64 reg
// EN_cpu_reset_server_request_put I 1
// EN_set_verbosity I 1
// EN_set_watch_tohost I 1
// EN_ma_ddr4_ready I 1
// EN_cpu_reset_server_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCore(RST_N_dm_power_on_reset,
CLK,
RST_N,
cpu_reset_server_request_put,
EN_cpu_reset_server_request_put,
RDY_cpu_reset_server_request_put,
EN_cpu_reset_server_response_get,
cpu_reset_server_response_get,
RDY_cpu_reset_server_response_get,
cpu_imem_master_awvalid,
cpu_imem_master_awid,
cpu_imem_master_awaddr,
cpu_imem_master_awlen,
cpu_imem_master_awsize,
cpu_imem_master_awburst,
cpu_imem_master_awlock,
cpu_imem_master_awcache,
cpu_imem_master_awprot,
cpu_imem_master_awqos,
cpu_imem_master_awregion,
cpu_imem_master_awready,
cpu_imem_master_wvalid,
cpu_imem_master_wdata,
cpu_imem_master_wstrb,
cpu_imem_master_wlast,
cpu_imem_master_wready,
cpu_imem_master_bvalid,
cpu_imem_master_bid,
cpu_imem_master_bresp,
cpu_imem_master_bready,
cpu_imem_master_arvalid,
cpu_imem_master_arid,
cpu_imem_master_araddr,
cpu_imem_master_arlen,
cpu_imem_master_arsize,
cpu_imem_master_arburst,
cpu_imem_master_arlock,
cpu_imem_master_arcache,
cpu_imem_master_arprot,
cpu_imem_master_arqos,
cpu_imem_master_arregion,
cpu_imem_master_arready,
cpu_imem_master_rvalid,
cpu_imem_master_rid,
cpu_imem_master_rdata,
cpu_imem_master_rresp,
cpu_imem_master_rlast,
cpu_imem_master_rready,
core_mem_master_awvalid,
core_mem_master_awid,
core_mem_master_awaddr,
core_mem_master_awlen,
core_mem_master_awsize,
core_mem_master_awburst,
core_mem_master_awlock,
core_mem_master_awcache,
core_mem_master_awprot,
core_mem_master_awqos,
core_mem_master_awregion,
core_mem_master_awready,
core_mem_master_wvalid,
core_mem_master_wdata,
core_mem_master_wstrb,
core_mem_master_wlast,
core_mem_master_wready,
core_mem_master_bvalid,
core_mem_master_bid,
core_mem_master_bresp,
core_mem_master_bready,
core_mem_master_arvalid,
core_mem_master_arid,
core_mem_master_araddr,
core_mem_master_arlen,
core_mem_master_arsize,
core_mem_master_arburst,
core_mem_master_arlock,
core_mem_master_arcache,
core_mem_master_arprot,
core_mem_master_arqos,
core_mem_master_arregion,
core_mem_master_arready,
core_mem_master_rvalid,
core_mem_master_rid,
core_mem_master_rdata,
core_mem_master_rresp,
core_mem_master_rlast,
core_mem_master_rready,
dma_server_awvalid,
dma_server_awid,
dma_server_awaddr,
dma_server_awlen,
dma_server_awsize,
dma_server_awburst,
dma_server_awlock,
dma_server_awcache,
dma_server_awprot,
dma_server_awqos,
dma_server_awregion,
dma_server_awready,
dma_server_wvalid,
dma_server_wdata,
dma_server_wstrb,
dma_server_wlast,
dma_server_wready,
dma_server_bvalid,
dma_server_bid,
dma_server_bresp,
dma_server_bready,
dma_server_arvalid,
dma_server_arid,
dma_server_araddr,
dma_server_arlen,
dma_server_arsize,
dma_server_arburst,
dma_server_arlock,
dma_server_arcache,
dma_server_arprot,
dma_server_arqos,
dma_server_arregion,
dma_server_arready,
dma_server_rvalid,
dma_server_rid,
dma_server_rdata,
dma_server_rresp,
dma_server_rlast,
dma_server_rready,
core_external_interrupt_sources_0_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_1_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_2_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_3_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_4_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_5_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_6_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_7_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_8_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_9_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_10_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_11_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_12_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_13_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_14_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_15_m_interrupt_req_set_not_clear,
nmi_req_set_not_clear,
set_verbosity_verbosity,
set_verbosity_logdelay,
EN_set_verbosity,
RDY_set_verbosity,
set_watch_tohost_watch_tohost,
set_watch_tohost_tohost_addr,
EN_set_watch_tohost,
RDY_set_watch_tohost,
mv_tohost_value,
RDY_mv_tohost_value,
EN_ma_ddr4_ready,
RDY_ma_ddr4_ready,
mv_status);
input RST_N_dm_power_on_reset;
input CLK;
input RST_N;
// action method cpu_reset_server_request_put
input cpu_reset_server_request_put;
input EN_cpu_reset_server_request_put;
output RDY_cpu_reset_server_request_put;
// actionvalue method cpu_reset_server_response_get
input EN_cpu_reset_server_response_get;
output cpu_reset_server_response_get;
output RDY_cpu_reset_server_response_get;
// value method cpu_imem_master_m_awvalid
output cpu_imem_master_awvalid;
// value method cpu_imem_master_m_awid
output [3 : 0] cpu_imem_master_awid;
// value method cpu_imem_master_m_awaddr
output [63 : 0] cpu_imem_master_awaddr;
// value method cpu_imem_master_m_awlen
output [7 : 0] cpu_imem_master_awlen;
// value method cpu_imem_master_m_awsize
output [2 : 0] cpu_imem_master_awsize;
// value method cpu_imem_master_m_awburst
output [1 : 0] cpu_imem_master_awburst;
// value method cpu_imem_master_m_awlock
output cpu_imem_master_awlock;
// value method cpu_imem_master_m_awcache
output [3 : 0] cpu_imem_master_awcache;
// value method cpu_imem_master_m_awprot
output [2 : 0] cpu_imem_master_awprot;
// value method cpu_imem_master_m_awqos
output [3 : 0] cpu_imem_master_awqos;
// value method cpu_imem_master_m_awregion
output [3 : 0] cpu_imem_master_awregion;
// value method cpu_imem_master_m_awuser
// action method cpu_imem_master_m_awready
input cpu_imem_master_awready;
// value method cpu_imem_master_m_wvalid
output cpu_imem_master_wvalid;
// value method cpu_imem_master_m_wdata
output [63 : 0] cpu_imem_master_wdata;
// value method cpu_imem_master_m_wstrb
output [7 : 0] cpu_imem_master_wstrb;
// value method cpu_imem_master_m_wlast
output cpu_imem_master_wlast;
// value method cpu_imem_master_m_wuser
// action method cpu_imem_master_m_wready
input cpu_imem_master_wready;
// action method cpu_imem_master_m_bvalid
input cpu_imem_master_bvalid;
input [3 : 0] cpu_imem_master_bid;
input [1 : 0] cpu_imem_master_bresp;
// value method cpu_imem_master_m_bready
output cpu_imem_master_bready;
// value method cpu_imem_master_m_arvalid
output cpu_imem_master_arvalid;
// value method cpu_imem_master_m_arid
output [3 : 0] cpu_imem_master_arid;
// value method cpu_imem_master_m_araddr
output [63 : 0] cpu_imem_master_araddr;
// value method cpu_imem_master_m_arlen
output [7 : 0] cpu_imem_master_arlen;
// value method cpu_imem_master_m_arsize
output [2 : 0] cpu_imem_master_arsize;
// value method cpu_imem_master_m_arburst
output [1 : 0] cpu_imem_master_arburst;
// value method cpu_imem_master_m_arlock
output cpu_imem_master_arlock;
// value method cpu_imem_master_m_arcache
output [3 : 0] cpu_imem_master_arcache;
// value method cpu_imem_master_m_arprot
output [2 : 0] cpu_imem_master_arprot;
// value method cpu_imem_master_m_arqos
output [3 : 0] cpu_imem_master_arqos;
// value method cpu_imem_master_m_arregion
output [3 : 0] cpu_imem_master_arregion;
// value method cpu_imem_master_m_aruser
// action method cpu_imem_master_m_arready
input cpu_imem_master_arready;
// action method cpu_imem_master_m_rvalid
input cpu_imem_master_rvalid;
input [3 : 0] cpu_imem_master_rid;
input [63 : 0] cpu_imem_master_rdata;
input [1 : 0] cpu_imem_master_rresp;
input cpu_imem_master_rlast;
// value method cpu_imem_master_m_rready
output cpu_imem_master_rready;
// value method core_mem_master_m_awvalid
output core_mem_master_awvalid;
// value method core_mem_master_m_awid
output [3 : 0] core_mem_master_awid;
// value method core_mem_master_m_awaddr
output [63 : 0] core_mem_master_awaddr;
// value method core_mem_master_m_awlen
output [7 : 0] core_mem_master_awlen;
// value method core_mem_master_m_awsize
output [2 : 0] core_mem_master_awsize;
// value method core_mem_master_m_awburst
output [1 : 0] core_mem_master_awburst;
// value method core_mem_master_m_awlock
output core_mem_master_awlock;
// value method core_mem_master_m_awcache
output [3 : 0] core_mem_master_awcache;
// value method core_mem_master_m_awprot
output [2 : 0] core_mem_master_awprot;
// value method core_mem_master_m_awqos
output [3 : 0] core_mem_master_awqos;
// value method core_mem_master_m_awregion
output [3 : 0] core_mem_master_awregion;
// value method core_mem_master_m_awuser
// action method core_mem_master_m_awready
input core_mem_master_awready;
// value method core_mem_master_m_wvalid
output core_mem_master_wvalid;
// value method core_mem_master_m_wdata
output [63 : 0] core_mem_master_wdata;
// value method core_mem_master_m_wstrb
output [7 : 0] core_mem_master_wstrb;
// value method core_mem_master_m_wlast
output core_mem_master_wlast;
// value method core_mem_master_m_wuser
// action method core_mem_master_m_wready
input core_mem_master_wready;
// action method core_mem_master_m_bvalid
input core_mem_master_bvalid;
input [3 : 0] core_mem_master_bid;
input [1 : 0] core_mem_master_bresp;
// value method core_mem_master_m_bready
output core_mem_master_bready;
// value method core_mem_master_m_arvalid
output core_mem_master_arvalid;
// value method core_mem_master_m_arid
output [3 : 0] core_mem_master_arid;
// value method core_mem_master_m_araddr
output [63 : 0] core_mem_master_araddr;
// value method core_mem_master_m_arlen
output [7 : 0] core_mem_master_arlen;
// value method core_mem_master_m_arsize
output [2 : 0] core_mem_master_arsize;
// value method core_mem_master_m_arburst
output [1 : 0] core_mem_master_arburst;
// value method core_mem_master_m_arlock
output core_mem_master_arlock;
// value method core_mem_master_m_arcache
output [3 : 0] core_mem_master_arcache;
// value method core_mem_master_m_arprot
output [2 : 0] core_mem_master_arprot;
// value method core_mem_master_m_arqos
output [3 : 0] core_mem_master_arqos;
// value method core_mem_master_m_arregion
output [3 : 0] core_mem_master_arregion;
// value method core_mem_master_m_aruser
// action method core_mem_master_m_arready
input core_mem_master_arready;
// action method core_mem_master_m_rvalid
input core_mem_master_rvalid;
input [3 : 0] core_mem_master_rid;
input [63 : 0] core_mem_master_rdata;
input [1 : 0] core_mem_master_rresp;
input core_mem_master_rlast;
// value method core_mem_master_m_rready
output core_mem_master_rready;
// action method dma_server_m_awvalid
input dma_server_awvalid;
input [15 : 0] dma_server_awid;
input [63 : 0] dma_server_awaddr;
input [7 : 0] dma_server_awlen;
input [2 : 0] dma_server_awsize;
input [1 : 0] dma_server_awburst;
input dma_server_awlock;
input [3 : 0] dma_server_awcache;
input [2 : 0] dma_server_awprot;
input [3 : 0] dma_server_awqos;
input [3 : 0] dma_server_awregion;
// value method dma_server_m_awready
output dma_server_awready;
// action method dma_server_m_wvalid
input dma_server_wvalid;
input [511 : 0] dma_server_wdata;
input [63 : 0] dma_server_wstrb;
input dma_server_wlast;
// value method dma_server_m_wready
output dma_server_wready;
// value method dma_server_m_bvalid
output dma_server_bvalid;
// value method dma_server_m_bid
output [15 : 0] dma_server_bid;
// value method dma_server_m_bresp
output [1 : 0] dma_server_bresp;
// value method dma_server_m_buser
// action method dma_server_m_bready
input dma_server_bready;
// action method dma_server_m_arvalid
input dma_server_arvalid;
input [15 : 0] dma_server_arid;
input [63 : 0] dma_server_araddr;
input [7 : 0] dma_server_arlen;
input [2 : 0] dma_server_arsize;
input [1 : 0] dma_server_arburst;
input dma_server_arlock;
input [3 : 0] dma_server_arcache;
input [2 : 0] dma_server_arprot;
input [3 : 0] dma_server_arqos;
input [3 : 0] dma_server_arregion;
// value method dma_server_m_arready
output dma_server_arready;
// value method dma_server_m_rvalid
output dma_server_rvalid;
// value method dma_server_m_rid
output [15 : 0] dma_server_rid;
// value method dma_server_m_rdata
output [511 : 0] dma_server_rdata;
// value method dma_server_m_rresp
output [1 : 0] dma_server_rresp;
// value method dma_server_m_rlast
output dma_server_rlast;
// value method dma_server_m_ruser
// action method dma_server_m_rready
input dma_server_rready;
// action method core_external_interrupt_sources_0_m_interrupt_req
input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_1_m_interrupt_req
input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_2_m_interrupt_req
input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_3_m_interrupt_req
input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_4_m_interrupt_req
input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_5_m_interrupt_req
input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_6_m_interrupt_req
input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_7_m_interrupt_req
input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_8_m_interrupt_req
input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_9_m_interrupt_req
input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_10_m_interrupt_req
input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_11_m_interrupt_req
input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_12_m_interrupt_req
input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_13_m_interrupt_req
input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_14_m_interrupt_req
input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_15_m_interrupt_req
input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear;
// action method nmi_req
input nmi_req_set_not_clear;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input [63 : 0] set_verbosity_logdelay;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method set_watch_tohost
input set_watch_tohost_watch_tohost;
input [63 : 0] set_watch_tohost_tohost_addr;
input EN_set_watch_tohost;
output RDY_set_watch_tohost;
// value method mv_tohost_value
output [63 : 0] mv_tohost_value;
output RDY_mv_tohost_value;
// action method ma_ddr4_ready
input EN_ma_ddr4_ready;
output RDY_ma_ddr4_ready;
// value method mv_status
output [7 : 0] mv_status;
// signals for module outputs
wire [511 : 0] dma_server_rdata;
wire [63 : 0] core_mem_master_araddr,
core_mem_master_awaddr,
core_mem_master_wdata,
cpu_imem_master_araddr,
cpu_imem_master_awaddr,
cpu_imem_master_wdata,
mv_tohost_value;
wire [15 : 0] dma_server_bid, dma_server_rid;
wire [7 : 0] core_mem_master_arlen,
core_mem_master_awlen,
core_mem_master_wstrb,
cpu_imem_master_arlen,
cpu_imem_master_awlen,
cpu_imem_master_wstrb,
mv_status;
wire [3 : 0] core_mem_master_arcache,
core_mem_master_arid,
core_mem_master_arqos,
core_mem_master_arregion,
core_mem_master_awcache,
core_mem_master_awid,
core_mem_master_awqos,
core_mem_master_awregion,
cpu_imem_master_arcache,
cpu_imem_master_arid,
cpu_imem_master_arqos,
cpu_imem_master_arregion,
cpu_imem_master_awcache,
cpu_imem_master_awid,
cpu_imem_master_awqos,
cpu_imem_master_awregion;
wire [2 : 0] core_mem_master_arprot,
core_mem_master_arsize,
core_mem_master_awprot,
core_mem_master_awsize,
cpu_imem_master_arprot,
cpu_imem_master_arsize,
cpu_imem_master_awprot,
cpu_imem_master_awsize;
wire [1 : 0] core_mem_master_arburst,
core_mem_master_awburst,
cpu_imem_master_arburst,
cpu_imem_master_awburst,
dma_server_bresp,
dma_server_rresp;
wire RDY_cpu_reset_server_request_put,
RDY_cpu_reset_server_response_get,
RDY_ma_ddr4_ready,
RDY_mv_tohost_value,
RDY_set_verbosity,
RDY_set_watch_tohost,
core_mem_master_arlock,
core_mem_master_arvalid,
core_mem_master_awlock,
core_mem_master_awvalid,
core_mem_master_bready,
core_mem_master_rready,
core_mem_master_wlast,
core_mem_master_wvalid,
cpu_imem_master_arlock,
cpu_imem_master_arvalid,
cpu_imem_master_awlock,
cpu_imem_master_awvalid,
cpu_imem_master_bready,
cpu_imem_master_rready,
cpu_imem_master_wlast,
cpu_imem_master_wvalid,
cpu_reset_server_response_get,
dma_server_arready,
dma_server_awready,
dma_server_bvalid,
dma_server_rlast,
dma_server_rvalid,
dma_server_wready;
// ports of submodule cpu
wire [511 : 0] cpu$dma_server_rdata, cpu$dma_server_wdata;
wire [63 : 0] cpu$dma_server_araddr,
cpu$dma_server_awaddr,
cpu$dma_server_wstrb,
cpu$imem_master_araddr,
cpu$imem_master_awaddr,
cpu$imem_master_rdata,
cpu$imem_master_wdata,
cpu$mem_master_araddr,
cpu$mem_master_awaddr,
cpu$mem_master_rdata,
cpu$mem_master_wdata,
cpu$mv_tohost_value,
cpu$set_verbosity_logdelay,
cpu$set_watch_tohost_tohost_addr;
wire [15 : 0] cpu$dma_server_arid,
cpu$dma_server_awid,
cpu$dma_server_bid,
cpu$dma_server_rid;
wire [7 : 0] cpu$dma_server_arlen,
cpu$dma_server_awlen,
cpu$imem_master_arlen,
cpu$imem_master_awlen,
cpu$imem_master_wstrb,
cpu$mem_master_arlen,
cpu$mem_master_awlen,
cpu$mem_master_wstrb,
cpu$mv_status;
wire [3 : 0] cpu$dma_server_arcache,
cpu$dma_server_arqos,
cpu$dma_server_arregion,
cpu$dma_server_awcache,
cpu$dma_server_awqos,
cpu$dma_server_awregion,
cpu$imem_master_arcache,
cpu$imem_master_arid,
cpu$imem_master_arqos,
cpu$imem_master_arregion,
cpu$imem_master_awcache,
cpu$imem_master_awid,
cpu$imem_master_awqos,
cpu$imem_master_awregion,
cpu$imem_master_bid,
cpu$imem_master_rid,
cpu$mem_master_arcache,
cpu$mem_master_arid,
cpu$mem_master_arqos,
cpu$mem_master_arregion,
cpu$mem_master_awcache,
cpu$mem_master_awid,
cpu$mem_master_awqos,
cpu$mem_master_awregion,
cpu$mem_master_bid,
cpu$mem_master_rid,
cpu$set_verbosity_verbosity;
wire [2 : 0] cpu$dma_server_arprot,
cpu$dma_server_arsize,
cpu$dma_server_awprot,
cpu$dma_server_awsize,
cpu$imem_master_arprot,
cpu$imem_master_arsize,
cpu$imem_master_awprot,
cpu$imem_master_awsize,
cpu$mem_master_arprot,
cpu$mem_master_arsize,
cpu$mem_master_awprot,
cpu$mem_master_awsize;
wire [1 : 0] cpu$dma_server_arburst,
cpu$dma_server_awburst,
cpu$dma_server_bresp,
cpu$dma_server_rresp,
cpu$imem_master_arburst,
cpu$imem_master_awburst,
cpu$imem_master_bresp,
cpu$imem_master_rresp,
cpu$mem_master_arburst,
cpu$mem_master_awburst,
cpu$mem_master_bresp,
cpu$mem_master_rresp;
wire cpu$EN_hart0_server_reset_request_put,
cpu$EN_hart0_server_reset_response_get,
cpu$EN_ma_ddr4_ready,
cpu$EN_set_verbosity,
cpu$EN_set_watch_tohost,
cpu$RDY_hart0_server_reset_request_put,
cpu$RDY_hart0_server_reset_response_get,
cpu$dma_server_arlock,
cpu$dma_server_arready,
cpu$dma_server_arvalid,
cpu$dma_server_awlock,
cpu$dma_server_awready,
cpu$dma_server_awvalid,
cpu$dma_server_bready,
cpu$dma_server_bvalid,
cpu$dma_server_rlast,
cpu$dma_server_rready,
cpu$dma_server_rvalid,
cpu$dma_server_wlast,
cpu$dma_server_wready,
cpu$dma_server_wvalid,
cpu$hart0_server_reset_request_put,
cpu$hart0_server_reset_response_get,
cpu$imem_master_arlock,
cpu$imem_master_arready,
cpu$imem_master_arvalid,
cpu$imem_master_awlock,
cpu$imem_master_awready,
cpu$imem_master_awvalid,
cpu$imem_master_bready,
cpu$imem_master_bvalid,
cpu$imem_master_rlast,
cpu$imem_master_rready,
cpu$imem_master_rvalid,
cpu$imem_master_wlast,
cpu$imem_master_wready,
cpu$imem_master_wvalid,
cpu$m_external_interrupt_req_set_not_clear,
cpu$mem_master_arlock,
cpu$mem_master_arready,
cpu$mem_master_arvalid,
cpu$mem_master_awlock,
cpu$mem_master_awready,
cpu$mem_master_awvalid,
cpu$mem_master_bready,
cpu$mem_master_bvalid,
cpu$mem_master_rlast,
cpu$mem_master_rready,
cpu$mem_master_rvalid,
cpu$mem_master_wlast,
cpu$mem_master_wready,
cpu$mem_master_wvalid,
cpu$nmi_req_set_not_clear,
cpu$s_external_interrupt_req_set_not_clear,
cpu$set_watch_tohost_watch_tohost,
cpu$software_interrupt_req_set_not_clear,
cpu$timer_interrupt_req_set_not_clear;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule fabric_2x3
wire [63 : 0] fabric_2x3$v_from_masters_0_araddr,
fabric_2x3$v_from_masters_0_awaddr,
fabric_2x3$v_from_masters_0_rdata,
fabric_2x3$v_from_masters_0_wdata,
fabric_2x3$v_from_masters_1_araddr,
fabric_2x3$v_from_masters_1_awaddr,
fabric_2x3$v_from_masters_1_wdata,
fabric_2x3$v_to_slaves_0_araddr,
fabric_2x3$v_to_slaves_0_awaddr,
fabric_2x3$v_to_slaves_0_rdata,
fabric_2x3$v_to_slaves_0_wdata,
fabric_2x3$v_to_slaves_1_araddr,
fabric_2x3$v_to_slaves_1_awaddr,
fabric_2x3$v_to_slaves_1_rdata,
fabric_2x3$v_to_slaves_1_wdata,
fabric_2x3$v_to_slaves_2_araddr,
fabric_2x3$v_to_slaves_2_awaddr,
fabric_2x3$v_to_slaves_2_rdata,
fabric_2x3$v_to_slaves_2_wdata;
wire [7 : 0] fabric_2x3$v_from_masters_0_arlen,
fabric_2x3$v_from_masters_0_awlen,
fabric_2x3$v_from_masters_0_wstrb,
fabric_2x3$v_from_masters_1_arlen,
fabric_2x3$v_from_masters_1_awlen,
fabric_2x3$v_from_masters_1_wstrb,
fabric_2x3$v_to_slaves_0_arlen,
fabric_2x3$v_to_slaves_0_awlen,
fabric_2x3$v_to_slaves_0_wstrb,
fabric_2x3$v_to_slaves_1_arlen,
fabric_2x3$v_to_slaves_1_awlen,
fabric_2x3$v_to_slaves_1_wstrb,
fabric_2x3$v_to_slaves_2_arlen,
fabric_2x3$v_to_slaves_2_awlen,
fabric_2x3$v_to_slaves_2_wstrb;
wire [3 : 0] fabric_2x3$set_verbosity_verbosity,
fabric_2x3$v_from_masters_0_arcache,
fabric_2x3$v_from_masters_0_arid,
fabric_2x3$v_from_masters_0_arqos,
fabric_2x3$v_from_masters_0_arregion,
fabric_2x3$v_from_masters_0_awcache,
fabric_2x3$v_from_masters_0_awid,
fabric_2x3$v_from_masters_0_awqos,
fabric_2x3$v_from_masters_0_awregion,
fabric_2x3$v_from_masters_0_bid,
fabric_2x3$v_from_masters_0_rid,
fabric_2x3$v_from_masters_1_arcache,
fabric_2x3$v_from_masters_1_arid,
fabric_2x3$v_from_masters_1_arqos,
fabric_2x3$v_from_masters_1_arregion,
fabric_2x3$v_from_masters_1_awcache,
fabric_2x3$v_from_masters_1_awid,
fabric_2x3$v_from_masters_1_awqos,
fabric_2x3$v_from_masters_1_awregion,
fabric_2x3$v_to_slaves_0_arcache,
fabric_2x3$v_to_slaves_0_arid,
fabric_2x3$v_to_slaves_0_arqos,
fabric_2x3$v_to_slaves_0_arregion,
fabric_2x3$v_to_slaves_0_awcache,
fabric_2x3$v_to_slaves_0_awid,
fabric_2x3$v_to_slaves_0_awqos,
fabric_2x3$v_to_slaves_0_awregion,
fabric_2x3$v_to_slaves_0_bid,
fabric_2x3$v_to_slaves_0_rid,
fabric_2x3$v_to_slaves_1_arcache,
fabric_2x3$v_to_slaves_1_arid,
fabric_2x3$v_to_slaves_1_arqos,
fabric_2x3$v_to_slaves_1_arregion,
fabric_2x3$v_to_slaves_1_awcache,
fabric_2x3$v_to_slaves_1_awid,
fabric_2x3$v_to_slaves_1_awqos,
fabric_2x3$v_to_slaves_1_awregion,
fabric_2x3$v_to_slaves_1_bid,
fabric_2x3$v_to_slaves_1_rid,
fabric_2x3$v_to_slaves_2_arcache,
fabric_2x3$v_to_slaves_2_arid,
fabric_2x3$v_to_slaves_2_arqos,
fabric_2x3$v_to_slaves_2_arregion,
fabric_2x3$v_to_slaves_2_awcache,
fabric_2x3$v_to_slaves_2_awid,
fabric_2x3$v_to_slaves_2_awqos,
fabric_2x3$v_to_slaves_2_awregion,
fabric_2x3$v_to_slaves_2_bid,
fabric_2x3$v_to_slaves_2_rid;
wire [2 : 0] fabric_2x3$v_from_masters_0_arprot,
fabric_2x3$v_from_masters_0_arsize,
fabric_2x3$v_from_masters_0_awprot,
fabric_2x3$v_from_masters_0_awsize,
fabric_2x3$v_from_masters_1_arprot,
fabric_2x3$v_from_masters_1_arsize,
fabric_2x3$v_from_masters_1_awprot,
fabric_2x3$v_from_masters_1_awsize,
fabric_2x3$v_to_slaves_0_arprot,
fabric_2x3$v_to_slaves_0_arsize,
fabric_2x3$v_to_slaves_0_awprot,
fabric_2x3$v_to_slaves_0_awsize,
fabric_2x3$v_to_slaves_1_arprot,
fabric_2x3$v_to_slaves_1_arsize,
fabric_2x3$v_to_slaves_1_awprot,
fabric_2x3$v_to_slaves_1_awsize,
fabric_2x3$v_to_slaves_2_arprot,
fabric_2x3$v_to_slaves_2_arsize,
fabric_2x3$v_to_slaves_2_awprot,
fabric_2x3$v_to_slaves_2_awsize;
wire [1 : 0] fabric_2x3$v_from_masters_0_arburst,
fabric_2x3$v_from_masters_0_awburst,
fabric_2x3$v_from_masters_0_bresp,
fabric_2x3$v_from_masters_0_rresp,
fabric_2x3$v_from_masters_1_arburst,
fabric_2x3$v_from_masters_1_awburst,
fabric_2x3$v_to_slaves_0_arburst,
fabric_2x3$v_to_slaves_0_awburst,
fabric_2x3$v_to_slaves_0_bresp,
fabric_2x3$v_to_slaves_0_rresp,
fabric_2x3$v_to_slaves_1_arburst,
fabric_2x3$v_to_slaves_1_awburst,
fabric_2x3$v_to_slaves_1_bresp,
fabric_2x3$v_to_slaves_1_rresp,
fabric_2x3$v_to_slaves_2_arburst,
fabric_2x3$v_to_slaves_2_awburst,
fabric_2x3$v_to_slaves_2_bresp,
fabric_2x3$v_to_slaves_2_rresp;
wire fabric_2x3$EN_reset,
fabric_2x3$EN_set_verbosity,
fabric_2x3$RDY_reset,
fabric_2x3$v_from_masters_0_arlock,
fabric_2x3$v_from_masters_0_arready,
fabric_2x3$v_from_masters_0_arvalid,
fabric_2x3$v_from_masters_0_awlock,
fabric_2x3$v_from_masters_0_awready,
fabric_2x3$v_from_masters_0_awvalid,
fabric_2x3$v_from_masters_0_bready,
fabric_2x3$v_from_masters_0_bvalid,
fabric_2x3$v_from_masters_0_rlast,
fabric_2x3$v_from_masters_0_rready,
fabric_2x3$v_from_masters_0_rvalid,
fabric_2x3$v_from_masters_0_wlast,
fabric_2x3$v_from_masters_0_wready,
fabric_2x3$v_from_masters_0_wvalid,
fabric_2x3$v_from_masters_1_arlock,
fabric_2x3$v_from_masters_1_arvalid,
fabric_2x3$v_from_masters_1_awlock,
fabric_2x3$v_from_masters_1_awvalid,
fabric_2x3$v_from_masters_1_bready,
fabric_2x3$v_from_masters_1_rready,
fabric_2x3$v_from_masters_1_wlast,
fabric_2x3$v_from_masters_1_wvalid,
fabric_2x3$v_to_slaves_0_arlock,
fabric_2x3$v_to_slaves_0_arready,
fabric_2x3$v_to_slaves_0_arvalid,
fabric_2x3$v_to_slaves_0_awlock,
fabric_2x3$v_to_slaves_0_awready,
fabric_2x3$v_to_slaves_0_awvalid,
fabric_2x3$v_to_slaves_0_bready,
fabric_2x3$v_to_slaves_0_bvalid,
fabric_2x3$v_to_slaves_0_rlast,
fabric_2x3$v_to_slaves_0_rready,
fabric_2x3$v_to_slaves_0_rvalid,
fabric_2x3$v_to_slaves_0_wlast,
fabric_2x3$v_to_slaves_0_wready,
fabric_2x3$v_to_slaves_0_wvalid,
fabric_2x3$v_to_slaves_1_arlock,
fabric_2x3$v_to_slaves_1_arready,
fabric_2x3$v_to_slaves_1_arvalid,
fabric_2x3$v_to_slaves_1_awlock,
fabric_2x3$v_to_slaves_1_awready,
fabric_2x3$v_to_slaves_1_awvalid,
fabric_2x3$v_to_slaves_1_bready,
fabric_2x3$v_to_slaves_1_bvalid,
fabric_2x3$v_to_slaves_1_rlast,
fabric_2x3$v_to_slaves_1_rready,
fabric_2x3$v_to_slaves_1_rvalid,
fabric_2x3$v_to_slaves_1_wlast,
fabric_2x3$v_to_slaves_1_wready,
fabric_2x3$v_to_slaves_1_wvalid,
fabric_2x3$v_to_slaves_2_arlock,
fabric_2x3$v_to_slaves_2_arready,
fabric_2x3$v_to_slaves_2_arvalid,
fabric_2x3$v_to_slaves_2_awlock,
fabric_2x3$v_to_slaves_2_awready,
fabric_2x3$v_to_slaves_2_awvalid,
fabric_2x3$v_to_slaves_2_bready,
fabric_2x3$v_to_slaves_2_bvalid,
fabric_2x3$v_to_slaves_2_rlast,
fabric_2x3$v_to_slaves_2_rready,
fabric_2x3$v_to_slaves_2_rvalid,
fabric_2x3$v_to_slaves_2_wlast,
fabric_2x3$v_to_slaves_2_wready,
fabric_2x3$v_to_slaves_2_wvalid;
// ports of submodule near_mem_io
wire [63 : 0] near_mem_io$axi4_slave_araddr,
near_mem_io$axi4_slave_awaddr,
near_mem_io$axi4_slave_rdata,
near_mem_io$axi4_slave_wdata,
near_mem_io$set_addr_map_addr_base,
near_mem_io$set_addr_map_addr_lim;
wire [7 : 0] near_mem_io$axi4_slave_arlen,
near_mem_io$axi4_slave_awlen,
near_mem_io$axi4_slave_wstrb;
wire [3 : 0] near_mem_io$axi4_slave_arcache,
near_mem_io$axi4_slave_arid,
near_mem_io$axi4_slave_arqos,
near_mem_io$axi4_slave_arregion,
near_mem_io$axi4_slave_awcache,
near_mem_io$axi4_slave_awid,
near_mem_io$axi4_slave_awqos,
near_mem_io$axi4_slave_awregion,
near_mem_io$axi4_slave_bid,
near_mem_io$axi4_slave_rid;
wire [2 : 0] near_mem_io$axi4_slave_arprot,
near_mem_io$axi4_slave_arsize,
near_mem_io$axi4_slave_awprot,
near_mem_io$axi4_slave_awsize;
wire [1 : 0] near_mem_io$axi4_slave_arburst,
near_mem_io$axi4_slave_awburst,
near_mem_io$axi4_slave_bresp,
near_mem_io$axi4_slave_rresp;
wire near_mem_io$EN_get_sw_interrupt_req_get,
near_mem_io$EN_get_timer_interrupt_req_get,
near_mem_io$EN_server_reset_request_put,
near_mem_io$EN_server_reset_response_get,
near_mem_io$EN_set_addr_map,
near_mem_io$RDY_get_sw_interrupt_req_get,
near_mem_io$RDY_get_timer_interrupt_req_get,
near_mem_io$RDY_server_reset_request_put,
near_mem_io$RDY_server_reset_response_get,
near_mem_io$axi4_slave_arlock,
near_mem_io$axi4_slave_arready,
near_mem_io$axi4_slave_arvalid,
near_mem_io$axi4_slave_awlock,
near_mem_io$axi4_slave_awready,
near_mem_io$axi4_slave_awvalid,
near_mem_io$axi4_slave_bready,
near_mem_io$axi4_slave_bvalid,
near_mem_io$axi4_slave_rlast,
near_mem_io$axi4_slave_rready,
near_mem_io$axi4_slave_rvalid,
near_mem_io$axi4_slave_wlast,
near_mem_io$axi4_slave_wready,
near_mem_io$axi4_slave_wvalid,
near_mem_io$get_sw_interrupt_req_get,
near_mem_io$get_timer_interrupt_req_get;
// ports of submodule plic
wire [63 : 0] plic$axi4_slave_araddr,
plic$axi4_slave_awaddr,
plic$axi4_slave_rdata,
plic$axi4_slave_wdata,
plic$set_addr_map_addr_base,
plic$set_addr_map_addr_lim;
wire [7 : 0] plic$axi4_slave_arlen,
plic$axi4_slave_awlen,
plic$axi4_slave_wstrb;
wire [3 : 0] plic$axi4_slave_arcache,
plic$axi4_slave_arid,
plic$axi4_slave_arqos,
plic$axi4_slave_arregion,
plic$axi4_slave_awcache,
plic$axi4_slave_awid,
plic$axi4_slave_awqos,
plic$axi4_slave_awregion,
plic$axi4_slave_bid,
plic$axi4_slave_rid,
plic$set_verbosity_verbosity;
wire [2 : 0] plic$axi4_slave_arprot,
plic$axi4_slave_arsize,
plic$axi4_slave_awprot,
plic$axi4_slave_awsize;
wire [1 : 0] plic$axi4_slave_arburst,
plic$axi4_slave_awburst,
plic$axi4_slave_bresp,
plic$axi4_slave_rresp;
wire plic$EN_server_reset_request_put,
plic$EN_server_reset_response_get,
plic$EN_set_addr_map,
plic$EN_set_verbosity,
plic$EN_show_PLIC_state,
plic$RDY_server_reset_request_put,
plic$RDY_server_reset_response_get,
plic$axi4_slave_arlock,
plic$axi4_slave_arready,
plic$axi4_slave_arvalid,
plic$axi4_slave_awlock,
plic$axi4_slave_awready,
plic$axi4_slave_awvalid,
plic$axi4_slave_bready,
plic$axi4_slave_bvalid,
plic$axi4_slave_rlast,
plic$axi4_slave_rready,
plic$axi4_slave_rvalid,
plic$axi4_slave_wlast,
plic$axi4_slave_wready,
plic$axi4_slave_wvalid,
plic$v_sources_0_m_interrupt_req_set_not_clear,
plic$v_sources_10_m_interrupt_req_set_not_clear,
plic$v_sources_11_m_interrupt_req_set_not_clear,
plic$v_sources_12_m_interrupt_req_set_not_clear,
plic$v_sources_13_m_interrupt_req_set_not_clear,
plic$v_sources_14_m_interrupt_req_set_not_clear,
plic$v_sources_15_m_interrupt_req_set_not_clear,
plic$v_sources_1_m_interrupt_req_set_not_clear,
plic$v_sources_2_m_interrupt_req_set_not_clear,
plic$v_sources_3_m_interrupt_req_set_not_clear,
plic$v_sources_4_m_interrupt_req_set_not_clear,
plic$v_sources_5_m_interrupt_req_set_not_clear,
plic$v_sources_6_m_interrupt_req_set_not_clear,
plic$v_sources_7_m_interrupt_req_set_not_clear,
plic$v_sources_8_m_interrupt_req_set_not_clear,
plic$v_sources_9_m_interrupt_req_set_not_clear,
plic$v_targets_0_m_eip,
plic$v_targets_1_m_eip;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_near_mem_io_addr_base,
soc_map$m_near_mem_io_addr_lim,
soc_map$m_plic_addr_base,
soc_map$m_plic_addr_lim;
// rule scheduling signals
wire CAN_FIRE_RL_rl_cpu_hart0_reset_complete,
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start,
CAN_FIRE_RL_rl_rd_addr_channel,
CAN_FIRE_RL_rl_rd_addr_channel_1,
CAN_FIRE_RL_rl_rd_addr_channel_2,
CAN_FIRE_RL_rl_rd_addr_channel_3,
CAN_FIRE_RL_rl_rd_data_channel,
CAN_FIRE_RL_rl_rd_data_channel_1,
CAN_FIRE_RL_rl_rd_data_channel_2,
CAN_FIRE_RL_rl_rd_data_channel_3,
CAN_FIRE_RL_rl_relay_external_interrupts,
CAN_FIRE_RL_rl_relay_sw_interrupts,
CAN_FIRE_RL_rl_relay_timer_interrupts,
CAN_FIRE_RL_rl_wr_addr_channel,
CAN_FIRE_RL_rl_wr_addr_channel_1,
CAN_FIRE_RL_rl_wr_addr_channel_2,
CAN_FIRE_RL_rl_wr_addr_channel_3,
CAN_FIRE_RL_rl_wr_data_channel,
CAN_FIRE_RL_rl_wr_data_channel_1,
CAN_FIRE_RL_rl_wr_data_channel_2,
CAN_FIRE_RL_rl_wr_data_channel_3,
CAN_FIRE_RL_rl_wr_response_channel,
CAN_FIRE_RL_rl_wr_response_channel_1,
CAN_FIRE_RL_rl_wr_response_channel_2,
CAN_FIRE_RL_rl_wr_response_channel_3,
CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req,
CAN_FIRE_core_mem_master_m_arready,
CAN_FIRE_core_mem_master_m_awready,
CAN_FIRE_core_mem_master_m_bvalid,
CAN_FIRE_core_mem_master_m_rvalid,
CAN_FIRE_core_mem_master_m_wready,
CAN_FIRE_cpu_imem_master_m_arready,
CAN_FIRE_cpu_imem_master_m_awready,
CAN_FIRE_cpu_imem_master_m_bvalid,
CAN_FIRE_cpu_imem_master_m_rvalid,
CAN_FIRE_cpu_imem_master_m_wready,
CAN_FIRE_cpu_reset_server_request_put,
CAN_FIRE_cpu_reset_server_response_get,
CAN_FIRE_dma_server_m_arvalid,
CAN_FIRE_dma_server_m_awvalid,
CAN_FIRE_dma_server_m_bready,
CAN_FIRE_dma_server_m_rready,
CAN_FIRE_dma_server_m_wvalid,
CAN_FIRE_ma_ddr4_ready,
CAN_FIRE_nmi_req,
CAN_FIRE_set_verbosity,
CAN_FIRE_set_watch_tohost,
WILL_FIRE_RL_rl_cpu_hart0_reset_complete,
WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start,
WILL_FIRE_RL_rl_rd_addr_channel,
WILL_FIRE_RL_rl_rd_addr_channel_1,
WILL_FIRE_RL_rl_rd_addr_channel_2,
WILL_FIRE_RL_rl_rd_addr_channel_3,
WILL_FIRE_RL_rl_rd_data_channel,
WILL_FIRE_RL_rl_rd_data_channel_1,
WILL_FIRE_RL_rl_rd_data_channel_2,
WILL_FIRE_RL_rl_rd_data_channel_3,
WILL_FIRE_RL_rl_relay_external_interrupts,
WILL_FIRE_RL_rl_relay_sw_interrupts,
WILL_FIRE_RL_rl_relay_timer_interrupts,
WILL_FIRE_RL_rl_wr_addr_channel,
WILL_FIRE_RL_rl_wr_addr_channel_1,
WILL_FIRE_RL_rl_wr_addr_channel_2,
WILL_FIRE_RL_rl_wr_addr_channel_3,
WILL_FIRE_RL_rl_wr_data_channel,
WILL_FIRE_RL_rl_wr_data_channel_1,
WILL_FIRE_RL_rl_wr_data_channel_2,
WILL_FIRE_RL_rl_wr_data_channel_3,
WILL_FIRE_RL_rl_wr_response_channel,
WILL_FIRE_RL_rl_wr_response_channel_1,
WILL_FIRE_RL_rl_wr_response_channel_2,
WILL_FIRE_RL_rl_wr_response_channel_3,
WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req,
WILL_FIRE_core_mem_master_m_arready,
WILL_FIRE_core_mem_master_m_awready,
WILL_FIRE_core_mem_master_m_bvalid,
WILL_FIRE_core_mem_master_m_rvalid,
WILL_FIRE_core_mem_master_m_wready,
WILL_FIRE_cpu_imem_master_m_arready,
WILL_FIRE_cpu_imem_master_m_awready,
WILL_FIRE_cpu_imem_master_m_bvalid,
WILL_FIRE_cpu_imem_master_m_rvalid,
WILL_FIRE_cpu_imem_master_m_wready,
WILL_FIRE_cpu_reset_server_request_put,
WILL_FIRE_cpu_reset_server_response_get,
WILL_FIRE_dma_server_m_arvalid,
WILL_FIRE_dma_server_m_awvalid,
WILL_FIRE_dma_server_m_bready,
WILL_FIRE_dma_server_m_rready,
WILL_FIRE_dma_server_m_wvalid,
WILL_FIRE_ma_ddr4_ready,
WILL_FIRE_nmi_req,
WILL_FIRE_set_verbosity,
WILL_FIRE_set_watch_tohost;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h4601;
reg [31 : 0] v__h4817;
reg [31 : 0] v__h4595;
reg [31 : 0] v__h4811;
// synopsys translate_on
// remaining internal signals
wire plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8;
// action method cpu_reset_server_request_put
assign RDY_cpu_reset_server_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_cpu_reset_server_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_cpu_reset_server_request_put =
EN_cpu_reset_server_request_put ;
// actionvalue method cpu_reset_server_response_get
assign cpu_reset_server_response_get = f_reset_rsps$D_OUT ;
assign RDY_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_cpu_reset_server_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_cpu_reset_server_response_get =
EN_cpu_reset_server_response_get ;
// value method cpu_imem_master_m_awvalid
assign cpu_imem_master_awvalid = cpu$imem_master_awvalid ;
// value method cpu_imem_master_m_awid
assign cpu_imem_master_awid = cpu$imem_master_awid ;
// value method cpu_imem_master_m_awaddr
assign cpu_imem_master_awaddr = cpu$imem_master_awaddr ;
// value method cpu_imem_master_m_awlen
assign cpu_imem_master_awlen = cpu$imem_master_awlen ;
// value method cpu_imem_master_m_awsize
assign cpu_imem_master_awsize = cpu$imem_master_awsize ;
// value method cpu_imem_master_m_awburst
assign cpu_imem_master_awburst = cpu$imem_master_awburst ;
// value method cpu_imem_master_m_awlock
assign cpu_imem_master_awlock = cpu$imem_master_awlock ;
// value method cpu_imem_master_m_awcache
assign cpu_imem_master_awcache = cpu$imem_master_awcache ;
// value method cpu_imem_master_m_awprot
assign cpu_imem_master_awprot = cpu$imem_master_awprot ;
// value method cpu_imem_master_m_awqos
assign cpu_imem_master_awqos = cpu$imem_master_awqos ;
// value method cpu_imem_master_m_awregion
assign cpu_imem_master_awregion = cpu$imem_master_awregion ;
// action method cpu_imem_master_m_awready
assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ;
// value method cpu_imem_master_m_wvalid
assign cpu_imem_master_wvalid = cpu$imem_master_wvalid ;
// value method cpu_imem_master_m_wdata
assign cpu_imem_master_wdata = cpu$imem_master_wdata ;
// value method cpu_imem_master_m_wstrb
assign cpu_imem_master_wstrb = cpu$imem_master_wstrb ;
// value method cpu_imem_master_m_wlast
assign cpu_imem_master_wlast = cpu$imem_master_wlast ;
// action method cpu_imem_master_m_wready
assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ;
// action method cpu_imem_master_m_bvalid
assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ;
// value method cpu_imem_master_m_bready
assign cpu_imem_master_bready = cpu$imem_master_bready ;
// value method cpu_imem_master_m_arvalid
assign cpu_imem_master_arvalid = cpu$imem_master_arvalid ;
// value method cpu_imem_master_m_arid
assign cpu_imem_master_arid = cpu$imem_master_arid ;
// value method cpu_imem_master_m_araddr
assign cpu_imem_master_araddr = cpu$imem_master_araddr ;
// value method cpu_imem_master_m_arlen
assign cpu_imem_master_arlen = cpu$imem_master_arlen ;
// value method cpu_imem_master_m_arsize
assign cpu_imem_master_arsize = cpu$imem_master_arsize ;
// value method cpu_imem_master_m_arburst
assign cpu_imem_master_arburst = cpu$imem_master_arburst ;
// value method cpu_imem_master_m_arlock
assign cpu_imem_master_arlock = cpu$imem_master_arlock ;
// value method cpu_imem_master_m_arcache
assign cpu_imem_master_arcache = cpu$imem_master_arcache ;
// value method cpu_imem_master_m_arprot
assign cpu_imem_master_arprot = cpu$imem_master_arprot ;
// value method cpu_imem_master_m_arqos
assign cpu_imem_master_arqos = cpu$imem_master_arqos ;
// value method cpu_imem_master_m_arregion
assign cpu_imem_master_arregion = cpu$imem_master_arregion ;
// action method cpu_imem_master_m_arready
assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ;
// action method cpu_imem_master_m_rvalid
assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ;
// value method cpu_imem_master_m_rready
assign cpu_imem_master_rready = cpu$imem_master_rready ;
// value method core_mem_master_m_awvalid
assign core_mem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ;
// value method core_mem_master_m_awid
assign core_mem_master_awid = fabric_2x3$v_to_slaves_0_awid ;
// value method core_mem_master_m_awaddr
assign core_mem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ;
// value method core_mem_master_m_awlen
assign core_mem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ;
// value method core_mem_master_m_awsize
assign core_mem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ;
// value method core_mem_master_m_awburst
assign core_mem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ;
// value method core_mem_master_m_awlock
assign core_mem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ;
// value method core_mem_master_m_awcache
assign core_mem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ;
// value method core_mem_master_m_awprot
assign core_mem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ;
// value method core_mem_master_m_awqos
assign core_mem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ;
// value method core_mem_master_m_awregion
assign core_mem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ;
// action method core_mem_master_m_awready
assign CAN_FIRE_core_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_core_mem_master_m_awready = 1'd1 ;
// value method core_mem_master_m_wvalid
assign core_mem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ;
// value method core_mem_master_m_wdata
assign core_mem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ;
// value method core_mem_master_m_wstrb
assign core_mem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ;
// value method core_mem_master_m_wlast
assign core_mem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ;
// action method core_mem_master_m_wready
assign CAN_FIRE_core_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_core_mem_master_m_wready = 1'd1 ;
// action method core_mem_master_m_bvalid
assign CAN_FIRE_core_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_core_mem_master_m_bvalid = 1'd1 ;
// value method core_mem_master_m_bready
assign core_mem_master_bready = fabric_2x3$v_to_slaves_0_bready ;
// value method core_mem_master_m_arvalid
assign core_mem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ;
// value method core_mem_master_m_arid
assign core_mem_master_arid = fabric_2x3$v_to_slaves_0_arid ;
// value method core_mem_master_m_araddr
assign core_mem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ;
// value method core_mem_master_m_arlen
assign core_mem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ;
// value method core_mem_master_m_arsize
assign core_mem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ;
// value method core_mem_master_m_arburst
assign core_mem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ;
// value method core_mem_master_m_arlock
assign core_mem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ;
// value method core_mem_master_m_arcache
assign core_mem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ;
// value method core_mem_master_m_arprot
assign core_mem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ;
// value method core_mem_master_m_arqos
assign core_mem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ;
// value method core_mem_master_m_arregion
assign core_mem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ;
// action method core_mem_master_m_arready
assign CAN_FIRE_core_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_core_mem_master_m_arready = 1'd1 ;
// action method core_mem_master_m_rvalid
assign CAN_FIRE_core_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_core_mem_master_m_rvalid = 1'd1 ;
// value method core_mem_master_m_rready
assign core_mem_master_rready = fabric_2x3$v_to_slaves_0_rready ;
// action method dma_server_m_awvalid
assign CAN_FIRE_dma_server_m_awvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_awvalid = 1'd1 ;
// value method dma_server_m_awready
assign dma_server_awready = cpu$dma_server_awready ;
// action method dma_server_m_wvalid
assign CAN_FIRE_dma_server_m_wvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_wvalid = 1'd1 ;
// value method dma_server_m_wready
assign dma_server_wready = cpu$dma_server_wready ;
// value method dma_server_m_bvalid
assign dma_server_bvalid = cpu$dma_server_bvalid ;
// value method dma_server_m_bid
assign dma_server_bid = cpu$dma_server_bid ;
// value method dma_server_m_bresp
assign dma_server_bresp = cpu$dma_server_bresp ;
// action method dma_server_m_bready
assign CAN_FIRE_dma_server_m_bready = 1'd1 ;
assign WILL_FIRE_dma_server_m_bready = 1'd1 ;
// action method dma_server_m_arvalid
assign CAN_FIRE_dma_server_m_arvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_arvalid = 1'd1 ;
// value method dma_server_m_arready
assign dma_server_arready = cpu$dma_server_arready ;
// value method dma_server_m_rvalid
assign dma_server_rvalid = cpu$dma_server_rvalid ;
// value method dma_server_m_rid
assign dma_server_rid = cpu$dma_server_rid ;
// value method dma_server_m_rdata
assign dma_server_rdata = cpu$dma_server_rdata ;
// value method dma_server_m_rresp
assign dma_server_rresp = cpu$dma_server_rresp ;
// value method dma_server_m_rlast
assign dma_server_rlast = cpu$dma_server_rlast ;
// action method dma_server_m_rready
assign CAN_FIRE_dma_server_m_rready = 1'd1 ;
assign WILL_FIRE_dma_server_m_rready = 1'd1 ;
// action method core_external_interrupt_sources_0_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_1_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_2_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_3_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_4_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_5_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_6_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_7_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_8_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_9_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_10_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_11_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_12_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_13_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_14_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_15_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ;
// action method nmi_req
assign CAN_FIRE_nmi_req = 1'd1 ;
assign WILL_FIRE_nmi_req = 1'd1 ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// value method mv_tohost_value
assign mv_tohost_value = cpu$mv_tohost_value ;
assign RDY_mv_tohost_value = 1'd1 ;
// action method ma_ddr4_ready
assign RDY_ma_ddr4_ready = 1'd1 ;
assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;
// value method mv_status
assign mv_status = cpu$mv_status ;
// submodule cpu
mkCPU cpu(.CLK(CLK),
.RST_N(RST_N),
.dma_server_araddr(cpu$dma_server_araddr),
.dma_server_arburst(cpu$dma_server_arburst),
.dma_server_arcache(cpu$dma_server_arcache),
.dma_server_arid(cpu$dma_server_arid),
.dma_server_arlen(cpu$dma_server_arlen),
.dma_server_arlock(cpu$dma_server_arlock),
.dma_server_arprot(cpu$dma_server_arprot),
.dma_server_arqos(cpu$dma_server_arqos),
.dma_server_arregion(cpu$dma_server_arregion),
.dma_server_arsize(cpu$dma_server_arsize),
.dma_server_arvalid(cpu$dma_server_arvalid),
.dma_server_awaddr(cpu$dma_server_awaddr),
.dma_server_awburst(cpu$dma_server_awburst),
.dma_server_awcache(cpu$dma_server_awcache),
.dma_server_awid(cpu$dma_server_awid),
.dma_server_awlen(cpu$dma_server_awlen),
.dma_server_awlock(cpu$dma_server_awlock),
.dma_server_awprot(cpu$dma_server_awprot),
.dma_server_awqos(cpu$dma_server_awqos),
.dma_server_awregion(cpu$dma_server_awregion),
.dma_server_awsize(cpu$dma_server_awsize),
.dma_server_awvalid(cpu$dma_server_awvalid),
.dma_server_bready(cpu$dma_server_bready),
.dma_server_rready(cpu$dma_server_rready),
.dma_server_wdata(cpu$dma_server_wdata),
.dma_server_wlast(cpu$dma_server_wlast),
.dma_server_wstrb(cpu$dma_server_wstrb),
.dma_server_wvalid(cpu$dma_server_wvalid),
.hart0_server_reset_request_put(cpu$hart0_server_reset_request_put),
.imem_master_arready(cpu$imem_master_arready),
.imem_master_awready(cpu$imem_master_awready),
.imem_master_bid(cpu$imem_master_bid),
.imem_master_bresp(cpu$imem_master_bresp),
.imem_master_bvalid(cpu$imem_master_bvalid),
.imem_master_rdata(cpu$imem_master_rdata),
.imem_master_rid(cpu$imem_master_rid),
.imem_master_rlast(cpu$imem_master_rlast),
.imem_master_rresp(cpu$imem_master_rresp),
.imem_master_rvalid(cpu$imem_master_rvalid),
.imem_master_wready(cpu$imem_master_wready),
.m_external_interrupt_req_set_not_clear(cpu$m_external_interrupt_req_set_not_clear),
.mem_master_arready(cpu$mem_master_arready),
.mem_master_awready(cpu$mem_master_awready),
.mem_master_bid(cpu$mem_master_bid),
.mem_master_bresp(cpu$mem_master_bresp),
.mem_master_bvalid(cpu$mem_master_bvalid),
.mem_master_rdata(cpu$mem_master_rdata),
.mem_master_rid(cpu$mem_master_rid),
.mem_master_rlast(cpu$mem_master_rlast),
.mem_master_rresp(cpu$mem_master_rresp),
.mem_master_rvalid(cpu$mem_master_rvalid),
.mem_master_wready(cpu$mem_master_wready),
.nmi_req_set_not_clear(cpu$nmi_req_set_not_clear),
.s_external_interrupt_req_set_not_clear(cpu$s_external_interrupt_req_set_not_clear),
.set_verbosity_logdelay(cpu$set_verbosity_logdelay),
.set_verbosity_verbosity(cpu$set_verbosity_verbosity),
.set_watch_tohost_tohost_addr(cpu$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(cpu$set_watch_tohost_watch_tohost),
.software_interrupt_req_set_not_clear(cpu$software_interrupt_req_set_not_clear),
.timer_interrupt_req_set_not_clear(cpu$timer_interrupt_req_set_not_clear),
.EN_hart0_server_reset_request_put(cpu$EN_hart0_server_reset_request_put),
.EN_hart0_server_reset_response_get(cpu$EN_hart0_server_reset_response_get),
.EN_set_verbosity(cpu$EN_set_verbosity),
.EN_set_watch_tohost(cpu$EN_set_watch_tohost),
.EN_ma_ddr4_ready(cpu$EN_ma_ddr4_ready),
.RDY_hart0_server_reset_request_put(cpu$RDY_hart0_server_reset_request_put),
.hart0_server_reset_response_get(cpu$hart0_server_reset_response_get),
.RDY_hart0_server_reset_response_get(cpu$RDY_hart0_server_reset_response_get),
.imem_master_awvalid(cpu$imem_master_awvalid),
.imem_master_awid(cpu$imem_master_awid),
.imem_master_awaddr(cpu$imem_master_awaddr),
.imem_master_awlen(cpu$imem_master_awlen),
.imem_master_awsize(cpu$imem_master_awsize),
.imem_master_awburst(cpu$imem_master_awburst),
.imem_master_awlock(cpu$imem_master_awlock),
.imem_master_awcache(cpu$imem_master_awcache),
.imem_master_awprot(cpu$imem_master_awprot),
.imem_master_awqos(cpu$imem_master_awqos),
.imem_master_awregion(cpu$imem_master_awregion),
.imem_master_wvalid(cpu$imem_master_wvalid),
.imem_master_wdata(cpu$imem_master_wdata),
.imem_master_wstrb(cpu$imem_master_wstrb),
.imem_master_wlast(cpu$imem_master_wlast),
.imem_master_bready(cpu$imem_master_bready),
.imem_master_arvalid(cpu$imem_master_arvalid),
.imem_master_arid(cpu$imem_master_arid),
.imem_master_araddr(cpu$imem_master_araddr),
.imem_master_arlen(cpu$imem_master_arlen),
.imem_master_arsize(cpu$imem_master_arsize),
.imem_master_arburst(cpu$imem_master_arburst),
.imem_master_arlock(cpu$imem_master_arlock),
.imem_master_arcache(cpu$imem_master_arcache),
.imem_master_arprot(cpu$imem_master_arprot),
.imem_master_arqos(cpu$imem_master_arqos),
.imem_master_arregion(cpu$imem_master_arregion),
.imem_master_rready(cpu$imem_master_rready),
.mem_master_awvalid(cpu$mem_master_awvalid),
.mem_master_awid(cpu$mem_master_awid),
.mem_master_awaddr(cpu$mem_master_awaddr),
.mem_master_awlen(cpu$mem_master_awlen),
.mem_master_awsize(cpu$mem_master_awsize),
.mem_master_awburst(cpu$mem_master_awburst),
.mem_master_awlock(cpu$mem_master_awlock),
.mem_master_awcache(cpu$mem_master_awcache),
.mem_master_awprot(cpu$mem_master_awprot),
.mem_master_awqos(cpu$mem_master_awqos),
.mem_master_awregion(cpu$mem_master_awregion),
.mem_master_wvalid(cpu$mem_master_wvalid),
.mem_master_wdata(cpu$mem_master_wdata),
.mem_master_wstrb(cpu$mem_master_wstrb),
.mem_master_wlast(cpu$mem_master_wlast),
.mem_master_bready(cpu$mem_master_bready),
.mem_master_arvalid(cpu$mem_master_arvalid),
.mem_master_arid(cpu$mem_master_arid),
.mem_master_araddr(cpu$mem_master_araddr),
.mem_master_arlen(cpu$mem_master_arlen),
.mem_master_arsize(cpu$mem_master_arsize),
.mem_master_arburst(cpu$mem_master_arburst),
.mem_master_arlock(cpu$mem_master_arlock),
.mem_master_arcache(cpu$mem_master_arcache),
.mem_master_arprot(cpu$mem_master_arprot),
.mem_master_arqos(cpu$mem_master_arqos),
.mem_master_arregion(cpu$mem_master_arregion),
.mem_master_rready(cpu$mem_master_rready),
.dma_server_awready(cpu$dma_server_awready),
.dma_server_wready(cpu$dma_server_wready),
.dma_server_bvalid(cpu$dma_server_bvalid),
.dma_server_bid(cpu$dma_server_bid),
.dma_server_bresp(cpu$dma_server_bresp),
.dma_server_arready(cpu$dma_server_arready),
.dma_server_rvalid(cpu$dma_server_rvalid),
.dma_server_rid(cpu$dma_server_rid),
.dma_server_rdata(cpu$dma_server_rdata),
.dma_server_rresp(cpu$dma_server_rresp),
.dma_server_rlast(cpu$dma_server_rlast),
.RDY_set_verbosity(),
.RDY_set_watch_tohost(),
.mv_tohost_value(cpu$mv_tohost_value),
.RDY_mv_tohost_value(),
.RDY_ma_ddr4_ready(),
.mv_status(cpu$mv_status));
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule fabric_2x3
mkFabric_2x3 fabric_2x3(.CLK(CLK),
.RST_N(RST_N),
.set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity),
.v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr),
.v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst),
.v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache),
.v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid),
.v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen),
.v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock),
.v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot),
.v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos),
.v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion),
.v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize),
.v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid),
.v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr),
.v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst),
.v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache),
.v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid),
.v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen),
.v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock),
.v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot),
.v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos),
.v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion),
.v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize),
.v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid),
.v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready),
.v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready),
.v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata),
.v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast),
.v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb),
.v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid),
.v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr),
.v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst),
.v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache),
.v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid),
.v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen),
.v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock),
.v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot),
.v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos),
.v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion),
.v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize),
.v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid),
.v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr),
.v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst),
.v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache),
.v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid),
.v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen),
.v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock),
.v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot),
.v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos),
.v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion),
.v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize),
.v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid),
.v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready),
.v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready),
.v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata),
.v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast),
.v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb),
.v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid),
.v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready),
.v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready),
.v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid),
.v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp),
.v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid),
.v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata),
.v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid),
.v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast),
.v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp),
.v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid),
.v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready),
.v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready),
.v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready),
.v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid),
.v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp),
.v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid),
.v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata),
.v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid),
.v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast),
.v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp),
.v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid),
.v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready),
.v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready),
.v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready),
.v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid),
.v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp),
.v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid),
.v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata),
.v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid),
.v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast),
.v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp),
.v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid),
.v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready),
.EN_reset(fabric_2x3$EN_reset),
.EN_set_verbosity(fabric_2x3$EN_set_verbosity),
.RDY_reset(fabric_2x3$RDY_reset),
.RDY_set_verbosity(),
.v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready),
.v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready),
.v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid),
.v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid),
.v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp),
.v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready),
.v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid),
.v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid),
.v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata),
.v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp),
.v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast),
.v_from_masters_1_awready(),
.v_from_masters_1_wready(),
.v_from_masters_1_bvalid(),
.v_from_masters_1_bid(),
.v_from_masters_1_bresp(),
.v_from_masters_1_arready(),
.v_from_masters_1_rvalid(),
.v_from_masters_1_rid(),
.v_from_masters_1_rdata(),
.v_from_masters_1_rresp(),
.v_from_masters_1_rlast(),
.v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid),
.v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid),
.v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr),
.v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen),
.v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize),
.v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst),
.v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock),
.v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache),
.v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot),
.v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos),
.v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion),
.v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid),
.v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata),
.v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb),
.v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast),
.v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready),
.v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid),
.v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid),
.v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr),
.v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen),
.v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize),
.v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst),
.v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock),
.v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache),
.v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot),
.v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos),
.v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion),
.v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready),
.v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid),
.v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid),
.v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr),
.v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen),
.v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize),
.v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst),
.v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock),
.v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache),
.v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot),
.v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos),
.v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion),
.v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid),
.v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata),
.v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb),
.v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast),
.v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready),
.v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid),
.v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid),
.v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr),
.v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen),
.v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize),
.v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst),
.v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock),
.v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache),
.v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot),
.v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos),
.v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion),
.v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready),
.v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid),
.v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid),
.v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr),
.v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen),
.v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize),
.v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst),
.v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock),
.v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache),
.v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot),
.v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos),
.v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion),
.v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid),
.v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata),
.v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb),
.v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast),
.v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready),
.v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid),
.v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid),
.v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr),
.v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen),
.v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize),
.v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst),
.v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock),
.v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache),
.v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot),
.v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos),
.v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion),
.v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready));
// submodule near_mem_io
mkNear_Mem_IO_AXI4 near_mem_io(.CLK(CLK),
.RST_N(RST_N),
.axi4_slave_araddr(near_mem_io$axi4_slave_araddr),
.axi4_slave_arburst(near_mem_io$axi4_slave_arburst),
.axi4_slave_arcache(near_mem_io$axi4_slave_arcache),
.axi4_slave_arid(near_mem_io$axi4_slave_arid),
.axi4_slave_arlen(near_mem_io$axi4_slave_arlen),
.axi4_slave_arlock(near_mem_io$axi4_slave_arlock),
.axi4_slave_arprot(near_mem_io$axi4_slave_arprot),
.axi4_slave_arqos(near_mem_io$axi4_slave_arqos),
.axi4_slave_arregion(near_mem_io$axi4_slave_arregion),
.axi4_slave_arsize(near_mem_io$axi4_slave_arsize),
.axi4_slave_arvalid(near_mem_io$axi4_slave_arvalid),
.axi4_slave_awaddr(near_mem_io$axi4_slave_awaddr),
.axi4_slave_awburst(near_mem_io$axi4_slave_awburst),
.axi4_slave_awcache(near_mem_io$axi4_slave_awcache),
.axi4_slave_awid(near_mem_io$axi4_slave_awid),
.axi4_slave_awlen(near_mem_io$axi4_slave_awlen),
.axi4_slave_awlock(near_mem_io$axi4_slave_awlock),
.axi4_slave_awprot(near_mem_io$axi4_slave_awprot),
.axi4_slave_awqos(near_mem_io$axi4_slave_awqos),
.axi4_slave_awregion(near_mem_io$axi4_slave_awregion),
.axi4_slave_awsize(near_mem_io$axi4_slave_awsize),
.axi4_slave_awvalid(near_mem_io$axi4_slave_awvalid),
.axi4_slave_bready(near_mem_io$axi4_slave_bready),
.axi4_slave_rready(near_mem_io$axi4_slave_rready),
.axi4_slave_wdata(near_mem_io$axi4_slave_wdata),
.axi4_slave_wlast(near_mem_io$axi4_slave_wlast),
.axi4_slave_wstrb(near_mem_io$axi4_slave_wstrb),
.axi4_slave_wvalid(near_mem_io$axi4_slave_wvalid),
.set_addr_map_addr_base(near_mem_io$set_addr_map_addr_base),
.set_addr_map_addr_lim(near_mem_io$set_addr_map_addr_lim),
.EN_server_reset_request_put(near_mem_io$EN_server_reset_request_put),
.EN_server_reset_response_get(near_mem_io$EN_server_reset_response_get),
.EN_set_addr_map(near_mem_io$EN_set_addr_map),
.EN_get_timer_interrupt_req_get(near_mem_io$EN_get_timer_interrupt_req_get),
.EN_get_sw_interrupt_req_get(near_mem_io$EN_get_sw_interrupt_req_get),
.RDY_server_reset_request_put(near_mem_io$RDY_server_reset_request_put),
.RDY_server_reset_response_get(near_mem_io$RDY_server_reset_response_get),
.RDY_set_addr_map(),
.axi4_slave_awready(near_mem_io$axi4_slave_awready),
.axi4_slave_wready(near_mem_io$axi4_slave_wready),
.axi4_slave_bvalid(near_mem_io$axi4_slave_bvalid),
.axi4_slave_bid(near_mem_io$axi4_slave_bid),
.axi4_slave_bresp(near_mem_io$axi4_slave_bresp),
.axi4_slave_arready(near_mem_io$axi4_slave_arready),
.axi4_slave_rvalid(near_mem_io$axi4_slave_rvalid),
.axi4_slave_rid(near_mem_io$axi4_slave_rid),
.axi4_slave_rdata(near_mem_io$axi4_slave_rdata),
.axi4_slave_rresp(near_mem_io$axi4_slave_rresp),
.axi4_slave_rlast(near_mem_io$axi4_slave_rlast),
.get_timer_interrupt_req_get(near_mem_io$get_timer_interrupt_req_get),
.RDY_get_timer_interrupt_req_get(near_mem_io$RDY_get_timer_interrupt_req_get),
.get_sw_interrupt_req_get(near_mem_io$get_sw_interrupt_req_get),
.RDY_get_sw_interrupt_req_get(near_mem_io$RDY_get_sw_interrupt_req_get));
// submodule plic
mkPLIC_16_2_7 plic(.CLK(CLK),
.RST_N(RST_N),
.axi4_slave_araddr(plic$axi4_slave_araddr),
.axi4_slave_arburst(plic$axi4_slave_arburst),
.axi4_slave_arcache(plic$axi4_slave_arcache),
.axi4_slave_arid(plic$axi4_slave_arid),
.axi4_slave_arlen(plic$axi4_slave_arlen),
.axi4_slave_arlock(plic$axi4_slave_arlock),
.axi4_slave_arprot(plic$axi4_slave_arprot),
.axi4_slave_arqos(plic$axi4_slave_arqos),
.axi4_slave_arregion(plic$axi4_slave_arregion),
.axi4_slave_arsize(plic$axi4_slave_arsize),
.axi4_slave_arvalid(plic$axi4_slave_arvalid),
.axi4_slave_awaddr(plic$axi4_slave_awaddr),
.axi4_slave_awburst(plic$axi4_slave_awburst),
.axi4_slave_awcache(plic$axi4_slave_awcache),
.axi4_slave_awid(plic$axi4_slave_awid),
.axi4_slave_awlen(plic$axi4_slave_awlen),
.axi4_slave_awlock(plic$axi4_slave_awlock),
.axi4_slave_awprot(plic$axi4_slave_awprot),
.axi4_slave_awqos(plic$axi4_slave_awqos),
.axi4_slave_awregion(plic$axi4_slave_awregion),
.axi4_slave_awsize(plic$axi4_slave_awsize),
.axi4_slave_awvalid(plic$axi4_slave_awvalid),
.axi4_slave_bready(plic$axi4_slave_bready),
.axi4_slave_rready(plic$axi4_slave_rready),
.axi4_slave_wdata(plic$axi4_slave_wdata),
.axi4_slave_wlast(plic$axi4_slave_wlast),
.axi4_slave_wstrb(plic$axi4_slave_wstrb),
.axi4_slave_wvalid(plic$axi4_slave_wvalid),
.set_addr_map_addr_base(plic$set_addr_map_addr_base),
.set_addr_map_addr_lim(plic$set_addr_map_addr_lim),
.set_verbosity_verbosity(plic$set_verbosity_verbosity),
.v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear),
.v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear),
.v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear),
.v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear),
.v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear),
.v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear),
.v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear),
.v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear),
.v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear),
.v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear),
.v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear),
.v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear),
.v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear),
.v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear),
.v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear),
.v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear),
.EN_set_verbosity(plic$EN_set_verbosity),
.EN_show_PLIC_state(plic$EN_show_PLIC_state),
.EN_server_reset_request_put(plic$EN_server_reset_request_put),
.EN_server_reset_response_get(plic$EN_server_reset_response_get),
.EN_set_addr_map(plic$EN_set_addr_map),
.RDY_set_verbosity(),
.RDY_show_PLIC_state(),
.RDY_server_reset_request_put(plic$RDY_server_reset_request_put),
.RDY_server_reset_response_get(plic$RDY_server_reset_response_get),
.RDY_set_addr_map(),
.axi4_slave_awready(plic$axi4_slave_awready),
.axi4_slave_wready(plic$axi4_slave_wready),
.axi4_slave_bvalid(plic$axi4_slave_bvalid),
.axi4_slave_bid(plic$axi4_slave_bid),
.axi4_slave_bresp(plic$axi4_slave_bresp),
.axi4_slave_arready(plic$axi4_slave_arready),
.axi4_slave_rvalid(plic$axi4_slave_rvalid),
.axi4_slave_rid(plic$axi4_slave_rid),
.axi4_slave_rdata(plic$axi4_slave_rdata),
.axi4_slave_rresp(plic$axi4_slave_rresp),
.axi4_slave_rlast(plic$axi4_slave_rlast),
.v_targets_0_m_eip(plic$v_targets_0_m_eip),
.v_targets_1_m_eip(plic$v_targets_1_m_eip));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim),
.m_plic_addr_base(soc_map$m_plic_addr_base),
.m_plic_addr_size(),
.m_plic_addr_lim(soc_map$m_plic_addr_lim),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_rl_wr_addr_channel
assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ;
// rule RL_rl_wr_data_channel
assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ;
// rule RL_rl_wr_response_channel
assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ;
// rule RL_rl_rd_addr_channel
assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ;
// rule RL_rl_rd_data_channel
assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ;
// rule RL_rl_wr_addr_channel_1
assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ;
// rule RL_rl_wr_data_channel_1
assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ;
// rule RL_rl_wr_response_channel_1
assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ;
// rule RL_rl_rd_addr_channel_1
assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ;
// rule RL_rl_rd_data_channel_1
assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ;
// rule RL_rl_wr_addr_channel_2
assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ;
// rule RL_rl_wr_data_channel_2
assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ;
// rule RL_rl_wr_response_channel_2
assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ;
// rule RL_rl_rd_addr_channel_2
assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ;
// rule RL_rl_rd_data_channel_2
assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ;
// rule RL_rl_wr_addr_channel_3
assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ;
// rule RL_rl_wr_data_channel_3
assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ;
// rule RL_rl_wr_response_channel_3
assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ;
// rule RL_rl_rd_addr_channel_3
assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ;
// rule RL_rl_rd_data_channel_3
assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ;
// rule RL_rl_relay_sw_interrupts
assign CAN_FIRE_RL_rl_relay_sw_interrupts =
near_mem_io$RDY_get_sw_interrupt_req_get ;
assign WILL_FIRE_RL_rl_relay_sw_interrupts =
near_mem_io$RDY_get_sw_interrupt_req_get ;
// rule RL_rl_relay_timer_interrupts
assign CAN_FIRE_RL_rl_relay_timer_interrupts =
near_mem_io$RDY_get_timer_interrupt_req_get ;
assign WILL_FIRE_RL_rl_relay_timer_interrupts =
near_mem_io$RDY_get_timer_interrupt_req_get ;
// rule RL_rl_relay_external_interrupts
assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ;
assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ;
// rule RL_rl_cpu_hart0_reset_from_soc_start
assign CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start =
near_mem_io$RDY_server_reset_request_put &&
plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ;
assign WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
// rule RL_rl_cpu_hart0_reset_complete
assign CAN_FIRE_RL_rl_cpu_hart0_reset_complete =
near_mem_io$RDY_server_reset_response_get &&
plic$RDY_server_reset_response_get &&
cpu$RDY_hart0_server_reset_response_get &&
f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_rl_cpu_hart0_reset_complete =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
// submodule cpu
assign cpu$dma_server_araddr = dma_server_araddr ;
assign cpu$dma_server_arburst = dma_server_arburst ;
assign cpu$dma_server_arcache = dma_server_arcache ;
assign cpu$dma_server_arid = dma_server_arid ;
assign cpu$dma_server_arlen = dma_server_arlen ;
assign cpu$dma_server_arlock = dma_server_arlock ;
assign cpu$dma_server_arprot = dma_server_arprot ;
assign cpu$dma_server_arqos = dma_server_arqos ;
assign cpu$dma_server_arregion = dma_server_arregion ;
assign cpu$dma_server_arsize = dma_server_arsize ;
assign cpu$dma_server_arvalid = dma_server_arvalid ;
assign cpu$dma_server_awaddr = dma_server_awaddr ;
assign cpu$dma_server_awburst = dma_server_awburst ;
assign cpu$dma_server_awcache = dma_server_awcache ;
assign cpu$dma_server_awid = dma_server_awid ;
assign cpu$dma_server_awlen = dma_server_awlen ;
assign cpu$dma_server_awlock = dma_server_awlock ;
assign cpu$dma_server_awprot = dma_server_awprot ;
assign cpu$dma_server_awqos = dma_server_awqos ;
assign cpu$dma_server_awregion = dma_server_awregion ;
assign cpu$dma_server_awsize = dma_server_awsize ;
assign cpu$dma_server_awvalid = dma_server_awvalid ;
assign cpu$dma_server_bready = dma_server_bready ;
assign cpu$dma_server_rready = dma_server_rready ;
assign cpu$dma_server_wdata = dma_server_wdata ;
assign cpu$dma_server_wlast = dma_server_wlast ;
assign cpu$dma_server_wstrb = dma_server_wstrb ;
assign cpu$dma_server_wvalid = dma_server_wvalid ;
assign cpu$hart0_server_reset_request_put = f_reset_reqs$D_OUT ;
assign cpu$imem_master_arready = cpu_imem_master_arready ;
assign cpu$imem_master_awready = cpu_imem_master_awready ;
assign cpu$imem_master_bid = cpu_imem_master_bid ;
assign cpu$imem_master_bresp = cpu_imem_master_bresp ;
assign cpu$imem_master_bvalid = cpu_imem_master_bvalid ;
assign cpu$imem_master_rdata = cpu_imem_master_rdata ;
assign cpu$imem_master_rid = cpu_imem_master_rid ;
assign cpu$imem_master_rlast = cpu_imem_master_rlast ;
assign cpu$imem_master_rresp = cpu_imem_master_rresp ;
assign cpu$imem_master_rvalid = cpu_imem_master_rvalid ;
assign cpu$imem_master_wready = cpu_imem_master_wready ;
assign cpu$m_external_interrupt_req_set_not_clear = plic$v_targets_0_m_eip ;
assign cpu$mem_master_arready = fabric_2x3$v_from_masters_0_arready ;
assign cpu$mem_master_awready = fabric_2x3$v_from_masters_0_awready ;
assign cpu$mem_master_bid = fabric_2x3$v_from_masters_0_bid ;
assign cpu$mem_master_bresp = fabric_2x3$v_from_masters_0_bresp ;
assign cpu$mem_master_bvalid = fabric_2x3$v_from_masters_0_bvalid ;
assign cpu$mem_master_rdata = fabric_2x3$v_from_masters_0_rdata ;
assign cpu$mem_master_rid = fabric_2x3$v_from_masters_0_rid ;
assign cpu$mem_master_rlast = fabric_2x3$v_from_masters_0_rlast ;
assign cpu$mem_master_rresp = fabric_2x3$v_from_masters_0_rresp ;
assign cpu$mem_master_rvalid = fabric_2x3$v_from_masters_0_rvalid ;
assign cpu$mem_master_wready = fabric_2x3$v_from_masters_0_wready ;
assign cpu$nmi_req_set_not_clear = nmi_req_set_not_clear ;
assign cpu$s_external_interrupt_req_set_not_clear = plic$v_targets_1_m_eip ;
assign cpu$set_verbosity_logdelay = set_verbosity_logdelay ;
assign cpu$set_verbosity_verbosity = set_verbosity_verbosity ;
assign cpu$set_watch_tohost_tohost_addr = set_watch_tohost_tohost_addr ;
assign cpu$set_watch_tohost_watch_tohost = set_watch_tohost_watch_tohost ;
assign cpu$software_interrupt_req_set_not_clear =
near_mem_io$get_sw_interrupt_req_get ;
assign cpu$timer_interrupt_req_set_not_clear =
near_mem_io$get_timer_interrupt_req_get ;
assign cpu$EN_hart0_server_reset_request_put =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign cpu$EN_hart0_server_reset_response_get =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign cpu$EN_set_verbosity = EN_set_verbosity ;
assign cpu$EN_set_watch_tohost = EN_set_watch_tohost ;
assign cpu$EN_ma_ddr4_ready = EN_ma_ddr4_ready ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = cpu_reset_server_request_put ;
assign f_reset_reqs$ENQ = EN_cpu_reset_server_request_put ;
assign f_reset_reqs$DEQ =
near_mem_io$RDY_server_reset_request_put &&
plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = cpu$hart0_server_reset_response_get ;
assign f_reset_rsps$ENQ =
near_mem_io$RDY_server_reset_response_get &&
plic$RDY_server_reset_response_get &&
cpu$RDY_hart0_server_reset_response_get &&
f_reset_rsps$FULL_N ;
assign f_reset_rsps$DEQ = EN_cpu_reset_server_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule fabric_2x3
assign fabric_2x3$set_verbosity_verbosity = 4'h0 ;
assign fabric_2x3$v_from_masters_0_araddr = cpu$mem_master_araddr ;
assign fabric_2x3$v_from_masters_0_arburst = cpu$mem_master_arburst ;
assign fabric_2x3$v_from_masters_0_arcache = cpu$mem_master_arcache ;
assign fabric_2x3$v_from_masters_0_arid = cpu$mem_master_arid ;
assign fabric_2x3$v_from_masters_0_arlen = cpu$mem_master_arlen ;
assign fabric_2x3$v_from_masters_0_arlock = cpu$mem_master_arlock ;
assign fabric_2x3$v_from_masters_0_arprot = cpu$mem_master_arprot ;
assign fabric_2x3$v_from_masters_0_arqos = cpu$mem_master_arqos ;
assign fabric_2x3$v_from_masters_0_arregion = cpu$mem_master_arregion ;
assign fabric_2x3$v_from_masters_0_arsize = cpu$mem_master_arsize ;
assign fabric_2x3$v_from_masters_0_arvalid = cpu$mem_master_arvalid ;
assign fabric_2x3$v_from_masters_0_awaddr = cpu$mem_master_awaddr ;
assign fabric_2x3$v_from_masters_0_awburst = cpu$mem_master_awburst ;
assign fabric_2x3$v_from_masters_0_awcache = cpu$mem_master_awcache ;
assign fabric_2x3$v_from_masters_0_awid = cpu$mem_master_awid ;
assign fabric_2x3$v_from_masters_0_awlen = cpu$mem_master_awlen ;
assign fabric_2x3$v_from_masters_0_awlock = cpu$mem_master_awlock ;
assign fabric_2x3$v_from_masters_0_awprot = cpu$mem_master_awprot ;
assign fabric_2x3$v_from_masters_0_awqos = cpu$mem_master_awqos ;
assign fabric_2x3$v_from_masters_0_awregion = cpu$mem_master_awregion ;
assign fabric_2x3$v_from_masters_0_awsize = cpu$mem_master_awsize ;
assign fabric_2x3$v_from_masters_0_awvalid = cpu$mem_master_awvalid ;
assign fabric_2x3$v_from_masters_0_bready = cpu$mem_master_bready ;
assign fabric_2x3$v_from_masters_0_rready = cpu$mem_master_rready ;
assign fabric_2x3$v_from_masters_0_wdata = cpu$mem_master_wdata ;
assign fabric_2x3$v_from_masters_0_wlast = cpu$mem_master_wlast ;
assign fabric_2x3$v_from_masters_0_wstrb = cpu$mem_master_wstrb ;
assign fabric_2x3$v_from_masters_0_wvalid = cpu$mem_master_wvalid ;
assign fabric_2x3$v_from_masters_1_araddr =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arburst =
2'b10 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arcache =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arid = 4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arlen =
8'b10101010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arlock = 1'b0 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arprot =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arqos =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arregion =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arsize =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_arvalid = 1'd0 ;
assign fabric_2x3$v_from_masters_1_awaddr =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awburst =
2'b10 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awcache =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awid = 4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awlen =
8'b10101010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awlock = 1'b0 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awprot =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awqos =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awregion =
4'b1010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awsize =
3'b010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_awvalid = 1'd0 ;
assign fabric_2x3$v_from_masters_1_bready = 1'd0 ;
assign fabric_2x3$v_from_masters_1_rready = 1'd0 ;
assign fabric_2x3$v_from_masters_1_wdata =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_wlast = 1'b0 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_wstrb =
8'b10101010 /* unspecified value */ ;
assign fabric_2x3$v_from_masters_1_wvalid = 1'd0 ;
assign fabric_2x3$v_to_slaves_0_arready = core_mem_master_arready ;
assign fabric_2x3$v_to_slaves_0_awready = core_mem_master_awready ;
assign fabric_2x3$v_to_slaves_0_bid = core_mem_master_bid ;
assign fabric_2x3$v_to_slaves_0_bresp = core_mem_master_bresp ;
assign fabric_2x3$v_to_slaves_0_bvalid = core_mem_master_bvalid ;
assign fabric_2x3$v_to_slaves_0_rdata = core_mem_master_rdata ;
assign fabric_2x3$v_to_slaves_0_rid = core_mem_master_rid ;
assign fabric_2x3$v_to_slaves_0_rlast = core_mem_master_rlast ;
assign fabric_2x3$v_to_slaves_0_rresp = core_mem_master_rresp ;
assign fabric_2x3$v_to_slaves_0_rvalid = core_mem_master_rvalid ;
assign fabric_2x3$v_to_slaves_0_wready = core_mem_master_wready ;
assign fabric_2x3$v_to_slaves_1_arready = near_mem_io$axi4_slave_arready ;
assign fabric_2x3$v_to_slaves_1_awready = near_mem_io$axi4_slave_awready ;
assign fabric_2x3$v_to_slaves_1_bid = near_mem_io$axi4_slave_bid ;
assign fabric_2x3$v_to_slaves_1_bresp = near_mem_io$axi4_slave_bresp ;
assign fabric_2x3$v_to_slaves_1_bvalid = near_mem_io$axi4_slave_bvalid ;
assign fabric_2x3$v_to_slaves_1_rdata = near_mem_io$axi4_slave_rdata ;
assign fabric_2x3$v_to_slaves_1_rid = near_mem_io$axi4_slave_rid ;
assign fabric_2x3$v_to_slaves_1_rlast = near_mem_io$axi4_slave_rlast ;
assign fabric_2x3$v_to_slaves_1_rresp = near_mem_io$axi4_slave_rresp ;
assign fabric_2x3$v_to_slaves_1_rvalid = near_mem_io$axi4_slave_rvalid ;
assign fabric_2x3$v_to_slaves_1_wready = near_mem_io$axi4_slave_wready ;
assign fabric_2x3$v_to_slaves_2_arready = plic$axi4_slave_arready ;
assign fabric_2x3$v_to_slaves_2_awready = plic$axi4_slave_awready ;
assign fabric_2x3$v_to_slaves_2_bid = plic$axi4_slave_bid ;
assign fabric_2x3$v_to_slaves_2_bresp = plic$axi4_slave_bresp ;
assign fabric_2x3$v_to_slaves_2_bvalid = plic$axi4_slave_bvalid ;
assign fabric_2x3$v_to_slaves_2_rdata = plic$axi4_slave_rdata ;
assign fabric_2x3$v_to_slaves_2_rid = plic$axi4_slave_rid ;
assign fabric_2x3$v_to_slaves_2_rlast = plic$axi4_slave_rlast ;
assign fabric_2x3$v_to_slaves_2_rresp = plic$axi4_slave_rresp ;
assign fabric_2x3$v_to_slaves_2_rvalid = plic$axi4_slave_rvalid ;
assign fabric_2x3$v_to_slaves_2_wready = plic$axi4_slave_wready ;
assign fabric_2x3$EN_reset = CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign fabric_2x3$EN_set_verbosity = 1'b0 ;
// submodule near_mem_io
assign near_mem_io$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ;
assign near_mem_io$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ;
assign near_mem_io$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ;
assign near_mem_io$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ;
assign near_mem_io$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ;
assign near_mem_io$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ;
assign near_mem_io$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ;
assign near_mem_io$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ;
assign near_mem_io$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ;
assign near_mem_io$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ;
assign near_mem_io$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ;
assign near_mem_io$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ;
assign near_mem_io$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ;
assign near_mem_io$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ;
assign near_mem_io$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ;
assign near_mem_io$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ;
assign near_mem_io$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ;
assign near_mem_io$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ;
assign near_mem_io$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ;
assign near_mem_io$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ;
assign near_mem_io$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ;
assign near_mem_io$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ;
assign near_mem_io$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ;
assign near_mem_io$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ;
assign near_mem_io$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ;
assign near_mem_io$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ;
assign near_mem_io$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ;
assign near_mem_io$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ;
assign near_mem_io$set_addr_map_addr_base =
soc_map$m_near_mem_io_addr_base ;
assign near_mem_io$set_addr_map_addr_lim = soc_map$m_near_mem_io_addr_lim ;
assign near_mem_io$EN_server_reset_request_put =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign near_mem_io$EN_server_reset_response_get =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign near_mem_io$EN_set_addr_map =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign near_mem_io$EN_get_timer_interrupt_req_get =
near_mem_io$RDY_get_timer_interrupt_req_get ;
assign near_mem_io$EN_get_sw_interrupt_req_get =
near_mem_io$RDY_get_sw_interrupt_req_get ;
// submodule plic
assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_2_araddr ;
assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_2_arburst ;
assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_2_arcache ;
assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_2_arid ;
assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_2_arlen ;
assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_2_arlock ;
assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_2_arprot ;
assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_2_arqos ;
assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_2_arregion ;
assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_2_arsize ;
assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_2_arvalid ;
assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_2_awaddr ;
assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_2_awburst ;
assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_2_awcache ;
assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_2_awid ;
assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_2_awlen ;
assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_2_awlock ;
assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_2_awprot ;
assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_2_awqos ;
assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_2_awregion ;
assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_2_awsize ;
assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_2_awvalid ;
assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_2_bready ;
assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_2_rready ;
assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_2_wdata ;
assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_2_wlast ;
assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_2_wstrb ;
assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_2_wvalid ;
assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ;
assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ;
assign plic$set_verbosity_verbosity = 4'h0 ;
assign plic$v_sources_0_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ;
assign plic$v_sources_10_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ;
assign plic$v_sources_11_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ;
assign plic$v_sources_12_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ;
assign plic$v_sources_13_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ;
assign plic$v_sources_14_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ;
assign plic$v_sources_15_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ;
assign plic$v_sources_1_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ;
assign plic$v_sources_2_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ;
assign plic$v_sources_3_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ;
assign plic$v_sources_4_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ;
assign plic$v_sources_5_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ;
assign plic$v_sources_6_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ;
assign plic$v_sources_7_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ;
assign plic$v_sources_8_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ;
assign plic$v_sources_9_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ;
assign plic$EN_set_verbosity = 1'b0 ;
assign plic$EN_show_PLIC_state = 1'b0 ;
assign plic$EN_server_reset_request_put =
CAN_FIRE_RL_rl_cpu_hart0_reset_from_soc_start ;
assign plic$EN_server_reset_response_get =
CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
assign plic$EN_set_addr_map = CAN_FIRE_RL_rl_cpu_hart0_reset_complete ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign plic_RDY_server_reset_request_put_AND_fabric_2_ETC___d8 =
plic$RDY_server_reset_request_put && fabric_2x3$RDY_reset &&
cpu$RDY_hart0_server_reset_request_put &&
f_reset_reqs$EMPTY_N ;
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start)
begin
v__h4601 = $stime;
#0;
end
v__h4595 = v__h4601 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_from_soc_start)
$display("%0d: Core.rl_cpu_hart0_reset_from_soc_start", v__h4595);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete)
begin
v__h4817 = $stime;
#0;
end
v__h4811 = v__h4817 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cpu_hart0_reset_complete)
$display("%0d: Core.rl_cpu_hart0_reset_complete", v__h4811);
end
// synopsys translate_on
endmodule // mkCore
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
// > Achronix eFPGA technology mapping. User must first simulate the generated \
// > netlist before going to test it on board/custom chip.
// > Input/Output buffers <
// Input buffer map
module \$__inpad (input I, output O);
PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
endmodule
// > end buffers <
// > Look-Up table <
// > VT: I still think Achronix folks would have chosen a better \
// > logic architecture.
// LUT Map
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
// VT: This is not consistent and ACE will complain: assign Y = ~A[0];
LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
end else
if (WIDTH == 2) begin
LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
end else
if(WIDTH == 3) begin
LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
end else
if(WIDTH == 4) begin
LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_
(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
// > end LUT <
// > Flops <
// DFF flop
module \$_DFF_P_ (input D, C, output Q);
DFF _TECHMAP_REPLACE_
(.q(Q), .d(D), .ck(C));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__SDFSTP_FUNCTIONAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_s_pg/sky130_fd_sc_hs__u_df_p_s_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfstp (
VPWR ,
VGND ,
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_s_pg `UNIT_DELAY u_df_p_s_pg0 (buf_Q , mux_out, CLK, SET, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_FUNCTIONAL_PP_V
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Sat Feb 11 18:26:51 EST 2017
//
// Method conflict info:
// Method: enq
// Conflict-free: deq, notEmpty, notFull
// Conflicts: enq
//
// Method: deq
// Conflict-free: enq, notEmpty, notFull
// Conflicts: deq
//
// Method: notEmpty
// Conflict-free: enq, deq, notEmpty, notFull
//
// Method: notFull
// Conflict-free: enq, deq, notEmpty, notFull
//
//
// Ports:
// Name I/O size props
// deq O 70
// notEmpty O 2 reg
// notFull O 2 reg
// CLK I 1 clock
// RST_N I 1 reset
// enq_fifo_in I 1
// enq_data_in I 70
// deq_fifo_out I 1
// EN_enq I 1
// EN_deq I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkInputVCQueues(CLK,
RST_N,
enq_fifo_in,
enq_data_in,
EN_enq,
deq_fifo_out,
EN_deq,
deq,
notEmpty,
notFull);
input CLK;
input RST_N;
// action method enq
input enq_fifo_in;
input [69 : 0] enq_data_in;
input EN_enq;
// actionvalue method deq
input deq_fifo_out;
input EN_deq;
output [69 : 0] deq;
// value method notEmpty
output [1 : 0] notEmpty;
// value method notFull
output [1 : 0] notFull;
// signals for module outputs
wire [69 : 0] deq;
wire [1 : 0] notEmpty, notFull;
// inlined wires
wire [2 : 0] inputVCQueues_ifc_mf_ifc_new_head$wget,
inputVCQueues_ifc_mf_ifc_new_tail$wget;
wire [1 : 0] inputVCQueues_ifc_mf_ifc_rdFIFO$wget,
inputVCQueues_ifc_mf_ifc_wrFIFO$wget;
// register inputVCQueues_ifc_mf_ifc_heads
reg [2 : 0] inputVCQueues_ifc_mf_ifc_heads;
wire [2 : 0] inputVCQueues_ifc_mf_ifc_heads$D_IN;
wire inputVCQueues_ifc_mf_ifc_heads$EN;
// register inputVCQueues_ifc_mf_ifc_heads_1
reg [2 : 0] inputVCQueues_ifc_mf_ifc_heads_1;
wire [2 : 0] inputVCQueues_ifc_mf_ifc_heads_1$D_IN;
wire inputVCQueues_ifc_mf_ifc_heads_1$EN;
// register inputVCQueues_ifc_mf_ifc_not_empty
reg inputVCQueues_ifc_mf_ifc_not_empty;
wire inputVCQueues_ifc_mf_ifc_not_empty$D_IN,
inputVCQueues_ifc_mf_ifc_not_empty$EN;
// register inputVCQueues_ifc_mf_ifc_not_empty_1
reg inputVCQueues_ifc_mf_ifc_not_empty_1;
wire inputVCQueues_ifc_mf_ifc_not_empty_1$D_IN,
inputVCQueues_ifc_mf_ifc_not_empty_1$EN;
// register inputVCQueues_ifc_mf_ifc_not_full
reg inputVCQueues_ifc_mf_ifc_not_full;
wire inputVCQueues_ifc_mf_ifc_not_full$D_IN,
inputVCQueues_ifc_mf_ifc_not_full$EN;
// register inputVCQueues_ifc_mf_ifc_not_full_1
reg inputVCQueues_ifc_mf_ifc_not_full_1;
wire inputVCQueues_ifc_mf_ifc_not_full_1$D_IN,
inputVCQueues_ifc_mf_ifc_not_full_1$EN;
// register inputVCQueues_ifc_mf_ifc_tails
reg [2 : 0] inputVCQueues_ifc_mf_ifc_tails;
wire [2 : 0] inputVCQueues_ifc_mf_ifc_tails$D_IN;
wire inputVCQueues_ifc_mf_ifc_tails$EN;
// register inputVCQueues_ifc_mf_ifc_tails_1
reg [2 : 0] inputVCQueues_ifc_mf_ifc_tails_1;
wire [2 : 0] inputVCQueues_ifc_mf_ifc_tails_1$D_IN;
wire inputVCQueues_ifc_mf_ifc_tails_1$EN;
// ports of submodule inputVCQueues_ifc_mf_ifc_fifoMem
wire [69 : 0] inputVCQueues_ifc_mf_ifc_fifoMem$D_IN,
inputVCQueues_ifc_mf_ifc_fifoMem$D_OUT;
wire [3 : 0] inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_IN,
inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_OUT;
wire inputVCQueues_ifc_mf_ifc_fifoMem$WE;
// remaining internal signals
wire [2 : 0] fifoRdPtr__h4019,
fifoWrPtr__h3549,
x__h2444,
x__h3036,
y__h2445,
y__h3037;
wire IF_deq_fifo_out_THEN_NOT_inputVCQueues_ifc_mf__ETC___d89,
IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88,
IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58,
IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36,
NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d38,
NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d41,
NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d43,
NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d60,
NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d63,
NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d65,
inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d52,
inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d54,
inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d30,
inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d32;
// actionvalue method deq
assign deq = inputVCQueues_ifc_mf_ifc_fifoMem$D_OUT ;
// value method notEmpty
assign notEmpty =
{ inputVCQueues_ifc_mf_ifc_not_empty_1,
inputVCQueues_ifc_mf_ifc_not_empty } ;
// value method notFull
assign notFull =
{ inputVCQueues_ifc_mf_ifc_not_full_1,
inputVCQueues_ifc_mf_ifc_not_full } ;
// submodule inputVCQueues_ifc_mf_ifc_fifoMem
RegFile_1port #( /*data_width*/ 32'd70,
/*addr_width*/ 32'd4) inputVCQueues_ifc_mf_ifc_fifoMem(.CLK(CLK),
.rst_n(RST_N),
.ADDR_IN(inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_IN),
.ADDR_OUT(inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_OUT),
.D_IN(inputVCQueues_ifc_mf_ifc_fifoMem$D_IN),
.WE(inputVCQueues_ifc_mf_ifc_fifoMem$WE),
.D_OUT(inputVCQueues_ifc_mf_ifc_fifoMem$D_OUT));
// inlined wires
assign inputVCQueues_ifc_mf_ifc_wrFIFO$wget = { 1'd1, enq_fifo_in } ;
assign inputVCQueues_ifc_mf_ifc_rdFIFO$wget = { 1'd1, deq_fifo_out } ;
assign inputVCQueues_ifc_mf_ifc_new_tail$wget = fifoWrPtr__h3549 + 3'd1 ;
assign inputVCQueues_ifc_mf_ifc_new_head$wget = fifoRdPtr__h4019 + 3'd1 ;
// register inputVCQueues_ifc_mf_ifc_heads
assign inputVCQueues_ifc_mf_ifc_heads$D_IN = x__h3036 ;
assign inputVCQueues_ifc_mf_ifc_heads$EN =
EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] &&
!inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ;
// register inputVCQueues_ifc_mf_ifc_heads_1
assign inputVCQueues_ifc_mf_ifc_heads_1$D_IN = x__h3036 ;
assign inputVCQueues_ifc_mf_ifc_heads_1$EN =
EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] &&
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ;
// register inputVCQueues_ifc_mf_ifc_not_empty
assign inputVCQueues_ifc_mf_ifc_not_empty$D_IN =
inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d32 ;
assign inputVCQueues_ifc_mf_ifc_not_empty$EN =
inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d32 ||
EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] &&
NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d63 ;
// register inputVCQueues_ifc_mf_ifc_not_empty_1
assign inputVCQueues_ifc_mf_ifc_not_empty_1$D_IN =
inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d30 ;
assign inputVCQueues_ifc_mf_ifc_not_empty_1$EN =
inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d30 ||
EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] &&
NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d60 ;
// register inputVCQueues_ifc_mf_ifc_not_full
assign inputVCQueues_ifc_mf_ifc_not_full$D_IN =
!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] ||
!NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d41 ;
assign inputVCQueues_ifc_mf_ifc_not_full$EN =
EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] &&
NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d41 ||
inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d54 ;
// register inputVCQueues_ifc_mf_ifc_not_full_1
assign inputVCQueues_ifc_mf_ifc_not_full_1$D_IN =
!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] ||
!NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d38 ;
assign inputVCQueues_ifc_mf_ifc_not_full_1$EN =
EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] &&
NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d38 ||
inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d52 ;
// register inputVCQueues_ifc_mf_ifc_tails
assign inputVCQueues_ifc_mf_ifc_tails$D_IN = x__h2444 ;
assign inputVCQueues_ifc_mf_ifc_tails$EN =
EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] &&
!inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ;
// register inputVCQueues_ifc_mf_ifc_tails_1
assign inputVCQueues_ifc_mf_ifc_tails_1$D_IN = x__h2444 ;
assign inputVCQueues_ifc_mf_ifc_tails_1$EN =
EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] &&
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ;
// submodule inputVCQueues_ifc_mf_ifc_fifoMem
assign inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_IN =
{ enq_fifo_in, fifoWrPtr__h3549 } ;
assign inputVCQueues_ifc_mf_ifc_fifoMem$ADDR_OUT =
{ deq_fifo_out, fifoRdPtr__h4019 } ;
assign inputVCQueues_ifc_mf_ifc_fifoMem$D_IN = enq_data_in ;
assign inputVCQueues_ifc_mf_ifc_fifoMem$WE = EN_enq ;
// remaining internal signals
assign IF_deq_fifo_out_THEN_NOT_inputVCQueues_ifc_mf__ETC___d89 =
deq_fifo_out ?
!inputVCQueues_ifc_mf_ifc_not_empty_1 :
!inputVCQueues_ifc_mf_ifc_not_empty ;
assign IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88 =
enq_fifo_in ?
!inputVCQueues_ifc_mf_ifc_not_full_1 :
!inputVCQueues_ifc_mf_ifc_not_full ;
assign IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58 =
x__h3036 == y__h3037 ;
assign IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36 =
x__h2444 == y__h2445 ;
assign NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d38 =
(!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) &&
IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36 &&
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ;
assign NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d41 =
(!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) &&
IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36 &&
!inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ;
assign NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d43 =
(!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) &&
IF_inputVCQueues_ifc_mf_ifc_new_tail_whas_THEN_ETC___d36 ;
assign NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d60 =
(!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) &&
IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58 &&
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ;
assign NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d63 =
(!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) &&
IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58 &&
!inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ;
assign NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d65 =
(!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) &&
IF_inputVCQueues_ifc_mf_ifc_new_head_whas__8_T_ETC___d58 ;
assign fifoRdPtr__h4019 =
deq_fifo_out ?
inputVCQueues_ifc_mf_ifc_heads_1 :
inputVCQueues_ifc_mf_ifc_heads ;
assign fifoWrPtr__h3549 =
enq_fifo_in ?
inputVCQueues_ifc_mf_ifc_tails_1 :
inputVCQueues_ifc_mf_ifc_tails ;
assign inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d52 =
EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] &&
(!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) &&
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ;
assign inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_AND_in_ETC___d54 =
EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] &&
(!EN_enq || !inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0]) &&
!inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ;
assign inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d30 =
EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] &&
(!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) &&
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ;
assign inputVCQueues_ifc_mf_ifc_wrFIFO_whas_AND_input_ETC___d32 =
EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] &&
(!EN_deq || !inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] ||
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] !=
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0]) &&
!inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ;
assign x__h2444 = EN_enq ? inputVCQueues_ifc_mf_ifc_new_tail$wget : 3'd0 ;
assign x__h3036 = EN_deq ? inputVCQueues_ifc_mf_ifc_new_head$wget : 3'd0 ;
assign y__h2445 =
inputVCQueues_ifc_mf_ifc_wrFIFO$wget[0] ?
inputVCQueues_ifc_mf_ifc_heads_1 :
inputVCQueues_ifc_mf_ifc_heads ;
assign y__h3037 =
inputVCQueues_ifc_mf_ifc_rdFIFO$wget[0] ?
inputVCQueues_ifc_mf_ifc_tails_1 :
inputVCQueues_ifc_mf_ifc_tails ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
inputVCQueues_ifc_mf_ifc_heads <= `BSV_ASSIGNMENT_DELAY 3'd0;
inputVCQueues_ifc_mf_ifc_heads_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
inputVCQueues_ifc_mf_ifc_not_empty <= `BSV_ASSIGNMENT_DELAY 1'd0;
inputVCQueues_ifc_mf_ifc_not_empty_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
inputVCQueues_ifc_mf_ifc_not_full <= `BSV_ASSIGNMENT_DELAY 1'd1;
inputVCQueues_ifc_mf_ifc_not_full_1 <= `BSV_ASSIGNMENT_DELAY 1'd1;
inputVCQueues_ifc_mf_ifc_tails <= `BSV_ASSIGNMENT_DELAY 3'd0;
inputVCQueues_ifc_mf_ifc_tails_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
end
else
begin
if (inputVCQueues_ifc_mf_ifc_heads$EN)
inputVCQueues_ifc_mf_ifc_heads <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_heads$D_IN;
if (inputVCQueues_ifc_mf_ifc_heads_1$EN)
inputVCQueues_ifc_mf_ifc_heads_1 <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_heads_1$D_IN;
if (inputVCQueues_ifc_mf_ifc_not_empty$EN)
inputVCQueues_ifc_mf_ifc_not_empty <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_not_empty$D_IN;
if (inputVCQueues_ifc_mf_ifc_not_empty_1$EN)
inputVCQueues_ifc_mf_ifc_not_empty_1 <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_not_empty_1$D_IN;
if (inputVCQueues_ifc_mf_ifc_not_full$EN)
inputVCQueues_ifc_mf_ifc_not_full <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_not_full$D_IN;
if (inputVCQueues_ifc_mf_ifc_not_full_1$EN)
inputVCQueues_ifc_mf_ifc_not_full_1 <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_not_full_1$D_IN;
if (inputVCQueues_ifc_mf_ifc_tails$EN)
inputVCQueues_ifc_mf_ifc_tails <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_tails$D_IN;
if (inputVCQueues_ifc_mf_ifc_tails_1$EN)
inputVCQueues_ifc_mf_ifc_tails_1 <= `BSV_ASSIGNMENT_DELAY
inputVCQueues_ifc_mf_ifc_tails_1$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
inputVCQueues_ifc_mf_ifc_heads = 3'h2;
inputVCQueues_ifc_mf_ifc_heads_1 = 3'h2;
inputVCQueues_ifc_mf_ifc_not_empty = 1'h0;
inputVCQueues_ifc_mf_ifc_not_empty_1 = 1'h0;
inputVCQueues_ifc_mf_ifc_not_full = 1'h0;
inputVCQueues_ifc_mf_ifc_not_full_1 = 1'h0;
inputVCQueues_ifc_mf_ifc_tails = 3'h2;
inputVCQueues_ifc_mf_ifc_tails_1 = 3'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N)
if (EN_enq && IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88)
$write("");
if (RST_N)
if (EN_enq && IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88)
$write("");
if (RST_N)
if (EN_enq && IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88)
$display("Dynamic assertion failed: \"MultiFIFOMem.bsv\", line 156, column 38\nEnqueing to full FIFO in MultiFIFOMem!");
if (RST_N)
if (EN_enq && IF_enq_fifo_in_THEN_NOT_inputVCQueues_ifc_mf_i_ETC___d88)
$finish(32'd0);
if (RST_N) if (EN_enq) $write("");
if (RST_N)
if (EN_deq && IF_deq_fifo_out_THEN_NOT_inputVCQueues_ifc_mf__ETC___d89)
$display("Dynamic assertion failed: \"MultiFIFOMem.bsv\", line 190, column 40\nDequeing from empty FIFO in MultiFIFOMem!");
if (RST_N)
if (EN_deq && IF_deq_fifo_out_THEN_NOT_inputVCQueues_ifc_mf__ETC___d89)
$finish(32'd0);
if (RST_N) if (EN_deq) $write("");
if (RST_N)
if (EN_enq && inputVCQueues_ifc_mf_ifc_wrFIFO$wget[1] &&
NOT_inputVCQueues_ifc_mf_ifc_rdFIFO_whas__2_3__ETC___d43)
$write("");
if (RST_N)
if (EN_deq && inputVCQueues_ifc_mf_ifc_rdFIFO$wget[1] &&
NOT_inputVCQueues_ifc_mf_ifc_wrFIFO_whas_5_OR__ETC___d65)
$write("");
end
// synopsys translate_on
endmodule // mkInputVCQueues
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:52:04 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_ov7670_controller_1_0 -prefix
// system_ov7670_controller_1_0_ system_ov7670_controller_0_0_sim_netlist.v
// Design : system_ov7670_controller_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_ov7670_controller_1_0_i2c_sender
(E,
sioc,
p_0_in,
\busy_sr_reg[1]_0 ,
siod,
\busy_sr_reg[31]_0 ,
clk,
p_1_in,
DOADO,
\busy_sr_reg[31]_1 );
output [0:0]E;
output sioc;
output p_0_in;
output \busy_sr_reg[1]_0 ;
output siod;
input \busy_sr_reg[31]_0 ;
input clk;
input [0:0]p_1_in;
input [15:0]DOADO;
input [0:0]\busy_sr_reg[31]_1 ;
wire [15:0]DOADO;
wire [0:0]E;
wire busy_sr0;
wire \busy_sr[0]_i_3_n_0 ;
wire \busy_sr[0]_i_5_n_0 ;
wire \busy_sr[10]_i_1_n_0 ;
wire \busy_sr[11]_i_1_n_0 ;
wire \busy_sr[12]_i_1_n_0 ;
wire \busy_sr[13]_i_1_n_0 ;
wire \busy_sr[14]_i_1_n_0 ;
wire \busy_sr[15]_i_1_n_0 ;
wire \busy_sr[16]_i_1_n_0 ;
wire \busy_sr[17]_i_1_n_0 ;
wire \busy_sr[18]_i_1_n_0 ;
wire \busy_sr[19]_i_1_n_0 ;
wire \busy_sr[1]_i_1_n_0 ;
wire \busy_sr[20]_i_1_n_0 ;
wire \busy_sr[21]_i_1_n_0 ;
wire \busy_sr[22]_i_1_n_0 ;
wire \busy_sr[23]_i_1_n_0 ;
wire \busy_sr[24]_i_1_n_0 ;
wire \busy_sr[25]_i_1_n_0 ;
wire \busy_sr[26]_i_1_n_0 ;
wire \busy_sr[27]_i_1_n_0 ;
wire \busy_sr[28]_i_1_n_0 ;
wire \busy_sr[29]_i_1_n_0 ;
wire \busy_sr[2]_i_1_n_0 ;
wire \busy_sr[30]_i_1_n_0 ;
wire \busy_sr[31]_i_1_n_0 ;
wire \busy_sr[31]_i_2_n_0 ;
wire \busy_sr[3]_i_1_n_0 ;
wire \busy_sr[4]_i_1_n_0 ;
wire \busy_sr[5]_i_1_n_0 ;
wire \busy_sr[6]_i_1_n_0 ;
wire \busy_sr[7]_i_1_n_0 ;
wire \busy_sr[8]_i_1_n_0 ;
wire \busy_sr[9]_i_1_n_0 ;
wire \busy_sr_reg[1]_0 ;
wire \busy_sr_reg[31]_0 ;
wire [0:0]\busy_sr_reg[31]_1 ;
wire \busy_sr_reg_n_0_[0] ;
wire \busy_sr_reg_n_0_[10] ;
wire \busy_sr_reg_n_0_[11] ;
wire \busy_sr_reg_n_0_[12] ;
wire \busy_sr_reg_n_0_[13] ;
wire \busy_sr_reg_n_0_[14] ;
wire \busy_sr_reg_n_0_[15] ;
wire \busy_sr_reg_n_0_[16] ;
wire \busy_sr_reg_n_0_[17] ;
wire \busy_sr_reg_n_0_[18] ;
wire \busy_sr_reg_n_0_[1] ;
wire \busy_sr_reg_n_0_[21] ;
wire \busy_sr_reg_n_0_[22] ;
wire \busy_sr_reg_n_0_[23] ;
wire \busy_sr_reg_n_0_[24] ;
wire \busy_sr_reg_n_0_[25] ;
wire \busy_sr_reg_n_0_[26] ;
wire \busy_sr_reg_n_0_[27] ;
wire \busy_sr_reg_n_0_[28] ;
wire \busy_sr_reg_n_0_[29] ;
wire \busy_sr_reg_n_0_[2] ;
wire \busy_sr_reg_n_0_[30] ;
wire \busy_sr_reg_n_0_[3] ;
wire \busy_sr_reg_n_0_[4] ;
wire \busy_sr_reg_n_0_[5] ;
wire \busy_sr_reg_n_0_[6] ;
wire \busy_sr_reg_n_0_[7] ;
wire \busy_sr_reg_n_0_[8] ;
wire \busy_sr_reg_n_0_[9] ;
wire clk;
wire \data_sr[10]_i_1_n_0 ;
wire \data_sr[12]_i_1_n_0 ;
wire \data_sr[13]_i_1_n_0 ;
wire \data_sr[14]_i_1_n_0 ;
wire \data_sr[15]_i_1_n_0 ;
wire \data_sr[16]_i_1_n_0 ;
wire \data_sr[17]_i_1_n_0 ;
wire \data_sr[18]_i_1_n_0 ;
wire \data_sr[19]_i_1_n_0 ;
wire \data_sr[22]_i_1_n_0 ;
wire \data_sr[27]_i_1_n_0 ;
wire \data_sr[30]_i_1_n_0 ;
wire \data_sr[31]_i_1_n_0 ;
wire \data_sr[31]_i_2_n_0 ;
wire \data_sr[3]_i_1_n_0 ;
wire \data_sr[4]_i_1_n_0 ;
wire \data_sr[5]_i_1_n_0 ;
wire \data_sr[6]_i_1_n_0 ;
wire \data_sr[7]_i_1_n_0 ;
wire \data_sr[8]_i_1_n_0 ;
wire \data_sr[9]_i_1_n_0 ;
wire \data_sr_reg_n_0_[10] ;
wire \data_sr_reg_n_0_[11] ;
wire \data_sr_reg_n_0_[12] ;
wire \data_sr_reg_n_0_[13] ;
wire \data_sr_reg_n_0_[14] ;
wire \data_sr_reg_n_0_[15] ;
wire \data_sr_reg_n_0_[16] ;
wire \data_sr_reg_n_0_[17] ;
wire \data_sr_reg_n_0_[18] ;
wire \data_sr_reg_n_0_[19] ;
wire \data_sr_reg_n_0_[1] ;
wire \data_sr_reg_n_0_[20] ;
wire \data_sr_reg_n_0_[21] ;
wire \data_sr_reg_n_0_[22] ;
wire \data_sr_reg_n_0_[23] ;
wire \data_sr_reg_n_0_[24] ;
wire \data_sr_reg_n_0_[25] ;
wire \data_sr_reg_n_0_[26] ;
wire \data_sr_reg_n_0_[27] ;
wire \data_sr_reg_n_0_[28] ;
wire \data_sr_reg_n_0_[29] ;
wire \data_sr_reg_n_0_[2] ;
wire \data_sr_reg_n_0_[30] ;
wire \data_sr_reg_n_0_[31] ;
wire \data_sr_reg_n_0_[3] ;
wire \data_sr_reg_n_0_[4] ;
wire \data_sr_reg_n_0_[5] ;
wire \data_sr_reg_n_0_[6] ;
wire \data_sr_reg_n_0_[7] ;
wire \data_sr_reg_n_0_[8] ;
wire \data_sr_reg_n_0_[9] ;
wire [7:6]divider_reg__0;
wire [5:0]divider_reg__1;
wire p_0_in;
wire [7:0]p_0_in__0;
wire [0:0]p_1_in;
wire [1:0]p_1_in_0;
wire sioc;
wire sioc_i_1_n_0;
wire sioc_i_2_n_0;
wire sioc_i_3_n_0;
wire sioc_i_4_n_0;
wire sioc_i_5_n_0;
wire siod;
wire siod_INST_0_i_1_n_0;
LUT6 #(
.INIT(64'h4000FFFF40004000))
\busy_sr[0]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.I2(divider_reg__0[7]),
.I3(p_0_in),
.I4(\busy_sr_reg[1]_0 ),
.I5(p_1_in),
.O(busy_sr0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\busy_sr[0]_i_3
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(\busy_sr[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\busy_sr[0]_i_4
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[3]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(\busy_sr[0]_i_5_n_0 ),
.O(\busy_sr_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFFFE))
\busy_sr[0]_i_5
(.I0(divider_reg__1[5]),
.I1(divider_reg__1[4]),
.I2(divider_reg__0[7]),
.I3(divider_reg__0[6]),
.O(\busy_sr[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[10]_i_1
(.I0(\busy_sr_reg_n_0_[9] ),
.I1(p_0_in),
.O(\busy_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[11]_i_1
(.I0(\busy_sr_reg_n_0_[10] ),
.I1(p_0_in),
.O(\busy_sr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[12]_i_1
(.I0(\busy_sr_reg_n_0_[11] ),
.I1(p_0_in),
.O(\busy_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[13]_i_1
(.I0(\busy_sr_reg_n_0_[12] ),
.I1(p_0_in),
.O(\busy_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[14]_i_1
(.I0(\busy_sr_reg_n_0_[13] ),
.I1(p_0_in),
.O(\busy_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[15]_i_1
(.I0(\busy_sr_reg_n_0_[14] ),
.I1(p_0_in),
.O(\busy_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[16]_i_1
(.I0(\busy_sr_reg_n_0_[15] ),
.I1(p_0_in),
.O(\busy_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[17]_i_1
(.I0(\busy_sr_reg_n_0_[16] ),
.I1(p_0_in),
.O(\busy_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[18]_i_1
(.I0(\busy_sr_reg_n_0_[17] ),
.I1(p_0_in),
.O(\busy_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[19]_i_1
(.I0(\busy_sr_reg_n_0_[18] ),
.I1(p_0_in),
.O(\busy_sr[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[1]_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(p_0_in),
.O(\busy_sr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[20]_i_1
(.I0(p_1_in_0[0]),
.I1(p_0_in),
.O(\busy_sr[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[21]_i_1
(.I0(p_1_in_0[1]),
.I1(p_0_in),
.O(\busy_sr[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[22]_i_1
(.I0(\busy_sr_reg_n_0_[21] ),
.I1(p_0_in),
.O(\busy_sr[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[23]_i_1
(.I0(\busy_sr_reg_n_0_[22] ),
.I1(p_0_in),
.O(\busy_sr[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[24]_i_1
(.I0(\busy_sr_reg_n_0_[23] ),
.I1(p_0_in),
.O(\busy_sr[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[25]_i_1
(.I0(\busy_sr_reg_n_0_[24] ),
.I1(p_0_in),
.O(\busy_sr[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[26]_i_1
(.I0(\busy_sr_reg_n_0_[25] ),
.I1(p_0_in),
.O(\busy_sr[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[27]_i_1
(.I0(\busy_sr_reg_n_0_[26] ),
.I1(p_0_in),
.O(\busy_sr[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[28]_i_1
(.I0(\busy_sr_reg_n_0_[27] ),
.I1(p_0_in),
.O(\busy_sr[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[29]_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(p_0_in),
.O(\busy_sr[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[2]_i_1
(.I0(\busy_sr_reg_n_0_[1] ),
.I1(p_0_in),
.O(\busy_sr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[30]_i_1
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(p_0_in),
.O(\busy_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h22222222A2222222))
\busy_sr[31]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.I3(divider_reg__0[7]),
.I4(divider_reg__0[6]),
.I5(\busy_sr[0]_i_3_n_0 ),
.O(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[31]_i_2
(.I0(p_0_in),
.I1(\busy_sr_reg_n_0_[30] ),
.O(\busy_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[3]_i_1
(.I0(\busy_sr_reg_n_0_[2] ),
.I1(p_0_in),
.O(\busy_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[4]_i_1
(.I0(\busy_sr_reg_n_0_[3] ),
.I1(p_0_in),
.O(\busy_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[5]_i_1
(.I0(\busy_sr_reg_n_0_[4] ),
.I1(p_0_in),
.O(\busy_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[6]_i_1
(.I0(\busy_sr_reg_n_0_[5] ),
.I1(p_0_in),
.O(\busy_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[7]_i_1
(.I0(\busy_sr_reg_n_0_[6] ),
.I1(p_0_in),
.O(\busy_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[8]_i_1
(.I0(\busy_sr_reg_n_0_[7] ),
.I1(p_0_in),
.O(\busy_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[9]_i_1
(.I0(\busy_sr_reg_n_0_[8] ),
.I1(p_0_in),
.O(\busy_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\busy_sr_reg[0]
(.C(clk),
.CE(busy_sr0),
.D(p_1_in),
.Q(\busy_sr_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[10]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[10] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[11]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[11] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[12]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[12] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[13]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[13] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[14]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[14] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[15]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[15] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[16]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[16] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[17]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[17] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[18]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[18] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[19]_i_1_n_0 ),
.Q(p_1_in_0[0]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[1]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[1] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[20]_i_1_n_0 ),
.Q(p_1_in_0[1]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[21]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[21] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[22]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[22]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[22] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[23]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[23] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[24]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[24] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[25]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[25] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[26]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[26] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[27]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[27]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[27] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[28]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[28] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[29]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[29] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[2]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[2] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[30]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[30] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[31]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[31]_i_2_n_0 ),
.Q(p_0_in),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[3]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[3] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[4]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[4] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[5]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[5] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[6]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[6] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[7]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[7] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[8]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[8] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[9]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[9] ),
.S(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[10]_i_1
(.I0(\data_sr_reg_n_0_[9] ),
.I1(p_0_in),
.I2(DOADO[7]),
.O(\data_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[12]_i_1
(.I0(\data_sr_reg_n_0_[11] ),
.I1(p_0_in),
.I2(DOADO[8]),
.O(\data_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[13]_i_1
(.I0(\data_sr_reg_n_0_[12] ),
.I1(p_0_in),
.I2(DOADO[9]),
.O(\data_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[14]_i_1
(.I0(\data_sr_reg_n_0_[13] ),
.I1(p_0_in),
.I2(DOADO[10]),
.O(\data_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[15]_i_1
(.I0(\data_sr_reg_n_0_[14] ),
.I1(p_0_in),
.I2(DOADO[11]),
.O(\data_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[16]_i_1
(.I0(\data_sr_reg_n_0_[15] ),
.I1(p_0_in),
.I2(DOADO[12]),
.O(\data_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[17]_i_1
(.I0(\data_sr_reg_n_0_[16] ),
.I1(p_0_in),
.I2(DOADO[13]),
.O(\data_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[18]_i_1
(.I0(\data_sr_reg_n_0_[17] ),
.I1(p_0_in),
.I2(DOADO[14]),
.O(\data_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[19]_i_1
(.I0(\data_sr_reg_n_0_[18] ),
.I1(p_0_in),
.I2(DOADO[15]),
.O(\data_sr[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[22]_i_1
(.I0(\data_sr_reg_n_0_[22] ),
.I1(\data_sr_reg_n_0_[21] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[27]_i_1
(.I0(\data_sr_reg_n_0_[27] ),
.I1(\data_sr_reg_n_0_[26] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[27]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\data_sr[30]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.O(\data_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[31]_i_1
(.I0(\data_sr_reg_n_0_[31] ),
.I1(\data_sr_reg_n_0_[30] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\data_sr[31]_i_2
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(\data_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[3]_i_1
(.I0(\data_sr_reg_n_0_[2] ),
.I1(p_0_in),
.I2(DOADO[0]),
.O(\data_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[4]_i_1
(.I0(\data_sr_reg_n_0_[3] ),
.I1(p_0_in),
.I2(DOADO[1]),
.O(\data_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[5]_i_1
(.I0(\data_sr_reg_n_0_[4] ),
.I1(p_0_in),
.I2(DOADO[2]),
.O(\data_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[6]_i_1
(.I0(\data_sr_reg_n_0_[5] ),
.I1(p_0_in),
.I2(DOADO[3]),
.O(\data_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[7]_i_1
(.I0(\data_sr_reg_n_0_[6] ),
.I1(p_0_in),
.I2(DOADO[4]),
.O(\data_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[8]_i_1
(.I0(\data_sr_reg_n_0_[7] ),
.I1(p_0_in),
.I2(DOADO[5]),
.O(\data_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[9]_i_1
(.I0(\data_sr_reg_n_0_[8] ),
.I1(p_0_in),
.I2(DOADO[6]),
.O(\data_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[10]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[10] ),
.Q(\data_sr_reg_n_0_[11] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[12]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[13]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[14]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[15]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[16]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[16] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[17]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[17] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[18]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[18] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[19]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[19] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(p_0_in),
.Q(\data_sr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[19] ),
.Q(\data_sr_reg_n_0_[20] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[20] ),
.Q(\data_sr_reg_n_0_[21] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[22]
(.C(clk),
.CE(1'b1),
.D(\data_sr[22]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[22] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[22] ),
.Q(\data_sr_reg_n_0_[23] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[23] ),
.Q(\data_sr_reg_n_0_[24] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[24] ),
.Q(\data_sr_reg_n_0_[25] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[25] ),
.Q(\data_sr_reg_n_0_[26] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[27]
(.C(clk),
.CE(1'b1),
.D(\data_sr[27]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[27] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[27] ),
.Q(\data_sr_reg_n_0_[28] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[28] ),
.Q(\data_sr_reg_n_0_[29] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[1] ),
.Q(\data_sr_reg_n_0_[2] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[29] ),
.Q(\data_sr_reg_n_0_[30] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[31]
(.C(clk),
.CE(1'b1),
.D(\data_sr[31]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[31] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[3]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[4]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[5]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[6]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[7]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[8]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[9]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT1 #(
.INIT(2'h1))
\divider[0]_i_1
(.I0(divider_reg__1[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\divider[1]_i_1
(.I0(divider_reg__1[0]),
.I1(divider_reg__1[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\divider[2]_i_1
(.I0(divider_reg__1[1]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[2]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\divider[3]_i_1
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[1]),
.I3(divider_reg__1[3]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\divider[4]_i_1
(.I0(divider_reg__1[3]),
.I1(divider_reg__1[1]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[2]),
.I4(divider_reg__1[4]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\divider[5]_i_1
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(p_0_in__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\divider[6]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hD2))
\divider[7]_i_2
(.I0(divider_reg__0[6]),
.I1(\busy_sr[0]_i_3_n_0 ),
.I2(divider_reg__0[7]),
.O(p_0_in__0[7]));
FDRE #(
.INIT(1'b1))
\divider_reg[0]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[0]),
.Q(divider_reg__1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[1]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[1]),
.Q(divider_reg__1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[2]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[2]),
.Q(divider_reg__1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[3]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[3]),
.Q(divider_reg__1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[4]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[4]),
.Q(divider_reg__1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[5]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[5]),
.Q(divider_reg__1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[6]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[6]),
.Q(divider_reg__0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[7]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[7]),
.Q(divider_reg__0[7]),
.R(1'b0));
LUT6 #(
.INIT(64'hFCFCFFF8FFFFFFFF))
sioc_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(sioc_i_2_n_0),
.I2(sioc_i_3_n_0),
.I3(\busy_sr_reg_n_0_[1] ),
.I4(sioc_i_4_n_0),
.I5(p_0_in),
.O(sioc_i_1_n_0));
LUT2 #(
.INIT(4'h6))
sioc_i_2
(.I0(divider_reg__0[6]),
.I1(divider_reg__0[7]),
.O(sioc_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hA222))
sioc_i_3
(.I0(sioc_i_5_n_0),
.I1(\busy_sr_reg_n_0_[30] ),
.I2(divider_reg__0[6]),
.I3(p_0_in),
.O(sioc_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7FFF))
sioc_i_4
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(\busy_sr_reg_n_0_[2] ),
.I2(p_0_in),
.I3(\busy_sr_reg_n_0_[30] ),
.O(sioc_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
sioc_i_5
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(\busy_sr_reg_n_0_[1] ),
.I2(\busy_sr_reg_n_0_[29] ),
.I3(\busy_sr_reg_n_0_[2] ),
.O(sioc_i_5_n_0));
FDRE sioc_reg
(.C(clk),
.CE(1'b1),
.D(sioc_i_1_n_0),
.Q(sioc),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
siod_INST_0
(.I0(\data_sr_reg_n_0_[31] ),
.I1(siod_INST_0_i_1_n_0),
.O(siod));
LUT6 #(
.INIT(64'hB0BBB0BB0000B0BB))
siod_INST_0_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(\busy_sr_reg_n_0_[29] ),
.I2(p_1_in_0[0]),
.I3(p_1_in_0[1]),
.I4(\busy_sr_reg_n_0_[11] ),
.I5(\busy_sr_reg_n_0_[10] ),
.O(siod_INST_0_i_1_n_0));
FDRE taken_reg
(.C(clk),
.CE(1'b1),
.D(\busy_sr_reg[31]_0 ),
.Q(E),
.R(1'b0));
endmodule
module system_ov7670_controller_1_0_ov7670_controller
(config_finished,
siod,
xclk,
sioc,
resend,
clk);
output config_finished;
output siod;
output xclk;
output sioc;
input resend;
input clk;
wire Inst_i2c_sender_n_3;
wire Inst_ov7670_registers_n_16;
wire Inst_ov7670_registers_n_18;
wire clk;
wire config_finished;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire sioc;
wire siod;
wire [15:0]sreg_reg;
wire sys_clk_i_1_n_0;
wire taken;
wire xclk;
system_ov7670_controller_1_0_i2c_sender Inst_i2c_sender
(.DOADO(sreg_reg),
.E(taken),
.\busy_sr_reg[1]_0 (Inst_i2c_sender_n_3),
.\busy_sr_reg[31]_0 (Inst_ov7670_registers_n_18),
.\busy_sr_reg[31]_1 (Inst_ov7670_registers_n_16),
.clk(clk),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.sioc(sioc),
.siod(siod));
system_ov7670_controller_1_0_ov7670_registers Inst_ov7670_registers
(.DOADO(sreg_reg),
.E(taken),
.clk(clk),
.config_finished(config_finished),
.\divider_reg[2] (Inst_i2c_sender_n_3),
.\divider_reg[7] (Inst_ov7670_registers_n_16),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.resend(resend),
.taken_reg(Inst_ov7670_registers_n_18));
LUT1 #(
.INIT(2'h1))
sys_clk_i_1
(.I0(xclk),
.O(sys_clk_i_1_n_0));
FDRE #(
.INIT(1'b0))
sys_clk_reg
(.C(clk),
.CE(1'b1),
.D(sys_clk_i_1_n_0),
.Q(xclk),
.R(1'b0));
endmodule
module system_ov7670_controller_1_0_ov7670_registers
(DOADO,
\divider_reg[7] ,
config_finished,
taken_reg,
p_1_in,
clk,
\divider_reg[2] ,
p_0_in,
resend,
E);
output [15:0]DOADO;
output [0:0]\divider_reg[7] ;
output config_finished;
output taken_reg;
output [0:0]p_1_in;
input clk;
input \divider_reg[2] ;
input p_0_in;
input resend;
input [0:0]E;
wire [15:0]DOADO;
wire [0:0]E;
wire [7:0]address;
wire [7:0]address_reg__0;
wire \address_rep[0]_i_1_n_0 ;
wire \address_rep[1]_i_1_n_0 ;
wire \address_rep[2]_i_1_n_0 ;
wire \address_rep[3]_i_1_n_0 ;
wire \address_rep[4]_i_1_n_0 ;
wire \address_rep[5]_i_1_n_0 ;
wire \address_rep[6]_i_1_n_0 ;
wire \address_rep[7]_i_1_n_0 ;
wire \address_rep[7]_i_2_n_0 ;
wire clk;
wire config_finished;
wire config_finished_INST_0_i_1_n_0;
wire config_finished_INST_0_i_2_n_0;
wire config_finished_INST_0_i_3_n_0;
wire config_finished_INST_0_i_4_n_0;
wire \divider_reg[2] ;
wire [0:0]\divider_reg[7] ;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire taken_reg;
wire [15:0]NLW_sreg_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPBDOP_UNCONNECTED;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address_reg__0[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address_reg__0[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address_reg__0[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address_reg__0[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address_reg__0[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address_reg__0[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address_reg__0[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address_reg__0[7]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address[7]),
.R(resend));
LUT1 #(
.INIT(2'h1))
\address_rep[0]_i_1
(.I0(address_reg__0[0]),
.O(\address_rep[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h6))
\address_rep[1]_i_1
(.I0(address_reg__0[0]),
.I1(address_reg__0[1]),
.O(\address_rep[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h78))
\address_rep[2]_i_1
(.I0(address_reg__0[1]),
.I1(address_reg__0[0]),
.I2(address_reg__0[2]),
.O(\address_rep[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h7F80))
\address_rep[3]_i_1
(.I0(address_reg__0[2]),
.I1(address_reg__0[0]),
.I2(address_reg__0[1]),
.I3(address_reg__0[3]),
.O(\address_rep[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h7FFF8000))
\address_rep[4]_i_1
(.I0(address_reg__0[3]),
.I1(address_reg__0[1]),
.I2(address_reg__0[0]),
.I3(address_reg__0[2]),
.I4(address_reg__0[4]),
.O(\address_rep[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\address_rep[5]_i_1
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h9))
\address_rep[6]_i_1
(.I0(\address_rep[7]_i_2_n_0 ),
.I1(address_reg__0[6]),
.O(\address_rep[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hD2))
\address_rep[7]_i_1
(.I0(address_reg__0[6]),
.I1(\address_rep[7]_i_2_n_0 ),
.I2(address_reg__0[7]),
.O(\address_rep[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\address_rep[7]_i_2
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h0000FFFE))
\busy_sr[0]_i_2
(.I0(config_finished_INST_0_i_4_n_0),
.I1(config_finished_INST_0_i_3_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_1_n_0),
.I4(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0001))
config_finished_INST_0
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.O(config_finished));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_1
(.I0(DOADO[5]),
.I1(DOADO[4]),
.I2(DOADO[7]),
.I3(DOADO[6]),
.O(config_finished_INST_0_i_1_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_2
(.I0(DOADO[1]),
.I1(DOADO[0]),
.I2(DOADO[3]),
.I3(DOADO[2]),
.O(config_finished_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_3
(.I0(DOADO[13]),
.I1(DOADO[12]),
.I2(DOADO[15]),
.I3(DOADO[14]),
.O(config_finished_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_4
(.I0(DOADO[9]),
.I1(DOADO[8]),
.I2(DOADO[11]),
.I3(DOADO[10]),
.O(config_finished_INST_0_i_4_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\divider[7]_i_1
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.I4(\divider_reg[2] ),
.I5(p_0_in),
.O(\divider_reg[7] ));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "4096" *)
(* RTL_RAM_NAME = "U0/Inst_ov7670_registers/sreg" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "1023" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "15" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h53295217510C50344F4014383A04401004008C003E000C001100120412801280),
.INIT_01(256'h229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440),
.INIT_02(256'h90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
sreg_reg
(.ADDRARDADDR({1'b0,1'b0,address,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(clk),
.CLKBWRCLK(1'b0),
.DIADI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO(DOADO),
.DOBDO(NLW_sreg_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_sreg_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_sreg_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000055555554))
taken_i_1
(.I0(p_0_in),
.I1(config_finished_INST_0_i_1_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_3_n_0),
.I4(config_finished_INST_0_i_4_n_0),
.I5(\divider_reg[2] ),
.O(taken_reg));
endmodule
(* CHECK_LICENSE_TYPE = "system_ov7670_controller_0_0,ov7670_controller,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_controller,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_ov7670_controller_1_0
(clk,
resend,
config_finished,
sioc,
siod,
reset,
pwdn,
xclk);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input resend;
output config_finished;
output sioc;
inout siod;
(* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) output reset;
output pwdn;
output xclk;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire config_finished;
wire resend;
wire sioc;
wire siod;
wire xclk;
assign pwdn = \<const0> ;
assign reset = \<const1> ;
GND GND
(.G(\<const0> ));
system_ov7670_controller_1_0_ov7670_controller U0
(.clk(clk),
.config_finished(config_finished),
.resend(resend),
.sioc(sioc),
.siod(siod),
.xclk(xclk));
VCC VCC
(.P(\<const1> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_geninterp18(
input sys_clk,
input load,
input next_point,
input signed [17:0] init,
input positive,
input [16:0] q,
input [16:0] r,
input [16:0] divisor,
output signed [17:0] o
);
reg positive_r;
reg [16:0] q_r;
reg [16:0] r_r;
reg [16:0] divisor_r;
always @(posedge sys_clk) begin
if(load) begin
positive_r <= positive;
q_r <= q;
r_r <= r;
divisor_r <= divisor;
end
end
reg [17:0] err;
reg correct;
reg signed [17:0] o_r;
assign o = o_r;
always @(posedge sys_clk) begin
if(load) begin
err = 18'd0;
o_r = init;
end else if(next_point) begin
err = err + r_r;
correct = (err[16:0] > {1'b0, divisor_r[16:1]}) & ~err[17];
if(positive_r) begin
o_r = o_r + {1'b0, q_r};
if(correct)
o_r = o_r + 18'd1;
end else begin
o_r = o_r - {1'b0, q_r};
if(correct)
o_r = o_r - 18'd1;
end
if(correct)
err = err - {1'b0, divisor_r};
end
end
endmodule
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module proj1_testbench;
//Inputs: Regs
//Out: Wires
reg A;
reg B;
wire out;
reg select;
reg clk;
toplevel DUT(A, B, select, out, clk);
always
#5 clk=~clk;
initial begin
select = 1'b0;
clk = 1'b0;
A = 1'b0;
B = 1'b0;
end
always @(posedge clk)
begin
if (select) select <= 0;
else select <= 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_SYMBOL_V
`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_pwrgood_pp$PG (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXBP_TB_V
`define SKY130_FD_SC_LS__DLXBP_TB_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlxbp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ls__dlxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXBP_TB_V
|
/* Atari on an FPGA
Masters of Engineering Project
Cornell University, 2007
Daniel Beer
RIOT.v
Redesign of the MOS 6532 chip. Provides RAM, I/O and timers to the Atari.
*/
`timescale 1ns / 1ps
`include "riot.vh"
module RIOT(A, // Address bus input
Din, // Data bus input
Dout, // Data bus output
CS, // Chip select input
CS_n, // Active low chip select input
R_W_n, // Active low read/write input
RS_n, // Active low rom select input
RES_n, // Active low reset input
IRQ_n, // Active low interrupt output
CLK, // Clock input
PAin, // 8 bit port A input
PAout, // 8 bit port A output
PBin, // 8 bit port B input
PBout);// 8 bit port B output
input [6:0] A;
input [7:0] Din;
output [7:0] Dout;
input CS, CS_n, R_W_n, RS_n, RES_n, CLK;
output IRQ_n;
input [7:0] PAin, PBin;
output [7:0] PAout, PBout; // Output register
reg [7:0] Dout; // RAM allocation
reg [7:0] RAM[127:0]; // I/O registers
reg [7:0] DRA, DRB; // Data registers
reg [7:0] DDRA, DDRB; // Data direction registers
wire PA7;
reg R_PA7;
assign PA7 = (PAin[7] & ~DDRA[7]) | (DRA[7] & DDRA[7]);
assign PAout = DRA & DDRA;
assign PBout = DRB & DDRB;
// Timer registers
reg [8:0] Timer;
reg [9:0] Prescaler;
reg [1:0] Timer_Mode;
reg Timer_Int_Flag, PA7_Int_Flag, Timer_Int_Enable, PA7_Int_Enable, PA7_Int_Mode; // Timer prescaler constants
wire [9:0] PRESCALER_VALS[3:0];
assign PRESCALER_VALS[0] = 10'd0;
assign PRESCALER_VALS[1] = 10'd7;
assign PRESCALER_VALS[2] = 10'd63;
assign PRESCALER_VALS[3] = 10'd1023;
// Interrupt
assign IRQ_n = ~(Timer_Int_Flag & Timer_Int_Enable | PA7_Int_Flag & PA7_Int_Enable);
// Operation decoding
wire [6:0] op;
reg [6:0] R_op;
assign op = {RS_n, R_W_n, A[4:0]};
// Registered data in
reg [7:0] R_Din;
integer cnt;
// Software operations
always @(posedge CLK)
begin
// Reset operation
if (~RES_n) begin
DRA <= 8'b0;
DDRA <= 8'b0;
DRB <= 8'b0;
DDRB <= 8'b0;
Timer_Int_Flag <= 1'b0;
PA7_Int_Flag <= 1'b0;
PA7_Int_Enable <= 1'b0;
PA7_Int_Mode <= 1'b0;
// Fill RAM with 0s
for (cnt = 0; cnt < 128; cnt = cnt + 1)
RAM[cnt] <= 8'b0;
R_PA7 <= 1'b0;
R_op <= `NOP;
R_Din <= 8'b0;
end
// If the chip is enabled, execute an operation
else if (CS & ~CS_n) begin
// Register inputs for use later
R_PA7 <= PA7;
R_op <= op;
R_Din <= Din;
// Update the timer interrupt flag
casex (op)
`WRITE_TIMER: Timer_Int_Flag <= 1'b0;
`READ_TIMER: Timer_Int_Flag <= 1'b0;
default: if (Timer == 9'b111111111) Timer_Int_Flag <= 1'b1;
endcase
// Update the port A interrupt flag
casex (op)
`READ_INT_FLAG: PA7_Int_Flag <= 1'b0;
default: PA7_Int_Flag <= PA7_Int_Flag | (PA7 != R_PA7 & PA7 == PA7_Int_Mode);
endcase
// Process the current operation
casex(op) // RAM access
`READ_RAM: Dout <= RAM[A];
`WRITE_RAM: RAM[A] <= Din;
// Port A data access
`READ_DRA : Dout <= (PAin & ~DDRA) | (DRA & DDRA);
`WRITE_DRA: DRA <= Din;
// Port A direction register access
`READ_DDRA: Dout <= DDRA;
`WRITE_DDRA: DDRA <= Din;
// Port B data access
`READ_DRB: Dout <= (PBin & ~DDRB) | (DRB & DDRB);
`WRITE_DRB: DRB <= Din;
// Port B direction register access
`READ_DDRB: Dout <= DDRB;
`WRITE_DDRB: DDRB <= Din;
// Timer access
`READ_TIMER: Dout <= Timer[7:0];
// Status register access
`READ_INT_FLAG: Dout <= {Timer_Int_Flag, PA7_Int_Flag, 6'b0};
// Enable the port A interrupt
`WRITE_EDGE_DETECT: begin
PA7_Int_Mode <= A[0]; PA7_Int_Enable <= A[1];
end
endcase
end
// Even if the chip is not enabled, update background functions
else begin
// Update the timer interrupt
if (Timer == 9'b111111111)
Timer_Int_Flag <= 1'b1;
// Update the port A interrupt
R_PA7 <= PA7;
PA7_Int_Flag <= PA7_Int_Flag | (PA7 != R_PA7 & PA7 == PA7_Int_Mode);
// Set the operation to a NOP
R_op <=`NOP;
end
end
// Update the timer at the negative edge of the clock
always @(negedge CLK)begin
// Reset operation
if (~RES_n) begin
Timer <= 9'b0;
Timer_Mode <= 2'b0;
Prescaler <= 10'b0;
Timer_Int_Enable <= 1'b0;
end
// Otherwise, process timer operations
else
casex
(R_op)
// Write value to the timer and update the prescaler based on the address
`WRITE_TIMER:begin
Timer <= {1'b0, R_Din};
Timer_Mode <= R_op[1:0];
Prescaler <= PRESCALER_VALS[R_op[1:0]];
Timer_Int_Enable <= R_op[3];
end
// Otherwise decrement the prescaler and if necessary the timer.
// The prescaler holds a variable number of counts that must be
// run before the timer is decremented
default:if (Timer != 9'b100000000) begin
if (Prescaler != 10'b0)
Prescaler <= Prescaler - 10'b1;
else begin
if (Timer == 9'b0)
begin
Prescaler <= 10'b0;
Timer_Mode <= 2'b0;
end
else
Prescaler <= PRESCALER_VALS[Timer_Mode];
Timer <= Timer - 9'b1;
end
end
endcase
end
endmodule
|
/*
* Quarter-wave sine table.
* Features:
* - Parameterized for arbitrary input & output widths
* - 1/2 LSB angle offset for glitch-free quarter wave sine table
* - Unsigned quarter wave Lookup table
* - Sine table size is 2^(ANGLE_WIDTH-2) x OUT_WIDTH-1
* - 2 clock delay between input and output
*
* For a size example, an 18-bit output with a 12-bit angle requires a 1024x17
* sine table, which readily fits into a single RAM16 block in a Spartan 6 FPGA.
*/
///////////////////////////////////////////////////////////////////////////
// MODULE DECLARATION
///////////////////////////////////////////////////////////////////////////
module sineTable #(
parameter ANGLE_WIDTH = 12,
parameter OUT_WIDTH = 18
) (
input wire clk, ///< System Clock
input wire [ANGLE_WIDTH-1:0] angle, ///< Angle to take sine of
output reg signed [OUT_WIDTH-1:0] sine ///< Sine of angle
);
///////////////////////////////////////////////////////////////////////////
// PARAMETER AND SIGNAL DECLARATIONS
///////////////////////////////////////////////////////////////////////////
localparam TABLE_LEN = 2**(ANGLE_WIDTH-2);
wire [ANGLE_WIDTH-3:0] quarterAngle;
reg [OUT_WIDTH-2:0] sineTable [TABLE_LEN-1:0];
reg signBit;
reg [OUT_WIDTH-2:0] halfSine;
integer i;
///////////////////////////////////////////////////////////////////////////
// MAIN CODE
///////////////////////////////////////////////////////////////////////////
assign quarterAngle = (angle[ANGLE_WIDTH-2]) ? ~angle[ANGLE_WIDTH-3:0] : angle[ANGLE_WIDTH-3:0];
initial begin
signBit = 1'b0;
halfSine = 'd0;
sine = 'd0;
for(i=0; i<TABLE_LEN; i=i+1) begin
sineTable[i] = $rtoi($floor($sin((i+0.5)*3.14159/(TABLE_LEN*2))*(2**(OUT_WIDTH-1)-1)+0.5));
end
end
always @(posedge clk) begin
signBit <= angle[ANGLE_WIDTH-1];
halfSine <= sineTable[quarterAngle];
sine <= signBit ? -$signed({1'b0,halfSine}) : $signed({1'b0, halfSine});
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:41:14 04/19/2014
// Design Name:
// Module Name: Image_viewer_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Image_viewer_top(ClkPort,
Hsync, Vsync, vgaRed, vgaGreen, vgaBlue,
MemOE, MemWR, MemClk, RamCS, RamUB, RamLB, RamAdv, RamCRE,
MemAdr, data,
An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp, Led,
btnC, btnR, btnL, btnU, btnD
);
// ===========================================================================
// Port Declarations
// ===========================================================================
input ClkPort;
output MemOE, MemWR, MemClk, RamCS, RamUB, RamLB, RamAdv, RamCRE;
output [26:1] MemAdr;
inout [15:0] data;
//Button
input btnC, btnR, btnL, btnU, btnD;
//Light/Display
output An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp;
output Vsync, Hsync;
output [2:0] vgaRed;
output [2:0] vgaGreen;
output [2:1] vgaBlue;
output [1:0] Led;
reg [2:0] _vgaRed;
reg [2:0] _vgaGreen;
reg [1:0] _vgaBlue;
wire inDisplayArea;
wire [9:0] CounterX;
wire [9:0] CounterY;
reg [5:0] bitCounter;
assign vgaRed = _vgaRed;
assign vgaGreen = _vgaGreen;
assign vgaBlue = _vgaBlue;
assign Led = readImage;
// ===========================================================================
// Parameters, Regsiters, and Wires
// ===========================================================================
//Global Stuff
wire ClkPort, sys_clk, Reset;
reg [26:0] DIV_CLK;
assign sys_clk = ClkPort;
assign MemClk = DIV_CLK[0];
//Memory Stuff
reg [22:0] address;
reg [15:0] dataRegister[0:127];
reg [22:0] imageRegister[0:3];
always@(posedge sys_clk)
begin
imageRegister[2'b00][22:0] <= 23'b00000000000000000000000;
imageRegister[2'b01][22:0] <= 23'b00000000000000010000000;
imageRegister[2'b10][22:0] <= 23'b00000000000000100000000;
imageRegister[2'b11][22:0] <= 23'b00000000000000110000000;
end
wire [7:0] uByte;
wire [7:0] lByte;
reg [1:0] readImage;
reg [6:0] readAddress;
reg [6:0] writePointer;
reg [6:0] readRow;
assign uByte = data[15:8];
assign lByte = data[7:0];
//Button Stuff
wire BtnR_Pulse, BtnL_Pulse, BtnU_Pulse, BtnD_Pulse;
assign Reset = btnC;
//-------------------------------------------------------------------//
always @ (posedge sys_clk, posedge Reset)
begin : CLOCK_DIVIDER
if (Reset)
DIV_CLK <= 0;
else
DIV_CLK <= DIV_CLK + 1;
end
//--------------------Debounce Controllers--------------------//
ee201_debouncer #(.N_dc(20)) ee201_debouncer_left
(.CLK(MemClk), .RESET(Reset), .PB(btnL), .DPB( ),
.SCEN(BtnL_Pulse), .MCEN( ), .CCEN( ));
ee201_debouncer #(.N_dc(20)) ee201_debouncer_right
(.CLK(MemClk), .RESET(Reset), .PB(btnR), .DPB( ),
.SCEN(BtnR_Pulse), .MCEN( ), .CCEN( ));
ee201_debouncer #(.N_dc(20)) ee201_debouncer_up
(.CLK(MemClk), .RESET(Reset), .PB(btnU), .DPB( ),
.SCEN(BtnU_Pulse), .MCEN( ), .CCEN( ));
ee201_debouncer #(.N_dc(20)) ee201_debouncer_down
(.CLK(MemClk), .RESET(Reset), .PB(btnD), .DPB( ),
.SCEN(BtnD_Pulse), .MCEN( ), .CCEN( ));
//--------------------Display Controller--------------------//
DisplayCtrl display (.Clk(DIV_CLK), .reset(Reset), .memoryData(dataRegister[readRow][15:0]),
.An0(An0), .An1(An1), .An2(An2), .An3(An3),
.Ca(Ca), .Cb(Cb), .Cc(Cc), .Cd(Cd), .Ce(Ce), .Cf(Cf), .Cg(Cg), .Dp(Dp)
);
//--------------------Memory Controller--------------------//
MemoryCtrl memory(.Clk(MemClk), .Reset(Reset), .MemAdr(MemAdr), .MemOE(MemOE), .MemWR(MemWR),
.RamCS(RamCS), .RamUB(RamUB), .RamLB(RamLB), .RamAdv(RamAdv), .RamCRE(RamCRE), .writeData(writeData),
.AddressIn(address), .BtnU_Pulse(BtnU_Pulse), .BtnD_Pulse(BtnD_Pulse)
);
//--------------------VGA Controller--------------------//
VGACtrl vga(.clk(DIV_CLK[1]), .reset(Reset), .vga_h_sync(Hsync),
.vga_v_sync(Vsync), .inDisplayArea(inDisplayArea),
.CounterX(CounterX), .CounterY(CounterY)
);
reg toggleByte;
always @(posedge DIV_CLK[1], posedge Reset)
begin
if(Reset)
begin
bitCounter <= 0;
toggleByte <= 0;
readAddress <= 0;
end
else if(CounterY > 192 && CounterY < 288)
begin
if(CounterX == 0)
begin
bitCounter <= 0;
toggleByte <= 1'b0;
end
else if(CounterX > 284 && bitCounter < 35)
begin
if(toggleByte == 1'b0)
begin
{_vgaRed, _vgaGreen, _vgaBlue} <= dataRegister[readAddress][7:0];
toggleByte <= 1'b1;
end
else
begin
{_vgaRed, _vgaGreen, _vgaBlue} <= dataRegister[readAddress][15:8];
toggleByte <= 1'b0;
bitCounter <= bitCounter + 1;
readAddress <= readAddress + 1;
end
end
else
begin
{_vgaRed, _vgaGreen, _vgaBlue} <= 0;
end
end
else if (CounterY == 288)
readAddress <= 0;
end
always@(posedge MemClk, posedge Reset)
begin
if(Reset)
readImage <= 0;
else if(BtnU_Pulse)
readImage <= readImage + 1;
else if(BtnD_Pulse)
readImage <= readImage - 1;
else
address <= imageRegister[readImage][22:0];
end
//--------------------Process Data--------------------//
always@(posedge MemClk, posedge Reset)
begin
if(Reset)
begin
writePointer <= 0;
end
else
if(writeData == 1'b1)
begin
dataRegister[writePointer][15:0] <= {lByte, uByte};
writePointer <= writePointer + 1;
end
else
writePointer <= 0;
end
//--------------------SSD Display Data--------------------//
always@(posedge MemClk, posedge Reset)
begin
if(Reset)
readRow <= 0;
else if(BtnR_Pulse)
readRow <= readRow + 1;
else if(BtnL_Pulse)
readRow <= readRow - 1;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 09 23:36:35 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xlconcat_0_0_stub.v
// Design : design_1_xlconcat_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "xlconcat,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(In0, In1, dout)
/* synthesis syn_black_box black_box_pad_pin="In0[0:0],In1[0:0],dout[1:0]" */;
input [0:0]In0;
input [0:0]In1;
output [1:0]dout;
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
always @ (posedge clk or negedge resetn) begin
// not in reset
if (resetn)
begin
case (state)
// Wake up processor and all B.C.
TASK0:
begin
c0_req_int <= 1;
state <= TX_WAIT;
end
// Querry nodes
TASK1:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_QUERRY, 28'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Enumerate with 4'h2
TASK2:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
// address should starts with 4'h2
c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h2, 24'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Enumerate with 4'h3
TASK3:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h3, 24'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Enumerate with 4'h4
TASK4:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h4, 24'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// Enumerate with 4'h5
TASK5:
begin
c0_tx_addr <= {28'h000000, `CHANNEL_ENUM};
c0_tx_data <= {`CMD_CHANNEL_ENUM_ENUMERATE, 4'h5, 24'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// n0 -> 4'h2
// n1 -> 4'h3
// n2 -> 4'h4
// n3 -> 4'h5
// n1 -> n2 byte streamming using short address
TASK6:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h4, 4'h1}; // 4'h1 is functional ID
n1_tx_data <= rand_dat;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
if (word_counter)
begin
word_counter <= word_counter - 1;
n1_tx_pend <= 1;
end
else
begin
n1_tx_pend <= 0;
state <= TX_WAIT;
end
end
end
// n1 -> n0 byte streamming using short address
TASK7:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h2, 4'h3}; // 4'h3 is functional ID
n1_tx_data <= rand_dat;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
if (word_counter)
begin
word_counter <= word_counter - 1;
n1_tx_pend <= 1;
end
else
begin
n1_tx_pend <= 0;
state <= TX_WAIT;
end
end
end
// n1 -> n2 byte streamming using long address
TASK8:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {4'hf, 4'h0, 20'hbbbb2, 4'h1}; // 4'h1 is functional ID
n1_tx_data <= rand_dat;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
if (word_counter)
begin
word_counter <= word_counter - 1;
n1_tx_pend <= 1;
end
else
begin
n1_tx_pend <= 0;
state <= TX_WAIT;
end
end
end
// n1 -> n0 byte streamming using short address
TASK9:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {4'hf, 4'h0, 20'hbbbb0, 4'h3}; // 4'h3 is functional ID
n1_tx_data <= rand_dat;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
if (word_counter)
begin
word_counter <= word_counter - 1;
n1_tx_pend <= 1;
end
else
begin
n1_tx_pend <= 0;
state <= TX_WAIT;
end
end
end
// Unknown address
TASK10:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {4'hf, 4'h0, 20'hbbbb5, 4'h2};
n1_tx_data <= rand_dat;
n1_tx_pend <= 0;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
state <= TX_WAIT;
end
end
// n1 -> n2 TX buffer underflow
TASK11:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h4, 4'h3};
n1_tx_data <= rand_dat;
n1_tx_pend <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
if (word_counter)
begin
n1_tx_req <= 1;
word_counter <= word_counter - 1;
end
else
begin
n1_tx_req <= 0;
state <= TX_WAIT;
end
end
end
// n1 -> n0 TX buffer underflow
TASK12:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h2, 4'h8};
n1_tx_data <= rand_dat;
n1_tx_pend <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
if (word_counter)
begin
n1_tx_req <= 1;
word_counter <= word_counter - 1;
end
else
begin
n1_tx_req <= 0;
state <= TX_WAIT;
end
end
end
// n1 -> n2 RX buffer overflow, middle of transmission
TASK13:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h4, 4'h3};
n1_tx_data <= rand_dat;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
if (word_counter)
begin
word_counter <= word_counter - 1;
n1_tx_pend <= 1;
end
else
begin
n1_tx_pend <= 0;
state <= TX_WAIT;
end
end
else if (n1_tx_fail)
begin
state <= TX_WAIT;
n1_tx_req <= 0;
end
end
// n1 -> n0 RX buffer overflow, middle of transmission
TASK14:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h2, 4'h9};
n1_tx_data <= rand_dat;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
if (word_counter)
begin
word_counter <= word_counter - 1;
n1_tx_pend <= 1;
end
else
begin
n1_tx_pend <= 0;
state <= TX_WAIT;
end
end
else if (n1_tx_fail)
begin
state <= TX_WAIT;
n1_tx_req <= 0;
end
end
// n1 -> n2 RX buffer overflow, last word
TASK15:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h4, 4'h3};
n1_tx_data <= rand_dat;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
if (word_counter)
begin
word_counter <= word_counter - 1;
n1_tx_pend <= 1;
end
else
begin
n1_tx_pend <= 0;
state <= TX_WAIT;
end
end
end
// n1 -> n0 RX buffer overflow, last word
TASK16:
begin
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h2, 4'h9};
n1_tx_data <= rand_dat;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
if (word_counter)
begin
word_counter <= word_counter - 1;
n1_tx_pend <= 1;
end
else
begin
n1_tx_pend <= 0;
state <= TX_WAIT;
end
end
end
// Arbitration test, both n0, n1 transmit to n3.
// n0 transmits first
TASK17:
begin
if ((~n0_tx_ack) & (~n0_tx_req))
begin
n0_tx_addr <= {24'h0, 4'h5, 4'h8};
n0_tx_data <= rand_dat;
n0_tx_pend <= 0;
n0_tx_req <= 1;
$fdisplay(handle, "N0 Data in =\t32'h%h", rand_dat);
end
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h5, 4'h3};
n1_tx_data <= rand_dat2;
n1_tx_pend <= 0;
n1_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat2);
end
state <= TX_WAIT;
end
// Priority test1, both n0, n1 transmit to n3
// n1 sets priority, n1 transmits first
TASK18:
begin
if ((~n0_tx_ack) & (~n0_tx_req))
begin
n0_tx_addr <= {24'h0, 4'h5, 4'h8};
n0_tx_data <= rand_dat;
n0_tx_pend <= 0;
n0_tx_req <= 1;
$fdisplay(handle, "N0 Data in =\t32'h%h", rand_dat);
end
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h5, 4'h3};
n1_tx_data <= rand_dat2;
n1_tx_pend <= 0;
n1_tx_req <= 1;
n1_priority <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat2);
end
state <= TX_WAIT;
end
// Priority test2, both n0, n1 transmit to n3
// both sets priority. n0 transmits first
TASK19:
begin
if ((~n0_tx_ack) & (~n0_tx_req))
begin
n0_tx_addr <= {24'h0, 4'h5, 4'h8};
n0_tx_data <= rand_dat;
n0_tx_pend <= 0;
n0_tx_req <= 1;
n0_priority <= 1;
$fdisplay(handle, "N0 Data in =\t32'h%h", rand_dat);
end
if ((~n1_tx_ack) & (~n1_tx_req))
begin
n1_tx_addr <= {24'h0, 4'h5, 4'h3};
n1_tx_data <= rand_dat2;
n1_tx_pend <= 0;
n1_tx_req <= 1;
n1_priority <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat2);
end
state <= TX_WAIT;
end
// Priority test3, only n0 transmits with priority set
TASK20:
begin
if ((~n0_tx_ack) & (~n0_tx_req))
begin
n0_tx_addr <= {24'h0, 4'h5, 4'h3};
n0_tx_data <= rand_dat;
n0_tx_pend <= 0;
n0_tx_req <= 1;
n0_priority <= 1;
$fdisplay(handle, "N0 Data in =\t32'h%h", rand_dat);
state <= TX_WAIT;
end
end
// Sleep all
TASK21:
begin
c0_tx_addr <= {28'hf00000, `CHANNEL_POWER};
c0_tx_data <= {`CMD_CHANNEL_POWER_ALL_SLEEP, 28'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// N2 asserts interrupt
TASK22:
begin
n2_req_int <= 1;
state <= TX_WAIT;
end
// n2 -> c0 using short address
TASK23:
begin
n2_tx_addr <= {24'h0, 4'h1, 4'h3}; // 4'h3 is functional ID
n2_tx_data <= rand_dat;
n2_tx_req <= 1;
n2_tx_pend <= 0;
n2_priority <= 0;
$fdisplay(handle, "N2 Data in =\t32'h%h", rand_dat);
state <= TX_WAIT;
end
// All layers wake
TASK24:
begin
c0_tx_addr <= {28'hf00000, `CHANNEL_POWER};
c0_tx_data <= {`CMD_CHANNEL_POWER_ALL_WAKE, 28'h0};
c0_tx_req <= 1;
c0_tx_pend <= 0;
c0_priority <= 0;
state <= TX_WAIT;
end
// stuck on TX (too long messages)
TASK25:
begin
if ((~n2_tx_ack) & (~n2_tx_req))
begin
n2_tx_addr <= {24'h0, 4'h2, 4'h9};
n2_tx_data <= rand_dat;
n2_tx_req <= 1;
$fdisplay(handle, "N1 Data in =\t32'h%h", rand_dat);
n2_tx_pend <= 1;
end
else if (n2_tx_fail)
begin
state <= TX_WAIT;
n2_tx_req <= 0;
n2_tx_pend <= 0;
end
end
endcase
end
end
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic [1:0] [3:0] [3:0] array_simp; // big endian array
logic [3:0] array_oned;
initial begin
array_oned = '{2:1'b1, 0:1'b1, default:1'b0};
if (array_oned != 4'b0101) $stop;
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
if (array_simp[0] !== 16'h3210) $stop;
// verilator lint_off WIDTH
array_simp[0] = '{ 3 ,2 ,1, 0 };
// verilator lint_on WIDTH
if (array_simp[0] !== 16'h3210) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//if (array_simp[0] !== 16'h3210) $stop;
//array_simp[0] = '{ 1:4'd3, default:13};
//if (array_simp[0] !== 16'hDD3D) $stop;
array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
if (array_simp !== 32'h3210_1234) $stop;
// IEEE says '{} allowed only on assignments, not !=, ==.
// Doesn't seem to work for unpacked arrays in other simulators
array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
if (array_simp !== 32'h3210_3210) $stop;
array_simp = '{2{ '{4{ 4'd3 }} }};
if (array_simp !== 32'h3333_3333) $stop;
// Not legal in other simulators - replication doesn't match
// However IEEE suggests this is legal.
//array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
$write("*-* All Finished *-*\n");
$finish;
end
//====================
// parameters for array sizes
localparam WA = 4; // address dimension size
localparam WB = 4; // bit dimension size
localparam NO = 11; // number of access events
// 2D packed arrays
logic [WA-1:0] [WB-1:0] array_bg; // big endian array
/* verilator lint_off LITENDIAN */
logic [0:WA-1] [0:WB-1] array_lt; // little endian array
/* verilator lint_on LITENDIAN */
integer cnt = 0;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]== 0) array_bg <= '0;
else if (cnt[30:2]== 1) array_bg <= '0;
else if (cnt[30:2]== 2) array_bg <= '0;
else if (cnt[30:2]== 3) array_bg <= '0;
else if (cnt[30:2]== 4) array_bg <= '0;
else if (cnt[30:2]== 5) array_bg <= '0;
else if (cnt[30:2]== 6) array_bg <= '0;
else if (cnt[30:2]== 7) array_bg <= '0;
else if (cnt[30:2]== 8) array_bg <= '0;
else if (cnt[30:2]== 9) array_bg <= '0;
else if (cnt[30:2]==10) array_bg <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]== 0) begin end
else if (cnt[30:2]== 1) array_bg <= '{ 3 ,2 ,1, 0 };
else if (cnt[30:2]== 2) array_bg <= '{default:13};
else if (cnt[30:2]== 3) array_bg <= '{0:4, 1:5, 2:6, 3:7};
else if (cnt[30:2]== 4) array_bg <= '{2:15, default:13};
else if (cnt[30:2]== 5) array_bg <= '{WA { {WB/2 {2'b10}} }};
else if (cnt[30:2]== 6) array_bg <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]== 0) begin if (array_bg !== 16'b0000000000000000) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 1) begin if (array_bg !== 16'b0011001000010000) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 2) begin if (array_bg !== 16'b1101110111011101) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 3) begin if (array_bg !== 16'b0111011001010100) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 4) begin if (array_bg !== 16'b1101111111011101) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 5) begin if (array_bg !== 16'b1010101010101010) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]== 6) begin if (array_bg !== 16'b1001101010111100) begin $display("%b", array_bg); $stop(); end end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaults (all bits 1'b0)
if (cnt[30:2]== 0) array_lt <= '0;
else if (cnt[30:2]== 1) array_lt <= '0;
else if (cnt[30:2]== 2) array_lt <= '0;
else if (cnt[30:2]== 3) array_lt <= '0;
else if (cnt[30:2]== 4) array_lt <= '0;
else if (cnt[30:2]== 5) array_lt <= '0;
else if (cnt[30:2]== 6) array_lt <= '0;
else if (cnt[30:2]== 7) array_lt <= '0;
else if (cnt[30:2]== 8) array_lt <= '0;
else if (cnt[30:2]== 9) array_lt <= '0;
else if (cnt[30:2]==10) array_lt <= '0;
end else if (cnt[1:0]==2'd1) begin
// write data into whole or part of the array using literals
if (cnt[30:2]== 0) begin end
else if (cnt[30:2]== 1) array_lt <= '{ 3 ,2 ,1, 0 };
else if (cnt[30:2]== 2) array_lt <= '{default:13};
else if (cnt[30:2]== 3) array_lt <= '{3:4, 2:5, 1:6, 0:7};
else if (cnt[30:2]== 4) array_lt <= '{1:15, default:13};
else if (cnt[30:2]== 5) array_lt <= '{WA { {WB/2 {2'b10}} }};
else if (cnt[30:2]==10) array_lt <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3};
end else if (cnt[1:0]==2'd2) begin
// chack array agains expected value
if (cnt[30:2]== 0) begin if (array_lt !== 16'b0000000000000000) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 1) begin if (array_lt !== 16'b0011001000010000) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 2) begin if (array_lt !== 16'b1101110111011101) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 3) begin if (array_lt !== 16'b0111011001010100) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 4) begin if (array_lt !== 16'b1101111111011101) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]== 5) begin if (array_lt !== 16'b1010101010101010) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==10) begin if (array_lt !== 16'b1001101010111100) begin $display("%b", array_lt); $stop(); end end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:01:37 04/27/2014
// Design Name: Image_viewer_top
// Module Name: /home/student/Dropbox/EE 201 Final Project/SynchronousRead/top_tb.v
// Project Name: SynchronousRead
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Image_viewer_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_tb;
// Inputs
reg ClkPort;
reg btnC;
reg btnR;
reg btnL;
// Outputs
wire Hsync;
wire Vsync;
wire [2:0] vgaRed;
wire [2:0] vgaGreen;
wire [2:1] vgaBlue;
wire MemOE;
wire MemWR;
wire MemClk;
wire RamCS;
wire RamUB;
wire RamLB;
wire RamAdv;
wire RamCRE;
wire [26:1] MemAdr;
wire An0;
wire An1;
wire An2;
wire An3;
wire Ca;
wire Cb;
wire Cc;
wire Cd;
wire Ce;
wire Cf;
wire Cg;
wire Dp;
wire [1:0] Led;
// Bidirs
wire [15:0] data;
// Instantiate the Unit Under Test (UUT)
Image_viewer_top uut (
.ClkPort(ClkPort),
.Hsync(Hsync),
.Vsync(Vsync),
.vgaRed(vgaRed),
.vgaGreen(vgaGreen),
.vgaBlue(vgaBlue),
.MemOE(MemOE),
.MemWR(MemWR),
.MemClk(MemClk),
.RamCS(RamCS),
.RamUB(RamUB),
.RamLB(RamLB),
.RamAdv(RamAdv),
.RamCRE(RamCRE),
.MemAdr(MemAdr),
.data(data),
.An0(An0),
.An1(An1),
.An2(An2),
.An3(An3),
.Ca(Ca),
.Cb(Cb),
.Cc(Cc),
.Cd(Cd),
.Ce(Ce),
.Cf(Cf),
.Cg(Cg),
.Dp(Dp),
.Led(Led),
.btnC(btnC),
.btnR(btnR),
.btnL(btnL)
);
initial
begin
ClkPort = 0;
forever
#5 ClkPort = ~ClkPort;
end
initial begin
// Initialize Inputs
btnC = 1;
btnR = 0;
btnL = 0;
// Wait 100 ns for global reset to finish
#100;
btnC = 0;
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_SYMBOL_V
`define SKY130_FD_SC_LP__AND4_SYMBOL_V
/**
* and4: 4-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A222OI_BEHAVIORAL_V
|
`timescale 1ns / 1ps
`timescale 1ns / 1ps
module ymplayer(
input clk50,
input rst,
// sound
output reg speaker_left,
output reg speaker_right,
// switches
input [3:0] sw_sel, //
input send_data, // 1=Send music over UART, 0=stop
// UART wires
input uart_rx,
output uart_tx,
output [7:0] led
);
wire locked, rst_clk, rst_clk50;
// Send data
reg [9:0] send_data_shr;
wire send_data_s = &send_data_shr;
always @(posedge clk50)
send_data_shr <= { send_data_shr[8:0], send_data };
wire E, Q, clk_dac;
clocks u_clocks(
.rst ( rst ),
.clk50 ( clk50 ),
.locked ( locked ),
.divide_more( send_data_s ),
//.clk_cpu( clk ),
.clk_dac( clk_dac ),
.clk_dac_sel( sw_sel[1] ),
.E ( E ),
.Q ( Q )
);
wire cpu_rw;
wire AVMA;
//wire BS, BA, BUSY, LIC;
wire clk_per = E; // mc6809i
wire cpu_rst_req;
rst_sync u_rst1(
.rst_in ( rst|(~locked)|cpu_rst_req ),
.clk ( Q ),
.rst_out( rst_clk )
);
/*
rst_sync u_rst2(
.rst_in ( rst_clk ),
.clk ( clk_dac ),
.rst_out( rst_fast )
);
*/
rst_sync u_rst50(
.rst_in ( rst|(~locked) ),
.clk ( clk50 ),
.rst_out( rst_clk50 )
);
wire [7:0] cpu_data_in, cpu_data_out;
wire [15:0] cpu_addr;
wire [7:0]jt_data_out;
wire jt_sample;
// JT51
`ifndef NOJT
wire signed [15:0] direct_l, direct_r;
jt51 u_jt51(
.clk ( clk_per ),
.rst ( rst_clk ),
.cs_n ( jt_cs_n ), // chip select
.wr_n ( cpu_rw ), // write
.a0 ( cpu_addr[0] ),
.d_in ( cpu_data_out ), // data in
.d_out ( jt_data_out ), // data out
.irq_n ( jt_irq_n ),
// uso salidas exactas para el DAC
.sample ( jt_sample ),
.xleft ( direct_l ),
.xright ( direct_r )
);
wire [15:0] inter_l, inter_r;
jt51_interpol i_jt51_interpol (
.clk (clk50 ),
.rst (rst ),
.sample_in (jt_sample ),
.left_in (direct_l ),
.right_in (direct_r ),
.left_other (16'd0 ),
.right_other(16'd0 ),
.out_l (inter_l ),
.out_r (inter_r ),
.sample_out (fir_sample )
);
reg [15:0] dacin_l, dacin_r;
always @(posedge clk_dac)
if( sw_sel[2] ) begin
dacin_l <= inter_l;
dacin_r <= inter_r;
end
else begin
dacin_l <= direct_l;
dacin_r <= direct_r;
end
wire dac2_l, dac2_r;
wire dacmist_l, dacmist_r;
speaker u_speaker(
.clk100 ( clk_dac ),
.left_in ( dacin_l ),
.right_in ( dacin_r ),
.left_out ( dacmist_l ),
.right_out ( dacmist_r )
);
always @(posedge clk_per)
if( sw_sel[3] ) begin
speaker_left <= dac2_l;
speaker_right<= dac2_r;
end
else begin
speaker_left<= dacmist_l;
speaker_right<=dacmist_r;
end
jt51_dac2 i_jt51_dac2_l (.clk(clk_dac), .rst(rst), .din(dacin_l), .dout(dac2_l));
jt51_dac2 i_jt51_dac2_r (.clk(clk_dac), .rst(rst), .din(dacin_r), .dout(dac2_r));
`else
wire jt_irq_n = 1'b1;
wire [15:0] dacin_l = 16'd0, dacin_r=16'd0;
`endif
parameter RAM_MSB = 10; // 10 for Contra;
wire [7:0] ROM_data_out, RAM_data;
wire fsm_wr;
wire [ 7:0] fsm_data;
wire [14:0] fsm_addr;
wire rom_prog;
//synthesis attribute box_type ram32 "black_box"
ram32 ROM( // 32kb
.clka ( clk_per ),
.dina ( fsm_data ),
.wea ( fsm_wr ),
.douta ( ROM_data_out ),
.addra ( rom_prog ? fsm_addr : cpu_addr[14:0])
);
//synthesis attribute box_type ram2 "black_box"
ram2 RAM( // 2kb
.clka ( clk_per ),
.dina ( cpu_data_out ),
.douta ( RAM_data ),
.addra ( cpu_addr[RAM_MSB:0] ),
.ena ( RAM_cs ),
.wea ( ~cpu_rw )
);
wire [7:0] sound_latch;
wire clear_irq;
assign led = rom_prog ? fsm_addr[14:7] : sound_latch;
fsm_control fsm_ctrl(
.clk ( clk50 ),
.clk_cpu ( E ),
.rst ( rst_clk50 ),
// Sound
.sound_latch(sound_latch),
.jt_left ( dacin_l ),
.jt_right ( dacin_r ),
.jt_sample ( jt_sample ),
.irq ( irq ),
.clear_irq ( clear_irq ),
// Programming
.cpu_rst ( cpu_rst_req),
.rom_prog ( rom_prog ),
.rom_wr ( fsm_wr ),
.rom_addr ( fsm_addr ),
.rom_data ( fsm_data ),
// UART wires
.uart_rx ( uart_rx ),
.uart_tx ( uart_tx )
);
reg cpu_vma;
always @(negedge E)
cpu_vma <= AVMA;
bus_manager #(RAM_MSB) bus_mng(
// .rst50 ( rst_clk50 ),
// .clk50 ( clk50 ),
// .clk_per ( clk_per ),
.game_sel ( sw_sel[0] ),
.ROM_data_out ( ROM_data_out ),
.RAM_data ( RAM_data ),
.sound_latch ( sound_latch ),
.clear_irq ( clear_irq ),
// .cpu_data_out ( cpu_data_out ),
.jt_data_out ( jt_data_out ),
//
.cpu_data_in ( cpu_data_in ),
.cpu_rw ( cpu_rw ),
.addr ( cpu_addr ),
.cpu_vma ( cpu_vma ),
.RAM_cs ( RAM_cs ),
.opm_cs_n ( jt_cs_n )
);
`ifndef NOCPU
wire cpu_firq_n = sw_sel[0] ? jt_irq_n : 1'b1;
mc6809i cpu_good(
.D ( cpu_data_in ),
.DOut ( cpu_data_out ),
.ADDR ( cpu_addr ),
.RnW ( cpu_rw ),
// .BS ( BS ),
// .BA ( BA ),
.nIRQ ( ~irq ),
.nFIRQ ( cpu_firq_n ),
.nNMI ( 1'b1 ),
.AVMA ( AVMA ),
// .BUSY ( BUSY ),
// .LIC ( LIC ),
.nRESET ( ~rst_clk ),
.nHALT ( 1'b1 ),
.nDMABREQ( 1'b1 ),
.E ( E ),
.Q ( Q )
);
`endif
endmodule
|
`include "senior_defines.vh"
module mac_scale
(input wire signed [39:0] to_scaling,
input wire [2:0] c_scalefactor,
output wire scale_overflow,
output reg [39:0] from_scaling);
reg scale_pos_overflow;
reg scale_neg_overflow;
assign scale_overflow = scale_neg_overflow | scale_pos_overflow;
// Mux for scaling
always@(*) begin
scale_pos_overflow = 0;
scale_neg_overflow = 0;
case (c_scalefactor)
3'b000: begin
from_scaling=to_scaling; // *1
end
3'b001: begin
from_scaling=to_scaling << 1; // *2
scale_pos_overflow = ~to_scaling[39] & to_scaling[38];
scale_neg_overflow = to_scaling[39] & ~to_scaling[38];
end
3'b010: begin
from_scaling=to_scaling << 2; // *4
scale_pos_overflow = ~to_scaling[39] & (|to_scaling[38:37]);
scale_neg_overflow = to_scaling[39] & ~(&to_scaling[38:37]);
end
3'b011: begin
from_scaling={to_scaling[39],to_scaling[39:1]}; // *0.5
end
3'b100: begin
from_scaling={{2{to_scaling[39]}},to_scaling[39:2]}; // *0.25
end
3'b101: begin
from_scaling={{3{to_scaling[39]}},to_scaling[39:3]}; // *0.125
end
3'b110: begin
from_scaling={{4{to_scaling[39]}},to_scaling[39:4]}; // *0.0625
end
3'b111: begin
from_scaling=to_scaling << 16; // *2^16
scale_pos_overflow = ~to_scaling[39] & (|to_scaling[38:23]);
scale_neg_overflow = to_scaling[39] & ~(&to_scaling[38:23]);
end
endcase
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file FifoCore32w8r.v when simulating
// the core, FifoCore32w8r. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module FifoCore32w8r(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
prog_full,
prog_empty
);
input rst;
input wr_clk;
input rd_clk;
input [31 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
output prog_full;
output prog_empty;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(8),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("spartan6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(511),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(512),
.C_PROG_EMPTY_TYPE(1),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(384),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(383),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(11),
.C_RD_DEPTH(2048),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(11),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.PROG_FULL(prog_full),
.PROG_EMPTY(prog_empty),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9234_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [63:0] adc_data;
input adc_or;
// channel interface
output [63:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations
axi_ad9234_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
assign adc_dfmt_data = adc_data;
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// THIS FILE IS AUTOGENERATED BY wb_intercon_gen
// ANY MANUAL CHANGES WILL BE LOST
module wb_intercon
(input wb_clk_i,
input wb_rst_i,
input [31:0] wb_iwmb_adr_i,
input [31:0] wb_iwmb_dat_i,
input [3:0] wb_iwmb_sel_i,
input wb_iwmb_we_i,
input wb_iwmb_cyc_i,
input wb_iwmb_stb_i,
input [2:0] wb_iwmb_cti_i,
input [1:0] wb_iwmb_bte_i,
output [31:0] wb_iwmb_dat_o,
output wb_iwmb_ack_o,
output wb_iwmb_err_o,
output wb_iwmb_rty_o,
input [31:0] wb_dwmb_adr_i,
input [31:0] wb_dwmb_dat_i,
input [3:0] wb_dwmb_sel_i,
input wb_dwmb_we_i,
input wb_dwmb_cyc_i,
input wb_dwmb_stb_i,
input [2:0] wb_dwmb_cti_i,
input [1:0] wb_dwmb_bte_i,
output [31:0] wb_dwmb_dat_o,
output wb_dwmb_ack_o,
output wb_dwmb_err_o,
output wb_dwmb_rty_o,
output [31:0] wb_uart_adr_o,
output [31:0] wb_uart_dat_o,
output [3:0] wb_uart_sel_o,
output wb_uart_we_o,
output wb_uart_cyc_o,
output wb_uart_stb_o,
output [2:0] wb_uart_cti_o,
output [1:0] wb_uart_bte_o,
input [31:0] wb_uart_dat_i,
input wb_uart_ack_i,
input wb_uart_err_i,
input wb_uart_rty_i,
output [31:0] wb_ram_adr_o,
output [31:0] wb_ram_dat_o,
output [3:0] wb_ram_sel_o,
output wb_ram_we_o,
output wb_ram_cyc_o,
output wb_ram_stb_o,
output [2:0] wb_ram_cti_o,
output [1:0] wb_ram_bte_o,
input [31:0] wb_ram_dat_i,
input wb_ram_ack_i,
input wb_ram_err_i,
input wb_ram_rty_i,
output [31:0] wb_rom_adr_o,
output [31:0] wb_rom_dat_o,
output [3:0] wb_rom_sel_o,
output wb_rom_we_o,
output wb_rom_cyc_o,
output wb_rom_stb_o,
output [2:0] wb_rom_cti_o,
output [1:0] wb_rom_bte_o,
input [31:0] wb_rom_dat_i,
input wb_rom_ack_i,
input wb_rom_err_i,
input wb_rom_rty_i,
output [31:0] wb_fw_interface_adr_o,
output [31:0] wb_fw_interface_dat_o,
output [3:0] wb_fw_interface_sel_o,
output wb_fw_interface_we_o,
output wb_fw_interface_cyc_o,
output wb_fw_interface_stb_o,
output [2:0] wb_fw_interface_cti_o,
output [1:0] wb_fw_interface_bte_o,
input [31:0] wb_fw_interface_dat_i,
input wb_fw_interface_ack_i,
input wb_fw_interface_err_i,
input wb_fw_interface_rty_i);
wire [31:0] wb_m2s_iwmb_ram_adr;
wire [31:0] wb_m2s_iwmb_ram_dat;
wire [3:0] wb_m2s_iwmb_ram_sel;
wire wb_m2s_iwmb_ram_we;
wire wb_m2s_iwmb_ram_cyc;
wire wb_m2s_iwmb_ram_stb;
wire [2:0] wb_m2s_iwmb_ram_cti;
wire [1:0] wb_m2s_iwmb_ram_bte;
wire [31:0] wb_s2m_iwmb_ram_dat;
wire wb_s2m_iwmb_ram_ack;
wire wb_s2m_iwmb_ram_err;
wire wb_s2m_iwmb_ram_rty;
wire [31:0] wb_m2s_iwmb_rom_adr;
wire [31:0] wb_m2s_iwmb_rom_dat;
wire [3:0] wb_m2s_iwmb_rom_sel;
wire wb_m2s_iwmb_rom_we;
wire wb_m2s_iwmb_rom_cyc;
wire wb_m2s_iwmb_rom_stb;
wire [2:0] wb_m2s_iwmb_rom_cti;
wire [1:0] wb_m2s_iwmb_rom_bte;
wire [31:0] wb_s2m_iwmb_rom_dat;
wire wb_s2m_iwmb_rom_ack;
wire wb_s2m_iwmb_rom_err;
wire wb_s2m_iwmb_rom_rty;
wire [31:0] wb_m2s_iwmb_uart_adr;
wire [31:0] wb_m2s_iwmb_uart_dat;
wire [3:0] wb_m2s_iwmb_uart_sel;
wire wb_m2s_iwmb_uart_we;
wire wb_m2s_iwmb_uart_cyc;
wire wb_m2s_iwmb_uart_stb;
wire [2:0] wb_m2s_iwmb_uart_cti;
wire [1:0] wb_m2s_iwmb_uart_bte;
wire [31:0] wb_s2m_iwmb_uart_dat;
wire wb_s2m_iwmb_uart_ack;
wire wb_s2m_iwmb_uart_err;
wire wb_s2m_iwmb_uart_rty;
wire [31:0] wb_m2s_iwmb_fw_interface_adr;
wire [31:0] wb_m2s_iwmb_fw_interface_dat;
wire [3:0] wb_m2s_iwmb_fw_interface_sel;
wire wb_m2s_iwmb_fw_interface_we;
wire wb_m2s_iwmb_fw_interface_cyc;
wire wb_m2s_iwmb_fw_interface_stb;
wire [2:0] wb_m2s_iwmb_fw_interface_cti;
wire [1:0] wb_m2s_iwmb_fw_interface_bte;
wire [31:0] wb_s2m_iwmb_fw_interface_dat;
wire wb_s2m_iwmb_fw_interface_ack;
wire wb_s2m_iwmb_fw_interface_err;
wire wb_s2m_iwmb_fw_interface_rty;
wire [31:0] wb_m2s_dwmb_uart_adr;
wire [31:0] wb_m2s_dwmb_uart_dat;
wire [3:0] wb_m2s_dwmb_uart_sel;
wire wb_m2s_dwmb_uart_we;
wire wb_m2s_dwmb_uart_cyc;
wire wb_m2s_dwmb_uart_stb;
wire [2:0] wb_m2s_dwmb_uart_cti;
wire [1:0] wb_m2s_dwmb_uart_bte;
wire [31:0] wb_s2m_dwmb_uart_dat;
wire wb_s2m_dwmb_uart_ack;
wire wb_s2m_dwmb_uart_err;
wire wb_s2m_dwmb_uart_rty;
wire [31:0] wb_m2s_dwmb_ram_adr;
wire [31:0] wb_m2s_dwmb_ram_dat;
wire [3:0] wb_m2s_dwmb_ram_sel;
wire wb_m2s_dwmb_ram_we;
wire wb_m2s_dwmb_ram_cyc;
wire wb_m2s_dwmb_ram_stb;
wire [2:0] wb_m2s_dwmb_ram_cti;
wire [1:0] wb_m2s_dwmb_ram_bte;
wire [31:0] wb_s2m_dwmb_ram_dat;
wire wb_s2m_dwmb_ram_ack;
wire wb_s2m_dwmb_ram_err;
wire wb_s2m_dwmb_ram_rty;
wire [31:0] wb_m2s_dwmb_rom_adr;
wire [31:0] wb_m2s_dwmb_rom_dat;
wire [3:0] wb_m2s_dwmb_rom_sel;
wire wb_m2s_dwmb_rom_we;
wire wb_m2s_dwmb_rom_cyc;
wire wb_m2s_dwmb_rom_stb;
wire [2:0] wb_m2s_dwmb_rom_cti;
wire [1:0] wb_m2s_dwmb_rom_bte;
wire [31:0] wb_s2m_dwmb_rom_dat;
wire wb_s2m_dwmb_rom_ack;
wire wb_s2m_dwmb_rom_err;
wire wb_s2m_dwmb_rom_rty;
wire [31:0] wb_m2s_dwmb_fw_interface_adr;
wire [31:0] wb_m2s_dwmb_fw_interface_dat;
wire [3:0] wb_m2s_dwmb_fw_interface_sel;
wire wb_m2s_dwmb_fw_interface_we;
wire wb_m2s_dwmb_fw_interface_cyc;
wire wb_m2s_dwmb_fw_interface_stb;
wire [2:0] wb_m2s_dwmb_fw_interface_cti;
wire [1:0] wb_m2s_dwmb_fw_interface_bte;
wire [31:0] wb_s2m_dwmb_fw_interface_dat;
wire wb_s2m_dwmb_fw_interface_ack;
wire wb_s2m_dwmb_fw_interface_err;
wire wb_s2m_dwmb_fw_interface_rty;
wb_mux
#(.num_slaves (4),
.MATCH_ADDR ({32'h20000000, 32'h00000000, 32'h40000000, 32'he0000000}),
.MATCH_MASK ({32'hffff8000, 32'hffff8000, 32'hffffffe0, 32'hffffff80}))
wb_mux_iwmb
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_iwmb_adr_i),
.wbm_dat_i (wb_iwmb_dat_i),
.wbm_sel_i (wb_iwmb_sel_i),
.wbm_we_i (wb_iwmb_we_i),
.wbm_cyc_i (wb_iwmb_cyc_i),
.wbm_stb_i (wb_iwmb_stb_i),
.wbm_cti_i (wb_iwmb_cti_i),
.wbm_bte_i (wb_iwmb_bte_i),
.wbm_dat_o (wb_iwmb_dat_o),
.wbm_ack_o (wb_iwmb_ack_o),
.wbm_err_o (wb_iwmb_err_o),
.wbm_rty_o (wb_iwmb_rty_o),
.wbs_adr_o ({wb_m2s_iwmb_ram_adr, wb_m2s_iwmb_rom_adr, wb_m2s_iwmb_uart_adr, wb_m2s_iwmb_fw_interface_adr}),
.wbs_dat_o ({wb_m2s_iwmb_ram_dat, wb_m2s_iwmb_rom_dat, wb_m2s_iwmb_uart_dat, wb_m2s_iwmb_fw_interface_dat}),
.wbs_sel_o ({wb_m2s_iwmb_ram_sel, wb_m2s_iwmb_rom_sel, wb_m2s_iwmb_uart_sel, wb_m2s_iwmb_fw_interface_sel}),
.wbs_we_o ({wb_m2s_iwmb_ram_we, wb_m2s_iwmb_rom_we, wb_m2s_iwmb_uart_we, wb_m2s_iwmb_fw_interface_we}),
.wbs_cyc_o ({wb_m2s_iwmb_ram_cyc, wb_m2s_iwmb_rom_cyc, wb_m2s_iwmb_uart_cyc, wb_m2s_iwmb_fw_interface_cyc}),
.wbs_stb_o ({wb_m2s_iwmb_ram_stb, wb_m2s_iwmb_rom_stb, wb_m2s_iwmb_uart_stb, wb_m2s_iwmb_fw_interface_stb}),
.wbs_cti_o ({wb_m2s_iwmb_ram_cti, wb_m2s_iwmb_rom_cti, wb_m2s_iwmb_uart_cti, wb_m2s_iwmb_fw_interface_cti}),
.wbs_bte_o ({wb_m2s_iwmb_ram_bte, wb_m2s_iwmb_rom_bte, wb_m2s_iwmb_uart_bte, wb_m2s_iwmb_fw_interface_bte}),
.wbs_dat_i ({wb_s2m_iwmb_ram_dat, wb_s2m_iwmb_rom_dat, wb_s2m_iwmb_uart_dat, wb_s2m_iwmb_fw_interface_dat}),
.wbs_ack_i ({wb_s2m_iwmb_ram_ack, wb_s2m_iwmb_rom_ack, wb_s2m_iwmb_uart_ack, wb_s2m_iwmb_fw_interface_ack}),
.wbs_err_i ({wb_s2m_iwmb_ram_err, wb_s2m_iwmb_rom_err, wb_s2m_iwmb_uart_err, wb_s2m_iwmb_fw_interface_err}),
.wbs_rty_i ({wb_s2m_iwmb_ram_rty, wb_s2m_iwmb_rom_rty, wb_s2m_iwmb_uart_rty, wb_s2m_iwmb_fw_interface_rty}));
wb_mux
#(.num_slaves (4),
.MATCH_ADDR ({32'h40000000, 32'h20000000, 32'h00000000, 32'he0000000}),
.MATCH_MASK ({32'hffffffe0, 32'hffff8000, 32'hffff8000, 32'hffffff80}))
wb_mux_dwmb
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i (wb_dwmb_adr_i),
.wbm_dat_i (wb_dwmb_dat_i),
.wbm_sel_i (wb_dwmb_sel_i),
.wbm_we_i (wb_dwmb_we_i),
.wbm_cyc_i (wb_dwmb_cyc_i),
.wbm_stb_i (wb_dwmb_stb_i),
.wbm_cti_i (wb_dwmb_cti_i),
.wbm_bte_i (wb_dwmb_bte_i),
.wbm_dat_o (wb_dwmb_dat_o),
.wbm_ack_o (wb_dwmb_ack_o),
.wbm_err_o (wb_dwmb_err_o),
.wbm_rty_o (wb_dwmb_rty_o),
.wbs_adr_o ({wb_m2s_dwmb_uart_adr, wb_m2s_dwmb_ram_adr, wb_m2s_dwmb_rom_adr, wb_m2s_dwmb_fw_interface_adr}),
.wbs_dat_o ({wb_m2s_dwmb_uart_dat, wb_m2s_dwmb_ram_dat, wb_m2s_dwmb_rom_dat, wb_m2s_dwmb_fw_interface_dat}),
.wbs_sel_o ({wb_m2s_dwmb_uart_sel, wb_m2s_dwmb_ram_sel, wb_m2s_dwmb_rom_sel, wb_m2s_dwmb_fw_interface_sel}),
.wbs_we_o ({wb_m2s_dwmb_uart_we, wb_m2s_dwmb_ram_we, wb_m2s_dwmb_rom_we, wb_m2s_dwmb_fw_interface_we}),
.wbs_cyc_o ({wb_m2s_dwmb_uart_cyc, wb_m2s_dwmb_ram_cyc, wb_m2s_dwmb_rom_cyc, wb_m2s_dwmb_fw_interface_cyc}),
.wbs_stb_o ({wb_m2s_dwmb_uart_stb, wb_m2s_dwmb_ram_stb, wb_m2s_dwmb_rom_stb, wb_m2s_dwmb_fw_interface_stb}),
.wbs_cti_o ({wb_m2s_dwmb_uart_cti, wb_m2s_dwmb_ram_cti, wb_m2s_dwmb_rom_cti, wb_m2s_dwmb_fw_interface_cti}),
.wbs_bte_o ({wb_m2s_dwmb_uart_bte, wb_m2s_dwmb_ram_bte, wb_m2s_dwmb_rom_bte, wb_m2s_dwmb_fw_interface_bte}),
.wbs_dat_i ({wb_s2m_dwmb_uart_dat, wb_s2m_dwmb_ram_dat, wb_s2m_dwmb_rom_dat, wb_s2m_dwmb_fw_interface_dat}),
.wbs_ack_i ({wb_s2m_dwmb_uart_ack, wb_s2m_dwmb_ram_ack, wb_s2m_dwmb_rom_ack, wb_s2m_dwmb_fw_interface_ack}),
.wbs_err_i ({wb_s2m_dwmb_uart_err, wb_s2m_dwmb_ram_err, wb_s2m_dwmb_rom_err, wb_s2m_dwmb_fw_interface_err}),
.wbs_rty_i ({wb_s2m_dwmb_uart_rty, wb_s2m_dwmb_ram_rty, wb_s2m_dwmb_rom_rty, wb_s2m_dwmb_fw_interface_rty}));
wb_arbiter
#(.num_masters (2))
wb_arbiter_uart
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_uart_adr, wb_m2s_dwmb_uart_adr}),
.wbm_dat_i ({wb_m2s_iwmb_uart_dat, wb_m2s_dwmb_uart_dat}),
.wbm_sel_i ({wb_m2s_iwmb_uart_sel, wb_m2s_dwmb_uart_sel}),
.wbm_we_i ({wb_m2s_iwmb_uart_we, wb_m2s_dwmb_uart_we}),
.wbm_cyc_i ({wb_m2s_iwmb_uart_cyc, wb_m2s_dwmb_uart_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_uart_stb, wb_m2s_dwmb_uart_stb}),
.wbm_cti_i ({wb_m2s_iwmb_uart_cti, wb_m2s_dwmb_uart_cti}),
.wbm_bte_i ({wb_m2s_iwmb_uart_bte, wb_m2s_dwmb_uart_bte}),
.wbm_dat_o ({wb_s2m_iwmb_uart_dat, wb_s2m_dwmb_uart_dat}),
.wbm_ack_o ({wb_s2m_iwmb_uart_ack, wb_s2m_dwmb_uart_ack}),
.wbm_err_o ({wb_s2m_iwmb_uart_err, wb_s2m_dwmb_uart_err}),
.wbm_rty_o ({wb_s2m_iwmb_uart_rty, wb_s2m_dwmb_uart_rty}),
.wbs_adr_o (wb_uart_adr_o),
.wbs_dat_o (wb_uart_dat_o),
.wbs_sel_o (wb_uart_sel_o),
.wbs_we_o (wb_uart_we_o),
.wbs_cyc_o (wb_uart_cyc_o),
.wbs_stb_o (wb_uart_stb_o),
.wbs_cti_o (wb_uart_cti_o),
.wbs_bte_o (wb_uart_bte_o),
.wbs_dat_i (wb_uart_dat_i),
.wbs_ack_i (wb_uart_ack_i),
.wbs_err_i (wb_uart_err_i),
.wbs_rty_i (wb_uart_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_ram
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_ram_adr, wb_m2s_dwmb_ram_adr}),
.wbm_dat_i ({wb_m2s_iwmb_ram_dat, wb_m2s_dwmb_ram_dat}),
.wbm_sel_i ({wb_m2s_iwmb_ram_sel, wb_m2s_dwmb_ram_sel}),
.wbm_we_i ({wb_m2s_iwmb_ram_we, wb_m2s_dwmb_ram_we}),
.wbm_cyc_i ({wb_m2s_iwmb_ram_cyc, wb_m2s_dwmb_ram_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_ram_stb, wb_m2s_dwmb_ram_stb}),
.wbm_cti_i ({wb_m2s_iwmb_ram_cti, wb_m2s_dwmb_ram_cti}),
.wbm_bte_i ({wb_m2s_iwmb_ram_bte, wb_m2s_dwmb_ram_bte}),
.wbm_dat_o ({wb_s2m_iwmb_ram_dat, wb_s2m_dwmb_ram_dat}),
.wbm_ack_o ({wb_s2m_iwmb_ram_ack, wb_s2m_dwmb_ram_ack}),
.wbm_err_o ({wb_s2m_iwmb_ram_err, wb_s2m_dwmb_ram_err}),
.wbm_rty_o ({wb_s2m_iwmb_ram_rty, wb_s2m_dwmb_ram_rty}),
.wbs_adr_o (wb_ram_adr_o),
.wbs_dat_o (wb_ram_dat_o),
.wbs_sel_o (wb_ram_sel_o),
.wbs_we_o (wb_ram_we_o),
.wbs_cyc_o (wb_ram_cyc_o),
.wbs_stb_o (wb_ram_stb_o),
.wbs_cti_o (wb_ram_cti_o),
.wbs_bte_o (wb_ram_bte_o),
.wbs_dat_i (wb_ram_dat_i),
.wbs_ack_i (wb_ram_ack_i),
.wbs_err_i (wb_ram_err_i),
.wbs_rty_i (wb_ram_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_rom
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_rom_adr, wb_m2s_dwmb_rom_adr}),
.wbm_dat_i ({wb_m2s_iwmb_rom_dat, wb_m2s_dwmb_rom_dat}),
.wbm_sel_i ({wb_m2s_iwmb_rom_sel, wb_m2s_dwmb_rom_sel}),
.wbm_we_i ({wb_m2s_iwmb_rom_we, wb_m2s_dwmb_rom_we}),
.wbm_cyc_i ({wb_m2s_iwmb_rom_cyc, wb_m2s_dwmb_rom_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_rom_stb, wb_m2s_dwmb_rom_stb}),
.wbm_cti_i ({wb_m2s_iwmb_rom_cti, wb_m2s_dwmb_rom_cti}),
.wbm_bte_i ({wb_m2s_iwmb_rom_bte, wb_m2s_dwmb_rom_bte}),
.wbm_dat_o ({wb_s2m_iwmb_rom_dat, wb_s2m_dwmb_rom_dat}),
.wbm_ack_o ({wb_s2m_iwmb_rom_ack, wb_s2m_dwmb_rom_ack}),
.wbm_err_o ({wb_s2m_iwmb_rom_err, wb_s2m_dwmb_rom_err}),
.wbm_rty_o ({wb_s2m_iwmb_rom_rty, wb_s2m_dwmb_rom_rty}),
.wbs_adr_o (wb_rom_adr_o),
.wbs_dat_o (wb_rom_dat_o),
.wbs_sel_o (wb_rom_sel_o),
.wbs_we_o (wb_rom_we_o),
.wbs_cyc_o (wb_rom_cyc_o),
.wbs_stb_o (wb_rom_stb_o),
.wbs_cti_o (wb_rom_cti_o),
.wbs_bte_o (wb_rom_bte_o),
.wbs_dat_i (wb_rom_dat_i),
.wbs_ack_i (wb_rom_ack_i),
.wbs_err_i (wb_rom_err_i),
.wbs_rty_i (wb_rom_rty_i));
wb_arbiter
#(.num_masters (2))
wb_arbiter_fw_interface
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbm_adr_i ({wb_m2s_iwmb_fw_interface_adr, wb_m2s_dwmb_fw_interface_adr}),
.wbm_dat_i ({wb_m2s_iwmb_fw_interface_dat, wb_m2s_dwmb_fw_interface_dat}),
.wbm_sel_i ({wb_m2s_iwmb_fw_interface_sel, wb_m2s_dwmb_fw_interface_sel}),
.wbm_we_i ({wb_m2s_iwmb_fw_interface_we, wb_m2s_dwmb_fw_interface_we}),
.wbm_cyc_i ({wb_m2s_iwmb_fw_interface_cyc, wb_m2s_dwmb_fw_interface_cyc}),
.wbm_stb_i ({wb_m2s_iwmb_fw_interface_stb, wb_m2s_dwmb_fw_interface_stb}),
.wbm_cti_i ({wb_m2s_iwmb_fw_interface_cti, wb_m2s_dwmb_fw_interface_cti}),
.wbm_bte_i ({wb_m2s_iwmb_fw_interface_bte, wb_m2s_dwmb_fw_interface_bte}),
.wbm_dat_o ({wb_s2m_iwmb_fw_interface_dat, wb_s2m_dwmb_fw_interface_dat}),
.wbm_ack_o ({wb_s2m_iwmb_fw_interface_ack, wb_s2m_dwmb_fw_interface_ack}),
.wbm_err_o ({wb_s2m_iwmb_fw_interface_err, wb_s2m_dwmb_fw_interface_err}),
.wbm_rty_o ({wb_s2m_iwmb_fw_interface_rty, wb_s2m_dwmb_fw_interface_rty}),
.wbs_adr_o (wb_fw_interface_adr_o),
.wbs_dat_o (wb_fw_interface_dat_o),
.wbs_sel_o (wb_fw_interface_sel_o),
.wbs_we_o (wb_fw_interface_we_o),
.wbs_cyc_o (wb_fw_interface_cyc_o),
.wbs_stb_o (wb_fw_interface_stb_o),
.wbs_cti_o (wb_fw_interface_cti_o),
.wbs_bte_o (wb_fw_interface_bte_o),
.wbs_dat_i (wb_fw_interface_dat_i),
.wbs_ack_i (wb_fw_interface_ack_i),
.wbs_err_i (wb_fw_interface_err_i),
.wbs_rty_i (wb_fw_interface_rty_i));
endmodule
|
`timescale 1ns / 1ps
module dmix_t;
// ins
reg rst;
reg clk;
parameter TCLK = 40;
initial clk = 0;
always #(TCLK/2) clk = ~clk;
reg signal;
reg sck;
parameter TCLK_SCK = 80;
reg mosi;
reg ss;
parameter TclkSPDIF = 40; // 24.576MHz == 192Khz * 32 bit * 2 (biphase)
nkmdhpa uut(
.rst(rst),
.clk245760_pad(clk),
.spdif_i(signal),
.csr_sck(sck),
.csr_mosi(mosi),
.csr_ss(ss));
task recv_rawbit;
input b;
begin
signal = b;
#(TclkSPDIF);//*6);
end
endtask
task recv_B;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
end
end
endtask
task recv_M;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
end
end
endtask
task recv_W;
begin
if(signal) begin
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(1);
end else begin
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
recv_rawbit(1);
recv_rawbit(0);
recv_rawbit(0);
end
end
endtask
task recv_bmcbit;
input b;
begin
if(signal) begin
if(b) begin
recv_rawbit(0);
recv_rawbit(1);
end else begin
recv_rawbit(0);
recv_rawbit(0);
end
end else begin
if(b) begin
recv_rawbit(1);
recv_rawbit(0);
end else begin
recv_rawbit(1);
recv_rawbit(1);
end
end
end
endtask
task recv_bmcbyte;
input [7:0] byte;
begin
recv_bmcbit(byte[0]);
recv_bmcbit(byte[1]);
recv_bmcbit(byte[2]);
recv_bmcbit(byte[3]);
recv_bmcbit(byte[4]);
recv_bmcbit(byte[5]);
recv_bmcbit(byte[6]);
recv_bmcbit(byte[7]);
end
endtask
task recv_bmcctl;
begin
recv_bmcbit(1);
recv_bmcbit(1);
recv_bmcbit(1);
recv_bmcbit(1);
end
endtask
task recv_subframe;
input [23:0] data;
begin
recv_bmcbyte(data[7:0]);
recv_bmcbyte(data[15:8]);
recv_bmcbyte(data[23:16]);
recv_bmcctl();
end
endtask
task spi_cycle;
input [7:0] data;
begin
#(TCLK_SCK/2);
ss = 0;
#(TCLK_SCK/2);
mosi = data[7];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[6];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[5];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[4];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[3];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[2];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[1];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[0];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
#(TCLK_SCK/2);
ss = 1;
#(TCLK_SCK/2);
end
endtask
`define USE_CAPTURE
`define PROGCMD_LEN 112
reg [7:0] progcmd [(`PROGCMD_LEN-1):0];
initial $readmemh("progcmd.memh", progcmd);
reg replay_capture;
initial replay_capture = 1'b0;
integer i;
reg [22:0] counter;
initial begin
$dumpfile("nkmdhpa_t.lxt");
$dumpvars(0, uut);
rst = 1'b0;
signal = 0;
counter = 0;
mosi = 1'b0;
ss = 1'b1;
#(100);
rst = 1'b1;
#(200);
rst = 1'b0;
#(1500);
for (i = 0; i < `PROGCMD_LEN; i = i + 1) begin
spi_cycle(progcmd[i]);
end
#(100);
$display("--- NKMD dbgin");
#(TCLK*3);
spi_cycle({4'b1_11_0, 4'h6});
spi_cycle(8'h00); // offset
spi_cycle(8'h01);
spi_cycle(8'h02);
spi_cycle(8'h03);
spi_cycle(8'h04);
spi_cycle(8'h05);
spi_cycle(8'h06);
spi_cycle(8'h07);
spi_cycle(8'h08);
spi_cycle(8'h09);
spi_cycle(8'h0a);
spi_cycle(8'h0b);
spi_cycle(8'h0c);
spi_cycle(8'h0d);
spi_cycle(8'h0e);
spi_cycle(8'h0f);
spi_cycle(8'h10);
#(TCLK*3);
$display("--- NKMD rst => 0");
#(TCLK*3);
spi_cycle({4'b1_01_0, 4'h4});
spi_cycle(8'h00); // offset
spi_cycle(8'h00); // data
#(TCLK*3);
replay_capture = 1'b1;
#(30000);
$finish(2);
end
`ifndef USE_CAPTURE
always begin
recv_B();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
repeat(63) begin
recv_M();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
end
$finish(2);
recv_B();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
repeat(63) begin
recv_M();
recv_subframe(counter);
counter = counter + 1;
recv_W();
recv_subframe(counter);
counter = counter + 1;
end
if (counter > 512)
$finish(2);
end
`else
reg [31:0] capture [262143:0];
integer capture_iter;
initial $readmemh("spdif_capture3", capture);
initial capture_iter = 0;
always begin
if (replay_capture) begin
signal = capture[capture_iter][2];
capture_iter = capture_iter + 1;
if (capture_iter > 262143)
$finish(2);
end
#(5);
end
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221O_2_V
`define SKY130_FD_SC_MS__A221O_2_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221o_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221O_2_V
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module watchdog(
input nLDS, RW,
input A23I, A22I,
input [21:17] M68K_ADDR_U,
//input [12:1] M68K_ADDR_L,
input WDCLK,
output nHALT,
output nRESET,
input nRST
);
reg [3:0] WDCNT;
initial
WDCNT <= 4'b0000;
// IMPORTANT:
// nRESET is an open-collector output on B1, so that the 68k can drive it (RESET instruction)
// The line has a 4.7k pullup (schematics page 1)
// nRESET changes state on posedge nBNKB (posedge mclk), but takes a slightly variable amount of time to
// return high after it is released. Low during 8 frames, released during 8 frames.
assign nRESET = nRST & ~WDCNT[3];
assign nHALT = nRESET;
// $300001 (LDS)
// 0011000xxxxxxxxxxxxxxxx1
// MAME says 00110001xxxxxxxxxxxxxxx1 but NEO-B1 doesn't have A16
assign WDRESET = &{nRST, ~|{nLDS, RW, A23I, A22I}, M68K_ADDR_U[21:20], ~|{M68K_ADDR_U[19:17]}};
always @(posedge WDCLK or posedge WDRESET or posedge ~nRST)
begin
if (WDRESET)
begin
WDCNT <= 4'b0000;
end
else if (!nRST)
begin
WDCNT <= 4'b1110; // DEBUG - Used to speed up simulation
//WDCNT <= 4'b1000; // Correct value
end
else
WDCNT <= WDCNT + 1'b1;
end
endmodule
|
//% @file fifo_over_ufc_tb.v
//% @brief test bench of FIFO I/O via Aurora 64B66B UFC interface
//% @author Yuan Mei
//%
`timescale 1ns / 1ps
module fifo_over_ufc_tb
#(
parameter FIFO_DATA_WIDTH = 32,
parameter AURORA_DATA_WIDTH = 64
)
();
reg clk;
reg reset;
wire a_tx_req;
wire [7:0] a_tx_ms;
reg a_tx_tready;
wire [AURORA_DATA_WIDTH-1:0] a_tx_tdata;
wire a_tx_tvalid;
wire [AURORA_DATA_WIDTH-1:0] a_rx_tdata;
reg a_rx_tvalid;
wire fifo_clk;
wire [FIFO_DATA_WIDTH-1:0] tx_fifo_q;
wire tx_fifo_wren;
reg tx_fifo_full;
reg [FIFO_DATA_WIDTH-1:0] rx_fifo_q;
wire rx_fifo_rden;
reg rx_fifo_empty;
wire err;
fifo_over_ufc #(.FIFO_DATA_WIDTH(FIFO_DATA_WIDTH), .AURORA_DATA_WIDTH(AURORA_DATA_WIDTH))
uut
(
.RESET(reset),
.AURORA_USER_CLK(clk),
.AURORA_TX_REQ(a_tx_req),
.AURORA_TX_MS(a_tx_ms),
.AURORA_TX_TREADY(a_tx_tready),
.AURORA_TX_TDATA(a_tx_tdata),
.AURORA_TX_TVALID(a_tx_tvalid),
.AURORA_RX_TDATA(a_rx_tdata),
.AURORA_RX_TVALID(a_rx_tvalid),
.FIFO_CLK(fifo_clk),
.TX_FIFO_Q(tx_fifo_q),
.TX_FIFO_WREN(tx_fifo_wren),
.TX_FIFO_FULL(tx_fifo_full),
.RX_FIFO_Q(rx_fifo_q),
.RX_FIFO_RDEN(rx_fifo_rden),
.RX_FIFO_EMPTY(rx_fifo_empty),
.ERR(err)
);
//initial begin
//$dumpfile("fifo_over_ufc.vcd");
//$dumpvars(0, fifo_over_ufc);
//end
initial begin
clk = 0;
reset = 0;
#16 reset = 1;
#26 reset = 0;
#200 reset = 1;
#10 reset = 0;
end
always #5 clk = ~clk;
initial begin
rx_fifo_empty = 1;
a_rx_tvalid = 0;
tx_fifo_full = 0;
#46 rx_fifo_empty = 0;
#120 rx_fifo_empty = 1;
#40 a_rx_tvalid = 1;
#10 a_rx_tvalid = 0; tx_fifo_full = 1;
end
// emulate Aurora UFC interface
reg [1:0] state;
localparam S0 = 2'h0;
localparam S1 = 2'h1;
localparam S2 = 2'h2;
localparam S3 = 2'h3;
always @ (posedge clk or posedge reset) begin
if (reset) begin
state <= S0;
a_tx_tready <= 1;
end
else begin
a_tx_tready <= 1;
case (state)
S0: begin
state <= S0;
if (a_tx_req == 1) begin
state <= S1;
a_tx_tready <= 0;
end
end
S1: begin
state <= S2;
a_tx_tready <= 0;
end
S2: begin
state <= S3;
a_tx_tready <= 1;
end
S3: begin
state <= S3;
a_tx_tready <= 1;
if (a_tx_tvalid == 1) begin
state <= S0;
end
end
default: begin
state <= S0;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFBUF_16_V
`define SKY130_FD_SC_HS__BUFBUF_16_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufbuf_16 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFBUF_16_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFLP_M_V
`define SKY130_FD_SC_LP__BUFLP_M_V
/**
* buflp: Buffer, Low Power.
*
* Verilog wrapper for buflp with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__buflp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buflp_m (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buflp base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buflp_m (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buflp base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFLP_M_V
|
/*
* TOP2049 Open Source programming suite
*
* Atmel AT89S5X DIP40
* FPGA bottomhalf implementation
*
* Copyright (c) 2010 Guido
* Copyright (c) 2010 Michael Buesch <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
/* The runtime ID and revision. */
`define RUNTIME_ID 16'h0005
`define RUNTIME_REV 16'h01
module at89s5xdip40(data, ale, write, read, osc_in, zif);
inout [7:0] data;
input ale;
input write;
input read;
input osc_in; /* 24MHz oscillator */
inout [48:1] zif;
/* Interface to the microcontroller */
wire read_oe; /* Read output-enable */
reg [7:0] address; /* Cached address value */
reg [7:0] read_data; /* Cached read data */
wire low, high; /* Constant lo/hi */
/* Programmer context */
reg [1:0] prog_busy;
reg [3:0] prog_command;
reg [3:0] prog_state;
reg [3:0] prog_count;
reg prog_err;
/* DUT signals */
reg [7:0] dut_data;
reg [13:0] dut_addr;
reg dut_p26;
reg dut_p27;
reg dut_p33;
reg dut_p36;
reg dut_p37;
reg dut_psen;
reg dut_prog;
reg dut_vpp;
reg dut_rst;
wire dut_clock;
assign low = 0;
assign high = 1;
initial begin
prog_busy <= 0;
prog_command <= 0;
prog_state <= 0;
prog_err <= 0;
prog_count <= 0;
dut_data <= 0;
dut_addr <= 0;
dut_p26 <= 0;
dut_p27 <= 0;
dut_p33 <= 0;
dut_p36 <= 0;
dut_p37 <= 0;
dut_psen <= 0;
dut_prog <= 0;
dut_vpp <= 0;
dut_rst <= 0;
end
/* The delay counter. Based on the 24MHz input clock. */
reg [15:0] delay_count;
wire osc;
assign dut_clock=osc;
IBUF osc_ibuf(.I(osc_in), .O(osc));
always @(posedge osc) begin
if (delay_count == 0) begin
if (prog_busy[0] != prog_busy[1]) begin
/* busy0 != busy1 indicates that a command is running.
* Continue executing it... */
case (prog_command)
1: begin /* Set P3.2 after init */
dut_prog <= 1;
prog_busy[1] <= prog_busy[0];
end
2: begin /* clear P3.2 before shutdown */
dut_prog <= 0;
prog_busy[1] <= prog_busy[0];
end
3: begin /* do nPROG pulsep with wait for ready */
case (prog_state)
0: begin /* raise dut_prog */
dut_prog <= 1;
prog_state <= 1;
delay_count <= 48;/*2us (48 tcl) wait*/
prog_err <= 0;
end
1: begin /* pulse */
delay_count <= 24;/* each 1us */
dut_prog <= 0;
prog_state <= 2;
end
2: begin /* raise dut_prog */
dut_prog <= 1;
prog_state <= 3;
prog_count <= 12;
delay_count <= 48;/*2us (48 tcl) wait*/
end
3: begin /* wait for ready (zif[14]) == 1 */
if (zif[14] == 0) begin
delay_count <= 80; /* each 3330ns */
prog_count <= prog_count - 1;
if (prog_count == 0) begin
prog_err <= 1;
prog_state <= 4;
end
end
else begin
prog_state <= 4;
end
end
4: begin /* finish */
prog_state <= 0;
prog_busy[1] <= prog_busy[0];
end
endcase
end
4: begin /* do nPROG pulsep */
case (prog_state)
0: begin
dut_prog <= 1;
prog_state <= 1;
delay_count <= 48;/*48tcy, 2us*/
prog_err <= 0;
end
1: begin /* pulse */
delay_count <= 24; /* 1us each */
dut_prog <= 0;
prog_state <= 2;
end
2: begin
dut_prog <= 1;
prog_state <= 3;
delay_count <= 48;/*48tcy, 2us*/
end
3: begin
prog_busy[1] <= prog_busy[0];
prog_state <= 0;
end
endcase
end
5: begin /* set dut_vpp */
dut_vpp <= 1;
prog_busy[1] <= prog_busy[0];
end
6: begin /* clear dut_vpp */
dut_vpp <= 0;
prog_busy[1] <= prog_busy[0];
end
endcase
end
end else begin
delay_count <= delay_count - 1;
end
end
always @(posedge write) begin
case (address)
8'h10: begin
/* Data write */
dut_data <= data;
end
8'h11: begin
/* Address LSB write */
dut_addr[7:0] <= data;
end
8'h12: begin
/* Address MSB write */
dut_addr[13:8] <= data[5:0];
end
8'h13: begin
/* Run a command. */
prog_command <= data;
prog_busy[0] <= ~prog_busy[1];
end
8'h16: begin
/* Set P26, P27, P33, P36, P37, dut_psen, dut_rst */
dut_p26 <= data[0];
dut_p27 <= data[1];
dut_p33 <= data[2];
dut_p36 <= data[3];
dut_p37 <= data[4];
dut_psen <= data[5];
dut_rst <= data[6];
end
endcase
end
always @(negedge read) begin
case (address)
8'h10: begin
/* Data read */
read_data[7] <= zif[36];
read_data[6] <= zif[37];
read_data[5] <= zif[38];
read_data[4] <= zif[39];
read_data[3] <= zif[40];
read_data[2] <= zif[41];
read_data[1] <= zif[42];
read_data[0] <= zif[43];
end
8'h12: begin
/* Read status */
read_data[0] <= (prog_busy[0] != prog_busy[1]);
read_data[1] <= prog_err;
end
8'hFD: read_data <= `RUNTIME_ID & 16'hFF;
8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF;
8'hFF: read_data <= `RUNTIME_REV;
endcase
end
always @(negedge ale) begin
address <= data;
end
assign read_oe = !read && address[4];
bufif0(zif[1], low, low);
bufif0(zif[2], low, low);
bufif0(zif[3], low, low);
bufif0(zif[4], low, low);
bufif0(zif[5], dut_addr[0], dut_p26);
bufif0(zif[6], dut_addr[1], dut_p26);
bufif0(zif[7], dut_addr[2], dut_p26);
bufif0(zif[8], dut_addr[3], dut_p26);
bufif0(zif[9], dut_addr[4], dut_p26);
bufif0(zif[10], dut_addr[5], dut_p26);
bufif0(zif[11], dut_addr[6], dut_p26);
bufif0(zif[12], dut_addr[7], dut_p26);
bufif0(zif[13], dut_rst, low); /*Reset*/
bufif0(zif[14], low, high); /* P3.0 */
bufif0(zif[15], low, low); /* P3.1 */
bufif0(zif[16], low, low); /* P3.2 */
bufif0(zif[17], dut_p33, low); /* P3.3 */
bufif0(zif[18], low, low); /* P3.4 */
bufif0(zif[19], low, low); /* P3.5 */
bufif0(zif[20], dut_p36, low); /* P3.6 */
bufif0(zif[21], dut_p37, low); /* P3.7 */
bufif0(zif[22], low, high); /* XTAL2 */
bufif0(zif[23], dut_clock, low); /* XTAL1 */
bufif0(zif[24], low, low); /* GND */
bufif0(zif[25], dut_addr[8], dut_p26); /* P2.0 */
bufif0(zif[26], dut_addr[9], dut_p26); /* P2.1 */
bufif0(zif[27], dut_addr[10], dut_p26); /* P2.2 */
bufif0(zif[28], dut_addr[11], dut_p26); /* P2.3 */
bufif0(zif[29], dut_addr[12], dut_p26); /* P2.4 */
bufif0(zif[30], dut_addr[13], dut_p26); /* P2.5 */
bufif0(zif[31], dut_p26, low); /* P2.6 */
bufif0(zif[32], dut_p27, low); /* P2.7 */
bufif0(zif[33], dut_psen, low); /* !PSEN */
bufif0(zif[34], dut_prog, low); /* !PROG */
bufif0(zif[35], low, dut_vpp); /* VPP/Reset */
bufif0(zif[36], dut_data[7], !(!dut_p26 && dut_p27));
bufif0(zif[37], dut_data[6], !(!dut_p26 && dut_p27));
bufif0(zif[38], dut_data[5], !(!dut_p26 && dut_p27));
bufif0(zif[39], dut_data[4], !(!dut_p26 && dut_p27));
bufif0(zif[40], dut_data[3], !(!dut_p26 && dut_p27));
bufif0(zif[41], dut_data[2], !(!dut_p26 && dut_p27));
bufif0(zif[42], dut_data[1], !(!dut_p26 && dut_p27));
bufif0(zif[43], dut_data[0], !(!dut_p26 && dut_p27));
bufif0(zif[44], high, low); /* VCC */
bufif0(zif[45], low, low);
bufif0(zif[46], low, low);
bufif0(zif[47], low, low);
bufif0(zif[48], low, low);
bufif1(data[0], read_data[0], read_oe);
bufif1(data[1], read_data[1], read_oe);
bufif1(data[2], read_data[2], read_oe);
bufif1(data[3], read_data[3], read_oe);
bufif1(data[4], read_data[4], read_oe);
bufif1(data[5], read_data[5], read_oe);
bufif1(data[6], read_data[6], read_oe);
bufif1(data[7], read_data[7], read_oe);
endmodule
|
`include "Global_Macros.v"
module Write_Back(
clk_i,
rst_i,
gbl_stl_i,
wait_to_fill_pipe_i,
control_signal_i,
p_i,
dat_i,
eff_adr_i,
mem_stl_i,
a_o,
x_o,
y_o,
mem_w_enb_o,
mem_w_cnt_o,
mem_w_adr_o,
mem_w_dat_o
`ifdef DEBUG
,debug_o
`endif
);
//Input signals :
input wire clk_i;
input wire rst_i;
input wire gbl_stl_i;
input wire wait_to_fill_pipe_i;
input wire [`execut_cntrl_o_width - 1:0] control_signal_i;
input wire [7:0] p_i;
input wire [15:0] dat_i;
input wire [15:0] eff_adr_i;
input wire mem_stl_i;
//Output signals :
output wire [7:0] a_o;
output wire [7:0] x_o;
output wire [7:0] y_o;
output reg mem_w_enb_o;
output reg [1:0] mem_w_cnt_o;
output reg [15:0] mem_w_adr_o;
output reg [23:0] mem_w_dat_o;
`ifdef DEBUG
output wire [`WRB_DBG_WIDTH - 1:0] debug_o;
`endif
//Internal registers :
reg [7:0] a_reg;
reg [7:0] x_reg;
reg [7:0] y_reg;
//Assignments :
assign a_o = a_reg;
assign x_o = x_reg;
assign y_o = y_reg;
`ifdef DEBUG
assign debug_o = mem_w_adr_o;
`endif
//Blocks :
always @(posedge clk_i)
begin
if(rst_i == 1'h1)
begin
mem_w_enb_o <= 1'h0;
mem_w_cnt_o <= `ONE;
end
else if(gbl_stl_i == 1'h1 || mem_stl_i == 1'h1)
begin
mem_w_enb_o <= 1'h0;
end
else if(wait_to_fill_pipe_i == 1'h1)
begin
mem_w_enb_o <= 1'h0;
end
else
begin
mem_w_enb_o <= `cntrl_wb_mem_wr;
mem_w_cnt_o <= ( `cntrl_wb_mem_wr_cnt == `ONE ) ? 2'h0 :
( `cntrl_wb_mem_wr_cnt == `TWO ) ? 2'h1 : 2'h2;
mem_w_dat_o <= {p_i, dat_i};
mem_w_adr_o <= eff_adr_i;
end
end
always @(posedge clk_i)
begin
if(rst_i == 1'h1)
begin
a_reg <= 8'h0;
x_reg <= 8'h0;
y_reg <= 8'h0;
end
else if(gbl_stl_i == 1'h1 || mem_stl_i == 1'h1)
begin
end
else if(wait_to_fill_pipe_i == 1'h1)
begin
end
else
begin
a_reg <= (`cntrl_wb_ra_ld == 1'h1) ? dat_i[7:0] : a_reg;
x_reg <= (`cntrl_wb_rx_ld == 1'h1) ? dat_i[7:0] : x_reg;
y_reg <= (`cntrl_wb_ry_ld == 1'h1) ? dat_i[7:0] : y_reg;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SDFSBP_BEHAVIORAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSBP_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1P_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__INPUTISO1P_PP_SYMBOL_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso1p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1P_PP_SYMBOL_V
|
//--------------------------------------------------------------------------------
//-- Filename: FLOW_CONTROLLER.v
//--
//-- Description: FLOW CONTROLLER Module
//--
//-- The module controls the TLP sending rates to ensure that the TLP
//-- TX buffer and RX buffer in the PCIE core do not overflow.
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module FLOW_CONTROLLER(
clk,
rst_n,
init_rst_i,
mrd_start_i,
mrd_len_i,
//mrd_cur_rd_count_i,
mrd_tlp_sent_i,
cpld_data_size_i,
cfg_rd_comp_bound_i,
rd_metering_i,
mwr_start_i,
trn_tbuf_av_i,
mrd_start_fc_o,
mwr_start_fc_o
);
// Set when the PCIe CORE was generated
parameter MAX_REQUEST_SIZE = 128;
parameter MAX_PAYLOAD_SIZE = 256;
parameter CPLH_CREDITS = 36;
parameter CPLD_CREDITS = 154;
parameter TRANSMIT_TLP_BUFFERD = 29;
parameter LIMIT_FC_MAX_NP = 18;
input clk;
input rst_n , init_rst_i;
input mrd_start_i;
input [10:0] mrd_len_i; // Memory Read Size Command (DWs)
//input [15:0] mrd_cur_rd_count_i;
input [31:0] mrd_tlp_sent_i;
input mwr_start_i;
input [31:0] cpld_data_size_i;
input cfg_rd_comp_bound_i; // Programmed RCB = 0=64B or 1=128B
input rd_metering_i; // enable send rate control
input [5:0] trn_tbuf_av_i;
output mrd_start_fc_o;
output mwr_start_fc_o;
reg mrd_start_fc_o;
reg mwr_start_fc_o;
wire [31:0] NPs_send = mrd_tlp_sent_i;
wire [26:0] NPs_recv = cpld_data_size_i >> 5;
wire [26:0] NPs_pending = NPs_send[26:0] - NPs_recv;
always @ ( posedge clk ) begin
if( !rst_n ) begin
mrd_start_fc_o <= 1'b0;
mwr_start_fc_o <= 1'b0;
end
else begin
if(init_rst_i) begin
mrd_start_fc_o <= 1'b0;
mwr_start_fc_o <= 1'b0;
end
if( rd_metering_i ) begin
`ifdef SIMULATION
if( NPs_pending > 0 )
mrd_start_fc_o <= 1'b0;
else
mrd_start_fc_o <= mrd_start_i;
`else
if ( ( NPs_pending < LIMIT_FC_MAX_NP + 5 ) && ( trn_tbuf_av_i > 1'b1 ) )
mrd_start_fc_o <= mrd_start_i;
else
mrd_start_fc_o <= 1'b0;
`endif
end
else
mrd_start_fc_o <= mrd_start_i;
if( trn_tbuf_av_i > 1'b1 )
mwr_start_fc_o <= mwr_start_i;
else
mwr_start_fc_o <= 1'b0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SRSDFXTP_PP_SYMBOL_V
/**
* srsdfxtp: Scan flop with sleep mode, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srsdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFXTP_PP_SYMBOL_V
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// altera message_off 10036
module altera_mem_if_ddr3_phy_0001_new_io_pads(
reset_n_addr_cmd_clk,
reset_n_afi_clk,
oct_ctl_rs_value,
oct_ctl_rt_value,
phy_ddio_addr_cmd_clk,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_reset_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_reset_n,
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
pll_dqs_ena_clk,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_oct_ena,
dqs_enable_ctrl,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask,
phy_mem_dq,
phy_mem_dm,
phy_mem_ck,
phy_mem_ck_n,
mem_dqs,
mem_dqs_n,
dll_phy_delayctrl,
ddio_phy_dq,
read_capture_clk,
scc_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking
);
parameter DEVICE_FAMILY = "";
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter DQS_ENABLE_CTRL_WIDTH = "";
parameter ALTDQDQS_INPUT_FREQ = "";
parameter ALTDQDQS_DELAY_CHAIN_BUFFER_MODE = "";
parameter ALTDQDQS_DQS_PHASE_SETTING = "";
parameter ALTDQDQS_DQS_PHASE_SHIFT = "";
parameter ALTDQDQS_DELAYED_CLOCK_PHASE_SETTING = "";
parameter FAST_SIM_MODEL = "";
localparam DOUBLE_MEM_DQ_WIDTH = MEM_DQ_WIDTH * 2;
localparam HALF_AFI_DATA_WIDTH = AFI_DATA_WIDTH / 2;
localparam HALF_AFI_DQS_WIDTH = AFI_DQS_WIDTH / 2;
input reset_n_afi_clk;
input reset_n_addr_cmd_clk;
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
input phy_ddio_addr_cmd_clk;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output phy_mem_reset_n;
input pll_afi_clk;
input pll_mem_clk;
input pll_write_clk;
input pll_dqs_ena_clk;
input [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
input [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
input [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
input [DQS_ENABLE_CTRL_WIDTH-1:0] dqs_enable_ctrl;
input [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
input [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
inout [MEM_DQ_WIDTH-1:0] phy_mem_dq;
output [MEM_DM_WIDTH-1:0] phy_mem_dm;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output [DOUBLE_MEM_DQ_WIDTH-1:0] ddio_phy_dq;
output [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input scc_clk;
input scc_data;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
input [MEM_DM_WIDTH - 1:0] scc_dm_ena;
input scc_upd;
output [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
wire [MEM_DQ_WIDTH-1:0] mem_phy_dq;
wire [DLL_DELAY_CTRL_WIDTH-1:0] read_bidir_dll_phy_delayctrl;
wire [MEM_READ_DQS_WIDTH-1:0] bidir_read_dqs_bus_out;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_high;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_low;
wire hr_clk = pll_afi_clk;
wire core_clk = pll_afi_clk;
wire reset_n_core_clk = reset_n_afi_clk;
wire [AFI_DATA_WIDTH-1:0] phy_ddio_dq_int = phy_ddio_dq;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en_int = phy_ddio_wrdata_en;
wire [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask_int = phy_ddio_wrdata_mask;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en_int = phy_ddio_dqs_en;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena_int = phy_ddio_oct_ena;
altera_mem_if_ddr3_phy_0001_addr_cmd_pads uaddr_cmd_pads(
.reset_n (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_write_clk (pll_write_clk),
.phy_ddio_addr_cmd_clk (phy_ddio_addr_cmd_clk),
.dll_delayctrl_in (dll_phy_delayctrl),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (phy_mem_address),
.phy_mem_bank (phy_mem_bank),
.phy_mem_cs_n (phy_mem_cs_n),
.phy_mem_cke (phy_mem_cke),
.phy_mem_odt (phy_mem_odt),
.phy_mem_we_n (phy_mem_we_n),
.phy_mem_ras_n (phy_mem_ras_n),
.phy_mem_cas_n (phy_mem_cas_n),
.phy_mem_reset_n (phy_mem_reset_n),
.phy_mem_ck (phy_mem_ck),
.phy_mem_ck_n (phy_mem_ck_n)
);
defparam uaddr_cmd_pads.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
defparam uaddr_cmd_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.AFI_BANK_WIDTH = AFI_BANK_WIDTH;
defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.AFI_ODT_WIDTH = AFI_ODT_WIDTH;
defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uaddr_cmd_pads.DLL_WIDTH = DLL_DELAY_CTRL_WIDTH;
localparam NUM_OF_DQDQS = MEM_WRITE_DQS_WIDTH;
localparam DQDQS_DATA_WIDTH = MEM_DQ_WIDTH / NUM_OF_DQDQS;
localparam DQDQS_DM_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
localparam NUM_OF_DQDQS_WITH_DM = MEM_WRITE_DQS_WIDTH;
wire [HALF_AFI_DQS_WIDTH-1:0] phy_ddio_oe_l;
wire [HALF_AFI_DQS_WIDTH-1:0] phy_ddio_oe_h;
assign phy_ddio_oe_l = phy_ddio_wrdata_en_int[HALF_AFI_DQS_WIDTH-1:0];
assign phy_ddio_oe_h = phy_ddio_wrdata_en_int[AFI_DQS_WIDTH-1:HALF_AFI_DQS_WIDTH];
generate
genvar i;
for (i=0; i<NUM_OF_DQDQS; i=i+1)
begin: dq_ddio
wire dqs_busout;
// The phy_ddio_dq_int bus is the write data for all DQS groups in one
// AFI cycle. The bus is ordered by time slow and subordered by
// DQS group:
//
// FR: D1_T1, D0_T1, D1_T0, D0_T0
// HR: D1_T3, D0_T3, D1_T2, D0_T2, D1_T1, D0_T1, D1_T0, D0_T0
//
// The following extracts write data targeting the current DQS
// group.
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t0 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+0*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+0*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t1 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+1*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+1*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t2 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+2*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+2*NUM_OF_DQDQS)];
wire [DQDQS_DATA_WIDTH-1:0] phy_ddio_dq_t3 = phy_ddio_dq_int [DQDQS_DATA_WIDTH*(i+1+3*NUM_OF_DQDQS)-1 : DQDQS_DATA_WIDTH*(i+3*NUM_OF_DQDQS)];
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t0;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t1;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t2;
wire [DQDQS_DM_WIDTH-1:0] phy_ddio_wrdata_mask_t3;
assign phy_ddio_wrdata_mask_t0 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+0*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+0*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t1 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+1*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+1*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t2 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+2*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+2*NUM_OF_DQDQS_WITH_DM)];
assign phy_ddio_wrdata_mask_t3 = phy_ddio_wrdata_mask_int [DQDQS_DM_WIDTH*(i+1+3*NUM_OF_DQDQS_WITH_DM)-1 : DQDQS_DM_WIDTH*(i+3*NUM_OF_DQDQS_WITH_DM)];
altera_mem_if_ddr3_phy_0001_altdqdqs ubidir_dq_dqs (
.write_strobe_clock_in (1'b0),
.reset_n_core_clock_in (reset_n_core_clk),
.core_clock_in (core_clk),
.fr_clock_in (pll_write_clk),
.hr_clock_in (hr_clk),
.parallelterminationcontrol_in(oct_ctl_rt_value),
.seriesterminationcontrol_in(oct_ctl_rs_value),
.strobe_ena_hr_clock_in (hr_clk),
.strobe_ena_clock_in (pll_dqs_ena_clk),
.read_write_data_io (phy_mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.read_data_out (ddio_phy_dq [(2*DQDQS_DATA_WIDTH*(i+1)-1) : 2*DQDQS_DATA_WIDTH*i]),
.capture_strobe_out(dqs_busout),
.extra_write_data_in ({phy_ddio_wrdata_mask_t3, phy_ddio_wrdata_mask_t2, phy_ddio_wrdata_mask_t1, phy_ddio_wrdata_mask_t0}),
.write_data_in ({phy_ddio_dq_t3, phy_ddio_dq_t2, phy_ddio_dq_t1, phy_ddio_dq_t0}),
.write_oe_in ({ {DQDQS_DATA_WIDTH{phy_ddio_oe_h[i]}}, {DQDQS_DATA_WIDTH{phy_ddio_oe_l[i]}} }),
.strobe_io (mem_dqs[i]),
.strobe_n_io (mem_dqs_n[i]),
.output_strobe_ena ({phy_ddio_dqs_en_int[i+NUM_OF_DQDQS], phy_ddio_dqs_en_int[i]}),
.oct_ena_in ({phy_ddio_oct_ena_int[i+NUM_OF_DQDQS], phy_ddio_oct_ena_int[i]}),
.capture_strobe_ena ({dqs_enable_ctrl[i+NUM_OF_DQDQS], dqs_enable_ctrl[i]}),
.extra_write_data_out (phy_mem_dm[i]),
.config_data_in (scc_data),
.config_dqs_ena (scc_dqs_ena[i]),
.config_io_ena (scc_dq_ena[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.config_dqs_io_ena (scc_dqs_io_ena[i]),
.config_update (scc_upd),
.config_clock_in (scc_clk),
.config_extra_io_ena (scc_dm_ena[i]),
.dll_delayctrl_in (dll_phy_delayctrl)
);
defparam ubidir_dq_dqs.ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = FAST_SIM_MODEL;
assign read_capture_clk[i] = ~dqs_busout;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Boston University
// Engineer: Schuyler Eldridge; Zafar M. Takhirov
//
// Create Date: 13:00:22 04/12/2011
// Design Name: EC311/EC551 Support Files
// Module Name: vga_controller_640_60
// Project Name: N/A
// Target Devices: Spartan 6 Family
// Tool versions: XILINX ISE 1x.x
// Description:
//
// Dependencies: none
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_controller_640_60 (rst,pixel_clk,HS,VS,hcounter,vcounter,blank);
input rst, pixel_clk; // global reset, pixel clock
output reg HS, VS, blank; // sync controls, blank indicator
output reg [10:0] hcounter, vcounter; // pixel coordinates
/*
parameter HMAX = 800; // maxium value for the horizontal pixel counter
parameter VMAX = 525; // maxium value for the vertical pixel counter
parameter HLINES = 640; // total number of visible columns
parameter HFP = 648; // value for the horizontal counter where front porch ends
parameter HSP = 744; // value for the horizontal counter where the synch pulse ends
parameter VLINES = 480; // total number of visible lines
parameter VFP = 482; // value for the vertical counter where the frone proch ends
parameter VSP = 484; // value for the vertical counter where the synch pulse ends
parameter SPP = 0; // value for the porch synchronization pulse
*/
parameter HMAX = 800; // maxium value for the horizontal pixel counter
parameter HLINES = 640; // total number of visible columns
parameter HFP = 648; // value for the horizontal counter where front porch ends
parameter HSP = 744; // value for the horizontal counter where the synch pulse ends
parameter VMAX = 525; // maxium value for the vertical pixel counter
parameter VLINES = 480; // total number of visible lines
parameter VFP = 482; // value for the vertical counter where the frone proch ends
parameter VSP = 484; // value for the vertical counter where the synch pulse ends
parameter SPP = 0; // value for the porch synchronization pulse
wire video_enable; // valid region indicator
initial begin
hcounter = 0;
vcounter = 0;
end
// create a "blank" indicator
always@(posedge pixel_clk)begin
blank <= ~video_enable;
end
// Create a horizontal beam trace (horizontal time):
always@(posedge pixel_clk, posedge rst)begin
if(rst == 1) hcounter <= 0;
else if (hcounter == HMAX) hcounter <= 0;
else hcounter <= hcounter + 1'b1;
end
// Create a vertical beam trace (vertical time):
always@(posedge pixel_clk, posedge rst)begin
if(rst == 1) vcounter <=0;
else if(hcounter == HMAX) begin
if(vcounter == VMAX) vcounter <= 0;
else vcounter <= vcounter + 1'b1;
end
end
// Check if between horizontal porches,
// if not send horizontal porch synchronization pulse
always@(posedge pixel_clk)begin
if(hcounter >= HFP && hcounter < HSP) HS <= SPP;
else HS <= ~SPP;
end
// Check if between vertical porches,
// if not send vertical porch synchronization pulse
always@(posedge pixel_clk)begin
if(vcounter >= VFP && vcounter < VSP) VS <= SPP;
else VS <= ~SPP;
end
// create a video enabled region
assign video_enable = (hcounter < HLINES && vcounter < VLINES) ? 1'b1 : 1'b0;
endmodule
|
`timescale 1ns / 100ps
`define EIC_DIRECT_CHANNELS 20
`define EIC_SENSE_CHANNELS 20
`include "mfp_eic_core.vh"
module test_eicAhb;
`include "ahb_lite.vh"
reg [ `EIC_CHANNELS -1 : 0 ] signal;
wire [ 17 : 1 ] EIC_Offset;
wire [ 3 : 0 ] EIC_ShadowSet;
wire [ 7 : 0 ] EIC_Interrupt;
wire [ 5 : 0 ] EIC_Vector;
wire EIC_Present;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire [ 31 : 0 ] read_data;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;
reg [ 31 : 0 ] write_data;
reg write_enable;
task delay;
begin
@(posedge HCLK);
@(posedge HCLK);
@(posedge HCLK);
end
endtask
mfp_ahb_lite_eic eic
(
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.HADDR ( HADDR ),
.HBURST ( HBURST ),
.HSEL ( HSEL ),
.HSIZE ( HSIZE ),
.HTRANS ( HTRANS ),
.HWDATA ( HWDATA ),
.HWRITE ( HWRITE ),
.HRDATA ( HRDATA ),
.HREADY ( HREADY ),
.HRESP ( HRESP ),
.signal ( signal ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector ),
.EIC_Present ( EIC_Present )
);
/*
module mfp_ahb_lite_eic
(
//ABB-Lite side
input HCLK,
input HRESETn,
input [ 31 : 0 ] HADDR,
input [ 2 : 0 ] HBURST,
input HMASTLOCK, // ignored
input [ 3 : 0 ] HPROT, // ignored
input HSEL,
input [ 2 : 0 ] HSIZE,
input [ 1 : 0 ] HTRANS,
input [ 31 : 0 ] HWDATA,
input HWRITE,
output reg [ 31 : 0 ] HRDATA,
output HREADY,
output HRESP,
input SI_Endian, // ignored
//Interrupt side
input [ `EIC_CHANNELS-1 : 0 ] signal,
//CPU side
output [ 17 : 1 ] EIC_Offset,
output [ 3 : 0 ] EIC_ShadowSet,
output [ 7 : 0 ] EIC_Interrupt,
output [ 5 : 0 ] EIC_Vector,
output EIC_Present
);
*/
parameter Tclk = 20;
always #(Tclk/2) HCLK = ~HCLK;
initial begin
begin
signal = 16'b0;
HRESETn = 0;
@(posedge HCLK);
@(posedge HCLK);
HRESETn = 1;
@(posedge HCLK);
@(posedge HCLK);
ahbPhaseFst(`EIC_REG_EICR << 2, WRITE, HSIZE_X32, St_x); //enable eic
ahbPhase (`EIC_REG_EISMSK_0 << 2, WRITE, HSIZE_X32, 32'h01); //any logical change for irq 1, 2 (pins 0, 1)
ahbPhase (`EIC_REG_EIMSK_0 << 2, WRITE, HSIZE_X32, 32'h05); //enable irq 1, 2 (pins 0, 1)
ahbPhase (`EIC_REG_EIMSK_1 << 2, WRITE, HSIZE_X32, 32'h03); //enable irq 33 (pin 32)
ahbPhase (`EIC_REG_EICR << 2, READ, HSIZE_X32, 32'h01); //enable irq 33 (pin 32)
ahbPhase (`EIC_REG_EISMSK_0 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIMSK_0 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIMSK_1 << 2, READ, HSIZE_X32, St_x);
@(posedge HCLK); signal[0] = 1'b1;
@(posedge HCLK); signal[1] = 1'b1;
delay();
@(posedge HCLK); signal[32] = 1'b1;
@(posedge HCLK); signal[32] = 1'b0;
delay();
ahbPhase (`EIC_REG_EIFR_1 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFRC_1 << 2, WRITE, HSIZE_X32, St_x); //clear irq 33 (pin 32)
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h01);
delay();
ahbPhase (`EIC_REG_EIFR_0 << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h01); //set EIFR word0
delay();
ahbPhase (`EIC_REG_EIFRS_0 << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h04); //set EIFR bit3
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);
ahbPhaseLst(`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);
delay();
end
$stop;
$finish;
end
endmodule
|
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