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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3B_PP_SYMBOL_V
`define SKY130_FD_SC_LS__NOR3B_PP_SYMBOL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3B_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A2BB2O_FUNCTIONAL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X, nor0_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_FUNCTIONAL_V
|
`timescale 1ns/1ps
module system
(
input wire CLK100MHZ,
input wire ck_rst,
// Sliding switches
input wire sw_0,
input wire sw_1,
input wire sw_2,
input wire sw_3,
// RGB LEDs, 3 pins each
output wire led0_r,
output wire led0_g,
output wire led0_b,
output wire led1_r,
output wire led1_g,
output wire led1_b,
output wire led2_r,
output wire led2_g,
output wire led2_b,
output wire led3_r,
output wire led3_g,
output wire led3_b,
// Green LEDs
output wire led_0,
output wire led_1,
output wire led_2,
output wire led_3,
// Buttons
inout wire btn_0,
inout wire btn_1,
inout wire btn_2,
inout wire btn_3,
// Pmod (GPIO) connectors
inout wire ja_0,
inout wire ja_1,
inout wire ja_2,
inout wire ja_3,
inout wire ja_4,
inout wire ja_5,
inout wire ja_6,
inout wire ja_7,
inout wire jd_0,
inout wire jd_1,
inout wire jd_2,
inout wire jd_3,
inout wire jd_4,
inout wire jd_5,
inout wire jd_6,
inout wire jd_7,
// Dedicated QSPI interface
output wire qspi_cs,
output wire qspi_sck,
inout wire [3:0] qspi_dq,
// UART0 (GPIO 16,17)
output wire uart_rxd_out_pad,
input wire uart_txd_in_pad,
// Arduino (aka chipkit) shield digital IO pins, 14 is not connected to the
// chip, used for debug.
inout wire [19:0] ck_io,
// Dedicated SPI pins on 6 pin header standard on later arduino models
// connected to SPI2 (on FPGA)
inout wire ck_miso,
inout wire ck_mosi,
inout wire ck_ss,
inout wire ck_sck
);
wire clk_out1;
wire hfclk;
wire mmcm_locked;
wire reset_core;
wire reset_bus;
wire reset_periph;
wire reset_intcon_n;
wire reset_periph_n;
// All wires connected to the chip top
wire dut_clock;
wire dut_reset;
wire dut_io_pads_gpio_0_i_ival;
wire dut_io_pads_gpio_0_o_oval;
wire dut_io_pads_gpio_0_o_oe;
wire dut_io_pads_gpio_0_o_ie;
wire dut_io_pads_gpio_0_o_pue;
wire dut_io_pads_gpio_0_o_ds;
wire dut_io_pads_gpio_1_i_ival;
wire dut_io_pads_gpio_1_o_oval;
wire dut_io_pads_gpio_1_o_oe;
wire dut_io_pads_gpio_1_o_ie;
wire dut_io_pads_gpio_1_o_pue;
wire dut_io_pads_gpio_1_o_ds;
wire dut_io_pads_gpio_2_i_ival;
wire dut_io_pads_gpio_2_o_oval;
wire dut_io_pads_gpio_2_o_oe;
wire dut_io_pads_gpio_2_o_ie;
wire dut_io_pads_gpio_2_o_pue;
wire dut_io_pads_gpio_2_o_ds;
wire dut_io_pads_gpio_3_i_ival;
wire dut_io_pads_gpio_3_o_oval;
wire dut_io_pads_gpio_3_o_oe;
wire dut_io_pads_gpio_3_o_ie;
wire dut_io_pads_gpio_3_o_pue;
wire dut_io_pads_gpio_3_o_ds;
wire dut_io_pads_gpio_4_i_ival;
wire dut_io_pads_gpio_4_o_oval;
wire dut_io_pads_gpio_4_o_oe;
wire dut_io_pads_gpio_4_o_ie;
wire dut_io_pads_gpio_4_o_pue;
wire dut_io_pads_gpio_4_o_ds;
wire dut_io_pads_gpio_5_i_ival;
wire dut_io_pads_gpio_5_o_oval;
wire dut_io_pads_gpio_5_o_oe;
wire dut_io_pads_gpio_5_o_ie;
wire dut_io_pads_gpio_5_o_pue;
wire dut_io_pads_gpio_5_o_ds;
wire dut_io_pads_gpio_6_i_ival;
wire dut_io_pads_gpio_6_o_oval;
wire dut_io_pads_gpio_6_o_oe;
wire dut_io_pads_gpio_6_o_ie;
wire dut_io_pads_gpio_6_o_pue;
wire dut_io_pads_gpio_6_o_ds;
wire dut_io_pads_gpio_7_i_ival;
wire dut_io_pads_gpio_7_o_oval;
wire dut_io_pads_gpio_7_o_oe;
wire dut_io_pads_gpio_7_o_ie;
wire dut_io_pads_gpio_7_o_pue;
wire dut_io_pads_gpio_7_o_ds;
wire dut_io_pads_gpio_8_i_ival;
wire dut_io_pads_gpio_8_o_oval;
wire dut_io_pads_gpio_8_o_oe;
wire dut_io_pads_gpio_8_o_ie;
wire dut_io_pads_gpio_8_o_pue;
wire dut_io_pads_gpio_8_o_ds;
wire dut_io_pads_gpio_9_i_ival;
wire dut_io_pads_gpio_9_o_oval;
wire dut_io_pads_gpio_9_o_oe;
wire dut_io_pads_gpio_9_o_ie;
wire dut_io_pads_gpio_9_o_pue;
wire dut_io_pads_gpio_9_o_ds;
wire dut_io_pads_gpio_10_i_ival;
wire dut_io_pads_gpio_10_o_oval;
wire dut_io_pads_gpio_10_o_oe;
wire dut_io_pads_gpio_10_o_ie;
wire dut_io_pads_gpio_10_o_pue;
wire dut_io_pads_gpio_10_o_ds;
wire dut_io_pads_gpio_11_i_ival;
wire dut_io_pads_gpio_11_o_oval;
wire dut_io_pads_gpio_11_o_oe;
wire dut_io_pads_gpio_11_o_ie;
wire dut_io_pads_gpio_11_o_pue;
wire dut_io_pads_gpio_11_o_ds;
wire dut_io_pads_gpio_12_i_ival;
wire dut_io_pads_gpio_12_o_oval;
wire dut_io_pads_gpio_12_o_oe;
wire dut_io_pads_gpio_12_o_ie;
wire dut_io_pads_gpio_12_o_pue;
wire dut_io_pads_gpio_12_o_ds;
wire dut_io_pads_gpio_13_i_ival;
wire dut_io_pads_gpio_13_o_oval;
wire dut_io_pads_gpio_13_o_oe;
wire dut_io_pads_gpio_13_o_ie;
wire dut_io_pads_gpio_13_o_pue;
wire dut_io_pads_gpio_13_o_ds;
wire dut_io_pads_gpio_14_i_ival;
wire dut_io_pads_gpio_14_o_oval;
wire dut_io_pads_gpio_14_o_oe;
wire dut_io_pads_gpio_14_o_ie;
wire dut_io_pads_gpio_14_o_pue;
wire dut_io_pads_gpio_14_o_ds;
wire dut_io_pads_gpio_15_i_ival;
wire dut_io_pads_gpio_15_o_oval;
wire dut_io_pads_gpio_15_o_oe;
wire dut_io_pads_gpio_15_o_ie;
wire dut_io_pads_gpio_15_o_pue;
wire dut_io_pads_gpio_15_o_ds;
wire dut_io_pads_gpio_16_i_ival;
wire dut_io_pads_gpio_16_o_oval;
wire dut_io_pads_gpio_16_o_oe;
wire dut_io_pads_gpio_16_o_ie;
wire dut_io_pads_gpio_16_o_pue;
wire dut_io_pads_gpio_16_o_ds;
wire dut_io_pads_gpio_17_i_ival;
wire dut_io_pads_gpio_17_o_oval;
wire dut_io_pads_gpio_17_o_oe;
wire dut_io_pads_gpio_17_o_ie;
wire dut_io_pads_gpio_17_o_pue;
wire dut_io_pads_gpio_17_o_ds;
wire dut_io_pads_gpio_18_i_ival;
wire dut_io_pads_gpio_18_o_oval;
wire dut_io_pads_gpio_18_o_oe;
wire dut_io_pads_gpio_18_o_ie;
wire dut_io_pads_gpio_18_o_pue;
wire dut_io_pads_gpio_18_o_ds;
wire dut_io_pads_gpio_19_i_ival;
wire dut_io_pads_gpio_19_o_oval;
wire dut_io_pads_gpio_19_o_oe;
wire dut_io_pads_gpio_19_o_ie;
wire dut_io_pads_gpio_19_o_pue;
wire dut_io_pads_gpio_19_o_ds;
wire dut_io_pads_gpio_20_i_ival;
wire dut_io_pads_gpio_20_o_oval;
wire dut_io_pads_gpio_20_o_oe;
wire dut_io_pads_gpio_20_o_ie;
wire dut_io_pads_gpio_20_o_pue;
wire dut_io_pads_gpio_20_o_ds;
wire dut_io_pads_gpio_21_i_ival;
wire dut_io_pads_gpio_21_o_oval;
wire dut_io_pads_gpio_21_o_oe;
wire dut_io_pads_gpio_21_o_ie;
wire dut_io_pads_gpio_21_o_pue;
wire dut_io_pads_gpio_21_o_ds;
wire dut_io_pads_gpio_22_i_ival;
wire dut_io_pads_gpio_22_o_oval;
wire dut_io_pads_gpio_22_o_oe;
wire dut_io_pads_gpio_22_o_ie;
wire dut_io_pads_gpio_22_o_pue;
wire dut_io_pads_gpio_22_o_ds;
wire dut_io_pads_gpio_23_i_ival;
wire dut_io_pads_gpio_23_o_oval;
wire dut_io_pads_gpio_23_o_oe;
wire dut_io_pads_gpio_23_o_ie;
wire dut_io_pads_gpio_23_o_pue;
wire dut_io_pads_gpio_23_o_ds;
wire dut_io_pads_gpio_24_i_ival;
wire dut_io_pads_gpio_24_o_oval;
wire dut_io_pads_gpio_24_o_oe;
wire dut_io_pads_gpio_24_o_ie;
wire dut_io_pads_gpio_24_o_pue;
wire dut_io_pads_gpio_24_o_ds;
wire dut_io_pads_gpio_25_i_ival;
wire dut_io_pads_gpio_25_o_oval;
wire dut_io_pads_gpio_25_o_oe;
wire dut_io_pads_gpio_25_o_ie;
wire dut_io_pads_gpio_25_o_pue;
wire dut_io_pads_gpio_25_o_ds;
wire dut_io_pads_gpio_26_i_ival;
wire dut_io_pads_gpio_26_o_oval;
wire dut_io_pads_gpio_26_o_oe;
wire dut_io_pads_gpio_26_o_ie;
wire dut_io_pads_gpio_26_o_pue;
wire dut_io_pads_gpio_26_o_ds;
wire dut_io_pads_gpio_27_i_ival;
wire dut_io_pads_gpio_27_o_oval;
wire dut_io_pads_gpio_27_o_oe;
wire dut_io_pads_gpio_27_o_ie;
wire dut_io_pads_gpio_27_o_pue;
wire dut_io_pads_gpio_27_o_ds;
wire dut_io_pads_gpio_28_i_ival;
wire dut_io_pads_gpio_28_o_oval;
wire dut_io_pads_gpio_28_o_oe;
wire dut_io_pads_gpio_28_o_ie;
wire dut_io_pads_gpio_28_o_pue;
wire dut_io_pads_gpio_28_o_ds;
wire dut_io_pads_gpio_29_i_ival;
wire dut_io_pads_gpio_29_o_oval;
wire dut_io_pads_gpio_29_o_oe;
wire dut_io_pads_gpio_29_o_ie;
wire dut_io_pads_gpio_29_o_pue;
wire dut_io_pads_gpio_29_o_ds;
wire dut_io_pads_qspi_sck_i_ival;
wire dut_io_pads_qspi_sck_o_oval;
wire dut_io_pads_qspi_sck_o_oe;
wire dut_io_pads_qspi_sck_o_ie;
wire dut_io_pads_qspi_sck_o_pue;
wire dut_io_pads_qspi_sck_o_ds;
wire dut_io_pads_qspi_dq_0_i_ival;
wire dut_io_pads_qspi_dq_0_o_oval;
wire dut_io_pads_qspi_dq_0_o_oe;
wire dut_io_pads_qspi_dq_0_o_ie;
wire dut_io_pads_qspi_dq_0_o_pue;
wire dut_io_pads_qspi_dq_0_o_ds;
wire dut_io_pads_qspi_dq_1_i_ival;
wire dut_io_pads_qspi_dq_1_o_oval;
wire dut_io_pads_qspi_dq_1_o_oe;
wire dut_io_pads_qspi_dq_1_o_ie;
wire dut_io_pads_qspi_dq_1_o_pue;
wire dut_io_pads_qspi_dq_1_o_ds;
wire dut_io_pads_qspi_dq_2_i_ival;
wire dut_io_pads_qspi_dq_2_o_oval;
wire dut_io_pads_qspi_dq_2_o_oe;
wire dut_io_pads_qspi_dq_2_o_ie;
wire dut_io_pads_qspi_dq_2_o_pue;
wire dut_io_pads_qspi_dq_2_o_ds;
wire dut_io_pads_qspi_dq_3_i_ival;
wire dut_io_pads_qspi_dq_3_o_oval;
wire dut_io_pads_qspi_dq_3_o_oe;
wire dut_io_pads_qspi_dq_3_o_ie;
wire dut_io_pads_qspi_dq_3_o_pue;
wire dut_io_pads_qspi_dq_3_o_ds;
wire dut_io_pads_qspi_cs_0_i_ival;
wire dut_io_pads_qspi_cs_0_o_oval;
wire dut_io_pads_qspi_cs_0_o_oe;
wire dut_io_pads_qspi_cs_0_o_ie;
wire dut_io_pads_qspi_cs_0_o_pue;
wire dut_io_pads_qspi_cs_0_o_ds;
wire dut_io_pads_aon_erst_n_i_ival;
wire dut_io_pads_aon_erst_n_o_oval;
wire dut_io_pads_aon_erst_n_o_oe;
wire dut_io_pads_aon_erst_n_o_ie;
wire dut_io_pads_aon_erst_n_o_pue;
wire dut_io_pads_aon_erst_n_o_ds;
wire dut_io_pads_aon_lfextclk_i_ival;
wire dut_io_pads_aon_lfextclk_o_oval;
wire dut_io_pads_aon_lfextclk_o_oe;
wire dut_io_pads_aon_lfextclk_o_ie;
wire dut_io_pads_aon_lfextclk_o_pue;
wire dut_io_pads_aon_lfextclk_o_ds;
//=================================================
// Clock & Reset
wire SRST_n; // From FTDI Chip
mmcm ip_mmcm
(
.clk_in1(CLK100MHZ),
.clk_out1(clk_out1), // 8.388 MHz = 32.768 kHz * 256
.clk_out2(hfclk), // 65 MHz
.resetn(ck_rst),
.locked(mmcm_locked)
);
wire slowclk;
clkdivider slowclkgen
(
.clk(clk_out1),
.reset(~mmcm_locked),
.clk_out(slowclk)
);
reset_sys ip_reset_sys
(
.slowest_sync_clk(clk_out1),
.ext_reset_in(ck_rst & SRST_n), // Active-low
.aux_reset_in(1'b1),
.mb_debug_sys_rst(1'b0),
.dcm_locked(mmcm_locked),
.mb_reset(reset_core),
.bus_struct_reset(reset_bus),
.peripheral_reset(reset_periph),
.interconnect_aresetn(reset_intcon_n),
.peripheral_aresetn(reset_periph_n)
);
//=================================================
// SPI Interface
wire [3:0] qspi_ui_dq_o, qspi_ui_dq_oe;
wire [3:0] qspi_ui_dq_i;
PULLUP qspi_pullup[3:0]
(
.O(qspi_dq)
);
IOBUF qspi_iobuf[3:0]
(
.IO(qspi_dq),
.O(qspi_ui_dq_i),
.I(qspi_ui_dq_o),
.T(~qspi_ui_dq_oe)
);
//=================================================
// IOBUF instantiation for GPIOs.
// Convert an inout to input, output, and drive wires.
// _o = output wire
// _io = inout (for external connection)
// _i = input data
// _oe = output enabled (true to drive, false to tristate)
// TODO: automatically generate these
wire btn_0_o;
wire btn_0_io;
wire btn_0_i;
wire btn_0_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_btn_0
(
.O(btn_0_o),
.IO(btn_0_io),
.I(btn_0_i),
.T(~btn_0_oe)
);
wire btn_1_o;
wire btn_1_io;
wire btn_1_i;
wire btn_1_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_btn_1
(
.O(btn_1_o),
.IO(btn_1_io),
.I(btn_1_i),
.T(~btn_1_oe)
);
wire btn_2_o;
wire btn_2_io;
wire btn_2_i;
wire btn_2_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_btn_2
(
.O(btn_2_o),
.IO(btn_2_io),
.I(btn_2_i),
.T(~btn_2_oe)
);
wire btn_3_o;
wire btn_3_io;
wire btn_3_i;
wire btn_3_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_btn_3
(
.O(btn_3_o),
.IO(btn_3_io),
.I(btn_3_i),
.T(~btn_3_oe)
);
wire ja_0_o;
wire ja_0_io;
wire ja_0_i;
wire ja_0_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_ja_0
(
.O(ja_0_o),
.IO(ja_0_io),
.I(ja_0_i),
.T(~ja_0_oe)
);
wire ja_1_o;
wire ja_1_io;
wire ja_1_i;
wire ja_1_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_ja_1
(
.O(ja_1_o),
.IO(ja_1_io),
.I(ja_1_i),
.T(~ja_1_oe)
);
wire ja_2_o;
wire ja_2_io;
wire ja_2_i;
wire ja_2_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_ja_2
(
.O(ja_2_o),
.IO(ja_2_io),
.I(ja_2_i),
.T(~ja_2_oe)
);
wire ja_3_o;
wire ja_3_io;
wire ja_3_i;
wire ja_3_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_ja_3
(
.O(ja_3_o),
.IO(ja_3_io),
.I(ja_3_i),
.T(~ja_3_oe)
);
wire ja_4_o;
wire ja_4_io;
wire ja_4_i;
wire ja_4_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_ja_4
(
.O(ja_4_o),
.IO(ja_4_io),
.I(ja_4_i),
.T(~ja_4_oe)
);
wire ja_5_o;
wire ja_5_io;
wire ja_5_i;
wire ja_5_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_ja_5
(
.O(ja_5_o),
.IO(ja_5_io),
.I(ja_5_i),
.T(~ja_5_oe)
);
wire ja_6_o;
wire ja_6_io;
wire ja_6_i;
wire ja_6_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_ja_6
(
.O(ja_6_o),
.IO(ja_6_io),
.I(ja_6_i),
.T(~ja_6_oe)
);
wire ja_7_o;
wire ja_7_io;
wire ja_7_i;
wire ja_7_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_ja_7
(
.O(ja_7_o),
.IO(ja_7_io),
.I(ja_7_i),
.T(~ja_7_oe)
);
wire jd_0_o;
wire jd_0_io;
wire jd_0_i;
wire jd_0_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_jd_0
(
.O(jd_0_o),
.IO(jd_0_io),
.I(jd_0_i),
.T(~jd_0_oe)
);
wire jd_1_o;
wire jd_1_io;
wire jd_1_i;
wire jd_1_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_jd_1
(
.O(jd_1_o),
.IO(jd_1_io),
.I(jd_1_i),
.T(~jd_1_oe)
);
wire jd_2_o;
wire jd_2_io;
wire jd_2_i;
wire jd_2_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_jd_2
(
.O(jd_2_o),
.IO(jd_2_io),
.I(jd_2_i),
.T(~jd_2_oe)
);
wire jd_3_o;
wire jd_3_io;
wire jd_3_i;
wire jd_3_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_jd_3
(
.O(jd_3_o),
.IO(jd_3_io),
.I(jd_3_i),
.T(~jd_3_oe)
);
wire jd_4_o;
wire jd_4_io;
wire jd_4_i;
wire jd_4_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_jd_4
(
.O(jd_4_o),
.IO(jd_4_io),
.I(jd_4_i),
.T(~jd_4_oe)
);
wire jd_5_o;
wire jd_5_io;
wire jd_5_i;
wire jd_5_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_jd_5
(
.O(jd_5_o),
.IO(jd_5_io),
.I(jd_5_i),
.T(~jd_5_oe)
);
wire jd_6_o;
wire jd_6_io;
wire jd_6_i;
wire jd_6_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_jd_6
(
.O(jd_6_o),
.IO(jd_6_io),
.I(jd_6_i),
.T(~jd_6_oe)
);
wire jd_7_o;
wire jd_7_io;
wire jd_7_i;
wire jd_7_oe;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_jd_7
(
.O(jd_7_o),
.IO(jd_7_io),
.I(jd_7_i),
.T(~jd_7_oe)
);
// Buffers for UART.
// Strictly speaking, they don't need separate buffers, but having them won't
// hurt.
wire uart_rxd_out;
OBUF
#(
.IOSTANDARD("DEFAULT"),
.SLEW("FAST")
)
OBUF_uart_rxd_out
(
.O(uart_rxd_out_pad),
.I(uart_rxd_out)
);
wire uart_txd_in;
IBUF
#(
.IBUF_LOW_PWR("FALSE"),
.IOSTANDARD("DEFAULT")
)
IBUF_uart_txd_in
(
.O(uart_txd_in),
.I(uart_txd_in_pad)
);
wire gpio_0;
wire gpio_1;
wire gpio_2;
wire gpio_3;
wire gpio_4;
wire gpio_5;
wire gpio_6;
wire gpio_7;
wire gpio_8;
wire gpio_9;
wire gpio_10;
wire gpio_11;
wire gpio_12;
wire gpio_13;
wire gpio_14;
wire gpio_15;
wire gpio_16;
wire gpio_17;
wire gpio_18;
wire gpio_19;
wire gpio_20;
wire gpio_21;
wire gpio_22;
wire gpio_23;
wire gpio_25;
wire gpio_26;
wire gpio_27;
wire gpio_28;
wire gpio_29;
wire gpio_30;
wire gpio_31;
wire iobuf_gpio_0_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_0
(
.O(iobuf_gpio_0_o),
.IO(gpio_0),
.I(dut_io_pads_gpio_0_o_oval),
.T(~dut_io_pads_gpio_0_o_oe)
);
assign dut_io_pads_gpio_0_i_ival = iobuf_gpio_0_o & dut_io_pads_gpio_0_o_ie;
wire iobuf_gpio_1_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_1
(
.O(iobuf_gpio_1_o),
.IO(gpio_1),
.I(dut_io_pads_gpio_1_o_oval),
.T(~dut_io_pads_gpio_1_o_oe)
);
assign dut_io_pads_gpio_1_i_ival = iobuf_gpio_1_o & dut_io_pads_gpio_1_o_ie;
wire iobuf_gpio_2_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_2
(
.O(iobuf_gpio_2_o),
.IO(gpio_2),
.I(dut_io_pads_gpio_2_o_oval),
.T(~dut_io_pads_gpio_2_o_oe)
);
assign dut_io_pads_gpio_2_i_ival = iobuf_gpio_2_o & dut_io_pads_gpio_2_o_ie;
wire iobuf_gpio_3_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_3
(
.O(iobuf_gpio_3_o),
.IO(gpio_3),
.I(dut_io_pads_gpio_3_o_oval),
.T(~dut_io_pads_gpio_3_o_oe)
);
assign dut_io_pads_gpio_3_i_ival = iobuf_gpio_3_o & dut_io_pads_gpio_3_o_ie;
wire iobuf_gpio_4_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_4
(
.O(iobuf_gpio_4_o),
.IO(gpio_4),
.I(dut_io_pads_gpio_4_o_oval),
.T(~dut_io_pads_gpio_4_o_oe)
);
assign dut_io_pads_gpio_4_i_ival = iobuf_gpio_4_o & dut_io_pads_gpio_4_o_ie;
wire iobuf_gpio_5_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_5
(
.O(iobuf_gpio_5_o),
.IO(gpio_5),
.I(dut_io_pads_gpio_5_o_oval),
.T(~dut_io_pads_gpio_5_o_oe)
);
assign dut_io_pads_gpio_5_i_ival = iobuf_gpio_5_o & dut_io_pads_gpio_5_o_ie;
assign dut_io_pads_gpio_6_i_ival = 1'b0;
assign dut_io_pads_gpio_7_i_ival = 1'b0;
assign dut_io_pads_gpio_8_i_ival = 1'b0;
wire iobuf_gpio_9_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_9
(
.O(iobuf_gpio_9_o),
.IO(gpio_9),
.I(dut_io_pads_gpio_9_o_oval),
.T(~dut_io_pads_gpio_9_o_oe)
);
assign dut_io_pads_gpio_9_i_ival = iobuf_gpio_9_o & dut_io_pads_gpio_9_o_ie;
wire iobuf_gpio_10_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_10
(
.O(iobuf_gpio_10_o),
.IO(gpio_10),
.I(dut_io_pads_gpio_10_o_oval),
.T(~dut_io_pads_gpio_10_o_oe)
);
assign dut_io_pads_gpio_10_i_ival = iobuf_gpio_10_o & dut_io_pads_gpio_10_o_ie;
wire iobuf_gpio_11_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_11
(
.O(iobuf_gpio_11_o),
.IO(gpio_11),
.I(dut_io_pads_gpio_11_o_oval),
.T(~dut_io_pads_gpio_11_o_oe)
);
assign dut_io_pads_gpio_11_i_ival = iobuf_gpio_11_o & dut_io_pads_gpio_11_o_ie;
wire iobuf_gpio_12_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_12
(
.O(iobuf_gpio_12_o),
.IO(gpio_12),
.I(dut_io_pads_gpio_12_o_oval),
.T(~dut_io_pads_gpio_12_o_oe)
);
assign dut_io_pads_gpio_12_i_ival = iobuf_gpio_12_o & dut_io_pads_gpio_12_o_ie;
wire iobuf_gpio_13_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_13
(
.O(iobuf_gpio_13_o),
.IO(gpio_13),
.I(dut_io_pads_gpio_13_o_oval),
.T(~dut_io_pads_gpio_13_o_oe)
);
assign dut_io_pads_gpio_13_i_ival = iobuf_gpio_13_o & dut_io_pads_gpio_13_o_ie;
wire iobuf_gpio_14_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_14
(
.O(iobuf_gpio_14_o),
.IO(gpio_14),
.I(dut_io_pads_gpio_14_o_oval),
.T(~dut_io_pads_gpio_14_o_oe)
);
assign dut_io_pads_gpio_14_i_ival = iobuf_gpio_14_o & dut_io_pads_gpio_14_o_ie;
wire iobuf_gpio_18_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_18
(
.O(iobuf_gpio_18_o),
.IO(gpio_18),
.I(dut_io_pads_gpio_18_o_oval),
.T(~dut_io_pads_gpio_18_o_oe)
);
assign dut_io_pads_gpio_18_i_ival = iobuf_gpio_18_o & dut_io_pads_gpio_18_o_ie;
wire iobuf_gpio_19_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_19
(
.O(iobuf_gpio_19_o),
.IO(gpio_19),
.I(dut_io_pads_gpio_19_o_oval),
.T(~dut_io_pads_gpio_19_o_oe)
);
assign dut_io_pads_gpio_19_i_ival = iobuf_gpio_19_o & dut_io_pads_gpio_19_o_ie;
wire iobuf_gpio_20_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_20
(
.O(iobuf_gpio_20_o),
.IO(gpio_20),
.I(dut_io_pads_gpio_20_o_oval),
.T(~dut_io_pads_gpio_20_o_oe)
);
assign dut_io_pads_gpio_20_i_ival = iobuf_gpio_20_o & dut_io_pads_gpio_20_o_ie;
wire iobuf_gpio_21_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_21
(
.O(iobuf_gpio_21_o),
.IO(gpio_21),
.I(dut_io_pads_gpio_21_o_oval),
.T(~dut_io_pads_gpio_21_o_oe)
);
assign dut_io_pads_gpio_21_i_ival = iobuf_gpio_21_o & dut_io_pads_gpio_21_o_ie;
wire iobuf_gpio_22_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_22
(
.O(iobuf_gpio_22_o),
.IO(gpio_22),
.I(dut_io_pads_gpio_22_o_oval),
.T(~dut_io_pads_gpio_22_o_oe)
);
assign dut_io_pads_gpio_22_i_ival = iobuf_gpio_22_o & dut_io_pads_gpio_22_o_ie;
wire iobuf_gpio_23_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_23
(
.O(iobuf_gpio_23_o),
.IO(gpio_23),
.I(dut_io_pads_gpio_23_o_oval),
.T(~dut_io_pads_gpio_23_o_oe)
);
assign dut_io_pads_gpio_23_i_ival = iobuf_gpio_23_o & dut_io_pads_gpio_23_o_ie;
wire iobuf_gpio_25_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_25
(
.O(iobuf_gpio_25_o),
.IO(gpio_25),
.I(dut_io_pads_gpio_25_o_oval),
.T(~dut_io_pads_gpio_25_o_oe)
);
assign dut_io_pads_gpio_25_i_ival = iobuf_gpio_25_o & dut_io_pads_gpio_25_o_ie;
wire iobuf_gpio_26_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_26
(
.O(iobuf_gpio_26_o),
.IO(gpio_26),
.I(dut_io_pads_gpio_26_o_oval),
.T(~dut_io_pads_gpio_26_o_oe)
);
assign dut_io_pads_gpio_26_i_ival = iobuf_gpio_26_o & dut_io_pads_gpio_26_o_ie;
wire iobuf_gpio_27_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_27
(
.O(iobuf_gpio_27_o),
.IO(gpio_27),
.I(dut_io_pads_gpio_27_o_oval),
.T(~dut_io_pads_gpio_27_o_oe)
);
assign dut_io_pads_gpio_27_i_ival = iobuf_gpio_27_o & dut_io_pads_gpio_27_o_ie;
wire iobuf_gpio_28_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_28
(
.O(iobuf_gpio_28_o),
.IO(gpio_28),
.I(dut_io_pads_gpio_28_o_oval),
.T(~dut_io_pads_gpio_28_o_oe)
);
assign dut_io_pads_gpio_28_i_ival = iobuf_gpio_28_o & dut_io_pads_gpio_28_o_ie;
wire iobuf_gpio_29_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_29
(
.O(iobuf_gpio_29_o),
.IO(gpio_29),
.I(dut_io_pads_gpio_29_o_oval),
.T(~dut_io_pads_gpio_29_o_oe)
);
assign dut_io_pads_gpio_29_i_ival = iobuf_gpio_29_o & dut_io_pads_gpio_29_o_ie;
//=================================================
// Assignment of IOBUF "IO" pins to package pins
// Pins IO0-IO13
// Shield header row 0: PD0-PD7
// FTDI UART TX/RX are not connected to ck_io[1,2]
// the way they are on Arduino boards. We copy outgoing
// data to both places, switch 3 (sw[3]) determines whether
// input to UART comes from FTDI chip or gpio_16 (shield pin PD0)
assign ck_io[0] = gpio_16; // UART0 RX
assign ck_io[1] = gpio_17; // UART0 TX
assign ck_io[2] = gpio_18;
assign ck_io[3] = gpio_19; // PWM1(1)
assign ck_io[4] = gpio_20; // PWM1(0)
assign ck_io[5] = gpio_21; // PWM1(2)
assign ck_io[6] = gpio_22; // PWM1(3)
assign ck_io[7] = gpio_23;
// Header row 1: PB0-PB5
assign ck_io[8] = gpio_0; // PWM0(0)
assign ck_io[9] = gpio_1; // PWM0(1)
assign ck_io[10] = gpio_2; // SPI1 CS(0) / PWM0(2)
assign ck_io[11] = gpio_3; // SPI1 MOSI / PWM0(3)
assign ck_io[12] = gpio_4; // SPI1 MISO
assign ck_io[13] = gpio_5; // SPI1 SCK
// Header row 3: A0-A5 (we don't support using them as analog inputs)
// just treat them as regular digital GPIOs
assign ck_io[14] = uart_txd_in; //gpio_9; // A0 = <unconnected> CS(1)
assign ck_io[15] = gpio_9; // A1 = CS(2)
assign ck_io[16] = gpio_10; // A2 = CS(3) / PWM2(0)
assign ck_io[17] = gpio_11; // A3 = PWM2(1)
assign ck_io[18] = gpio_12; // A4 = PWM2(2) / SDA
assign ck_io[19] = gpio_13; // A5 = PWM2(3) / SCL
assign btn_0 = btn_0_io;
assign btn_1 = btn_1_io;
assign btn_2 = btn_2_io;
assign btn_3 = btn_3_io;
assign ja_0 = ja_0_io;
assign ja_1 = ja_1_io;
assign ja_2 = ja_2_io;
assign ja_3 = ja_3_io;
assign ja_4 = ja_4_io;
assign ja_5 = ja_5_io;
assign ja_6 = ja_6_io;
assign ja_7 = ja_7_io;
assign jd_0 = jd_0_io;
assign jd_1 = jd_1_io;
assign jd_2 = jd_2_io;
assign jd_3 = jd_3_io;
assign jd_4 = jd_4_io;
assign jd_5 = jd_5_io;
assign jd_6 = jd_6_io;
assign jd_7 = jd_7_io;
// SPI2 pins mapped to 6 pin ICSP connector (standard on later arduinos)
// These are connected to some extra GPIO pads not connected on the HiFive1
// board
assign ck_ss = gpio_26;
assign ck_mosi = gpio_27;
assign ck_miso = gpio_28;
assign ck_sck = gpio_29;
// Instantiate the top-level Verilog module here.
// Do not alter the following line (auto-generated by PLSI).
// ***PLSI_REPLACE_ME***
// End auto-generated section.
// Assign reasonable values to otherwise unconnected inputs to chip top
assign dut_io_pads_aon_erst_n_i_ival = ~reset_periph;
assign dut_io_pads_aon_lfextclk_i_ival = slowclk;
assign dut_io_pads_aon_pmu_vddpaden_i_ival = 1'b1;
assign qspi_cs = dut_io_pads_qspi_cs_0_o_oval;
assign qspi_ui_dq_o = {
dut_io_pads_qspi_dq_3_o_oval,
dut_io_pads_qspi_dq_2_o_oval,
dut_io_pads_qspi_dq_1_o_oval,
dut_io_pads_qspi_dq_0_o_oval
};
assign qspi_ui_dq_oe = {
dut_io_pads_qspi_dq_3_o_oe,
dut_io_pads_qspi_dq_2_o_oe,
dut_io_pads_qspi_dq_1_o_oe,
dut_io_pads_qspi_dq_0_o_oe
};
assign dut_io_pads_qspi_dq_0_i_ival = qspi_ui_dq_i[0];
assign dut_io_pads_qspi_dq_1_i_ival = qspi_ui_dq_i[1];
assign dut_io_pads_qspi_dq_2_i_ival = qspi_ui_dq_i[2];
assign dut_io_pads_qspi_dq_3_i_ival = qspi_ui_dq_i[3];
assign qspi_sck = dut_io_pads_qspi_sck_o_oval;
endmodule
// Divide clock by 256, used to generate 32.768 kHz clock for AON block
module clkdivider
(
input wire clk,
input wire reset,
output reg clk_out
);
reg [7:0] counter;
always @(posedge clk)
begin
if (reset)
begin
counter <= 8'd0;
clk_out <= 1'b0;
end
else if (counter == 8'hff)
begin
counter <= 8'd0;
clk_out <= ~clk_out;
end
else
begin
counter <= counter+1;
end
end
endmodule
|
`default_nettype none
module lcdc(
input wire clk, // clk491520
input wire rst,
output wire [8:0] x_o,
output wire [6:0] y_o,
output wire in_vsync_o,
output wire in_hsync_o,
output wire pop_o,
input wire [5:0] r_i,
input wire [5:0] g_i,
input wire [5:0] b_i,
input wire ack_i,
output wire [5:0] lcd_r,
output wire [5:0] lcd_g,
output wire [5:0] lcd_b,
output wire lcd_vsync,
output wire lcd_hsync,
output wire lcd_nclk,
output wire lcd_de);
reg [3:0] counter_ff;
always @(posedge clk) begin
if (rst) begin
counter_ff <= 4'h0;
end else begin
counter_ff <= counter_ff + 1;
end
end
/*
case (counter_ff) begin
4'h0: // send req
4'h1:
4'h2:
4'h3:
4'h4:
4'h5:
4'h6:
4'h7:
4'h8:
4'h9:
4'ha:
4'hb:
4'hc:
4'hd: // update x
4'he: // update y
4'hf: // update data
endcase
*/
reg send_req_ff;
reg update_x_ff;
reg update_y_ff;
reg update_data_ff;
always @(posedge clk) begin
if (rst) begin
send_req_ff <= 1'b0;
update_x_ff <= 1'b0;
update_y_ff <= 1'b0;
update_data_ff <= 1'b0;
end else begin
if (counter_ff == 4'hf)
send_req_ff <= 1'b1;
else
send_req_ff <= 1'b0;
if (counter_ff == 4'hc)
update_x_ff <= 1'b1;
else
update_x_ff <= 1'b0;
if (counter_ff == 4'hd)
update_y_ff <= 1'b1;
else
update_y_ff <= 1'b0;
if (counter_ff == 4'he)
update_data_ff <= 1'b1;
else
update_data_ff <= 1'b0;
end
end
wire send_req = send_req_ff;
wire update_x = update_x_ff;
wire update_y = update_y_ff;
wire update_data = update_data_ff;
reg lcd_nclk_ff;
always @(posedge clk) begin
if (rst)
lcd_nclk_ff <= 1'b0;
else begin
if (counter_ff < 4'h8)
lcd_nclk_ff <= 1'b1;
else
lcd_nclk_ff <= 1'b0;
end
end
reg [8:0] curr_x_ff;
reg in_hsync_ff;
always @(posedge clk) begin
if (rst) begin
curr_x_ff <= 9'd400;
in_hsync_ff <= 1'b0;
end else begin
if (update_x) begin
if (curr_x_ff == 9'd506) begin
curr_x_ff <= 9'd000;
in_hsync_ff <= 0;
end else begin
curr_x_ff <= curr_x_ff + 1;
in_hsync_ff <= (curr_x_ff >= 9'd400) ? 1'b1 : 1'b0;
end
end
end
end
reg lcd_hsync_ff;
always @(posedge clk) begin
if (rst)
lcd_hsync_ff <= 1'b1;
else begin
if (update_data) begin
if (curr_x_ff == 9'd401)
lcd_hsync_ff <= 1'b0;
else
lcd_hsync_ff <= 1'b1;
end
end
end
reg [6:0] curr_y_ff;
reg in_vsync_ff;
always @(posedge clk) begin
if (rst) begin
curr_y_ff <= 7'd96;
in_vsync_ff <= 1'b0;
end else begin
if (update_y && curr_x_ff == 9'd400) begin
if (curr_y_ff == 7'd111) begin
curr_y_ff <= 7'd0;
in_vsync_ff <= 1'b0;
end else begin
curr_y_ff <= curr_y_ff + 1;
in_vsync_ff <= (curr_y_ff >= 7'd96) ? 1'b1 : 1'b0;
end
end
end
end
reg lcd_vsync_ff;
always @(posedge clk) begin
if (rst)
lcd_vsync_ff <= 1'b1;
else begin
if (update_data) begin
if (curr_y_ff == 7'd97)
lcd_vsync_ff <= 1'b0;
else
lcd_vsync_ff <= 1'b1;
end
end
end
assign x_o = curr_x_ff;
assign y_o = curr_y_ff;
assign in_hsync_o = in_hsync_ff;
assign in_vsync_o = in_vsync_ff;
assign pop_o = send_req;
reg [5:0] lcd_r_pending_ff;
reg [5:0] lcd_g_pending_ff;
reg [5:0] lcd_b_pending_ff;
always @(posedge clk) begin
if (rst) begin
lcd_r_pending_ff <= 6'h00;
lcd_g_pending_ff <= 6'h00;
lcd_b_pending_ff <= 6'h00;
end else if (ack_i) begin
lcd_r_pending_ff <= r_i;
lcd_g_pending_ff <= g_i;
lcd_b_pending_ff <= b_i;
end
end
reg [5:0] lcd_r_ff;
reg [5:0] lcd_g_ff;
reg [5:0] lcd_b_ff;
always @(posedge clk) begin
if (rst) begin
lcd_r_ff <= 6'h00;
lcd_g_ff <= 6'h00;
lcd_b_ff <= 6'h00;
end else if (update_data) begin
lcd_r_ff <= lcd_r_pending_ff;
lcd_g_ff <= lcd_g_pending_ff;
lcd_b_ff <= lcd_b_pending_ff;
end
end
assign lcd_de = 1'b0;
assign lcd_vsync = lcd_vsync_ff;
assign lcd_hsync = lcd_hsync_ff;
assign lcd_nclk = lcd_nclk_ff;
assign lcd_r[5:0] = lcd_r_ff;
assign lcd_g[5:0] = lcd_g_ff;
assign lcd_b[5:0] = lcd_b_ff;
endmodule
module patterngen(
input wire clk, // clk491520
input wire rst,
input wire [8:0] x_i,
input wire [6:0] y_i,
input wire pop_i,
output wire [5:0] r_o,
output wire [5:0] g_o,
output wire [5:0] b_o,
output wire ack_o);
reg [5:0] r_ff;
reg [5:0] g_ff;
reg [5:0] b_ff;
reg ack_ff;
always @(posedge clk) begin
if (rst) begin
r_ff <= 6'h00;
g_ff <= 6'h00;
b_ff <= 6'h00;
ack_ff <= 1'b0;
end else if (pop_i) begin
if (y_i == 7'd1)
r_ff <= 6'h3f;
else
r_ff <= 6'h00;
if (y_i == 7'd0)
g_ff <= 6'h3f;
else
g_ff <= 6'h00;
if (y_i == 7'd95)
b_ff <= 6'h3f;
else
b_ff <= 6'h00;
ack_ff <= 1'b1;
end else
ack_ff <= 1'b0;
end
assign r_o = r_ff;
assign g_o = g_ff;
assign b_o = b_ff;
assign ack_o = ack_ff;
endmodule
`default_nettype wire
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_p0_addr_cmd_pads(
reset_n,
reset_n_afi_clk,
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
phy_ddio_addr_cmd_clk,
phy_ddio_address,
dll_delayctrl_in,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_reset_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_reset_n,
phy_mem_ck,
phy_mem_ck_n
);
parameter DEVICE_FAMILY = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter DLL_WIDTH = "";
input reset_n;
input reset_n_afi_clk;
input pll_afi_clk;
input pll_mem_clk;
input pll_write_clk;
input phy_ddio_addr_cmd_clk;
input [DLL_WIDTH-1:0] dll_delayctrl_in;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output phy_mem_reset_n;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
wire [MEM_ADDRESS_WIDTH-1:0] address_l;
wire [MEM_ADDRESS_WIDTH-1:0] address_h;
wire [MEM_CHIP_SELECT_WIDTH-1:0] cs_n_l;
wire [MEM_CHIP_SELECT_WIDTH-1:0] cs_n_h;
wire [MEM_CLK_EN_WIDTH-1:0] cke_l;
wire [MEM_CLK_EN_WIDTH-1:0] cke_h;
wire [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address_hr = phy_ddio_address;
wire [AFI_BANK_WIDTH-1:0] phy_ddio_bank_hr = phy_ddio_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n_hr = phy_ddio_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke_hr = phy_ddio_cke;
wire [AFI_ODT_WIDTH-1:0] phy_ddio_odt_hr = phy_ddio_odt;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n_hr = phy_ddio_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n_hr = phy_ddio_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n_hr = phy_ddio_we_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n_hr = phy_ddio_reset_n;
wire [MEM_ADDRESS_WIDTH-1:0] phy_ddio_address_l;
wire [MEM_ADDRESS_WIDTH-1:0] phy_ddio_address_h;
wire [MEM_BANK_WIDTH-1:0] phy_ddio_bank_l;
wire [MEM_BANK_WIDTH-1:0] phy_ddio_bank_h;
wire [MEM_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n_l;
wire [MEM_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n_h;
wire [MEM_CLK_EN_WIDTH-1:0] phy_ddio_cke_l;
wire [MEM_CLK_EN_WIDTH-1:0] phy_ddio_cke_h;
wire [MEM_ODT_WIDTH-1:0] phy_ddio_odt_l;
wire [MEM_ODT_WIDTH-1:0] phy_ddio_odt_h;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_ras_n_l;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_ras_n_h;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_cas_n_l;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_cas_n_h;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_we_n_l;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_we_n_h;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_reset_n_l;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_reset_n_h;
// each signal has a high and a low portion,
// connecting to the high and low inputs of the DDIO_OUT,
// for the purpose of creating double data rate
assign phy_ddio_address_l = phy_ddio_address_hr[MEM_ADDRESS_WIDTH-1:0];
assign phy_ddio_bank_l = phy_ddio_bank_hr[MEM_BANK_WIDTH-1:0];
assign phy_ddio_cke_l = phy_ddio_cke_hr[MEM_CLK_EN_WIDTH-1:0];
assign phy_ddio_odt_l = phy_ddio_odt_hr[MEM_ODT_WIDTH-1:0];
assign phy_ddio_cs_n_l = phy_ddio_cs_n_hr[MEM_CHIP_SELECT_WIDTH-1:0];
assign phy_ddio_we_n_l = phy_ddio_we_n_hr[MEM_CONTROL_WIDTH-1:0];
assign phy_ddio_ras_n_l = phy_ddio_ras_n_hr[MEM_CONTROL_WIDTH-1:0];
assign phy_ddio_cas_n_l = phy_ddio_cas_n_hr[MEM_CONTROL_WIDTH-1:0];
assign phy_ddio_reset_n_l = phy_ddio_reset_n_hr[MEM_CONTROL_WIDTH-1:0];
assign phy_ddio_address_h = phy_ddio_address_hr[2*MEM_ADDRESS_WIDTH-1:MEM_ADDRESS_WIDTH];
assign phy_ddio_bank_h = phy_ddio_bank_hr[2*MEM_BANK_WIDTH-1:MEM_BANK_WIDTH];
assign phy_ddio_cke_h = phy_ddio_cke_hr[2*MEM_CLK_EN_WIDTH-1:MEM_CLK_EN_WIDTH];
assign phy_ddio_odt_h = phy_ddio_odt_hr[2*MEM_ODT_WIDTH-1:MEM_ODT_WIDTH];
assign phy_ddio_cs_n_h = phy_ddio_cs_n_hr[2*MEM_CHIP_SELECT_WIDTH-1:MEM_CHIP_SELECT_WIDTH];
assign phy_ddio_we_n_h = phy_ddio_we_n_hr[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
assign phy_ddio_ras_n_h = phy_ddio_ras_n_hr[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
assign phy_ddio_cas_n_h = phy_ddio_cas_n_hr[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
assign phy_ddio_reset_n_h = phy_ddio_reset_n_hr[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
assign address_l = phy_ddio_address_l;
assign address_h = phy_ddio_address_h;
altddio_out uaddress_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (address_l),
.datain_l (address_h),
.dataout (phy_mem_address),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uaddress_pad.extend_oe_disable = "UNUSED",
uaddress_pad.intended_device_family = DEVICE_FAMILY,
uaddress_pad.invert_output = "OFF",
uaddress_pad.lpm_hint = "UNUSED",
uaddress_pad.lpm_type = "altddio_out",
uaddress_pad.oe_reg = "UNUSED",
uaddress_pad.power_up_high = "OFF",
uaddress_pad.width = MEM_ADDRESS_WIDTH;
altddio_out ubank_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (phy_ddio_bank_l),
.datain_l (phy_ddio_bank_h),
.dataout (phy_mem_bank),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ubank_pad.extend_oe_disable = "UNUSED",
ubank_pad.intended_device_family = DEVICE_FAMILY,
ubank_pad.invert_output = "OFF",
ubank_pad.lpm_hint = "UNUSED",
ubank_pad.lpm_type = "altddio_out",
ubank_pad.oe_reg = "UNUSED",
ubank_pad.power_up_high = "OFF",
ubank_pad.width = MEM_BANK_WIDTH;
assign cs_n_l = phy_ddio_cs_n_l;
assign cs_n_h = phy_ddio_cs_n_h;
altddio_out ucs_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (cs_n_l),
.datain_l (cs_n_h),
.dataout (phy_mem_cs_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ucs_n_pad.extend_oe_disable = "UNUSED",
ucs_n_pad.intended_device_family = DEVICE_FAMILY,
ucs_n_pad.invert_output = "OFF",
ucs_n_pad.lpm_hint = "UNUSED",
ucs_n_pad.lpm_type = "altddio_out",
ucs_n_pad.oe_reg = "UNUSED",
ucs_n_pad.power_up_high = "OFF",
ucs_n_pad.width = MEM_CHIP_SELECT_WIDTH;
assign cke_l = phy_ddio_cke_l;
assign cke_h = phy_ddio_cke_h;
altddio_out ucke_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (cke_l),
.datain_l (cke_h),
.dataout (phy_mem_cke),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ucke_pad.extend_oe_disable = "UNUSED",
ucke_pad.intended_device_family = DEVICE_FAMILY,
ucke_pad.invert_output = "OFF",
ucke_pad.lpm_hint = "UNUSED",
ucke_pad.lpm_type = "altddio_out",
ucke_pad.oe_reg = "UNUSED",
ucke_pad.power_up_high = "OFF",
ucke_pad.width = MEM_CLK_EN_WIDTH;
altddio_out uodt_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (phy_ddio_odt_l),
.datain_l (phy_ddio_odt_h),
.dataout (phy_mem_odt),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uodt_pad.extend_oe_disable = "UNUSED",
uodt_pad.intended_device_family = DEVICE_FAMILY,
uodt_pad.invert_output = "OFF",
uodt_pad.lpm_hint = "UNUSED",
uodt_pad.lpm_type = "altddio_out",
uodt_pad.oe_reg = "UNUSED",
uodt_pad.power_up_high = "OFF",
uodt_pad.width = MEM_ODT_WIDTH;
altddio_out uwe_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (phy_ddio_we_n_l),
.datain_l (phy_ddio_we_n_h),
.dataout (phy_mem_we_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uwe_n_pad.extend_oe_disable = "UNUSED",
uwe_n_pad.intended_device_family = DEVICE_FAMILY,
uwe_n_pad.invert_output = "OFF",
uwe_n_pad.lpm_hint = "UNUSED",
uwe_n_pad.lpm_type = "altddio_out",
uwe_n_pad.oe_reg = "UNUSED",
uwe_n_pad.power_up_high = "OFF",
uwe_n_pad.width = MEM_CONTROL_WIDTH;
altddio_out uras_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (phy_ddio_ras_n_l),
.datain_l (phy_ddio_ras_n_h),
.dataout (phy_mem_ras_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uras_n_pad.extend_oe_disable = "UNUSED",
uras_n_pad.intended_device_family = DEVICE_FAMILY,
uras_n_pad.invert_output = "OFF",
uras_n_pad.lpm_hint = "UNUSED",
uras_n_pad.lpm_type = "altddio_out",
uras_n_pad.oe_reg = "UNUSED",
uras_n_pad.power_up_high = "OFF",
uras_n_pad.width = MEM_CONTROL_WIDTH;
altddio_out ucas_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (phy_ddio_cas_n_l),
.datain_l (phy_ddio_cas_n_h),
.dataout (phy_mem_cas_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ucas_n_pad.extend_oe_disable = "UNUSED",
ucas_n_pad.intended_device_family = DEVICE_FAMILY,
ucas_n_pad.invert_output = "OFF",
ucas_n_pad.lpm_hint = "UNUSED",
ucas_n_pad.lpm_type = "altddio_out",
ucas_n_pad.oe_reg = "UNUSED",
ucas_n_pad.power_up_high = "OFF",
ucas_n_pad.width = MEM_CONTROL_WIDTH;
altddio_out ureset_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (phy_ddio_reset_n_l),
.datain_l (phy_ddio_reset_n_h),
.dataout (phy_mem_reset_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ureset_n_pad.extend_oe_disable = "UNUSED",
ureset_n_pad.intended_device_family = DEVICE_FAMILY,
ureset_n_pad.invert_output = "OFF",
ureset_n_pad.lpm_hint = "UNUSED",
ureset_n_pad.lpm_type = "altddio_out",
ureset_n_pad.oe_reg = "UNUSED",
ureset_n_pad.power_up_high = "OFF",
ureset_n_pad.width = MEM_CONTROL_WIDTH;
wire mem_ck_source;
wire [MEM_CK_WIDTH-1:0] mem_ck;
assign mem_ck_source = pll_mem_clk;
generate
genvar clock_width;
for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
begin: clock_gen
altddio_out umem_ck_pad(
.aclr (1'b0),
.aset (1'b0),
.datain_h (1'b1),
.datain_l (1'b0),
.dataout (mem_ck[clock_width]),
.oe (1'b1),
.outclock (mem_ck_source),
.outclocken (1'b1)
);
defparam
umem_ck_pad.extend_oe_disable = "UNUSED",
umem_ck_pad.intended_device_family = DEVICE_FAMILY,
umem_ck_pad.invert_output = "OFF",
umem_ck_pad.lpm_hint = "UNUSED",
umem_ck_pad.lpm_type = "altddio_out",
umem_ck_pad.oe_reg = "UNUSED",
umem_ck_pad.power_up_high = "OFF",
umem_ck_pad.width = 1;
wire mem_ck_temp;
assign mem_ck_temp = mem_ck[clock_width];
ddr3_s4_uniphy_p0_clock_pair_generator uclk_generator(
.datain (mem_ck_temp),
.dataout (phy_mem_ck[clock_width]),
.dataout_b (phy_mem_ck_n[clock_width])
);
end
endgenerate
endmodule
|
/*!
* <b>Module:</b>sata_phy
* @file sata_phy.v
* @date 2015-07-11
* @author Alexey
*
* @brief phy-level, including oob, clock generation and GTXE2
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* sata_phy.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sata_phy.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
//`include "oob_ctrl.v"
//`include "gtx_wrap.v"
module sata_phy #(
`ifdef USE_DATASCOPE
parameter ADDRESS_BITS = 10, //for datascope
parameter DATASCOPE_START_BIT = 14, // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
parameter DATASCOPE_POST_MEAS = 16, // number of measurements to perform after event
`endif
parameter DATA_BYTE_WIDTH = 4,
parameter ELASTIC_DEPTH = 4, //5, With 4/7 got infrequent overflows!
parameter ELASTIC_OFFSET = 7 // 5 //10
)
(
// initial reset, resets PLL. After pll is locked, an internal sata reset is generated.
input wire extrst,
// sata clk, generated in pll as usrclk2
output wire clk, // 75MHz, bufg
output wire rst,
// reliable clock to source drp and cpll lock det circuits
input wire reliable_clk,
// state
output wire phy_ready,
// tmp output TODO
output wire gtx_ready,
output wire [11:0] debug_cnt,
// top-level ifaces
// ref clk from an external source, shall be connected to pads
input wire extclk_p,
input wire extclk_n,
// sata link data pins
output wire txp_out,
output wire txn_out,
input wire rxp_in,
input wire rxn_in,
// to link layer
output wire [DATA_BYTE_WIDTH * 8 - 1:0] ll_data_out,
output wire [DATA_BYTE_WIDTH - 1:0] ll_charisk_out,
output wire [DATA_BYTE_WIDTH - 1:0] ll_err_out, // TODO!!!
// from link layer
input wire [DATA_BYTE_WIDTH * 8 - 1:0] ll_data_in,
input wire [DATA_BYTE_WIDTH - 1:0] ll_charisk_in,
input set_offline, // electrically idle
input comreset_send, // Not possible yet?
output wire cominit_got,
output wire comwake_got,
// elastic buffer status
output wire rxelsfull,
output wire rxelsempty,
output cplllock_debug,
output usrpll_locked_debug,
output re_aligned, // re-aligned after alignment loss
output xclk, // just to measure frequency to set the local clock
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
output datascope_clk,
output [ADDRESS_BITS-1:0] datascope_waddr,
output datascope_we,
output [31:0] datascope_di,
input datascope_trig, // external trigger event for the datascope
`endif
`ifdef USE_DRP
input drp_rst,
input drp_clk,
input drp_en, // @aclk strobes drp_ad
input drp_we,
input [14:0] drp_addr,
input [15:0] drp_di,
output drp_rdy,
output [15:0] drp_do,
`endif
output [31:0] debug_sata
,output debug_detected_alignp
);
wire [DATA_BYTE_WIDTH * 8 - 1:0] txdata;
wire [DATA_BYTE_WIDTH * 8 - 1:0] rxdata;
wire [DATA_BYTE_WIDTH * 8 - 1:0] rxdata_out;
wire [DATA_BYTE_WIDTH * 8 - 1:0] txdata_in;
wire [DATA_BYTE_WIDTH - 1:0] txcharisk;
wire [DATA_BYTE_WIDTH - 1:0] rxcharisk;
wire [DATA_BYTE_WIDTH - 1:0] txcharisk_in;
wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_out;
wire [DATA_BYTE_WIDTH - 1:0] rxdisperr;
wire [DATA_BYTE_WIDTH - 1:0] rxnotintable;
wire [1:0] txbufstatus;
`ifdef DEBUG_ELASTIC
wire [15:0] dbg_data_cntr; // output[11:0] reg 4 MSBs - got primitives during data receive
`endif
assign ll_err_out = rxdisperr | rxnotintable;
// once gtx_ready -> 1, gtx_configured latches
// after this point it's possible to perform additional resets and reconfigurations by higher-level logic
reg gtx_configured;
// after external rst -> 0, after sata logic resets -> 1
wire sata_reset_done;
wire rxcomwakedet;
wire rxcominitdet;
wire cplllock;
wire txcominit;
wire txcomwake;
wire rxreset;
wire rxelecidle;
wire txelecidle;
wire rxbyteisaligned;
wire txpcsreset_req;
wire recal_tx_done;
wire rxreset_req;
wire rxreset_ack;
wire clk_phase_align_req;
wire clk_phase_align_ack;
wire rxreset_oob;
// elastic buffer status signals TODO
//wire rxelsfull;
//wire rxelsempty;
wire dbg_rxphaligndone;
wire dbg_rx_clocks_aligned;
wire dbg_rxcdrlock;
wire dbg_rxdlysresetdone;
//wire gtx_ready;
assign cominit_got = rxcominitdet; // For AHCI
assign comwake_got = rxcomwakedet; // For AHCI
wire dummy;
oob_ctrl oob_ctrl(
.clk (clk), // input wire // sata clk = usrclk2
.rst (rst), // input wire // reset oob
.gtx_ready (gtx_ready), // input wire // gtx is ready = all resets are done
.debug ({dummy,debug_cnt[10:0]}),
// oob responses
.rxcominitdet_in (rxcominitdet), // input wire
.rxcomwakedet_in (rxcomwakedet), // input wire
.rxelecidle_in (rxelecidle), // input wire
// oob issues
.txcominit (txcominit), // output wire
.txcomwake (txcomwake), // output wire
.txelecidle (txelecidle), // output wire
.txpcsreset_req (txpcsreset_req), // output wire
.recal_tx_done (recal_tx_done), // input wire
.rxreset_req (rxreset_req), // output wire
.rxreset_ack (rxreset_ack), // input wire
.clk_phase_align_req (clk_phase_align_req), // output wire
.clk_phase_align_ack (clk_phase_align_ack), // input wire
.txdata_in (txdata_in), // input[31:0] wire // input data stream (if any data during OOB setting => ignored)
.txcharisk_in (txcharisk_in), // input[3:0] wire // same
.txdata_out (txdata), // output[31:0] wire // output data stream to gtx
.txcharisk_out (txcharisk), // output[3:0] wire // same
.rxdata_in (rxdata[31:0]), // input[31:0] wire // input data from gtx
.rxcharisk_in (rxcharisk[3:0]), // input[3:0] wire // same
.rxdata_out (rxdata_out), // output[31:0] wire // bypassed data from gtx
.rxcharisk_out (rxcharisk_out), // output[3:0]wire // same
.rxbyteisaligned (rxbyteisaligned), // input wire // receiving data is aligned
.phy_ready (phy_ready), // output wire // shows if channel is ready
// To/from AHCI
.set_offline (set_offline), // input
.comreset_send (comreset_send), // input
.re_aligned (re_aligned) // output reg
,.debug_detected_alignp(debug_detected_alignp) // output
);
wire cplllockdetclk; // TODO
wire cpllreset;
wire gtrefclk;
wire rxresetdone;
wire txresetdone;
wire txpcsreset;
wire txreset;
wire txuserrdy;
wire rxuserrdy;
wire txusrclk;
wire txusrclk2;
//wire rxusrclk;
wire rxusrclk2;
wire txp;
wire txn;
wire rxp;
wire rxn;
wire txoutclk; // comes out global from gtx_wrap
wire txpmareset_done;
wire rxeyereset_done;
// tx reset sequence; waves @ ug476 p67
localparam TXPMARESET_TIME = 5'h1;
reg [2:0] txpmareset_cnt;
assign txpmareset_done = txpmareset_cnt == TXPMARESET_TIME;
always @ (posedge gtrefclk)
txpmareset_cnt <= txreset ? 3'h0 : txpmareset_done ? txpmareset_cnt : txpmareset_cnt + 1'b1;
// rx reset sequence; waves @ ug476 p77
localparam RXPMARESET_TIME = 5'h11;
localparam RXCDRPHRESET_TIME = 5'h1;
localparam RXCDRFREQRESET_TIME = 5'h1;
localparam RXDFELPMRESET_TIME = 7'hf;
localparam RXISCANRESET_TIME = 5'h1;
localparam RXEYERESET_TIME = 7'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + RXCDRFREQRESET_TIME + RXDFELPMRESET_TIME + RXISCANRESET_TIME;
reg [6:0] rxeyereset_cnt;
assign rxeyereset_done = rxeyereset_cnt == RXEYERESET_TIME;
always @ (posedge gtrefclk) begin
if (rxreset) rxeyereset_cnt <= 0;
else if (!rxeyereset_done) rxeyereset_cnt <= rxeyereset_cnt + 1;
end
/*
* Resets
*/
wire usrpll_locked;
// make tx/rxreset synchronous to gtrefclk - gather singals from different domains: async, aclk, usrclk2, gtrefclk
localparam [7:0] RST_TIMER_LIMIT = 8'b1000;
reg rxreset_f;
reg txreset_f;
reg rxreset_f_r;
reg txreset_f_r;
reg rxreset_f_rr;
reg txreset_f_rr;
//reg pre_sata_reset_done;
reg sata_areset;
reg [2:0] sata_reset_done_r;
reg [7:0] rst_timer;
//reg rst_r = 1;
assign rst = !sata_reset_done_r;
assign sata_reset_done = sata_reset_done_r[1];
assign cplllock_debug = cplllock;
assign usrpll_locked_debug = usrpll_locked;
always @ (posedge clk or posedge sata_areset) begin
if (sata_areset) sata_reset_done_r <= 0;
else sata_reset_done_r <= {sata_reset_done_r[1:0], 1'b1};
end
reg cplllock_r;
always @ (posedge gtrefclk) begin
cplllock_r <= cplllock;
rxreset_f <= ~cplllock_r | ~cplllock | cpllreset | rxreset_oob & gtx_configured;
txreset_f <= ~cplllock_r | ~cplllock | cpllreset;
txreset_f_r <= txreset_f;
rxreset_f_r <= rxreset_f;
txreset_f_rr <= txreset_f_r;
rxreset_f_rr <= rxreset_f_r;
if (!(cplllock && usrpll_locked)) rst_timer <= RST_TIMER_LIMIT;
else if (|rst_timer) rst_timer <= rst_timer - 1;
sata_areset <= !(cplllock && usrpll_locked && !(|rst_timer));
end
assign rxreset = rxreset_f_rr;
assign txreset = txreset_f_rr;
assign cpllreset = extrst;
assign rxuserrdy = usrpll_locked & cplllock & ~cpllreset & ~rxreset & rxeyereset_done & sata_reset_done;
assign txuserrdy = usrpll_locked & cplllock & ~cpllreset & ~txreset & txpmareset_done & sata_reset_done;
assign gtx_ready = rxuserrdy & txuserrdy & rxresetdone & txresetdone;
// assert gtx_configured. Once gtx_ready -> 1, gtx_configured latches
always @ (posedge clk or posedge extrst)
if (extrst) gtx_configured <= 0;
else gtx_configured <= gtx_ready | gtx_configured;
// issue partial tx reset to restore functionality after oob sequence. Let it lasts 8 clock cycles
// Not enough or too early (after txelctidle?) txbufstatus shows overflow
localparam TXPCSRESET_CYCLES = 100;
reg txpcsreset_r;
reg [7:0] txpcsreset_cntr;
reg recal_tx_done_r;
assign recal_tx_done = recal_tx_done_r;
assign txpcsreset = txpcsreset_r;
always @ (posedge clk) begin
if (rst || (txpcsreset_cntr == 0)) txpcsreset_r <= 0;
else if (txpcsreset_req) txpcsreset_r <= 1;
if (rst) txpcsreset_cntr <= 0;
else if (txpcsreset_req) txpcsreset_cntr <= TXPCSRESET_CYCLES;
else if (txpcsreset_cntr != 0) txpcsreset_cntr <= txpcsreset_cntr - 1;
if (rst || txelecidle || txpcsreset_r) recal_tx_done_r <= 0;
else if (txresetdone) recal_tx_done_r <= 1;
end
// issue rx reset to restore functionality after oob sequence. Let it last 8 clock cycles
reg [3:0] rxreset_oob_cnt;
wire rxreset_oob_stop;
assign rxreset_oob_stop = rxreset_oob_cnt[3];
assign rxreset_oob = rxreset_req & ~rxreset_oob_stop;
assign rxreset_ack = rxreset_oob_stop & gtx_ready;
always @ (posedge clk or posedge extrst)
if (extrst) rxreset_oob_cnt <= 1;
else rxreset_oob_cnt <= rst | ~rxreset_req ? 4'h0 : rxreset_oob_stop ? rxreset_oob_cnt : rxreset_oob_cnt + 1'b1;
/*
* USRCLKs generation. USRCLK @ 150MHz, same as TXOUTCLK; USRCLK2 @ 75Mhz -> sata_clk === sclk
* It's recommended to use MMCM instead of PLL, whatever
*/
wire usrclk_global;
wire usrclk2;
// divide txoutclk (global) by 2, then make global. Does not need to be phase-aligned - will use FIFO
reg usrclk2_r;
always @ (posedge txoutclk) begin
if (~cplllock) usrclk2_r <= 0;
else usrclk2_r <= ~usrclk2;
end
assign txusrclk = txoutclk; // 150MHz, was already global
assign usrclk_global = txoutclk; // 150MHz, was already global
assign usrclk2 = usrclk2_r;
assign usrpll_locked = cplllock;
assign txusrclk = usrclk_global; // 150MHz
assign txusrclk2 = clk; // usrclk2;
//assign rxusrclk = usrclk_global; // 150MHz
assign rxusrclk2 = clk; // usrclk2;
select_clk_buf #(
.BUFFER_TYPE("BUFG")
) bufg_sclk (
.o (clk), // output
.i (usrclk2), // input
.clr (1'b0) // input
);
/*
* Padding for an external input clock @ 150 MHz
*/
localparam [1:0] CLKSWING_CFG = 2'b11;
IBUFDS_GTE2 #(
.CLKRCV_TRST ("TRUE"),
.CLKCM_CFG ("TRUE"),
.CLKSWING_CFG (CLKSWING_CFG)
)
ext_clock_buf(
.I (extclk_p),
.IB (extclk_n),
.CEB (1'b0),
.O (gtrefclk),
.ODIV2 ()
);
gtx_wrap #(
`ifdef USE_DATASCOPE
.ADDRESS_BITS (ADDRESS_BITS), // for datascope
.DATASCOPE_START_BIT (DATASCOPE_START_BIT),
.DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS),
`endif
.DATA_BYTE_WIDTH (DATA_BYTE_WIDTH),
.TXPMARESET_TIME (TXPMARESET_TIME),
.RXPMARESET_TIME (RXPMARESET_TIME),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME),
.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME),
.RXISCANRESET_TIME (RXISCANRESET_TIME),
.ELASTIC_DEPTH (ELASTIC_DEPTH), // with 4/7 infrequent full !
.ELASTIC_OFFSET (ELASTIC_OFFSET)
)
gtx_wrap
(
.debug (debug_cnt[11]), // output reg
.cplllock (cplllock), // output wire
.cplllockdetclk (cplllockdetclk), // input wire
.cpllreset (cpllreset), // input wire
.gtrefclk (gtrefclk), // input wire
.rxuserrdy (rxuserrdy), // input wire
.txuserrdy (txuserrdy), // input wire
// .rxusrclk (rxusrclk), // input wire
.rxusrclk2 (rxusrclk2), // input wire
.rxp (rxp), // input wire
.rxn (rxn), // input wire
.rxbyteisaligned (rxbyteisaligned), // output wire
.rxreset (rxreset), // input wire
.rxcomwakedet (rxcomwakedet), // output wire
.rxcominitdet (rxcominitdet), // output wire
.rxelecidle (rxelecidle), // output wire
.rxresetdone (rxresetdone), // output wire
.txreset (txreset), // input wire
.clk_phase_align_req(clk_phase_align_req), // output wire
.clk_phase_align_ack(clk_phase_align_ack), // input wire
.txusrclk (txusrclk), // input wire
.txusrclk2 (txusrclk2), // input wire
.txelecidle (txelecidle), // input wire
.txp (txp), // output wire
.txn (txn), // output wire
.txoutclk (txoutclk), // output wire // made global inside
.txpcsreset (txpcsreset), // input wire
.txresetdone (txresetdone), // output wire
.txcominit (txcominit), // input wire
.txcomwake (txcomwake), // input wire
.txcomfinish (), // output wire
.rxelsfull (rxelsfull), // output wire
.rxelsempty (rxelsempty), // output wire
.txdata (txdata), // input [31:0] wire
.txcharisk (txcharisk), // input [3:0] wire
.rxdata (rxdata), // output[31:0] wire
.rxcharisk (rxcharisk), // output[3:0] wire
.rxdisperr (rxdisperr), // output[3:0] wire
.rxnotintable (rxnotintable), // output[3:0] wire
.dbg_rxphaligndone (dbg_rxphaligndone),
.dbg_rx_clocks_aligned (dbg_rx_clocks_aligned),
.dbg_rxcdrlock (dbg_rxcdrlock) ,
.dbg_rxdlysresetdone (dbg_rxdlysresetdone),
.txbufstatus (txbufstatus[1:0]),
.xclk (xclk) // output receive clock, just to measure frequency // global
`ifdef USE_DATASCOPE
,.datascope_clk (datascope_clk), // output
.datascope_waddr (datascope_waddr), // output[9:0]
.datascope_we (datascope_we), // output
.datascope_di (datascope_di), // output[31:0]
.datascope_trig (datascope_trig) // input // external trigger event for the datascope
`endif
`ifdef USE_DRP
,.drp_rst (drp_rst), // input
.drp_clk (drp_clk), // input
.drp_en (drp_en), // input
.drp_we (drp_we), // input
.drp_addr (drp_addr), // input[14:0]
.drp_di (drp_di), // input[15:0]
.drp_rdy (drp_rdy), // output
.drp_do (drp_do) // output[15:0]
`endif
`ifdef DEBUG_ELASTIC
,.dbg_data_cntr (dbg_data_cntr) // output[11:0] reg
`endif
);
/*
* Interfaces
*/
assign cplllockdetclk = reliable_clk; //gtrefclk;
assign rxn = rxn_in;
assign rxp = rxp_in;
assign txn_out = txn;
assign txp_out = txp;
assign ll_data_out = rxdata_out;
assign ll_charisk_out = rxcharisk_out;
assign txdata_in = ll_data_in;
assign txcharisk_in = ll_charisk_in;
reg [3:0] debug_cntr1;
reg [3:0] debug_cntr2;
reg [3:0] debug_cntr3;
reg [3:0] debug_cntr4;
reg [15:0] debug_cntr5;
reg [15:0] debug_cntr6;
reg [1:0] debug_rxbyteisaligned_r;
reg debug_error_r;
//txoutclk
always @ (posedge gtrefclk) begin
if (extrst) debug_cntr1 <= 0;
else debug_cntr1 <= debug_cntr1 + 1;
end
always @ (posedge clk) begin
if (rst) debug_cntr2 <= 0;
else debug_cntr2 <= debug_cntr2 + 1;
end
always @ (posedge reliable_clk) begin
if (extrst) debug_cntr3 <= 0;
else debug_cntr3 <= debug_cntr3 + 1;
end
always @ (posedge txoutclk) begin
if (extrst) debug_cntr4 <= 0;
else debug_cntr4 <= debug_cntr4 + 1;
end
always @ (posedge clk) begin
debug_rxbyteisaligned_r <= {debug_rxbyteisaligned_r[0],rxbyteisaligned};
debug_error_r <= |ll_err_out;
if (rst) debug_cntr5 <= 0;
else if (debug_rxbyteisaligned_r==1) debug_cntr5 <= debug_cntr5 + 1;
if (rst) debug_cntr6 <= 0;
else if (debug_error_r) debug_cntr6 <= debug_cntr6 + 1;
end
reg [15:0] dbg_clk_align_cntr;
reg dbg_clk_align_wait;
reg [11:0] error_count;
always @ (posedge clk) begin
if (rxelecidle) error_count <= 0;
else if (phy_ready && (|ll_err_out)) error_count <= error_count + 1;
if (rxelecidle || clk_phase_align_ack) dbg_clk_align_wait <= 0;
else if (clk_phase_align_req) dbg_clk_align_wait <= 1;
if (rxelecidle) dbg_clk_align_cntr <= 0;
else if (dbg_clk_align_wait) dbg_clk_align_cntr <= dbg_clk_align_cntr +1;
end
`ifdef USE_DATASCOPE
`ifdef DEBUG_ELASTIC
assign debug_sata = {dbg_data_cntr[15:0], // latched at error from previous FIS (@sof) (otherwise overwritten by h2d rfis)
error_count[3:0],
2'b0,
datascope_waddr[9:0]};
`else //DEBUG_ELASTIC
assign debug_sata = {8'b0,
error_count[11:0],
2'b0,
datascope_waddr[9:0]};
`endif //`else DEBUG_ELASTIC
//dbg_data_cntr
`else
assign debug_sata = {8'b0, dbg_clk_align_cntr, txbufstatus[1:0], rxelecidle, dbg_rxcdrlock, rxelsfull, rxelsempty, dbg_rxphaligndone, dbg_rx_clocks_aligned};
`endif
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Encoder Core - Verilog ////
//// ////
//// Author: David Lundgren ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 David Lundgren ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
/* This module is the Huffman encoder. It takes in the quantized outputs
from the quantizer, and creates the Huffman codes from these value. The
output from this module is the jpeg code of the actual pixel data. The jpeg
file headers will need to be generated separately. The Huffman codes are constant,
and they can be changed by changing the parameters in this module. */
`timescale 1ns / 100ps
module y_huff(clk, rst, enable,
Y11, Y12, Y13, Y14, Y15, Y16, Y17, Y18, Y21, Y22, Y23, Y24, Y25, Y26, Y27, Y28,
Y31, Y32, Y33, Y34, Y35, Y36, Y37, Y38, Y41, Y42, Y43, Y44, Y45, Y46, Y47, Y48,
Y51, Y52, Y53, Y54, Y55, Y56, Y57, Y58, Y61, Y62, Y63, Y64, Y65, Y66, Y67, Y68,
Y71, Y72, Y73, Y74, Y75, Y76, Y77, Y78, Y81, Y82, Y83, Y84, Y85, Y86, Y87, Y88,
JPEG_bitstream, data_ready, output_reg_count, end_of_block_output,
end_of_block_empty);
input clk;
input rst;
input enable;
input [10:0] Y11, Y12, Y13, Y14, Y15, Y16, Y17, Y18, Y21, Y22, Y23, Y24;
input [10:0] Y25, Y26, Y27, Y28, Y31, Y32, Y33, Y34, Y35, Y36, Y37, Y38;
input [10:0] Y41, Y42, Y43, Y44, Y45, Y46, Y47, Y48, Y51, Y52, Y53, Y54;
input [10:0] Y55, Y56, Y57, Y58, Y61, Y62, Y63, Y64, Y65, Y66, Y67, Y68;
input [10:0] Y71, Y72, Y73, Y74, Y75, Y76, Y77, Y78, Y81, Y82, Y83, Y84;
input [10:0] Y85, Y86, Y87, Y88;
output [31:0] JPEG_bitstream;
output data_ready;
output [4:0] output_reg_count;
output end_of_block_output;
output end_of_block_empty;
reg [7:0] block_counter;
reg [11:0] Y11_amp, Y11_1_pos, Y11_1_neg, Y11_diff;
reg [11:0] Y11_previous, Y11_1;
reg [10:0] Y12_amp, Y12_pos, Y12_neg;
reg [10:0] Y21_pos, Y21_neg, Y31_pos, Y31_neg, Y22_pos, Y22_neg;
reg [10:0] Y13_pos, Y13_neg, Y14_pos, Y14_neg, Y15_pos, Y15_neg;
reg [10:0] Y16_pos, Y16_neg, Y17_pos, Y17_neg, Y18_pos, Y18_neg;
reg [10:0] Y23_pos, Y23_neg, Y24_pos, Y24_neg, Y25_pos, Y25_neg;
reg [10:0] Y26_pos, Y26_neg, Y27_pos, Y27_neg, Y28_pos, Y28_neg;
reg [10:0] Y32_pos, Y32_neg;
reg [10:0] Y33_pos, Y33_neg, Y34_pos, Y34_neg, Y35_pos, Y35_neg;
reg [10:0] Y36_pos, Y36_neg, Y37_pos, Y37_neg, Y38_pos, Y38_neg;
reg [10:0] Y41_pos, Y41_neg, Y42_pos, Y42_neg;
reg [10:0] Y43_pos, Y43_neg, Y44_pos, Y44_neg, Y45_pos, Y45_neg;
reg [10:0] Y46_pos, Y46_neg, Y47_pos, Y47_neg, Y48_pos, Y48_neg;
reg [10:0] Y51_pos, Y51_neg, Y52_pos, Y52_neg;
reg [10:0] Y53_pos, Y53_neg, Y54_pos, Y54_neg, Y55_pos, Y55_neg;
reg [10:0] Y56_pos, Y56_neg, Y57_pos, Y57_neg, Y58_pos, Y58_neg;
reg [10:0] Y61_pos, Y61_neg, Y62_pos, Y62_neg;
reg [10:0] Y63_pos, Y63_neg, Y64_pos, Y64_neg, Y65_pos, Y65_neg;
reg [10:0] Y66_pos, Y66_neg, Y67_pos, Y67_neg, Y68_pos, Y68_neg;
reg [10:0] Y71_pos, Y71_neg, Y72_pos, Y72_neg;
reg [10:0] Y73_pos, Y73_neg, Y74_pos, Y74_neg, Y75_pos, Y75_neg;
reg [10:0] Y76_pos, Y76_neg, Y77_pos, Y77_neg, Y78_pos, Y78_neg;
reg [10:0] Y81_pos, Y81_neg, Y82_pos, Y82_neg;
reg [10:0] Y83_pos, Y83_neg, Y84_pos, Y84_neg, Y85_pos, Y85_neg;
reg [10:0] Y86_pos, Y86_neg, Y87_pos, Y87_neg, Y88_pos, Y88_neg;
reg [3:0] Y11_bits_pos, Y11_bits_neg, Y11_bits, Y11_bits_1;
reg [3:0] Y12_bits_pos, Y12_bits_neg, Y12_bits, Y12_bits_1;
reg [3:0] Y12_bits_2, Y12_bits_3;
reg Y11_msb, Y12_msb, Y12_msb_1, data_ready;
reg enable_1, enable_2, enable_3, enable_4, enable_5, enable_6;
reg enable_7, enable_8, enable_9, enable_10, enable_11, enable_12;
reg enable_13, enable_module, enable_latch_7, enable_latch_8;
reg Y12_et_zero, rollover, rollover_1, rollover_2, rollover_3;
reg rollover_4, rollover_5, rollover_6, rollover_7;
reg Y21_et_zero, Y21_msb, Y31_et_zero, Y31_msb;
reg Y22_et_zero, Y22_msb, Y13_et_zero, Y13_msb;
reg Y14_et_zero, Y14_msb, Y15_et_zero, Y15_msb;
reg Y16_et_zero, Y16_msb, Y17_et_zero, Y17_msb;
reg Y18_et_zero, Y18_msb;
reg Y23_et_zero, Y23_msb, Y24_et_zero, Y24_msb;
reg Y25_et_zero, Y25_msb, Y26_et_zero, Y26_msb;
reg Y27_et_zero, Y27_msb, Y28_et_zero, Y28_msb;
reg Y32_et_zero, Y32_msb, Y33_et_zero, Y33_msb;
reg Y34_et_zero, Y34_msb, Y35_et_zero, Y35_msb;
reg Y36_et_zero, Y36_msb, Y37_et_zero, Y37_msb;
reg Y38_et_zero, Y38_msb;
reg Y41_et_zero, Y41_msb, Y42_et_zero, Y42_msb;
reg Y43_et_zero, Y43_msb, Y44_et_zero, Y44_msb;
reg Y45_et_zero, Y45_msb, Y46_et_zero, Y46_msb;
reg Y47_et_zero, Y47_msb, Y48_et_zero, Y48_msb;
reg Y51_et_zero, Y51_msb, Y52_et_zero, Y52_msb;
reg Y53_et_zero, Y53_msb, Y54_et_zero, Y54_msb;
reg Y55_et_zero, Y55_msb, Y56_et_zero, Y56_msb;
reg Y57_et_zero, Y57_msb, Y58_et_zero, Y58_msb;
reg Y61_et_zero, Y61_msb, Y62_et_zero, Y62_msb;
reg Y63_et_zero, Y63_msb, Y64_et_zero, Y64_msb;
reg Y65_et_zero, Y65_msb, Y66_et_zero, Y66_msb;
reg Y67_et_zero, Y67_msb, Y68_et_zero, Y68_msb;
reg Y71_et_zero, Y71_msb, Y72_et_zero, Y72_msb;
reg Y73_et_zero, Y73_msb, Y74_et_zero, Y74_msb;
reg Y75_et_zero, Y75_msb, Y76_et_zero, Y76_msb;
reg Y77_et_zero, Y77_msb, Y78_et_zero, Y78_msb;
reg Y81_et_zero, Y81_msb, Y82_et_zero, Y82_msb;
reg Y83_et_zero, Y83_msb, Y84_et_zero, Y84_msb;
reg Y85_et_zero, Y85_msb, Y86_et_zero, Y86_msb;
reg Y87_et_zero, Y87_msb, Y88_et_zero, Y88_msb;
reg Y12_et_zero_1, Y12_et_zero_2, Y12_et_zero_3, Y12_et_zero_4, Y12_et_zero_5;
reg [10:0] Y_DC [11:0];
reg [3:0] Y_DC_code_length [11:0];
reg [15:0] Y_AC [161:0];
reg [4:0] Y_AC_code_length [161:0];
reg [7:0] Y_AC_run_code [250:0];
reg [10:0] Y11_Huff, Y11_Huff_1, Y11_Huff_2;
reg [15:0] Y12_Huff, Y12_Huff_1, Y12_Huff_2;
reg [3:0] Y11_Huff_count, Y11_Huff_shift, Y11_Huff_shift_1, Y11_amp_shift, Y12_amp_shift;
reg [3:0] Y12_Huff_shift, Y12_Huff_shift_1, zero_run_length, zrl_1, zrl_2, zrl_3;
reg [4:0] Y12_Huff_count, Y12_Huff_count_1;
reg [4:0] output_reg_count, Y11_output_count, old_orc_1, old_orc_2;
reg [4:0] old_orc_3, old_orc_4, old_orc_5, old_orc_6, Y12_oc_1;
reg [4:0] orc_3, orc_4, orc_5, orc_6, orc_7, orc_8;
reg [4:0] Y12_output_count;
reg [4:0] Y12_edge, Y12_edge_1, Y12_edge_2, Y12_edge_3, Y12_edge_4;
reg [31:0] JPEG_bitstream, JPEG_bs, JPEG_bs_1, JPEG_bs_2, JPEG_bs_3, JPEG_bs_4, JPEG_bs_5;
reg [31:0] JPEG_Y12_bs, JPEG_Y12_bs_1, JPEG_Y12_bs_2, JPEG_Y12_bs_3, JPEG_Y12_bs_4;
reg [31:0] JPEG_ro_bs, JPEG_ro_bs_1, JPEG_ro_bs_2, JPEG_ro_bs_3, JPEG_ro_bs_4;
reg [21:0] Y11_JPEG_LSBs_3;
reg [10:0] Y11_JPEG_LSBs, Y11_JPEG_LSBs_1, Y11_JPEG_LSBs_2;
reg [9:0] Y12_JPEG_LSBs, Y12_JPEG_LSBs_1, Y12_JPEG_LSBs_2, Y12_JPEG_LSBs_3;
reg [25:0] Y11_JPEG_bits, Y11_JPEG_bits_1, Y12_JPEG_bits, Y12_JPEG_LSBs_4;
reg [7:0] Y12_code_entry;
reg third_8_all_0s, fourth_8_all_0s, fifth_8_all_0s, sixth_8_all_0s, seventh_8_all_0s;
reg eighth_8_all_0s, end_of_block, code_15_0, zrl_et_15, end_of_block_output;
reg end_of_block_empty;
wire [7:0] code_index = { zrl_2, Y12_bits };
always @(posedge clk)
begin
if (rst) begin
third_8_all_0s <= 0; fourth_8_all_0s <= 0;
fifth_8_all_0s <= 0; sixth_8_all_0s <= 0; seventh_8_all_0s <= 0;
eighth_8_all_0s <= 0;
end
else if (enable_1) begin
third_8_all_0s <= Y25_et_zero & Y34_et_zero & Y43_et_zero & Y52_et_zero
& Y61_et_zero & Y71_et_zero & Y62_et_zero & Y53_et_zero;
fourth_8_all_0s <= Y44_et_zero & Y35_et_zero & Y26_et_zero & Y17_et_zero
& Y18_et_zero & Y27_et_zero & Y36_et_zero & Y45_et_zero;
fifth_8_all_0s <= Y54_et_zero & Y63_et_zero & Y72_et_zero & Y81_et_zero
& Y82_et_zero & Y73_et_zero & Y64_et_zero & Y55_et_zero;
sixth_8_all_0s <= Y46_et_zero & Y37_et_zero & Y28_et_zero & Y38_et_zero
& Y47_et_zero & Y56_et_zero & Y65_et_zero & Y74_et_zero;
seventh_8_all_0s <= Y83_et_zero & Y84_et_zero & Y75_et_zero & Y66_et_zero
& Y57_et_zero & Y48_et_zero & Y58_et_zero & Y67_et_zero;
eighth_8_all_0s <= Y76_et_zero & Y85_et_zero & Y86_et_zero & Y77_et_zero
& Y68_et_zero & Y78_et_zero & Y87_et_zero & Y88_et_zero;
end
end
/* end_of_block checks to see if there are any nonzero elements left in the block
If there aren't any nonzero elements left, then the last bits in the JPEG stream
will be the end of block code. The purpose of this register is to determine if the
zero run length code 15-0 should be used or not. It should be used if there are 15 or more
zeros in a row, followed by a nonzero value. If there are only zeros left in the block,
then end_of_block will be 1. If there are any nonzero values left in the block, end_of_block
will be 0. */
always @(posedge clk)
begin
if (rst)
end_of_block <= 0;
else if (enable)
end_of_block <= 0;
else if (enable_module & block_counter < 32)
end_of_block <= third_8_all_0s & fourth_8_all_0s & fifth_8_all_0s
& sixth_8_all_0s & seventh_8_all_0s & eighth_8_all_0s;
else if (enable_module & block_counter < 48)
end_of_block <= fifth_8_all_0s & sixth_8_all_0s & seventh_8_all_0s
& eighth_8_all_0s;
else if (enable_module & block_counter <= 64)
end_of_block <= seventh_8_all_0s & eighth_8_all_0s;
else if (enable_module & block_counter > 64)
end_of_block <= 1;
end
always @(posedge clk)
begin
if (rst) begin
block_counter <= 0;
end
else if (enable) begin
block_counter <= 0;
end
else if (enable_module) begin
block_counter <= block_counter + 1;
end
end
always @(posedge clk)
begin
if (rst) begin
output_reg_count <= 0;
end
else if (end_of_block_output) begin
output_reg_count <= 0;
end
else if (enable_6) begin
output_reg_count <= output_reg_count + Y11_output_count;
end
else if (enable_latch_7) begin
output_reg_count <= output_reg_count + Y12_oc_1;
end
end
always @(posedge clk)
begin
if (rst) begin
old_orc_1 <= 0;
end
else if (end_of_block_output) begin
old_orc_1 <= 0;
end
else if (enable_module) begin
old_orc_1 <= output_reg_count;
end
end
always @(posedge clk)
begin
if (rst) begin
rollover <= 0; rollover_1 <= 0; rollover_2 <= 0;
rollover_3 <= 0; rollover_4 <= 0; rollover_5 <= 0;
rollover_6 <= 0; rollover_7 <= 0;
old_orc_2 <= 0;
orc_3 <= 0; orc_4 <= 0; orc_5 <= 0; orc_6 <= 0;
orc_7 <= 0; orc_8 <= 0; data_ready <= 0;
end_of_block_output <= 0; end_of_block_empty <= 0;
end
else if (enable_module) begin
rollover <= (old_orc_1 > output_reg_count);
rollover_1 <= rollover;
rollover_2 <= rollover_1;
rollover_3 <= rollover_2;
rollover_4 <= rollover_3;
rollover_5 <= rollover_4;
rollover_6 <= rollover_5;
rollover_7 <= rollover_6;
old_orc_2 <= old_orc_1;
orc_3 <= old_orc_2;
orc_4 <= orc_3; orc_5 <= orc_4;
orc_6 <= orc_5; orc_7 <= orc_6;
orc_8 <= orc_7;
data_ready <= rollover_6 | block_counter == 77;
end_of_block_output <= block_counter == 77;
end_of_block_empty <= rollover_7 & block_counter == 77 & output_reg_count == 0;
end
end
always @(posedge clk)
begin
if (rst) begin
JPEG_bs_5 <= 0;
end
else if (enable_module) begin
JPEG_bs_5[31] <= (rollover_6 & orc_7 > 0) ? JPEG_ro_bs_4[31] : JPEG_bs_4[31];
JPEG_bs_5[30] <= (rollover_6 & orc_7 > 1) ? JPEG_ro_bs_4[30] : JPEG_bs_4[30];
JPEG_bs_5[29] <= (rollover_6 & orc_7 > 2) ? JPEG_ro_bs_4[29] : JPEG_bs_4[29];
JPEG_bs_5[28] <= (rollover_6 & orc_7 > 3) ? JPEG_ro_bs_4[28] : JPEG_bs_4[28];
JPEG_bs_5[27] <= (rollover_6 & orc_7 > 4) ? JPEG_ro_bs_4[27] : JPEG_bs_4[27];
JPEG_bs_5[26] <= (rollover_6 & orc_7 > 5) ? JPEG_ro_bs_4[26] : JPEG_bs_4[26];
JPEG_bs_5[25] <= (rollover_6 & orc_7 > 6) ? JPEG_ro_bs_4[25] : JPEG_bs_4[25];
JPEG_bs_5[24] <= (rollover_6 & orc_7 > 7) ? JPEG_ro_bs_4[24] : JPEG_bs_4[24];
JPEG_bs_5[23] <= (rollover_6 & orc_7 > 8) ? JPEG_ro_bs_4[23] : JPEG_bs_4[23];
JPEG_bs_5[22] <= (rollover_6 & orc_7 > 9) ? JPEG_ro_bs_4[22] : JPEG_bs_4[22];
JPEG_bs_5[21] <= (rollover_6 & orc_7 > 10) ? JPEG_ro_bs_4[21] : JPEG_bs_4[21];
JPEG_bs_5[20] <= (rollover_6 & orc_7 > 11) ? JPEG_ro_bs_4[20] : JPEG_bs_4[20];
JPEG_bs_5[19] <= (rollover_6 & orc_7 > 12) ? JPEG_ro_bs_4[19] : JPEG_bs_4[19];
JPEG_bs_5[18] <= (rollover_6 & orc_7 > 13) ? JPEG_ro_bs_4[18] : JPEG_bs_4[18];
JPEG_bs_5[17] <= (rollover_6 & orc_7 > 14) ? JPEG_ro_bs_4[17] : JPEG_bs_4[17];
JPEG_bs_5[16] <= (rollover_6 & orc_7 > 15) ? JPEG_ro_bs_4[16] : JPEG_bs_4[16];
JPEG_bs_5[15] <= (rollover_6 & orc_7 > 16) ? JPEG_ro_bs_4[15] : JPEG_bs_4[15];
JPEG_bs_5[14] <= (rollover_6 & orc_7 > 17) ? JPEG_ro_bs_4[14] : JPEG_bs_4[14];
JPEG_bs_5[13] <= (rollover_6 & orc_7 > 18) ? JPEG_ro_bs_4[13] : JPEG_bs_4[13];
JPEG_bs_5[12] <= (rollover_6 & orc_7 > 19) ? JPEG_ro_bs_4[12] : JPEG_bs_4[12];
JPEG_bs_5[11] <= (rollover_6 & orc_7 > 20) ? JPEG_ro_bs_4[11] : JPEG_bs_4[11];
JPEG_bs_5[10] <= (rollover_6 & orc_7 > 21) ? JPEG_ro_bs_4[10] : JPEG_bs_4[10];
JPEG_bs_5[9] <= (rollover_6 & orc_7 > 22) ? JPEG_ro_bs_4[9] : JPEG_bs_4[9];
JPEG_bs_5[8] <= (rollover_6 & orc_7 > 23) ? JPEG_ro_bs_4[8] : JPEG_bs_4[8];
JPEG_bs_5[7] <= (rollover_6 & orc_7 > 24) ? JPEG_ro_bs_4[7] : JPEG_bs_4[7];
JPEG_bs_5[6] <= (rollover_6 & orc_7 > 25) ? JPEG_ro_bs_4[6] : JPEG_bs_4[6];
JPEG_bs_5[5] <= (rollover_6 & orc_7 > 26) ? JPEG_ro_bs_4[5] : JPEG_bs_4[5];
JPEG_bs_5[4] <= (rollover_6 & orc_7 > 27) ? JPEG_ro_bs_4[4] : JPEG_bs_4[4];
JPEG_bs_5[3] <= (rollover_6 & orc_7 > 28) ? JPEG_ro_bs_4[3] : JPEG_bs_4[3];
JPEG_bs_5[2] <= (rollover_6 & orc_7 > 29) ? JPEG_ro_bs_4[2] : JPEG_bs_4[2];
JPEG_bs_5[1] <= (rollover_6 & orc_7 > 30) ? JPEG_ro_bs_4[1] : JPEG_bs_4[1];
JPEG_bs_5[0] <= JPEG_bs_4[0];
end
end
always @(posedge clk)
begin
if (rst) begin
JPEG_bs_4 <= 0; JPEG_ro_bs_4 <= 0;
end
else if (enable_module) begin
JPEG_bs_4 <= (old_orc_6 == 1) ? JPEG_bs_3 >> 1 : JPEG_bs_3;
JPEG_ro_bs_4 <= (Y12_edge_4 <= 1) ? JPEG_ro_bs_3 << 1 : JPEG_ro_bs_3;
end
end
always @(posedge clk)
begin
if (rst) begin
JPEG_bs_3 <= 0; old_orc_6 <= 0; JPEG_ro_bs_3 <= 0;
Y12_edge_4 <= 0;
end
else if (enable_module) begin
JPEG_bs_3 <= (old_orc_5 >= 2) ? JPEG_bs_2 >> 2 : JPEG_bs_2;
old_orc_6 <= (old_orc_5 >= 2) ? old_orc_5 - 2 : old_orc_5;
JPEG_ro_bs_3 <= (Y12_edge_3 <= 2) ? JPEG_ro_bs_2 << 2 : JPEG_ro_bs_2;
Y12_edge_4 <= (Y12_edge_3 <= 2) ? Y12_edge_3 : Y12_edge_3 - 2;
end
end
always @(posedge clk)
begin
if (rst) begin
JPEG_bs_2 <= 0; old_orc_5 <= 0; JPEG_ro_bs_2 <= 0;
Y12_edge_3 <= 0;
end
else if (enable_module) begin
JPEG_bs_2 <= (old_orc_4 >= 4) ? JPEG_bs_1 >> 4 : JPEG_bs_1;
old_orc_5 <= (old_orc_4 >= 4) ? old_orc_4 - 4 : old_orc_4;
JPEG_ro_bs_2 <= (Y12_edge_2 <= 4) ? JPEG_ro_bs_1 << 4 : JPEG_ro_bs_1;
Y12_edge_3 <= (Y12_edge_2 <= 4) ? Y12_edge_2 : Y12_edge_2 - 4;
end
end
always @(posedge clk)
begin
if (rst) begin
JPEG_bs_1 <= 0; old_orc_4 <= 0; JPEG_ro_bs_1 <= 0;
Y12_edge_2 <= 0;
end
else if (enable_module) begin
JPEG_bs_1 <= (old_orc_3 >= 8) ? JPEG_bs >> 8 : JPEG_bs;
old_orc_4 <= (old_orc_3 >= 8) ? old_orc_3 - 8 : old_orc_3;
JPEG_ro_bs_1 <= (Y12_edge_1 <= 8) ? JPEG_ro_bs << 8 : JPEG_ro_bs;
Y12_edge_2 <= (Y12_edge_1 <= 8) ? Y12_edge_1 : Y12_edge_1 - 8;
end
end
always @(posedge clk)
begin
if (rst) begin
JPEG_bs <= 0; old_orc_3 <= 0; JPEG_ro_bs <= 0;
Y12_edge_1 <= 0; Y11_JPEG_bits_1 <= 0;
end
else if (enable_module) begin
JPEG_bs <= (old_orc_2 >= 16) ? Y11_JPEG_bits >> 10 : Y11_JPEG_bits << 6;
old_orc_3 <= (old_orc_2 >= 16) ? old_orc_2 - 16 : old_orc_2;
JPEG_ro_bs <= (Y12_edge <= 16) ? Y11_JPEG_bits_1 << 16 : Y11_JPEG_bits_1;
Y12_edge_1 <= (Y12_edge <= 16) ? Y12_edge : Y12_edge - 16;
Y11_JPEG_bits_1 <= Y11_JPEG_bits;
end
end
always @(posedge clk)
begin
if (rst) begin
Y12_JPEG_bits <= 0; Y12_edge <= 0;
end
else if (enable_module) begin
Y12_JPEG_bits[25] <= (Y12_Huff_shift_1 >= 16) ? Y12_JPEG_LSBs_4[25] : Y12_Huff_2[15];
Y12_JPEG_bits[24] <= (Y12_Huff_shift_1 >= 15) ? Y12_JPEG_LSBs_4[24] : Y12_Huff_2[14];
Y12_JPEG_bits[23] <= (Y12_Huff_shift_1 >= 14) ? Y12_JPEG_LSBs_4[23] : Y12_Huff_2[13];
Y12_JPEG_bits[22] <= (Y12_Huff_shift_1 >= 13) ? Y12_JPEG_LSBs_4[22] : Y12_Huff_2[12];
Y12_JPEG_bits[21] <= (Y12_Huff_shift_1 >= 12) ? Y12_JPEG_LSBs_4[21] : Y12_Huff_2[11];
Y12_JPEG_bits[20] <= (Y12_Huff_shift_1 >= 11) ? Y12_JPEG_LSBs_4[20] : Y12_Huff_2[10];
Y12_JPEG_bits[19] <= (Y12_Huff_shift_1 >= 10) ? Y12_JPEG_LSBs_4[19] : Y12_Huff_2[9];
Y12_JPEG_bits[18] <= (Y12_Huff_shift_1 >= 9) ? Y12_JPEG_LSBs_4[18] : Y12_Huff_2[8];
Y12_JPEG_bits[17] <= (Y12_Huff_shift_1 >= 8) ? Y12_JPEG_LSBs_4[17] : Y12_Huff_2[7];
Y12_JPEG_bits[16] <= (Y12_Huff_shift_1 >= 7) ? Y12_JPEG_LSBs_4[16] : Y12_Huff_2[6];
Y12_JPEG_bits[15] <= (Y12_Huff_shift_1 >= 6) ? Y12_JPEG_LSBs_4[15] : Y12_Huff_2[5];
Y12_JPEG_bits[14] <= (Y12_Huff_shift_1 >= 5) ? Y12_JPEG_LSBs_4[14] : Y12_Huff_2[4];
Y12_JPEG_bits[13] <= (Y12_Huff_shift_1 >= 4) ? Y12_JPEG_LSBs_4[13] : Y12_Huff_2[3];
Y12_JPEG_bits[12] <= (Y12_Huff_shift_1 >= 3) ? Y12_JPEG_LSBs_4[12] : Y12_Huff_2[2];
Y12_JPEG_bits[11] <= (Y12_Huff_shift_1 >= 2) ? Y12_JPEG_LSBs_4[11] : Y12_Huff_2[1];
Y12_JPEG_bits[10] <= (Y12_Huff_shift_1 >= 1) ? Y12_JPEG_LSBs_4[10] : Y12_Huff_2[0];
Y12_JPEG_bits[9:0] <= Y12_JPEG_LSBs_4[9:0];
Y12_edge <= old_orc_2 + 26; // 26 is the size of Y11_JPEG_bits
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_JPEG_bits <= 0;
end
else if (enable_7) begin
Y11_JPEG_bits[25] <= (Y11_Huff_shift_1 >= 11) ? Y11_JPEG_LSBs_3[21] : Y11_Huff_2[10];
Y11_JPEG_bits[24] <= (Y11_Huff_shift_1 >= 10) ? Y11_JPEG_LSBs_3[20] : Y11_Huff_2[9];
Y11_JPEG_bits[23] <= (Y11_Huff_shift_1 >= 9) ? Y11_JPEG_LSBs_3[19] : Y11_Huff_2[8];
Y11_JPEG_bits[22] <= (Y11_Huff_shift_1 >= 8) ? Y11_JPEG_LSBs_3[18] : Y11_Huff_2[7];
Y11_JPEG_bits[21] <= (Y11_Huff_shift_1 >= 7) ? Y11_JPEG_LSBs_3[17] : Y11_Huff_2[6];
Y11_JPEG_bits[20] <= (Y11_Huff_shift_1 >= 6) ? Y11_JPEG_LSBs_3[16] : Y11_Huff_2[5];
Y11_JPEG_bits[19] <= (Y11_Huff_shift_1 >= 5) ? Y11_JPEG_LSBs_3[15] : Y11_Huff_2[4];
Y11_JPEG_bits[18] <= (Y11_Huff_shift_1 >= 4) ? Y11_JPEG_LSBs_3[14] : Y11_Huff_2[3];
Y11_JPEG_bits[17] <= (Y11_Huff_shift_1 >= 3) ? Y11_JPEG_LSBs_3[13] : Y11_Huff_2[2];
Y11_JPEG_bits[16] <= (Y11_Huff_shift_1 >= 2) ? Y11_JPEG_LSBs_3[12] : Y11_Huff_2[1];
Y11_JPEG_bits[15] <= (Y11_Huff_shift_1 >= 1) ? Y11_JPEG_LSBs_3[11] : Y11_Huff_2[0];
Y11_JPEG_bits[14:4] <= Y11_JPEG_LSBs_3[10:0];
end
else if (enable_latch_8) begin
Y11_JPEG_bits <= Y12_JPEG_bits;
end
end
always @(posedge clk)
begin
if (rst) begin
Y12_oc_1 <= 0; Y12_JPEG_LSBs_4 <= 0;
Y12_Huff_2 <= 0; Y12_Huff_shift_1 <= 0;
end
else if (enable_module) begin
Y12_oc_1 <= (Y12_et_zero_5 & !code_15_0 & block_counter != 67) ? 0 :
Y12_bits_3 + Y12_Huff_count_1;
Y12_JPEG_LSBs_4 <= Y12_JPEG_LSBs_3 << Y12_Huff_shift;
Y12_Huff_2 <= Y12_Huff_1;
Y12_Huff_shift_1 <= Y12_Huff_shift;
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_JPEG_LSBs_3 <= 0; Y11_Huff_2 <= 0;
Y11_Huff_shift_1 <= 0;
end
else if (enable_6) begin
Y11_JPEG_LSBs_3 <= Y11_JPEG_LSBs_2 << Y11_Huff_shift;
Y11_Huff_2 <= Y11_Huff_1;
Y11_Huff_shift_1 <= Y11_Huff_shift;
end
end
always @(posedge clk)
begin
if (rst) begin
Y12_Huff_shift <= 0;
Y12_Huff_1 <= 0; Y12_JPEG_LSBs_3 <= 0; Y12_bits_3 <= 0;
Y12_Huff_count_1 <= 0; Y12_et_zero_5 <= 0; code_15_0 <= 0;
end
else if (enable_module) begin
Y12_Huff_shift <= 16 - Y12_Huff_count;
Y12_Huff_1 <= Y12_Huff;
Y12_JPEG_LSBs_3 <= Y12_JPEG_LSBs_2;
Y12_bits_3 <= Y12_bits_2;
Y12_Huff_count_1 <= Y12_Huff_count;
Y12_et_zero_5 <= Y12_et_zero_4;
code_15_0 <= zrl_et_15 & !end_of_block;
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_output_count <= 0; Y11_JPEG_LSBs_2 <= 0; Y11_Huff_shift <= 0;
Y11_Huff_1 <= 0;
end
else if (enable_5) begin
Y11_output_count <= Y11_bits_1 + Y11_Huff_count;
Y11_JPEG_LSBs_2 <= Y11_JPEG_LSBs_1 << Y11_amp_shift;
Y11_Huff_shift <= 11 - Y11_Huff_count;
Y11_Huff_1 <= Y11_Huff;
end
end
always @(posedge clk)
begin
if (rst) begin
Y12_JPEG_LSBs_2 <= 0;
Y12_Huff <= 0; Y12_Huff_count <= 0; Y12_bits_2 <= 0;
Y12_et_zero_4 <= 0; zrl_et_15 <= 0; zrl_3 <= 0;
end
else if (enable_module) begin
Y12_JPEG_LSBs_2 <= Y12_JPEG_LSBs_1 << Y12_amp_shift;
Y12_Huff <= Y_AC[Y12_code_entry];
Y12_Huff_count <= Y_AC_code_length[Y12_code_entry];
Y12_bits_2 <= Y12_bits_1;
Y12_et_zero_4 <= Y12_et_zero_3;
zrl_et_15 <= zrl_3 == 15;
zrl_3 <= zrl_2;
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_Huff <= 0; Y11_Huff_count <= 0; Y11_amp_shift <= 0;
Y11_JPEG_LSBs_1 <= 0; Y11_bits_1 <= 0;
end
else if (enable_4) begin
Y11_Huff[10:0] <= Y_DC[Y11_bits];
Y11_Huff_count <= Y_DC_code_length[Y11_bits];
Y11_amp_shift <= 11 - Y11_bits;
Y11_JPEG_LSBs_1 <= Y11_JPEG_LSBs;
Y11_bits_1 <= Y11_bits;
end
end
always @(posedge clk)
begin
if (rst) begin
Y12_code_entry <= 0; Y12_JPEG_LSBs_1 <= 0; Y12_amp_shift <= 0;
Y12_bits_1 <= 0; Y12_et_zero_3 <= 0; zrl_2 <= 0;
end
else if (enable_module) begin
Y12_code_entry <= Y_AC_run_code[code_index];
Y12_JPEG_LSBs_1 <= Y12_JPEG_LSBs;
Y12_amp_shift <= 10 - Y12_bits;
Y12_bits_1 <= Y12_bits;
Y12_et_zero_3 <= Y12_et_zero_2;
zrl_2 <= zrl_1;
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_bits <= 0; Y11_JPEG_LSBs <= 0;
end
else if (enable_3) begin
Y11_bits <= Y11_msb ? Y11_bits_neg : Y11_bits_pos;
Y11_JPEG_LSBs <= Y11_amp[10:0]; // The top bit of Y11_amp is the sign bit
end
end
always @(posedge clk)
begin
if (rst) begin
Y12_bits <= 0; Y12_JPEG_LSBs <= 0; zrl_1 <= 0;
Y12_et_zero_2 <= 0;
end
else if (enable_module) begin
Y12_bits <= Y12_msb_1 ? Y12_bits_neg : Y12_bits_pos;
Y12_JPEG_LSBs <= Y12_amp[9:0]; // The top bit of Y12_amp is the sign bit
zrl_1 <= block_counter == 62 & Y12_et_zero ? 0 : zero_run_length;
Y12_et_zero_2 <= Y12_et_zero_1;
end
end
// Y11_amp is the amplitude that will be represented in bits in the
// JPEG code, following the run length code
always @(posedge clk)
begin
if (rst) begin
Y11_amp <= 0;
end
else if (enable_2) begin
Y11_amp <= Y11_msb ? Y11_1_neg : Y11_1_pos;
end
end
always @(posedge clk)
begin
if (rst)
zero_run_length <= 0;
else if (enable)
zero_run_length <= 0;
else if (enable_module)
zero_run_length <= Y12_et_zero ? zero_run_length + 1: 0;
end
always @(posedge clk)
begin
if (rst) begin
Y12_amp <= 0;
Y12_et_zero_1 <= 0; Y12_msb_1 <= 0;
end
else if (enable_module) begin
Y12_amp <= Y12_msb ? Y12_neg : Y12_pos;
Y12_et_zero_1 <= Y12_et_zero;
Y12_msb_1 <= Y12_msb;
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_1_pos <= 0; Y11_1_neg <= 0; Y11_msb <= 0;
Y11_previous <= 0;
end
else if (enable_1) begin
Y11_1_pos <= Y11_diff;
Y11_1_neg <= Y11_diff - 1;
Y11_msb <= Y11_diff[11];
Y11_previous <= Y11_1;
end
end
always @(posedge clk)
begin
if (rst) begin
Y12_pos <= 0; Y12_neg <= 0; Y12_msb <= 0; Y12_et_zero <= 0;
Y13_pos <= 0; Y13_neg <= 0; Y13_msb <= 0; Y13_et_zero <= 0;
Y14_pos <= 0; Y14_neg <= 0; Y14_msb <= 0; Y14_et_zero <= 0;
Y15_pos <= 0; Y15_neg <= 0; Y15_msb <= 0; Y15_et_zero <= 0;
Y16_pos <= 0; Y16_neg <= 0; Y16_msb <= 0; Y16_et_zero <= 0;
Y17_pos <= 0; Y17_neg <= 0; Y17_msb <= 0; Y17_et_zero <= 0;
Y18_pos <= 0; Y18_neg <= 0; Y18_msb <= 0; Y18_et_zero <= 0;
Y21_pos <= 0; Y21_neg <= 0; Y21_msb <= 0; Y21_et_zero <= 0;
Y22_pos <= 0; Y22_neg <= 0; Y22_msb <= 0; Y22_et_zero <= 0;
Y23_pos <= 0; Y23_neg <= 0; Y23_msb <= 0; Y23_et_zero <= 0;
Y24_pos <= 0; Y24_neg <= 0; Y24_msb <= 0; Y24_et_zero <= 0;
Y25_pos <= 0; Y25_neg <= 0; Y25_msb <= 0; Y25_et_zero <= 0;
Y26_pos <= 0; Y26_neg <= 0; Y26_msb <= 0; Y26_et_zero <= 0;
Y27_pos <= 0; Y27_neg <= 0; Y27_msb <= 0; Y27_et_zero <= 0;
Y28_pos <= 0; Y28_neg <= 0; Y28_msb <= 0; Y28_et_zero <= 0;
Y31_pos <= 0; Y31_neg <= 0; Y31_msb <= 0; Y31_et_zero <= 0;
Y32_pos <= 0; Y32_neg <= 0; Y32_msb <= 0; Y32_et_zero <= 0;
Y33_pos <= 0; Y33_neg <= 0; Y33_msb <= 0; Y33_et_zero <= 0;
Y34_pos <= 0; Y34_neg <= 0; Y34_msb <= 0; Y34_et_zero <= 0;
Y35_pos <= 0; Y35_neg <= 0; Y35_msb <= 0; Y35_et_zero <= 0;
Y36_pos <= 0; Y36_neg <= 0; Y36_msb <= 0; Y36_et_zero <= 0;
Y37_pos <= 0; Y37_neg <= 0; Y37_msb <= 0; Y37_et_zero <= 0;
Y38_pos <= 0; Y38_neg <= 0; Y38_msb <= 0; Y38_et_zero <= 0;
Y41_pos <= 0; Y41_neg <= 0; Y41_msb <= 0; Y41_et_zero <= 0;
Y42_pos <= 0; Y42_neg <= 0; Y42_msb <= 0; Y42_et_zero <= 0;
Y43_pos <= 0; Y43_neg <= 0; Y43_msb <= 0; Y43_et_zero <= 0;
Y44_pos <= 0; Y44_neg <= 0; Y44_msb <= 0; Y44_et_zero <= 0;
Y45_pos <= 0; Y45_neg <= 0; Y45_msb <= 0; Y45_et_zero <= 0;
Y46_pos <= 0; Y46_neg <= 0; Y46_msb <= 0; Y46_et_zero <= 0;
Y47_pos <= 0; Y47_neg <= 0; Y47_msb <= 0; Y47_et_zero <= 0;
Y48_pos <= 0; Y48_neg <= 0; Y48_msb <= 0; Y48_et_zero <= 0;
Y51_pos <= 0; Y51_neg <= 0; Y51_msb <= 0; Y51_et_zero <= 0;
Y52_pos <= 0; Y52_neg <= 0; Y52_msb <= 0; Y52_et_zero <= 0;
Y53_pos <= 0; Y53_neg <= 0; Y53_msb <= 0; Y53_et_zero <= 0;
Y54_pos <= 0; Y54_neg <= 0; Y54_msb <= 0; Y54_et_zero <= 0;
Y55_pos <= 0; Y55_neg <= 0; Y55_msb <= 0; Y55_et_zero <= 0;
Y56_pos <= 0; Y56_neg <= 0; Y56_msb <= 0; Y56_et_zero <= 0;
Y57_pos <= 0; Y57_neg <= 0; Y57_msb <= 0; Y57_et_zero <= 0;
Y58_pos <= 0; Y58_neg <= 0; Y58_msb <= 0; Y58_et_zero <= 0;
Y61_pos <= 0; Y61_neg <= 0; Y61_msb <= 0; Y61_et_zero <= 0;
Y62_pos <= 0; Y62_neg <= 0; Y62_msb <= 0; Y62_et_zero <= 0;
Y63_pos <= 0; Y63_neg <= 0; Y63_msb <= 0; Y63_et_zero <= 0;
Y64_pos <= 0; Y64_neg <= 0; Y64_msb <= 0; Y64_et_zero <= 0;
Y65_pos <= 0; Y65_neg <= 0; Y65_msb <= 0; Y65_et_zero <= 0;
Y66_pos <= 0; Y66_neg <= 0; Y66_msb <= 0; Y66_et_zero <= 0;
Y67_pos <= 0; Y67_neg <= 0; Y67_msb <= 0; Y67_et_zero <= 0;
Y68_pos <= 0; Y68_neg <= 0; Y68_msb <= 0; Y68_et_zero <= 0;
Y71_pos <= 0; Y71_neg <= 0; Y71_msb <= 0; Y71_et_zero <= 0;
Y72_pos <= 0; Y72_neg <= 0; Y72_msb <= 0; Y72_et_zero <= 0;
Y73_pos <= 0; Y73_neg <= 0; Y73_msb <= 0; Y73_et_zero <= 0;
Y74_pos <= 0; Y74_neg <= 0; Y74_msb <= 0; Y74_et_zero <= 0;
Y75_pos <= 0; Y75_neg <= 0; Y75_msb <= 0; Y75_et_zero <= 0;
Y76_pos <= 0; Y76_neg <= 0; Y76_msb <= 0; Y76_et_zero <= 0;
Y77_pos <= 0; Y77_neg <= 0; Y77_msb <= 0; Y77_et_zero <= 0;
Y78_pos <= 0; Y78_neg <= 0; Y78_msb <= 0; Y78_et_zero <= 0;
Y81_pos <= 0; Y81_neg <= 0; Y81_msb <= 0; Y81_et_zero <= 0;
Y82_pos <= 0; Y82_neg <= 0; Y82_msb <= 0; Y82_et_zero <= 0;
Y83_pos <= 0; Y83_neg <= 0; Y83_msb <= 0; Y83_et_zero <= 0;
Y84_pos <= 0; Y84_neg <= 0; Y84_msb <= 0; Y84_et_zero <= 0;
Y85_pos <= 0; Y85_neg <= 0; Y85_msb <= 0; Y85_et_zero <= 0;
Y86_pos <= 0; Y86_neg <= 0; Y86_msb <= 0; Y86_et_zero <= 0;
Y87_pos <= 0; Y87_neg <= 0; Y87_msb <= 0; Y87_et_zero <= 0;
Y88_pos <= 0; Y88_neg <= 0; Y88_msb <= 0; Y88_et_zero <= 0;
end
else if (enable) begin
Y12_pos <= Y12;
Y12_neg <= Y12 - 1;
Y12_msb <= Y12[10];
Y12_et_zero <= !(|Y12);
Y13_pos <= Y13;
Y13_neg <= Y13 - 1;
Y13_msb <= Y13[10];
Y13_et_zero <= !(|Y13);
Y14_pos <= Y14;
Y14_neg <= Y14 - 1;
Y14_msb <= Y14[10];
Y14_et_zero <= !(|Y14);
Y15_pos <= Y15;
Y15_neg <= Y15 - 1;
Y15_msb <= Y15[10];
Y15_et_zero <= !(|Y15);
Y16_pos <= Y16;
Y16_neg <= Y16 - 1;
Y16_msb <= Y16[10];
Y16_et_zero <= !(|Y16);
Y17_pos <= Y17;
Y17_neg <= Y17 - 1;
Y17_msb <= Y17[10];
Y17_et_zero <= !(|Y17);
Y18_pos <= Y18;
Y18_neg <= Y18 - 1;
Y18_msb <= Y18[10];
Y18_et_zero <= !(|Y18);
Y21_pos <= Y21;
Y21_neg <= Y21 - 1;
Y21_msb <= Y21[10];
Y21_et_zero <= !(|Y21);
Y22_pos <= Y22;
Y22_neg <= Y22 - 1;
Y22_msb <= Y22[10];
Y22_et_zero <= !(|Y22);
Y23_pos <= Y23;
Y23_neg <= Y23 - 1;
Y23_msb <= Y23[10];
Y23_et_zero <= !(|Y23);
Y24_pos <= Y24;
Y24_neg <= Y24 - 1;
Y24_msb <= Y24[10];
Y24_et_zero <= !(|Y24);
Y25_pos <= Y25;
Y25_neg <= Y25 - 1;
Y25_msb <= Y25[10];
Y25_et_zero <= !(|Y25);
Y26_pos <= Y26;
Y26_neg <= Y26 - 1;
Y26_msb <= Y26[10];
Y26_et_zero <= !(|Y26);
Y27_pos <= Y27;
Y27_neg <= Y27 - 1;
Y27_msb <= Y27[10];
Y27_et_zero <= !(|Y27);
Y28_pos <= Y28;
Y28_neg <= Y28 - 1;
Y28_msb <= Y28[10];
Y28_et_zero <= !(|Y28);
Y31_pos <= Y31;
Y31_neg <= Y31 - 1;
Y31_msb <= Y31[10];
Y31_et_zero <= !(|Y31);
Y32_pos <= Y32;
Y32_neg <= Y32 - 1;
Y32_msb <= Y32[10];
Y32_et_zero <= !(|Y32);
Y33_pos <= Y33;
Y33_neg <= Y33 - 1;
Y33_msb <= Y33[10];
Y33_et_zero <= !(|Y33);
Y34_pos <= Y34;
Y34_neg <= Y34 - 1;
Y34_msb <= Y34[10];
Y34_et_zero <= !(|Y34);
Y35_pos <= Y35;
Y35_neg <= Y35 - 1;
Y35_msb <= Y35[10];
Y35_et_zero <= !(|Y35);
Y36_pos <= Y36;
Y36_neg <= Y36 - 1;
Y36_msb <= Y36[10];
Y36_et_zero <= !(|Y36);
Y37_pos <= Y37;
Y37_neg <= Y37 - 1;
Y37_msb <= Y37[10];
Y37_et_zero <= !(|Y37);
Y38_pos <= Y38;
Y38_neg <= Y38 - 1;
Y38_msb <= Y38[10];
Y38_et_zero <= !(|Y38);
Y41_pos <= Y41;
Y41_neg <= Y41 - 1;
Y41_msb <= Y41[10];
Y41_et_zero <= !(|Y41);
Y42_pos <= Y42;
Y42_neg <= Y42 - 1;
Y42_msb <= Y42[10];
Y42_et_zero <= !(|Y42);
Y43_pos <= Y43;
Y43_neg <= Y43 - 1;
Y43_msb <= Y43[10];
Y43_et_zero <= !(|Y43);
Y44_pos <= Y44;
Y44_neg <= Y44 - 1;
Y44_msb <= Y44[10];
Y44_et_zero <= !(|Y44);
Y45_pos <= Y45;
Y45_neg <= Y45 - 1;
Y45_msb <= Y45[10];
Y45_et_zero <= !(|Y45);
Y46_pos <= Y46;
Y46_neg <= Y46 - 1;
Y46_msb <= Y46[10];
Y46_et_zero <= !(|Y46);
Y47_pos <= Y47;
Y47_neg <= Y47 - 1;
Y47_msb <= Y47[10];
Y47_et_zero <= !(|Y47);
Y48_pos <= Y48;
Y48_neg <= Y48 - 1;
Y48_msb <= Y48[10];
Y48_et_zero <= !(|Y48);
Y51_pos <= Y51;
Y51_neg <= Y51 - 1;
Y51_msb <= Y51[10];
Y51_et_zero <= !(|Y51);
Y52_pos <= Y52;
Y52_neg <= Y52 - 1;
Y52_msb <= Y52[10];
Y52_et_zero <= !(|Y52);
Y53_pos <= Y53;
Y53_neg <= Y53 - 1;
Y53_msb <= Y53[10];
Y53_et_zero <= !(|Y53);
Y54_pos <= Y54;
Y54_neg <= Y54 - 1;
Y54_msb <= Y54[10];
Y54_et_zero <= !(|Y54);
Y55_pos <= Y55;
Y55_neg <= Y55 - 1;
Y55_msb <= Y55[10];
Y55_et_zero <= !(|Y55);
Y56_pos <= Y56;
Y56_neg <= Y56 - 1;
Y56_msb <= Y56[10];
Y56_et_zero <= !(|Y56);
Y57_pos <= Y57;
Y57_neg <= Y57 - 1;
Y57_msb <= Y57[10];
Y57_et_zero <= !(|Y57);
Y58_pos <= Y58;
Y58_neg <= Y58 - 1;
Y58_msb <= Y58[10];
Y58_et_zero <= !(|Y58);
Y61_pos <= Y61;
Y61_neg <= Y61 - 1;
Y61_msb <= Y61[10];
Y61_et_zero <= !(|Y61);
Y62_pos <= Y62;
Y62_neg <= Y62 - 1;
Y62_msb <= Y62[10];
Y62_et_zero <= !(|Y62);
Y63_pos <= Y63;
Y63_neg <= Y63 - 1;
Y63_msb <= Y63[10];
Y63_et_zero <= !(|Y63);
Y64_pos <= Y64;
Y64_neg <= Y64 - 1;
Y64_msb <= Y64[10];
Y64_et_zero <= !(|Y64);
Y65_pos <= Y65;
Y65_neg <= Y65 - 1;
Y65_msb <= Y65[10];
Y65_et_zero <= !(|Y65);
Y66_pos <= Y66;
Y66_neg <= Y66 - 1;
Y66_msb <= Y66[10];
Y66_et_zero <= !(|Y66);
Y67_pos <= Y67;
Y67_neg <= Y67 - 1;
Y67_msb <= Y67[10];
Y67_et_zero <= !(|Y67);
Y68_pos <= Y68;
Y68_neg <= Y68 - 1;
Y68_msb <= Y68[10];
Y68_et_zero <= !(|Y68);
Y71_pos <= Y71;
Y71_neg <= Y71 - 1;
Y71_msb <= Y71[10];
Y71_et_zero <= !(|Y71);
Y72_pos <= Y72;
Y72_neg <= Y72 - 1;
Y72_msb <= Y72[10];
Y72_et_zero <= !(|Y72);
Y73_pos <= Y73;
Y73_neg <= Y73 - 1;
Y73_msb <= Y73[10];
Y73_et_zero <= !(|Y73);
Y74_pos <= Y74;
Y74_neg <= Y74 - 1;
Y74_msb <= Y74[10];
Y74_et_zero <= !(|Y74);
Y75_pos <= Y75;
Y75_neg <= Y75 - 1;
Y75_msb <= Y75[10];
Y75_et_zero <= !(|Y75);
Y76_pos <= Y76;
Y76_neg <= Y76 - 1;
Y76_msb <= Y76[10];
Y76_et_zero <= !(|Y76);
Y77_pos <= Y77;
Y77_neg <= Y77 - 1;
Y77_msb <= Y77[10];
Y77_et_zero <= !(|Y77);
Y78_pos <= Y78;
Y78_neg <= Y78 - 1;
Y78_msb <= Y78[10];
Y78_et_zero <= !(|Y78);
Y81_pos <= Y81;
Y81_neg <= Y81 - 1;
Y81_msb <= Y81[10];
Y81_et_zero <= !(|Y81);
Y82_pos <= Y82;
Y82_neg <= Y82 - 1;
Y82_msb <= Y82[10];
Y82_et_zero <= !(|Y82);
Y83_pos <= Y83;
Y83_neg <= Y83 - 1;
Y83_msb <= Y83[10];
Y83_et_zero <= !(|Y83);
Y84_pos <= Y84;
Y84_neg <= Y84 - 1;
Y84_msb <= Y84[10];
Y84_et_zero <= !(|Y84);
Y85_pos <= Y85;
Y85_neg <= Y85 - 1;
Y85_msb <= Y85[10];
Y85_et_zero <= !(|Y85);
Y86_pos <= Y86;
Y86_neg <= Y86 - 1;
Y86_msb <= Y86[10];
Y86_et_zero <= !(|Y86);
Y87_pos <= Y87;
Y87_neg <= Y87 - 1;
Y87_msb <= Y87[10];
Y87_et_zero <= !(|Y87);
Y88_pos <= Y88;
Y88_neg <= Y88 - 1;
Y88_msb <= Y88[10];
Y88_et_zero <= !(|Y88);
end
else if (enable_module) begin
Y12_pos <= Y21_pos;
Y12_neg <= Y21_neg;
Y12_msb <= Y21_msb;
Y12_et_zero <= Y21_et_zero;
Y21_pos <= Y31_pos;
Y21_neg <= Y31_neg;
Y21_msb <= Y31_msb;
Y21_et_zero <= Y31_et_zero;
Y31_pos <= Y22_pos;
Y31_neg <= Y22_neg;
Y31_msb <= Y22_msb;
Y31_et_zero <= Y22_et_zero;
Y22_pos <= Y13_pos;
Y22_neg <= Y13_neg;
Y22_msb <= Y13_msb;
Y22_et_zero <= Y13_et_zero;
Y13_pos <= Y14_pos;
Y13_neg <= Y14_neg;
Y13_msb <= Y14_msb;
Y13_et_zero <= Y14_et_zero;
Y14_pos <= Y23_pos;
Y14_neg <= Y23_neg;
Y14_msb <= Y23_msb;
Y14_et_zero <= Y23_et_zero;
Y23_pos <= Y32_pos;
Y23_neg <= Y32_neg;
Y23_msb <= Y32_msb;
Y23_et_zero <= Y32_et_zero;
Y32_pos <= Y41_pos;
Y32_neg <= Y41_neg;
Y32_msb <= Y41_msb;
Y32_et_zero <= Y41_et_zero;
Y41_pos <= Y51_pos;
Y41_neg <= Y51_neg;
Y41_msb <= Y51_msb;
Y41_et_zero <= Y51_et_zero;
Y51_pos <= Y42_pos;
Y51_neg <= Y42_neg;
Y51_msb <= Y42_msb;
Y51_et_zero <= Y42_et_zero;
Y42_pos <= Y33_pos;
Y42_neg <= Y33_neg;
Y42_msb <= Y33_msb;
Y42_et_zero <= Y33_et_zero;
Y33_pos <= Y24_pos;
Y33_neg <= Y24_neg;
Y33_msb <= Y24_msb;
Y33_et_zero <= Y24_et_zero;
Y24_pos <= Y15_pos;
Y24_neg <= Y15_neg;
Y24_msb <= Y15_msb;
Y24_et_zero <= Y15_et_zero;
Y15_pos <= Y16_pos;
Y15_neg <= Y16_neg;
Y15_msb <= Y16_msb;
Y15_et_zero <= Y16_et_zero;
Y16_pos <= Y25_pos;
Y16_neg <= Y25_neg;
Y16_msb <= Y25_msb;
Y16_et_zero <= Y25_et_zero;
Y25_pos <= Y34_pos;
Y25_neg <= Y34_neg;
Y25_msb <= Y34_msb;
Y25_et_zero <= Y34_et_zero;
Y34_pos <= Y43_pos;
Y34_neg <= Y43_neg;
Y34_msb <= Y43_msb;
Y34_et_zero <= Y43_et_zero;
Y43_pos <= Y52_pos;
Y43_neg <= Y52_neg;
Y43_msb <= Y52_msb;
Y43_et_zero <= Y52_et_zero;
Y52_pos <= Y61_pos;
Y52_neg <= Y61_neg;
Y52_msb <= Y61_msb;
Y52_et_zero <= Y61_et_zero;
Y61_pos <= Y71_pos;
Y61_neg <= Y71_neg;
Y61_msb <= Y71_msb;
Y61_et_zero <= Y71_et_zero;
Y71_pos <= Y62_pos;
Y71_neg <= Y62_neg;
Y71_msb <= Y62_msb;
Y71_et_zero <= Y62_et_zero;
Y62_pos <= Y53_pos;
Y62_neg <= Y53_neg;
Y62_msb <= Y53_msb;
Y62_et_zero <= Y53_et_zero;
Y53_pos <= Y44_pos;
Y53_neg <= Y44_neg;
Y53_msb <= Y44_msb;
Y53_et_zero <= Y44_et_zero;
Y44_pos <= Y35_pos;
Y44_neg <= Y35_neg;
Y44_msb <= Y35_msb;
Y44_et_zero <= Y35_et_zero;
Y35_pos <= Y26_pos;
Y35_neg <= Y26_neg;
Y35_msb <= Y26_msb;
Y35_et_zero <= Y26_et_zero;
Y26_pos <= Y17_pos;
Y26_neg <= Y17_neg;
Y26_msb <= Y17_msb;
Y26_et_zero <= Y17_et_zero;
Y17_pos <= Y18_pos;
Y17_neg <= Y18_neg;
Y17_msb <= Y18_msb;
Y17_et_zero <= Y18_et_zero;
Y18_pos <= Y27_pos;
Y18_neg <= Y27_neg;
Y18_msb <= Y27_msb;
Y18_et_zero <= Y27_et_zero;
Y27_pos <= Y36_pos;
Y27_neg <= Y36_neg;
Y27_msb <= Y36_msb;
Y27_et_zero <= Y36_et_zero;
Y36_pos <= Y45_pos;
Y36_neg <= Y45_neg;
Y36_msb <= Y45_msb;
Y36_et_zero <= Y45_et_zero;
Y45_pos <= Y54_pos;
Y45_neg <= Y54_neg;
Y45_msb <= Y54_msb;
Y45_et_zero <= Y54_et_zero;
Y54_pos <= Y63_pos;
Y54_neg <= Y63_neg;
Y54_msb <= Y63_msb;
Y54_et_zero <= Y63_et_zero;
Y63_pos <= Y72_pos;
Y63_neg <= Y72_neg;
Y63_msb <= Y72_msb;
Y63_et_zero <= Y72_et_zero;
Y72_pos <= Y81_pos;
Y72_neg <= Y81_neg;
Y72_msb <= Y81_msb;
Y72_et_zero <= Y81_et_zero;
Y81_pos <= Y82_pos;
Y81_neg <= Y82_neg;
Y81_msb <= Y82_msb;
Y81_et_zero <= Y82_et_zero;
Y82_pos <= Y73_pos;
Y82_neg <= Y73_neg;
Y82_msb <= Y73_msb;
Y82_et_zero <= Y73_et_zero;
Y73_pos <= Y64_pos;
Y73_neg <= Y64_neg;
Y73_msb <= Y64_msb;
Y73_et_zero <= Y64_et_zero;
Y64_pos <= Y55_pos;
Y64_neg <= Y55_neg;
Y64_msb <= Y55_msb;
Y64_et_zero <= Y55_et_zero;
Y55_pos <= Y46_pos;
Y55_neg <= Y46_neg;
Y55_msb <= Y46_msb;
Y55_et_zero <= Y46_et_zero;
Y46_pos <= Y37_pos;
Y46_neg <= Y37_neg;
Y46_msb <= Y37_msb;
Y46_et_zero <= Y37_et_zero;
Y37_pos <= Y28_pos;
Y37_neg <= Y28_neg;
Y37_msb <= Y28_msb;
Y37_et_zero <= Y28_et_zero;
Y28_pos <= Y38_pos;
Y28_neg <= Y38_neg;
Y28_msb <= Y38_msb;
Y28_et_zero <= Y38_et_zero;
Y38_pos <= Y47_pos;
Y38_neg <= Y47_neg;
Y38_msb <= Y47_msb;
Y38_et_zero <= Y47_et_zero;
Y47_pos <= Y56_pos;
Y47_neg <= Y56_neg;
Y47_msb <= Y56_msb;
Y47_et_zero <= Y56_et_zero;
Y56_pos <= Y65_pos;
Y56_neg <= Y65_neg;
Y56_msb <= Y65_msb;
Y56_et_zero <= Y65_et_zero;
Y65_pos <= Y74_pos;
Y65_neg <= Y74_neg;
Y65_msb <= Y74_msb;
Y65_et_zero <= Y74_et_zero;
Y74_pos <= Y83_pos;
Y74_neg <= Y83_neg;
Y74_msb <= Y83_msb;
Y74_et_zero <= Y83_et_zero;
Y83_pos <= Y84_pos;
Y83_neg <= Y84_neg;
Y83_msb <= Y84_msb;
Y83_et_zero <= Y84_et_zero;
Y84_pos <= Y75_pos;
Y84_neg <= Y75_neg;
Y84_msb <= Y75_msb;
Y84_et_zero <= Y75_et_zero;
Y75_pos <= Y66_pos;
Y75_neg <= Y66_neg;
Y75_msb <= Y66_msb;
Y75_et_zero <= Y66_et_zero;
Y66_pos <= Y57_pos;
Y66_neg <= Y57_neg;
Y66_msb <= Y57_msb;
Y66_et_zero <= Y57_et_zero;
Y57_pos <= Y48_pos;
Y57_neg <= Y48_neg;
Y57_msb <= Y48_msb;
Y57_et_zero <= Y48_et_zero;
Y48_pos <= Y58_pos;
Y48_neg <= Y58_neg;
Y48_msb <= Y58_msb;
Y48_et_zero <= Y58_et_zero;
Y58_pos <= Y67_pos;
Y58_neg <= Y67_neg;
Y58_msb <= Y67_msb;
Y58_et_zero <= Y67_et_zero;
Y67_pos <= Y76_pos;
Y67_neg <= Y76_neg;
Y67_msb <= Y76_msb;
Y67_et_zero <= Y76_et_zero;
Y76_pos <= Y85_pos;
Y76_neg <= Y85_neg;
Y76_msb <= Y85_msb;
Y76_et_zero <= Y85_et_zero;
Y85_pos <= Y86_pos;
Y85_neg <= Y86_neg;
Y85_msb <= Y86_msb;
Y85_et_zero <= Y86_et_zero;
Y86_pos <= Y77_pos;
Y86_neg <= Y77_neg;
Y86_msb <= Y77_msb;
Y86_et_zero <= Y77_et_zero;
Y77_pos <= Y68_pos;
Y77_neg <= Y68_neg;
Y77_msb <= Y68_msb;
Y77_et_zero <= Y68_et_zero;
Y68_pos <= Y78_pos;
Y68_neg <= Y78_neg;
Y68_msb <= Y78_msb;
Y68_et_zero <= Y78_et_zero;
Y78_pos <= Y87_pos;
Y78_neg <= Y87_neg;
Y78_msb <= Y87_msb;
Y78_et_zero <= Y87_et_zero;
Y87_pos <= Y88_pos;
Y87_neg <= Y88_neg;
Y87_msb <= Y88_msb;
Y87_et_zero <= Y88_et_zero;
Y88_pos <= 0;
Y88_neg <= 0;
Y88_msb <= 0;
Y88_et_zero <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_diff <= 0; Y11_1 <= 0;
end
else if (enable) begin // Need to sign extend Y11 to 12 bits
Y11_diff <= {Y11[10], Y11} - Y11_previous;
Y11_1 <= Y11[10] ? { 1'b1, Y11 } : { 1'b0, Y11 };
end
end
always @(posedge clk)
begin
if (rst)
Y11_bits_pos <= 0;
else if (Y11_1_pos[10] == 1)
Y11_bits_pos <= 11;
else if (Y11_1_pos[9] == 1)
Y11_bits_pos <= 10;
else if (Y11_1_pos[8] == 1)
Y11_bits_pos <= 9;
else if (Y11_1_pos[7] == 1)
Y11_bits_pos <= 8;
else if (Y11_1_pos[6] == 1)
Y11_bits_pos <= 7;
else if (Y11_1_pos[5] == 1)
Y11_bits_pos <= 6;
else if (Y11_1_pos[4] == 1)
Y11_bits_pos <= 5;
else if (Y11_1_pos[3] == 1)
Y11_bits_pos <= 4;
else if (Y11_1_pos[2] == 1)
Y11_bits_pos <= 3;
else if (Y11_1_pos[1] == 1)
Y11_bits_pos <= 2;
else if (Y11_1_pos[0] == 1)
Y11_bits_pos <= 1;
else
Y11_bits_pos <= 0;
end
always @(posedge clk)
begin
if (rst)
Y11_bits_neg <= 0;
else if (Y11_1_neg[10] == 0)
Y11_bits_neg <= 11;
else if (Y11_1_neg[9] == 0)
Y11_bits_neg <= 10;
else if (Y11_1_neg[8] == 0)
Y11_bits_neg <= 9;
else if (Y11_1_neg[7] == 0)
Y11_bits_neg <= 8;
else if (Y11_1_neg[6] == 0)
Y11_bits_neg <= 7;
else if (Y11_1_neg[5] == 0)
Y11_bits_neg <= 6;
else if (Y11_1_neg[4] == 0)
Y11_bits_neg <= 5;
else if (Y11_1_neg[3] == 0)
Y11_bits_neg <= 4;
else if (Y11_1_neg[2] == 0)
Y11_bits_neg <= 3;
else if (Y11_1_neg[1] == 0)
Y11_bits_neg <= 2;
else if (Y11_1_neg[0] == 0)
Y11_bits_neg <= 1;
else
Y11_bits_neg <= 0;
end
always @(posedge clk)
begin
if (rst)
Y12_bits_pos <= 0;
else if (Y12_pos[9] == 1)
Y12_bits_pos <= 10;
else if (Y12_pos[8] == 1)
Y12_bits_pos <= 9;
else if (Y12_pos[7] == 1)
Y12_bits_pos <= 8;
else if (Y12_pos[6] == 1)
Y12_bits_pos <= 7;
else if (Y12_pos[5] == 1)
Y12_bits_pos <= 6;
else if (Y12_pos[4] == 1)
Y12_bits_pos <= 5;
else if (Y12_pos[3] == 1)
Y12_bits_pos <= 4;
else if (Y12_pos[2] == 1)
Y12_bits_pos <= 3;
else if (Y12_pos[1] == 1)
Y12_bits_pos <= 2;
else if (Y12_pos[0] == 1)
Y12_bits_pos <= 1;
else
Y12_bits_pos <= 0;
end
always @(posedge clk)
begin
if (rst)
Y12_bits_neg <= 0;
else if (Y12_neg[9] == 0)
Y12_bits_neg <= 10;
else if (Y12_neg[8] == 0)
Y12_bits_neg <= 9;
else if (Y12_neg[7] == 0)
Y12_bits_neg <= 8;
else if (Y12_neg[6] == 0)
Y12_bits_neg <= 7;
else if (Y12_neg[5] == 0)
Y12_bits_neg <= 6;
else if (Y12_neg[4] == 0)
Y12_bits_neg <= 5;
else if (Y12_neg[3] == 0)
Y12_bits_neg <= 4;
else if (Y12_neg[2] == 0)
Y12_bits_neg <= 3;
else if (Y12_neg[1] == 0)
Y12_bits_neg <= 2;
else if (Y12_neg[0] == 0)
Y12_bits_neg <= 1;
else
Y12_bits_neg <= 0;
end
always @(posedge clk)
begin
if (rst) begin
enable_module <= 0;
end
else if (enable) begin
enable_module <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
enable_latch_7 <= 0;
end
else if (block_counter == 68) begin
enable_latch_7 <= 0;
end
else if (enable_6) begin
enable_latch_7 <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
enable_latch_8 <= 0;
end
else if (enable_7) begin
enable_latch_8 <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
enable_1 <= 0; enable_2 <= 0; enable_3 <= 0;
enable_4 <= 0; enable_5 <= 0; enable_6 <= 0;
enable_7 <= 0; enable_8 <= 0; enable_9 <= 0;
enable_10 <= 0; enable_11 <= 0; enable_12 <= 0;
enable_13 <= 0;
end
else begin
enable_1 <= enable; enable_2 <= enable_1; enable_3 <= enable_2;
enable_4 <= enable_3; enable_5 <= enable_4; enable_6 <= enable_5;
enable_7 <= enable_6; enable_8 <= enable_7; enable_9 <= enable_8;
enable_10 <= enable_9; enable_11 <= enable_10; enable_12 <= enable_11;
enable_13 <= enable_12;
end
end
/* These Y DC and AC code lengths, run lengths, and bit codes
were created from the Huffman table entries in the JPEG file header.
For different Huffman tables for different images, these values
below will need to be changed. I created a matlab file to automatically
create these entries from the already encoded JPEG image. This matlab program
won't be any help if you're starting from scratch with a .tif or other
raw image file format. The values below come from a Huffman table, they
do not actually create the Huffman table based on the probabilities of
each code created from the image data. You will need another program to
create the optimal Huffman table, or you can go with a generic Huffman table,
which will have slightly less than the best compression.*/
always @(posedge clk)
begin
Y_DC_code_length[0] <= 2;
Y_DC_code_length[1] <= 2;
Y_DC_code_length[2] <= 2;
Y_DC_code_length[3] <= 3;
Y_DC_code_length[4] <= 4;
Y_DC_code_length[5] <= 5;
Y_DC_code_length[6] <= 6;
Y_DC_code_length[7] <= 7;
Y_DC_code_length[8] <= 8;
Y_DC_code_length[9] <= 9;
Y_DC_code_length[10] <= 10;
Y_DC_code_length[11] <= 11;
Y_DC[0] <= 11'b00000000000;
Y_DC[1] <= 11'b01000000000;
Y_DC[2] <= 11'b10000000000;
Y_DC[3] <= 11'b11000000000;
Y_DC[4] <= 11'b11100000000;
Y_DC[5] <= 11'b11110000000;
Y_DC[6] <= 11'b11111000000;
Y_DC[7] <= 11'b11111100000;
Y_DC[8] <= 11'b11111110000;
Y_DC[9] <= 11'b11111111000;
Y_DC[10] <= 11'b11111111100;
Y_DC[11] <= 11'b11111111110;
Y_AC_code_length[0] <= 2;
Y_AC_code_length[1] <= 2;
Y_AC_code_length[2] <= 3;
Y_AC_code_length[3] <= 4;
Y_AC_code_length[4] <= 4;
Y_AC_code_length[5] <= 4;
Y_AC_code_length[6] <= 5;
Y_AC_code_length[7] <= 5;
Y_AC_code_length[8] <= 5;
Y_AC_code_length[9] <= 6;
Y_AC_code_length[10] <= 6;
Y_AC_code_length[11] <= 7;
Y_AC_code_length[12] <= 7;
Y_AC_code_length[13] <= 7;
Y_AC_code_length[14] <= 7;
Y_AC_code_length[15] <= 8;
Y_AC_code_length[16] <= 8;
Y_AC_code_length[17] <= 8;
Y_AC_code_length[18] <= 9;
Y_AC_code_length[19] <= 9;
Y_AC_code_length[20] <= 9;
Y_AC_code_length[21] <= 9;
Y_AC_code_length[22] <= 9;
Y_AC_code_length[23] <= 10;
Y_AC_code_length[24] <= 10;
Y_AC_code_length[25] <= 10;
Y_AC_code_length[26] <= 10;
Y_AC_code_length[27] <= 10;
Y_AC_code_length[28] <= 11;
Y_AC_code_length[29] <= 11;
Y_AC_code_length[30] <= 11;
Y_AC_code_length[31] <= 11;
Y_AC_code_length[32] <= 12;
Y_AC_code_length[33] <= 12;
Y_AC_code_length[34] <= 12;
Y_AC_code_length[35] <= 12;
Y_AC_code_length[36] <= 15;
Y_AC_code_length[37] <= 16;
Y_AC_code_length[38] <= 16;
Y_AC_code_length[39] <= 16;
Y_AC_code_length[40] <= 16;
Y_AC_code_length[41] <= 16;
Y_AC_code_length[42] <= 16;
Y_AC_code_length[43] <= 16;
Y_AC_code_length[44] <= 16;
Y_AC_code_length[45] <= 16;
Y_AC_code_length[46] <= 16;
Y_AC_code_length[47] <= 16;
Y_AC_code_length[48] <= 16;
Y_AC_code_length[49] <= 16;
Y_AC_code_length[50] <= 16;
Y_AC_code_length[51] <= 16;
Y_AC_code_length[52] <= 16;
Y_AC_code_length[53] <= 16;
Y_AC_code_length[54] <= 16;
Y_AC_code_length[55] <= 16;
Y_AC_code_length[56] <= 16;
Y_AC_code_length[57] <= 16;
Y_AC_code_length[58] <= 16;
Y_AC_code_length[59] <= 16;
Y_AC_code_length[60] <= 16;
Y_AC_code_length[61] <= 16;
Y_AC_code_length[62] <= 16;
Y_AC_code_length[63] <= 16;
Y_AC_code_length[64] <= 16;
Y_AC_code_length[65] <= 16;
Y_AC_code_length[66] <= 16;
Y_AC_code_length[67] <= 16;
Y_AC_code_length[68] <= 16;
Y_AC_code_length[69] <= 16;
Y_AC_code_length[70] <= 16;
Y_AC_code_length[71] <= 16;
Y_AC_code_length[72] <= 16;
Y_AC_code_length[73] <= 16;
Y_AC_code_length[74] <= 16;
Y_AC_code_length[75] <= 16;
Y_AC_code_length[76] <= 16;
Y_AC_code_length[77] <= 16;
Y_AC_code_length[78] <= 16;
Y_AC_code_length[79] <= 16;
Y_AC_code_length[80] <= 16;
Y_AC_code_length[81] <= 16;
Y_AC_code_length[82] <= 16;
Y_AC_code_length[83] <= 16;
Y_AC_code_length[84] <= 16;
Y_AC_code_length[85] <= 16;
Y_AC_code_length[86] <= 16;
Y_AC_code_length[87] <= 16;
Y_AC_code_length[88] <= 16;
Y_AC_code_length[89] <= 16;
Y_AC_code_length[90] <= 16;
Y_AC_code_length[91] <= 16;
Y_AC_code_length[92] <= 16;
Y_AC_code_length[93] <= 16;
Y_AC_code_length[94] <= 16;
Y_AC_code_length[95] <= 16;
Y_AC_code_length[96] <= 16;
Y_AC_code_length[97] <= 16;
Y_AC_code_length[98] <= 16;
Y_AC_code_length[99] <= 16;
Y_AC_code_length[100] <= 16;
Y_AC_code_length[101] <= 16;
Y_AC_code_length[102] <= 16;
Y_AC_code_length[103] <= 16;
Y_AC_code_length[104] <= 16;
Y_AC_code_length[105] <= 16;
Y_AC_code_length[106] <= 16;
Y_AC_code_length[107] <= 16;
Y_AC_code_length[108] <= 16;
Y_AC_code_length[109] <= 16;
Y_AC_code_length[110] <= 16;
Y_AC_code_length[111] <= 16;
Y_AC_code_length[112] <= 16;
Y_AC_code_length[113] <= 16;
Y_AC_code_length[114] <= 16;
Y_AC_code_length[115] <= 16;
Y_AC_code_length[116] <= 16;
Y_AC_code_length[117] <= 16;
Y_AC_code_length[118] <= 16;
Y_AC_code_length[119] <= 16;
Y_AC_code_length[120] <= 16;
Y_AC_code_length[121] <= 16;
Y_AC_code_length[122] <= 16;
Y_AC_code_length[123] <= 16;
Y_AC_code_length[124] <= 16;
Y_AC_code_length[125] <= 16;
Y_AC_code_length[126] <= 16;
Y_AC_code_length[127] <= 16;
Y_AC_code_length[128] <= 16;
Y_AC_code_length[129] <= 16;
Y_AC_code_length[130] <= 16;
Y_AC_code_length[131] <= 16;
Y_AC_code_length[132] <= 16;
Y_AC_code_length[133] <= 16;
Y_AC_code_length[134] <= 16;
Y_AC_code_length[135] <= 16;
Y_AC_code_length[136] <= 16;
Y_AC_code_length[137] <= 16;
Y_AC_code_length[138] <= 16;
Y_AC_code_length[139] <= 16;
Y_AC_code_length[140] <= 16;
Y_AC_code_length[141] <= 16;
Y_AC_code_length[142] <= 16;
Y_AC_code_length[143] <= 16;
Y_AC_code_length[144] <= 16;
Y_AC_code_length[145] <= 16;
Y_AC_code_length[146] <= 16;
Y_AC_code_length[147] <= 16;
Y_AC_code_length[148] <= 16;
Y_AC_code_length[149] <= 16;
Y_AC_code_length[150] <= 16;
Y_AC_code_length[151] <= 16;
Y_AC_code_length[152] <= 16;
Y_AC_code_length[153] <= 16;
Y_AC_code_length[154] <= 16;
Y_AC_code_length[155] <= 16;
Y_AC_code_length[156] <= 16;
Y_AC_code_length[157] <= 16;
Y_AC_code_length[158] <= 16;
Y_AC_code_length[159] <= 16;
Y_AC_code_length[160] <= 16;
Y_AC_code_length[161] <= 16;
Y_AC[0] <= 16'b0000000000000000;
Y_AC[1] <= 16'b0100000000000000;
Y_AC[2] <= 16'b1000000000000000;
Y_AC[3] <= 16'b1010000000000000;
Y_AC[4] <= 16'b1011000000000000;
Y_AC[5] <= 16'b1100000000000000;
Y_AC[6] <= 16'b1101000000000000;
Y_AC[7] <= 16'b1101100000000000;
Y_AC[8] <= 16'b1110000000000000;
Y_AC[9] <= 16'b1110100000000000;
Y_AC[10] <= 16'b1110110000000000;
Y_AC[11] <= 16'b1111000000000000;
Y_AC[12] <= 16'b1111001000000000;
Y_AC[13] <= 16'b1111010000000000;
Y_AC[14] <= 16'b1111011000000000;
Y_AC[15] <= 16'b1111100000000000;
Y_AC[16] <= 16'b1111100100000000;
Y_AC[17] <= 16'b1111101000000000;
Y_AC[18] <= 16'b1111101100000000;
Y_AC[19] <= 16'b1111101110000000;
Y_AC[20] <= 16'b1111110000000000;
Y_AC[21] <= 16'b1111110010000000;
Y_AC[22] <= 16'b1111110100000000;
Y_AC[23] <= 16'b1111110110000000;
Y_AC[24] <= 16'b1111110111000000;
Y_AC[25] <= 16'b1111111000000000;
Y_AC[26] <= 16'b1111111001000000;
Y_AC[27] <= 16'b1111111010000000;
Y_AC[28] <= 16'b1111111011000000;
Y_AC[29] <= 16'b1111111011100000;
Y_AC[30] <= 16'b1111111100000000;
Y_AC[31] <= 16'b1111111100100000;
Y_AC[32] <= 16'b1111111101000000;
Y_AC[33] <= 16'b1111111101010000;
Y_AC[34] <= 16'b1111111101100000;
Y_AC[35] <= 16'b1111111101110000;
Y_AC[36] <= 16'b1111111110000000;
Y_AC[37] <= 16'b1111111110000010;
Y_AC[38] <= 16'b1111111110000011;
Y_AC[39] <= 16'b1111111110000100;
Y_AC[40] <= 16'b1111111110000101;
Y_AC[41] <= 16'b1111111110000110;
Y_AC[42] <= 16'b1111111110000111;
Y_AC[43] <= 16'b1111111110001000;
Y_AC[44] <= 16'b1111111110001001;
Y_AC[45] <= 16'b1111111110001010;
Y_AC[46] <= 16'b1111111110001011;
Y_AC[47] <= 16'b1111111110001100;
Y_AC[48] <= 16'b1111111110001101;
Y_AC[49] <= 16'b1111111110001110;
Y_AC[50] <= 16'b1111111110001111;
Y_AC[51] <= 16'b1111111110010000;
Y_AC[52] <= 16'b1111111110010001;
Y_AC[53] <= 16'b1111111110010010;
Y_AC[54] <= 16'b1111111110010011;
Y_AC[55] <= 16'b1111111110010100;
Y_AC[56] <= 16'b1111111110010101;
Y_AC[57] <= 16'b1111111110010110;
Y_AC[58] <= 16'b1111111110010111;
Y_AC[59] <= 16'b1111111110011000;
Y_AC[60] <= 16'b1111111110011001;
Y_AC[61] <= 16'b1111111110011010;
Y_AC[62] <= 16'b1111111110011011;
Y_AC[63] <= 16'b1111111110011100;
Y_AC[64] <= 16'b1111111110011101;
Y_AC[65] <= 16'b1111111110011110;
Y_AC[66] <= 16'b1111111110011111;
Y_AC[67] <= 16'b1111111110100000;
Y_AC[68] <= 16'b1111111110100001;
Y_AC[69] <= 16'b1111111110100010;
Y_AC[70] <= 16'b1111111110100011;
Y_AC[71] <= 16'b1111111110100100;
Y_AC[72] <= 16'b1111111110100101;
Y_AC[73] <= 16'b1111111110100110;
Y_AC[74] <= 16'b1111111110100111;
Y_AC[75] <= 16'b1111111110101000;
Y_AC[76] <= 16'b1111111110101001;
Y_AC[77] <= 16'b1111111110101010;
Y_AC[78] <= 16'b1111111110101011;
Y_AC[79] <= 16'b1111111110101100;
Y_AC[80] <= 16'b1111111110101101;
Y_AC[81] <= 16'b1111111110101110;
Y_AC[82] <= 16'b1111111110101111;
Y_AC[83] <= 16'b1111111110110000;
Y_AC[84] <= 16'b1111111110110001;
Y_AC[85] <= 16'b1111111110110010;
Y_AC[86] <= 16'b1111111110110011;
Y_AC[87] <= 16'b1111111110110100;
Y_AC[88] <= 16'b1111111110110101;
Y_AC[89] <= 16'b1111111110110110;
Y_AC[90] <= 16'b1111111110110111;
Y_AC[91] <= 16'b1111111110111000;
Y_AC[92] <= 16'b1111111110111001;
Y_AC[93] <= 16'b1111111110111010;
Y_AC[94] <= 16'b1111111110111011;
Y_AC[95] <= 16'b1111111110111100;
Y_AC[96] <= 16'b1111111110111101;
Y_AC[97] <= 16'b1111111110111110;
Y_AC[98] <= 16'b1111111110111111;
Y_AC[99] <= 16'b1111111111000000;
Y_AC[100] <= 16'b1111111111000001;
Y_AC[101] <= 16'b1111111111000010;
Y_AC[102] <= 16'b1111111111000011;
Y_AC[103] <= 16'b1111111111000100;
Y_AC[104] <= 16'b1111111111000101;
Y_AC[105] <= 16'b1111111111000110;
Y_AC[106] <= 16'b1111111111000111;
Y_AC[107] <= 16'b1111111111001000;
Y_AC[108] <= 16'b1111111111001001;
Y_AC[109] <= 16'b1111111111001010;
Y_AC[110] <= 16'b1111111111001011;
Y_AC[111] <= 16'b1111111111001100;
Y_AC[112] <= 16'b1111111111001101;
Y_AC[113] <= 16'b1111111111001110;
Y_AC[114] <= 16'b1111111111001111;
Y_AC[115] <= 16'b1111111111010000;
Y_AC[116] <= 16'b1111111111010001;
Y_AC[117] <= 16'b1111111111010010;
Y_AC[118] <= 16'b1111111111010011;
Y_AC[119] <= 16'b1111111111010100;
Y_AC[120] <= 16'b1111111111010101;
Y_AC[121] <= 16'b1111111111010110;
Y_AC[122] <= 16'b1111111111010111;
Y_AC[123] <= 16'b1111111111011000;
Y_AC[124] <= 16'b1111111111011001;
Y_AC[125] <= 16'b1111111111011010;
Y_AC[126] <= 16'b1111111111011011;
Y_AC[127] <= 16'b1111111111011100;
Y_AC[128] <= 16'b1111111111011101;
Y_AC[129] <= 16'b1111111111011110;
Y_AC[130] <= 16'b1111111111011111;
Y_AC[131] <= 16'b1111111111100000;
Y_AC[132] <= 16'b1111111111100001;
Y_AC[133] <= 16'b1111111111100010;
Y_AC[134] <= 16'b1111111111100011;
Y_AC[135] <= 16'b1111111111100100;
Y_AC[136] <= 16'b1111111111100101;
Y_AC[137] <= 16'b1111111111100110;
Y_AC[138] <= 16'b1111111111100111;
Y_AC[139] <= 16'b1111111111101000;
Y_AC[140] <= 16'b1111111111101001;
Y_AC[141] <= 16'b1111111111101010;
Y_AC[142] <= 16'b1111111111101011;
Y_AC[143] <= 16'b1111111111101100;
Y_AC[144] <= 16'b1111111111101101;
Y_AC[145] <= 16'b1111111111101110;
Y_AC[146] <= 16'b1111111111101111;
Y_AC[147] <= 16'b1111111111110000;
Y_AC[148] <= 16'b1111111111110001;
Y_AC[149] <= 16'b1111111111110010;
Y_AC[150] <= 16'b1111111111110011;
Y_AC[151] <= 16'b1111111111110100;
Y_AC[152] <= 16'b1111111111110101;
Y_AC[153] <= 16'b1111111111110110;
Y_AC[154] <= 16'b1111111111110111;
Y_AC[155] <= 16'b1111111111111000;
Y_AC[156] <= 16'b1111111111111001;
Y_AC[157] <= 16'b1111111111111010;
Y_AC[158] <= 16'b1111111111111011;
Y_AC[159] <= 16'b1111111111111100;
Y_AC[160] <= 16'b1111111111111101;
Y_AC[161] <= 16'b1111111111111110;
Y_AC_run_code[1] <= 0;
Y_AC_run_code[2] <= 1;
Y_AC_run_code[3] <= 2;
Y_AC_run_code[0] <= 3;
Y_AC_run_code[4] <= 4;
Y_AC_run_code[17] <= 5;
Y_AC_run_code[5] <= 6;
Y_AC_run_code[18] <= 7;
Y_AC_run_code[33] <= 8;
Y_AC_run_code[49] <= 9;
Y_AC_run_code[65] <= 10;
Y_AC_run_code[6] <= 11;
Y_AC_run_code[19] <= 12;
Y_AC_run_code[81] <= 13;
Y_AC_run_code[97] <= 14;
Y_AC_run_code[7] <= 15;
Y_AC_run_code[34] <= 16;
Y_AC_run_code[113] <= 17;
Y_AC_run_code[20] <= 18;
Y_AC_run_code[50] <= 19;
Y_AC_run_code[129] <= 20;
Y_AC_run_code[145] <= 21;
Y_AC_run_code[161] <= 22;
Y_AC_run_code[8] <= 23;
Y_AC_run_code[35] <= 24;
Y_AC_run_code[66] <= 25;
Y_AC_run_code[177] <= 26;
Y_AC_run_code[193] <= 27;
Y_AC_run_code[21] <= 28;
Y_AC_run_code[82] <= 29;
Y_AC_run_code[209] <= 30;
Y_AC_run_code[240] <= 31;
Y_AC_run_code[36] <= 32;
Y_AC_run_code[51] <= 33;
Y_AC_run_code[98] <= 34;
Y_AC_run_code[114] <= 35;
Y_AC_run_code[130] <= 36;
Y_AC_run_code[9] <= 37;
Y_AC_run_code[10] <= 38;
Y_AC_run_code[22] <= 39;
Y_AC_run_code[23] <= 40;
Y_AC_run_code[24] <= 41;
Y_AC_run_code[25] <= 42;
Y_AC_run_code[26] <= 43;
Y_AC_run_code[37] <= 44;
Y_AC_run_code[38] <= 45;
Y_AC_run_code[39] <= 46;
Y_AC_run_code[40] <= 47;
Y_AC_run_code[41] <= 48;
Y_AC_run_code[42] <= 49;
Y_AC_run_code[52] <= 50;
Y_AC_run_code[53] <= 51;
Y_AC_run_code[54] <= 52;
Y_AC_run_code[55] <= 53;
Y_AC_run_code[56] <= 54;
Y_AC_run_code[57] <= 55;
Y_AC_run_code[58] <= 56;
Y_AC_run_code[67] <= 57;
Y_AC_run_code[68] <= 58;
Y_AC_run_code[69] <= 59;
Y_AC_run_code[70] <= 60;
Y_AC_run_code[71] <= 61;
Y_AC_run_code[72] <= 62;
Y_AC_run_code[73] <= 63;
Y_AC_run_code[74] <= 64;
Y_AC_run_code[83] <= 65;
Y_AC_run_code[84] <= 66;
Y_AC_run_code[85] <= 67;
Y_AC_run_code[86] <= 68;
Y_AC_run_code[87] <= 69;
Y_AC_run_code[88] <= 70;
Y_AC_run_code[89] <= 71;
Y_AC_run_code[90] <= 72;
Y_AC_run_code[99] <= 73;
Y_AC_run_code[100] <= 74;
Y_AC_run_code[101] <= 75;
Y_AC_run_code[102] <= 76;
Y_AC_run_code[103] <= 77;
Y_AC_run_code[104] <= 78;
Y_AC_run_code[105] <= 79;
Y_AC_run_code[106] <= 80;
Y_AC_run_code[115] <= 81;
Y_AC_run_code[116] <= 82;
Y_AC_run_code[117] <= 83;
Y_AC_run_code[118] <= 84;
Y_AC_run_code[119] <= 85;
Y_AC_run_code[120] <= 86;
Y_AC_run_code[121] <= 87;
Y_AC_run_code[122] <= 88;
Y_AC_run_code[131] <= 89;
Y_AC_run_code[132] <= 90;
Y_AC_run_code[133] <= 91;
Y_AC_run_code[134] <= 92;
Y_AC_run_code[135] <= 93;
Y_AC_run_code[136] <= 94;
Y_AC_run_code[137] <= 95;
Y_AC_run_code[138] <= 96;
Y_AC_run_code[146] <= 97;
Y_AC_run_code[147] <= 98;
Y_AC_run_code[148] <= 99;
Y_AC_run_code[149] <= 100;
Y_AC_run_code[150] <= 101;
Y_AC_run_code[151] <= 102;
Y_AC_run_code[152] <= 103;
Y_AC_run_code[153] <= 104;
Y_AC_run_code[154] <= 105;
Y_AC_run_code[162] <= 106;
Y_AC_run_code[163] <= 107;
Y_AC_run_code[164] <= 108;
Y_AC_run_code[165] <= 109;
Y_AC_run_code[166] <= 110;
Y_AC_run_code[167] <= 111;
Y_AC_run_code[168] <= 112;
Y_AC_run_code[169] <= 113;
Y_AC_run_code[170] <= 114;
Y_AC_run_code[178] <= 115;
Y_AC_run_code[179] <= 116;
Y_AC_run_code[180] <= 117;
Y_AC_run_code[181] <= 118;
Y_AC_run_code[182] <= 119;
Y_AC_run_code[183] <= 120;
Y_AC_run_code[184] <= 121;
Y_AC_run_code[185] <= 122;
Y_AC_run_code[186] <= 123;
Y_AC_run_code[194] <= 124;
Y_AC_run_code[195] <= 125;
Y_AC_run_code[196] <= 126;
Y_AC_run_code[197] <= 127;
Y_AC_run_code[198] <= 128;
Y_AC_run_code[199] <= 129;
Y_AC_run_code[200] <= 130;
Y_AC_run_code[201] <= 131;
Y_AC_run_code[202] <= 132;
Y_AC_run_code[210] <= 133;
Y_AC_run_code[211] <= 134;
Y_AC_run_code[212] <= 135;
Y_AC_run_code[213] <= 136;
Y_AC_run_code[214] <= 137;
Y_AC_run_code[215] <= 138;
Y_AC_run_code[216] <= 139;
Y_AC_run_code[217] <= 140;
Y_AC_run_code[218] <= 141;
Y_AC_run_code[225] <= 142;
Y_AC_run_code[226] <= 143;
Y_AC_run_code[227] <= 144;
Y_AC_run_code[228] <= 145;
Y_AC_run_code[229] <= 146;
Y_AC_run_code[230] <= 147;
Y_AC_run_code[231] <= 148;
Y_AC_run_code[232] <= 149;
Y_AC_run_code[233] <= 150;
Y_AC_run_code[234] <= 151;
Y_AC_run_code[241] <= 152;
Y_AC_run_code[242] <= 153;
Y_AC_run_code[243] <= 154;
Y_AC_run_code[244] <= 155;
Y_AC_run_code[245] <= 156;
Y_AC_run_code[246] <= 157;
Y_AC_run_code[247] <= 158;
Y_AC_run_code[248] <= 159;
Y_AC_run_code[249] <= 160;
Y_AC_run_code[250] <= 161;
Y_AC_run_code[16] <= 0;
Y_AC_run_code[32] <= 0;
Y_AC_run_code[48] <= 0;
Y_AC_run_code[64] <= 0;
Y_AC_run_code[80] <= 0;
Y_AC_run_code[96] <= 0;
Y_AC_run_code[112] <= 0;
Y_AC_run_code[128] <= 0;
Y_AC_run_code[144] <= 0;
Y_AC_run_code[160] <= 0;
Y_AC_run_code[176] <= 0;
Y_AC_run_code[192] <= 0;
Y_AC_run_code[208] <= 0;
Y_AC_run_code[224] <= 0;
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[31] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[31] <= JPEG_bs_5[31];
else if (enable_module && orc_8 == 0)
JPEG_bitstream[31] <= JPEG_bs_5[31];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[30] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[30] <= JPEG_bs_5[30];
else if (enable_module && orc_8 <= 1)
JPEG_bitstream[30] <= JPEG_bs_5[30];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[29] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[29] <= JPEG_bs_5[29];
else if (enable_module && orc_8 <= 2)
JPEG_bitstream[29] <= JPEG_bs_5[29];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[28] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[28] <= JPEG_bs_5[28];
else if (enable_module && orc_8 <= 3)
JPEG_bitstream[28] <= JPEG_bs_5[28];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[27] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[27] <= JPEG_bs_5[27];
else if (enable_module && orc_8 <= 4)
JPEG_bitstream[27] <= JPEG_bs_5[27];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[26] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[26] <= JPEG_bs_5[26];
else if (enable_module && orc_8 <= 5)
JPEG_bitstream[26] <= JPEG_bs_5[26];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[25] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[25] <= JPEG_bs_5[25];
else if (enable_module && orc_8 <= 6)
JPEG_bitstream[25] <= JPEG_bs_5[25];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[24] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[24] <= JPEG_bs_5[24];
else if (enable_module && orc_8 <= 7)
JPEG_bitstream[24] <= JPEG_bs_5[24];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[23] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[23] <= JPEG_bs_5[23];
else if (enable_module && orc_8 <= 8)
JPEG_bitstream[23] <= JPEG_bs_5[23];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[22] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[22] <= JPEG_bs_5[22];
else if (enable_module && orc_8 <= 9)
JPEG_bitstream[22] <= JPEG_bs_5[22];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[21] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[21] <= JPEG_bs_5[21];
else if (enable_module && orc_8 <= 10)
JPEG_bitstream[21] <= JPEG_bs_5[21];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[20] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[20] <= JPEG_bs_5[20];
else if (enable_module && orc_8 <= 11)
JPEG_bitstream[20] <= JPEG_bs_5[20];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[19] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[19] <= JPEG_bs_5[19];
else if (enable_module && orc_8 <= 12)
JPEG_bitstream[19] <= JPEG_bs_5[19];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[18] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[18] <= JPEG_bs_5[18];
else if (enable_module && orc_8 <= 13)
JPEG_bitstream[18] <= JPEG_bs_5[18];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[17] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[17] <= JPEG_bs_5[17];
else if (enable_module && orc_8 <= 14)
JPEG_bitstream[17] <= JPEG_bs_5[17];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[16] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[16] <= JPEG_bs_5[16];
else if (enable_module && orc_8 <= 15)
JPEG_bitstream[16] <= JPEG_bs_5[16];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[15] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[15] <= JPEG_bs_5[15];
else if (enable_module && orc_8 <= 16)
JPEG_bitstream[15] <= JPEG_bs_5[15];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[14] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[14] <= JPEG_bs_5[14];
else if (enable_module && orc_8 <= 17)
JPEG_bitstream[14] <= JPEG_bs_5[14];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[13] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[13] <= JPEG_bs_5[13];
else if (enable_module && orc_8 <= 18)
JPEG_bitstream[13] <= JPEG_bs_5[13];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[12] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[12] <= JPEG_bs_5[12];
else if (enable_module && orc_8 <= 19)
JPEG_bitstream[12] <= JPEG_bs_5[12];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[11] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[11] <= JPEG_bs_5[11];
else if (enable_module && orc_8 <= 20)
JPEG_bitstream[11] <= JPEG_bs_5[11];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[10] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[10] <= JPEG_bs_5[10];
else if (enable_module && orc_8 <= 21)
JPEG_bitstream[10] <= JPEG_bs_5[10];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[9] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[9] <= JPEG_bs_5[9];
else if (enable_module && orc_8 <= 22)
JPEG_bitstream[9] <= JPEG_bs_5[9];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[8] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[8] <= JPEG_bs_5[8];
else if (enable_module && orc_8 <= 23)
JPEG_bitstream[8] <= JPEG_bs_5[8];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[7] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[7] <= JPEG_bs_5[7];
else if (enable_module && orc_8 <= 24)
JPEG_bitstream[7] <= JPEG_bs_5[7];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[6] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[6] <= JPEG_bs_5[6];
else if (enable_module && orc_8 <= 25)
JPEG_bitstream[6] <= JPEG_bs_5[6];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[5] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[5] <= JPEG_bs_5[5];
else if (enable_module && orc_8 <= 26)
JPEG_bitstream[5] <= JPEG_bs_5[5];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[4] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[4] <= JPEG_bs_5[4];
else if (enable_module && orc_8 <= 27)
JPEG_bitstream[4] <= JPEG_bs_5[4];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[3] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[3] <= JPEG_bs_5[3];
else if (enable_module && orc_8 <= 28)
JPEG_bitstream[3] <= JPEG_bs_5[3];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[2] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[2] <= JPEG_bs_5[2];
else if (enable_module && orc_8 <= 29)
JPEG_bitstream[2] <= JPEG_bs_5[2];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[1] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[1] <= JPEG_bs_5[1];
else if (enable_module && orc_8 <= 30)
JPEG_bitstream[1] <= JPEG_bs_5[1];
end
always @(posedge clk)
begin
if (rst)
JPEG_bitstream[0] <= 0;
else if (enable_module && rollover_7)
JPEG_bitstream[0] <= JPEG_bs_5[0];
else if (enable_module && orc_8 <= 31)
JPEG_bitstream[0] <= JPEG_bs_5[0];
end
endmodule
|
// MBT 11/9/2014
//
// 1 read-port, 1 write-port ram
//
// reads are asynchronous
//
`include "bsg_defines.v"
module bsg_mem_1r1w #(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=0
)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r_data_o
);
bsg_mem_1r1w_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.*);
//synopsys translate_off
initial
begin
if (width_p*els_p > 256)
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)"
,width_p,els_p,read_write_same_addr_p,harden_p);
end
always_ff @(negedge w_clk_i)
if (w_v_i===1'b1)
begin
assert ((w_reset_i === 'X) || (w_reset_i === 1'b1) || (w_addr_i < els_p))
else $error("Invalid address %x to %m of size %x (w_reset_i=%b, w_v_i=%b)\n", w_addr_i, els_p, w_reset_i, w_v_i);
assert ((w_reset_i === 'X) || (w_reset_i === 1'b1) || !(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address %x (w_v_i = %b, w_reset_i = %b)",w_addr_i,w_v_i,w_reset_i);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_SYMBOL_V
`define SKY130_FD_SC_HD__DLYMETAL6S6S_SYMBOL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlymetal6s6s (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_SYMBOL_V
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: DynamicDelay_Start.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module DynamicDelay_Start (
address,
clock,
q);
input [0:0] address;
input clock;
output [127:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "DynamicDelay_Start.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "1"
// Retrieval info: PRIVATE: WidthData NUMERIC "128"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "DynamicDelay_Start.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 1 0 INPUT NODEFVAL address[0..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
// Retrieval info: CONNECT: @address_a 0 0 1 0 address 0 0 1 0
// Retrieval info: CONNECT: q 0 0 128 0 @q_a 0 0 128 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
////////////////////////////////////////////////////////////////////////////////////////////////////
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
// 02111-1307, USA.
//
// ©2013 - Roman Ovseitsev <[email protected]>
////////////////////////////////////////////////////////////////////////////////////////////////////
//##################################################################################################
//
// Helper modules for working with clock signals.
//
//##################################################################################################
`timescale 1ns / 1ps
//**************************************************************************************************
//
// Generates clock frequency. By default 100MHz from 12MHz clock signal is generated.
//
//**************************************************************************************************
module ClkGen (clk_i, clk_o, clk180_o);
parameter MUL = 25;
parameter DIV = 3;
parameter real IN_FREQ = 12.0;
input clk_i;
output clk_o;
output clk180_o;
localparam real CLK_PERIOD = 1000.0/IN_FREQ;
DCM_SP
#(
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(DIV), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(MUL), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(CLK_PERIOD), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
DCM_SP_inst
(
.CLKFX(clk_o), // DCM CLK synthesis out (M/D)
.CLKFX180(clk180_o), // 180 degree CLK synthesis out
.CLKIN(clk_i), // Clock input (from IBUFG, BUFG or DCM)
.RST(1'b0) // DCM asynchronous reset input
);
endmodule
//**************************************************************************************************
// Convenience module for forwarding low skew copy of an internal clock to output pins.
// Useful when working with high frequencies.
//
// For a detailed explanation see Xilinx ug331.pdf p.116 Figures 3-28, 3-29.
//**************************************************************************************************
module ClkToPin (clk_i, clk180_i, clk_o);
input clk_i;
input clk180_i;
output clk_o;
ODDR2
#(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
)
ODDR2_inst
(
.Q(clk_o), // 1-bit DDR output data
.C0(clk_i), // 1-bit clock input
.C1(clk180_i), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
endmodule
//**************************************************************************************************
// n-stage synchronizer
//**************************************************************************************************
module SyncToClock (clk_i, unsynced_i, synced_o);
parameter syncStages = 2; //number of stages in syncing register
input clk_i;
input unsynced_i;
output synced_o;
reg [syncStages:1] sync_r;
always @(posedge clk_i)
sync_r <= {sync_r[syncStages-1:1], unsynced_i};
assign synced_o = sync_r[syncStages];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:32:12 01/08/2011
// Design Name:
// Module Name: rtc_srtc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rtc (
input clkin,
input pgm_we,
input [55:0] rtc_data_in,
input we1,
input [59:0] rtc_data_in1,
output [59:0] rtc_data
);
reg [59:0] rtc_data_r;
reg [59:0] rtc_data_out_r;
reg [1:0] pgm_we_sreg;
always @(posedge clkin) pgm_we_sreg <= {pgm_we_sreg[0], pgm_we};
wire pgm_we_rising = (pgm_we_sreg[1:0] == 2'b01);
reg [2:0] we1_sreg;
always @(posedge clkin) we1_sreg <= {we1_sreg[1:0], we1};
wire we1_rising = (we1_sreg[2:1] == 2'b01);
reg [31:0] tick_cnt;
always @(posedge clkin) begin
tick_cnt <= tick_cnt + 1;
if((tick_cnt == 22000000) || pgm_we_rising) tick_cnt <= 0;
end
assign rtc_data = rtc_data_out_r;
reg [21:0] rtc_state;
reg carry;
reg [3:0] dom1[11:0];
reg [3:0] dom10[11:0];
reg [3:0] month;
reg [1:0] year;
reg [4:0] dow_day;
reg [3:0] dow_month;
reg [13:0] dow_year;
reg [6:0] dow_year1;
reg [6:0] dow_year100;
reg [15:0] dow_tmp;
parameter [21:0]
STATE_SEC1 = 22'b0000000000000000000001,
STATE_SEC10 = 22'b0000000000000000000010,
STATE_MIN1 = 22'b0000000000000000000100,
STATE_MIN10 = 22'b0000000000000000001000,
STATE_HOUR1 = 22'b0000000000000000010000,
STATE_HOUR10 = 22'b0000000000000000100000,
STATE_DAY1 = 22'b0000000000000001000000,
STATE_DAY10 = 22'b0000000000000010000000,
STATE_MON1 = 22'b0000000000000100000000,
STATE_MON10 = 22'b0000000000001000000000,
STATE_YEAR1 = 22'b0000000000010000000000,
STATE_YEAR10 = 22'b0000000000100000000000,
STATE_YEAR100 = 22'b0000000001000000000000,
STATE_YEAR1000 = 22'b0000000010000000000000,
STATE_DOW0 = 22'b0000000100000000000000,
STATE_DOW1 = 22'b0000001000000000000000,
STATE_DOW2 = 22'b0000010000000000000000,
STATE_DOW3 = 22'b0000100000000000000000,
STATE_DOW4 = 22'b0001000000000000000000,
STATE_DOW5 = 22'b0010000000000000000000,
STATE_LATCH = 22'b0100000000000000000000,
STATE_IDLE = 22'b1000000000000000000000;
initial begin
rtc_state = STATE_IDLE;
dom1[0] = 1; dom10[0] = 3;
dom1[1] = 8; dom10[1] = 2;
dom1[2] = 1; dom10[2] = 3;
dom1[3] = 0; dom10[3] = 3;
dom1[4] = 1; dom10[4] = 3;
dom1[5] = 0; dom10[5] = 3;
dom1[6] = 1; dom10[6] = 3;
dom1[7] = 1; dom10[7] = 3;
dom1[8] = 0; dom10[8] = 3;
dom1[9] = 1; dom10[9] = 3;
dom1[10] = 0; dom10[10] = 3;
dom1[11] = 1; dom10[11] = 3;
month = 0;
rtc_data_r = 60'h220110301000000;
tick_cnt = 0;
end
wire is_leapyear_feb = (month == 1) && (year[1:0] == 2'b00);
always @(posedge clkin) begin
if(!tick_cnt) begin
rtc_state <= STATE_SEC1;
end else begin
case (rtc_state)
STATE_SEC1:
rtc_state <= STATE_SEC10;
STATE_SEC10:
rtc_state <= STATE_MIN1;
STATE_MIN1:
rtc_state <= STATE_MIN10;
STATE_MIN10:
rtc_state <= STATE_HOUR1;
STATE_HOUR1:
rtc_state <= STATE_HOUR10;
STATE_HOUR10:
rtc_state <= STATE_DAY1;
STATE_DAY1:
rtc_state <= STATE_DAY10;
STATE_DAY10:
rtc_state <= STATE_MON1;
STATE_MON1:
rtc_state <= STATE_MON10;
STATE_MON10:
rtc_state <= STATE_YEAR1;
STATE_YEAR1:
rtc_state <= STATE_YEAR10;
STATE_YEAR10:
rtc_state <= STATE_YEAR100;
STATE_YEAR100:
rtc_state <= STATE_YEAR1000;
STATE_YEAR1000:
rtc_state <= STATE_DOW0;
STATE_DOW0:
rtc_state <= STATE_DOW1;
STATE_DOW1:
rtc_state <= STATE_DOW2;
STATE_DOW2:
rtc_state <= STATE_DOW3;
STATE_DOW3:
rtc_state <= STATE_DOW4;
STATE_DOW4:
if(dow_tmp > 13)
rtc_state <= STATE_DOW4;
else
rtc_state <= STATE_DOW5;
STATE_DOW5:
rtc_state <= STATE_LATCH;
STATE_LATCH:
rtc_state <= STATE_IDLE;
default:
rtc_state <= STATE_IDLE;
endcase
end
end
always @(posedge clkin) begin
if(pgm_we_rising) begin
rtc_data_r[55:0] <= rtc_data_in;
end else if (we1_rising) begin
rtc_data_r <= rtc_data_in1;
end else begin
case(rtc_state)
STATE_SEC1: begin
if(rtc_data_r[3:0] == 9) begin
rtc_data_r[3:0] <= 0;
carry <= 1;
end else begin
rtc_data_r[3:0] <= rtc_data_r[3:0] + 1;
carry <= 0;
end
end
STATE_SEC10: begin
if(carry) begin
if(rtc_data_r[7:4] == 5) begin
rtc_data_r[7:4] <= 0;
carry <= 1;
end else begin
rtc_data_r[7:4] <= rtc_data_r[7:4] + 1;
carry <= 0;
end
end
end
STATE_MIN1: begin
if(carry) begin
if(rtc_data_r[11:8] == 9) begin
rtc_data_r[11:8] <= 0;
carry <= 1;
end else begin
rtc_data_r[11:8] <= rtc_data_r[11:8] + 1;
carry <= 0;
end
end
end
STATE_MIN10: begin
if(carry) begin
if(rtc_data_r[15:12] == 5) begin
rtc_data_r[15:12] <= 0;
carry <= 1;
end else begin
rtc_data_r[15:12] <= rtc_data_r[15:12] + 1;
carry <= 0;
end
end
end
STATE_HOUR1: begin
if(carry) begin
if(rtc_data_r[23:20] == 2 && rtc_data_r[19:16] == 3) begin
rtc_data_r[19:16] <= 0;
carry <= 1;
end else if (rtc_data_r[19:16] == 9) begin
rtc_data_r[19:16] <= 0;
carry <= 1;
end else begin
rtc_data_r[19:16] <= rtc_data_r[19:16] + 1;
carry <= 0;
end
end
end
STATE_HOUR10: begin
if(carry) begin
if(rtc_data_r[23:20] == 2) begin
rtc_data_r[23:20] <= 0;
carry <= 1;
end else begin
rtc_data_r[23:20] <= rtc_data_r[23:20] + 1;
carry <= 0;
end
end
end
STATE_DAY1: begin
if(carry) begin
if(rtc_data_r[31:28] == dom10[month]
&& rtc_data_r[27:24] == dom1[month] + is_leapyear_feb) begin
rtc_data_r[27:24] <= 0;
carry <= 1;
end else if (rtc_data_r[27:24] == 9) begin
rtc_data_r[27:24] <= 0;
carry <= 1;
end else begin
rtc_data_r[27:24] <= rtc_data_r[27:24] + 1;
carry <= 0;
end
end
end
STATE_DAY10: begin
if(carry) begin
if(rtc_data_r[31:28] == dom10[month]) begin
rtc_data_r[31:28] <= 0;
rtc_data_r[27:24] <= 1;
carry <= 1;
end else begin
rtc_data_r[31:28] <= rtc_data_r[31:28] + 1;
carry <= 0;
end
end
end
STATE_MON1: begin
if(carry) begin
if(rtc_data_r[39:36] == 1 && rtc_data_r[35:32] == 2) begin
rtc_data_r[35:32] <= 1;
carry <= 1;
end else if (rtc_data_r[35:32] == 9) begin
rtc_data_r[35:32] <= 0;
carry <= 1;
end else begin
rtc_data_r[35:32] <= rtc_data_r[35:32] + 1;
carry <= 0;
end
end
end
STATE_MON10: begin
if(carry) begin
if(rtc_data_r[39:36] == 1) begin
rtc_data_r[39:36] <= 0;
carry <= 1;
end else begin
rtc_data_r[39:36] <= rtc_data_r[39:36] + 1;
carry <= 0;
end
end
end
STATE_YEAR1: begin
month <= rtc_data_r[35:32] + (rtc_data_r[36] ? 10 : 0) - 1;
if(carry) begin
if(rtc_data_r[43:40] == 9) begin
rtc_data_r[43:40] <= 0;
carry <= 1;
end else begin
rtc_data_r[43:40] <= rtc_data_r[43:40] + 1;
carry <= 0;
end
end
end
STATE_YEAR10: begin
if(carry) begin
if(rtc_data_r[47:44] == 9) begin
rtc_data_r[47:44] <= 0;
carry <= 1;
end else begin
rtc_data_r[47:44] <= rtc_data_r[47:44] + 1;
carry <= 0;
end
end
end
STATE_YEAR100: begin
if(carry) begin
if(rtc_data_r[51:48] == 9) begin
rtc_data_r[51:48] <= 0;
carry <= 1;
end else begin
rtc_data_r[51:48] <= rtc_data_r[51:48] + 1;
carry <= 0;
end
end
end
STATE_YEAR1000: begin
if(carry) begin
if(rtc_data_r[55:52] == 9) begin
rtc_data_r[55:52] <= 0;
carry <= 1;
end else begin
rtc_data_r[55:52] <= rtc_data_r[55:52] + 1;
carry <= 0;
end
end
end
STATE_DOW0: begin
dow_year1 <= rtc_data_r[43:40]
+(rtc_data_r[47:44] << 1) + (rtc_data_r[47:44] << 3);
dow_year100 <= rtc_data_r[51:48]
+(rtc_data_r[55:52] << 1) + (rtc_data_r[55:52] << 3);
dow_month <= month + 1;
dow_day <= rtc_data_r[27:24]
+ (rtc_data_r[31:28] << 1)
+ (rtc_data_r[31:28] << 3);
end
STATE_DOW1: begin
year <= dow_year1[1:0];
if(dow_month <= 2) begin
dow_month <= dow_month + 10;
dow_year <= dow_year1
+ (dow_year100 << 2)
+ (dow_year100 << 5)
+ (dow_year100 << 6) - 1;
if(dow_year1)
dow_year1 <= dow_year1 - 1;
else begin
dow_year1 <= 99;
dow_year100 <= dow_year100 - 1;
end
end else begin
dow_month <= dow_month - 2;
dow_year <= dow_year1 + (dow_year100 << 2) + (dow_year100 << 5) + (dow_year100 << 6);
end
end
STATE_DOW2: begin
dow_tmp <= (83 * dow_month);
end
STATE_DOW3: begin
dow_tmp <= (dow_tmp >> 5)
+ dow_day
+ dow_year
+ (dow_year >> 2)
- (dow_year100)
+ (dow_year100 >> 2);
end
STATE_DOW4: begin
dow_tmp <= dow_tmp - 7;
end
STATE_DOW5: begin
rtc_data_r[59:56] <= {1'b0, dow_tmp[2:0]};
end
STATE_LATCH: begin
rtc_data_out_r <= rtc_data_r;
end
endcase
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9739a_core (
// dac interface
dac_div_clk,
dac_rst,
dac_data_00,
dac_data_01,
dac_data_02,
dac_data_03,
dac_data_04,
dac_data_05,
dac_data_06,
dac_data_07,
dac_data_08,
dac_data_09,
dac_data_10,
dac_data_11,
dac_data_12,
dac_data_13,
dac_data_14,
dac_data_15,
dac_status,
// dma interface
dac_valid,
dac_enable,
dac_ddata,
dac_dovf,
dac_dunf,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter PCORE_ID = 0;
parameter DP_DISABLE = 0;
// dac interface
input dac_div_clk;
output dac_rst;
output [ 15:0] dac_data_00;
output [ 15:0] dac_data_01;
output [ 15:0] dac_data_02;
output [ 15:0] dac_data_03;
output [ 15:0] dac_data_04;
output [ 15:0] dac_data_05;
output [ 15:0] dac_data_06;
output [ 15:0] dac_data_07;
output [ 15:0] dac_data_08;
output [ 15:0] dac_data_09;
output [ 15:0] dac_data_10;
output [ 15:0] dac_data_11;
output [ 15:0] dac_data_12;
output [ 15:0] dac_data_13;
output [ 15:0] dac_data_14;
output [ 15:0] dac_data_15;
input dac_status;
// dma interface
output dac_valid;
output dac_enable;
input [255:0] dac_ddata;
input dac_dovf;
input dac_dunf;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [ 13:0] up_waddr;
input [ 31:0] up_wdata;
output up_wack;
input up_rreq;
input [ 13:0] up_raddr;
output [ 31:0] up_rdata;
output up_rack;
// internal registers
reg [ 31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
wire dac_sync_s;
wire dac_datafmt_s;
wire [ 31:0] up_rdata_0_s;
wire up_rack_0_s;
wire up_wack_0_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
wire up_wack_s;
// defaults
assign dac_valid = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s | up_rdata_0_s;
up_rack <= up_rack_s | up_rack_0_s;
up_wack <= up_wack_s | up_wack_0_s;
end
end
// dac channel
axi_ad9739a_channel #(
.CHID(0),
.DP_DISABLE(DP_DISABLE))
i_channel_0 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable),
.dac_data_00 (dac_data_00),
.dac_data_01 (dac_data_01),
.dac_data_02 (dac_data_02),
.dac_data_03 (dac_data_03),
.dac_data_04 (dac_data_04),
.dac_data_05 (dac_data_05),
.dac_data_06 (dac_data_06),
.dac_data_07 (dac_data_07),
.dac_data_08 (dac_data_08),
.dac_data_09 (dac_data_09),
.dac_data_10 (dac_data_10),
.dac_data_11 (dac_data_11),
.dac_data_12 (dac_data_12),
.dac_data_13 (dac_data_13),
.dac_data_14 (dac_data_14),
.dac_data_15 (dac_data_15),
.dma_data (dac_ddata),
.dac_data_sync (dac_sync_s),
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_0_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_0_s),
.up_rack (up_rack_0_s));
// dac common processor interface
up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync_s),
.dac_frame (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.dac_datafmt (dac_datafmt_s),
.dac_datarate (),
.dac_status (dac_status),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd4),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd1),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd1),
.up_dac_gpio_in (32'd0),
.up_dac_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__HA_SYMBOL_V
`define SKY130_FD_SC_LP__HA_SYMBOL_V
/**
* ha: Half adder.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__ha (
//# {{data|Data Signals}}
input A ,
input B ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__HA_SYMBOL_V
|
// This module is instantiated inside the l2cache
//
// The l1TLB has to track at least 4 SPBTRs at once, but no need to have
// unlimited. This means that just 4 flops translating SBPTR to valid indexes
// are enough. If a new SBPTR checkpoint create arrives, the TLB can
// invalidate all the associated TLB entries (and notify the L1 accordingly)
//
`include "scmem.vh"
`define L2TLB_PASSTHROUGH
module l2tlb(
/* verilator lint_off UNUSED */
/* verilator lint_off UNDRIVEN */
input clk
,input reset
// L2TLB listens the same L1 request (but no ack). Response sent to L2
,input l1tol2tlb_req_valid
,output l1tol2tlb_req_retry
,input I_l1tol2tlb_req_type l1tol2tlb_req
,output l2tlbtol2_fwd_valid
,input l2tlbtol2_fwd_retry
,output I_l2tlbtol2_fwd_type l2tlbtol2_fwd
// l1TLB and L2TLB interface
,output l2tlbtol1tlb_snoop_valid
,input l2tlbtol1tlb_snoop_retry
,output I_l2tlbtol1tlb_snoop_type l2tlbtol1tlb_snoop
,output l2tlbtol1tlb_ack_valid
,input l2tlbtol1tlb_ack_retry
,output I_l2tlbtol1tlb_ack_type l2tlbtol1tlb_ack
,input l1tlbtol2tlb_req_valid
,output l1tlbtol2tlb_req_retry
,input I_l1tlbtol2tlb_req_type l1tlbtol2tlb_req
,input l1tlbtol2tlb_sack_valid
,output l1tlbtol2tlb_sack_retry
,input I_l1tlbtol2tlb_sack_type l1tlbtol2tlb_sack
//---------------------------
// Directory interface (l2 has to arbitrate between L2 and L2TLB
// messages based on nodeid. Even nodeid is L2, odd is L2TLB)
,output l2todr_req_valid
,input l2todr_req_retry
,output I_l2todr_req_type l2todr_req
,input drtol2_snack_valid
,output drtol2_snack_retry
,input I_drtol2_snack_type drtol2_snack
,output l2todr_snoop_ack_valid
,input l2todr_snoop_ack_retry
,output I_l2snoop_ack_type l2todr_snoop_ack
,output l2todr_disp_valid
,input l2todr_disp_retry
,output I_l2todr_disp_type l2todr_disp
,input drtol2_dack_valid
,output drtol2_dack_retry
,input I_drtol2_dack_type drtol2_dack
/* verilator lint_on UNDRIVEN */
/* verilator lint_on UNUSED */
);
//`ifdef THIS_DOES_NOT_LINT
`ifdef L2TLB_PASSTHROUGH
assign l2tlbtol1tlb_snoop_valid = 1'b0;
assign l2todr_req_valid = 1'b0;
assign l2todr_disp_valid = 1'b0;
// l2tlb -> l2 fwd
I_l2tlbtol2_fwd_type l2tlbtol2_fwd_next;
logic l2tlbtol2_fwd_valid_next, l2tlbtol2_fwd_retry_next;
always_comb begin
if(l1tol2tlb_req_valid) begin
l2tlbtol2_fwd_next.l1id = l1tol2tlb_req.l1id;
l2tlbtol2_fwd_next.prefetch = l1tol2tlb_req.prefetch;
l2tlbtol2_fwd_next.fault = 3'b000;
l2tlbtol2_fwd_next.hpaddr = l1tol2tlb_req.hpaddr;
l2tlbtol2_fwd_next.paddr = {27'b0, l1tol2tlb_req.hpaddr, 12'b0};
l2tlbtol2_fwd_valid_next = l1tol2tlb_req_valid;
l1tol2tlb_req_retry = l2tlbtol2_fwd_retry_next;
end else begin
l2tlbtol2_fwd_valid_next = 1'b0;
end
end
fflop #(.Size($bits(I_l2tlbtol2_fwd_type))) ff_l2tlbtol2_fwd_pt(
.clk(clk)
,.reset(reset)
,.dinValid(l2tlbtol2_fwd_valid_next)
,.dinRetry(l2tlbtol2_fwd_retry_next)
,.din(l2tlbtol2_fwd_next)
,.qValid(l2tlbtol2_fwd_valid)
,.qRetry(l2tlbtol2_fwd_retry)
,.q(l2tlbtol2_fwd)
);
// l2tlb -> l1tlb ack
I_l2tlbtol1tlb_ack_type l2tlbtol1tlb_ack_next;
logic l2tlbtol1tlb_ack_valid_next, l2tlbtol1tlb_ack_retry_next;
always_comb begin
if(l1tlbtol2tlb_req_valid) begin
l2tlbtol1tlb_ack_next.rid = l1tlbtol2tlb_req.rid;
l2tlbtol1tlb_ack_next.hpaddr = l1tlbtol2tlb_req.laddr[22:12];
l2tlbtol1tlb_ack_next.ppaddr = l1tlbtol2tlb_req.laddr[14:12];
l2tlbtol1tlb_ack_next.dctlbe = 13'b0_0000_0000_0000;
l2tlbtol1tlb_ack_valid_next = l1tlbtol2tlb_req_valid;
l1tlbtol2tlb_req_retry = l2tlbtol1tlb_ack_retry_next;
end else begin
l2tlbtol1tlb_ack_valid_next = 1'b0;
end
end
fflop #(.Size($bits(I_l2tlbtol1tlb_ack_type))) ff_l2tlbtol1tlb_ack_pt(
.clk(clk)
,.reset(reset)
,.dinValid(l2tlbtol1tlb_ack_valid_next)
,.dinRetry(l2tlbtol1tlb_ack_retry_next)
,.din(l2tlbtol1tlb_ack_next)
,.qValid(l2tlbtol1tlb_ack_valid)
,.qRetry(l2tlbtol1tlb_ack_retry)
,.q(l2tlbtol1tlb_ack)
);
// l2 -> dr snoop_ack
I_l2snoop_ack_type l2todr_snoop_ack_next;
logic l2todr_snoop_ack_valid_next, l2todr_snoop_ack_retry_next;
always_comb begin
if(drtol2_snack_valid) begin
l2todr_snoop_ack_next.l2id = drtol2_snack.l2id;
l2todr_snoop_ack_next.directory_id = drtol2_snack.directory_id;
l2todr_snoop_ack_valid_next = drtol2_snack_valid;
drtol2_snack_retry = l2todr_snoop_ack_retry_next;
end else begin
l2todr_snoop_ack_valid_next = 1'b0;
end
end
fflop #(.Size($bits(I_l2snoop_ack_type))) ff_l2snoop_ack_pt(
.clk(clk)
,.reset(reset)
,.dinValid(l2todr_snoop_ack_valid_next)
,.dinRetry(l2todr_snoop_ack_retry_next)
,.din(l2todr_snoop_ack_next)
,.qValid(l2todr_snoop_ack_valid)
,.qRetry(l2todr_snoop_ack_retry)
,.q(l2todr_snoop_ack)
);
`endif
`ifdef L2TLB_ENTRIES
logic TLBT_valid;
logic TLBT_retry;
logic TLB_write[3:0];
logic TLBT_valid_next[3:0]
logic TLBT_valid_retry
logic TLBE_valid_next[3:0];
SC_dctlbe_type TLBE_dctlbe_next[3:0];
logic[18:0] TLBE_tag_next[3:0];
TLB_hpaddr_type TLBE_hpaddr;
// 1024 entries, 4 way
// 33 bits for each TLB entry:
// 1 bit for valid
// 13 bits for dctlbe
// 19 bits for tag
ram_1port_dense #(33, 256) TLBE0(
.clk(clk)
,.reset(reset)
,.req_valid(l1tlbtol2tlb_req_valid)
,.req_retry(l1tlbtol2tlb_req_retry)
,.req_we(TLBE_write[0])
,.req_pos(l1tlbtol2tlb_req.laddr[19:12])
,.req_data({1, 13'b0_0000_0000_0000, l1tlbtol2tlb_req.laddr[38:20]})
,.ack_valid(TLBT_valid_next[0])
,.ack_retry(TLBT_valid_retry)
,.ack_data({TLBE_valid_next[0], TLBE_dctlbe_next[0], TLBE_tag_next[0]})
);
ram_1port_dense #(33, 256) TLBE1(
.clk(clk)
,.reset(reset)
,.req_valid(l1tlbtol2tlb_req_valid)
,.req_retry(l1tlbtol2tlb_req_retry)
,.req_we(TLBE_write[1])
,.req_pos(l1tlbtol2tlb_req.laddr[19:12])
,.req_data({1, 13'b0_0000_0000_0000, l1tlbtol2tlb_req.laddr[38:20]})
,.ack_valid(TLBT_valid_next[1])
,.ack_retry(TLBT_valid_retry)
,.ack_data({TLBE_valid_next[1], TLBE_dctlbe_next[1], TLBE_tag_next[1]})
);
ram_1port_dense #(33, 256) TLBE2(
.clk(clk)
,.reset(reset)
,.req_valid(l1tlbtol2tlb_req_valid)
,.req_retry(l1tlbtol2tlb_req_retry)
,.req_we(TLBE_write[2])
,.req_pos(l1tlbtol2tlb_req.laddr[19:12])
,.req_data({1, 13'b0_0000_0000_0000, l1tlbtol2tlb_req.laddr[38:20]})
,.ack_valid(TLBT_valid_next[2])
,.ack_retry(TLBT_valid_retry)
,.ack_data({TLBE_valid_next[2], TLBE_dctlbe_next[2], TLBE_tag_next[2]})
);
ram_1port_dense #(33, 256) TLBE3(
.clk(clk)
,.reset(reset)
,.req_valid(l1tlbtol2tlb_req_valid)
,.req_retry(l1tlbtol2tlb_req_retry)
,.req_we(TLBE_write[3])
,.req_pos(l1tlbtol2tlb_req.laddr[19:12])
,.req_data({1, 13'b0_0000_0000_0000, l1tlbtol2tlb_req.laddr[38:20]})
,.ack_valid(TLBT_valid_next[3])
,.ack_retry(TLBT_valid_retry)
,.ack_data({TLBE_valid_next[3], TLBE_dctlbe_next[3], TLBE_tag_next[3]})
);
always_comb begin
if(l1tlbtol2tlb_req_valid = 1'b1) begin
l2tlbtol1tlb_ack.rid = l1tlbtol2tlb_req.rid;
TLBT_valid = 1'b1;
TLBT_retry = 1'b0;
TLBE_write = {1'b0, 1'b0, 1'b0, 1'b0};
if((TLBT_valid_next[0]) && (TLBE_valid_next[0] == 1) && (l1tlbtol2tlb_req.laddr[38:20] == TLBE_tag_next[0])) begin
l2tlbtol1tlb_ack_valid = 1'b1;
l2tlbtol1tlb_ack.hpaddr = {3'b000, l1tlbtol2tlb_req.laddr[19:12]};
l2tlbtol1tlb_ack.dctlbe = TLBE_dctlbe_next[0];
end else if((TLBT_valid_next[1]) && (TLBE_valid_next[1] == 1) && (l1tlbtol2tlb_req.laddr[38:20] == TLBE_tag_next[1])) begin
l2tlbtol1tlb_ack_valid = 1'b1;
l2tlbtol1tlb_ack.hpaddr = {3'b001, l1tlbtol2tlb_req.laddr[19:12]};
l2tlbtol1tlb_ack.dctlbe = TLBE_dctlbe_next[1];
end else if((TLBT_valid_next[2]) && (TLBE_valid_next[2] == 1) && (l1tlbtol2tlb_req.laddr[38:20] == TLBE_tag_next[2])) begin
l2tlbtol1tlb_ack_valid = 1'b1;
l2tlbtol1tlb_ack.hpaddr = {3'b010, l1tlbtol2tlb_req.laddr[19:12]};
l2tlbtol1tlb_ack.dctlbe = TLBE_dctlbe_next[2];
end else if((TLBT_valid_next[3]) && (TLBE_valid_next[3] == 1) && (l1tlbtol2tlb_req.laddr[38:20] == TLBE_tag_next[3])) begin
l2tlbtol1tlb_ack_valid = 1'b1;
l2tlbtol1tlb_ack.hpaddr = {3'b011, l1tlbtol2tlb_req.laddr[19:12]};
l2tlbtol1tlb_ack.dctlbe = TLBE_dctlbe_next[3];
end else begin
l2tlbtol1tlb_ack_valid = 1'b0;
end
end
end
logic HT_valid;
logic HT_retry;
logic HE_write;
TLB_hpaddr_type HE_hpaddr;
logic HE_valid;
SC_paddr_type HE_paddr;
logic HT_valid_next;
logic HT_retry_next;
logic HE_valid_next;
SC_paddr_type HE_paddr_next;
ram_1port_dense #(51, 2048) H0(
.clk(clk)
,.reset(reset)
,.req_valid(HT_valid)
,.req_retry(HT_retry)
,.req_we(HE_write)
,.req_pos(HE_hpaddr)
,.req_data({HE_valid, HE_paddr})
,.ack_valid(HT_valid_next)
,.ack_retry(HT_retry_next)
,.ack_data({HE_valid_next, HE_paddr_next})
);
always_comb begin
if(l1tol2tlb_req_valid) begin
l2tlbtol2_fwd.lid = l1tol2tlb_req.lid;
HT_valid = 1'b1;
HT_retry = 1'b0;
HE_write = 1'b0;
HE_hpaddr = l1tol2tlb_req.hpaddr;
if((HT_valid_next == 1'b1) && (HE_valid_next == 1'b1)) begin
l2tlbtol2_fwd_valid = 1'b1;
l2tlbtol2_fwd.paddr = l1tol2tlb_req.hpaddr;
l2tlbtol2_fwd.paddr = HE_paddr_next;
end else begin
l2tlbtol2_fwd_valid = 1'b0;
end
end
end
`endif
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's instruction fetch ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PC, instruction fetch, interface to IC. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_if.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.5 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.2 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/20 18:46:15 simons
// Break point bug fixed
//
// Revision 1.9 2001/11/18 09:58:28 lampret
// Fixed some l.trap typos.
//
// Revision 1.8 2001/11/18 08:36:28 lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_if(
// Clock and reset
clk, rst,
// External i/f to IC
icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
// Internal i/f
if_freeze, if_insn, if_pc, flushpipe,
if_stall, no_more_dslot, genpc_refetch, rfe,
except_itlbmiss, except_immufault, except_ibuserr
);
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// External i/f to IC
//
input [31:0] icpu_dat_i;
input icpu_ack_i;
input icpu_err_i;
input [31:0] icpu_adr_i;
input [3:0] icpu_tag_i;
//
// Internal i/f
//
input if_freeze;
output [31:0] if_insn;
output [31:0] if_pc;
input flushpipe;
output if_stall;
input no_more_dslot;
output genpc_refetch;
input rfe;
output except_itlbmiss;
output except_immufault;
output except_ibuserr;
//
// Internal wires and regs
//
reg [31:0] insn_saved;
reg [31:0] addr_saved;
reg saved;
//
// IF stage insn
//
assign if_insn = icpu_err_i | no_more_dslot | rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
assign if_pc = saved ? addr_saved : icpu_adr_i;
// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot;
assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
assign genpc_refetch = saved & icpu_ack_i;
assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot;
assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot;
assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot;
//
// Flag for saved insn/address
//
always @(posedge clk or posedge rst)
if (rst)
saved <= #1 1'b0;
else if (flushpipe)
saved <= #1 1'b0;
else if (icpu_ack_i & if_freeze & !saved)
saved <= #1 1'b1;
else if (!if_freeze)
saved <= #1 1'b0;
//
// Store fetched instruction
//
always @(posedge clk or posedge rst)
if (rst)
insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
else if (flushpipe)
insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
else if (icpu_ack_i & if_freeze & !saved)
insn_saved <= #1 icpu_dat_i;
else if (!if_freeze)
insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
//
// Store fetched instruction's address
//
always @(posedge clk or posedge rst)
if (rst)
addr_saved <= #1 32'h00000000;
else if (flushpipe)
addr_saved <= #1 32'h00000000;
else if (icpu_ack_i & if_freeze & !saved)
addr_saved <= #1 icpu_adr_i;
else if (!if_freeze)
addr_saved <= #1 icpu_adr_i;
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module AXIvideo2Mat (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
stream_in_TDATA,
stream_in_TVALID,
stream_in_TREADY,
stream_in_TKEEP,
stream_in_TSTRB,
stream_in_TUSER,
stream_in_TLAST,
stream_in_TID,
stream_in_TDEST,
img_rows_V_read,
img_cols_V_read,
img_data_stream_0_V_din,
img_data_stream_0_V_full_n,
img_data_stream_0_V_write,
img_data_stream_1_V_din,
img_data_stream_1_V_full_n,
img_data_stream_1_V_write,
img_data_stream_2_V_din,
img_data_stream_2_V_full_n,
img_data_stream_2_V_write
);
parameter ap_ST_fsm_state1 = 8'd1;
parameter ap_ST_fsm_state2 = 8'd2;
parameter ap_ST_fsm_state3 = 8'd4;
parameter ap_ST_fsm_state4 = 8'd8;
parameter ap_ST_fsm_pp1_stage0 = 8'd16;
parameter ap_ST_fsm_state7 = 8'd32;
parameter ap_ST_fsm_pp2_stage0 = 8'd64;
parameter ap_ST_fsm_state10 = 8'd128;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [23:0] stream_in_TDATA;
input stream_in_TVALID;
output stream_in_TREADY;
input [2:0] stream_in_TKEEP;
input [2:0] stream_in_TSTRB;
input [0:0] stream_in_TUSER;
input [0:0] stream_in_TLAST;
input [0:0] stream_in_TID;
input [0:0] stream_in_TDEST;
input [15:0] img_rows_V_read;
input [15:0] img_cols_V_read;
output [7:0] img_data_stream_0_V_din;
input img_data_stream_0_V_full_n;
output img_data_stream_0_V_write;
output [7:0] img_data_stream_1_V_din;
input img_data_stream_1_V_full_n;
output img_data_stream_1_V_write;
output [7:0] img_data_stream_2_V_din;
input img_data_stream_2_V_full_n;
output img_data_stream_2_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg img_data_stream_0_V_write;
reg img_data_stream_1_V_write;
reg img_data_stream_2_V_write;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [7:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg [23:0] AXI_video_strm_V_data_V_0_data_out;
wire AXI_video_strm_V_data_V_0_vld_in;
wire AXI_video_strm_V_data_V_0_vld_out;
wire AXI_video_strm_V_data_V_0_ack_in;
reg AXI_video_strm_V_data_V_0_ack_out;
reg [23:0] AXI_video_strm_V_data_V_0_payload_A;
reg [23:0] AXI_video_strm_V_data_V_0_payload_B;
reg AXI_video_strm_V_data_V_0_sel_rd;
reg AXI_video_strm_V_data_V_0_sel_wr;
wire AXI_video_strm_V_data_V_0_sel;
wire AXI_video_strm_V_data_V_0_load_A;
wire AXI_video_strm_V_data_V_0_load_B;
reg [1:0] AXI_video_strm_V_data_V_0_state;
wire AXI_video_strm_V_data_V_0_state_cmp_full;
reg [0:0] AXI_video_strm_V_user_V_0_data_out;
wire AXI_video_strm_V_user_V_0_vld_in;
wire AXI_video_strm_V_user_V_0_vld_out;
wire AXI_video_strm_V_user_V_0_ack_in;
reg AXI_video_strm_V_user_V_0_ack_out;
reg [0:0] AXI_video_strm_V_user_V_0_payload_A;
reg [0:0] AXI_video_strm_V_user_V_0_payload_B;
reg AXI_video_strm_V_user_V_0_sel_rd;
reg AXI_video_strm_V_user_V_0_sel_wr;
wire AXI_video_strm_V_user_V_0_sel;
wire AXI_video_strm_V_user_V_0_load_A;
wire AXI_video_strm_V_user_V_0_load_B;
reg [1:0] AXI_video_strm_V_user_V_0_state;
wire AXI_video_strm_V_user_V_0_state_cmp_full;
reg [0:0] AXI_video_strm_V_last_V_0_data_out;
wire AXI_video_strm_V_last_V_0_vld_in;
wire AXI_video_strm_V_last_V_0_vld_out;
wire AXI_video_strm_V_last_V_0_ack_in;
reg AXI_video_strm_V_last_V_0_ack_out;
reg [0:0] AXI_video_strm_V_last_V_0_payload_A;
reg [0:0] AXI_video_strm_V_last_V_0_payload_B;
reg AXI_video_strm_V_last_V_0_sel_rd;
reg AXI_video_strm_V_last_V_0_sel_wr;
wire AXI_video_strm_V_last_V_0_sel;
wire AXI_video_strm_V_last_V_0_load_A;
wire AXI_video_strm_V_last_V_0_load_B;
reg [1:0] AXI_video_strm_V_last_V_0_state;
wire AXI_video_strm_V_last_V_0_state_cmp_full;
wire AXI_video_strm_V_dest_V_0_vld_in;
reg AXI_video_strm_V_dest_V_0_ack_out;
reg [1:0] AXI_video_strm_V_dest_V_0_state;
reg stream_in_TDATA_blk_n;
wire ap_CS_fsm_state2;
wire ap_CS_fsm_pp1_stage0;
reg ap_enable_reg_pp1_iter1;
wire ap_block_pp1_stage0;
reg [0:0] exitcond_reg_420;
reg [0:0] brmerge_reg_429;
wire ap_CS_fsm_pp2_stage0;
reg ap_enable_reg_pp2_iter1;
wire ap_block_pp2_stage0;
reg [0:0] eol_2_reg_248;
reg img_data_stream_0_V_blk_n;
reg img_data_stream_1_V_blk_n;
reg img_data_stream_2_V_blk_n;
reg [10:0] t_V_2_reg_178;
reg [0:0] eol_reg_189;
reg [0:0] eol_1_reg_201;
reg [23:0] axi_data_V_1_reg_212;
reg [0:0] axi_last_V_3_reg_259;
reg [23:0] axi_data_V_3_reg_271;
wire [11:0] tmp_13_fu_293_p1;
reg [11:0] tmp_13_reg_381;
reg ap_block_state1;
wire [11:0] tmp_14_fu_297_p1;
reg [11:0] tmp_14_reg_386;
reg [23:0] tmp_data_V_reg_391;
reg [0:0] tmp_last_V_reg_399;
wire [0:0] exitcond2_fu_314_p2;
wire ap_CS_fsm_state4;
wire [10:0] i_V_fu_319_p2;
reg [10:0] i_V_reg_415;
wire [0:0] exitcond_fu_329_p2;
wire ap_block_state5_pp1_stage0_iter0;
reg ap_predicate_op62_read_state6;
reg ap_block_state6_pp1_stage0_iter1;
reg ap_block_pp1_stage0_11001;
wire [10:0] j_V_fu_334_p2;
reg ap_enable_reg_pp1_iter0;
wire [0:0] brmerge_fu_343_p2;
wire ap_block_state8_pp2_stage0_iter0;
reg ap_block_state9_pp2_stage0_iter1;
reg ap_block_pp2_stage0_11001;
reg ap_block_pp1_stage0_subdone;
reg ap_enable_reg_pp2_iter0;
wire ap_CS_fsm_state7;
reg ap_block_pp2_stage0_subdone;
reg [0:0] ap_phi_mux_eol_2_phi_fu_251_p4;
reg [0:0] axi_last_V1_reg_147;
wire ap_CS_fsm_state10;
wire ap_CS_fsm_state3;
reg [23:0] axi_data_V1_reg_157;
reg [10:0] t_V_reg_167;
reg [0:0] ap_phi_mux_eol_phi_fu_193_p4;
reg [0:0] ap_phi_mux_axi_last_V_2_phi_fu_228_p4;
reg [23:0] ap_phi_mux_p_Val2_s_phi_fu_240_p4;
wire [0:0] ap_phi_reg_pp1_iter1_axi_last_V_2_reg_223;
wire [23:0] ap_phi_reg_pp1_iter1_p_Val2_s_reg_236;
reg ap_block_pp1_stage0_01001;
reg [0:0] sof_1_fu_92;
wire [11:0] t_V_cast_fu_310_p1;
wire [11:0] t_V_3_cast_fu_325_p1;
wire [0:0] tmp_user_V_fu_301_p1;
reg [7:0] ap_NS_fsm;
reg ap_idle_pp1;
wire ap_enable_pp1;
reg ap_idle_pp2;
wire ap_enable_pp2;
reg ap_condition_495;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 8'd1;
#0 AXI_video_strm_V_data_V_0_sel_rd = 1'b0;
#0 AXI_video_strm_V_data_V_0_sel_wr = 1'b0;
#0 AXI_video_strm_V_data_V_0_state = 2'd0;
#0 AXI_video_strm_V_user_V_0_sel_rd = 1'b0;
#0 AXI_video_strm_V_user_V_0_sel_wr = 1'b0;
#0 AXI_video_strm_V_user_V_0_state = 2'd0;
#0 AXI_video_strm_V_last_V_0_sel_rd = 1'b0;
#0 AXI_video_strm_V_last_V_0_sel_wr = 1'b0;
#0 AXI_video_strm_V_last_V_0_state = 2'd0;
#0 AXI_video_strm_V_dest_V_0_state = 2'd0;
#0 ap_enable_reg_pp1_iter1 = 1'b0;
#0 ap_enable_reg_pp2_iter1 = 1'b0;
#0 ap_enable_reg_pp1_iter0 = 1'b0;
#0 ap_enable_reg_pp2_iter0 = 1'b0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_data_V_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_data_V_0_ack_out) & (1'b1 == AXI_video_strm_V_data_V_0_vld_out))) begin
AXI_video_strm_V_data_V_0_sel_rd <= ~AXI_video_strm_V_data_V_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_data_V_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_data_V_0_ack_in) & (1'b1 == AXI_video_strm_V_data_V_0_vld_in))) begin
AXI_video_strm_V_data_V_0_sel_wr <= ~AXI_video_strm_V_data_V_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_data_V_0_state <= 2'd0;
end else begin
if ((((2'd2 == AXI_video_strm_V_data_V_0_state) & (1'b0 == AXI_video_strm_V_data_V_0_vld_in)) | ((2'd3 == AXI_video_strm_V_data_V_0_state) & (1'b0 == AXI_video_strm_V_data_V_0_vld_in) & (1'b1 == AXI_video_strm_V_data_V_0_ack_out)))) begin
AXI_video_strm_V_data_V_0_state <= 2'd2;
end else if ((((2'd1 == AXI_video_strm_V_data_V_0_state) & (1'b0 == AXI_video_strm_V_data_V_0_ack_out)) | ((2'd3 == AXI_video_strm_V_data_V_0_state) & (1'b0 == AXI_video_strm_V_data_V_0_ack_out) & (1'b1 == AXI_video_strm_V_data_V_0_vld_in)))) begin
AXI_video_strm_V_data_V_0_state <= 2'd1;
end else if (((~((1'b0 == AXI_video_strm_V_data_V_0_vld_in) & (1'b1 == AXI_video_strm_V_data_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_data_V_0_ack_out) & (1'b1 == AXI_video_strm_V_data_V_0_vld_in)) & (2'd3 == AXI_video_strm_V_data_V_0_state)) | ((2'd1 == AXI_video_strm_V_data_V_0_state) & (1'b1 == AXI_video_strm_V_data_V_0_ack_out)) | ((2'd2 == AXI_video_strm_V_data_V_0_state) & (1'b1 == AXI_video_strm_V_data_V_0_vld_in)))) begin
AXI_video_strm_V_data_V_0_state <= 2'd3;
end else begin
AXI_video_strm_V_data_V_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_dest_V_0_state <= 2'd0;
end else begin
if ((((2'd2 == AXI_video_strm_V_dest_V_0_state) & (1'b0 == AXI_video_strm_V_dest_V_0_vld_in)) | ((2'd3 == AXI_video_strm_V_dest_V_0_state) & (1'b0 == AXI_video_strm_V_dest_V_0_vld_in) & (1'b1 == AXI_video_strm_V_dest_V_0_ack_out)))) begin
AXI_video_strm_V_dest_V_0_state <= 2'd2;
end else if ((((2'd1 == AXI_video_strm_V_dest_V_0_state) & (1'b0 == AXI_video_strm_V_dest_V_0_ack_out)) | ((2'd3 == AXI_video_strm_V_dest_V_0_state) & (1'b0 == AXI_video_strm_V_dest_V_0_ack_out) & (1'b1 == AXI_video_strm_V_dest_V_0_vld_in)))) begin
AXI_video_strm_V_dest_V_0_state <= 2'd1;
end else if (((~((1'b0 == AXI_video_strm_V_dest_V_0_vld_in) & (1'b1 == AXI_video_strm_V_dest_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_dest_V_0_ack_out) & (1'b1 == AXI_video_strm_V_dest_V_0_vld_in)) & (2'd3 == AXI_video_strm_V_dest_V_0_state)) | ((2'd1 == AXI_video_strm_V_dest_V_0_state) & (1'b1 == AXI_video_strm_V_dest_V_0_ack_out)) | ((2'd2 == AXI_video_strm_V_dest_V_0_state) & (1'b1 == AXI_video_strm_V_dest_V_0_vld_in)))) begin
AXI_video_strm_V_dest_V_0_state <= 2'd3;
end else begin
AXI_video_strm_V_dest_V_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_last_V_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_last_V_0_ack_out) & (1'b1 == AXI_video_strm_V_last_V_0_vld_out))) begin
AXI_video_strm_V_last_V_0_sel_rd <= ~AXI_video_strm_V_last_V_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_last_V_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_last_V_0_ack_in) & (1'b1 == AXI_video_strm_V_last_V_0_vld_in))) begin
AXI_video_strm_V_last_V_0_sel_wr <= ~AXI_video_strm_V_last_V_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_last_V_0_state <= 2'd0;
end else begin
if ((((2'd2 == AXI_video_strm_V_last_V_0_state) & (1'b0 == AXI_video_strm_V_last_V_0_vld_in)) | ((2'd3 == AXI_video_strm_V_last_V_0_state) & (1'b0 == AXI_video_strm_V_last_V_0_vld_in) & (1'b1 == AXI_video_strm_V_last_V_0_ack_out)))) begin
AXI_video_strm_V_last_V_0_state <= 2'd2;
end else if ((((2'd1 == AXI_video_strm_V_last_V_0_state) & (1'b0 == AXI_video_strm_V_last_V_0_ack_out)) | ((2'd3 == AXI_video_strm_V_last_V_0_state) & (1'b0 == AXI_video_strm_V_last_V_0_ack_out) & (1'b1 == AXI_video_strm_V_last_V_0_vld_in)))) begin
AXI_video_strm_V_last_V_0_state <= 2'd1;
end else if (((~((1'b0 == AXI_video_strm_V_last_V_0_vld_in) & (1'b1 == AXI_video_strm_V_last_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_last_V_0_ack_out) & (1'b1 == AXI_video_strm_V_last_V_0_vld_in)) & (2'd3 == AXI_video_strm_V_last_V_0_state)) | ((2'd1 == AXI_video_strm_V_last_V_0_state) & (1'b1 == AXI_video_strm_V_last_V_0_ack_out)) | ((2'd2 == AXI_video_strm_V_last_V_0_state) & (1'b1 == AXI_video_strm_V_last_V_0_vld_in)))) begin
AXI_video_strm_V_last_V_0_state <= 2'd3;
end else begin
AXI_video_strm_V_last_V_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_user_V_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_user_V_0_ack_out) & (1'b1 == AXI_video_strm_V_user_V_0_vld_out))) begin
AXI_video_strm_V_user_V_0_sel_rd <= ~AXI_video_strm_V_user_V_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_user_V_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == AXI_video_strm_V_user_V_0_ack_in) & (1'b1 == AXI_video_strm_V_user_V_0_vld_in))) begin
AXI_video_strm_V_user_V_0_sel_wr <= ~AXI_video_strm_V_user_V_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
AXI_video_strm_V_user_V_0_state <= 2'd0;
end else begin
if ((((2'd2 == AXI_video_strm_V_user_V_0_state) & (1'b0 == AXI_video_strm_V_user_V_0_vld_in)) | ((2'd3 == AXI_video_strm_V_user_V_0_state) & (1'b0 == AXI_video_strm_V_user_V_0_vld_in) & (1'b1 == AXI_video_strm_V_user_V_0_ack_out)))) begin
AXI_video_strm_V_user_V_0_state <= 2'd2;
end else if ((((2'd1 == AXI_video_strm_V_user_V_0_state) & (1'b0 == AXI_video_strm_V_user_V_0_ack_out)) | ((2'd3 == AXI_video_strm_V_user_V_0_state) & (1'b0 == AXI_video_strm_V_user_V_0_ack_out) & (1'b1 == AXI_video_strm_V_user_V_0_vld_in)))) begin
AXI_video_strm_V_user_V_0_state <= 2'd1;
end else if (((~((1'b0 == AXI_video_strm_V_user_V_0_vld_in) & (1'b1 == AXI_video_strm_V_user_V_0_ack_out)) & ~((1'b0 == AXI_video_strm_V_user_V_0_ack_out) & (1'b1 == AXI_video_strm_V_user_V_0_vld_in)) & (2'd3 == AXI_video_strm_V_user_V_0_state)) | ((2'd1 == AXI_video_strm_V_user_V_0_state) & (1'b1 == AXI_video_strm_V_user_V_0_ack_out)) | ((2'd2 == AXI_video_strm_V_user_V_0_state) & (1'b1 == AXI_video_strm_V_user_V_0_vld_in)))) begin
AXI_video_strm_V_user_V_0_state <= 2'd3;
end else begin
AXI_video_strm_V_user_V_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if (((exitcond2_fu_314_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp1_iter0 <= 1'b0;
end else begin
if (((1'b0 == ap_block_pp1_stage0_subdone) & (exitcond_fu_329_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
ap_enable_reg_pp1_iter0 <= 1'b0;
end else if (((exitcond2_fu_314_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
ap_enable_reg_pp1_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp1_iter1 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp1_stage0_subdone)) begin
ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
end else if (((exitcond2_fu_314_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
ap_enable_reg_pp1_iter1 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp2_iter0 <= 1'b0;
end else begin
if (((1'b0 == ap_block_pp2_stage0_subdone) & (ap_phi_mux_eol_2_phi_fu_251_p4 == 1'd1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
ap_enable_reg_pp2_iter0 <= 1'b0;
end else if ((1'b1 == ap_CS_fsm_state7)) begin
ap_enable_reg_pp2_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp2_iter1 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp2_stage0_subdone)) begin
ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
end else if ((1'b1 == ap_CS_fsm_state7)) begin
ap_enable_reg_pp2_iter1 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
axi_data_V1_reg_157 <= tmp_data_V_reg_391;
end else if ((1'b1 == ap_CS_fsm_state10)) begin
axi_data_V1_reg_157 <= axi_data_V_3_reg_271;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp1_stage0_11001) & (exitcond_reg_420 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
axi_data_V_1_reg_212 <= ap_phi_mux_p_Val2_s_phi_fu_240_p4;
end else if (((exitcond2_fu_314_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
axi_data_V_1_reg_212 <= axi_data_V1_reg_157;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state7)) begin
axi_data_V_3_reg_271 <= axi_data_V_1_reg_212;
end else if (((1'b0 == ap_block_pp2_stage0_11001) & (eol_2_reg_248 == 1'd0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
axi_data_V_3_reg_271 <= AXI_video_strm_V_data_V_0_data_out;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
axi_last_V1_reg_147 <= tmp_last_V_reg_399;
end else if ((1'b1 == ap_CS_fsm_state10)) begin
axi_last_V1_reg_147 <= axi_last_V_3_reg_259;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state7)) begin
axi_last_V_3_reg_259 <= eol_1_reg_201;
end else if (((1'b0 == ap_block_pp2_stage0_11001) & (eol_2_reg_248 == 1'd0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
axi_last_V_3_reg_259 <= AXI_video_strm_V_last_V_0_data_out;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp1_stage0_11001) & (exitcond_reg_420 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
eol_1_reg_201 <= ap_phi_mux_axi_last_V_2_phi_fu_228_p4;
end else if (((exitcond2_fu_314_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
eol_1_reg_201 <= axi_last_V1_reg_147;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state7)) begin
eol_2_reg_248 <= eol_reg_189;
end else if (((1'b0 == ap_block_pp2_stage0_11001) & (eol_2_reg_248 == 1'd0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
eol_2_reg_248 <= AXI_video_strm_V_last_V_0_data_out;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp1_stage0_11001) & (exitcond_reg_420 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
eol_reg_189 <= ap_phi_mux_axi_last_V_2_phi_fu_228_p4;
end else if (((exitcond2_fu_314_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
eol_reg_189 <= 1'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp1_stage0_11001) & (exitcond_fu_329_p2 == 1'd0) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
sof_1_fu_92 <= 1'd0;
end else if ((1'b1 == ap_CS_fsm_state3)) begin
sof_1_fu_92 <= 1'd1;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp1_stage0_11001) & (exitcond_fu_329_p2 == 1'd0) & (ap_enable_reg_pp1_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
t_V_2_reg_178 <= j_V_fu_334_p2;
end else if (((exitcond2_fu_314_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state4))) begin
t_V_2_reg_178 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
t_V_reg_167 <= 11'd0;
end else if ((1'b1 == ap_CS_fsm_state10)) begin
t_V_reg_167 <= i_V_reg_415;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_data_V_0_load_A)) begin
AXI_video_strm_V_data_V_0_payload_A <= stream_in_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_data_V_0_load_B)) begin
AXI_video_strm_V_data_V_0_payload_B <= stream_in_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_last_V_0_load_A)) begin
AXI_video_strm_V_last_V_0_payload_A <= stream_in_TLAST;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_last_V_0_load_B)) begin
AXI_video_strm_V_last_V_0_payload_B <= stream_in_TLAST;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_user_V_0_load_A)) begin
AXI_video_strm_V_user_V_0_payload_A <= stream_in_TUSER;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == AXI_video_strm_V_user_V_0_load_B)) begin
AXI_video_strm_V_user_V_0_payload_B <= stream_in_TUSER;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp1_stage0_11001) & (exitcond_fu_329_p2 == 1'd0) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
brmerge_reg_429 <= brmerge_fu_343_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp1_stage0_11001) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
exitcond_reg_420 <= exitcond_fu_329_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state4)) begin
i_V_reg_415 <= i_V_fu_319_p2;
end
end
always @ (posedge ap_clk) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
tmp_13_reg_381 <= tmp_13_fu_293_p1;
tmp_14_reg_386 <= tmp_14_fu_297_p1;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2))) begin
tmp_data_V_reg_391 <= AXI_video_strm_V_data_V_0_data_out;
tmp_last_V_reg_399 <= AXI_video_strm_V_last_V_0_data_out;
end
end
always @ (*) begin
if ((((1'b0 == ap_block_pp2_stage0_11001) & (eol_2_reg_248 == 1'd0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_predicate_op62_read_state6 == 1'b1) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0)) | ((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2)))) begin
AXI_video_strm_V_data_V_0_ack_out = 1'b1;
end else begin
AXI_video_strm_V_data_V_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == AXI_video_strm_V_data_V_0_sel)) begin
AXI_video_strm_V_data_V_0_data_out = AXI_video_strm_V_data_V_0_payload_B;
end else begin
AXI_video_strm_V_data_V_0_data_out = AXI_video_strm_V_data_V_0_payload_A;
end
end
always @ (*) begin
if ((((1'b0 == ap_block_pp2_stage0_11001) & (eol_2_reg_248 == 1'd0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_predicate_op62_read_state6 == 1'b1) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0)) | ((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2)))) begin
AXI_video_strm_V_dest_V_0_ack_out = 1'b1;
end else begin
AXI_video_strm_V_dest_V_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((((1'b0 == ap_block_pp2_stage0_11001) & (eol_2_reg_248 == 1'd0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_predicate_op62_read_state6 == 1'b1) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0)) | ((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2)))) begin
AXI_video_strm_V_last_V_0_ack_out = 1'b1;
end else begin
AXI_video_strm_V_last_V_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == AXI_video_strm_V_last_V_0_sel)) begin
AXI_video_strm_V_last_V_0_data_out = AXI_video_strm_V_last_V_0_payload_B;
end else begin
AXI_video_strm_V_last_V_0_data_out = AXI_video_strm_V_last_V_0_payload_A;
end
end
always @ (*) begin
if ((((1'b0 == ap_block_pp2_stage0_11001) & (eol_2_reg_248 == 1'd0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((1'b0 == ap_block_pp1_stage0_11001) & (ap_predicate_op62_read_state6 == 1'b1) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0)) | ((1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2)))) begin
AXI_video_strm_V_user_V_0_ack_out = 1'b1;
end else begin
AXI_video_strm_V_user_V_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == AXI_video_strm_V_user_V_0_sel)) begin
AXI_video_strm_V_user_V_0_data_out = AXI_video_strm_V_user_V_0_payload_B;
end else begin
AXI_video_strm_V_user_V_0_data_out = AXI_video_strm_V_user_V_0_payload_A;
end
end
always @ (*) begin
if (((exitcond2_fu_314_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b0))) begin
ap_idle_pp1 = 1'b1;
end else begin
ap_idle_pp1 = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp2_iter0 == 1'b0) & (ap_enable_reg_pp2_iter1 == 1'b0))) begin
ap_idle_pp2 = 1'b1;
end else begin
ap_idle_pp2 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_condition_495)) begin
if ((brmerge_reg_429 == 1'd1)) begin
ap_phi_mux_axi_last_V_2_phi_fu_228_p4 = eol_1_reg_201;
end else if ((brmerge_reg_429 == 1'd0)) begin
ap_phi_mux_axi_last_V_2_phi_fu_228_p4 = AXI_video_strm_V_last_V_0_data_out;
end else begin
ap_phi_mux_axi_last_V_2_phi_fu_228_p4 = ap_phi_reg_pp1_iter1_axi_last_V_2_reg_223;
end
end else begin
ap_phi_mux_axi_last_V_2_phi_fu_228_p4 = ap_phi_reg_pp1_iter1_axi_last_V_2_reg_223;
end
end
always @ (*) begin
if (((eol_2_reg_248 == 1'd0) & (1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
ap_phi_mux_eol_2_phi_fu_251_p4 = AXI_video_strm_V_last_V_0_data_out;
end else begin
ap_phi_mux_eol_2_phi_fu_251_p4 = eol_2_reg_248;
end
end
always @ (*) begin
if (((exitcond_reg_420 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
ap_phi_mux_eol_phi_fu_193_p4 = ap_phi_mux_axi_last_V_2_phi_fu_228_p4;
end else begin
ap_phi_mux_eol_phi_fu_193_p4 = eol_reg_189;
end
end
always @ (*) begin
if ((1'b1 == ap_condition_495)) begin
if ((brmerge_reg_429 == 1'd1)) begin
ap_phi_mux_p_Val2_s_phi_fu_240_p4 = axi_data_V_1_reg_212;
end else if ((brmerge_reg_429 == 1'd0)) begin
ap_phi_mux_p_Val2_s_phi_fu_240_p4 = AXI_video_strm_V_data_V_0_data_out;
end else begin
ap_phi_mux_p_Val2_s_phi_fu_240_p4 = ap_phi_reg_pp1_iter1_p_Val2_s_reg_236;
end
end else begin
ap_phi_mux_p_Val2_s_phi_fu_240_p4 = ap_phi_reg_pp1_iter1_p_Val2_s_reg_236;
end
end
always @ (*) begin
if (((exitcond2_fu_314_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((exitcond_reg_420 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_0_V_blk_n = img_data_stream_0_V_full_n;
end else begin
img_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp1_stage0_11001) & (exitcond_reg_420 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_0_V_write = 1'b1;
end else begin
img_data_stream_0_V_write = 1'b0;
end
end
always @ (*) begin
if (((exitcond_reg_420 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_1_V_blk_n = img_data_stream_1_V_full_n;
end else begin
img_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp1_stage0_11001) & (exitcond_reg_420 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_1_V_write = 1'b1;
end else begin
img_data_stream_1_V_write = 1'b0;
end
end
always @ (*) begin
if (((exitcond_reg_420 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_2_V_blk_n = img_data_stream_2_V_full_n;
end else begin
img_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp1_stage0_11001) & (exitcond_reg_420 == 1'd0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
img_data_stream_2_V_write = 1'b1;
end else begin
img_data_stream_2_V_write = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) | ((eol_2_reg_248 == 1'd0) & (1'b0 == ap_block_pp2_stage0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0)) | ((brmerge_reg_429 == 1'd0) & (exitcond_reg_420 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0)))) begin
stream_in_TDATA_blk_n = AXI_video_strm_V_data_V_0_state[1'd0];
end else begin
stream_in_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
if (((tmp_user_V_fu_301_p1 == 1'd0) & (1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else if (((tmp_user_V_fu_301_p1 == 1'd1) & (1'b1 == AXI_video_strm_V_data_V_0_vld_out) & (1'b1 == ap_CS_fsm_state2))) begin
ap_NS_fsm = ap_ST_fsm_state3;
end else begin
ap_NS_fsm = ap_ST_fsm_state2;
end
end
ap_ST_fsm_state3 : begin
ap_NS_fsm = ap_ST_fsm_state4;
end
ap_ST_fsm_state4 : begin
if (((exitcond2_fu_314_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state4))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_pp1_stage0;
end
end
ap_ST_fsm_pp1_stage0 : begin
if (~((1'b0 == ap_block_pp1_stage0_subdone) & (ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
ap_NS_fsm = ap_ST_fsm_pp1_stage0;
end else if (((1'b0 == ap_block_pp1_stage0_subdone) & (ap_enable_reg_pp1_iter0 == 1'b0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0))) begin
ap_NS_fsm = ap_ST_fsm_state7;
end else begin
ap_NS_fsm = ap_ST_fsm_pp1_stage0;
end
end
ap_ST_fsm_state7 : begin
ap_NS_fsm = ap_ST_fsm_pp2_stage0;
end
ap_ST_fsm_pp2_stage0 : begin
if (~((1'b0 == ap_block_pp2_stage0_subdone) & (ap_enable_reg_pp2_iter0 == 1'b0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
ap_NS_fsm = ap_ST_fsm_pp2_stage0;
end else if (((1'b0 == ap_block_pp2_stage0_subdone) & (ap_enable_reg_pp2_iter0 == 1'b0) & (ap_enable_reg_pp2_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp2_stage0))) begin
ap_NS_fsm = ap_ST_fsm_state10;
end else begin
ap_NS_fsm = ap_ST_fsm_pp2_stage0;
end
end
ap_ST_fsm_state10 : begin
ap_NS_fsm = ap_ST_fsm_state4;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign AXI_video_strm_V_data_V_0_ack_in = AXI_video_strm_V_data_V_0_state[1'd1];
assign AXI_video_strm_V_data_V_0_load_A = (~AXI_video_strm_V_data_V_0_sel_wr & AXI_video_strm_V_data_V_0_state_cmp_full);
assign AXI_video_strm_V_data_V_0_load_B = (AXI_video_strm_V_data_V_0_state_cmp_full & AXI_video_strm_V_data_V_0_sel_wr);
assign AXI_video_strm_V_data_V_0_sel = AXI_video_strm_V_data_V_0_sel_rd;
assign AXI_video_strm_V_data_V_0_state_cmp_full = ((AXI_video_strm_V_data_V_0_state != 2'd1) ? 1'b1 : 1'b0);
assign AXI_video_strm_V_data_V_0_vld_in = stream_in_TVALID;
assign AXI_video_strm_V_data_V_0_vld_out = AXI_video_strm_V_data_V_0_state[1'd0];
assign AXI_video_strm_V_dest_V_0_vld_in = stream_in_TVALID;
assign AXI_video_strm_V_last_V_0_ack_in = AXI_video_strm_V_last_V_0_state[1'd1];
assign AXI_video_strm_V_last_V_0_load_A = (~AXI_video_strm_V_last_V_0_sel_wr & AXI_video_strm_V_last_V_0_state_cmp_full);
assign AXI_video_strm_V_last_V_0_load_B = (AXI_video_strm_V_last_V_0_state_cmp_full & AXI_video_strm_V_last_V_0_sel_wr);
assign AXI_video_strm_V_last_V_0_sel = AXI_video_strm_V_last_V_0_sel_rd;
assign AXI_video_strm_V_last_V_0_state_cmp_full = ((AXI_video_strm_V_last_V_0_state != 2'd1) ? 1'b1 : 1'b0);
assign AXI_video_strm_V_last_V_0_vld_in = stream_in_TVALID;
assign AXI_video_strm_V_last_V_0_vld_out = AXI_video_strm_V_last_V_0_state[1'd0];
assign AXI_video_strm_V_user_V_0_ack_in = AXI_video_strm_V_user_V_0_state[1'd1];
assign AXI_video_strm_V_user_V_0_load_A = (~AXI_video_strm_V_user_V_0_sel_wr & AXI_video_strm_V_user_V_0_state_cmp_full);
assign AXI_video_strm_V_user_V_0_load_B = (AXI_video_strm_V_user_V_0_state_cmp_full & AXI_video_strm_V_user_V_0_sel_wr);
assign AXI_video_strm_V_user_V_0_sel = AXI_video_strm_V_user_V_0_sel_rd;
assign AXI_video_strm_V_user_V_0_state_cmp_full = ((AXI_video_strm_V_user_V_0_state != 2'd1) ? 1'b1 : 1'b0);
assign AXI_video_strm_V_user_V_0_vld_in = stream_in_TVALID;
assign AXI_video_strm_V_user_V_0_vld_out = AXI_video_strm_V_user_V_0_state[1'd0];
assign ap_CS_fsm_pp1_stage0 = ap_CS_fsm[32'd4];
assign ap_CS_fsm_pp2_stage0 = ap_CS_fsm[32'd6];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state10 = ap_CS_fsm[32'd7];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state7 = ap_CS_fsm[32'd5];
assign ap_block_pp1_stage0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp1_stage0_01001 = ((ap_enable_reg_pp1_iter1 == 1'b1) & (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_predicate_op62_read_state6 == 1'b1)) | ((exitcond_reg_420 == 1'd0) & (img_data_stream_2_V_full_n == 1'b0)) | ((exitcond_reg_420 == 1'd0) & (img_data_stream_1_V_full_n == 1'b0)) | ((exitcond_reg_420 == 1'd0) & (img_data_stream_0_V_full_n == 1'b0))));
end
always @ (*) begin
ap_block_pp1_stage0_11001 = ((ap_enable_reg_pp1_iter1 == 1'b1) & (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_predicate_op62_read_state6 == 1'b1)) | ((exitcond_reg_420 == 1'd0) & (img_data_stream_2_V_full_n == 1'b0)) | ((exitcond_reg_420 == 1'd0) & (img_data_stream_1_V_full_n == 1'b0)) | ((exitcond_reg_420 == 1'd0) & (img_data_stream_0_V_full_n == 1'b0))));
end
always @ (*) begin
ap_block_pp1_stage0_subdone = ((ap_enable_reg_pp1_iter1 == 1'b1) & (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_predicate_op62_read_state6 == 1'b1)) | ((exitcond_reg_420 == 1'd0) & (img_data_stream_2_V_full_n == 1'b0)) | ((exitcond_reg_420 == 1'd0) & (img_data_stream_1_V_full_n == 1'b0)) | ((exitcond_reg_420 == 1'd0) & (img_data_stream_0_V_full_n == 1'b0))));
end
assign ap_block_pp2_stage0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp2_stage0_11001 = ((eol_2_reg_248 == 1'd0) & (1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_enable_reg_pp2_iter1 == 1'b1));
end
always @ (*) begin
ap_block_pp2_stage0_subdone = ((eol_2_reg_248 == 1'd0) & (1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_enable_reg_pp2_iter1 == 1'b1));
end
always @ (*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_block_state5_pp1_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state6_pp1_stage0_iter1 = (((1'b0 == AXI_video_strm_V_data_V_0_vld_out) & (ap_predicate_op62_read_state6 == 1'b1)) | ((exitcond_reg_420 == 1'd0) & (img_data_stream_2_V_full_n == 1'b0)) | ((exitcond_reg_420 == 1'd0) & (img_data_stream_1_V_full_n == 1'b0)) | ((exitcond_reg_420 == 1'd0) & (img_data_stream_0_V_full_n == 1'b0)));
end
assign ap_block_state8_pp2_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state9_pp2_stage0_iter1 = ((eol_2_reg_248 == 1'd0) & (1'b0 == AXI_video_strm_V_data_V_0_vld_out));
end
always @ (*) begin
ap_condition_495 = ((exitcond_reg_420 == 1'd0) & (1'b0 == ap_block_pp1_stage0) & (ap_enable_reg_pp1_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp1_stage0));
end
assign ap_enable_pp1 = (ap_idle_pp1 ^ 1'b1);
assign ap_enable_pp2 = (ap_idle_pp2 ^ 1'b1);
assign ap_phi_reg_pp1_iter1_axi_last_V_2_reg_223 = 'bx;
assign ap_phi_reg_pp1_iter1_p_Val2_s_reg_236 = 'bx;
always @ (*) begin
ap_predicate_op62_read_state6 = ((brmerge_reg_429 == 1'd0) & (exitcond_reg_420 == 1'd0));
end
assign brmerge_fu_343_p2 = (sof_1_fu_92 | ap_phi_mux_eol_phi_fu_193_p4);
assign exitcond2_fu_314_p2 = ((t_V_cast_fu_310_p1 == tmp_13_reg_381) ? 1'b1 : 1'b0);
assign exitcond_fu_329_p2 = ((t_V_3_cast_fu_325_p1 == tmp_14_reg_386) ? 1'b1 : 1'b0);
assign i_V_fu_319_p2 = (t_V_reg_167 + 11'd1);
assign img_data_stream_0_V_din = ap_phi_mux_p_Val2_s_phi_fu_240_p4[7:0];
assign img_data_stream_1_V_din = {{ap_phi_mux_p_Val2_s_phi_fu_240_p4[15:8]}};
assign img_data_stream_2_V_din = {{ap_phi_mux_p_Val2_s_phi_fu_240_p4[23:16]}};
assign j_V_fu_334_p2 = (t_V_2_reg_178 + 11'd1);
assign stream_in_TREADY = AXI_video_strm_V_dest_V_0_state[1'd1];
assign t_V_3_cast_fu_325_p1 = t_V_2_reg_178;
assign t_V_cast_fu_310_p1 = t_V_reg_167;
assign tmp_13_fu_293_p1 = img_rows_V_read[11:0];
assign tmp_14_fu_297_p1 = img_cols_V_read[11:0];
assign tmp_user_V_fu_301_p1 = AXI_video_strm_V_user_V_0_data_out;
endmodule //AXIvideo2Mat
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DFXTP_PP_BLACKBOX_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXTP_PP_BLACKBOX_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "bd_c3fe_slot_0_ar_0,xlconcat_v2_1_1_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "bd_c3fe_slot_0_ar_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_W\
IDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_c3fe_slot_0_ar_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_CH0_THRESH (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 23: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 23: 0] data_out;
wire [ 23: 0] out_port;
wire [ 23: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {24 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[23 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:27:21 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n511, n512, n513,
n514, n515, n516, n517, n518, n519, n520, n521, n522, n523, n524,
n525, n526, n527, n528, n529, n530, n531, n532, n533, n534, n535,
n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, n546,
n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568,
n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590,
n591, n592, n593, n594, n595, n596, n597, n599, n600, n601, n602,
n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624,
n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635,
n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646,
n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657,
n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668,
n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690,
n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712,
n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734,
n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n746,
n747, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758,
n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769,
n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780,
n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791,
n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802,
n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813,
n814, n815, n817, n818, n819, n820, n821, n822, n823, n824, n825,
n826, n827, n828, n829, n830, n831, n832, n833, n834, n835, n836,
n837, n838, n839, n840, n841, n842, n843, n844, n845, n846, n847,
n848, n849, n850, n851, n852, n853, n854, n855, n856, n857, n858,
n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, n869,
n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880,
n881, n882, n883, n884, n885, n886, n887, n888, n889, n890, n891,
n892, n893, n894, n895, n896, n897, n898, n899, n900, n901, n902,
n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913,
n914, n915, n916, n917, n918, n919, DP_OP_15J33_125_2314_n8,
DP_OP_15J33_125_2314_n7, DP_OP_15J33_125_2314_n6,
DP_OP_15J33_125_2314_n5, DP_OP_15J33_125_2314_n4, intadd_33_B_2_,
intadd_33_B_1_, intadd_33_B_0_, intadd_33_CI, intadd_33_SUM_2_,
intadd_33_SUM_1_, intadd_33_SUM_0_, intadd_33_n3, intadd_33_n2,
intadd_33_n1, intadd_34_B_2_, intadd_34_B_1_, intadd_34_B_0_,
intadd_34_CI, intadd_34_SUM_2_, intadd_34_SUM_1_, intadd_34_SUM_0_,
intadd_34_n3, intadd_34_n2, intadd_34_n1, n921, n922, n923, n924,
n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935,
n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946,
n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957,
n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990,
n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001,
n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011,
n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021,
n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,
n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041,
n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051,
n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061,
n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071,
n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081,
n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091,
n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442,
n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452,
n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462,
n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482,
n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492,
n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502,
n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512,
n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522,
n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532,
n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542,
n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552,
n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562,
n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572,
n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582,
n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592,
n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602,
n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612,
n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622,
n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632,
n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642,
n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652,
n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662,
n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672,
n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682,
n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692,
n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n917), .CK(clk), .RN(n1744), .Q(
Shift_reg_FLAGS_7_6), .QN(n972) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n914), .CK(clk), .RN(n1744), .Q(
Shift_reg_FLAGS_7[3]) );
DFFRXLTS inst_ShiftRegister_Q_reg_2_ ( .D(n913), .CK(clk), .RN(n1783), .Q(
Shift_reg_FLAGS_7[2]), .QN(n1739) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n878), .CK(clk), .RN(n1748), .Q(
intAS) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n812), .CK(clk), .RN(n1754),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n811), .CK(clk), .RN(n1754),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n810), .CK(clk), .RN(n1754),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n801), .CK(clk), .RN(n1179), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n800), .CK(clk), .RN(n1758), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n799), .CK(clk), .RN(n1183), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n798), .CK(clk), .RN(n1756), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n797), .CK(clk), .RN(n1755), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n796), .CK(clk), .RN(n1182), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n795), .CK(clk), .RN(n1180), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n794), .CK(clk), .RN(n1179), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n793), .CK(clk), .RN(n1181), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n792), .CK(clk), .RN(n1759), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n791), .CK(clk), .RN(n1183), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n790), .CK(clk), .RN(n1183), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n789), .CK(clk), .RN(n1758), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n788), .CK(clk), .RN(n1756), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n787), .CK(clk), .RN(n1755), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1182), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n785), .CK(clk), .RN(n1180), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n784), .CK(clk), .RN(n1179), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n783), .CK(clk), .RN(n1181), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n782), .CK(clk), .RN(n1759), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n781), .CK(clk), .RN(n1180), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n780), .CK(clk), .RN(n1179), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n779), .CK(clk), .RN(n1181), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n773), .CK(clk), .RN(n1759), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n772), .CK(clk), .RN(n1759), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n771), .CK(clk), .RN(n1757), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n770), .CK(clk), .RN(n1757), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n769), .CK(clk), .RN(n1757), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n768), .CK(clk), .RN(n1757), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n767), .CK(clk), .RN(n1757), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1757), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n764), .CK(clk), .RN(n1757), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n763), .CK(clk), .RN(n1757), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n761), .CK(clk), .RN(n1759), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n760), .CK(clk), .RN(n1183), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n758), .CK(clk), .RN(n1183), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n757), .CK(clk), .RN(n1758), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n755), .CK(clk), .RN(n1756), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n754), .CK(clk), .RN(n1755), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n752), .CK(clk), .RN(n1182), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n751), .CK(clk), .RN(n1183), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n749), .CK(clk), .RN(n1179), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1743), .CK(clk), .RN(n1782), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1758), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1742), .CK(clk), .RN(n1782), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n743), .CK(clk), .RN(n1756), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n742), .CK(clk), .RN(n1755), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n740), .CK(clk), .RN(n1182), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n739), .CK(clk), .RN(n1180), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n737), .CK(clk), .RN(n1179), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n736), .CK(clk), .RN(n1181), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n734), .CK(clk), .RN(n1760), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n733), .CK(clk), .RN(n1760), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n731), .CK(clk), .RN(n1760), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n730), .CK(clk), .RN(n1760), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n728), .CK(clk), .RN(n1760), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n727), .CK(clk), .RN(n1760), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n725), .CK(clk), .RN(n1760), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n724), .CK(clk), .RN(n1760), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n722), .CK(clk), .RN(n1760), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n721), .CK(clk), .RN(n1760), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n719), .CK(clk), .RN(n1761), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n718), .CK(clk), .RN(n1761), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n716), .CK(clk), .RN(n1761), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n715), .CK(clk), .RN(n1761), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n713), .CK(clk), .RN(n1761), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n712), .CK(clk), .RN(n1761), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n710), .CK(clk), .RN(n1761), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n709), .CK(clk), .RN(n1761), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n707), .CK(clk), .RN(n1761), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n706), .CK(clk), .RN(n1761), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n704), .CK(clk), .RN(n1762), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n703), .CK(clk), .RN(n1762), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n701), .CK(clk), .RN(n1762), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n700), .CK(clk), .RN(n1762), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n698), .CK(clk), .RN(n1762), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n697), .CK(clk), .RN(n1762), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n696), .CK(clk), .RN(n1762), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n695), .CK(clk), .RN(n1762), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n693), .CK(clk), .RN(n1762), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n692), .CK(clk), .RN(n1762), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n691), .CK(clk), .RN(n1763), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n690), .CK(clk), .RN(n1763), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n688), .CK(clk), .RN(n1763), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n687), .CK(clk), .RN(n1763), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n686), .CK(clk), .RN(n1763), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n685), .CK(clk), .RN(n1763), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n683), .CK(clk), .RN(n1763), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n682), .CK(clk), .RN(n1763), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n681), .CK(clk), .RN(n1763), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n680), .CK(clk), .RN(n1763), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n678), .CK(clk), .RN(n1764), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n677), .CK(clk), .RN(n1764), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n676), .CK(clk), .RN(n1764), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n675), .CK(clk), .RN(n1764), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n673), .CK(clk), .RN(n1764), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n672), .CK(clk), .RN(n1764), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n671), .CK(clk), .RN(n1764), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n670), .CK(clk), .RN(n1764), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n668), .CK(clk), .RN(n1764), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n667), .CK(clk), .RN(n1764), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n666), .CK(clk), .RN(n1765), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n665), .CK(clk), .RN(n1765), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n663), .CK(clk), .RN(n1765), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n662), .CK(clk), .RN(n1765), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n661), .CK(clk), .RN(n1765), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n660), .CK(clk), .RN(n1765), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n658), .CK(clk), .RN(n1765), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n656), .CK(clk), .RN(n1765), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n654), .CK(clk), .RN(n1766), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n652), .CK(clk), .RN(n1766), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n650), .CK(clk), .RN(n1766), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n648), .CK(clk), .RN(n1766), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n646), .CK(clk), .RN(n1766), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n644), .CK(clk), .RN(n1767), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n642), .CK(clk), .RN(n1767), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n640), .CK(clk), .RN(n1767), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n638), .CK(clk), .RN(n1767), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n636), .CK(clk), .RN(n1767), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n634), .CK(clk), .RN(n1768), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n632), .CK(clk), .RN(n1768), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n630), .CK(clk), .RN(n1768), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n628), .CK(clk), .RN(n1768), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n626), .CK(clk), .RN(n1768), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n624), .CK(clk), .RN(n1769), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n622), .CK(clk), .RN(n1769), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n620), .CK(clk), .RN(n1769), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n618), .CK(clk), .RN(n1769), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n616), .CK(clk), .RN(n1769), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n614), .CK(clk), .RN(n1770), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n605), .CK(clk), .RN(n1770), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n604), .CK(clk), .RN(n1770), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n603), .CK(clk), .RN(n1771), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n602), .CK(clk), .RN(n1771), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n601), .CK(clk), .RN(n1771), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n599), .CK(clk), .RN(n1771), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1741), .CK(clk), .RN(n1783), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n596), .CK(clk), .RN(n1771), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n595), .CK(clk), .RN(n1771), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n594), .CK(clk), .RN(n1771), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n593), .CK(clk), .RN(n1771), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n592), .CK(clk), .RN(n1771), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n589), .CK(clk), .RN(n1778), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n584), .CK(clk), .RN(n1779), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n574), .CK(clk), .RN(n1777), .Q(
LZD_output_NRM2_EW[4]), .QN(n1688) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n573), .CK(clk), .RN(n1772), .Q(
DmP_mant_SFG_SWR[1]), .QN(n1738) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n571), .CK(clk), .RN(n1777), .Q(
LZD_output_NRM2_EW[2]), .QN(n1691) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n565), .CK(clk), .RN(n1772), .Q(
DmP_mant_SFG_SWR[0]), .QN(n969) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n563), .CK(clk), .RN(n1772), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n560), .CK(clk), .RN(n1777), .Q(
LZD_output_NRM2_EW[3]), .QN(n1690) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n559), .CK(clk), .RN(n1776), .Q(
LZD_output_NRM2_EW[1]), .QN(n1689) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n558), .CK(clk), .RN(n1772), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n550), .CK(clk), .RN(n1773), .Q(
DmP_mant_SFG_SWR[4]), .QN(n1720) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n534), .CK(clk), .RN(n1774), .Q(
DmP_mant_SFG_SWR[7]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n512), .CK(clk), .RN(n1780), .Q(
DmP_mant_SFG_SWR[24]) );
CMPR32X2TS intadd_33_U4 ( .A(n928), .B(intadd_33_B_0_), .C(intadd_33_CI),
.CO(intadd_33_n3), .S(intadd_33_SUM_0_) );
CMPR32X2TS intadd_33_U3 ( .A(n925), .B(intadd_33_B_1_), .C(intadd_33_n3),
.CO(intadd_33_n2), .S(intadd_33_SUM_1_) );
CMPR32X2TS intadd_33_U2 ( .A(n1669), .B(intadd_33_B_2_), .C(intadd_33_n2),
.CO(intadd_33_n1), .S(intadd_33_SUM_2_) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1748),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n600), .CK(clk), .RN(n1771), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n549), .CK(clk), .RN(n1773), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n548), .CK(clk), .RN(n1773), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n541), .CK(clk), .RN(n1774), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n540), .CK(clk), .RN(n1774), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n529), .CK(clk), .RN(n1775), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n528), .CK(clk), .RN(n1775), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n525), .CK(clk), .RN(n1775), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1770), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1775), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n802), .CK(clk), .RN(n1776), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n552), .CK(clk), .RN(n1773), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n551), .CK(clk), .RN(n1773), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n544), .CK(clk), .RN(n1773), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n543), .CK(clk), .RN(n1774), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n539), .CK(clk), .RN(n1774), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n538), .CK(clk), .RN(n1774), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n536), .CK(clk), .RN(n1774), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n535), .CK(clk), .RN(n1774), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n533), .CK(clk), .RN(n1774), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n532), .CK(clk), .RN(n1775), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n531), .CK(clk), .RN(n1775), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n530), .CK(clk), .RN(n1775), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n527), .CK(clk), .RN(n1775), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n526), .CK(clk), .RN(n1775), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n591), .CK(clk), .RN(n1775), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n809), .CK(clk), .RN(n1776), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n808), .CK(clk), .RN(n1776), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n807), .CK(clk), .RN(n1776), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n806), .CK(clk), .RN(n1776), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n805), .CK(clk), .RN(n1776), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n804), .CK(clk), .RN(n1776), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n803), .CK(clk), .RN(n1776), .Q(
final_result_ieee[29]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n907), .CK(clk), .RN(n1745), .Q(
intDX_EWSW[3]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n572), .CK(clk), .RN(n1778), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1730) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n562), .CK(clk), .RN(n1772), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1676) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n561), .CK(clk), .RN(n1772), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1665) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1744), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1657) );
DFFRX2TS inst_ShiftRegister_Q_reg_0_ ( .D(n911), .CK(clk), .RN(n1744), .Q(
Shift_reg_FLAGS_7[0]), .QN(n1723) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n557), .CK(clk), .RN(n1772), .Q(
Raw_mant_NRM_SWR[4]), .QN(n1653) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n588), .CK(clk), .RN(n1778), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1673) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n568), .CK(clk), .RN(n1778), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1695) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n818), .CK(clk), .RN(n1751), .Q(
shift_value_SHT2_EWR[2]), .QN(n1682) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n817), .CK(clk), .RN(n1752), .Q(
shift_value_SHT2_EWR[3]), .QN(n1683) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n555), .CK(clk), .RN(n1772), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1654) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n882), .CK(clk), .RN(n1747),
.Q(intDX_EWSW[28]), .QN(n1716) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n886), .CK(clk), .RN(n1747),
.Q(intDX_EWSW[24]), .QN(n1731) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n884), .CK(clk), .RN(n1747),
.Q(intDX_EWSW[26]), .QN(n1671) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n885), .CK(clk), .RN(n1747),
.Q(intDX_EWSW[25]), .QN(n1670) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n862), .CK(clk), .RN(n1749),
.Q(intDY_EWSW[14]), .QN(n1710) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n863), .CK(clk), .RN(n1749),
.Q(intDY_EWSW[13]), .QN(n1704) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n864), .CK(clk), .RN(n1749),
.Q(intDY_EWSW[12]), .QN(n1709) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n859), .CK(clk), .RN(n1750),
.Q(intDY_EWSW[17]), .QN(n1702) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n861), .CK(clk), .RN(n1749),
.Q(intDY_EWSW[15]), .QN(n1661) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n865), .CK(clk), .RN(n1749),
.Q(intDY_EWSW[11]), .QN(n1686) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n868), .CK(clk), .RN(n1749), .Q(
intDY_EWSW[8]), .QN(n1706) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n873), .CK(clk), .RN(n1748), .Q(
intDY_EWSW[3]), .QN(n1701) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n853), .CK(clk), .RN(n1750),
.Q(intDY_EWSW[23]), .QN(n1715) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n854), .CK(clk), .RN(n1750),
.Q(intDY_EWSW[22]), .QN(n1662) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n855), .CK(clk), .RN(n1750),
.Q(intDY_EWSW[21]), .QN(n1705) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n856), .CK(clk), .RN(n1750),
.Q(intDY_EWSW[20]), .QN(n1712) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n850), .CK(clk), .RN(n1751),
.Q(intDY_EWSW[26]), .QN(n1699) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n851), .CK(clk), .RN(n1750),
.Q(intDY_EWSW[25]), .QN(n1700) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n858), .CK(clk), .RN(n1750),
.Q(intDY_EWSW[18]), .QN(n1717) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n575), .CK(clk), .RN(n1772), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1672) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n894), .CK(clk), .RN(n1746),
.Q(intDX_EWSW[16]), .QN(n1681) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n903), .CK(clk), .RN(n1745), .Q(
intDX_EWSW[7]), .QN(n1678) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n904), .CK(clk), .RN(n1745), .Q(
intDX_EWSW[6]), .QN(n1655) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n905), .CK(clk), .RN(n1745), .Q(
intDX_EWSW[5]), .QN(n1677) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n906), .CK(clk), .RN(n1745), .Q(
intDX_EWSW[4]), .QN(n1652) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n569), .CK(clk), .RN(n1778), .Q(
Raw_mant_NRM_SWR[8]) );
DFFRX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n597), .CK(clk), .RN(n1783), .Q(n1784), .QN(n1785) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n590), .CK(clk), .RN(n1778), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1675) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n567), .CK(clk), .RN(n1778), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1684) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n875), .CK(clk), .RN(n1748), .Q(
intDY_EWSW[1]), .QN(n1787) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n844), .CK(clk), .RN(n1752), .Q(
Data_array_SWR[25]), .QN(n1659) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n831), .CK(clk), .RN(n1752), .Q(
Data_array_SWR[12]), .QN(n1729) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n839), .CK(clk), .RN(n1753), .Q(
Data_array_SWR[20]), .QN(n1735) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n842), .CK(clk), .RN(n1752), .Q(
Data_array_SWR[23]), .QN(n1726) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n582), .CK(clk), .RN(n1779), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n577), .CK(clk), .RN(n1779), .Q(
Raw_mant_NRM_SWR[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n546), .CK(clk), .RN(n1773), .Q(
final_result_ieee[11]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n694), .CK(clk), .RN(n1777), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1679) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n738), .CK(clk), .RN(n1782), .Q(
DMP_SFG[9]), .QN(n1687) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n880), .CK(clk), .RN(n1747),
.Q(intDX_EWSW[30]), .QN(n1663) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n828), .CK(clk), .RN(n1752), .Q(
Data_array_SWR[9]), .QN(n1734) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n841), .CK(clk), .RN(n1751), .Q(
Data_array_SWR[22]), .QN(n1725) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n887), .CK(clk), .RN(n1747),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n895), .CK(clk), .RN(n1746),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n897), .CK(clk), .RN(n1746),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n889), .CK(clk), .RN(n1747),
.Q(intDX_EWSW[21]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n815), .CK(clk), .RN(n1751), .Q(
shift_value_SHT2_EWR[4]), .QN(n923) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n902), .CK(clk), .RN(n1745), .Q(
intDX_EWSW[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n843), .CK(clk), .RN(n1752), .Q(
Data_array_SWR[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n893), .CK(clk), .RN(n1746),
.Q(intDX_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n899), .CK(clk), .RN(n1746),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n901), .CK(clk), .RN(n1745), .Q(
intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n883), .CK(clk), .RN(n1747),
.Q(intDX_EWSW[27]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n908), .CK(clk), .RN(n1745), .Q(
intDX_EWSW[2]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n556), .CK(clk), .RN(n1772), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n832), .CK(clk), .RN(n1752), .Q(
Data_array_SWR[13]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n919), .CK(clk), .RN(
n1744), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n892), .CK(clk), .RN(n1746),
.Q(intDX_EWSW[18]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n910), .CK(clk), .RN(n1744), .Q(
intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n891), .CK(clk), .RN(n1746),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n834), .CK(clk), .RN(n1754), .Q(
Data_array_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n838), .CK(clk), .RN(n1753), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n827), .CK(clk), .RN(n1753), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n837), .CK(clk), .RN(n1753), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n835), .CK(clk), .RN(n1754), .Q(
Data_array_SWR[16]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n741), .CK(clk), .RN(n1782), .Q(
DMP_SFG[8]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n823), .CK(clk), .RN(n1753), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n824), .CK(clk), .RN(n1753), .Q(
Data_array_SWR[5]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n879), .CK(clk), .RN(n1748),
.Q(intDX_EWSW[31]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n714), .CK(clk), .RN(n1781), .Q(
DMP_SFG[17]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n720), .CK(clk), .RN(n1781), .Q(
DMP_SFG[15]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1782), .Q(
DMP_SFG[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n833), .CK(clk), .RN(n1752), .Q(
Data_array_SWR[14]), .QN(n1666) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n723), .CK(clk), .RN(n1781), .Q(
DMP_SFG[14]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n717), .CK(clk), .RN(n1781), .Q(
DMP_SFG[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n613), .CK(clk), .RN(n1770), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n765), .CK(clk), .RN(n1757), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n750), .CK(clk), .RN(n1756), .Q(
DMP_SFG[5]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n566), .CK(clk), .RN(n1776), .Q(
LZD_output_NRM2_EW[0]), .QN(n970) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n813), .CK(clk), .RN(n1754),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n674), .CK(clk), .RN(n1777), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n679), .CK(clk), .RN(n1777), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n684), .CK(clk), .RN(n1777), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n689), .CK(clk), .RN(n1777), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n726), .CK(clk), .RN(n1783), .Q(
DMP_SFG[13]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n729), .CK(clk), .RN(n1783), .Q(
DMP_SFG[12]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n732), .CK(clk), .RN(n1783), .Q(
DMP_SFG[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n735), .CK(clk), .RN(n1783), .Q(
DMP_SFG[10]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n702), .CK(clk), .RN(n1781), .Q(
DMP_SFG[21]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n708), .CK(clk), .RN(n1781), .Q(
DMP_SFG[19]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n699), .CK(clk), .RN(n1781), .Q(
DMP_SFG[22]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n705), .CK(clk), .RN(n1781), .Q(
DMP_SFG[20]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n711), .CK(clk), .RN(n1781), .Q(
DMP_SFG[18]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n609), .CK(clk), .RN(n1770), .Q(
DmP_EXP_EWSW[26]), .QN(n929) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n553), .CK(clk), .RN(n1773), .Q(
DmP_mant_SFG_SWR[6]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n848), .CK(clk), .RN(n1751),
.Q(intDY_EWSW[28]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n821), .CK(clk), .RN(n1754), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n822), .CK(clk), .RN(n1753), .Q(
Data_array_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n545), .CK(clk), .RN(n1782), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n756), .CK(clk), .RN(n1755), .Q(
DMP_SFG[3]), .QN(n925) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n759), .CK(clk), .RN(n1182), .Q(
DMP_SFG[2]), .QN(n928) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n845), .CK(clk), .RN(n1751),
.Q(intDY_EWSW[31]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n610), .CK(clk), .RN(n1770), .Q(
DmP_EXP_EWSW[25]), .QN(n1733) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n523), .CK(clk), .RN(n1783), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n524), .CK(clk), .RN(n1782), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n515), .CK(clk), .RN(n1780), .Q(
DmP_mant_SFG_SWR[21]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n516), .CK(clk), .RN(n1780), .Q(
DmP_mant_SFG_SWR[20]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n519), .CK(clk), .RN(n1780), .Q(
DmP_mant_SFG_SWR[17]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n570), .CK(clk), .RN(n1782), .Q(
DmP_mant_SFG_SWR[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n909), .CK(clk), .RN(n1745), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n898), .CK(clk), .RN(n1746),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n890), .CK(clk), .RN(n1746),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n896), .CK(clk), .RN(n1746),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n888), .CK(clk), .RN(n1747),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n900), .CK(clk), .RN(n1745),
.Q(intDX_EWSW[10]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n836), .CK(clk), .RN(n1754), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n830), .CK(clk), .RN(n1752), .Q(
Data_array_SWR[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n744), .CK(clk), .RN(n1782), .Q(
DMP_SFG[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n651), .CK(clk), .RN(n1766), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n641), .CK(clk), .RN(n1767), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n637), .CK(clk), .RN(n1767), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n633), .CK(clk), .RN(n1768), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n621), .CK(clk), .RN(n1769), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n619), .CK(clk), .RN(n1769), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n629), .CK(clk), .RN(n1768), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n655), .CK(clk), .RN(n1765), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n774), .CK(clk), .RN(n1180), .Q(
DMP_EXP_EWSW[27]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n627), .CK(clk), .RN(n1768), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n776), .CK(clk), .RN(n1179), .Q(
DMP_EXP_EWSW[25]), .QN(n966) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n657), .CK(clk), .RN(n1765), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n647), .CK(clk), .RN(n1766), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n775), .CK(clk), .RN(n1181), .Q(
DMP_EXP_EWSW[26]), .QN(n1732) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n615), .CK(clk), .RN(n1769), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n653), .CK(clk), .RN(n1766), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n645), .CK(clk), .RN(n1766), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n639), .CK(clk), .RN(n1767), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n635), .CK(clk), .RN(n1767), .Q(
DmP_mant_SHT1_SW[11]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n631), .CK(clk), .RN(n1768), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n617), .CK(clk), .RN(n1769), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n643), .CK(clk), .RN(n1767), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n625), .CK(clk), .RN(n1768), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n623), .CK(clk), .RN(n1769), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n814), .CK(clk), .RN(n1754),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n576), .CK(clk), .RN(n1781), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n612), .CK(clk), .RN(n1770), .Q(
DmP_EXP_EWSW[23]), .QN(n967) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n542), .CK(clk), .RN(n1774), .Q(
DmP_mant_SFG_SWR[5]), .QN(n968) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n537), .CK(clk), .RN(n1782), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n608), .CK(clk), .RN(n1770), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n819), .CK(clk), .RN(n1751), .Q(
Data_array_SWR[0]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n820), .CK(clk), .RN(n1754), .Q(
Data_array_SWR[1]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n521), .CK(clk), .RN(n1783), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n520), .CK(clk), .RN(n1780), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n518), .CK(clk), .RN(n1780), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n517), .CK(clk), .RN(n1780), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n514), .CK(clk), .RN(n1780), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n513), .CK(clk), .RN(n1780), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n511), .CK(clk), .RN(n1780), .Q(
DmP_mant_SFG_SWR[25]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n649), .CK(clk), .RN(n1766), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRX2TS inst_ShiftRegister_Q_reg_4_ ( .D(n915), .CK(clk), .RN(n1744), .Q(
busy), .QN(n1786) );
DFFRX1TS inst_ShiftRegister_Q_reg_1_ ( .D(n912), .CK(clk), .RN(n1744), .Q(
Shift_reg_FLAGS_7[1]), .QN(n921) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n587), .CK(clk), .RN(n1779), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n586), .CK(clk), .RN(n1778), .Q(
Raw_mant_NRM_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n585), .CK(clk), .RN(n1779), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1721) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n583), .CK(clk), .RN(n1779), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n581), .CK(clk), .RN(n1779), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1698) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n580), .CK(clk), .RN(n1779), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1740) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n579), .CK(clk), .RN(n1779), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n578), .CK(clk), .RN(n1779), .Q(
Raw_mant_NRM_SWR[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n547), .CK(clk), .RN(n1773), .Q(
final_result_ieee[10]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n659), .CK(clk), .RN(n1778), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1724) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n664), .CK(clk), .RN(n1777), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1696) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n669), .CK(clk), .RN(n1777), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1697) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n564), .CK(clk), .RN(n1778), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1736) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n918), .CK(clk), .RN(
n1744), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1694) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n762), .CK(clk), .RN(n1757), .Q(
DMP_SFG[1]), .QN(n1719) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n753), .CK(clk), .RN(n1183), .Q(
DMP_SFG[4]), .QN(n1669) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n846), .CK(clk), .RN(n1751),
.Q(intDY_EWSW[30]), .QN(n1656) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n847), .CK(clk), .RN(n1751),
.Q(intDY_EWSW[29]), .QN(n1685) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n866), .CK(clk), .RN(n1749),
.Q(intDY_EWSW[10]), .QN(n1680) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n876), .CK(clk), .RN(n1748), .Q(
intDY_EWSW[0]), .QN(n1660) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n867), .CK(clk), .RN(n1749), .Q(
intDY_EWSW[9]), .QN(n1703) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n874), .CK(clk), .RN(n1748), .Q(
intDY_EWSW[2]), .QN(n1707) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n860), .CK(clk), .RN(n1750),
.Q(intDY_EWSW[16]), .QN(n1711) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n870), .CK(clk), .RN(n1749), .Q(
intDY_EWSW[6]), .QN(n1692) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n881), .CK(clk), .RN(n1747),
.Q(intDX_EWSW[29]), .QN(n1714) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n872), .CK(clk), .RN(n1748), .Q(
intDY_EWSW[4]), .QN(n1708) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n869), .CK(clk), .RN(n1749), .Q(
intDY_EWSW[7]), .QN(n1693) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n871), .CK(clk), .RN(n1748), .Q(
intDY_EWSW[5]), .QN(n1658) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n857), .CK(clk), .RN(n1750),
.Q(intDY_EWSW[19]), .QN(n1664) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n849), .CK(clk), .RN(n1751),
.Q(intDY_EWSW[27]), .QN(n1713) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n852), .CK(clk), .RN(n1750),
.Q(intDY_EWSW[24]), .QN(n1650) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n829), .CK(clk), .RN(n1752), .Q(
Data_array_SWR[10]), .QN(n1722) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n825), .CK(clk), .RN(n1753), .Q(
Data_array_SWR[6]), .QN(n1727) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n826), .CK(clk), .RN(n1753), .Q(
Data_array_SWR[7]), .QN(n1728) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n840), .CK(clk), .RN(n1753), .Q(
Data_array_SWR[21]), .QN(n1718) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n777), .CK(clk), .RN(n1183), .Q(
DMP_EXP_EWSW[24]), .QN(n1668) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n611), .CK(clk), .RN(n1770), .Q(
DmP_EXP_EWSW[24]), .QN(n1667) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n778), .CK(clk), .RN(n1758), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n554), .CK(clk), .RN(n1773), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1674) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n522), .CK(clk), .RN(n1783), .Q(
DmP_mant_SFG_SWR[14]) );
CMPR32X2TS DP_OP_15J33_125_2314_U8 ( .A(n1689), .B(DMP_exp_NRM2_EW[1]), .C(
DP_OP_15J33_125_2314_n8), .CO(DP_OP_15J33_125_2314_n7), .S(
exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J33_125_2314_U7 ( .A(n1691), .B(DMP_exp_NRM2_EW[2]), .C(
DP_OP_15J33_125_2314_n7), .CO(DP_OP_15J33_125_2314_n6), .S(
exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_15J33_125_2314_U6 ( .A(n1690), .B(DMP_exp_NRM2_EW[3]), .C(
DP_OP_15J33_125_2314_n6), .CO(DP_OP_15J33_125_2314_n5), .S(
exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_15J33_125_2314_U5 ( .A(n1688), .B(DMP_exp_NRM2_EW[4]), .C(
DP_OP_15J33_125_2314_n5), .CO(DP_OP_15J33_125_2314_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n877), .CK(clk), .RN(n1748), .Q(
left_right_SHT2), .QN(n924) );
CMPR32X2TS intadd_34_U4 ( .A(DMP_SFG[6]), .B(intadd_34_B_0_), .C(
intadd_34_CI), .CO(intadd_34_n3), .S(intadd_34_SUM_0_) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n916), .CK(clk), .RN(n1744), .Q(
n1651), .QN(n1737) );
CMPR32X2TS intadd_34_U3 ( .A(DMP_SFG[7]), .B(intadd_34_B_1_), .C(
intadd_34_n3), .CO(intadd_34_n2), .S(intadd_34_SUM_1_) );
CMPR32X2TS intadd_34_U2 ( .A(DMP_SFG[8]), .B(intadd_34_B_2_), .C(
intadd_34_n2), .CO(intadd_34_n1), .S(intadd_34_SUM_2_) );
OAI2BB2XLTS U927 ( .B0(n1649), .B1(n1648), .A0N(final_result_ieee[22]),
.A1N(n1723), .Y(n525) );
INVX2TS U928 ( .A(n1648), .Y(n960) );
BUFX3TS U929 ( .A(n1398), .Y(n1330) );
AOI222X4TS U930 ( .A0(Data_array_SWR[20]), .A1(n958), .B0(Data_array_SWR[24]), .B1(n1235), .C0(Data_array_SWR[16]), .C1(n1259), .Y(n1232) );
AND2X2TS U931 ( .A(beg_OP), .B(n1533), .Y(n1536) );
NAND2X2TS U932 ( .A(n1041), .B(n1040), .Y(n1042) );
AO21X1TS U933 ( .A0(n1026), .A1(n1025), .B0(n1024), .Y(n1041) );
INVX2TS U934 ( .A(n1595), .Y(n1323) );
INVX2TS U935 ( .A(n921), .Y(n945) );
BUFX3TS U936 ( .A(Shift_reg_FLAGS_7_6), .Y(n1595) );
NAND2X1TS U937 ( .A(n1614), .B(DMP_SFG[0]), .Y(n1617) );
CMPR32X2TS U938 ( .A(n1493), .B(DMP_SFG[13]), .C(n1492), .CO(n1506), .S(
n1494) );
CMPR32X2TS U939 ( .A(n1509), .B(DMP_SFG[12]), .C(n1508), .CO(n1492), .S(
n1510) );
CMPR32X2TS U940 ( .A(n1512), .B(DMP_SFG[11]), .C(n1511), .CO(n1508), .S(
n1513) );
CMPR32X2TS U941 ( .A(n1515), .B(DMP_SFG[10]), .C(n1514), .CO(n1511), .S(
n1516) );
NAND2X4TS U942 ( .A(n1142), .B(n1673), .Y(n1046) );
NOR2XLTS U943 ( .A(n1071), .B(exp_rslt_NRM2_EW1[1]), .Y(n1057) );
NOR2XLTS U944 ( .A(n1058), .B(n1251), .Y(n1059) );
NAND2X4TS U945 ( .A(n1105), .B(n1672), .Y(n1087) );
INVX2TS U946 ( .A(n1287), .Y(n939) );
INVX2TS U947 ( .A(n1287), .Y(n940) );
BUFX3TS U948 ( .A(n1369), .Y(n1398) );
CLKINVX3TS U949 ( .A(n1371), .Y(n1395) );
OAI21XLTS U950 ( .A0(n1715), .A1(n1408), .B0(n1404), .Y(n778) );
OAI211XLTS U951 ( .A0(n1350), .A1(n952), .B0(n1284), .C0(n1283), .Y(n825) );
OAI21XLTS U952 ( .A0(n1234), .A1(n1441), .B0(n1233), .Y(n511) );
OAI21XLTS U953 ( .A0(n1713), .A1(n1346), .B0(n1333), .Y(n608) );
OAI21XLTS U954 ( .A0(n1713), .A1(n1596), .B0(n1403), .Y(n774) );
OAI211XLTS U955 ( .A0(n1357), .A1(n955), .B0(n1305), .C0(n1304), .Y(n830) );
OAI211XLTS U956 ( .A0(n1386), .A1(n951), .B0(n1385), .C0(n1384), .Y(n822) );
OAI21XLTS U957 ( .A0(n938), .A1(n923), .B0(n1055), .Y(n815) );
OAI211XLTS U958 ( .A0(n1360), .A1(n955), .B0(n1359), .C0(n1358), .Y(n828) );
OAI21XLTS U959 ( .A0(n1703), .A1(n1343), .B0(n1342), .Y(n640) );
OAI21XLTS U960 ( .A0(n1662), .A1(n1596), .B0(n1400), .Y(n779) );
INVX2TS U961 ( .A(n945), .Y(n1531) );
OR2X4TS U962 ( .A(n1531), .B(n1113), .Y(n1553) );
OAI21X1TS U963 ( .A0(n1549), .A1(n952), .B0(n1292), .Y(n842) );
OAI211X1TS U964 ( .A0(n1368), .A1(n954), .B0(n1367), .C0(n1366), .Y(n823) );
OAI211X1TS U965 ( .A0(n1297), .A1(n954), .B0(n1296), .C0(n1295), .Y(n820) );
OAI21X1TS U966 ( .A0(n1561), .A1(n955), .B0(n1280), .Y(n835) );
OAI21X1TS U967 ( .A0(n1567), .A1(n952), .B0(n1352), .Y(n827) );
OAI21X1TS U968 ( .A0(n1556), .A1(n951), .B0(n1290), .Y(n837) );
OAI211X1TS U969 ( .A0(n1413), .A1(n954), .B0(n1412), .C0(n1411), .Y(n838) );
OAI211X1TS U970 ( .A0(n1410), .A1(n955), .B0(n1376), .C0(n1375), .Y(n840) );
OAI21X1TS U971 ( .A0(n1665), .A1(n1553), .B0(n1552), .Y(n1554) );
AOI222X1TS U972 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n1361), .B0(n962), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1550), .C1(DmP_mant_SHT1_SW[8]), .Y(n1360)
);
AOI222X1TS U973 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1421), .B0(n963), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1558), .C1(DmP_mant_SHT1_SW[4]), .Y(n1386)
);
OAI21X1TS U974 ( .A0(n1653), .A1(n1563), .B0(n1285), .Y(n1286) );
OAI21X1TS U975 ( .A0(n1684), .A1(n1563), .B0(n1559), .Y(n1560) );
OAI21X1TS U976 ( .A0(n1675), .A1(n1563), .B0(n1562), .Y(n1564) );
OAI21X1TS U977 ( .A0(n1673), .A1(n1563), .B0(n1348), .Y(n1349) );
OAI211X2TS U978 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1107), .B0(n1106), .C0(
n1147), .Y(n1158) );
AO22X1TS U979 ( .A0(n960), .A1(n1643), .B0(final_result_ieee[8]), .B1(n1642),
.Y(n536) );
AO22X1TS U980 ( .A0(n960), .A1(n1442), .B0(final_result_ieee[14]), .B1(n1642), .Y(n543) );
AO22X1TS U981 ( .A0(n960), .A1(n1435), .B0(final_result_ieee[9]), .B1(n1642),
.Y(n539) );
AO22X1TS U982 ( .A0(n960), .A1(n1612), .B0(final_result_ieee[0]), .B1(n1642),
.Y(n530) );
AO22X1TS U983 ( .A0(n960), .A1(n1427), .B0(final_result_ieee[11]), .B1(n1642), .Y(n546) );
AO22X1TS U984 ( .A0(n960), .A1(n1438), .B0(final_result_ieee[20]), .B1(n1642), .Y(n527) );
AO22X1TS U985 ( .A0(n960), .A1(n1166), .B0(final_result_ieee[1]), .B1(n1646),
.Y(n531) );
OAI211X1TS U986 ( .A0(n1253), .A1(n1257), .B0(n1256), .C0(n1252), .Y(n804)
);
OAI211X1TS U987 ( .A0(n1247), .A1(n1257), .B0(n1256), .C0(n1246), .Y(n805)
);
OAI211X1TS U988 ( .A0(n1258), .A1(n1257), .B0(n1256), .C0(n1255), .Y(n806)
);
OAI211X1TS U989 ( .A0(n1250), .A1(n1257), .B0(n1256), .C0(n1249), .Y(n803)
);
OAI211X1TS U990 ( .A0(n1065), .A1(n1723), .B0(n1256), .C0(n1064), .Y(n808)
);
OAI211X1TS U991 ( .A0(n1069), .A1(n1723), .B0(n1256), .C0(n1068), .Y(n807)
);
OAI21X1TS U992 ( .A0(n1716), .A1(n1594), .B0(n1316), .Y(n773) );
OAI21X1TS U993 ( .A0(n1714), .A1(n1415), .B0(n1372), .Y(n772) );
OAI21X1TS U994 ( .A0(n1703), .A1(n1395), .B0(n1389), .Y(n792) );
OAI21X1TS U995 ( .A0(n1787), .A1(n1311), .B0(n1310), .Y(n800) );
OAI21X1TS U996 ( .A0(n1662), .A1(n1594), .B0(n1313), .Y(n614) );
OAI21X1TS U997 ( .A0(n1706), .A1(n1395), .B0(n1391), .Y(n793) );
OAI21X1TS U998 ( .A0(n1705), .A1(n1594), .B0(n1314), .Y(n616) );
OAI21X1TS U999 ( .A0(n1680), .A1(n1395), .B0(n1387), .Y(n791) );
OAI21X1TS U1000 ( .A0(n1693), .A1(n1395), .B0(n1377), .Y(n794) );
OAI21X1TS U1001 ( .A0(n1658), .A1(n1395), .B0(n1319), .Y(n796) );
OAI21X1TS U1002 ( .A0(n1686), .A1(n1395), .B0(n1390), .Y(n790) );
OAI21X1TS U1003 ( .A0(n1701), .A1(n1395), .B0(n1317), .Y(n798) );
OAI21X1TS U1004 ( .A0(n1712), .A1(n1594), .B0(n1312), .Y(n618) );
OAI21X1TS U1005 ( .A0(n1660), .A1(n1596), .B0(n1318), .Y(n801) );
OAI21X1TS U1006 ( .A0(n1664), .A1(n1346), .B0(n1331), .Y(n620) );
OAI21X1TS U1007 ( .A0(n1708), .A1(n1395), .B0(n1320), .Y(n797) );
OAI21X1TS U1008 ( .A0(n1692), .A1(n1395), .B0(n1321), .Y(n795) );
OAI21X1TS U1009 ( .A0(n1661), .A1(n1346), .B0(n1345), .Y(n628) );
OAI21X1TS U1010 ( .A0(n1707), .A1(n1311), .B0(n1309), .Y(n799) );
OAI21X1TS U1011 ( .A0(n1709), .A1(n1395), .B0(n1394), .Y(n789) );
INVX3TS U1012 ( .A(n1371), .Y(n1408) );
OAI21X1TS U1013 ( .A0(n1706), .A1(n1343), .B0(n1340), .Y(n642) );
OAI21X1TS U1014 ( .A0(n1708), .A1(n1343), .B0(n1332), .Y(n650) );
OAI21X1TS U1015 ( .A0(n1660), .A1(n1415), .B0(n1373), .Y(n658) );
OAI21X1TS U1016 ( .A0(n1701), .A1(n1343), .B0(n1326), .Y(n652) );
OAI21X1TS U1017 ( .A0(n1787), .A1(n1343), .B0(n1334), .Y(n656) );
INVX3TS U1018 ( .A(n1330), .Y(n1596) );
OAI21X1TS U1019 ( .A0(n1704), .A1(n1346), .B0(n1344), .Y(n632) );
OAI21X1TS U1020 ( .A0(n1709), .A1(n1346), .B0(n1341), .Y(n634) );
OAI21X1TS U1021 ( .A0(n1419), .A1(n1581), .B0(n1415), .Y(n1417) );
INVX2TS U1022 ( .A(n1325), .Y(n1343) );
INVX2TS U1023 ( .A(n1325), .Y(n1346) );
OAI21X1TS U1024 ( .A0(n1663), .A1(n1415), .B0(n1370), .Y(n771) );
CLKAND2X2TS U1025 ( .A(n1724), .B(n1076), .Y(n1077) );
INVX3TS U1026 ( .A(n971), .Y(n1594) );
OAI21X1TS U1027 ( .A0(n1645), .A1(n1274), .B0(n1245), .Y(n570) );
AOI31X1TS U1028 ( .A0(n1101), .A1(Raw_mant_NRM_SWR[16]), .A2(n1721), .B0(
n1100), .Y(n1110) );
OAI21X1TS U1029 ( .A0(n1274), .A1(n1647), .B0(n1267), .Y(n519) );
OAI21X1TS U1030 ( .A0(n1274), .A1(n1633), .B0(n1263), .Y(n515) );
NAND2BX1TS U1031 ( .AN(n1248), .B(n1059), .Y(n1062) );
INVX1TS U1032 ( .A(n1248), .Y(n1250) );
AOI222X1TS U1033 ( .A0(n1630), .A1(n1636), .B0(n936), .B1(Data_array_SWR[4]),
.C0(n1629), .C1(n1634), .Y(n1632) );
OAI21X1TS U1034 ( .A0(n1718), .A1(n1133), .B0(n1132), .Y(n1134) );
OAI221X1TS U1035 ( .A0(n946), .A1(n1141), .B0(n948), .B1(n1140), .C0(n1139),
.Y(n1428) );
OAI21X1TS U1036 ( .A0(n1666), .A1(n1127), .B0(n1081), .Y(n1082) );
OAI21X1TS U1037 ( .A0(n1274), .A1(n1641), .B0(n1273), .Y(n516) );
OAI21X1TS U1038 ( .A0(n1649), .A1(n1441), .B0(n1239), .Y(n512) );
NOR2X1TS U1039 ( .A(n1457), .B(n1461), .Y(n1455) );
AO22XLTS U1040 ( .A0(n1544), .A1(Data_X[9]), .B0(n1534), .B1(intDX_EWSW[9]),
.Y(n901) );
AO22XLTS U1041 ( .A0(n1536), .A1(Data_X[14]), .B0(n1547), .B1(intDX_EWSW[14]), .Y(n896) );
AOI222X1TS U1042 ( .A0(n1637), .A1(n1636), .B0(n936), .B1(Data_array_SWR[5]),
.C0(n1635), .C1(n1634), .Y(n1640) );
AO22XLTS U1043 ( .A0(n1546), .A1(Data_X[3]), .B0(n1534), .B1(intDX_EWSW[3]),
.Y(n907) );
AO22XLTS U1044 ( .A0(n1535), .A1(Data_X[11]), .B0(n1534), .B1(intDX_EWSW[11]), .Y(n899) );
NAND4BX1TS U1045 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1057), .C(n1258), .D(n1069), .Y(n1058) );
AO22XLTS U1046 ( .A0(n1535), .A1(Data_X[15]), .B0(n1547), .B1(intDX_EWSW[15]), .Y(n895) );
AO22XLTS U1047 ( .A0(n1544), .A1(add_subt), .B0(n1537), .B1(intAS), .Y(n878)
);
INVX3TS U1048 ( .A(n1569), .Y(n937) );
BUFX3TS U1049 ( .A(n1347), .Y(n1558) );
AOI222X1TS U1050 ( .A0(Data_array_SWR[21]), .A1(n942), .B0(
Data_array_SWR[17]), .B1(n1079), .C0(Data_array_SWR[25]), .C1(n1268),
.Y(n1140) );
INVX3TS U1051 ( .A(n1590), .Y(n1274) );
INVX3TS U1052 ( .A(n1590), .Y(n1441) );
AOI222X1TS U1053 ( .A0(intDY_EWSW[4]), .A1(n1652), .B0(n999), .B1(n998),
.C0(intDY_EWSW[5]), .C1(n1677), .Y(n1001) );
INVX3TS U1054 ( .A(n1631), .Y(n1638) );
AOI211X1TS U1055 ( .A0(intDY_EWSW[16]), .A1(n1681), .B0(n1017), .C0(n1199),
.Y(n1007) );
OAI21X1TS U1056 ( .A0(n1617), .A1(n1719), .B0(n1616), .Y(n1228) );
NAND2BX1TS U1057 ( .AN(n1090), .B(n1089), .Y(n1093) );
INVX3TS U1058 ( .A(n1626), .Y(n1518) );
INVX3TS U1059 ( .A(n1626), .Y(n1622) );
OAI211X2TS U1060 ( .A0(intDX_EWSW[20]), .A1(n1712), .B0(n1022), .C0(n1006),
.Y(n1017) );
NAND3X1TS U1061 ( .A(n1699), .B(n1029), .C(intDX_EWSW[26]), .Y(n1031) );
NOR2BX4TS U1062 ( .AN(Shift_amount_SHT1_EWR[0]), .B(n945), .Y(n1347) );
OR2X2TS U1063 ( .A(n945), .B(Shift_amount_SHT1_EWR[0]), .Y(n927) );
NOR2X4TS U1064 ( .A(shift_value_SHT2_EWR[4]), .B(n922), .Y(n1079) );
OAI211X2TS U1065 ( .A0(intDX_EWSW[12]), .A1(n1709), .B0(n985), .C0(n976),
.Y(n987) );
NAND3X1TS U1066 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1657), .C(
n1694), .Y(n1526) );
CLKINVX2TS U1067 ( .A(Shift_reg_FLAGS_7[3]), .Y(n1424) );
OR2X2TS U1068 ( .A(shift_value_SHT2_EWR[3]), .B(n1682), .Y(n922) );
NAND2BX1TS U1069 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1029) );
NAND2BX1TS U1070 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1030) );
NOR2X1TS U1071 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .Y(n1049)
);
OAI21X1TS U1072 ( .A0(intDX_EWSW[23]), .A1(n1715), .B0(intDX_EWSW[22]), .Y(
n1018) );
OAI21X1TS U1073 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1676), .B0(n1653), .Y(n1103) );
NAND2BX1TS U1074 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1023) );
NAND2BX1TS U1075 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1014) );
NAND2BX1TS U1076 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1006) );
NOR2X4TS U1077 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1092) );
AOI211X2TS U1078 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n947), .B0(n1558), .C0(
n1422), .Y(n1555) );
NOR2X4TS U1079 ( .A(n1042), .B(n1581), .Y(n1369) );
NAND2X1TS U1080 ( .A(n1696), .B(n1061), .Y(n1075) );
NAND2BXLTS U1081 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n978) );
AOI211X1TS U1082 ( .A0(intDY_EWSW[28]), .A1(n1716), .B0(n1036), .C0(n1034),
.Y(n1038) );
OAI21XLTS U1083 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1099), .B0(n1098), .Y(
n1100) );
AND4X1TS U1084 ( .A(n1248), .B(n1251), .C(exp_rslt_NRM2_EW1[4]), .D(n1072),
.Y(n1073) );
NOR3X1TS U1085 ( .A(Raw_mant_NRM_SWR[12]), .B(n1684), .C(n1087), .Y(n1149)
);
NAND2BXLTS U1086 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n976) );
NOR2XLTS U1087 ( .A(n1027), .B(intDY_EWSW[24]), .Y(n1028) );
NAND3X1TS U1088 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n923), .Y(n1133) );
CLKINVX6TS U1089 ( .A(n1563), .Y(n1551) );
INVX4TS U1090 ( .A(n1553), .Y(n1361) );
NAND2X1TS U1091 ( .A(n1697), .B(n1056), .Y(n1060) );
AOI31XLTS U1092 ( .A0(n1675), .A1(Raw_mant_NRM_SWR[11]), .A2(n1105), .B0(
n1102), .Y(n1096) );
NOR3X2TS U1093 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1154) );
NAND2X1TS U1094 ( .A(n1486), .B(n1488), .Y(n1457) );
AOI2BB2X1TS U1095 ( .B0(n1039), .B1(n1038), .A0N(n1037), .A1N(n1036), .Y(
n1040) );
INVX4TS U1096 ( .A(n1553), .Y(n1565) );
AOI222X1TS U1097 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1361), .B0(n961), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1558), .C1(DmP_mant_SHT1_SW[3]), .Y(n1368)
);
INVX2TS U1098 ( .A(n1785), .Y(n1443) );
OAI2BB1X2TS U1099 ( .A0N(n1078), .A1N(n1077), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1525) );
NOR2X1TS U1100 ( .A(n1070), .B(n1254), .Y(n1597) );
NOR2XLTS U1101 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1051)
);
INVX2TS U1102 ( .A(n1458), .Y(n1459) );
INVX2TS U1103 ( .A(n1503), .Y(n1496) );
NAND4XLTS U1104 ( .A(n1197), .B(n1196), .C(n1195), .D(n1194), .Y(n1225) );
NAND4XLTS U1105 ( .A(n1221), .B(n1220), .C(n1219), .D(n1218), .Y(n1222) );
NAND4XLTS U1106 ( .A(n1213), .B(n1212), .C(n1211), .D(n1210), .Y(n1223) );
BUFX3TS U1107 ( .A(n971), .Y(n1406) );
BUFX3TS U1108 ( .A(n971), .Y(n1393) );
CLKBUFX2TS U1109 ( .A(n971), .Y(n1325) );
AND2X4TS U1110 ( .A(n1595), .B(n1042), .Y(n971) );
AO22XLTS U1111 ( .A0(n1535), .A1(Data_X[10]), .B0(n1534), .B1(intDX_EWSW[10]), .Y(n900) );
AO22XLTS U1112 ( .A0(n1535), .A1(Data_X[22]), .B0(n1537), .B1(intDX_EWSW[22]), .Y(n888) );
AO22XLTS U1113 ( .A0(n1544), .A1(Data_X[20]), .B0(n1547), .B1(intDX_EWSW[20]), .Y(n890) );
AO22XLTS U1114 ( .A0(n1535), .A1(Data_X[12]), .B0(n1547), .B1(intDX_EWSW[12]), .Y(n898) );
AO22XLTS U1115 ( .A0(n1544), .A1(Data_X[31]), .B0(n1537), .B1(intDX_EWSW[31]), .Y(n879) );
AO22XLTS U1116 ( .A0(n1535), .A1(Data_X[19]), .B0(n1547), .B1(intDX_EWSW[19]), .Y(n891) );
AO22XLTS U1117 ( .A0(n1546), .A1(Data_X[18]), .B0(n1547), .B1(intDX_EWSW[18]), .Y(n892) );
AO22XLTS U1118 ( .A0(n1546), .A1(Data_X[2]), .B0(n1534), .B1(intDX_EWSW[2]),
.Y(n908) );
AO22XLTS U1119 ( .A0(n1535), .A1(Data_X[17]), .B0(n1547), .B1(intDX_EWSW[17]), .Y(n893) );
AO22XLTS U1120 ( .A0(n1544), .A1(Data_X[8]), .B0(n1534), .B1(intDX_EWSW[8]),
.Y(n902) );
AO22XLTS U1121 ( .A0(n1544), .A1(Data_X[21]), .B0(n1537), .B1(intDX_EWSW[21]), .Y(n889) );
AO22XLTS U1122 ( .A0(n1535), .A1(Data_X[13]), .B0(n1547), .B1(intDX_EWSW[13]), .Y(n897) );
AO22XLTS U1123 ( .A0(n1538), .A1(intDX_EWSW[30]), .B0(n1540), .B1(Data_X[30]), .Y(n880) );
AO22XLTS U1124 ( .A0(n1543), .A1(intDY_EWSW[19]), .B0(n1540), .B1(Data_Y[19]), .Y(n857) );
AO22XLTS U1125 ( .A0(n1538), .A1(intDY_EWSW[5]), .B0(n1541), .B1(Data_Y[5]),
.Y(n871) );
AO22XLTS U1126 ( .A0(n1538), .A1(intDY_EWSW[7]), .B0(n1541), .B1(Data_Y[7]),
.Y(n869) );
AO22XLTS U1127 ( .A0(n1538), .A1(intDY_EWSW[4]), .B0(n1540), .B1(Data_Y[4]),
.Y(n872) );
AO22XLTS U1128 ( .A0(n1538), .A1(intDX_EWSW[29]), .B0(n1540), .B1(Data_X[29]), .Y(n881) );
AO22XLTS U1129 ( .A0(n1538), .A1(intDY_EWSW[6]), .B0(n1541), .B1(Data_Y[6]),
.Y(n870) );
AO22XLTS U1130 ( .A0(n1539), .A1(intDY_EWSW[16]), .B0(n1542), .B1(Data_Y[16]), .Y(n860) );
AO22XLTS U1131 ( .A0(n1538), .A1(intDY_EWSW[2]), .B0(n1540), .B1(Data_Y[2]),
.Y(n874) );
AO22XLTS U1132 ( .A0(n1539), .A1(intDY_EWSW[9]), .B0(n1540), .B1(Data_Y[9]),
.Y(n867) );
AO22XLTS U1133 ( .A0(n1538), .A1(intDY_EWSW[0]), .B0(n1540), .B1(Data_Y[0]),
.Y(n876) );
AO22XLTS U1134 ( .A0(n1538), .A1(intDY_EWSW[1]), .B0(n1540), .B1(Data_Y[1]),
.Y(n875) );
AO22XLTS U1135 ( .A0(n1539), .A1(intDY_EWSW[10]), .B0(n1542), .B1(Data_Y[10]), .Y(n866) );
AO22XLTS U1136 ( .A0(n1546), .A1(Data_X[4]), .B0(n1534), .B1(intDX_EWSW[4]),
.Y(n906) );
AO22XLTS U1137 ( .A0(n1541), .A1(Data_X[5]), .B0(n1534), .B1(intDX_EWSW[5]),
.Y(n905) );
AO22XLTS U1138 ( .A0(n1541), .A1(Data_X[6]), .B0(n1534), .B1(intDX_EWSW[6]),
.Y(n904) );
AO22XLTS U1139 ( .A0(n1544), .A1(Data_X[7]), .B0(n1534), .B1(intDX_EWSW[7]),
.Y(n903) );
AO22XLTS U1140 ( .A0(n1535), .A1(Data_X[16]), .B0(n1547), .B1(intDX_EWSW[16]), .Y(n894) );
AO22XLTS U1141 ( .A0(n1543), .A1(intDY_EWSW[18]), .B0(n1540), .B1(Data_Y[18]), .Y(n858) );
AO22XLTS U1142 ( .A0(n1543), .A1(intDY_EWSW[20]), .B0(n1541), .B1(Data_Y[20]), .Y(n856) );
AO22XLTS U1143 ( .A0(n1543), .A1(intDY_EWSW[21]), .B0(n1548), .B1(Data_Y[21]), .Y(n855) );
AO22XLTS U1144 ( .A0(n1543), .A1(intDY_EWSW[22]), .B0(n1548), .B1(Data_Y[22]), .Y(n854) );
AO22XLTS U1145 ( .A0(n1538), .A1(intDY_EWSW[3]), .B0(n1540), .B1(Data_Y[3]),
.Y(n873) );
AO22XLTS U1146 ( .A0(n1539), .A1(intDY_EWSW[8]), .B0(n1541), .B1(Data_Y[8]),
.Y(n868) );
AO22XLTS U1147 ( .A0(n1539), .A1(intDY_EWSW[11]), .B0(n1542), .B1(Data_Y[11]), .Y(n865) );
AO22XLTS U1148 ( .A0(n1539), .A1(intDY_EWSW[15]), .B0(n1542), .B1(Data_Y[15]), .Y(n861) );
AO22XLTS U1149 ( .A0(n1539), .A1(intDY_EWSW[17]), .B0(n1542), .B1(Data_Y[17]), .Y(n859) );
AO22XLTS U1150 ( .A0(n1539), .A1(intDY_EWSW[12]), .B0(n1542), .B1(Data_Y[12]), .Y(n864) );
AO22XLTS U1151 ( .A0(n1539), .A1(intDY_EWSW[13]), .B0(n1542), .B1(Data_Y[13]), .Y(n863) );
AO22XLTS U1152 ( .A0(n1539), .A1(intDY_EWSW[14]), .B0(n1542), .B1(Data_Y[14]), .Y(n862) );
AO22XLTS U1153 ( .A0(n1537), .A1(intDX_EWSW[28]), .B0(n1541), .B1(Data_X[28]), .Y(n882) );
NAND2BXLTS U1154 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n995) );
NAND2BXLTS U1155 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n989) );
OAI2BB2XLTS U1156 ( .B0(n980), .B1(n987), .A0N(n979), .A1N(n988), .Y(n983)
);
OAI32X1TS U1157 ( .A0(n1003), .A1(n1002), .A2(n1001), .B0(n1000), .B1(n1002),
.Y(n1004) );
NOR2BX1TS U1158 ( .AN(n991), .B(n990), .Y(n1005) );
OAI211XLTS U1159 ( .A0(intDX_EWSW[8]), .A1(n1706), .B0(n989), .C0(n988), .Y(
n990) );
INVX2TS U1160 ( .A(n987), .Y(n991) );
AOI2BB1XLTS U1161 ( .A0N(n1097), .A1N(Raw_mant_NRM_SWR[23]), .B0(
Raw_mant_NRM_SWR[24]), .Y(n1099) );
INVX2TS U1162 ( .A(n1086), .Y(n1101) );
NOR2XLTS U1163 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1088) );
AO21X1TS U1164 ( .A0(n1101), .A1(Raw_mant_NRM_SWR[18]), .B0(n1149), .Y(n1102) );
OAI21X1TS U1165 ( .A0(n1010), .A1(n1009), .B0(n1008), .Y(n1026) );
NOR2BX1TS U1166 ( .AN(n1007), .B(n1012), .Y(n1008) );
NOR2BX1TS U1167 ( .AN(n1005), .B(n1004), .Y(n1009) );
INVX2TS U1168 ( .A(n986), .Y(n1010) );
AOI222X1TS U1169 ( .A0(Data_array_SWR[20]), .A1(n942), .B0(
Data_array_SWR[24]), .B1(n1268), .C0(Data_array_SWR[16]), .C1(n1079),
.Y(n1141) );
AO22XLTS U1170 ( .A0(Data_array_SWR[15]), .A1(n1080), .B0(Data_array_SWR[11]), .B1(n941), .Y(n1163) );
AOI2BB2XLTS U1171 ( .B0(intDX_EWSW[7]), .B1(n1693), .A0N(n1693), .A1N(
intDX_EWSW[7]), .Y(n1194) );
NAND4XLTS U1172 ( .A(n1205), .B(n1204), .C(n1203), .D(n1202), .Y(n1224) );
OAI21X1TS U1173 ( .A0(n1687), .A1(n1603), .B0(n1448), .Y(n1514) );
AO21XLTS U1174 ( .A0(n1447), .A1(n1446), .B0(n1445), .Y(n1448) );
OAI211XLTS U1175 ( .A0(intadd_33_B_2_), .A1(n1669), .B0(n1124), .C0(n1623),
.Y(n1126) );
INVX2TS U1176 ( .A(n1528), .Y(n1527) );
NAND2X1TS U1177 ( .A(n1679), .B(LZD_output_NRM2_EW[0]), .Y(
DP_OP_15J33_125_2314_n8) );
NAND2BXLTS U1178 ( .AN(n1430), .B(n949), .Y(n1431) );
AOI222X1TS U1179 ( .A0(n1266), .A1(n949), .B0(Data_array_SWR[8]), .B1(n934),
.C0(n1265), .C1(n1272), .Y(n1647) );
AOI222X1TS U1180 ( .A0(n1637), .A1(left_right_SHT2), .B0(Data_array_SWR[5]),
.B1(n934), .C0(n1635), .C1(n1272), .Y(n1641) );
NAND4XLTS U1181 ( .A(n1147), .B(n1152), .C(n1146), .D(n1145), .Y(n1148) );
OAI21XLTS U1182 ( .A0(n1154), .A1(n1153), .B0(n1152), .Y(n1159) );
INVX2TS U1183 ( .A(n1151), .Y(n1153) );
AO22XLTS U1184 ( .A0(n1591), .A1(DmP_EXP_EWSW[4]), .B0(n1592), .B1(
DmP_mant_SHT1_SW[4]), .Y(n649) );
MX2X1TS U1185 ( .A(n1437), .B(DmP_mant_SFG_SWR[23]), .S0(n1441), .Y(n513) );
MX2X1TS U1186 ( .A(n1438), .B(DmP_mant_SFG_SWR[22]), .S0(n1441), .Y(n514) );
MX2X1TS U1187 ( .A(n1439), .B(DmP_mant_SFG_SWR[19]), .S0(n1441), .Y(n517) );
MX2X1TS U1188 ( .A(n1440), .B(DmP_mant_SFG_SWR[18]), .S0(n1441), .Y(n518) );
MX2X1TS U1189 ( .A(n1442), .B(DmP_mant_SFG_SWR[16]), .S0(n1441), .Y(n520) );
MX2X1TS U1190 ( .A(n1425), .B(DmP_mant_SFG_SWR[15]), .S0(n1441), .Y(n521) );
MX2X1TS U1191 ( .A(n1643), .B(DmP_mant_SFG_SWR[10]), .S0(n1441), .Y(n537) );
MX2X1TS U1192 ( .A(n1435), .B(DmP_mant_SFG_SWR[11]), .S0(n1441), .Y(n576) );
AOI2BB2XLTS U1193 ( .B0(n1601), .B1(n1570), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1579), .Y(n814) );
AO22XLTS U1194 ( .A0(n1601), .A1(DmP_EXP_EWSW[17]), .B0(n1593), .B1(
DmP_mant_SHT1_SW[17]), .Y(n623) );
AO22XLTS U1195 ( .A0(n1601), .A1(DmP_EXP_EWSW[16]), .B0(n1593), .B1(
DmP_mant_SHT1_SW[16]), .Y(n625) );
AO22XLTS U1196 ( .A0(n1651), .A1(DmP_EXP_EWSW[7]), .B0(n1592), .B1(
DmP_mant_SHT1_SW[7]), .Y(n643) );
AO22XLTS U1197 ( .A0(n1601), .A1(DmP_EXP_EWSW[20]), .B0(n1598), .B1(
DmP_mant_SHT1_SW[20]), .Y(n617) );
AO22XLTS U1198 ( .A0(n1651), .A1(DmP_EXP_EWSW[13]), .B0(n1593), .B1(
DmP_mant_SHT1_SW[13]), .Y(n631) );
AO22XLTS U1199 ( .A0(n1651), .A1(DmP_EXP_EWSW[11]), .B0(n1593), .B1(
DmP_mant_SHT1_SW[11]), .Y(n635) );
AO22XLTS U1200 ( .A0(n1651), .A1(DmP_EXP_EWSW[9]), .B0(n1593), .B1(
DmP_mant_SHT1_SW[9]), .Y(n639) );
AO22XLTS U1201 ( .A0(n965), .A1(DmP_EXP_EWSW[6]), .B0(n1592), .B1(
DmP_mant_SHT1_SW[6]), .Y(n645) );
AO22XLTS U1202 ( .A0(n1591), .A1(DmP_EXP_EWSW[2]), .B0(n1592), .B1(
DmP_mant_SHT1_SW[2]), .Y(n653) );
AO22XLTS U1203 ( .A0(n1601), .A1(DmP_EXP_EWSW[21]), .B0(n1598), .B1(
DmP_mant_SHT1_SW[21]), .Y(n615) );
AO22XLTS U1204 ( .A0(n1591), .A1(DmP_EXP_EWSW[5]), .B0(n1592), .B1(
DmP_mant_SHT1_SW[5]), .Y(n647) );
AO22XLTS U1205 ( .A0(n1591), .A1(DmP_EXP_EWSW[0]), .B0(n1592), .B1(
DmP_mant_SHT1_SW[0]), .Y(n657) );
AO22XLTS U1206 ( .A0(n1651), .A1(DmP_EXP_EWSW[15]), .B0(n1593), .B1(
DmP_mant_SHT1_SW[15]), .Y(n627) );
AO22XLTS U1207 ( .A0(n1591), .A1(DmP_EXP_EWSW[1]), .B0(n1592), .B1(
DmP_mant_SHT1_SW[1]), .Y(n655) );
AO22XLTS U1208 ( .A0(n1651), .A1(DmP_EXP_EWSW[14]), .B0(n1593), .B1(
DmP_mant_SHT1_SW[14]), .Y(n629) );
AO22XLTS U1209 ( .A0(n1601), .A1(DmP_EXP_EWSW[19]), .B0(n1598), .B1(
DmP_mant_SHT1_SW[19]), .Y(n619) );
AO22XLTS U1210 ( .A0(n1601), .A1(DmP_EXP_EWSW[18]), .B0(n1593), .B1(
DmP_mant_SHT1_SW[18]), .Y(n621) );
AO22XLTS U1211 ( .A0(n1651), .A1(DmP_EXP_EWSW[12]), .B0(n1593), .B1(
DmP_mant_SHT1_SW[12]), .Y(n633) );
AO22XLTS U1212 ( .A0(n1651), .A1(DmP_EXP_EWSW[10]), .B0(n1593), .B1(
DmP_mant_SHT1_SW[10]), .Y(n637) );
AO22XLTS U1213 ( .A0(n1651), .A1(DmP_EXP_EWSW[8]), .B0(n1592), .B1(
DmP_mant_SHT1_SW[8]), .Y(n641) );
AO22XLTS U1214 ( .A0(n1591), .A1(DmP_EXP_EWSW[3]), .B0(n1592), .B1(
DmP_mant_SHT1_SW[3]), .Y(n651) );
MX2X1TS U1215 ( .A(DMP_SFG[7]), .B(DMP_SHT2_EWSW[7]), .S0(n1639), .Y(n744)
);
AOI2BB2XLTS U1216 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n939), .A0N(n1413), .A1N(
n950), .Y(n1306) );
AO22XLTS U1217 ( .A0(n1546), .A1(Data_X[1]), .B0(n1545), .B1(intDX_EWSW[1]),
.Y(n909) );
MX2X1TS U1218 ( .A(n1428), .B(DmP_mant_SFG_SWR[12]), .S0(n1638), .Y(n524) );
MX2X1TS U1219 ( .A(n1427), .B(DmP_mant_SFG_SWR[13]), .S0(n1638), .Y(n523) );
MX2X1TS U1220 ( .A(n1426), .B(DmP_mant_SFG_SWR[14]), .S0(n1638), .Y(n522) );
AO22XLTS U1221 ( .A0(n1548), .A1(Data_Y[31]), .B0(n1547), .B1(intDY_EWSW[31]), .Y(n845) );
AO22XLTS U1222 ( .A0(n1638), .A1(DMP_SFG[2]), .B0(n1613), .B1(
DMP_SHT2_EWSW[2]), .Y(n759) );
AO22XLTS U1223 ( .A0(n1589), .A1(DMP_SFG[3]), .B0(n1613), .B1(
DMP_SHT2_EWSW[3]), .Y(n756) );
MX2X1TS U1224 ( .A(n1429), .B(DmP_mant_SFG_SWR[9]), .S0(n1638), .Y(n545) );
AO22XLTS U1225 ( .A0(n1544), .A1(Data_Y[28]), .B0(n1545), .B1(intDY_EWSW[28]), .Y(n848) );
AO22XLTS U1226 ( .A0(n1589), .A1(DmP_mant_SFG_SWR[6]), .B0(n1436), .B1(n1165), .Y(n553) );
MX2X1TS U1227 ( .A(DMP_SFG[18]), .B(DMP_SHT2_EWSW[18]), .S0(n1639), .Y(n711)
);
MX2X1TS U1228 ( .A(DMP_SFG[20]), .B(DMP_SHT2_EWSW[20]), .S0(n1639), .Y(n705)
);
MX2X1TS U1229 ( .A(DMP_SFG[22]), .B(DMP_SHT2_EWSW[22]), .S0(n1590), .Y(n699)
);
MX2X1TS U1230 ( .A(DMP_SFG[19]), .B(DMP_SHT2_EWSW[19]), .S0(n1639), .Y(n708)
);
MX2X1TS U1231 ( .A(DMP_SFG[21]), .B(DMP_SHT2_EWSW[21]), .S0(n1436), .Y(n702)
);
MX2X1TS U1232 ( .A(DMP_SFG[10]), .B(DMP_SHT2_EWSW[10]), .S0(n1590), .Y(n735)
);
MX2X1TS U1233 ( .A(DMP_SFG[11]), .B(DMP_SHT2_EWSW[11]), .S0(n1590), .Y(n732)
);
MX2X1TS U1234 ( .A(DMP_SFG[12]), .B(DMP_SHT2_EWSW[12]), .S0(n1590), .Y(n729)
);
MX2X1TS U1235 ( .A(DMP_SFG[13]), .B(DMP_SHT2_EWSW[13]), .S0(n1590), .Y(n726)
);
MX2X1TS U1236 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n945),
.Y(n689) );
MX2X1TS U1237 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n1520),
.Y(n684) );
MX2X1TS U1238 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n945),
.Y(n679) );
MX2X1TS U1239 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n1520),
.Y(n674) );
AO22XLTS U1240 ( .A0(n1579), .A1(n1574), .B0(n1600), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n813) );
AO22XLTS U1241 ( .A0(n1608), .A1(DMP_SHT2_EWSW[5]), .B0(n1611), .B1(
DMP_SFG[5]), .Y(n750) );
AO22XLTS U1242 ( .A0(n1613), .A1(DMP_SHT2_EWSW[0]), .B0(n1589), .B1(
DMP_SFG[0]), .Y(n765) );
AO22XLTS U1243 ( .A0(n1601), .A1(DmP_EXP_EWSW[22]), .B0(n1598), .B1(
DmP_mant_SHT1_SW[22]), .Y(n613) );
MX2X1TS U1244 ( .A(DMP_SFG[16]), .B(DMP_SHT2_EWSW[16]), .S0(n1639), .Y(n717)
);
MX2X1TS U1245 ( .A(DMP_SFG[14]), .B(DMP_SHT2_EWSW[14]), .S0(n1639), .Y(n723)
);
MX2X1TS U1246 ( .A(DMP_SFG[6]), .B(DMP_SHT2_EWSW[6]), .S0(n1436), .Y(n747)
);
MX2X1TS U1247 ( .A(DMP_SFG[15]), .B(DMP_SHT2_EWSW[15]), .S0(n1639), .Y(n720)
);
MX2X1TS U1248 ( .A(DMP_SFG[17]), .B(DMP_SHT2_EWSW[17]), .S0(n1639), .Y(n714)
);
OAI211XLTS U1249 ( .A0(n1386), .A1(n954), .B0(n1382), .C0(n1381), .Y(n824)
);
MX2X1TS U1250 ( .A(DMP_SFG[8]), .B(DMP_SHT2_EWSW[8]), .S0(n1639), .Y(n741)
);
AOI2BB2XLTS U1251 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n940), .A0N(n1410), .A1N(
n951), .Y(n1411) );
AO22XLTS U1252 ( .A0(n1546), .A1(Data_X[0]), .B0(n1545), .B1(intDX_EWSW[0]),
.Y(n910) );
AOI2BB2XLTS U1253 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n939), .A0N(n1302), .A1N(
n950), .Y(n1298) );
AOI2BB2XLTS U1254 ( .B0(n1622), .B1(intadd_33_SUM_1_), .A0N(
Raw_mant_NRM_SWR[5]), .A1N(n1620), .Y(n556) );
AO22XLTS U1255 ( .A0(n1535), .A1(Data_X[27]), .B0(n1537), .B1(intDX_EWSW[27]), .Y(n883) );
AO22XLTS U1256 ( .A0(n1544), .A1(Data_X[23]), .B0(n1537), .B1(intDX_EWSW[23]), .Y(n887) );
MX2X1TS U1257 ( .A(DMP_SFG[9]), .B(DMP_SHT2_EWSW[9]), .S0(n1436), .Y(n738)
);
MX2X1TS U1258 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n1520),
.Y(n694) );
MX2X1TS U1259 ( .A(Raw_mant_NRM_SWR[25]), .B(n1484), .S0(n1628), .Y(n577) );
MX2X1TS U1260 ( .A(Raw_mant_NRM_SWR[20]), .B(n1469), .S0(n1628), .Y(n582) );
AOI2BB2XLTS U1261 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n940), .A0N(n1374), .A1N(
n952), .Y(n1375) );
OAI211XLTS U1262 ( .A0(n1360), .A1(n951), .B0(n1356), .C0(n1355), .Y(n826)
);
NAND2BXLTS U1263 ( .AN(n1624), .B(n1623), .Y(n1625) );
AO22XLTS U1264 ( .A0(n1543), .A1(intDY_EWSW[24]), .B0(n1536), .B1(Data_Y[24]), .Y(n852) );
AO22XLTS U1265 ( .A0(n1543), .A1(intDY_EWSW[27]), .B0(n1542), .B1(Data_Y[27]), .Y(n849) );
MX2X1TS U1266 ( .A(Raw_mant_NRM_SWR[10]), .B(intadd_34_SUM_2_), .S0(n1518),
.Y(n567) );
AO22XLTS U1267 ( .A0(n1544), .A1(Data_Y[29]), .B0(n1545), .B1(intDY_EWSW[29]), .Y(n847) );
AO22XLTS U1268 ( .A0(n1546), .A1(Data_Y[30]), .B0(n1545), .B1(intDY_EWSW[30]), .Y(n846) );
AO22XLTS U1269 ( .A0(n1638), .A1(DMP_SFG[4]), .B0(n1613), .B1(
DMP_SHT2_EWSW[4]), .Y(n753) );
AO22XLTS U1270 ( .A0(n1631), .A1(DMP_SHT2_EWSW[1]), .B0(n1589), .B1(
DMP_SFG[1]), .Y(n762) );
AOI2BB2XLTS U1271 ( .B0(beg_OP), .B1(n1657), .A0N(n1657), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1118) );
MX2X1TS U1272 ( .A(Raw_mant_NRM_SWR[12]), .B(n1516), .S0(n1518), .Y(n590) );
MX2X1TS U1273 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n945),
.Y(n669) );
MX2X1TS U1274 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n664) );
MX2X1TS U1275 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n945),
.Y(n659) );
MX2X1TS U1276 ( .A(n1443), .B(OP_FLAG_SHT2), .S0(n1436), .Y(n597) );
MX2X1TS U1277 ( .A(Raw_mant_NRM_SWR[8]), .B(intadd_34_SUM_0_), .S0(n1518),
.Y(n569) );
AO22XLTS U1278 ( .A0(n1543), .A1(intDY_EWSW[25]), .B0(n1548), .B1(Data_Y[25]), .Y(n851) );
AO22XLTS U1279 ( .A0(n1543), .A1(intDY_EWSW[26]), .B0(n1548), .B1(Data_Y[26]), .Y(n850) );
AO22XLTS U1280 ( .A0(n1543), .A1(intDY_EWSW[23]), .B0(n1548), .B1(Data_Y[23]), .Y(n853) );
AO22XLTS U1281 ( .A0(n1537), .A1(intDX_EWSW[25]), .B0(n1541), .B1(Data_X[25]), .Y(n885) );
AO22XLTS U1282 ( .A0(n1537), .A1(intDX_EWSW[26]), .B0(n1541), .B1(Data_X[26]), .Y(n884) );
AO22XLTS U1283 ( .A0(n1537), .A1(intDX_EWSW[24]), .B0(n1542), .B1(Data_X[24]), .Y(n886) );
MX2X1TS U1284 ( .A(Raw_mant_NRM_SWR[9]), .B(intadd_34_SUM_1_), .S0(n1518),
.Y(n568) );
MX2X1TS U1285 ( .A(Raw_mant_NRM_SWR[14]), .B(n1510), .S0(n1518), .Y(n588) );
NOR2XLTS U1286 ( .A(n1063), .B(SIGN_FLAG_SHT1SHT2), .Y(n1227) );
AO22XLTS U1287 ( .A0(n1644), .A1(n1437), .B0(final_result_ieee[21]), .B1(
n1257), .Y(n526) );
AO22XLTS U1288 ( .A0(n1644), .A1(n1440), .B0(final_result_ieee[16]), .B1(
n1646), .Y(n532) );
AO22XLTS U1289 ( .A0(n1644), .A1(n1164), .B0(final_result_ieee[5]), .B1(
n1646), .Y(n533) );
AO22XLTS U1290 ( .A0(n1644), .A1(n1425), .B0(final_result_ieee[13]), .B1(
n1642), .Y(n535) );
AO22XLTS U1291 ( .A0(n1644), .A1(n1426), .B0(final_result_ieee[12]), .B1(
n1642), .Y(n538) );
AO22XLTS U1292 ( .A0(n1644), .A1(n1429), .B0(final_result_ieee[7]), .B1(
n1642), .Y(n544) );
AO22XLTS U1293 ( .A0(n1644), .A1(n1428), .B0(final_result_ieee[10]), .B1(
n1642), .Y(n547) );
AO22XLTS U1294 ( .A0(n1644), .A1(n1439), .B0(final_result_ieee[17]), .B1(
n1257), .Y(n551) );
AO22XLTS U1295 ( .A0(n1644), .A1(n1165), .B0(final_result_ieee[4]), .B1(
n1257), .Y(n552) );
AO22XLTS U1296 ( .A0(n1170), .A1(n1169), .B0(final_result_ieee[30]), .B1(
n1254), .Y(n802) );
AO21XLTS U1297 ( .A0(underflow_flag), .A1(n1646), .B0(n1597), .Y(n607) );
AO22XLTS U1298 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1646), .B1(zero_flag), .Y(n600) );
AO22XLTS U1299 ( .A0(n1589), .A1(DmP_mant_SFG_SWR[7]), .B0(n1436), .B1(n1164), .Y(n534) );
AO22XLTS U1300 ( .A0(n1589), .A1(DmP_mant_SFG_SWR[3]), .B0(n1613), .B1(n1166), .Y(n558) );
AO21XLTS U1301 ( .A0(LZD_output_NRM2_EW[1]), .A1(n1531), .B0(n1524), .Y(n559) );
AO22XLTS U1302 ( .A0(n1613), .A1(n1612), .B0(n1611), .B1(DmP_mant_SFG_SWR[2]), .Y(n563) );
AO21XLTS U1303 ( .A0(LZD_output_NRM2_EW[4]), .A1(n947), .B0(n1521), .Y(n574)
);
MX2X1TS U1304 ( .A(Raw_mant_NRM_SWR[24]), .B(n1478), .S0(n1628), .Y(n578) );
MX2X1TS U1305 ( .A(Raw_mant_NRM_SWR[23]), .B(n1475), .S0(n1628), .Y(n579) );
MX2X1TS U1306 ( .A(Raw_mant_NRM_SWR[22]), .B(n1472), .S0(n1628), .Y(n580) );
MX2X1TS U1307 ( .A(Raw_mant_NRM_SWR[21]), .B(n1456), .S0(n1518), .Y(n581) );
MX2X1TS U1308 ( .A(Raw_mant_NRM_SWR[19]), .B(n1466), .S0(n1628), .Y(n583) );
MX2X1TS U1309 ( .A(Raw_mant_NRM_SWR[18]), .B(n1491), .S0(n1628), .Y(n584) );
MX2X1TS U1310 ( .A(Raw_mant_NRM_SWR[17]), .B(n1502), .S0(n1628), .Y(n585) );
MX2X1TS U1311 ( .A(Raw_mant_NRM_SWR[16]), .B(n1507), .S0(n1518), .Y(n586) );
MX2X1TS U1312 ( .A(Raw_mant_NRM_SWR[15]), .B(n1494), .S0(n1628), .Y(n587) );
MX2X1TS U1313 ( .A(Raw_mant_NRM_SWR[13]), .B(n1513), .S0(n1518), .Y(n589) );
AO22XLTS U1314 ( .A0(n1520), .A1(SIGN_FLAG_NRM), .B0(n947), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n592) );
AO22XLTS U1315 ( .A0(n1620), .A1(SIGN_FLAG_SFG), .B0(n1621), .B1(
SIGN_FLAG_NRM), .Y(n593) );
AO22XLTS U1316 ( .A0(n1613), .A1(SIGN_FLAG_SHT2), .B0(n1611), .B1(
SIGN_FLAG_SFG), .Y(n594) );
AO22XLTS U1317 ( .A0(n964), .A1(SIGN_FLAG_SHT1), .B0(n1786), .B1(
SIGN_FLAG_SHT2), .Y(n595) );
AO22XLTS U1318 ( .A0(n1579), .A1(SIGN_FLAG_EXP), .B0(n1602), .B1(
SIGN_FLAG_SHT1), .Y(n596) );
AO22XLTS U1319 ( .A0(busy), .A1(OP_FLAG_SHT1), .B0(OP_FLAG_SHT2), .B1(n932),
.Y(n1741) );
AO22XLTS U1320 ( .A0(n1601), .A1(OP_FLAG_EXP), .B0(n1600), .B1(OP_FLAG_SHT1),
.Y(n599) );
AO22XLTS U1321 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n1531),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n601) );
AO22XLTS U1322 ( .A0(n1622), .A1(ZERO_FLAG_SFG), .B0(n1599), .B1(
ZERO_FLAG_NRM), .Y(n602) );
AO22XLTS U1323 ( .A0(n1613), .A1(ZERO_FLAG_SHT2), .B0(n1611), .B1(
ZERO_FLAG_SFG), .Y(n603) );
AO22XLTS U1324 ( .A0(busy), .A1(ZERO_FLAG_SHT1), .B0(n1786), .B1(
ZERO_FLAG_SHT2), .Y(n604) );
AO22XLTS U1325 ( .A0(n1601), .A1(ZERO_FLAG_EXP), .B0(n1598), .B1(
ZERO_FLAG_SHT1), .Y(n605) );
OAI21XLTS U1326 ( .A0(n1717), .A1(n1346), .B0(n1324), .Y(n622) );
OAI21XLTS U1327 ( .A0(n1702), .A1(n1346), .B0(n1322), .Y(n624) );
OAI21XLTS U1328 ( .A0(n1711), .A1(n1346), .B0(n1336), .Y(n626) );
OAI21XLTS U1329 ( .A0(n1710), .A1(n1346), .B0(n1338), .Y(n630) );
OAI21XLTS U1330 ( .A0(n1686), .A1(n1346), .B0(n1339), .Y(n636) );
OAI21XLTS U1331 ( .A0(n1680), .A1(n1343), .B0(n1337), .Y(n638) );
OAI21XLTS U1332 ( .A0(n1693), .A1(n1343), .B0(n1335), .Y(n644) );
OAI21XLTS U1333 ( .A0(n1692), .A1(n1343), .B0(n1329), .Y(n646) );
OAI21XLTS U1334 ( .A0(n1658), .A1(n1343), .B0(n1328), .Y(n648) );
OAI21XLTS U1335 ( .A0(n1707), .A1(n1343), .B0(n1327), .Y(n654) );
AO22XLTS U1336 ( .A0(n1620), .A1(DMP_SFG[30]), .B0(n1621), .B1(
DMP_exp_NRM_EW[7]), .Y(n660) );
AO22XLTS U1337 ( .A0(n1613), .A1(DMP_SHT2_EWSW[30]), .B0(n1611), .B1(
DMP_SFG[30]), .Y(n661) );
AO22XLTS U1338 ( .A0(n964), .A1(DMP_SHT1_EWSW[30]), .B0(n1786), .B1(
DMP_SHT2_EWSW[30]), .Y(n662) );
AO22XLTS U1339 ( .A0(n1591), .A1(DMP_EXP_EWSW[30]), .B0(n1592), .B1(
DMP_SHT1_EWSW[30]), .Y(n663) );
AO22XLTS U1340 ( .A0(n1622), .A1(DMP_SFG[29]), .B0(n1621), .B1(
DMP_exp_NRM_EW[6]), .Y(n665) );
AO22XLTS U1341 ( .A0(n1613), .A1(DMP_SHT2_EWSW[29]), .B0(n1589), .B1(
DMP_SFG[29]), .Y(n666) );
AO22XLTS U1342 ( .A0(busy), .A1(DMP_SHT1_EWSW[29]), .B0(n1786), .B1(
DMP_SHT2_EWSW[29]), .Y(n667) );
AO22XLTS U1343 ( .A0(n1591), .A1(DMP_EXP_EWSW[29]), .B0(n1602), .B1(
DMP_SHT1_EWSW[29]), .Y(n668) );
AO22XLTS U1344 ( .A0(n1620), .A1(DMP_SFG[28]), .B0(n1621), .B1(
DMP_exp_NRM_EW[5]), .Y(n670) );
AO22XLTS U1345 ( .A0(n1590), .A1(DMP_SHT2_EWSW[28]), .B0(n1611), .B1(
DMP_SFG[28]), .Y(n671) );
AO22XLTS U1346 ( .A0(n964), .A1(DMP_SHT1_EWSW[28]), .B0(n932), .B1(
DMP_SHT2_EWSW[28]), .Y(n672) );
AO22XLTS U1347 ( .A0(n1591), .A1(DMP_EXP_EWSW[28]), .B0(n1602), .B1(
DMP_SHT1_EWSW[28]), .Y(n673) );
AO22XLTS U1348 ( .A0(n1622), .A1(DMP_SFG[27]), .B0(n1739), .B1(
DMP_exp_NRM_EW[4]), .Y(n675) );
AO22XLTS U1349 ( .A0(n1590), .A1(DMP_SHT2_EWSW[27]), .B0(n1589), .B1(
DMP_SFG[27]), .Y(n676) );
AO22XLTS U1350 ( .A0(n1588), .A1(DMP_SHT1_EWSW[27]), .B0(n1786), .B1(
DMP_SHT2_EWSW[27]), .Y(n677) );
AO22XLTS U1351 ( .A0(n1591), .A1(DMP_EXP_EWSW[27]), .B0(n1602), .B1(
DMP_SHT1_EWSW[27]), .Y(n678) );
AO22XLTS U1352 ( .A0(n1620), .A1(DMP_SFG[26]), .B0(n1621), .B1(
DMP_exp_NRM_EW[3]), .Y(n680) );
AO22XLTS U1353 ( .A0(n1590), .A1(DMP_SHT2_EWSW[26]), .B0(n1611), .B1(
DMP_SFG[26]), .Y(n681) );
AO22XLTS U1354 ( .A0(n1588), .A1(DMP_SHT1_EWSW[26]), .B0(n1786), .B1(
DMP_SHT2_EWSW[26]), .Y(n682) );
AO22XLTS U1355 ( .A0(n965), .A1(DMP_EXP_EWSW[26]), .B0(n1602), .B1(
DMP_SHT1_EWSW[26]), .Y(n683) );
AO22XLTS U1356 ( .A0(n1620), .A1(DMP_SFG[25]), .B0(n1621), .B1(
DMP_exp_NRM_EW[2]), .Y(n685) );
AO22XLTS U1357 ( .A0(n1608), .A1(DMP_SHT2_EWSW[25]), .B0(n1589), .B1(
DMP_SFG[25]), .Y(n686) );
AO22XLTS U1358 ( .A0(busy), .A1(DMP_SHT1_EWSW[25]), .B0(n1786), .B1(
DMP_SHT2_EWSW[25]), .Y(n687) );
AO22XLTS U1359 ( .A0(n965), .A1(DMP_EXP_EWSW[25]), .B0(n1602), .B1(
DMP_SHT1_EWSW[25]), .Y(n688) );
AO22XLTS U1360 ( .A0(n1620), .A1(DMP_SFG[24]), .B0(n1621), .B1(
DMP_exp_NRM_EW[1]), .Y(n690) );
AO22XLTS U1361 ( .A0(n1608), .A1(DMP_SHT2_EWSW[24]), .B0(n1611), .B1(
DMP_SFG[24]), .Y(n691) );
AO22XLTS U1362 ( .A0(n1588), .A1(DMP_SHT1_EWSW[24]), .B0(n1786), .B1(
DMP_SHT2_EWSW[24]), .Y(n692) );
AO22XLTS U1363 ( .A0(n965), .A1(DMP_EXP_EWSW[24]), .B0(n1602), .B1(
DMP_SHT1_EWSW[24]), .Y(n693) );
AO22XLTS U1364 ( .A0(n1622), .A1(DMP_SFG[23]), .B0(n1739), .B1(
DMP_exp_NRM_EW[0]), .Y(n695) );
AO22XLTS U1365 ( .A0(n1608), .A1(DMP_SHT2_EWSW[23]), .B0(n1589), .B1(
DMP_SFG[23]), .Y(n696) );
AO22XLTS U1366 ( .A0(n1588), .A1(DMP_SHT1_EWSW[23]), .B0(n1786), .B1(
DMP_SHT2_EWSW[23]), .Y(n697) );
AO22XLTS U1367 ( .A0(n965), .A1(DMP_EXP_EWSW[23]), .B0(n1602), .B1(
DMP_SHT1_EWSW[23]), .Y(n698) );
AO22XLTS U1368 ( .A0(n1588), .A1(DMP_SHT1_EWSW[22]), .B0(n1587), .B1(
DMP_SHT2_EWSW[22]), .Y(n700) );
AO22XLTS U1369 ( .A0(n965), .A1(DMP_EXP_EWSW[22]), .B0(n1602), .B1(
DMP_SHT1_EWSW[22]), .Y(n701) );
AO22XLTS U1370 ( .A0(n1588), .A1(DMP_SHT1_EWSW[21]), .B0(n1587), .B1(
DMP_SHT2_EWSW[21]), .Y(n703) );
AO22XLTS U1371 ( .A0(n965), .A1(DMP_EXP_EWSW[21]), .B0(n1602), .B1(
DMP_SHT1_EWSW[21]), .Y(n704) );
AO22XLTS U1372 ( .A0(n1588), .A1(DMP_SHT1_EWSW[20]), .B0(n1587), .B1(
DMP_SHT2_EWSW[20]), .Y(n706) );
AO22XLTS U1373 ( .A0(n965), .A1(DMP_EXP_EWSW[20]), .B0(n1586), .B1(
DMP_SHT1_EWSW[20]), .Y(n707) );
AO22XLTS U1374 ( .A0(n1588), .A1(DMP_SHT1_EWSW[19]), .B0(n1587), .B1(
DMP_SHT2_EWSW[19]), .Y(n709) );
AO22XLTS U1375 ( .A0(n965), .A1(DMP_EXP_EWSW[19]), .B0(n1586), .B1(
DMP_SHT1_EWSW[19]), .Y(n710) );
AO22XLTS U1376 ( .A0(n1588), .A1(DMP_SHT1_EWSW[18]), .B0(n1587), .B1(
DMP_SHT2_EWSW[18]), .Y(n712) );
AO22XLTS U1377 ( .A0(n965), .A1(DMP_EXP_EWSW[18]), .B0(n1586), .B1(
DMP_SHT1_EWSW[18]), .Y(n713) );
AO22XLTS U1378 ( .A0(n1588), .A1(DMP_SHT1_EWSW[17]), .B0(n1587), .B1(
DMP_SHT2_EWSW[17]), .Y(n715) );
AO22XLTS U1379 ( .A0(n1585), .A1(DMP_EXP_EWSW[17]), .B0(n1586), .B1(
DMP_SHT1_EWSW[17]), .Y(n716) );
AO22XLTS U1380 ( .A0(n964), .A1(DMP_SHT1_EWSW[16]), .B0(n1587), .B1(
DMP_SHT2_EWSW[16]), .Y(n718) );
AO22XLTS U1381 ( .A0(n1585), .A1(DMP_EXP_EWSW[16]), .B0(n1586), .B1(
DMP_SHT1_EWSW[16]), .Y(n719) );
AO22XLTS U1382 ( .A0(busy), .A1(DMP_SHT1_EWSW[15]), .B0(n1587), .B1(
DMP_SHT2_EWSW[15]), .Y(n721) );
AO22XLTS U1383 ( .A0(n1585), .A1(DMP_EXP_EWSW[15]), .B0(n1586), .B1(
DMP_SHT1_EWSW[15]), .Y(n722) );
AO22XLTS U1384 ( .A0(n964), .A1(DMP_SHT1_EWSW[14]), .B0(n1587), .B1(
DMP_SHT2_EWSW[14]), .Y(n724) );
AO22XLTS U1385 ( .A0(n1585), .A1(DMP_EXP_EWSW[14]), .B0(n1586), .B1(
DMP_SHT1_EWSW[14]), .Y(n725) );
AO22XLTS U1386 ( .A0(busy), .A1(DMP_SHT1_EWSW[13]), .B0(n1587), .B1(
DMP_SHT2_EWSW[13]), .Y(n727) );
AO22XLTS U1387 ( .A0(n1585), .A1(DMP_EXP_EWSW[13]), .B0(n1586), .B1(
DMP_SHT1_EWSW[13]), .Y(n728) );
AO22XLTS U1388 ( .A0(n964), .A1(DMP_SHT1_EWSW[12]), .B0(n1584), .B1(
DMP_SHT2_EWSW[12]), .Y(n730) );
AO22XLTS U1389 ( .A0(n1585), .A1(DMP_EXP_EWSW[12]), .B0(n1586), .B1(
DMP_SHT1_EWSW[12]), .Y(n731) );
AO22XLTS U1390 ( .A0(busy), .A1(DMP_SHT1_EWSW[11]), .B0(n1584), .B1(
DMP_SHT2_EWSW[11]), .Y(n733) );
AO22XLTS U1391 ( .A0(n1585), .A1(DMP_EXP_EWSW[11]), .B0(n1586), .B1(
DMP_SHT1_EWSW[11]), .Y(n734) );
AO22XLTS U1392 ( .A0(n964), .A1(DMP_SHT1_EWSW[10]), .B0(n1584), .B1(
DMP_SHT2_EWSW[10]), .Y(n736) );
AO22XLTS U1393 ( .A0(n1585), .A1(DMP_EXP_EWSW[10]), .B0(n1583), .B1(
DMP_SHT1_EWSW[10]), .Y(n737) );
AO22XLTS U1394 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n1584), .B1(
DMP_SHT2_EWSW[9]), .Y(n739) );
AO22XLTS U1395 ( .A0(n1585), .A1(DMP_EXP_EWSW[9]), .B0(n1583), .B1(
DMP_SHT1_EWSW[9]), .Y(n740) );
AO22XLTS U1396 ( .A0(n964), .A1(DMP_SHT1_EWSW[8]), .B0(n1584), .B1(
DMP_SHT2_EWSW[8]), .Y(n742) );
AO22XLTS U1397 ( .A0(n1585), .A1(DMP_EXP_EWSW[8]), .B0(n1583), .B1(
DMP_SHT1_EWSW[8]), .Y(n743) );
AO22XLTS U1398 ( .A0(n964), .A1(DMP_SHT1_EWSW[7]), .B0(DMP_SHT2_EWSW[7]),
.B1(n932), .Y(n1742) );
AO22XLTS U1399 ( .A0(n1582), .A1(DMP_EXP_EWSW[7]), .B0(n1583), .B1(
DMP_SHT1_EWSW[7]), .Y(n746) );
AO22XLTS U1400 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(DMP_SHT2_EWSW[6]),
.B1(n932), .Y(n1743) );
AO22XLTS U1401 ( .A0(n1582), .A1(DMP_EXP_EWSW[6]), .B0(n1583), .B1(
DMP_SHT1_EWSW[6]), .Y(n749) );
AO22XLTS U1402 ( .A0(n930), .A1(DMP_SHT1_EWSW[5]), .B0(n1584), .B1(
DMP_SHT2_EWSW[5]), .Y(n751) );
AO22XLTS U1403 ( .A0(n1582), .A1(DMP_EXP_EWSW[5]), .B0(n1583), .B1(
DMP_SHT1_EWSW[5]), .Y(n752) );
AO22XLTS U1404 ( .A0(n930), .A1(DMP_SHT1_EWSW[4]), .B0(n1584), .B1(
DMP_SHT2_EWSW[4]), .Y(n754) );
AO22XLTS U1405 ( .A0(n1582), .A1(DMP_EXP_EWSW[4]), .B0(n1583), .B1(
DMP_SHT1_EWSW[4]), .Y(n755) );
AO22XLTS U1406 ( .A0(n930), .A1(DMP_SHT1_EWSW[3]), .B0(n1584), .B1(
DMP_SHT2_EWSW[3]), .Y(n757) );
AO22XLTS U1407 ( .A0(n1582), .A1(DMP_EXP_EWSW[3]), .B0(n1583), .B1(
DMP_SHT1_EWSW[3]), .Y(n758) );
AO22XLTS U1408 ( .A0(n930), .A1(DMP_SHT1_EWSW[2]), .B0(n1584), .B1(
DMP_SHT2_EWSW[2]), .Y(n760) );
AO22XLTS U1409 ( .A0(n1582), .A1(DMP_EXP_EWSW[2]), .B0(n1583), .B1(
DMP_SHT1_EWSW[2]), .Y(n761) );
AO22XLTS U1410 ( .A0(n930), .A1(DMP_SHT1_EWSW[1]), .B0(n1584), .B1(
DMP_SHT2_EWSW[1]), .Y(n763) );
AO22XLTS U1411 ( .A0(n1582), .A1(DMP_EXP_EWSW[1]), .B0(n1583), .B1(
DMP_SHT1_EWSW[1]), .Y(n764) );
AO22XLTS U1412 ( .A0(n930), .A1(DMP_SHT1_EWSW[0]), .B0(n932), .B1(
DMP_SHT2_EWSW[0]), .Y(n766) );
AO22XLTS U1413 ( .A0(n1582), .A1(DMP_EXP_EWSW[0]), .B0(n1737), .B1(
DMP_SHT1_EWSW[0]), .Y(n767) );
AO22XLTS U1414 ( .A0(n1420), .A1(n1580), .B0(ZERO_FLAG_EXP), .B1(n1581), .Y(
n769) );
AO21XLTS U1415 ( .A0(OP_FLAG_EXP), .A1(n1581), .B0(n1580), .Y(n770) );
OAI21X1TS U1416 ( .A0(n1661), .A1(n1408), .B0(n1044), .Y(n786) );
OAI21X1TS U1417 ( .A0(n1704), .A1(n1408), .B0(n1043), .Y(n788) );
AO22XLTS U1418 ( .A0(n1582), .A1(n1190), .B0(n1737), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n810) );
AO22XLTS U1419 ( .A0(n1582), .A1(n1185), .B0(n1737), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n811) );
AO22XLTS U1420 ( .A0(n1579), .A1(n1578), .B0(n1737), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n812) );
OAI21XLTS U1421 ( .A0(n930), .A1(n1636), .B0(n921), .Y(n877) );
AO22XLTS U1422 ( .A0(n1532), .A1(n930), .B0(n1530), .B1(Shift_reg_FLAGS_7[3]), .Y(n914) );
AO22XLTS U1423 ( .A0(n1530), .A1(n1595), .B0(n1532), .B1(n1533), .Y(n917) );
INVX2TS U1424 ( .A(n949), .Y(n1636) );
AND2X2TS U1425 ( .A(n1277), .B(n938), .Y(n926) );
BUFX3TS U1426 ( .A(n1398), .Y(n1371) );
INVX2TS U1427 ( .A(n1079), .Y(n943) );
BUFX3TS U1428 ( .A(n1080), .Y(n1268) );
CLKBUFX2TS U1429 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1520) );
CLKINVX3TS U1430 ( .A(rst), .Y(n1178) );
INVX2TS U1431 ( .A(n1786), .Y(n930) );
INVX2TS U1432 ( .A(n930), .Y(n931) );
INVX2TS U1433 ( .A(n930), .Y(n932) );
INVX2TS U1434 ( .A(n1173), .Y(n933) );
INVX2TS U1435 ( .A(n1173), .Y(n934) );
INVX2TS U1436 ( .A(n1171), .Y(n935) );
INVX2TS U1437 ( .A(n1171), .Y(n936) );
INVX2TS U1438 ( .A(n937), .Y(n938) );
INVX2TS U1439 ( .A(n1127), .Y(n941) );
INVX2TS U1440 ( .A(n1127), .Y(n942) );
INVX2TS U1441 ( .A(n943), .Y(n944) );
INVX2TS U1442 ( .A(n1636), .Y(n946) );
INVX2TS U1443 ( .A(Shift_reg_FLAGS_7[1]), .Y(n947) );
INVX2TS U1444 ( .A(left_right_SHT2), .Y(n948) );
INVX2TS U1445 ( .A(n948), .Y(n949) );
INVX2TS U1446 ( .A(n1380), .Y(n950) );
INVX2TS U1447 ( .A(n1380), .Y(n951) );
INVX2TS U1448 ( .A(n1380), .Y(n952) );
INVX2TS U1449 ( .A(n926), .Y(n953) );
INVX2TS U1450 ( .A(n926), .Y(n954) );
INVX2TS U1451 ( .A(n926), .Y(n955) );
OAI211XLTS U1452 ( .A0(n1067), .A1(n1723), .B0(n1256), .C0(n1066), .Y(n809)
);
NOR2XLTS U1453 ( .A(n1720), .B(n1784), .Y(n1119) );
BUFX3TS U1454 ( .A(n1178), .Y(n1183) );
BUFX3TS U1455 ( .A(n1178), .Y(n1179) );
CLKBUFX3TS U1456 ( .A(n1178), .Y(n1180) );
NOR3X1TS U1457 ( .A(n1716), .B(n1034), .C(intDY_EWSW[28]), .Y(n1035) );
AOI221X1TS U1458 ( .A0(n1713), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n1716), .C0(n1192), .Y(n1196) );
INVX2TS U1459 ( .A(n1409), .Y(n956) );
INVX2TS U1460 ( .A(n956), .Y(n957) );
AOI222X1TS U1461 ( .A0(n1630), .A1(left_right_SHT2), .B0(Data_array_SWR[4]),
.B1(n934), .C0(n1629), .C1(n1272), .Y(n1633) );
OAI22X2TS U1462 ( .A0(n1718), .A1(n1262), .B0(n1659), .B1(n922), .Y(n1629)
);
AOI222X4TS U1463 ( .A0(Data_array_SWR[21]), .A1(n958), .B0(
Data_array_SWR[17]), .B1(n1259), .C0(Data_array_SWR[25]), .C1(n1235),
.Y(n1264) );
NOR2X4TS U1464 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1259) );
INVX2TS U1465 ( .A(n922), .Y(n958) );
AOI222X2TS U1466 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1361), .B0(n963), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1550), .C1(DmP_mant_SHT1_SW[18]), .Y(n1413) );
AOI222X4TS U1467 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1361), .B0(n961), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1550), .C1(DmP_mant_SHT1_SW[17]), .Y(n1288) );
AOI222X1TS U1468 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1361), .B0(n962), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1550), .C1(DmP_mant_SHT1_SW[16]), .Y(n1308) );
AOI222X4TS U1469 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1361), .B0(n962), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1550), .C1(DmP_mant_SHT1_SW[7]), .Y(n1350)
);
AOI222X2TS U1470 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1421), .B0(
DmP_mant_SHT1_SW[20]), .B1(n1558), .C0(n963), .C1(DmP_mant_SHT1_SW[19]), .Y(n1410) );
AOI222X2TS U1471 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1361), .B0(n961), .B1(
DmP_mant_SHT1_SW[13]), .C0(n1550), .C1(DmP_mant_SHT1_SW[14]), .Y(n1302) );
AOI222X1TS U1472 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1361), .B0(n962), .B1(
DmP_mant_SHT1_SW[11]), .C0(n1550), .C1(DmP_mant_SHT1_SW[12]), .Y(n1303) );
AOI222X1TS U1473 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n1361), .B0(n961), .B1(
DmP_mant_SHT1_SW[9]), .C0(n1550), .C1(DmP_mant_SHT1_SW[10]), .Y(n1357)
);
AOI222X2TS U1474 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1421), .B0(n963), .B1(
DmP_mant_SHT1_SW[21]), .C0(n1558), .C1(DmP_mant_SHT1_SW[22]), .Y(n1374) );
INVX4TS U1475 ( .A(n1626), .Y(n1628) );
BUFX3TS U1476 ( .A(n1737), .Y(n1598) );
INVX2TS U1477 ( .A(n938), .Y(n959) );
OAI211XLTS U1478 ( .A0(n1308), .A1(n954), .B0(n1307), .C0(n1306), .Y(n836)
);
AOI221X1TS U1479 ( .A0(n1680), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]),
.B1(n1686), .C0(n1207), .Y(n1212) );
AOI221X1TS U1480 ( .A0(n1662), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1715), .C0(n1201), .Y(n1202) );
AOI221X1TS U1481 ( .A0(n1710), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1661), .C0(n1209), .Y(n1210) );
AOI221X1TS U1482 ( .A0(n1712), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1705), .C0(n1200), .Y(n1203) );
AOI221X1TS U1483 ( .A0(n1709), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1704), .C0(n1208), .Y(n1211) );
OAI2BB2XLTS U1484 ( .B0(intDY_EWSW[0]), .B1(n994), .A0N(intDX_EWSW[1]),
.A1N(n1787), .Y(n996) );
AOI221X1TS U1485 ( .A0(n1787), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n1702), .C0(n1198), .Y(n1205) );
NOR2X4TS U1486 ( .A(n1063), .B(n1525), .Y(n1644) );
OAI21XLTS U1487 ( .A0(DmP_EXP_EWSW[25]), .A1(n966), .B0(n1575), .Y(n1576) );
OAI221X4TS U1488 ( .A0(left_right_SHT2), .A1(n1140), .B0(n924), .B1(n1141),
.C0(n1138), .Y(n1427) );
OAI211XLTS U1489 ( .A0(n1368), .A1(n952), .B0(n1364), .C0(n1363), .Y(n821)
);
NOR4X2TS U1490 ( .A(n1225), .B(n1224), .C(n1223), .D(n1222), .Y(n1420) );
NOR2X2TS U1491 ( .A(n967), .B(DMP_EXP_EWSW[23]), .Y(n1573) );
AOI21X2TS U1492 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n947), .B0(n1524), .Y(
n1277) );
NAND2X2TS U1493 ( .A(n923), .B(n1235), .Y(n1127) );
NOR2X2TS U1494 ( .A(shift_value_SHT2_EWR[2]), .B(n1683), .Y(n1235) );
XNOR2X2TS U1495 ( .A(DMP_exp_NRM2_EW[0]), .B(n970), .Y(n1071) );
BUFX3TS U1496 ( .A(n1178), .Y(n1181) );
OAI21XLTS U1497 ( .A0(n1614), .A1(DMP_SFG[0]), .B0(n1617), .Y(n1615) );
OR2X1TS U1498 ( .A(n1451), .B(DMP_SFG[16]), .Y(n1488) );
OAI21XLTS U1499 ( .A0(n1414), .A1(intDX_EWSW[31]), .B0(n1595), .Y(n1226) );
INVX2TS U1500 ( .A(n927), .Y(n961) );
INVX2TS U1501 ( .A(n927), .Y(n962) );
INVX2TS U1502 ( .A(n927), .Y(n963) );
AOI22X2TS U1503 ( .A0(Data_array_SWR[22]), .A1(n958), .B0(Data_array_SWR[18]), .B1(n1259), .Y(n1131) );
AOI222X4TS U1504 ( .A0(Data_array_SWR[22]), .A1(n1268), .B0(
Data_array_SWR[14]), .B1(n1079), .C0(Data_array_SWR[18]), .C1(n942),
.Y(n1434) );
AOI222X4TS U1505 ( .A0(Data_array_SWR[23]), .A1(n1268), .B0(
Data_array_SWR[19]), .B1(n942), .C0(Data_array_SWR[15]), .C1(n1079),
.Y(n1177) );
AOI22X2TS U1506 ( .A0(Data_array_SWR[23]), .A1(n958), .B0(Data_array_SWR[19]), .B1(n1259), .Y(n1161) );
AOI221X1TS U1507 ( .A0(n1717), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1664), .C0(n1199), .Y(n1204) );
AOI32X1TS U1508 ( .A0(n1717), .A1(n1014), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1664), .Y(n1015) );
OAI21X2TS U1509 ( .A0(intDX_EWSW[18]), .A1(n1717), .B0(n1014), .Y(n1199) );
OAI211XLTS U1510 ( .A0(n1303), .A1(n955), .B0(n1299), .C0(n1298), .Y(n832)
);
INVX2TS U1511 ( .A(n932), .Y(n964) );
AOI31XLTS U1512 ( .A0(n964), .A1(Shift_amount_SHT1_EWR[4]), .A2(n947), .B0(
n1521), .Y(n1055) );
NOR3X6TS U1513 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .C(n1111),
.Y(n1104) );
NOR2XLTS U1514 ( .A(n1686), .B(intDX_EWSW[11]), .Y(n974) );
BUFX3TS U1515 ( .A(n1651), .Y(n965) );
NOR2X4TS U1516 ( .A(n1262), .B(shift_value_SHT2_EWR[4]), .Y(n1236) );
OAI21XLTS U1517 ( .A0(intDX_EWSW[21]), .A1(n1705), .B0(intDX_EWSW[20]), .Y(
n1011) );
OAI21XLTS U1518 ( .A0(intDX_EWSW[13]), .A1(n1704), .B0(intDX_EWSW[12]), .Y(
n973) );
OA22X1TS U1519 ( .A0(n1710), .A1(intDX_EWSW[14]), .B0(n1661), .B1(
intDX_EWSW[15]), .Y(n985) );
OAI21XLTS U1520 ( .A0(intDX_EWSW[15]), .A1(n1661), .B0(intDX_EWSW[14]), .Y(
n981) );
OA22X1TS U1521 ( .A0(n1662), .A1(intDX_EWSW[22]), .B0(n1715), .B1(
intDX_EWSW[23]), .Y(n1022) );
INVX2TS U1522 ( .A(n1063), .Y(n1070) );
OAI21XLTS U1523 ( .A0(intDX_EWSW[1]), .A1(n1787), .B0(intDX_EWSW[0]), .Y(
n994) );
OAI21XLTS U1524 ( .A0(intDX_EWSW[3]), .A1(n1701), .B0(intDX_EWSW[2]), .Y(
n997) );
NOR2XLTS U1525 ( .A(n1012), .B(intDY_EWSW[16]), .Y(n1013) );
NOR2XLTS U1526 ( .A(intadd_33_B_1_), .B(n925), .Y(n1122) );
NOR2XLTS U1527 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1089) );
OAI211XLTS U1528 ( .A0(intadd_34_B_1_), .A1(DMP_SFG[7]), .B0(intadd_34_CI),
.C0(DMP_SFG[6]), .Y(n1447) );
NAND2X1TS U1529 ( .A(n1169), .B(n1073), .Y(n1074) );
INVX2TS U1530 ( .A(n1597), .Y(n1256) );
NOR2X1TS U1531 ( .A(n1278), .B(n947), .Y(n1524) );
INVX2TS U1532 ( .A(Shift_reg_FLAGS_7[2]), .Y(n1599) );
BUFX3TS U1533 ( .A(n1536), .Y(n1546) );
OAI2BB2XLTS U1534 ( .B0(intDY_EWSW[12]), .B1(n973), .A0N(intDX_EWSW[13]),
.A1N(n1704), .Y(n984) );
NOR2X1TS U1535 ( .A(n974), .B(intDY_EWSW[10]), .Y(n975) );
AOI22X1TS U1536 ( .A0(intDX_EWSW[11]), .A1(n1686), .B0(intDX_EWSW[10]), .B1(
n975), .Y(n980) );
NAND3X1TS U1537 ( .A(n1706), .B(n989), .C(intDX_EWSW[8]), .Y(n977) );
AOI21X1TS U1538 ( .A0(n978), .A1(n977), .B0(n987), .Y(n979) );
OAI22X1TS U1539 ( .A0(n1680), .A1(intDX_EWSW[10]), .B0(n1686), .B1(
intDX_EWSW[11]), .Y(n1207) );
INVX2TS U1540 ( .A(n1207), .Y(n988) );
OAI2BB2XLTS U1541 ( .B0(intDY_EWSW[14]), .B1(n981), .A0N(intDX_EWSW[15]),
.A1N(n1661), .Y(n982) );
AOI211X1TS U1542 ( .A0(n985), .A1(n984), .B0(n983), .C0(n982), .Y(n986) );
OAI2BB1X1TS U1543 ( .A0N(n1677), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n992) );
OAI22X1TS U1544 ( .A0(intDY_EWSW[4]), .A1(n992), .B0(n1677), .B1(
intDY_EWSW[5]), .Y(n1003) );
OAI2BB1X1TS U1545 ( .A0N(n1678), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n993) );
OAI22X1TS U1546 ( .A0(intDY_EWSW[6]), .A1(n993), .B0(n1678), .B1(
intDY_EWSW[7]), .Y(n1002) );
OAI211X1TS U1547 ( .A0(n1701), .A1(intDX_EWSW[3]), .B0(n996), .C0(n995), .Y(
n999) );
AOI2BB2X1TS U1548 ( .B0(intDX_EWSW[3]), .B1(n1701), .A0N(intDY_EWSW[2]),
.A1N(n997), .Y(n998) );
AOI22X1TS U1549 ( .A0(intDY_EWSW[7]), .A1(n1678), .B0(intDY_EWSW[6]), .B1(
n1655), .Y(n1000) );
NOR2X1TS U1550 ( .A(n1702), .B(intDX_EWSW[17]), .Y(n1012) );
OAI2BB2XLTS U1551 ( .B0(intDY_EWSW[20]), .B1(n1011), .A0N(intDX_EWSW[21]),
.A1N(n1705), .Y(n1021) );
AOI22X1TS U1552 ( .A0(intDX_EWSW[17]), .A1(n1702), .B0(intDX_EWSW[16]), .B1(
n1013), .Y(n1016) );
OAI32X1TS U1553 ( .A0(n1199), .A1(n1017), .A2(n1016), .B0(n1015), .B1(n1017),
.Y(n1020) );
OAI2BB2XLTS U1554 ( .B0(intDY_EWSW[22]), .B1(n1018), .A0N(intDX_EWSW[23]),
.A1N(n1715), .Y(n1019) );
AOI211X1TS U1555 ( .A0(n1022), .A1(n1021), .B0(n1020), .C0(n1019), .Y(n1025)
);
OAI21X1TS U1556 ( .A0(intDX_EWSW[26]), .A1(n1699), .B0(n1029), .Y(n1032) );
NOR2X1TS U1557 ( .A(n1700), .B(intDX_EWSW[25]), .Y(n1027) );
NOR2X1TS U1558 ( .A(n1656), .B(intDX_EWSW[30]), .Y(n1036) );
NOR2X1TS U1559 ( .A(n1685), .B(intDX_EWSW[29]), .Y(n1034) );
NAND4BBX1TS U1560 ( .AN(n1032), .BN(n1027), .C(n1038), .D(n1023), .Y(n1024)
);
AOI22X1TS U1561 ( .A0(intDX_EWSW[25]), .A1(n1700), .B0(intDX_EWSW[24]), .B1(
n1028), .Y(n1033) );
OAI211X1TS U1562 ( .A0(n1033), .A1(n1032), .B0(n1031), .C0(n1030), .Y(n1039)
);
AOI221X1TS U1563 ( .A0(intDX_EWSW[30]), .A1(n1656), .B0(intDX_EWSW[29]),
.B1(n1685), .C0(n1035), .Y(n1037) );
BUFX3TS U1564 ( .A(n1323), .Y(n1581) );
CLKBUFX2TS U1565 ( .A(n1323), .Y(n1315) );
BUFX3TS U1566 ( .A(n1315), .Y(n1392) );
AOI22X1TS U1567 ( .A0(intDX_EWSW[13]), .A1(n1393), .B0(DMP_EXP_EWSW[13]),
.B1(n1392), .Y(n1043) );
AOI22X1TS U1568 ( .A0(intDX_EWSW[15]), .A1(n1393), .B0(DMP_EXP_EWSW[15]),
.B1(n1392), .Y(n1044) );
XNOR2X2TS U1569 ( .A(n1784), .B(DmP_mant_SFG_SWR[6]), .Y(intadd_33_B_2_) );
NAND2X4TS U1570 ( .A(n947), .B(n931), .Y(n1569) );
OR2X4TS U1571 ( .A(Raw_mant_NRM_SWR[25]), .B(Raw_mant_NRM_SWR[24]), .Y(n1091) );
INVX2TS U1572 ( .A(n1092), .Y(n1045) );
NOR2X4TS U1573 ( .A(n1091), .B(n1045), .Y(n1151) );
NAND2X4TS U1574 ( .A(n1154), .B(n1151), .Y(n1086) );
NOR2X6TS U1575 ( .A(Raw_mant_NRM_SWR[18]), .B(n1086), .Y(n1143) );
NOR3X2TS U1576 ( .A(Raw_mant_NRM_SWR[15]), .B(Raw_mant_NRM_SWR[17]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1144) );
AND2X8TS U1577 ( .A(n1143), .B(n1144), .Y(n1142) );
NOR2X8TS U1578 ( .A(Raw_mant_NRM_SWR[13]), .B(n1046), .Y(n1105) );
NOR2X6TS U1579 ( .A(Raw_mant_NRM_SWR[10]), .B(n1087), .Y(n1108) );
NAND2X6TS U1580 ( .A(n1108), .B(n1675), .Y(n1050) );
NOR3X6TS U1581 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1050),
.Y(n1047) );
NAND2X6TS U1582 ( .A(n1047), .B(n1674), .Y(n1111) );
NAND2X4TS U1583 ( .A(n1104), .B(n1653), .Y(n1155) );
OAI21X1TS U1584 ( .A0(Raw_mant_NRM_SWR[7]), .A1(Raw_mant_NRM_SWR[6]), .B0(
n1047), .Y(n1048) );
OAI21X2TS U1585 ( .A0(n1049), .A1(n1155), .B0(n1048), .Y(n1095) );
NAND2BX1TS U1586 ( .AN(n1111), .B(Raw_mant_NRM_SWR[5]), .Y(n1156) );
OAI21XLTS U1587 ( .A0(n1051), .A1(n1050), .B0(n1156), .Y(n1052) );
AOI211X1TS U1588 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1104), .B0(n1095), .C0(
n1052), .Y(n1054) );
NOR3X4TS U1589 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .C(n1155),
.Y(n1053) );
NAND2X4TS U1590 ( .A(n1053), .B(Raw_mant_NRM_SWR[0]), .Y(n1107) );
NAND2X1TS U1591 ( .A(Raw_mant_NRM_SWR[1]), .B(n1053), .Y(n1146) );
AOI31X1TS U1592 ( .A0(n1054), .A1(n1107), .A2(n1146), .B0(n1531), .Y(n1521)
);
INVX2TS U1593 ( .A(exp_rslt_NRM2_EW1[1]), .Y(n1065) );
INVX2TS U1594 ( .A(DP_OP_15J33_125_2314_n4), .Y(n1056) );
XNOR2X2TS U1595 ( .A(DMP_exp_NRM2_EW[6]), .B(n1060), .Y(n1248) );
INVX2TS U1596 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1258) );
INVX2TS U1597 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1069) );
XNOR2X2TS U1598 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J33_125_2314_n4), .Y(
n1251) );
INVX2TS U1599 ( .A(n1060), .Y(n1061) );
XNOR2X2TS U1600 ( .A(DMP_exp_NRM2_EW[7]), .B(n1075), .Y(n1169) );
NOR2X2TS U1601 ( .A(n1062), .B(n1169), .Y(n1063) );
BUFX3TS U1602 ( .A(n1723), .Y(n1254) );
NAND2X1TS U1603 ( .A(n1254), .B(final_result_ieee[24]), .Y(n1064) );
INVX2TS U1604 ( .A(n1071), .Y(n1067) );
NAND2X1TS U1605 ( .A(n1254), .B(final_result_ieee[23]), .Y(n1066) );
NAND2X1TS U1606 ( .A(n1254), .B(final_result_ieee[25]), .Y(n1068) );
AND4X1TS U1607 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
n1071), .D(exp_rslt_NRM2_EW1[1]), .Y(n1072) );
INVX2TS U1608 ( .A(n1074), .Y(n1078) );
INVX2TS U1609 ( .A(n1075), .Y(n1076) );
INVX2TS U1610 ( .A(n1259), .Y(n1262) );
NAND2X2TS U1611 ( .A(n949), .B(n1236), .Y(n1173) );
NOR2X2TS U1612 ( .A(shift_value_SHT2_EWR[4]), .B(n949), .Y(n1272) );
INVX2TS U1613 ( .A(n1272), .Y(n1168) );
NOR2X2TS U1614 ( .A(n923), .B(n1262), .Y(n1240) );
INVX2TS U1615 ( .A(n1133), .Y(n1080) );
AOI22X1TS U1616 ( .A0(Data_array_SWR[10]), .A1(n944), .B0(Data_array_SWR[18]), .B1(n1080), .Y(n1081) );
AOI21X1TS U1617 ( .A0(Data_array_SWR[22]), .A1(n1240), .B0(n1082), .Y(n1083)
);
OAI222X1TS U1618 ( .A0(n1173), .A1(n1727), .B0(n1168), .B1(n1161), .C0(n948),
.C1(n1083), .Y(n1439) );
CLKBUFX2TS U1619 ( .A(n1723), .Y(n1257) );
NAND2X2TS U1620 ( .A(n948), .B(n1236), .Y(n1171) );
NOR2X2TS U1621 ( .A(shift_value_SHT2_EWR[4]), .B(n1636), .Y(n1634) );
INVX2TS U1622 ( .A(n1634), .Y(n1244) );
OAI222X1TS U1623 ( .A0(n1171), .A1(n1727), .B0(left_right_SHT2), .B1(n1083),
.C0(n1244), .C1(n1161), .Y(n1165) );
AOI22X1TS U1624 ( .A0(Data_array_SWR[19]), .A1(n1080), .B0(
Data_array_SWR[11]), .B1(n944), .Y(n1084) );
OAI2BB1X1TS U1625 ( .A0N(Data_array_SWR[15]), .A1N(n941), .B0(n1084), .Y(
n1085) );
AOI21X1TS U1626 ( .A0(Data_array_SWR[23]), .A1(n1240), .B0(n1085), .Y(n1130)
);
OAI222X1TS U1627 ( .A0(n1171), .A1(n1728), .B0(left_right_SHT2), .B1(n1130),
.C0(n1244), .C1(n1131), .Y(n1164) );
BUFX3TS U1628 ( .A(n1723), .Y(n1646) );
NAND2X1TS U1629 ( .A(n1142), .B(Raw_mant_NRM_SWR[14]), .Y(n1098) );
AOI21X1TS U1630 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1088), .B0(
Raw_mant_NRM_SWR[19]), .Y(n1090) );
AOI21X1TS U1631 ( .A0(n1093), .A1(n1092), .B0(n1091), .Y(n1094) );
NOR4BBX4TS U1632 ( .AN(n1098), .BN(n1096), .C(n1095), .D(n1094), .Y(n1278)
);
AOI21X1TS U1633 ( .A0(n1698), .A1(Raw_mant_NRM_SWR[20]), .B0(
Raw_mant_NRM_SWR[22]), .Y(n1097) );
AOI21X1TS U1634 ( .A0(n1104), .A1(n1103), .B0(n1102), .Y(n1106) );
NAND2X1TS U1635 ( .A(Raw_mant_NRM_SWR[12]), .B(n1105), .Y(n1147) );
AOI31X1TS U1636 ( .A0(n1108), .A1(Raw_mant_NRM_SWR[8]), .A2(n1695), .B0(
n1158), .Y(n1109) );
OAI211X4TS U1637 ( .A0(n1654), .A1(n1111), .B0(n1110), .C0(n1109), .Y(n1113)
);
NAND2X6TS U1638 ( .A(n1113), .B(n1520), .Y(n1563) );
NAND2X2TS U1639 ( .A(n1278), .B(n1551), .Y(n1287) );
INVX2TS U1640 ( .A(n938), .Y(n1112) );
AOI22X1TS U1641 ( .A0(n940), .A1(Raw_mant_NRM_SWR[24]), .B0(
Data_array_SWR[0]), .B1(n959), .Y(n1117) );
NAND2X1TS U1642 ( .A(n1565), .B(Raw_mant_NRM_SWR[23]), .Y(n1115) );
AOI22X1TS U1643 ( .A0(n1347), .A1(DmP_mant_SHT1_SW[1]), .B0(n962), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1114) );
OAI211X1TS U1644 ( .A0(n1563), .A1(n1740), .B0(n1115), .C0(n1114), .Y(n1362)
);
NOR2X4TS U1645 ( .A(n937), .B(n1277), .Y(n1380) );
AOI22X1TS U1646 ( .A0(n1362), .A1(n1380), .B0(n1565), .B1(
Raw_mant_NRM_SWR[25]), .Y(n1116) );
NAND2X1TS U1647 ( .A(n1117), .B(n1116), .Y(n819) );
NOR2X2TS U1648 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1694), .Y(n1528) );
OAI21XLTS U1649 ( .A0(n1528), .A1(n1118), .B0(n1526), .Y(n918) );
MXI2X2TS U1650 ( .A(DmP_mant_SFG_SWR[5]), .B(n968), .S0(n1784), .Y(
intadd_33_B_1_) );
NOR2XLTS U1651 ( .A(n1785), .B(DmP_mant_SFG_SWR[4]), .Y(n1120) );
NOR2X1TS U1652 ( .A(n1120), .B(n1119), .Y(intadd_33_CI) );
AOI211X1TS U1653 ( .A0(intadd_33_B_1_), .A1(n925), .B0(intadd_33_CI), .C0(
n928), .Y(n1123) );
INVX2TS U1654 ( .A(intadd_33_B_2_), .Y(n1121) );
OAI22X1TS U1655 ( .A0(n1123), .A1(n1122), .B0(DMP_SFG[4]), .B1(n1121), .Y(
n1124) );
XOR2X1TS U1656 ( .A(n1784), .B(DmP_mant_SFG_SWR[7]), .Y(n1125) );
NAND2X1TS U1657 ( .A(n1125), .B(DMP_SFG[5]), .Y(n1623) );
NOR2X1TS U1658 ( .A(n1125), .B(DMP_SFG[5]), .Y(n1624) );
NOR2BX1TS U1659 ( .AN(n1126), .B(n1624), .Y(intadd_34_B_0_) );
OAI22X1TS U1660 ( .A0(n1666), .A1(n1133), .B0(n1722), .B1(n1127), .Y(n1129)
);
OAI22X1TS U1661 ( .A0(n1131), .A1(n923), .B0(n1727), .B1(n943), .Y(n1128) );
AOI211X1TS U1662 ( .A0(Data_array_SWR[2]), .A1(n1236), .B0(n1129), .C0(n1128), .Y(n1174) );
OAI22X1TS U1663 ( .A0(n1174), .A1(n948), .B0(n1726), .B1(n1171), .Y(n1437)
);
OAI222X1TS U1664 ( .A0(n1173), .A1(n1728), .B0(n1168), .B1(n1131), .C0(n924),
.C1(n1130), .Y(n1440) );
AOI22X1TS U1665 ( .A0(Data_array_SWR[17]), .A1(n941), .B0(Data_array_SWR[13]), .B1(n944), .Y(n1132) );
AOI21X1TS U1666 ( .A0(Data_array_SWR[25]), .A1(n1240), .B0(n1134), .Y(n1167)
);
OA22X1TS U1667 ( .A0(n1167), .A1(left_right_SHT2), .B0(n1171), .B1(n1734),
.Y(n1135) );
OAI21X1TS U1668 ( .A0(n1244), .A1(n1232), .B0(n1135), .Y(n1429) );
BUFX3TS U1669 ( .A(n1723), .Y(n1642) );
AOI22X1TS U1670 ( .A0(Data_array_SWR[23]), .A1(n942), .B0(Data_array_SWR[19]), .B1(n1079), .Y(n1430) );
AOI22X1TS U1671 ( .A0(Data_array_SWR[10]), .A1(n933), .B0(Data_array_SWR[15]), .B1(n935), .Y(n1136) );
OAI221X1TS U1672 ( .A0(n949), .A1(n1430), .B0(n948), .B1(n1434), .C0(n1136),
.Y(n1425) );
AOI22X1TS U1673 ( .A0(Data_array_SWR[22]), .A1(n942), .B0(Data_array_SWR[18]), .B1(n1079), .Y(n1176) );
AOI22X1TS U1674 ( .A0(Data_array_SWR[14]), .A1(n935), .B0(Data_array_SWR[11]), .B1(n933), .Y(n1137) );
OAI221X1TS U1675 ( .A0(n949), .A1(n1176), .B0(n948), .B1(n1177), .C0(n1137),
.Y(n1426) );
AOI22X1TS U1676 ( .A0(Data_array_SWR[12]), .A1(n933), .B0(Data_array_SWR[13]), .B1(n936), .Y(n1138) );
AOI22X1TS U1677 ( .A0(Data_array_SWR[12]), .A1(n936), .B0(Data_array_SWR[13]), .B1(n934), .Y(n1139) );
AOI32X1TS U1678 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n1569), .A2(n1531),
.B0(shift_value_SHT2_EWR[3]), .B1(n937), .Y(n1150) );
OAI211X1TS U1679 ( .A0(Raw_mant_NRM_SWR[11]), .A1(Raw_mant_NRM_SWR[13]),
.B0(n1142), .C0(n1673), .Y(n1152) );
OAI2BB1X1TS U1680 ( .A0N(n1144), .A1N(n1673), .B0(n1143), .Y(n1145) );
OAI21X1TS U1681 ( .A0(n1149), .A1(n1148), .B0(n945), .Y(n1522) );
NAND2X1TS U1682 ( .A(n1150), .B(n1522), .Y(n817) );
AOI32X1TS U1683 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1569), .A2(n947), .B0(
shift_value_SHT2_EWR[2]), .B1(n959), .Y(n1160) );
OAI22X1TS U1684 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1156), .B0(n1155), .B1(
n1665), .Y(n1157) );
OAI31X1TS U1685 ( .A0(n1159), .A1(n1158), .A2(n1157), .B0(n1520), .Y(n1523)
);
NAND2X1TS U1686 ( .A(n1160), .B(n1523), .Y(n818) );
NOR2X4TS U1687 ( .A(n1424), .B(Shift_reg_FLAGS_7[0]), .Y(n1608) );
CLKBUFX2TS U1688 ( .A(n1608), .Y(n1631) );
INVX2TS U1689 ( .A(n1631), .Y(n1589) );
BUFX3TS U1690 ( .A(n1608), .Y(n1613) );
OAI22X1TS U1691 ( .A0(n1161), .A1(n923), .B0(n1728), .B1(n943), .Y(n1162) );
AOI211X1TS U1692 ( .A0(Data_array_SWR[3]), .A1(n1236), .B0(n1163), .C0(n1162), .Y(n1172) );
OAI22X1TS U1693 ( .A0(n946), .A1(n1172), .B0(n1725), .B1(n1173), .Y(n1166)
);
CLKBUFX2TS U1694 ( .A(n1608), .Y(n1436) );
OAI222X1TS U1695 ( .A0(n1173), .A1(n1734), .B0(n1168), .B1(n1232), .C0(n948),
.C1(n1167), .Y(n1442) );
INVX2TS U1696 ( .A(n1525), .Y(n1170) );
OAI22X1TS U1697 ( .A0(n1172), .A1(n1636), .B0(n1725), .B1(n1171), .Y(n1438)
);
OAI22X1TS U1698 ( .A0(left_right_SHT2), .A1(n1174), .B0(n1726), .B1(n1173),
.Y(n1612) );
AOI22X1TS U1699 ( .A0(Data_array_SWR[14]), .A1(n933), .B0(Data_array_SWR[11]), .B1(n935), .Y(n1175) );
OAI221X1TS U1700 ( .A0(left_right_SHT2), .A1(n1177), .B0(n1636), .B1(n1176),
.C0(n1175), .Y(n1435) );
INVX4TS U1701 ( .A(n1785), .Y(n1481) );
CLKXOR2X2TS U1702 ( .A(n1481), .B(DmP_mant_SFG_SWR[9]), .Y(intadd_34_B_1_)
);
XOR2X1TS U1703 ( .A(n1443), .B(DmP_mant_SFG_SWR[8]), .Y(intadd_34_CI) );
BUFX3TS U1704 ( .A(n1180), .Y(n1762) );
BUFX3TS U1705 ( .A(n1759), .Y(n1763) );
BUFX3TS U1706 ( .A(n1181), .Y(n1764) );
BUFX3TS U1707 ( .A(n1755), .Y(n1765) );
BUFX3TS U1708 ( .A(n1759), .Y(n1766) );
BUFX3TS U1709 ( .A(n1181), .Y(n1768) );
BUFX3TS U1710 ( .A(n1755), .Y(n1769) );
CLKBUFX2TS U1711 ( .A(n1178), .Y(n1182) );
BUFX3TS U1712 ( .A(n1181), .Y(n1779) );
BUFX3TS U1713 ( .A(n1759), .Y(n1754) );
BUFX3TS U1714 ( .A(n1178), .Y(n1755) );
BUFX3TS U1715 ( .A(n1178), .Y(n1756) );
BUFX3TS U1716 ( .A(n1178), .Y(n1759) );
BUFX3TS U1717 ( .A(n1756), .Y(n1760) );
BUFX3TS U1718 ( .A(n1755), .Y(n1781) );
BUFX3TS U1719 ( .A(n1758), .Y(n1761) );
BUFX3TS U1720 ( .A(n1756), .Y(n1767) );
BUFX3TS U1721 ( .A(n1758), .Y(n1757) );
BUFX3TS U1722 ( .A(n1756), .Y(n1753) );
BUFX3TS U1723 ( .A(n1180), .Y(n1746) );
BUFX3TS U1724 ( .A(n1178), .Y(n1758) );
BUFX3TS U1725 ( .A(n1183), .Y(n1747) );
BUFX3TS U1726 ( .A(n1759), .Y(n1749) );
BUFX3TS U1727 ( .A(n1758), .Y(n1780) );
BUFX3TS U1728 ( .A(n1178), .Y(n1752) );
BUFX3TS U1729 ( .A(n1758), .Y(n1751) );
BUFX3TS U1730 ( .A(n1181), .Y(n1745) );
BUFX3TS U1731 ( .A(n1179), .Y(n1783) );
BUFX3TS U1732 ( .A(n1755), .Y(n1750) );
BUFX3TS U1733 ( .A(n1756), .Y(n1748) );
BUFX3TS U1734 ( .A(n1183), .Y(n1771) );
BUFX3TS U1735 ( .A(n1759), .Y(n1770) );
BUFX3TS U1736 ( .A(n1179), .Y(n1782) );
BUFX3TS U1737 ( .A(n1758), .Y(n1744) );
BUFX3TS U1738 ( .A(n1181), .Y(n1773) );
BUFX3TS U1739 ( .A(n1180), .Y(n1778) );
BUFX3TS U1740 ( .A(n1179), .Y(n1774) );
BUFX3TS U1741 ( .A(n1180), .Y(n1775) );
BUFX3TS U1742 ( .A(n1182), .Y(n1772) );
BUFX3TS U1743 ( .A(n1755), .Y(n1777) );
BUFX3TS U1744 ( .A(n1756), .Y(n1776) );
CLKBUFX2TS U1745 ( .A(n1737), .Y(n1600) );
INVX2TS U1746 ( .A(n1600), .Y(n1582) );
NAND2X1TS U1747 ( .A(DmP_EXP_EWSW[25]), .B(n966), .Y(n1575) );
NOR2X1TS U1748 ( .A(n1667), .B(DMP_EXP_EWSW[24]), .Y(n1571) );
OAI22X1TS U1749 ( .A0(n1573), .A1(n1571), .B0(DmP_EXP_EWSW[24]), .B1(n1668),
.Y(n1577) );
AOI22X1TS U1750 ( .A0(DMP_EXP_EWSW[25]), .A1(n1733), .B0(n1575), .B1(n1577),
.Y(n1186) );
NOR2X1TS U1751 ( .A(n929), .B(DMP_EXP_EWSW[26]), .Y(n1187) );
AOI21X1TS U1752 ( .A0(DMP_EXP_EWSW[26]), .A1(n929), .B0(n1187), .Y(n1184) );
XNOR2X1TS U1753 ( .A(n1186), .B(n1184), .Y(n1185) );
OAI22X1TS U1754 ( .A0(n1187), .A1(n1186), .B0(DmP_EXP_EWSW[26]), .B1(n1732),
.Y(n1189) );
XNOR2X1TS U1755 ( .A(DmP_EXP_EWSW[27]), .B(DMP_EXP_EWSW[27]), .Y(n1188) );
XOR2X1TS U1756 ( .A(n1189), .B(n1188), .Y(n1190) );
OAI22X1TS U1757 ( .A0(n1700), .A1(intDX_EWSW[25]), .B0(n1699), .B1(
intDX_EWSW[26]), .Y(n1191) );
AOI221X1TS U1758 ( .A0(n1700), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n1699), .C0(n1191), .Y(n1197) );
OAI22X1TS U1759 ( .A0(n1713), .A1(intDX_EWSW[27]), .B0(n1716), .B1(
intDY_EWSW[28]), .Y(n1192) );
OAI22X1TS U1760 ( .A0(n1714), .A1(intDY_EWSW[29]), .B0(n1663), .B1(
intDY_EWSW[30]), .Y(n1193) );
AOI221X1TS U1761 ( .A0(n1714), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n1663), .C0(n1193), .Y(n1195) );
OAI22X1TS U1762 ( .A0(n1787), .A1(intDX_EWSW[1]), .B0(n1702), .B1(
intDX_EWSW[17]), .Y(n1198) );
OAI22X1TS U1763 ( .A0(n1712), .A1(intDX_EWSW[20]), .B0(n1705), .B1(
intDX_EWSW[21]), .Y(n1200) );
OAI22X1TS U1764 ( .A0(n1662), .A1(intDX_EWSW[22]), .B0(n1715), .B1(
intDX_EWSW[23]), .Y(n1201) );
OAI22X1TS U1765 ( .A0(n1650), .A1(intDX_EWSW[24]), .B0(n1703), .B1(
intDX_EWSW[9]), .Y(n1206) );
AOI221X1TS U1766 ( .A0(n1650), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1703), .C0(n1206), .Y(n1213) );
OAI22X1TS U1767 ( .A0(n1709), .A1(intDX_EWSW[12]), .B0(n1704), .B1(
intDX_EWSW[13]), .Y(n1208) );
OAI22X1TS U1768 ( .A0(n1710), .A1(intDX_EWSW[14]), .B0(n1661), .B1(
intDX_EWSW[15]), .Y(n1209) );
OAI22X1TS U1769 ( .A0(n1711), .A1(intDX_EWSW[16]), .B0(n1660), .B1(
intDX_EWSW[0]), .Y(n1214) );
AOI221X1TS U1770 ( .A0(n1711), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1660), .C0(n1214), .Y(n1221) );
OAI22X1TS U1771 ( .A0(n1707), .A1(intDX_EWSW[2]), .B0(n1701), .B1(
intDX_EWSW[3]), .Y(n1215) );
AOI221X1TS U1772 ( .A0(n1707), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1701), .C0(n1215), .Y(n1220) );
OAI22X1TS U1773 ( .A0(n1708), .A1(intDX_EWSW[4]), .B0(n1658), .B1(
intDX_EWSW[5]), .Y(n1216) );
AOI221X1TS U1774 ( .A0(n1708), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1658), .C0(n1216), .Y(n1219) );
OAI22X1TS U1775 ( .A0(n1706), .A1(intDX_EWSW[8]), .B0(n1692), .B1(
intDX_EWSW[6]), .Y(n1217) );
AOI221X1TS U1776 ( .A0(n1706), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1692), .C0(n1217), .Y(n1218) );
CLKXOR2X2TS U1777 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1414) );
AOI21X1TS U1778 ( .A0(n1414), .A1(intDX_EWSW[31]), .B0(n1226), .Y(n1580) );
OAI2BB2XLTS U1779 ( .B0(n1227), .B1(n1525), .A0N(final_result_ieee[31]),
.A1N(n1254), .Y(n591) );
XOR2X1TS U1780 ( .A(n1784), .B(DmP_mant_SFG_SWR[2]), .Y(n1614) );
INVX2TS U1781 ( .A(n1617), .Y(n1229) );
XNOR2X1TS U1782 ( .A(n1784), .B(DmP_mant_SFG_SWR[3]), .Y(n1616) );
OAI21X1TS U1783 ( .A0(n1229), .A1(DMP_SFG[1]), .B0(n1228), .Y(intadd_33_B_0_) );
AOI22X1TS U1784 ( .A0(Data_array_SWR[12]), .A1(n1268), .B0(Data_array_SWR[8]), .B1(n942), .Y(n1231) );
AOI22X1TS U1785 ( .A0(Data_array_SWR[4]), .A1(n1079), .B0(Data_array_SWR[0]),
.B1(n1236), .Y(n1230) );
OAI211X1TS U1786 ( .A0(n1232), .A1(n923), .B0(n1231), .C0(n1230), .Y(n1609)
);
AOI22X1TS U1787 ( .A0(Data_array_SWR[25]), .A1(n936), .B0(n949), .B1(n1609),
.Y(n1234) );
BUFX3TS U1788 ( .A(n1608), .Y(n1590) );
NAND2X1TS U1789 ( .A(n1274), .B(DmP_mant_SFG_SWR[25]), .Y(n1233) );
AOI22X1TS U1790 ( .A0(Data_array_SWR[13]), .A1(n1268), .B0(Data_array_SWR[9]), .B1(n941), .Y(n1238) );
AOI22X1TS U1791 ( .A0(Data_array_SWR[5]), .A1(n1079), .B0(Data_array_SWR[1]),
.B1(n1236), .Y(n1237) );
OAI211X1TS U1792 ( .A0(n1264), .A1(n923), .B0(n1238), .C0(n1237), .Y(n1606)
);
AOI22X1TS U1793 ( .A0(Data_array_SWR[24]), .A1(n936), .B0(n946), .B1(n1606),
.Y(n1649) );
NAND2X1TS U1794 ( .A(DmP_mant_SFG_SWR[24]), .B(n1274), .Y(n1239) );
AOI22X1TS U1795 ( .A0(Data_array_SWR[12]), .A1(n944), .B0(Data_array_SWR[16]), .B1(n941), .Y(n1242) );
AOI22X1TS U1796 ( .A0(Data_array_SWR[20]), .A1(n1080), .B0(
Data_array_SWR[24]), .B1(n1240), .Y(n1241) );
NAND2X1TS U1797 ( .A(n1242), .B(n1241), .Y(n1266) );
AOI22X1TS U1798 ( .A0(Data_array_SWR[8]), .A1(n935), .B0(n1266), .B1(n1636),
.Y(n1243) );
OA21XLTS U1799 ( .A0(n1264), .A1(n1244), .B0(n1243), .Y(n1645) );
NAND2X1TS U1800 ( .A(n1274), .B(DmP_mant_SFG_SWR[8]), .Y(n1245) );
INVX2TS U1801 ( .A(exp_rslt_NRM2_EW1[4]), .Y(n1247) );
NAND2X1TS U1802 ( .A(n1254), .B(final_result_ieee[27]), .Y(n1246) );
NAND2X1TS U1803 ( .A(n1254), .B(final_result_ieee[29]), .Y(n1249) );
INVX2TS U1804 ( .A(n1251), .Y(n1253) );
NAND2X1TS U1805 ( .A(n1254), .B(final_result_ieee[28]), .Y(n1252) );
NAND2X1TS U1806 ( .A(n1254), .B(final_result_ieee[26]), .Y(n1255) );
AOI22X1TS U1807 ( .A0(Data_array_SWR[20]), .A1(n1259), .B0(
Data_array_SWR[24]), .B1(n958), .Y(n1271) );
AOI22X1TS U1808 ( .A0(Data_array_SWR[12]), .A1(n942), .B0(Data_array_SWR[8]),
.B1(n944), .Y(n1261) );
NAND2X1TS U1809 ( .A(Data_array_SWR[16]), .B(n1268), .Y(n1260) );
OAI211X1TS U1810 ( .A0(n1271), .A1(n923), .B0(n1261), .C0(n1260), .Y(n1630)
);
NAND2X1TS U1811 ( .A(n1274), .B(DmP_mant_SFG_SWR[21]), .Y(n1263) );
INVX2TS U1812 ( .A(n1264), .Y(n1265) );
NAND2X1TS U1813 ( .A(n1274), .B(DmP_mant_SFG_SWR[17]), .Y(n1267) );
AOI22X1TS U1814 ( .A0(Data_array_SWR[13]), .A1(n942), .B0(Data_array_SWR[9]),
.B1(n1079), .Y(n1270) );
AOI22X1TS U1815 ( .A0(Data_array_SWR[17]), .A1(n1268), .B0(
shift_value_SHT2_EWR[4]), .B1(n1629), .Y(n1269) );
NAND2X1TS U1816 ( .A(n1270), .B(n1269), .Y(n1637) );
INVX2TS U1817 ( .A(n1271), .Y(n1635) );
NAND2X1TS U1818 ( .A(n1274), .B(DmP_mant_SFG_SWR[20]), .Y(n1273) );
CLKXOR2X2TS U1819 ( .A(n1443), .B(DmP_mant_SFG_SWR[10]), .Y(intadd_34_B_2_)
);
AOI22X1TS U1820 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1551), .B0(n1558), .B1(
DmP_mant_SHT1_SW[15]), .Y(n1275) );
OAI21X1TS U1821 ( .A0(n1695), .A1(n1553), .B0(n1275), .Y(n1276) );
AOI21X1TS U1822 ( .A0(n961), .A1(DmP_mant_SHT1_SW[14]), .B0(n1276), .Y(n1561) );
BUFX3TS U1823 ( .A(n1558), .Y(n1550) );
NOR2X4TS U1824 ( .A(n1278), .B(n1563), .Y(n1409) );
OAI2BB2XLTS U1825 ( .B0(n1288), .B1(n950), .A0N(Raw_mant_NRM_SWR[6]), .A1N(
n1409), .Y(n1279) );
AOI21X1TS U1826 ( .A0(n959), .A1(Data_array_SWR[16]), .B0(n1279), .Y(n1280)
);
AOI22X1TS U1827 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1551), .B0(n1347), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1282) );
AOI22X1TS U1828 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1565), .B0(n962), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1281) );
NAND2X1TS U1829 ( .A(n1282), .B(n1281), .Y(n1365) );
AOI22X1TS U1830 ( .A0(n959), .A1(Data_array_SWR[6]), .B0(n926), .B1(n1365),
.Y(n1284) );
NAND2X1TS U1831 ( .A(Raw_mant_NRM_SWR[16]), .B(n957), .Y(n1283) );
AOI22X1TS U1832 ( .A0(n961), .A1(DmP_mant_SHT1_SW[18]), .B0(n1550), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1285) );
AOI21X1TS U1833 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n1361), .B0(n1286), .Y(n1556) );
OAI22X1TS U1834 ( .A0(n1288), .A1(n953), .B0(n1654), .B1(n1287), .Y(n1289)
);
AOI21X1TS U1835 ( .A0(n937), .A1(Data_array_SWR[18]), .B0(n1289), .Y(n1290)
);
AOI21X1TS U1836 ( .A0(n1565), .A1(Raw_mant_NRM_SWR[0]), .B0(n962), .Y(n1549)
);
INVX2TS U1837 ( .A(n1553), .Y(n1421) );
OAI22X1TS U1838 ( .A0(n1374), .A1(n953), .B0(n1569), .B1(n1726), .Y(n1291)
);
AOI21X1TS U1839 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n940), .B0(n1291), .Y(n1292)
);
AOI22X1TS U1840 ( .A0(n1565), .A1(Raw_mant_NRM_SWR[24]), .B0(n1347), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1297) );
AOI22X1TS U1841 ( .A0(n939), .A1(Raw_mant_NRM_SWR[23]), .B0(n1112), .B1(
Data_array_SWR[1]), .Y(n1296) );
AOI22X1TS U1842 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1551), .B0(n1347), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1294) );
AOI22X1TS U1843 ( .A0(n1565), .A1(Raw_mant_NRM_SWR[22]), .B0(
DmP_mant_SHT1_SW[1]), .B1(n962), .Y(n1293) );
NAND2X1TS U1844 ( .A(n1294), .B(n1293), .Y(n1383) );
NAND2X1TS U1845 ( .A(n1380), .B(n1383), .Y(n1295) );
AOI22X1TS U1846 ( .A0(n1112), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1409), .Y(n1299) );
AOI22X1TS U1847 ( .A0(n937), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n957), .Y(n1301) );
AOI2BB2X1TS U1848 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n940), .A0N(n1308), .A1N(
n951), .Y(n1300) );
OAI211X1TS U1849 ( .A0(n1302), .A1(n954), .B0(n1301), .C0(n1300), .Y(n834)
);
AOI22X1TS U1850 ( .A0(n1112), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1409), .Y(n1305) );
AOI2BB2X1TS U1851 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n939), .A0N(n1303), .A1N(
n950), .Y(n1304) );
AOI22X1TS U1852 ( .A0(n937), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1409), .Y(n1307) );
INVX2TS U1853 ( .A(n1371), .Y(n1311) );
AOI22X1TS U1854 ( .A0(intDX_EWSW[2]), .A1(n971), .B0(DMP_EXP_EWSW[2]), .B1(
n1581), .Y(n1309) );
AOI22X1TS U1855 ( .A0(intDX_EWSW[1]), .A1(n971), .B0(DMP_EXP_EWSW[1]), .B1(
n1581), .Y(n1310) );
BUFX3TS U1856 ( .A(n1315), .Y(n1529) );
AOI22X1TS U1857 ( .A0(intDX_EWSW[20]), .A1(n1330), .B0(DmP_EXP_EWSW[20]),
.B1(n1529), .Y(n1312) );
AOI22X1TS U1858 ( .A0(intDX_EWSW[22]), .A1(n1330), .B0(DmP_EXP_EWSW[22]),
.B1(n1529), .Y(n1313) );
AOI22X1TS U1859 ( .A0(intDX_EWSW[21]), .A1(n1330), .B0(DmP_EXP_EWSW[21]),
.B1(n1529), .Y(n1314) );
BUFX3TS U1860 ( .A(n1315), .Y(n1405) );
AOI22X1TS U1861 ( .A0(intDY_EWSW[28]), .A1(n1330), .B0(DMP_EXP_EWSW[28]),
.B1(n1405), .Y(n1316) );
AOI22X1TS U1862 ( .A0(intDX_EWSW[3]), .A1(n971), .B0(DMP_EXP_EWSW[3]), .B1(
n1581), .Y(n1317) );
AOI22X1TS U1863 ( .A0(intDX_EWSW[0]), .A1(n971), .B0(DMP_EXP_EWSW[0]), .B1(
n1581), .Y(n1318) );
AOI22X1TS U1864 ( .A0(intDX_EWSW[5]), .A1(n1325), .B0(DMP_EXP_EWSW[5]), .B1(
n1392), .Y(n1319) );
AOI22X1TS U1865 ( .A0(intDX_EWSW[4]), .A1(n1325), .B0(DMP_EXP_EWSW[4]), .B1(
n1392), .Y(n1320) );
AOI22X1TS U1866 ( .A0(intDX_EWSW[6]), .A1(n971), .B0(DMP_EXP_EWSW[6]), .B1(
n1392), .Y(n1321) );
AOI22X1TS U1867 ( .A0(intDX_EWSW[17]), .A1(n1330), .B0(DmP_EXP_EWSW[17]),
.B1(n1529), .Y(n1322) );
AOI22X1TS U1868 ( .A0(intDX_EWSW[18]), .A1(n1330), .B0(DmP_EXP_EWSW[18]),
.B1(n1323), .Y(n1324) );
BUFX3TS U1869 ( .A(n1581), .Y(n1416) );
AOI22X1TS U1870 ( .A0(intDX_EWSW[3]), .A1(n1398), .B0(DmP_EXP_EWSW[3]), .B1(
n1416), .Y(n1326) );
AOI22X1TS U1871 ( .A0(intDX_EWSW[2]), .A1(n1330), .B0(DmP_EXP_EWSW[2]), .B1(
n1416), .Y(n1327) );
AOI22X1TS U1872 ( .A0(intDX_EWSW[5]), .A1(n1398), .B0(DmP_EXP_EWSW[5]), .B1(
n1323), .Y(n1328) );
AOI22X1TS U1873 ( .A0(intDX_EWSW[6]), .A1(n1330), .B0(DmP_EXP_EWSW[6]), .B1(
n1416), .Y(n1329) );
AOI22X1TS U1874 ( .A0(intDX_EWSW[19]), .A1(n1330), .B0(DmP_EXP_EWSW[19]),
.B1(n1529), .Y(n1331) );
AOI22X1TS U1875 ( .A0(intDX_EWSW[4]), .A1(n1398), .B0(DmP_EXP_EWSW[4]), .B1(
n1416), .Y(n1332) );
AOI22X1TS U1876 ( .A0(DmP_EXP_EWSW[27]), .A1(n1529), .B0(intDX_EWSW[27]),
.B1(n1398), .Y(n1333) );
AOI22X1TS U1877 ( .A0(intDX_EWSW[1]), .A1(n1398), .B0(DmP_EXP_EWSW[1]), .B1(
n1416), .Y(n1334) );
AOI22X1TS U1878 ( .A0(intDX_EWSW[7]), .A1(n1371), .B0(DmP_EXP_EWSW[7]), .B1(
n1323), .Y(n1335) );
AOI22X1TS U1879 ( .A0(intDX_EWSW[16]), .A1(n1371), .B0(DmP_EXP_EWSW[16]),
.B1(n1323), .Y(n1336) );
AOI22X1TS U1880 ( .A0(intDX_EWSW[10]), .A1(n1371), .B0(DmP_EXP_EWSW[10]),
.B1(n1416), .Y(n1337) );
AOI22X1TS U1881 ( .A0(intDX_EWSW[14]), .A1(n1371), .B0(DmP_EXP_EWSW[14]),
.B1(n1315), .Y(n1338) );
AOI22X1TS U1882 ( .A0(intDX_EWSW[11]), .A1(n1371), .B0(DmP_EXP_EWSW[11]),
.B1(n1315), .Y(n1339) );
AOI22X1TS U1883 ( .A0(intDX_EWSW[8]), .A1(n1398), .B0(DmP_EXP_EWSW[8]), .B1(
n972), .Y(n1340) );
AOI22X1TS U1884 ( .A0(intDX_EWSW[12]), .A1(n1369), .B0(DmP_EXP_EWSW[12]),
.B1(n1315), .Y(n1341) );
AOI22X1TS U1885 ( .A0(intDX_EWSW[9]), .A1(n1369), .B0(DmP_EXP_EWSW[9]), .B1(
n1323), .Y(n1342) );
AOI22X1TS U1886 ( .A0(intDX_EWSW[13]), .A1(n1369), .B0(DmP_EXP_EWSW[13]),
.B1(n972), .Y(n1344) );
AOI22X1TS U1887 ( .A0(intDX_EWSW[15]), .A1(n1371), .B0(DmP_EXP_EWSW[15]),
.B1(n1529), .Y(n1345) );
AOI22X1TS U1888 ( .A0(n963), .A1(DmP_mant_SHT1_SW[8]), .B0(n1347), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1348) );
AOI21X1TS U1889 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1565), .B0(n1349), .Y(
n1567) );
OAI2BB2X1TS U1890 ( .B0(n1350), .B1(n953), .A0N(Raw_mant_NRM_SWR[16]), .A1N(
n939), .Y(n1351) );
AOI21X1TS U1891 ( .A0(n959), .A1(Data_array_SWR[8]), .B0(n1351), .Y(n1352)
);
AOI22X1TS U1892 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1551), .B0(n1347), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1354) );
AOI22X1TS U1893 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1565), .B0(n961), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1353) );
NAND2X1TS U1894 ( .A(n1354), .B(n1353), .Y(n1379) );
AOI22X1TS U1895 ( .A0(n937), .A1(Data_array_SWR[7]), .B0(n926), .B1(n1379),
.Y(n1356) );
NAND2X1TS U1896 ( .A(Raw_mant_NRM_SWR[15]), .B(n957), .Y(n1355) );
AOI22X1TS U1897 ( .A0(n937), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n957), .Y(n1359) );
AOI2BB2X1TS U1898 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n940), .A0N(n1357), .A1N(
n952), .Y(n1358) );
AOI22X1TS U1899 ( .A0(n959), .A1(Data_array_SWR[2]), .B0(n926), .B1(n1362),
.Y(n1364) );
NAND2X1TS U1900 ( .A(Raw_mant_NRM_SWR[20]), .B(n1409), .Y(n1363) );
AOI22X1TS U1901 ( .A0(n959), .A1(Data_array_SWR[4]), .B0(n1380), .B1(n1365),
.Y(n1367) );
NAND2X1TS U1902 ( .A(Raw_mant_NRM_SWR[20]), .B(n940), .Y(n1366) );
INVX2TS U1903 ( .A(n971), .Y(n1415) );
AOI22X1TS U1904 ( .A0(intDY_EWSW[30]), .A1(n1369), .B0(DMP_EXP_EWSW[30]),
.B1(n1416), .Y(n1370) );
AOI22X1TS U1905 ( .A0(intDY_EWSW[29]), .A1(n1371), .B0(DMP_EXP_EWSW[29]),
.B1(n1416), .Y(n1372) );
AOI22X1TS U1906 ( .A0(intDX_EWSW[0]), .A1(n1398), .B0(DmP_EXP_EWSW[0]), .B1(
n1416), .Y(n1373) );
AOI22X1TS U1907 ( .A0(n959), .A1(Data_array_SWR[21]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n957), .Y(n1376) );
AOI22X1TS U1908 ( .A0(intDX_EWSW[7]), .A1(n1393), .B0(DMP_EXP_EWSW[7]), .B1(
n1392), .Y(n1377) );
AOI22X1TS U1909 ( .A0(intDX_EWSW[16]), .A1(n1393), .B0(DMP_EXP_EWSW[16]),
.B1(n1405), .Y(n1378) );
OAI21X1TS U1910 ( .A0(n1711), .A1(n1408), .B0(n1378), .Y(n785) );
AOI22X1TS U1911 ( .A0(n937), .A1(Data_array_SWR[5]), .B0(n1380), .B1(n1379),
.Y(n1382) );
NAND2X1TS U1912 ( .A(Raw_mant_NRM_SWR[19]), .B(n940), .Y(n1381) );
AOI22X1TS U1913 ( .A0(n1112), .A1(Data_array_SWR[3]), .B0(n926), .B1(n1383),
.Y(n1385) );
NAND2X1TS U1914 ( .A(Raw_mant_NRM_SWR[19]), .B(n957), .Y(n1384) );
AOI22X1TS U1915 ( .A0(intDX_EWSW[10]), .A1(n1393), .B0(DMP_EXP_EWSW[10]),
.B1(n1392), .Y(n1387) );
AOI22X1TS U1916 ( .A0(intDX_EWSW[14]), .A1(n1393), .B0(DMP_EXP_EWSW[14]),
.B1(n1405), .Y(n1388) );
OAI21X1TS U1917 ( .A0(n1710), .A1(n1408), .B0(n1388), .Y(n787) );
AOI22X1TS U1918 ( .A0(intDX_EWSW[9]), .A1(n1393), .B0(DMP_EXP_EWSW[9]), .B1(
n1392), .Y(n1389) );
AOI22X1TS U1919 ( .A0(intDX_EWSW[11]), .A1(n1393), .B0(DMP_EXP_EWSW[11]),
.B1(n1405), .Y(n1390) );
AOI22X1TS U1920 ( .A0(intDX_EWSW[8]), .A1(n1393), .B0(DMP_EXP_EWSW[8]), .B1(
n1392), .Y(n1391) );
AOI22X1TS U1921 ( .A0(intDX_EWSW[12]), .A1(n1393), .B0(DMP_EXP_EWSW[12]),
.B1(n1392), .Y(n1394) );
AOI22X1TS U1922 ( .A0(intDX_EWSW[19]), .A1(n1406), .B0(DMP_EXP_EWSW[19]),
.B1(n1405), .Y(n1396) );
OAI21X1TS U1923 ( .A0(n1664), .A1(n1408), .B0(n1396), .Y(n782) );
AOI22X1TS U1924 ( .A0(intDX_EWSW[18]), .A1(n1406), .B0(DMP_EXP_EWSW[18]),
.B1(n1405), .Y(n1397) );
OAI21X1TS U1925 ( .A0(n1717), .A1(n1408), .B0(n1397), .Y(n783) );
AOI222X1TS U1926 ( .A0(n1398), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1581), .C0(intDY_EWSW[23]), .C1(n1406), .Y(n1399) );
INVX2TS U1927 ( .A(n1399), .Y(n612) );
AOI22X1TS U1928 ( .A0(intDX_EWSW[22]), .A1(n1406), .B0(DMP_EXP_EWSW[22]),
.B1(n1405), .Y(n1400) );
AOI22X1TS U1929 ( .A0(intDX_EWSW[17]), .A1(n1406), .B0(DMP_EXP_EWSW[17]),
.B1(n1405), .Y(n1401) );
OAI21X1TS U1930 ( .A0(n1702), .A1(n1408), .B0(n1401), .Y(n784) );
AOI22X1TS U1931 ( .A0(intDX_EWSW[20]), .A1(n1406), .B0(DMP_EXP_EWSW[20]),
.B1(n1405), .Y(n1402) );
OAI21X1TS U1932 ( .A0(n1712), .A1(n1408), .B0(n1402), .Y(n781) );
AOI22X1TS U1933 ( .A0(DMP_EXP_EWSW[27]), .A1(n1529), .B0(intDX_EWSW[27]),
.B1(n1406), .Y(n1403) );
AOI22X1TS U1934 ( .A0(DMP_EXP_EWSW[23]), .A1(n1529), .B0(intDX_EWSW[23]),
.B1(n1406), .Y(n1404) );
AOI22X1TS U1935 ( .A0(intDX_EWSW[21]), .A1(n1406), .B0(DMP_EXP_EWSW[21]),
.B1(n1405), .Y(n1407) );
OAI21X1TS U1936 ( .A0(n1705), .A1(n1408), .B0(n1407), .Y(n780) );
AOI22X1TS U1937 ( .A0(n959), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n957), .Y(n1412) );
INVX2TS U1938 ( .A(n1414), .Y(n1419) );
AOI22X1TS U1939 ( .A0(intDX_EWSW[31]), .A1(n1417), .B0(SIGN_FLAG_EXP), .B1(
n1416), .Y(n1418) );
OAI31X1TS U1940 ( .A0(n1420), .A1(n1419), .A2(n1596), .B0(n1418), .Y(n768)
);
AO22X1TS U1941 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1421), .B0(
Raw_mant_NRM_SWR[0]), .B1(n1551), .Y(n1422) );
OAI2BB2XLTS U1942 ( .B0(n1555), .B1(n954), .A0N(n937), .A1N(
Data_array_SWR[24]), .Y(n843) );
BUFX3TS U1943 ( .A(n1599), .Y(n1626) );
NOR2XLTS U1944 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1423) );
AOI32X4TS U1945 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1423), .B1(n1694), .Y(n1532)
);
MXI2X1TS U1946 ( .A(n1626), .B(n1424), .S0(n1532), .Y(n913) );
BUFX3TS U1947 ( .A(n1608), .Y(n1639) );
AOI22X1TS U1948 ( .A0(Data_array_SWR[10]), .A1(n935), .B0(Data_array_SWR[15]), .B1(n933), .Y(n1432) );
OAI211X1TS U1949 ( .A0(n1434), .A1(left_right_SHT2), .B0(n1432), .C0(n1431),
.Y(n1643) );
XOR2X1TS U1950 ( .A(n1481), .B(DmP_mant_SFG_SWR[21]), .Y(n1471) );
XOR2X1TS U1951 ( .A(n1481), .B(DmP_mant_SFG_SWR[20]), .Y(n1468) );
XOR2X1TS U1952 ( .A(n1443), .B(DmP_mant_SFG_SWR[15]), .Y(n1493) );
XOR2X1TS U1953 ( .A(n1443), .B(DmP_mant_SFG_SWR[14]), .Y(n1509) );
XOR2X1TS U1954 ( .A(n1443), .B(DmP_mant_SFG_SWR[13]), .Y(n1512) );
XOR2X1TS U1955 ( .A(n1443), .B(DmP_mant_SFG_SWR[12]), .Y(n1515) );
XNOR2X2TS U1956 ( .A(n1784), .B(DmP_mant_SFG_SWR[11]), .Y(n1603) );
AOI22X1TS U1957 ( .A0(DMP_SFG[7]), .A1(intadd_34_B_1_), .B0(intadd_34_B_2_),
.B1(DMP_SFG[8]), .Y(n1446) );
INVX2TS U1958 ( .A(n1603), .Y(n1444) );
OAI22X1TS U1959 ( .A0(n1444), .A1(DMP_SFG[9]), .B0(intadd_34_B_2_), .B1(
DMP_SFG[8]), .Y(n1445) );
XOR2X1TS U1960 ( .A(n1784), .B(DmP_mant_SFG_SWR[16]), .Y(n1449) );
NOR2X1TS U1961 ( .A(n1449), .B(DMP_SFG[14]), .Y(n1495) );
XOR2X1TS U1962 ( .A(n1481), .B(DmP_mant_SFG_SWR[17]), .Y(n1450) );
NOR2X2TS U1963 ( .A(n1450), .B(DMP_SFG[15]), .Y(n1497) );
NOR2X1TS U1964 ( .A(n1495), .B(n1497), .Y(n1486) );
XOR2X1TS U1965 ( .A(n1481), .B(DmP_mant_SFG_SWR[18]), .Y(n1451) );
XOR2X1TS U1966 ( .A(n1481), .B(DmP_mant_SFG_SWR[19]), .Y(n1453) );
NOR2X2TS U1967 ( .A(n1453), .B(DMP_SFG[17]), .Y(n1461) );
NAND2X1TS U1968 ( .A(n1449), .B(DMP_SFG[14]), .Y(n1503) );
NAND2X1TS U1969 ( .A(n1450), .B(DMP_SFG[15]), .Y(n1498) );
OAI21X1TS U1970 ( .A0(n1497), .A1(n1503), .B0(n1498), .Y(n1485) );
NAND2X1TS U1971 ( .A(n1451), .B(DMP_SFG[16]), .Y(n1487) );
INVX2TS U1972 ( .A(n1487), .Y(n1452) );
AOI21X1TS U1973 ( .A0(n1485), .A1(n1488), .B0(n1452), .Y(n1458) );
NAND2X1TS U1974 ( .A(n1453), .B(DMP_SFG[17]), .Y(n1462) );
OAI21X1TS U1975 ( .A0(n1458), .A1(n1461), .B0(n1462), .Y(n1454) );
AOI21X4TS U1976 ( .A0(n1506), .A1(n1455), .B0(n1454), .Y(n1467) );
INVX2TS U1977 ( .A(n1457), .Y(n1460) );
AOI21X1TS U1978 ( .A0(n1506), .A1(n1460), .B0(n1459), .Y(n1465) );
INVX2TS U1979 ( .A(n1461), .Y(n1463) );
NAND2X1TS U1980 ( .A(n1463), .B(n1462), .Y(n1464) );
XOR2X1TS U1981 ( .A(n1465), .B(n1464), .Y(n1466) );
AFHCINX2TS U1982 ( .CIN(n1467), .B(n1468), .A(DMP_SFG[18]), .S(n1469), .CO(
n1470) );
XOR2X1TS U1983 ( .A(n1481), .B(DmP_mant_SFG_SWR[22]), .Y(n1474) );
AFHCONX2TS U1984 ( .A(DMP_SFG[19]), .B(n1471), .CI(n1470), .CON(n1473), .S(
n1456) );
XOR2X1TS U1985 ( .A(n1481), .B(DmP_mant_SFG_SWR[23]), .Y(n1477) );
AFHCINX2TS U1986 ( .CIN(n1473), .B(n1474), .A(DMP_SFG[20]), .S(n1472), .CO(
n1476) );
XOR2X1TS U1987 ( .A(n1481), .B(DmP_mant_SFG_SWR[24]), .Y(n1480) );
AFHCONX2TS U1988 ( .A(DMP_SFG[21]), .B(n1477), .CI(n1476), .CON(n1479), .S(
n1475) );
AFHCINX2TS U1989 ( .CIN(n1479), .B(n1480), .A(DMP_SFG[22]), .S(n1478), .CO(
n1483) );
XOR2X1TS U1990 ( .A(n1481), .B(DmP_mant_SFG_SWR[25]), .Y(n1482) );
XNOR2X1TS U1991 ( .A(n1483), .B(n1482), .Y(n1484) );
AOI21X1TS U1992 ( .A0(n1506), .A1(n1486), .B0(n1485), .Y(n1490) );
NAND2X1TS U1993 ( .A(n1488), .B(n1487), .Y(n1489) );
XOR2X1TS U1994 ( .A(n1490), .B(n1489), .Y(n1491) );
INVX2TS U1995 ( .A(n1495), .Y(n1504) );
AOI21X1TS U1996 ( .A0(n1506), .A1(n1504), .B0(n1496), .Y(n1501) );
INVX2TS U1997 ( .A(n1497), .Y(n1499) );
NAND2X1TS U1998 ( .A(n1499), .B(n1498), .Y(n1500) );
XOR2X1TS U1999 ( .A(n1501), .B(n1500), .Y(n1502) );
NAND2X1TS U2000 ( .A(n1504), .B(n1503), .Y(n1505) );
XNOR2X1TS U2001 ( .A(n1506), .B(n1505), .Y(n1507) );
MXI2X1TS U2002 ( .A(DmP_mant_SFG_SWR[0]), .B(n969), .S0(n1784), .Y(n1517) );
MXI2X1TS U2003 ( .A(n1736), .B(n1517), .S0(n1518), .Y(n564) );
MXI2X1TS U2004 ( .A(DmP_mant_SFG_SWR[1]), .B(n1738), .S0(n1784), .Y(n1519)
);
MXI2X1TS U2005 ( .A(n1730), .B(n1519), .S0(n1518), .Y(n572) );
OAI2BB1X1TS U2006 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n1531), .B0(n1522),
.Y(n560) );
OAI2BB1X1TS U2007 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n921), .B0(n1523), .Y(
n571) );
OAI2BB1X1TS U2008 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n1531), .B0(n1563),
.Y(n566) );
OA21XLTS U2009 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1525),
.Y(n606) );
AOI22X1TS U2010 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1527), .B1(n1657), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U2011 ( .A(n1527), .B(n1526), .Y(n919) );
INVX2TS U2012 ( .A(n1532), .Y(n1530) );
AOI22X1TS U2013 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1528), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1657), .Y(n1533) );
AOI22X1TS U2014 ( .A0(n1532), .A1(n1529), .B0(n1598), .B1(n1530), .Y(n916)
);
AOI22X1TS U2015 ( .A0(n1532), .A1(n1598), .B0(n932), .B1(n1530), .Y(n915) );
AOI22X1TS U2016 ( .A0(n1532), .A1(n1626), .B0(n1531), .B1(n1530), .Y(n912)
);
AOI22X1TS U2017 ( .A0(n1532), .A1(n921), .B0(n1723), .B1(n1530), .Y(n911) );
INVX2TS U2018 ( .A(n1536), .Y(n1545) );
INVX2TS U2019 ( .A(n1546), .Y(n1534) );
BUFX3TS U2020 ( .A(n1536), .Y(n1541) );
BUFX3TS U2021 ( .A(n1536), .Y(n1544) );
BUFX3TS U2022 ( .A(n1536), .Y(n1548) );
BUFX3TS U2023 ( .A(n1548), .Y(n1535) );
INVX2TS U2024 ( .A(n1546), .Y(n1547) );
INVX2TS U2025 ( .A(n1548), .Y(n1537) );
BUFX3TS U2026 ( .A(n1536), .Y(n1542) );
INVX2TS U2027 ( .A(n1548), .Y(n1538) );
BUFX3TS U2028 ( .A(n1536), .Y(n1540) );
INVX2TS U2029 ( .A(n1548), .Y(n1539) );
INVX2TS U2030 ( .A(n1546), .Y(n1543) );
OAI22X1TS U2031 ( .A0(n1549), .A1(n955), .B0(n1569), .B1(n1659), .Y(n844) );
AOI22X1TS U2032 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1551), .B0(
DmP_mant_SHT1_SW[21]), .B1(n1550), .Y(n1552) );
AOI21X1TS U2033 ( .A0(DmP_mant_SHT1_SW[20]), .A1(n963), .B0(n1554), .Y(n1557) );
OAI222X1TS U2034 ( .A0(n1569), .A1(n1725), .B0(n952), .B1(n1555), .C0(n954),
.C1(n1557), .Y(n841) );
OAI222X1TS U2035 ( .A0(n1735), .A1(n1569), .B0(n951), .B1(n1557), .C0(n955),
.C1(n1556), .Y(n839) );
AOI22X1TS U2036 ( .A0(n963), .A1(DmP_mant_SHT1_SW[12]), .B0(n1558), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1559) );
AOI21X1TS U2037 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n1565), .B0(n1560), .Y(
n1566) );
OAI222X1TS U2038 ( .A0(n1666), .A1(n1569), .B0(n951), .B1(n1561), .C0(n955),
.C1(n1566), .Y(n833) );
AOI22X1TS U2039 ( .A0(n961), .A1(DmP_mant_SHT1_SW[10]), .B0(n1347), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1562) );
AOI21X1TS U2040 ( .A0(Raw_mant_NRM_SWR[13]), .A1(n1565), .B0(n1564), .Y(
n1568) );
OAI222X1TS U2041 ( .A0(n1729), .A1(n1569), .B0(n952), .B1(n1566), .C0(n954),
.C1(n1568), .Y(n831) );
OAI222X1TS U2042 ( .A0(n1722), .A1(n1569), .B0(n951), .B1(n1568), .C0(n955),
.C1(n1567), .Y(n829) );
INVX2TS U2043 ( .A(n1598), .Y(n1601) );
AOI21X1TS U2044 ( .A0(DMP_EXP_EWSW[23]), .A1(n967), .B0(n1573), .Y(n1570) );
INVX2TS U2045 ( .A(n1600), .Y(n1579) );
AOI21X1TS U2046 ( .A0(DMP_EXP_EWSW[24]), .A1(n1667), .B0(n1571), .Y(n1572)
);
XNOR2X1TS U2047 ( .A(n1573), .B(n1572), .Y(n1574) );
XNOR2X1TS U2048 ( .A(n1577), .B(n1576), .Y(n1578) );
OAI222X1TS U2049 ( .A0(n1594), .A1(n1731), .B0(n1668), .B1(n1595), .C0(n1650), .C1(n1596), .Y(n777) );
OAI222X1TS U2050 ( .A0(n1594), .A1(n1670), .B0(n966), .B1(n1595), .C0(n1700),
.C1(n1596), .Y(n776) );
OAI222X1TS U2051 ( .A0(n1594), .A1(n1671), .B0(n1732), .B1(n1595), .C0(n1699), .C1(n1596), .Y(n775) );
BUFX3TS U2052 ( .A(n1737), .Y(n1583) );
BUFX3TS U2053 ( .A(n932), .Y(n1584) );
INVX2TS U2054 ( .A(n1631), .Y(n1611) );
INVX2TS U2055 ( .A(n1600), .Y(n1585) );
BUFX3TS U2056 ( .A(n1737), .Y(n1586) );
BUFX3TS U2057 ( .A(n932), .Y(n1587) );
INVX2TS U2058 ( .A(n931), .Y(n1588) );
BUFX3TS U2059 ( .A(n1737), .Y(n1602) );
INVX2TS U2060 ( .A(n1626), .Y(n1620) );
BUFX3TS U2061 ( .A(n1626), .Y(n1621) );
INVX2TS U2062 ( .A(n1598), .Y(n1591) );
BUFX3TS U2063 ( .A(n1737), .Y(n1592) );
BUFX3TS U2064 ( .A(n1600), .Y(n1593) );
OAI222X1TS U2065 ( .A0(n1596), .A1(n1731), .B0(n1667), .B1(n1595), .C0(n1650), .C1(n1594), .Y(n611) );
OAI222X1TS U2066 ( .A0(n1596), .A1(n1670), .B0(n1733), .B1(n1595), .C0(n1700), .C1(n1594), .Y(n610) );
OAI222X1TS U2067 ( .A0(n1596), .A1(n1671), .B0(n929), .B1(n1595), .C0(n1699),
.C1(n1594), .Y(n609) );
XOR2X1TS U2068 ( .A(n1603), .B(DMP_SFG[9]), .Y(n1604) );
XOR2X1TS U2069 ( .A(intadd_34_n1), .B(n1604), .Y(n1605) );
AOI22X1TS U2070 ( .A0(n1622), .A1(n1605), .B0(n1672), .B1(n1626), .Y(n575)
);
AOI22X1TS U2071 ( .A0(Data_array_SWR[24]), .A1(n934), .B0(n948), .B1(n1606),
.Y(n1607) );
AOI22X1TS U2072 ( .A0(n1608), .A1(n1607), .B0(n1738), .B1(n1638), .Y(n573)
);
AOI22X1TS U2073 ( .A0(Data_array_SWR[25]), .A1(n934), .B0(n1636), .B1(n1609),
.Y(n1610) );
AOI22X1TS U2074 ( .A0(n1631), .A1(n1610), .B0(n969), .B1(n1638), .Y(n565) );
AOI22X1TS U2075 ( .A0(n1622), .A1(n1615), .B0(n1676), .B1(n1626), .Y(n562)
);
XOR2X1TS U2076 ( .A(n1616), .B(DMP_SFG[1]), .Y(n1618) );
XNOR2X1TS U2077 ( .A(n1618), .B(n1617), .Y(n1619) );
AOI22X1TS U2078 ( .A0(n1622), .A1(n1619), .B0(n1665), .B1(n1621), .Y(n561)
);
AOI22X1TS U2079 ( .A0(n1622), .A1(intadd_33_SUM_0_), .B0(n1653), .B1(n1621),
.Y(n557) );
AOI22X1TS U2080 ( .A0(n1622), .A1(intadd_33_SUM_2_), .B0(n1654), .B1(n1621),
.Y(n555) );
XNOR2X1TS U2081 ( .A(intadd_33_n1), .B(n1625), .Y(n1627) );
AOI22X1TS U2082 ( .A0(n1628), .A1(n1627), .B0(n1674), .B1(n1626), .Y(n554)
);
AOI22X1TS U2083 ( .A0(n1631), .A1(n1632), .B0(n1720), .B1(n1638), .Y(n550)
);
INVX2TS U2084 ( .A(n1644), .Y(n1648) );
OAI2BB2XLTS U2085 ( .B0(n1632), .B1(n1648), .A0N(final_result_ieee[2]),
.A1N(n1646), .Y(n549) );
OAI2BB2XLTS U2086 ( .B0(n1633), .B1(n1648), .A0N(final_result_ieee[19]),
.A1N(n1723), .Y(n548) );
AOI22X1TS U2087 ( .A0(n1639), .A1(n1640), .B0(n968), .B1(n1638), .Y(n542) );
OAI2BB2XLTS U2088 ( .B0(n1640), .B1(n1648), .A0N(final_result_ieee[3]),
.A1N(n1646), .Y(n541) );
OAI2BB2XLTS U2089 ( .B0(n1641), .B1(n1648), .A0N(final_result_ieee[18]),
.A1N(n1646), .Y(n540) );
OAI2BB2XLTS U2090 ( .B0(n1645), .B1(n1648), .A0N(final_result_ieee[6]),
.A1N(n1646), .Y(n529) );
OAI2BB2XLTS U2091 ( .B0(n1647), .B1(n1648), .A0N(final_result_ieee[15]),
.A1N(n1646), .Y(n528) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk10.tcl_GDAN16M4P4_syn.sdf");
endmodule
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: March, 7th 2017
*/
`timescale 1ns / 1ps
module jt51_interpol(
input clk, // Use a clock at least 162*2 times faster than JT51 sampling rate
input rst,
input sample_in,
input signed [15:0] left_in,
input signed [15:0] right_in,
// mix in other sound sources, like ADPCM sound of arcade boards
// other sound sources should be at the same
// sampling frequency than the FM sound
// for best results
input signed [15:0] left_other,
input signed [15:0] right_other,
output signed [15:0] out_l,
output signed [15:0] out_r,
output sample_out
);
/* max_clk_count is chosen so as to divide the input clock to
obtain a 32xFs frequency.
Fs = JT51 sampling frequency, normally ~55kHz
32xFs = 1.78MHz
If this module's clock is 50MHz then
max_clk_count = 50/1.78=28
The division must be exact, otherwise samples will get out of sync
eventually and sound will get distorted.
max_clk_count*32 is the number of clock ticks that the FIR module
has to process the two sound channels. Each channels needs at least
162 clock ticks, so in total it needs just over 324 ticks.
(162 is the number of stages of the filter)
Using 50MHz and max_clk_count=28 gives 896 clock ticks, which is
more than enough.
*/
parameter max_clk_count = 7'd111;
reg [15:0] fir_left_in, fir_right_in, left_mux, right_mux;
reg fir_sample_in;
reg fir4_sample_in;
reg [2:0] state;
reg [6:0] cnt;
always @(*)
case( state )
3'd0: { left_mux, right_mux } <= { left_in, right_in};
3'd3: { left_mux, right_mux } <= { left_other, right_other};
default: { left_mux, right_mux } <= 32'd0;
endcase
always @(posedge clk)
if( rst ) begin
state <= 2'b0;
fir_sample_in <= 1'b0;
cnt <= 6'd0;
end else begin
fir4_sample_in <= ( cnt==0 || cnt==28 || cnt==56 || cnt==84 );
if( cnt==max_clk_count ) begin
cnt <= 6'd0;
state <= state+1'b1;
fir_sample_in <= 1'b1;
{fir_left_in,fir_right_in} <= { left_mux, right_mux };
end
else begin
cnt <= cnt + 1'b1;
fir_sample_in <= 1'b0;
end
end
localparam fir8_w=16; // at least 16
localparam fir4_w=16; // at least 16
wire [fir8_w-1:0] fir8_out_l, fir8_out_r;
wire [fir4_w-1:0] fir4_out_l, fir4_out_r;
assign out_l = fir4_out_l[15:0];
assign out_r = fir4_out_r[15:0];
//assign out_l = fir8_out_l[15:0];
//assign out_r = fir8_out_r[15:0];
//wire fir8_sample;
jt51_fir8 #(.data_width(16), .output_width(fir8_w)) u_fir8 (
.clk ( clk ),
.rst ( rst ),
.sample ( fir_sample_in ),
.left_in ( fir_left_in ),
.right_in ( fir_right_in ),
.left_out ( fir8_out_l ),
.right_out ( fir8_out_r )
// .sample_out ( fir8_sample )
);
jt51_fir4 #(.data_width(16), .output_width(fir4_w)) u_fir4 (
.clk ( clk ),
.rst ( rst ),
.sample ( fir4_sample_in),
.left_in ( fir8_out_l[fir8_w-1:fir8_w-16] ),
.right_in ( fir8_out_r[fir8_w-1:fir8_w-16] ),
.left_out ( fir4_out_l ),
.right_out ( fir4_out_r ),
.sample_out ( sample_out )
);
endmodule
|
/*
******************************************************************************
* File Name : tb_ada_core.v
* Project : ADA processor
* Version : 0.1
* Date : Sept 2nd, 2014
* Author : Angel Terrones <[email protected]>
*
* Disclaimer : Copyright (c) 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Testbench for the EXU (execution unit)
******************************************************************************
*/
`timescale 1ns / 1ns
`include "ada_defines.v"
`define cycle 10
module tb_ada_core;
reg clk;
reg rst;
reg [31:0] io_interrupt; //
reg [31:0] io_data_i; // data from device
reg io_ready; // device is ready
reg [31:0] eimem_cache_data_i; // Data from memory
reg eimem_cache_ready; // memory is ready
reg [31:0] edmem_cache_data_i; // Data from memory
reg edmem_cache_ready; // memory is ready
wire [31:0] io_address; // device address
wire [31:0] io_data_o; // data to device
wire io_we; // write to device
wire io_enable; // enable operation
wire [31:0] eimem_cache_address; // data address
wire eimem_cache_wr; // write = 1, read = 0,
wire eimem_cache_enable; // enable operation
wire [31:0] edmem_cache_address; // data address
wire [31:0] edmem_cache_data_o; // data to memory
wire edmem_cache_wr; // write = 1, read = 0,
wire edmem_cache_enable; // enable operation
wire icache_flush;
wire dcache_flush;
//--------------------------------------------------------------------------
// UUT
//--------------------------------------------------------------------------
ada_core uut(
.clk(clk),
.rst(rst),
.io_interrupt(io_interrupt),
.io_data_i(io_data_i),
.io_ready(io_ready),
.io_address(io_address),
.io_data_o(io_data_o),
.io_we(io_we),
.io_enable(io_enable),
.eimem_cache_data_i(eimem_cache_data_i),
.eimem_cache_ready(eimem_cache_ready),
.eimem_cache_address(eimem_cache_address),
.eimem_cache_wr(eimem_cache_wr),
.eimem_cache_enable(eimem_cache_enable),
.edmem_cache_data_i(edmem_cache_data_i),
.edmem_cache_ready(edmem_cache_ready),
.edmem_cache_address(edmem_cache_address),
.edmem_cache_data_o(edmem_cache_data_o),
.edmem_cache_wr(edmem_cache_wr),
.edmem_cache_enable(edmem_cache_enable),
.icache_flush(icache_flush),
.dcache_flush(dcache_flush)
);
//--------------------------------------------------------------------------
// Setup
//--------------------------------------------------------------------------
initial begin
// Initialize regs
clk <= 1;
rst <= 1;
io_interrupt <= 0;
io_data_i <= 0;
io_ready <= 0;
eimem_cache_data_i <= 0;
eimem_cache_ready <= 0;
edmem_cache_data_i <= 0;
edmem_cache_ready <= 0;
// dump the wave file
$dumpfile("tb_core.vcd");
$dumpvars;
end
//--------------------------------------------------------------------------
// clock
//--------------------------------------------------------------------------
always begin
#(`cycle/2) clk = !clk;
end
//--------------------------------------------------------------------------
// simulation
//--------------------------------------------------------------------------
initial begin
rst = #(4.5*`cycle)0;
$display("Testing the ADA Core: begin");
//--------------------------------------------------------------------------
rst = #(10*`cycle)0;
@(posedge clk)
//--------------------------------------------------------------------------
@(posedge clk)
//--------------------------------------------------------------------------
$display("Testing the ADA Core: finished");
$finish;
end
endmodule
|
// Notes to self: latency is parameterized by LATENCY_CYCLES
// bandwidth is DATA_WIDTH / cycle
// latency_cycles is minus one the true latency due to a reg needed to isolate RAM from the rest of the chip
module wb_shift_ram
#(
parameter DATA_WIDTH = 32,
parameter WORD_WIDTH = 8,
parameter ADDR_WIDTH = 3,
parameter LATENCY_CYCLES = 3,
)
(
input wire clk_i,
input wire rst_i,
input wire [0 +: ADDR_WIDTH] adr_i,
input wire [0 +: DATA_WIDTH] dat_i,
output wire [0 +: DATA_WIDTH] dat_o,
output wire [0 +: ADDR_WIDTH] tag_o, // replies back with the requested address, for cacheline purposes
input wire sel_i,
input wire we_i,
input wire stb_i,
input wire cyc_i,
output wire ack_o,
output wire stall_o
);
// FIFO shift registers
reg [0 +: ADDR_WIDTH] lat_pipe_addr [LATENCY_CYCLES];
reg [0 +: DATA_WIDTH] lat_pipe_data [LATENCY_CYCLES];
reg [0 +: DATA_WIDTH / WORD_WIDTH] lat_pipe_sel [LATENCY_CYCLES];
reg lat_pipe_we [LATENCY_CYCLES];
reg lat_pipe_stb [LATENCY_CYCLES];
// RAM
reg [0 +: DATA_WIDTH] mem [1<<ADDR_WIDTH];
// Internal wires
reg [0 +: ADDR_WIDTH] current_addr;
reg [0 +: DATA_WIDTH] current_data;
reg [0 +: DATA_WIDTH / WORD_WIDTH] current_sel;
reg current_we;
reg current_stb;
integer lat_idx;
// Outputs
assign stall_o = 1'b0; // Never stall (no need to, there will always be one slot open
assign ack_o = current_stb; // Send an ACK once everything's gone through the pipe
assign tag_o = current_addr; // Send back the requested address for caching purposes (assuming the synthizer will optimize out unneeded bits)
assign dat_o = current_data;
// Write to mem only the parts we requested, leaving the others alone
genvar sel_idx;
generate
for (sel_idx = 0 ; sel_idx < (DATA_WIDTH / WORD_WIDTH); sel_idx++) begin : gen_sel_cases
always @(posedge clk_i) begin
if(!rst_i && current_stb && current_we && current_sel[sel_idx]) begin
// mem[current_addr][0:7] <= current_data[0:7];
mem[current_addr][sel_idx*WORD_WIDTH : (sel_idx+1)*WORD_WIDTH - 1] <= current_data[sel_idx*WORD_WIDTH: (sel_idx+1)*WORD_WIDTH - 1];
end
end
endgenerate
always @(posedge clk_i) begin
if (rst_i) begin
for (lat_idx = 0; lat_idx < LATENCY_CYCLES; lat_idx++) begin
lat_pipe_stb[lat_idx] <= 0;
end
end
else begin
lat_pipe_stb [0] <= stb_i;
lat_pipe_sel [0] <= sel_i;
lat_pipe_we [0] <= we_i;
lat_pipe_addr[0] <= adr_i;
lat_pipe_data[0] <= dat_i;
current_addr <= lat_pipe_addr[LATENCY_CYCLES - 1];
current_data <= mem[lat_pipe_addr[LATENCY_CYCLES - 1]];;
current_sel <= lat_pipe_sel [LATENCY_CYCLES - 1];
current_we <= lat_pipe_we [LATENCY_CYCLES - 1];
current_stb <= lat_pipe_stb [LATENCY_CYCLES - 1];
for (lat_idx = 1; lat_idx < LATENCY_CYCLES; lat_idx++) begin
lat_pipe_addr[lat_idx] <= lat_pipe_addr[lat_idx-1];
lat_pipe_data[lat_idx] <= lat_pipe_data[lat_idx-1];
lat_pipe_sel [lat_idx] <= lat_pipe_sel [lat_idx-1];
lat_pipe_we [lat_idx] <= lat_pipe_we [lat_idx-1];
lat_pipe_stb [lat_idx] <= lat_pipe_stb [lat_idx-1];
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S4S_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DLYMETAL6S4S_BEHAVIORAL_PP_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__dlymetal6s4s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S4S_BEHAVIORAL_PP_V
|
/*
* TX (Transmit)
*
* Including Frame Generator, FM0 Encoder, Miller Encoder
*
* bs_data is connected to Gate of NMOS in BACKSCATTER circuit which is the part of Analog front-end circuit
*/
`timescale 1us / 1ns
module tx
(
output bs_data,
output pre_p_complete,
output p_complete,
output bs_complete,
input clk_blf,
input clk_frm,
input clk_fm0,
input clk_mil,
input rst_for_new_package,
input reply_data,
input [15:0]crc_16,
input [1:0]m,
input trext,
input reply_complete,
input en_crc16_for_rpy,
input start_working
);
frmgen frmgen_1
(
.send_data(send_data),
.en_fm0(en_fm0),
.st_enc(st_enc),
.pre_p_complete(pre_p_complete),
.p_complete(p_complete),
.fg_complete(fg_complete),
.clk_frm(clk_frm),
.rst_for_new_package(rst_for_new_package),
.reply_data(reply_data),
.crc_16(crc_16),
.m(m),
.trext(trext),
.reply_complete(reply_complete),
.en_crc16_for_rpy(en_crc16_for_rpy)
);
fm0_enc fm0_enc_1
(
.fm0_data(fm0_data),
.fm0_complete(fm0_complete),
.clk_fm0(clk_fm0),
.rst_for_new_package(rst_for_new_package),
.send_data(send_data),
.en_fm0(en_fm0),
.trext(trext),
.st_enc(st_enc),
.fg_complete(fg_complete)
);
miller_enc miller_enc_1
(
.miller_data(miller_data),
.mil_complete(mil_complete),
.clk_mil(clk_mil),
.rst_for_new_package(rst_for_new_package),
.clk_blf(clk_blf),
.send_data(send_data),
.en_fm0(en_fm0),
.trext(trext),
.st_enc(st_enc),
.fg_complete(fg_complete)
);
// --- Backscattered Data ---
assign bs_data = (start_working)? fm0_data | miller_data : 1'b0;
assign bs_complete = fm0_complete | mil_complete;
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : fme_satd_gen.v
// Author : Yufeng Bai
// Email : [email protected]
//
// $Id$
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module fme_satd_gen (
clk ,
rstn ,
satd_start_i ,
blk_idx_i ,
half_ip_flag_i ,
mv_x_i ,
mv_y_i ,
mv_x_o ,
mv_y_o ,
blk_idx_o ,
half_ip_flag_o ,
ip_ready_i ,
end_ip_i ,
cost_start_o ,
cur_rden_o ,
//cur_sel_o ,
//cur_idx_o ,
cur_4x4_idx_o ,
cur_4x4_x_o ,
cur_4x4_y_o ,
cur_pel_i ,
candi0_valid_i ,
candi1_valid_i ,
candi2_valid_i ,
candi3_valid_i ,
candi4_valid_i ,
candi5_valid_i ,
candi6_valid_i ,
candi7_valid_i ,
candi8_valid_i ,
candi0_pixles_i ,
candi1_pixles_i ,
candi2_pixles_i ,
candi3_pixles_i ,
candi4_pixles_i ,
candi5_pixles_i ,
candi6_pixles_i ,
candi7_pixles_i ,
candi8_pixles_i ,
satd0_o ,
satd1_o ,
satd2_o ,
satd3_o ,
satd4_o ,
satd5_o ,
satd6_o ,
satd7_o ,
satd8_o ,
satd_valid_o
);
parameter SATD_WIDTH = `PIXEL_WIDTH + 10;
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input [1-1:0] satd_start_i ; // 8x8 block satd start signal
input [6-1:0] blk_idx_i ; // specify current block index
input [1-1:0] half_ip_flag_i ; // half/ quarter interpolation
input [`FMV_WIDTH-1:0] mv_x_i ; //
input [`FMV_WIDTH-1:0] mv_y_i ; //
output [`FMV_WIDTH-1:0] mv_x_o ; // mv pass to cost cal. & cmp
output [`FMV_WIDTH-1:0] mv_y_o ; //
output [1-1:0] half_ip_flag_o ; // half/ quarter interpolation : pass to cost cal & cmp
output [6-1:0] blk_idx_o ; // specify current block index
input [1-1:0] ip_ready_i ; // ip ready
input [1-1:0] end_ip_i ; // end of interpolation
output [1-1:0] cost_start_o ; // mv ready, cost start
output [1-1:0] cur_rden_o ; // current lcu read enable
//output [1-1:0] cur_sel_o ; // use block read mode
//output [6-1:0] cur_idx_o ; // current block read index
output [4-1:0] cur_4x4_x_o ; // current 8x8 block x position
output [4-1:0] cur_4x4_y_o ; // current 8x8 block y position
output [5-1:0] cur_4x4_idx_o ; // current 8x8 block idx
input [32*`PIXEL_WIDTH-1:0] cur_pel_i ; // current block pixel
input [1-1:0] candi0_valid_i ; // candidate 0 row pixels valid
input [1-1:0] candi1_valid_i ; // candidate 1 row pixels valid
input [1-1:0] candi2_valid_i ; // candidate 2 row pixels valid
input [1-1:0] candi3_valid_i ; // candidate 3 row pixels valid
input [1-1:0] candi4_valid_i ; // candidate 4 row pixels valid
input [1-1:0] candi5_valid_i ; // candidate 5 row pixels valid
input [1-1:0] candi6_valid_i ; // candidate 6 row pixels valid
input [1-1:0] candi7_valid_i ; // candidate 7 row pixels valid
input [1-1:0] candi8_valid_i ; // candidate 8 row pixels valid
input [`PIXEL_WIDTH*8-1:0] candi0_pixles_i ; // candidate 0 row pixels
input [`PIXEL_WIDTH*8-1:0] candi1_pixles_i ; // candidate 1 row pixels
input [`PIXEL_WIDTH*8-1:0] candi2_pixles_i ; // candidate 2 row pixels
input [`PIXEL_WIDTH*8-1:0] candi3_pixles_i ; // candidate 3 row pixels
input [`PIXEL_WIDTH*8-1:0] candi4_pixles_i ; // candidate 4 row pixels
input [`PIXEL_WIDTH*8-1:0] candi5_pixles_i ; // candidate 5 row pixels
input [`PIXEL_WIDTH*8-1:0] candi6_pixles_i ; // candidate 6 row pixels
input [`PIXEL_WIDTH*8-1:0] candi7_pixles_i ; // candidate 7 row pixels
input [`PIXEL_WIDTH*8-1:0] candi8_pixles_i ; // candidate 8 row pixels
output [SATD_WIDTH-1 :0] satd0_o ; // candidate 0 SATD
output [SATD_WIDTH-1 :0] satd1_o ; // candidate 1 SATD
output [SATD_WIDTH-1 :0] satd2_o ; // candidate 2 SATD
output [SATD_WIDTH-1 :0] satd3_o ; // candidate 3 SATD
output [SATD_WIDTH-1 :0] satd4_o ; // candidate 4 SATD
output [SATD_WIDTH-1 :0] satd5_o ; // candidate 5 SATD
output [SATD_WIDTH-1 :0] satd6_o ; // candidate 6 SATD
output [SATD_WIDTH-1 :0] satd7_o ; // candidate 7 SATD
output [SATD_WIDTH-1 :0] satd8_o ; // candidate 8 SATD
output [1-1:0] satd_valid_o ; // satd valid
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
reg [`FMV_WIDTH-1: 0] mv_x_o; // buffer0 to store mv information
reg [`FMV_WIDTH-1: 0] mv_y_o;
reg [1-1: 0] half_ip_flag_o;
reg [1-1: 0] cost_start_o;
reg [1-1: 0] cur_4x4_idx;
reg [6-1: 0] blk_idx_r0;
reg [6-1: 0] blk_idx_r1;
wire [6-1: 0] blk_idx ;
reg idx_in_flag;
reg idx_out_flag;
wire [8*`PIXEL_WIDTH-1:0] cur_pixel0;
wire [8*`PIXEL_WIDTH-1:0] cur_pixel1;
wire [8*`PIXEL_WIDTH-1:0] cur_pixel2;
wire [8*`PIXEL_WIDTH-1:0] cur_pixel3;
wire [8*`PIXEL_WIDTH-1:0] cur_pixel4;
wire [8*`PIXEL_WIDTH-1:0] cur_pixel5;
wire [8*`PIXEL_WIDTH-1:0] cur_pixel6;
wire [8*`PIXEL_WIDTH-1:0] cur_pixel7;
reg [32*`PIXEL_WIDTH-1:0] cur_pel_reg0;
reg [32*`PIXEL_WIDTH-1:0] cur_pel_reg1;
reg cur_valid;
reg [8*`PIXEL_WIDTH-1 :0] sp0_cur;
reg [8*`PIXEL_WIDTH-1 :0] sp1_cur;
reg [8*`PIXEL_WIDTH-1 :0] sp2_cur;
reg [8*`PIXEL_WIDTH-1 :0] sp3_cur;
reg [8*`PIXEL_WIDTH-1 :0] sp4_cur;
reg [8*`PIXEL_WIDTH-1 :0] sp5_cur;
reg [8*`PIXEL_WIDTH-1 :0] sp6_cur;
reg [8*`PIXEL_WIDTH-1 :0] sp7_cur;
reg [8*`PIXEL_WIDTH-1 :0] sp8_cur;
reg [3-1 :0] sp0_cnt;
reg [3-1 :0] sp1_cnt;
reg [3-1 :0] sp2_cnt;
reg [3-1 :0] sp3_cnt;
reg [3-1 :0] sp4_cnt;
reg [3-1 :0] sp5_cnt;
reg [3-1 :0] sp6_cnt;
reg [3-1 :0] sp7_cnt;
reg [3-1 :0] sp8_cnt;
//reg [4-1 :0] satd_cnt;
wire [SATD_WIDTH-1 :0] sp0_satd;
wire [SATD_WIDTH-1 :0] sp1_satd;
wire [SATD_WIDTH-1 :0] sp2_satd;
wire [SATD_WIDTH-1 :0] sp3_satd;
wire [SATD_WIDTH-1 :0] sp4_satd;
wire [SATD_WIDTH-1 :0] sp5_satd;
wire [SATD_WIDTH-1 :0] sp6_satd;
wire [SATD_WIDTH-1 :0] sp7_satd;
wire [SATD_WIDTH-1 :0] sp8_satd;
wire [2-1 :0] cur_idx32, cur_idx16, cur_idx08;
wire [3-1 :0] cur_idx_x, cur_idx_y;
wire [6-1 :0] cur_idx;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign cur_pixel7 = cur_pel_reg1[1*8*`PIXEL_WIDTH-1:0*8*`PIXEL_WIDTH];
assign cur_pixel6 = cur_pel_reg1[2*8*`PIXEL_WIDTH-1:1*8*`PIXEL_WIDTH];
assign cur_pixel5 = cur_pel_reg1[3*8*`PIXEL_WIDTH-1:2*8*`PIXEL_WIDTH];
assign cur_pixel4 = cur_pel_reg1[4*8*`PIXEL_WIDTH-1:3*8*`PIXEL_WIDTH];
assign cur_pixel3 = cur_pel_reg0[1*8*`PIXEL_WIDTH-1:0*8*`PIXEL_WIDTH];
assign cur_pixel2 = cur_pel_reg0[2*8*`PIXEL_WIDTH-1:1*8*`PIXEL_WIDTH];
assign cur_pixel1 = cur_pel_reg0[3*8*`PIXEL_WIDTH-1:2*8*`PIXEL_WIDTH];
assign cur_pixel0 = cur_pel_reg0[4*8*`PIXEL_WIDTH-1:3*8*`PIXEL_WIDTH];
assign cur_rden_o = ip_ready_i;
//assign cur_sel_o = 1'b1;
//assign cur_idx_o = {cur_idx_y, cur_idx_x};
assign cur_4x4_x_o = {cur_idx_x,1'b0};
assign cur_4x4_y_o = {cur_idx_y,1'b0};
assign cur_4x4_idx_o = {2'b0,cur_4x4_idx,2'b0};
assign satd0_o = sp0_satd;
assign satd1_o = sp1_satd;
assign satd2_o = sp2_satd;
assign satd3_o = sp3_satd;
assign satd4_o = sp4_satd;
assign satd5_o = sp5_satd;
assign satd6_o = sp6_satd;
assign satd7_o = sp7_satd;
assign satd8_o = sp8_satd;
//assign satd_valid_o = (satd_cnt == 'd9);
assign blk_idx = (idx_out_flag) ? blk_idx_r1 : blk_idx_r0;
assign cur_idx = (idx_in_flag ) ? blk_idx_r0 : blk_idx_r1;
// zig-zag to raster
assign cur_idx32 = cur_idx[5:4];
assign cur_idx16 = cur_idx[3:2];
assign cur_idx08 = cur_idx[1:0];
assign cur_idx_x = {cur_idx32[0],cur_idx16[0],cur_idx08[0]};
assign cur_idx_y = {cur_idx32[1],cur_idx16[1],cur_idx08[1]};
assign blk_idx_o = blk_idx;
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
mv_x_o <= 'd0;
mv_y_o <= 'd0;
half_ip_flag_o <= 1'b0;
end
else if (end_ip_i) begin
mv_x_o <= mv_x_i;
mv_y_o <= mv_y_i;
half_ip_flag_o <= half_ip_flag_i;
end
end
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
cost_start_o <= 1'b0;
end
else begin
cost_start_o <= end_ip_i;
end
end
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
idx_in_flag <= 1'b0;
blk_idx_r0 <= 'd0;
blk_idx_r1 <= 'd0;
end
else if (satd_start_i) begin
idx_in_flag <= ~idx_in_flag;
if(~idx_in_flag)
blk_idx_r0 <= blk_idx_i;
else
blk_idx_r1 <= blk_idx_i;
end
end
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
idx_out_flag <= 1'd0;
end
else if (satd_valid_o) begin
idx_out_flag <= ~idx_out_flag;
end
end
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
cur_4x4_idx <= 1'b0;
cur_valid <= 1'b0;
end
else if(cur_rden_o) begin
cur_4x4_idx <= ~cur_4x4_idx;
cur_valid <= 1'b1;
end
else begin
cur_4x4_idx <= cur_4x4_idx;
cur_valid <= 1'b0;
end
end
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
cur_pel_reg0 <= 'b0;
cur_pel_reg1 <= 'b0;
end
else if(cur_valid) begin
if(cur_4x4_idx)
cur_pel_reg0 <= cur_pel_i;
else
cur_pel_reg1 <= cur_pel_i;
end
end
/*
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
satd_cnt <= 'd0;
end
else if ( end_ip_i) begin
satd_cnt <= 'd0;
end
else begin
satd_cnt <= satd_cnt + 'd1;
end
end
*/
// ********************************************
//
// SATD for Search Points
//
// ********************************************
// sp 0
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
sp0_cnt <= 'd0;
end
else if (satd_start_i) begin
sp0_cnt <= 'd0;
end
else if (candi0_valid_i) begin
sp0_cnt <= sp0_cnt + 'd1;
end
end
always @(*) begin
case(sp0_cnt)
3'd0: sp0_cur = cur_pixel0;
3'd1: sp0_cur = cur_pixel1;
3'd2: sp0_cur = cur_pixel2;
3'd3: sp0_cur = cur_pixel3;
3'd4: sp0_cur = cur_pixel4;
3'd5: sp0_cur = cur_pixel5;
3'd6: sp0_cur = cur_pixel6;
3'd7: sp0_cur = cur_pixel7;
endcase
end
fme_satd_8x8 sp0(
.clk (clk),
.rstn (rstn),
.cur_p0_i(sp0_cur[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.cur_p1_i(sp0_cur[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.cur_p2_i(sp0_cur[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.cur_p3_i(sp0_cur[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.cur_p4_i(sp0_cur[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.cur_p5_i(sp0_cur[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.cur_p6_i(sp0_cur[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.cur_p7_i(sp0_cur[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.sp_valid_i(candi0_valid_i),
.sp0_i(candi0_pixles_i[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.sp1_i(candi0_pixles_i[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.sp2_i(candi0_pixles_i[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.sp3_i(candi0_pixles_i[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.sp4_i(candi0_pixles_i[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.sp5_i(candi0_pixles_i[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.sp6_i(candi0_pixles_i[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.sp7_i(candi0_pixles_i[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.satd_8x8_o(sp0_satd),
.satd_8x8_valid_o(sp0_valid)
);
/*
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
satd0_o <= 'd0;
end
else if (sp0_valid) begin
satd0_o <= sp0_satd;
end
end
*/
// sp 1
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
sp1_cnt <= 'd0;
end
else if (satd_start_i) begin
sp1_cnt <= 'd0;
end
else if (candi1_valid_i) begin
sp1_cnt <= sp1_cnt + 'd1;
end
end
always @(*) begin
case(sp1_cnt)
3'd0: sp1_cur = cur_pixel0;
3'd1: sp1_cur = cur_pixel1;
3'd2: sp1_cur = cur_pixel2;
3'd3: sp1_cur = cur_pixel3;
3'd4: sp1_cur = cur_pixel4;
3'd5: sp1_cur = cur_pixel5;
3'd6: sp1_cur = cur_pixel6;
3'd7: sp1_cur = cur_pixel7;
endcase
end
fme_satd_8x8 sp1(
.clk (clk),
.rstn (rstn),
.cur_p0_i(sp1_cur[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.cur_p1_i(sp1_cur[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.cur_p2_i(sp1_cur[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.cur_p3_i(sp1_cur[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.cur_p4_i(sp1_cur[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.cur_p5_i(sp1_cur[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.cur_p6_i(sp1_cur[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.cur_p7_i(sp1_cur[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.sp_valid_i(candi1_valid_i),
.sp0_i(candi1_pixles_i[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.sp1_i(candi1_pixles_i[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.sp2_i(candi1_pixles_i[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.sp3_i(candi1_pixles_i[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.sp4_i(candi1_pixles_i[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.sp5_i(candi1_pixles_i[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.sp6_i(candi1_pixles_i[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.sp7_i(candi1_pixles_i[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.satd_8x8_o(sp1_satd),
.satd_8x8_valid_o(sp1_valid)
);
/*
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
satd1_o <= 'd0;
end
else if (sp1_valid) begin
satd1_o <= sp1_satd;
end
end
*/
// sp 2
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
sp2_cnt <= 'd0;
end
else if (satd_start_i) begin
sp2_cnt <= 'd0;
end
else if (candi2_valid_i) begin
sp2_cnt <= sp2_cnt + 'd1;
end
end
always @(*) begin
case(sp2_cnt)
3'd0: sp2_cur = cur_pixel0;
3'd1: sp2_cur = cur_pixel1;
3'd2: sp2_cur = cur_pixel2;
3'd3: sp2_cur = cur_pixel3;
3'd4: sp2_cur = cur_pixel4;
3'd5: sp2_cur = cur_pixel5;
3'd6: sp2_cur = cur_pixel6;
3'd7: sp2_cur = cur_pixel7;
endcase
end
fme_satd_8x8 sp2(
.clk (clk),
.rstn (rstn),
.cur_p0_i(sp2_cur[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.cur_p1_i(sp2_cur[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.cur_p2_i(sp2_cur[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.cur_p3_i(sp2_cur[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.cur_p4_i(sp2_cur[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.cur_p5_i(sp2_cur[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.cur_p6_i(sp2_cur[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.cur_p7_i(sp2_cur[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.sp_valid_i(candi2_valid_i),
.sp0_i(candi2_pixles_i[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.sp1_i(candi2_pixles_i[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.sp2_i(candi2_pixles_i[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.sp3_i(candi2_pixles_i[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.sp4_i(candi2_pixles_i[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.sp5_i(candi2_pixles_i[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.sp6_i(candi2_pixles_i[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.sp7_i(candi2_pixles_i[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.satd_8x8_o(sp2_satd),
.satd_8x8_valid_o(sp2_valid)
);
/*
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
satd2_o <= 'd0;
end
else if (sp2_valid) begin
satd2_o <= sp2_satd;
end
end
*/
// sp 3
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
sp3_cnt <= 'd0;
end
else if (satd_start_i) begin
sp3_cnt <= 'd0;
end
else if (candi3_valid_i) begin
sp3_cnt <= sp3_cnt + 'd1;
end
end
always @(*) begin
case(sp3_cnt)
3'd0: sp3_cur = cur_pixel0;
3'd1: sp3_cur = cur_pixel1;
3'd2: sp3_cur = cur_pixel2;
3'd3: sp3_cur = cur_pixel3;
3'd4: sp3_cur = cur_pixel4;
3'd5: sp3_cur = cur_pixel5;
3'd6: sp3_cur = cur_pixel6;
3'd7: sp3_cur = cur_pixel7;
endcase
end
fme_satd_8x8 sp3(
.clk (clk),
.rstn (rstn),
.cur_p0_i(sp3_cur[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.cur_p1_i(sp3_cur[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.cur_p2_i(sp3_cur[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.cur_p3_i(sp3_cur[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.cur_p4_i(sp3_cur[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.cur_p5_i(sp3_cur[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.cur_p6_i(sp3_cur[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.cur_p7_i(sp3_cur[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.sp_valid_i(candi3_valid_i),
.sp0_i(candi3_pixles_i[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.sp1_i(candi3_pixles_i[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.sp2_i(candi3_pixles_i[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.sp3_i(candi3_pixles_i[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.sp4_i(candi3_pixles_i[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.sp5_i(candi3_pixles_i[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.sp6_i(candi3_pixles_i[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.sp7_i(candi3_pixles_i[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.satd_8x8_o(sp3_satd),
.satd_8x8_valid_o(sp3_valid)
);
/*
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
satd3_o <= 'd0;
end
else if (sp3_valid) begin
satd3_o <= sp3_satd;
end
end
*/
// sp 4
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
sp4_cnt <= 'd0;
end
else if (satd_start_i) begin
sp4_cnt <= 'd0;
end
else if (candi4_valid_i) begin
sp4_cnt <= sp4_cnt + 'd1;
end
end
always @(*) begin
case(sp4_cnt)
3'd0: sp4_cur = cur_pixel0;
3'd1: sp4_cur = cur_pixel1;
3'd2: sp4_cur = cur_pixel2;
3'd3: sp4_cur = cur_pixel3;
3'd4: sp4_cur = cur_pixel4;
3'd5: sp4_cur = cur_pixel5;
3'd6: sp4_cur = cur_pixel6;
3'd7: sp4_cur = cur_pixel7;
endcase
end
fme_satd_8x8 sp4(
.clk (clk),
.rstn (rstn),
.cur_p0_i(sp4_cur[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.cur_p1_i(sp4_cur[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.cur_p2_i(sp4_cur[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.cur_p3_i(sp4_cur[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.cur_p4_i(sp4_cur[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.cur_p5_i(sp4_cur[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.cur_p6_i(sp4_cur[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.cur_p7_i(sp4_cur[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.sp_valid_i(candi4_valid_i),
.sp0_i(candi4_pixles_i[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.sp1_i(candi4_pixles_i[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.sp2_i(candi4_pixles_i[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.sp3_i(candi4_pixles_i[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.sp4_i(candi4_pixles_i[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.sp5_i(candi4_pixles_i[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.sp6_i(candi4_pixles_i[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.sp7_i(candi4_pixles_i[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.satd_8x8_o(sp4_satd),
.satd_8x8_valid_o(sp4_valid)
);
/*
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
satd4_o <= 'd0;
end
else if (sp4_valid) begin
satd4_o <= sp4_satd;
end
end
*/
// sp 5
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
sp5_cnt <= 'd0;
end
else if (satd_start_i) begin
sp5_cnt <= 'd0;
end
else if (candi5_valid_i) begin
sp5_cnt <= sp5_cnt + 'd1;
end
end
always @(*) begin
case(sp5_cnt)
3'd0: sp5_cur = cur_pixel0;
3'd1: sp5_cur = cur_pixel1;
3'd2: sp5_cur = cur_pixel2;
3'd3: sp5_cur = cur_pixel3;
3'd4: sp5_cur = cur_pixel4;
3'd5: sp5_cur = cur_pixel5;
3'd6: sp5_cur = cur_pixel6;
3'd7: sp5_cur = cur_pixel7;
endcase
end
fme_satd_8x8 sp5(
.clk (clk),
.rstn (rstn),
.cur_p0_i(sp5_cur[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.cur_p1_i(sp5_cur[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.cur_p2_i(sp5_cur[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.cur_p3_i(sp5_cur[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.cur_p4_i(sp5_cur[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.cur_p5_i(sp5_cur[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.cur_p6_i(sp5_cur[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.cur_p7_i(sp5_cur[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.sp_valid_i(candi5_valid_i),
.sp0_i(candi5_pixles_i[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.sp1_i(candi5_pixles_i[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.sp2_i(candi5_pixles_i[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.sp3_i(candi5_pixles_i[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.sp4_i(candi5_pixles_i[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.sp5_i(candi5_pixles_i[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.sp6_i(candi5_pixles_i[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.sp7_i(candi5_pixles_i[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.satd_8x8_o(sp5_satd),
.satd_8x8_valid_o(sp5_valid)
);
/*
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
satd5_o <= 'd0;
end
else if (sp5_valid) begin
satd5_o <= sp5_satd;
end
end
*/
// sp 6
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
sp6_cnt <= 'd0;
end
else if (satd_start_i) begin
sp6_cnt <= 'd0;
end
else if (candi6_valid_i) begin
sp6_cnt <= sp6_cnt + 'd1;
end
end
always @(*) begin
case(sp6_cnt)
3'd0: sp6_cur = cur_pixel0;
3'd1: sp6_cur = cur_pixel1;
3'd2: sp6_cur = cur_pixel2;
3'd3: sp6_cur = cur_pixel3;
3'd4: sp6_cur = cur_pixel4;
3'd5: sp6_cur = cur_pixel5;
3'd6: sp6_cur = cur_pixel6;
3'd7: sp6_cur = cur_pixel7;
endcase
end
fme_satd_8x8 sp6(
.clk (clk),
.rstn (rstn),
.cur_p0_i(sp6_cur[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.cur_p1_i(sp6_cur[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.cur_p2_i(sp6_cur[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.cur_p3_i(sp6_cur[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.cur_p4_i(sp6_cur[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.cur_p5_i(sp6_cur[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.cur_p6_i(sp6_cur[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.cur_p7_i(sp6_cur[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.sp_valid_i(candi6_valid_i),
.sp0_i(candi6_pixles_i[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.sp1_i(candi6_pixles_i[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.sp2_i(candi6_pixles_i[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.sp3_i(candi6_pixles_i[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.sp4_i(candi6_pixles_i[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.sp5_i(candi6_pixles_i[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.sp6_i(candi6_pixles_i[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.sp7_i(candi6_pixles_i[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.satd_8x8_o(sp6_satd),
.satd_8x8_valid_o(sp6_valid)
);
/*
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
satd6_o <= 'd0;
end
else if (sp6_valid) begin
satd6_o <= sp6_satd;
end
end
*/
// sp 7
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
sp7_cnt <= 'd0;
end
else if (satd_start_i) begin
sp7_cnt <= 'd0;
end
else if (candi7_valid_i) begin
sp7_cnt <= sp7_cnt + 'd1;
end
end
always @(*) begin
case(sp7_cnt)
3'd0: sp7_cur = cur_pixel0;
3'd1: sp7_cur = cur_pixel1;
3'd2: sp7_cur = cur_pixel2;
3'd3: sp7_cur = cur_pixel3;
3'd4: sp7_cur = cur_pixel4;
3'd5: sp7_cur = cur_pixel5;
3'd6: sp7_cur = cur_pixel6;
3'd7: sp7_cur = cur_pixel7;
endcase
end
fme_satd_8x8 sp7(
.clk (clk),
.rstn (rstn),
.cur_p0_i(sp7_cur[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.cur_p1_i(sp7_cur[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.cur_p2_i(sp7_cur[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.cur_p3_i(sp7_cur[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.cur_p4_i(sp7_cur[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.cur_p5_i(sp7_cur[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.cur_p6_i(sp7_cur[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.cur_p7_i(sp7_cur[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.sp_valid_i(candi7_valid_i),
.sp0_i(candi7_pixles_i[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.sp1_i(candi7_pixles_i[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.sp2_i(candi7_pixles_i[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.sp3_i(candi7_pixles_i[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.sp4_i(candi7_pixles_i[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.sp5_i(candi7_pixles_i[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.sp6_i(candi7_pixles_i[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.sp7_i(candi7_pixles_i[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.satd_8x8_o(sp7_satd),
.satd_8x8_valid_o(sp7_valid)
);
/*
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
satd7_o <= 'd0;
end
else if (sp7_valid) begin
satd7_o <= sp7_satd;
end
end
*/
// sp 8
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
sp8_cnt <= 'd0;
end
else if (satd_start_i) begin
sp8_cnt <= 'd0;
end
else if (candi8_valid_i) begin
sp8_cnt <= sp8_cnt + 'd1;
end
end
always @(*) begin
case(sp8_cnt)
3'd0: sp8_cur = cur_pixel0;
3'd1: sp8_cur = cur_pixel1;
3'd2: sp8_cur = cur_pixel2;
3'd3: sp8_cur = cur_pixel3;
3'd4: sp8_cur = cur_pixel4;
3'd5: sp8_cur = cur_pixel5;
3'd6: sp8_cur = cur_pixel6;
3'd7: sp8_cur = cur_pixel7;
endcase
end
fme_satd_8x8 sp8(
.clk (clk),
.rstn (rstn),
.cur_p0_i(sp8_cur[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.cur_p1_i(sp8_cur[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.cur_p2_i(sp8_cur[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.cur_p3_i(sp8_cur[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.cur_p4_i(sp8_cur[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.cur_p5_i(sp8_cur[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.cur_p6_i(sp8_cur[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.cur_p7_i(sp8_cur[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.sp_valid_i(candi8_valid_i),
.sp0_i(candi8_pixles_i[8*`PIXEL_WIDTH-1:7*`PIXEL_WIDTH]),
.sp1_i(candi8_pixles_i[7*`PIXEL_WIDTH-1:6*`PIXEL_WIDTH]),
.sp2_i(candi8_pixles_i[6*`PIXEL_WIDTH-1:5*`PIXEL_WIDTH]),
.sp3_i(candi8_pixles_i[5*`PIXEL_WIDTH-1:4*`PIXEL_WIDTH]),
.sp4_i(candi8_pixles_i[4*`PIXEL_WIDTH-1:3*`PIXEL_WIDTH]),
.sp5_i(candi8_pixles_i[3*`PIXEL_WIDTH-1:2*`PIXEL_WIDTH]),
.sp6_i(candi8_pixles_i[2*`PIXEL_WIDTH-1:1*`PIXEL_WIDTH]),
.sp7_i(candi8_pixles_i[1*`PIXEL_WIDTH-1:0*`PIXEL_WIDTH]),
.satd_8x8_o(sp8_satd),
.satd_8x8_valid_o(satd_valid_o)
);
/*
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
satd8_o <= 'd0;
end
else if (sp8_valid) begin
satd8_o <= sp8_satd;
end
end
*/
endmodule
|
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "../afu_defines.vh"
module fthread #(parameter AFU_OPERATOR = `UNDEF_AFU,
parameter MAX_FTHREAD_CONFIG_CLS = 2,
parameter USER_RD_TAG = `AFU_TAG,
parameter USER_WR_TAG = `AFU_TAG,
parameter USER_AFU_PARAMETER1 = 1,
parameter USER_AFU_PARAMETER2 = 1) (
input wire clk,
input wire Clk_400,
input wire rst_n,
/// fthread <--> scheduler
input wire cmd_valid,
input wire [`CMD_LINE_WIDTH-1:0] cmd_line,
output wire fthread_job_done,
/// fthread <--> arbiter
//-------------- read interface
output wire tx_rd_valid,
output wire [67:0] tx_rd_hdr,
input wire tx_rd_ready,
input wire rx_rd_valid,
input wire [`FTHREAD_TAG-1:0] rx_rd_tag,
input wire [511:0] rx_data,
//-------------- write interface
output wire [71:0] tx_wr_hdr,
output wire [511:0] tx_data,
output wire tx_wr_valid,
input wire tx_wr_ready,
input wire [`FTHREAD_TAG-1:0] rx_wr_tag,
input wire rx_wr_valid,
//------------------------ Pipeline Interfaces ---------------------//
// Left Pipe
output wire left_pipe_tx_rd_valid,
output wire [`IF_TAG-1:0] left_pipe_tx_rd_tag,
input wire left_pipe_tx_rd_ready,
input wire left_pipe_rx_rd_valid,
input wire [`IF_TAG-1:0] left_pipe_rx_rd_tag,
input wire [511:0] left_pipe_rx_data,
output wire left_pipe_rx_rd_ready,
// Right Pipe
input wire right_pipe_tx_rd_valid,
input wire [`IF_TAG-1:0] right_pipe_tx_rd_tag,
output wire right_pipe_tx_rd_ready,
output wire right_pipe_rx_rd_valid,
output wire [`IF_TAG-1:0] right_pipe_rx_rd_tag,
output wire [511:0] right_pipe_rx_data,
input wire right_pipe_rx_rd_ready
);
wire start_um;
wire [(MAX_FTHREAD_CONFIG_CLS*512)-1:0] um_params;
wire um_done;
wire [`NUM_USER_STATE_COUNTERS*32-1:0] um_state_counters;
wire um_state_counters_valid;
// User Module TX RD
wire [57:0] um_tx_rd_addr;
wire [USER_RD_TAG-1:0] um_tx_rd_tag;
wire um_tx_rd_valid;
wire um_tx_rd_ready;
// User Module TX WR
wire [57:0] um_tx_wr_addr;
wire [USER_WR_TAG-1:0] um_tx_wr_tag;
wire um_tx_wr_valid;
wire [511:0] um_tx_data;
wire um_tx_wr_ready;
// User Module RX RD
wire [USER_RD_TAG-1:0] um_rx_rd_tag;
wire [511:0] um_rx_data;
wire um_rx_rd_valid;
wire um_rx_rd_ready;
// User Module RX WR
wire um_rx_wr_valid;
wire [USER_WR_TAG-1:0] um_rx_wr_tag;
wire reset_user_logic;
reg afu_rst_n = 0;
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// FThread Controller ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
FThread_controller #(.MAX_NUM_CONFIG_CL(MAX_FTHREAD_CONFIG_CLS),
.USER_RD_TAG(USER_RD_TAG),
.USER_WR_TAG(USER_WR_TAG)
)
FThread_controller(
.clk (clk),
.rst_n (rst_n),
//--------------- fthread <--> scheduler
.cmd_valid (cmd_valid),
.cmd_line (cmd_line),
.fthread_job_done (fthread_job_done),
.reset_user_logic (reset_user_logic),
//--------------- fthread <--> arbiter
//- TX RD, RX RD
.tx_rd_valid (tx_rd_valid),
.tx_rd_hdr (tx_rd_hdr),
.tx_rd_ready (tx_rd_ready),
.rx_rd_valid (rx_rd_valid),
.rx_rd_tag (rx_rd_tag),
.rx_data (rx_data),
//- TX WR, RX WR
.tx_wr_hdr (tx_wr_hdr),
.tx_data (tx_data),
.tx_wr_valid (tx_wr_valid),
.tx_wr_ready (tx_wr_ready),
.rx_wr_tag (rx_wr_tag),
.rx_wr_valid (rx_wr_valid),
//------------------------ Pipeline Interfaces ---------------------//
// Left Pipe
.left_pipe_tx_rd_valid (left_pipe_tx_rd_valid),
.left_pipe_tx_rd_tag (left_pipe_tx_rd_tag),
.left_pipe_tx_rd_ready (left_pipe_tx_rd_ready),
.left_pipe_rx_rd_valid (left_pipe_rx_rd_valid),
.left_pipe_rx_rd_tag (left_pipe_rx_rd_tag),
.left_pipe_rx_data (left_pipe_rx_data),
.left_pipe_rx_rd_ready (left_pipe_rx_rd_ready),
// Right Pipe
.right_pipe_tx_rd_valid (right_pipe_tx_rd_valid),
.right_pipe_tx_rd_tag (right_pipe_tx_rd_tag),
.right_pipe_tx_rd_ready (right_pipe_tx_rd_ready),
.right_pipe_rx_rd_valid (right_pipe_rx_rd_valid),
.right_pipe_rx_rd_tag (right_pipe_rx_rd_tag),
.right_pipe_rx_data (right_pipe_rx_data),
.right_pipe_rx_rd_ready (right_pipe_rx_rd_ready),
//------------------------ User Module interface
.start_um (start_um),
.um_params (um_params),
.um_done (um_done),
.um_state_counters (um_state_counters),
.um_state_counters_valid (um_state_counters_valid),
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag)
);
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// User AFU ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
afu_rst_n <= rst_n & ~reset_user_logic;
end
AFU #(.AFU_OPERATOR(AFU_OPERATOR),
.MAX_AFU_CONFIG_WIDTH(MAX_FTHREAD_CONFIG_CLS*512),
.USER_RD_TAG(USER_RD_TAG),
.USER_WR_TAG(USER_WR_TAG),
.USER_AFU_PARAMETER1(USER_AFU_PARAMETER1),
.USER_AFU_PARAMETER2(USER_AFU_PARAMETER2)
)
AFU(
.clk (clk),
.Clk_400 (Clk_400),
.rst_n (afu_rst_n ),
//-------------------------------------------------//
.start_um (start_um),
.um_params (um_params),
.um_done (um_done),
.um_state_counters (um_state_counters),
.um_state_counters_valid (um_state_counters_valid),
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag)
);
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_quiescent_state (clock, reset, enable, state_expr, check_value, sample_event, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input sample_event;
input [width-1:0] state_expr, check_value;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_QUIESCENT_STATE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_quiescent_state_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_quiescent_state_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_quiescent_state_psl_logic.v"
`else
`endmodule // ovl_quiescent_state
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 30.06.2017 11:21:41
// Design Name:
// Module Name: memoryaccess
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: I'll design this hardware while imagining that it is for
// a pipelined processor. To make it single-cycle, I'll just instantiate each
// module without a register and use continuous assignment to connect the inputs
// with the outputs of the previous segment. This will make it easier to adapt
// code.
//
// Instantialising ALUResultsIn with A and also using CA to link ALUResultsOut
// and ALUResultsIn might not. I will have to edit if the implementation doesn't
// work and/or the simulation doesn't work.
//////////////////////////////////////////////////////////////////////////////////
module memoryaccess(
output [31:0] ReadDataM, ALUResultOut, PCBranchM2,
output [4:0] WriteRegM2,
output RegWriteM2, MemToRegM2, PCSrcM,
input [31:0] WriteDataM, ALUResultIn, PCBranchM1,
input [4:0] WriteRegM1,
input BranchM, MemWriteM, MemToRegM1, RegWriteM1, ZerowireM, clk
);
dmem dmem_mem(
.RD( ReadDataM ),
.A( ALUResultIn ),
.WD( WriteDataM ),
.WE( MemWriteM ),
.clk( clk )
);
assign PCSrcM = BranchM & ZerowireM;
//Send signals to next section
assign ALUResultOut = ALUResultIn;
assign WriteRegM2 = WriteRegM1;
assign PCBranchM2 = PCBranchM1;
assign MemToRegM2 = MemToRegM1;
assign RegWriteM2 = RegWriteM1;
endmodule
|
module moore_fsm ( input wire clk,
input wire rst,
input wire i_input,
output reg o_output,
output wire [2:0] o_current_state,
output wire [2:0] o_next_state
);
reg [2:0] current_state;
reg [2:0] next_state;
// Input value enumerations (constants)
localparam i_val_a = 1'b0;
localparam i_val_b = 1'b1;
// State assignment (constants)
localparam STATE_U = 3'b000;
localparam STATE_V = 3'b001;
localparam STATE_W = 3'b010;
localparam STATE_X = 3'b011;
localparam STATE_Y = 3'b100;
localparam STATE_Z = 3'b101;
// Current state s(k) = delay[s(k+1)], where s(k+1) = next state
always @ ( posedge clk, posedge rst ) begin
if ( rst == 1'b1 ) begin
current_state <= 3'b0;
end else if ( clk == 1'b1) begin
current_state <= next_state;
end
end
assign o_current_state = current_state;
assign o_next_state = next_state;
// Next state s(k+1) = f[i(k), s(k)], where i(k) = current input, s(k) = current state, k = current clock cycle
always @ ( * ) begin
case (current_state)
STATE_U: begin
if (i_input == i_val_a) begin
next_state = STATE_Z;
end else if (i_input == i_val_b) begin
next_state = STATE_W;
end
end
STATE_V: begin
if (i_input == i_val_a) begin
next_state = STATE_Z;
end else if (i_input == i_val_b) begin
next_state = STATE_W;
end
end
STATE_W: begin
if (i_input == i_val_a) begin
next_state = STATE_X;
end else if (i_input == i_val_b) begin
next_state = STATE_U;
end
end
STATE_X: begin
if (i_input == i_val_a) begin
next_state = STATE_Y;
end else if (i_input == i_val_b) begin
next_state = STATE_X;
end
end
STATE_Y: begin
if (i_input == i_val_a) begin
next_state = STATE_V;
end else if (i_input == i_val_b) begin
next_state = STATE_Y;
end
end
STATE_Z: begin
if (i_input == i_val_a) begin
next_state = STATE_Y;
end else if (i_input == i_val_b) begin
next_state = STATE_X;
end
end
default: begin
// unreachable states. go back to proper state
next_state = STATE_U;
end
endcase
end
// Current output O(k) = g[s(k)], where s(k) = current state, k = current clock cycle
always @ ( * ) begin
case (current_state)
STATE_U: begin
o_output = 1'b1;
end
STATE_V: begin
o_output = 1'b0;
end
STATE_W: begin
o_output = 1'b0;
end
STATE_X: begin
o_output = 1'b0;
end
STATE_Y: begin
o_output = 1'b1;
end
STATE_Z: begin
o_output = 1'b1;
end
default: begin
// unreachable states
o_output = 1'b0;
end
endcase
end
endmodule //moore_fsm
|
simulator language=verilog
// This File is part of gnucap-geda
// (C) 2012 Felix Salfelder
// GPLv3 or later
// mapping geda-symbols to actual devices
// "analog" section
module CAPACITOR(1 2);
parameter value=1;
capacitor #(.c(value)) c(1,2);
endmodule
hidemodule CAPACITOR
module POLARIZED_CAPACITOR(p n);
// nothing yet
endmodule
hidemodule POLARIZED_CAPACITOR
module RESISTOR(1 2);
parameter value=1;
resistor #(.r(value)) r(1,2);
endmodule
hidemodule RESISTOR
module BATTERY(n p);
parameter value=1;
vsource #(.dc(value)) v(n,p);
endmodule
hidemodule BATTERY
module VOLTAGE_SOURCE(1 2);
parameter value=1;
vsource #(.dc(value)) v(1 2);
endmodule
hidemodule VOLTAGE_SOURCE
module CURRENT_SOURCE(1 2);
parameter value=1;
isource #(.dc(value)) i(1 2);
endmodule
hidemodule CURRENT_SOURCE
module BC547(1 2 3 4);
// nothing yet
endmodule
hidemodule BC557
module TRANSFORMER(1 2 3 4 5 6 7);
// not yet
endmodule
hidemodule TRANSFORMER
module NMOS_TRANSISTOR(D G S B);
paramset cmosn_local nmos;
.level=1; .kp=41.5964u; .vto=0.8; .gamma=0.863074; .phi=0.6; .lambda=.01;
.tox=41.8n; .nsub=15.3142E+15; .nss=1.E+12; .xj=400.n; .uo=503.521; .tpg=1;
.fc=0.5; .pb=0.7; .cj=384.4u; .mj=0.4884; .cjsw=527.2p; .mjsw=0.3002; .js=0.;
.rsh=0.; .cbd=0.; .cbs=0.; .cgso=218.971p; .cgdo=218.971p; .cgbo=0.;
.ld=265.073n;
endparamset
parameter l
parameter w
cmosn_local #(.l(l), .w(w)) m(D,G,S,B);
endmodule
hidemodule NMOS_TRANSISTOR
module PMOS_TRANSISTOR(D G S B);
paramset local_cmosp pmos;
.level=1; .vto=-0.8; .kp= 41.5964u; .gamma= 0.863074; .phi= 0.6; .rd= 0.;
.rs= 0.; .cbd= 0.; .cbs= 0.; .is= 0; .pb= 0.7; .cgso= 218.971p;
.cgdo=218.971p; .cgbo= 0.; .rsh= 0.; .cj= 384.4u; .mj= 0.4884; .cjsw= 527.2p;
.mjsw= 0.3002; .js= 0.; .tox= 41.8n; .nsub= 15.3142E+15; .nss= 1.E+12; .tpg=1;
.xj= 400.n; .ld= 265.073n; .uo= 503.521; .kf= 0.; .af= 1.; .fc= 0.5;
.lambda=.01;
endparamset
parameter l
parameter w
local_cmosp #(.l(l), .w(w)) m(D,G,S,B);
endmodule
hidemodule PMOS_TRANSISTOR
module NPN_TRANSISTOR(C B E);
// later..
endmodule
hidemodule NPN_TRANSISTOR
module LED(CATHODE, ANODE);
// nothing
endmodule
hidemodule LED
simulator lang=acs
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
reg fire_2state;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_2state <= 1'b0;
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not FALSE");
fire_2state <= ovl_fire_2state_f(property_type);
end
else begin
fire_2state <= 1'b0;
end
end
end
assign fire_2state_1 = (test_expr == 1'b1);
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
reg fire_xcheck_1;
reg fire_xcheck;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_xcheck <= 1'b0;
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
fire_xcheck <= ovl_fire_xcheck_f(property_type);
end
else begin
fire_xcheck <= 1'b0;
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`else
wire fire_2state = 1'b0;
wire fire_xcheck = 1'b0;
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
// No coverage for this OVL
wire fire_cover = 1'b0;
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_TB_V
`define SKY130_FD_SC_MS__NAND4B_TB_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand4b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_ms__nand4b dut (.A_N(A_N), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/02/2013 10:51:56 PM
// Design Name:
// Module Name: tag_manager
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tag_manager # (
parameter TCQ = 1,
parameter RAM_ADDR_BITS = 5
)(
input clk,
input reset_n,
input tag_mang_write_en,
input [2:0] tag_mang_tc_wr, //[15:0]
input [2:0] tag_mang_attr_wr, //[15:0]
input [15:0] tag_mang_requester_id_wr, //[15:0]
input [6:0] tag_mang_lower_addr_wr, //[6:0]
input tag_mang_completer_func_wr, //[0:0]
input [7:0] tag_mang_tag_wr, //[7:0]
input [3:0] tag_mang_first_be_wr, //[2:0]
input tag_mang_read_en,
output [2:0] tag_mang_tc_rd, //[15:0]
output [2:0] tag_mang_attr_rd, //[15:0]
output [15:0] tag_mang_requester_id_rd, //[15:0]
output [6:0] tag_mang_lower_addr_rd, //[6:0]
output tag_mang_completer_func_rd, //[0:0]
output [7:0] tag_mang_tag_rd, //[7:0]
output [3:0] tag_mang_first_be_rd //[2:0]
);
reg [RAM_ADDR_BITS-1:0] tag_mang_write_id;
reg [RAM_ADDR_BITS-1:0] tag_mang_read_id;
always @( posedge clk )
if ( !reset_n )
tag_mang_write_id <= #TCQ 1;
else if ( tag_mang_write_en )
tag_mang_write_id <= #TCQ tag_mang_write_id + 1;
always @( posedge clk )
if ( !reset_n )
tag_mang_read_id <= #TCQ 0;
else if ( tag_mang_read_en )
tag_mang_read_id <= #TCQ tag_mang_read_id + 1;
localparam RAM_WIDTH = 42;
(* RAM_STYLE="distributed" *)
reg [RAM_WIDTH-1:0] tag_storage [(2**RAM_ADDR_BITS)-1:0];
wire [RAM_WIDTH-1:0] completion_data;
always @(posedge clk)
if (tag_mang_write_en)
tag_storage[tag_mang_write_id] <= #TCQ { tag_mang_attr_wr, tag_mang_tc_wr, tag_mang_requester_id_wr, tag_mang_lower_addr_wr, tag_mang_completer_func_wr, tag_mang_tag_wr, tag_mang_first_be_wr};
assign completion_data = tag_storage[tag_mang_read_id];
assign tag_mang_attr_rd = completion_data[41:39];
assign tag_mang_tc_rd = completion_data[38:36];
assign tag_mang_requester_id_rd = completion_data[35:20]; //[15:0]
assign tag_mang_lower_addr_rd = completion_data[19:13]; //[6:0]
assign tag_mang_completer_func_rd = completion_data[12]; //[0:0]
assign tag_mang_tag_rd = completion_data[11:4]; //[7:0]
assign tag_mang_first_be_rd = completion_data[3:0]; //[2:0]
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCON_TB_V
`define SKY130_FD_SC_HD__FAHCON_TB_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__fahcon.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CI;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT_N;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CI = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CI = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 CI = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 CI = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 CI = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 CI = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__fahcon dut (.A(A), .B(B), .CI(CI), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT_N(COUT_N), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCON_TB_V
|
package mypackage;
bit [7:0] pkg_addr;
bit [7:0] pkg_data;
endpackage
module times ();
time x;
initial x = 33ns; // Note no space
endmodule : times
interface itf #(parameter num_of_cli = 0);
logic blabla;
logic [7:0] addr, data[9];
modport Master(input data, date_delayed, output addr);
endinterface : itf
module test (
itf whole_int,
itf.test modported_int,
input logic clk, rst,
input logic d_in,
output logic d_out
);
import mypackage::*;
logic d_int;
logic [7:0] data_, bork[2];
assign d_int = d_in + pkg_data;
assign modported_int.data = data_;
always_ff @(posedge clk or negedge rst) begin
if (~rst) d_out <= '0;
else d_out <= d_int;
end
property p1;
@(posedge clk)
disable iff(!rst)
$rose(d_int) |-> ##1 d_int;
endproperty
//a1: assert property(p1) else $warning("\nProperty violated\n");
c1: cover property(p1) $display("\np1_cover\n");
endmodule : test
// Different ways of declaring pins/vars
module line49_diff_pins1 (
input in_nw, // Input, no type
input [1:0] in_vec[2:0], // Input, implicit
input in_nvec, // Isn't vectorized
output logic out_logic, // Output and var
output out_also_logic // "logic" sticks
);
endmodule
module line49_diff_pins2 (in2_nw, in2_vec, out2reg);
input in2_nw;
input [1:0] in2_vec [2:0];
output reg out2_reg;
input signed in2_signed;
var var1_imp;
var [1:0] var1_imp_vec [2:0];
var reg var1_imp_reg;
var logic var1_imp_logic;
endmodule
program automatic first_prog;
int i;
endprogram
// Importing
package imp_test_pkg;
typedef logic [7:0] byte_t;
typedef logic [15:0] word_t;
function afunc(integer w); afunc=0; endfunction
endpackage
module imp_test_mod;
import imp_test_pkg::byte_t;
byte_t some_byte;
endmodule
module imp_test_mod2;
import imp_test_pkg::*;
word_t some_word;
endmodule
module imp_test_mod3
( input imp_test_pkg::word_t wordin );
localparam FROM_FUNC = imp_test_pkg::afunc(1);
endmodule
module var_unnamed_block;
initial begin
integer var_in_unnamed;
end
endmodule
module cell_with_typeparam;
addr #(.PARAMTYPE(integer)) acell ();
endmodule
module arrayed_wire;
wire [3:0][7:0] n2;
endmodule
task empty_task; // sv design book
endtask
task empty_task2; // sv design book
integer i;
endtask
task check_casts;
typedef integer integer_t;
sum = a + integer '(3);
sum = a + integer_t '(3);
sum = a + 10'(3);
endtask
module comma_assign;
int n[1:2][1:3] = '{'{0,1,2}, '{3{4}}};
endmodule
task typed_pattern;
typedef int triple [1:3];
$mydisplay(triple'{0,1,2});
endtask
virtual class VclassWCopy;
extern function new();
virtual function VclassWCopy copy(input VclassWCopy src=null);
endfunction
endclass : VclassWCopy
function VclassWCopy::new();
endfunction : new
typedef class FwdClass;
function bit [3:0] FwdClass::ffunc (bit [3:0] in);
ffunc = in;
endfunction : ffunc
function VclassWCopy VclassWCopy::copy
(input VclassWCopy to);
dst = new();
endfunction : copy
task foreach_memref;
bit [0:52] [7:0] mem;
// It's *not* legal according to the grammar to have dotted/package ids here
foreach (mem[i]) $write("i=%x ", mem[i]); $display;
endtask
typedef class PreTypedefedClass;
class PreTypedefedClass;
extern function new();
endclass
typedef class PreTypedefedClass;
class NewInNew;
function new;
s_self = new;
endfunction : new
endclass
// std package
class TryStd;
semaphore s1;
std::semaphore s2;
mailbox #(integer) m1;
std::mailbox m2;
process p1;
std::process p2;
endclass
module cg_test1;
covergroup counter1 @ (posedge cyc);
cyc_bined : coverpoint cyc {
bins zero = {0};
bins low = {1,5};
bins mid = {[5:$]};
}
value_and_toggle:
cross cyc_value, toggle;
endgroup
endmodule
task randomize_dotted();
int vbl;
assert(vbl.randomize());
endtask
module prop_parens;
LABEL: cover property (@(posedge clk) ((foo[3:0] == 4'h0) & bar));
endmodule
class this_dot_tests;
task ass;
this.super.foo = this.bar;
endtask
endclass
module sized_out
#( parameter SZ = 4 )
( output logic [SZ-1:0] o_sized );
endmodule
class solve_size;
rand byte arrayed[];
rand bit b;
// The dot below doesn't seem legal according to grammar, but
// the intent makes sense, and it appears in the VMM
constraint solve_a_b { solve arrayed.size before b; }
endclass
class vmm_stuff;
task examples;
void'(this.a.funccall(x));
this.a.taskcall();
super.new(name2);
endtask
extern static local function bit foo1();
extern virtual protected function void foo2();
protected static string foo3;
extern function bit foo4();
static local bit foo5[string];
endclass
class vmm_cl_func_colon;
typedef enum int unsigned {FIRM} restart_e;
function void do_all(vmm_cl_func_colon::restart_e kind = vmm_cl_func_colon::FIRM);
endfunction
extern function int uses_class_type();
endclass
class vmm_cl_subenv;
extern protected virtual task do_reset(vmm_cl_func_colon::restart_e kind = vmm_cl_func_colon::FIRM);
endclass
task empty_comma;
extracomma1(,);
extracomma2("a",);
extracomma3("a",,"c");
extracomma4(,"b");
endtask
task vmm_more;
file_is_a_string(`__FILE__,`__LINE__);
foreach(this.text[i]) begin $display("%s\n", this.text[i]); end
// Not part of 1800-2005 grammar, but likely in 1800-2009
queue = '{};
-> this.item_taken;
endtask
// Extern Functions/tasks when defined must scope to the class they're in to get appropriate types
function int vmm_cl_func_colon::uses_class_type(restart_e note_uses_class_type);
var restart_e also_uses_class_type;
endfunction
module hidden_checks;
typedef int T;
sub (.T(123)); // Different T
task hidden;
typedef bit T; // Different T
endtask
endmodule
typedef struct packed signed {
rand int m_a;
bit [7:0] m_b;
} t_bug91;
t_bug91 v_bug91;
module bug98(interfacex x_if);
h inst_h(.push(x_if.pop));
endmodule
module bugas;
initial begin
ASSERT_CHK: assert (0) else $error("%m -- not allowed %d", 0);
end
endmodule
typedef enum [2:0] { ENUM_RANGED_VALUE } enum_ranged_t;
typedef struct packed { logic val; } t_bug202_struct;
typedef union packed { logic val; } t_bug202_union;
class ln288;
extern virtual function string extvirtstr;
extern virtual task extvirttask;
endclass
class cl_to_init;
extern function new();
extern static function cl_to_init init();
endclass
function cl_to_init cl_to_init::init();
endfunction
function cl_to_init::new();
endfunction
cl_to_init cl_inited = cl_to_init::init();
// pure virtual functions have no endfunction.
virtual class pure_virt_func_class;
pure virtual function string pure_virt_func();
pure virtual task pure_virt_task();
endclass
class extend_base;
typedef enum { EN_A, EN_B } base_enum;
virtual function extend_base create(); return null; endfunction
endclass
class extended extends extend_base;
typedef base_enum be_t; // type must come from base class
virtual function int create (); // Must override base's create
be_t mye;
endfunction
endclass
task rand_with_ln320();
if (!randomize(v) with { v > 0 && v < maxval; }) begin end
if (randomize(null)) begin end
endtask
task apply_request(data_req, input bit randomize = 1);
if (randomize == 1) begin
data_req.randomize(); // Generic method, not std::randomize
end
endtask
task foreach_class_scope_ln330;
foreach (extended::some_array[i,j]) begin end
endtask
module clkif_334;
always @(posedge top.clk iff !top.clken_l) begin end
endmodule
module gen_ln338;
generate
case (P)
32'b0: initial begin end
default: initial begin end
endcase
endgenerate
endmodule
module par_packed;
parameter logic [31:0] P1 [3:0] = '{ 1, 2, 3, 4 } ; // unpacked array
wire struct packed { logic ecc; logic [7:0] data; } memsig;
endmodule
module not_a_bug315;
typedef int supply_net_t;
input int i;
input imp_test_pkg::byte_t i;
input supply_net_t bug316;
endmodule
module bins_bracket;
parameter N = 2;
covergroup cg_debitor @(posedge eclk);
count: coverpoint count iff (erst_n) {
// 'std' overrides std:: package, which confuses VP
//bins std[] = { [0:N] };
}
endgroup
endmodule
virtual class ovm_void;
endclass
virtual class ovm_port_base #(type IF=ovm_void) extends ovm_void;
endclass
virtual class uvm_build_phase #(type BASE=ovm_void) extends BASE;
static const string type_name = "uvm_build_phase";
endclass
class bug627sub;
endclass
class bug627 #(type TYPE=bug627sub);
typedef TYPE types_t[$];
static function types_t f();
$display("%s", { TYPE::type_name });
return types;
endfunction
endclass
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "system_xlconcat_0_0,xlconcat,{}" *)
(* CORE_GENERATION_INFO = "system_xlconcat_0_0,xlconcat,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_BLACKBOX_V
`define SKY130_FD_SC_MS__BUF_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__buf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:40:50 03/07/2016
// Design Name: Modificacion_Ciclo_Trabajo
// Module Name: D:/TEC/I 2016/Lab Digitales/Proyecto I/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales/TB_CT.v
// Project Name: PRIMER_PROYECTO
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Modificacion_Ciclo_Trabajo
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_CT;
// Inputs
reg clk_100MHz;
reg clk_de_trabajo;
reg rst;
reg up;
reg down;
reg chip_select;
// Outputs
wire signal_out;
wire [3:0] ciclo_actual;
// Instantiate the Unit Under Test (UUT)
Modificacion_Ciclo_Trabajo uut (
.clk_100MHz(clk_100MHz),
.clk_de_trabajo(clk_de_trabajo),
.rst(rst),
.up(up),
.down(down),
.chip_select(chip_select),
.signal_out(signal_out),
.ciclo_actual(ciclo_actual)
);
initial begin
forever #5 clk_100MHz = ~clk_100MHz;
end
initial begin
forever #10 clk_de_trabajo = ~clk_de_trabajo;
end
initial begin
// Initialize Inputs
clk_100MHz = 0;
clk_de_trabajo = 0;
rst = 1;
up = 0;
down = 0;
chip_select = 1;
// Wait 100 ns for global reset to finish
#10;
rst = 0;
/*
#10
up = 1;
#50
up = 0;
*/
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX4_TB_V
`define SKY130_FD_SC_LP__MUX4_TB_V
/**
* mux4: 4-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux4.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A0 = 1'b1;
#240 A1 = 1'b1;
#260 A2 = 1'b1;
#280 A3 = 1'b1;
#300 S0 = 1'b1;
#320 S1 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A0 = 1'b0;
#440 A1 = 1'b0;
#460 A2 = 1'b0;
#480 A3 = 1'b0;
#500 S0 = 1'b0;
#520 S1 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 S1 = 1'b1;
#720 S0 = 1'b1;
#740 A3 = 1'b1;
#760 A2 = 1'b1;
#780 A1 = 1'b1;
#800 A0 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 S1 = 1'bx;
#920 S0 = 1'bx;
#940 A3 = 1'bx;
#960 A2 = 1'bx;
#980 A1 = 1'bx;
#1000 A0 = 1'bx;
end
sky130_fd_sc_lp__mux4 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX4_TB_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_sync_clk1_clk2.v ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_sync_clk1_clk2.v,v $
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.3 2001/11/26 10:47:09 mohor
// Crc generation is different for read or write commands. Small synthesys fixes.
//
// Revision 1.2 2001/10/19 11:40:01 mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
//
//
//
//
// synopsys translate_off
`include "rtl/verilog/dbg_interface/timescale.v"
// synopsys translate_on
// FF in clock domain 1 is being set by a signal from the clock domain 2
module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);
parameter Tp = 1;
input clk1;
input clk2;
input reset1;
input reset2;
input set2;
output sync_out;
reg set2_q;
reg set2_q2;
reg set1_q;
reg set1_q2;
reg clear2_q;
reg clear2_q2;
reg sync_out;
wire z;
assign z = set2 | set2_q & ~clear2_q2;
// Latching and synchronizing "set" to clk2
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
set2_q <=#Tp 1'b0;
else
set2_q <=#Tp z;
end
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
set2_q2 <=#Tp 1'b0;
else
set2_q2 <=#Tp set2_q;
end
// Synchronizing "set" to clk1
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
set1_q <=#Tp 1'b0;
else
set1_q <=#Tp set2_q2;
end
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
set1_q2 <=#Tp 1'b0;
else
set1_q2 <=#Tp set1_q;
end
// Synchronizing "clear" to clk2
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
clear2_q <=#Tp 1'b0;
else
clear2_q <=#Tp set1_q2;
end
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
clear2_q2 <=#Tp 1'b0;
else
clear2_q2 <=#Tp clear2_q;
end
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
sync_out <=#Tp 1'b0;
else
sync_out <=#Tp set1_q2;
end
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
// Date : Sat Oct 31 15:04:15 2015
// Host : cascade.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.1 (Maipo)
// Command : write_verilog -force -mode funcsim
// /afs/ece.cmu.edu/usr/rmrobert/Private/18545/Atari7800/Atari7800/Atari7800.srcs/sources_1/ip/BIOS_ROM/BIOS_ROM_funcsim.v
// Design : BIOS_ROM
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "BIOS_ROM,blk_mem_gen_v8_2,{}" *) (* core_generation_info = "BIOS_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=BIOS_ROM.mif,C_INIT_FILE=BIOS_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=4096,C_READ_DEPTH_B=4096,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.535699 mW}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2015.2" *)
(* NotValidForBitStream *)
module BIOS_ROM
(clka,
ena,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [11:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [7:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [7:0]douta;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [7:0]NLW_U0_doutb_UNCONNECTED;
wire [11:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [7:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "12" *)
(* C_ADDRB_WIDTH = "12" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.535699 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "BIOS_ROM.mem" *)
(* C_INIT_FILE_NAME = "BIOS_ROM.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "4096" *)
(* C_READ_DEPTH_B = "4096" *)
(* C_READ_WIDTH_A = "8" *)
(* C_READ_WIDTH_B = "8" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "4096" *)
(* C_WRITE_DEPTH_B = "4096" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "8" *)
(* C_WRITE_WIDTH_B = "8" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
BIOS_ROM_blk_mem_gen_v8_2 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[7:0]),
.eccpipece(1'b0),
.ena(ena),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[11:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rstb(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[11:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[7:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module BIOS_ROM_blk_mem_gen_generic_cstr
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module BIOS_ROM_blk_mem_gen_prim_width
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module BIOS_ROM_blk_mem_gen_prim_wrapper_init
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71 ;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00F46C48),
.INIT_01(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_02(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_11(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_13(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_14(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_15(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_16(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_17(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_18(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_19(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_1F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_20(256'hFFFD2DFFFCADF410CA88EAD0FD80D9FE00BD7FA2FFA0018516A926C24C26C24C),
.INIT_21(256'hF9ADC5D0F029F049FFF8ADCED0FFC9FE09FFF8ADD4F0FFFD0DFFFCADDCF0FFC9),
.INIT_22(256'hA9253620A7B0FFFDCD01E9AE9040C924068DEE85F029FFF9ADBCD003C90B29FF),
.INIT_23(256'hD0F8C088180099FF00B97FA048FAD0CA18009D8A00A2018516A9241B20F08500),
.INIT_24(256'h241B20EED0FFC92406AD2406EE4823FF2068241B20240A8D24A924098D2EA9F5),
.INIT_25(256'h06AD2406CE4823FF2068241B202406CE240A8D24A924098D36A9241220241220),
.INIT_26(256'h8D07291A00ADF110CA1A009D18885D18505D1800BD77A23C8560A9EEB0EEC524),
.INIT_27(256'hA226C24C26B94CF510CA06D01A00DD2000BD77A220009D1A009D04A200A91A00),
.INIT_28(256'h0C10F0C60860FAD0E818003E00A260F0D0E818009D2DD5B9A8FF007D18007D00),
.INIT_29(256'h918E5572B6626792D0E10983F7EECAAB65C76028018516A9FC30F0A5018502A9),
.INIT_2A(256'hEDB890FA94A38734FC17A98473FBD1383108C8AF45063DE6B7592078BE81C5DC),
.INIT_2B(256'hEC352656F6E3E741807FE4BC1011B9A7519D605A6D0DB38253F3D9430A5B3BCE),
.INIT_2C(256'h3E022B7718805805B18C42B01C4A971513A43FA2BFCFEF4652AC9EF47F0CDFD6),
.INIT_2D(256'h93DE0307F94B2EE80E762D2AF819579B9FD88B79144FF1EB8A0B6ECB6A1A49A8),
.INIT_2E(256'hC02F0FAD9689AA391FFE85361E2295A0235EE01DCCA1D2DA7A7DF0B2E5D47E16),
.INIT_2F(256'h54BD9986BB752C7B33D770A6CD7CC1DD2574AE8F401B5F21F5A5C3EA245D2747),
.INIT_30(256'h440164DB3A88C2E94D04E26B69D59C98C61237294EC4615CBA8D4C4832636C9A),
.INIT_31(256'h9DFF80BDE586E48677A2EE0965F7ABC783CAD3C96866B43C7150FD2830F2B56F),
.INIT_32(256'h10CA19019DFED5BDE48677A2F2C6257B20FB8420018502A9F410CA20009D1901),
.INIT_33(256'hE5A426392060F710CA20009D1800BD77A225728DE0A5F2C625E120E385E1A5F7),
.INIT_34(256'h7C8C26748C266E8CC818008DFAD0CA18009D26718D00A9AA48E2651898E184C8),
.INIT_35(256'h09F025D93D2000B9E1A41B30E1C62681CE267CCE2674CE266ECE00A226818C26),
.INIT_36(256'h4020100804020160E08501A9E1856825A44CE83008E0E8266A2026728D2662BD),
.INIT_37(256'h8E268C8E26A98ECA26AC8E268F8E18008E00A2E185E085E4E538E3A526392080),
.INIT_38(256'h2662BD1730E1C6269FEE269AEE2692EE268CEE26A9EE07A2269F8E269A8E2692),
.INIT_39(256'h00A0E286E8E4A660E185E3A526084CEC10CA268820039026A62026AD8D26908D),
.INIT_3A(256'h3007C0F610CA19009D2A1900BD18E2A626598D2662B9C826558D2662B919008C),
.INIT_3B(256'h00691700B90C90F410881800991900791800B918E2A4211F1E1D1C1B1A1960E2),
.INIT_3C(256'h009900E91700B90CB0F410881800991900F91800B938E2A46026794C88170099),
.INIT_3D(256'h6CF89A018616A226A84CC8FBF0E2C46001F01900D91800B900A06026974C8817),
.INIT_3E(256'hF9D02AE0E803950185AA00A904804CF710CA04809DF7D4BD7FA2018502A9FFFC),
.INIT_3F(256'h85EA0F851C851B85118504CB2004CB2001108D9AFD10CA04A22330EA04A90285),
.INIT_40(256'h608DF1188D068502A90C3002241ED0F1128D098502A9093003240430EA00A902),
.INIT_41(256'hFFFFFFFFFFFFFFEAFFFC6C0885FDA9D9300224EA04CB201B8508A92C850ED0F4),
.INIT_42(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_43(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_44(256'hA0F91DBD05A2208500A93C857FA9F48512A9F585FBA9018502A9D87801851DA9),
.INIT_45(256'h0BD080C520808D43A9E510CAEDD0881FD02100D921009927D02000D920009900),
.INIT_46(256'h4C02A0F8804C01A00AD01800CD18008DF8804C04A0F9384C03D00180CD21808D),
.INIT_47(256'hF91DBD05A2F385F92BB9F185F923B9F48407A0F285F08500A9F8804C03A0F880),
.INIT_48(256'h55FF00FB174CD710F4A4F4C6E910CAF1D088CFD0F2D1F291D0D0F0D1F09100A0),
.INIT_49(256'h0330F510F7F0AAA9F8804C00A01F1E1D1C1B1A191823222726252423220F69AA),
.INIT_4A(256'h00C9F9334C03F0F9334C0310DF30E1D000A9E5D0AAC5AA85F9334C03D0F9334C),
.INIT_4B(256'hB3D001AAEC01AA8EBBF056E055A2F9334C0390C6B001C9F9334C03B0CF90D1D0),
.INIT_4C(256'hAAC9984ED00155EC488A55D0AAC968E89ACAA5D00155CC01558CADF0ABC0AAA4),
.INIT_4D(256'h00D92DD055C5000099FF4936D0AAC93AD0AAC500B540D055C0A80100BDAA49D0),
.INIT_4E(256'h85EEA90ED02121CDF09115D0CCC54681F085CCA9F18520A923D020ABDD28D001),
.INIT_4F(256'h5569EDD0AAC9F1F0F310F5B0EA55691855A9F9334CF9EB4C00F06CF185F9A9F0),
.INIT_50(256'hE8AAFFA9CFD0D130D390AAE918D8D0ABC9DCF0DE10E0B055E9E4D0E630E890EA),
.INIT_51(256'hC619D0F0C41DD0F0E6F08523D0C826F08829D0C8A82DD0FFE0311033F0CA36D0),
.INIT_52(256'hB00AFA900AF9334C03F0AAC96A6A6A07D052C92A2A2A18AAA911D0F0C515F0F0),
.INIT_53(256'hC91B295529DDD05FC91B0955A9E5D00AC94AEAB04AED904A0549F2D050C90AF7),
.INIT_54(256'hB8D0FAC968BDD08DC968C2D052E0BAFA584CFA9120CDD04EC91B495509D5D011),
.INIT_55(256'h2485248502100650F3242285EFA50FA23C8543A9488AFA584C6048E6A948F8A9),
.INIT_56(256'h0609F029EFA527850E09F0293C8640A2EC10CA22850FE902B010C910E9382485),
.INIT_57(256'h0290106918EFA511906069F3A51910F1C6268503090F690290406918F0292585),
.INIT_58(256'hE80195AA00A99AFFA2FB144C4068AA68F08502A9F38500A9F185F2A5EF850F69),
.INIT_59(256'h00BD25009DF600BD24009DF500BD23009DF400BD208600A2018502A9F9D02CE0),
.INIT_5A(256'h19849DFCC6BD1F849DFC4BBD2A3000E022009DFBBEBD27009DF800BD26009DF7),
.INIT_5B(256'hD0CA1E849DFE96BD1D849DFE57BD1C849DFE18BD1B849DFDB4BD1A849DFD3DBD),
.INIT_5C(256'h852EA9268556A9258566A9EF8549A9F285F18503A932F00429FFF9AD23064CAB),
.INIT_5D(256'h1F84603C8543A92C851FA9308584A9FC102824FC302824F585FAA9F485AAA927),
.INIT_5E(256'h191B91000048191C8D00004A191C8900004A191C850000BB1F1940840000BB19),
.INIT_5F(256'hAF0000501C2CAF001C2CAF00003E1917A600003E19179D000042191996000046),
.INIT_60(256'h0028192DE8000028192DD5000028192DC2000028192DAF0000501D2CAF001D2C),
.INIT_61(256'hC20000281B2DAF0000281A2DE80000281A2DD50000281A2DC20000281A2DAF00),
.INIT_62(256'h1322050D228500220300220F00220F00220F06220F0000281B2DD50000281B2D),
.INIT_63(256'h22025122003722024B220037220100220F3122052B22052522051F2205192205),
.INIT_64(256'h003722026F22003722026922003722026322003722025D220037220257220037),
.INIT_65(256'h00220F00220F00220F4122018722003722028122003722027B22003722027522),
.INIT_66(256'h1FF87F807F80FF07FC817FE00F7EF8871FC08F7FFC808F7F7C0000220F00220F),
.INIT_67(256'hFF3F0000C000F0FFFFFF3F000C00003E0000807F0000001FFEFF03807F00F0FF),
.INIT_68(256'h0000FF0300C0FF0000FC03FCFFFF3F0000F003F0FFFFFF3F003F0000FC0300FF),
.INIT_69(256'h7F7C00FCC33F00F03F0000FF3F0000FF0300F0FF0300FCC3FF03F03F0000FC0F),
.INIT_6A(256'h1FFEFF07807F00F8FF1FE07F807F80FF01FC837FF00F7EF8871F808F7F7C808F),
.INIT_6B(256'h00FFC03F00FCC3FF00F03F00C03FFF0000FF0300FCF30F00FE0300807F0000F0),
.INIT_6C(256'h03C0FFF03F00FC03F00F00FF03C03F00FF00FC03FC3FF03F00F00FFC0300FF03),
.INIT_6D(256'hF8871F808F7F7C808F7F7C00FC03F03FF03F00FFFFFF3F00FF03F0FFFFFF03FC),
.INIT_6E(256'h0FFE0F00807F0000FC1FFEFF0F807F00FCFF1FC0FF807FC0FF00F8837FF0077E),
.INIT_6F(256'h3FF03F0000FF03FF03FF0300F03FFC03FC0FF03FC0FFFFFFFF00FF03FCFFFFFF),
.INIT_70(256'h8F7F7C808F7F7C00FCC3FF00F03FFC0F0000FC0FFFC3FF0000C0FFFC03FF03F0),
.INIT_71(256'h807F0000FF1FFEFF1F807F00FEFF1F80FF807FC07F00F8837FF0077CF8870F80),
.INIT_72(256'h808F7F7C808F7F7C005555555555555555555555555555555555555555FE3F00),
.INIT_73(256'h00807F00C0FF1FE0FF1F807F00FEFF0100FF817FE03F00F0837FF003FCF8C70F),
.INIT_74(256'h0F808F7F7C808F7F7C00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAFEFF),
.INIT_75(256'hFF01807F00E0FF1F00FE3F807F00FF1F0000FE817FE01F00F0877FF803FCF8C7),
.INIT_76(256'h8158601B0812B4C6C9CA095555555555555555555555555555555555555555FE),
.INIT_77(256'h9306CD8A2DAFECC53B000A8DFAE2E22FBC7C3B847932DC7BA025D9BFD801864B),
.INIT_78(256'hC855510C4723EF20B5066DF7E873D37168A20CCE8CEF3653B26AC4774614A56A),
.INIT_79(256'hBD870A801D8F71B388CC222D3B583CF86305D8C4E276B03867A7203FC458F4FE),
.INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEA3942806846ECD3E270E92359A1),
.INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7F(256'hF933F884F000F72D34383931294328434347FFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module BIOS_ROM_blk_mem_gen_top
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "12" *) (* C_ADDRB_WIDTH = "12" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.535699 mW" *) (* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) (* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) (* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *) (* C_INIT_FILE = "BIOS_ROM.mem" *) (* C_INIT_FILE_NAME = "BIOS_ROM.mif" *)
(* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *) (* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) (* C_READ_DEPTH_A = "4096" *)
(* C_READ_DEPTH_B = "4096" *) (* C_READ_WIDTH_A = "8" *) (* C_READ_WIDTH_B = "8" *)
(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "4096" *)
(* C_WRITE_DEPTH_B = "4096" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "8" *) (* C_WRITE_WIDTH_B = "8" *) (* C_XDEVICEFAMILY = "zynq" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *) (* downgradeipidentifiedwarnings = "yes" *)
module BIOS_ROM_blk_mem_gen_v8_2
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [11:0]addra;
input [7:0]dina;
output [7:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [11:0]addrb;
input [7:0]dinb;
output [7:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [11:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [7:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [7:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [11:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [11:0]addra;
wire [11:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire [7:0]douta;
wire eccpipece;
wire ena;
wire enb;
wire injectdbiterr;
wire injectsbiterr;
wire regcea;
wire regceb;
wire rsta;
wire rstb;
wire s_aclk;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_injectdbiterr;
wire s_axi_injectsbiterr;
wire s_axi_rready;
wire [7:0]s_axi_wdata;
wire s_axi_wlast;
wire [0:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sleep;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
BIOS_ROM_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module BIOS_ROM_blk_mem_gen_v8_2_synth
(douta,
ena,
clka,
addra,
dina,
wea);
output [7:0]douta;
input ena;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire ena;
wire [0:0]wea;
BIOS_ROM_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <[email protected]>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
module counter #(
parameter MAX = 15,
parameter START = 0,
parameter signed INC = 1
) (
input clk,
input reset,
input ce,
output reg [$clog2(MAX+1)-1:0] count = START
);
localparam TCQ = 1;
always @(posedge clk)
if (reset)
count <= #TCQ START;
else if (ce)
count <= #TCQ count + INC;
endmodule
module pipeline_ce_reset #(
parameter STAGES = 0
) (
input clk,
input ce,
input reset,
input i,
output o
);
localparam TCQ = 1;
if (!STAGES)
assign o = i;
else begin
reg [STAGES-1:0] pipeline = 0;
assign o = pipeline[STAGES-1];
always @(posedge clk)
if (reset)
pipeline <= #TCQ pipeline << 1;
else if (ce)
pipeline <= #TCQ (pipeline << 1) | i;
end
endmodule
module pipeline_ce #(
parameter STAGES = 0
) (
input clk,
input ce,
input i,
output o
);
pipeline_ce_reset #(STAGES) u_ce(clk, ce, 1'b0, i, o);
endmodule
module pipeline_reset #(
parameter STAGES = 0
) (
input clk,
input reset,
input i,
output o
);
pipeline_ce_reset #(STAGES) u_ce(clk, 1'b1, reset, i, o);
endmodule
module pipeline #(
parameter STAGES = 0
) (
input clk,
input i,
output o
);
pipeline_ce_reset #(STAGES) u_ce(clk, 1'b1, 1'b0, i, o);
endmodule
module reverse_words #(
parameter M = 4,
parameter WORDS = 1
) (
input [M*WORDS-1:0] in,
output [M*WORDS-1:0] out
);
genvar i;
for (i = 0; i < WORDS; i = i + 1) begin : REV
assign out[i*M+:M] = in[(WORDS-i-1)*M+:M];
end
endmodule
module rotate_right #(
parameter M = 4,
parameter S = 0
) (
input [M-1:0] in,
output [M-1:0] out
);
wire [M*2-1:0] in2 = {in, in};
assign out = in2[S%M+:M];
endmodule
module rotate_left #(
parameter M = 4,
parameter S = 0
) (
input [M-1:0] in,
output [M-1:0] out
);
wire [M*2-1:0] in2 = {in, in};
assign out = in2[M-(S%M)+:M];
endmodule
module mux_one #(
parameter WIDTH = 2,
parameter WIDTH_SZ = $clog2(WIDTH+1)
) (
input [WIDTH-1:0] in,
input [WIDTH_SZ-1:0] sel,
output out
);
assign out = in[sel];
endmodule
module mux_shuffle #(
parameter U = 2,
parameter V = 2
) (
input [U*V-1:0] in,
output [V*U-1:0] out
);
genvar u, v;
generate
for (u = 0; u < U; u = u + 1) begin : _U
for (v = 0; v < V; v = v + 1) begin : _V
assign out[v*U+u] = in[u*V+v];
end
end
endgenerate
endmodule
module mux #(
parameter WIDTH = 2,
parameter BITS = 1,
parameter WIDTH_SZ = $clog2(WIDTH+1)
) (
input [BITS*WIDTH-1:0] in,
input [WIDTH_SZ-1:0] sel,
output [BITS-1:0] out
);
wire [WIDTH*BITS-1:0] shuffled;
mux_shuffle #(WIDTH, BITS) u_mux_shuffle(in, shuffled);
mux_one #(WIDTH) u_mux_one [BITS-1:0] (shuffled, sel, out);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:07:12 12/12/2016
// Design Name:
// Module Name: Controller
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Controller(
input wire clk, clr,
// Keyboard Signal
input wire ps2c, ps2d,
output reg [ 3:0] status,
// VGA signal
output wire hsync, vsync,
output wire [ 9:0] pixel_x, pixel_y,
output reg btn_visible, explode_visible,
output reg signed [31:0] scroll,
output wire video_on,
output wire btn_pos, mycar_pos, explode_pos, game_over_pos, score_pos,
output wire obstacle_pos0, obstacle_pos1, obstacle_pos2, obstacle_pos3, obstacle_pos4,
output wire digit_pos0, digit_pos1, digit_pos2, digit_pos3,
output wire iscollide0, iscollide1, iscollide2, iscollide3, iscollide4,
output wire [16:0] back_addr, side_addr,
output wire [15:0] explode_addr,
output wire [14:0] game_over_addr,
output wire [13:0] btn_addr, score_addr,
output wire [13:0] digit_addr0, digit_addr1, digit_addr2, digit_addr3,
output wire [12:0] mycar_addr,
output wire [12:0] obstacle_addr0, obstacle_addr1, obstacle_addr2, obstacle_addr3, obstacle_addr4,
output wire [3: 0] high_score0, high_score1, high_score2, high_score3
);
// Game status signal declaration
localparam [3:0]
prepare = 4'b1000,
activate = 4'b0100,
pause = 4'b0010,
terminate = 4'b0001;
reg [9:0] mycar_pos_x, mycar_pos_y, explode_pos_x, explode_pos_y;
reg [9:0] obstacle_pos_x [0:4], obstacle_pos_y [0:4];
reg [4:0] num;
reg [31:0] cnt;
reg [24:0] car_on_road;
//=========================================================================
// Reg content: x x x x x _ x x x x x _ x x x x x _ x x x x x _ x x x x x
// Road number: 0 | 1 | 2 | 3 | 4
// Car number : 4 3 2 1 0 | 4 3 2 1 0 | 4 3 2 1 0 | 4 3 2 1 0 | 4 3 2 1 0
//=========================================================================
initial
begin
status <= prepare;
btn_visible <= 1'b0;
explode_visible <= 1'b0;
scroll <= 32'b0;
mycar_pos_x <= 289;
mycar_pos_y <= 384;
num <= 1'b0;
obstacle_pos_x[0] = 101;
obstacle_pos_y[0] = 100;
obstacle_pos_x[1] = 485;
obstacle_pos_y[1] = 100;
obstacle_pos_x[2] = 197;
obstacle_pos_y[2] = 100;
obstacle_pos_x[3] = 293;
obstacle_pos_y[3] = 100;
obstacle_pos_x[4] = 389;
obstacle_pos_y[4] = 100;
car_on_road = 25'b00001_00100_01000_10000_00010;
cnt <= 32'b0;
end
//============================================================================
// vga_test module
//============================================================================
// vga_test debug_unit ( .clk(clk), .clr(clr), .hsync(hsync), .vsync(vsync), .red(red), .green(green), .blue(blue) );
//============================================================================
// Instantiation
//============================================================================
// Instantiate vga_sync circuit
wire clk25m, clk6400, clk200, clk100, clk50;
clkdiv div_unit (.clk(clk), .clr(clr), .clk25m(clk25m), .clk800(clk800), .clk200(clk200), .clk100(clk100), .clk50(clk50));
vga_sync sync_unit (
.clk(clk25m), .clr(clr), .hsync(hsync), .vsync(vsync), .video_on(video_on), .pixel_x(pixel_x), .pixel_y(pixel_y)
);
// Instantiate keyboard circuit
wire [15:0] xkey;
ps2_receiver keyboard (.clk(clk25m), .clr(clr), .ps2c(ps2c), .ps2d(ps2d), .xkey(xkey));
//===========================================================================
// Keyboard
//===========================================================================
// Output the signals we need according to the shift register
reg [3:0] direction;
always @ (posedge clk25m or posedge clr)
begin
if (clr)
begin
status <= prepare;
direction <= 4'b0;
btn_visible <= 1'b0;
end
else
begin
// prepare -> activate
if (xkey[15: 8] != 8'hF0 && xkey[ 7: 0] == 8'h29)
btn_visible <= 1'b1;
else if (xkey[15: 8] == 8'hF0 && xkey[ 7: 0] == 8'h29)
status <= activate;
// activate -> pause
if (xkey[15: 8] != 8'hF0 && xkey[ 7: 0] == 8'h76 && status == activate)
status <= pause;
// pause -> activate
if (xkey[15: 8] != 8'hF0 && xkey[ 7: 0] == 8'h29 && status == pause)
status <= activate;
// activate -> terminate
if (iscollide0 || iscollide1)
status <= terminate;
if (status == activate)
begin
if (xkey[15: 8] != 8'hF0 && xkey[ 7: 0] == 8'h1d)
direction <= 4'b1000; // Up
else if (xkey[15: 8] != 8'hF0 && xkey[ 7: 0] == 8'h1b)
direction <= 4'b0100; // Down
else if (xkey[15: 8] != 8'hF0 && xkey[ 7: 0] == 8'h1c)
direction <= 4'b0010; // Left
else if (xkey[15: 8] != 8'hF0 && xkey[ 7: 0] == 8'h23)
direction <= 4'b0001; // Right
else if (xkey[15: 8] == 8'hF0)
direction <= 4'b0000;
end
end
end
//============================================================================
// Object's properity
//============================================================================
wire [9:0] back_x, back_y, btn_x, btn_y, side_x, side_y, mycar_x, mycar_y, game_over_x, game_over_y, score_x, score_y;
wire [9:0] explode_x, explode_y;
wire [9:0] obstacle_x [0:4], obstacle_y [0:4];
wire [9:0] digit_x [0:3], digit_y [0:3];
wire [10:0] back_xrom, back_yrom, btn_xrom, btn_yrom, side_xrom, side_yrom;
// Background's properties
assign back_x = pixel_x;
assign back_y = pixel_y;
assign back_xrom = {1'b0, back_x[9:1]};
assign back_yrom = {1'b0, back_y[9:1]};
assign back_addr = back_yrom * 320 + back_xrom;
// Start Button's properties
assign btn_x = pixel_x - 252;
assign btn_y = pixel_y - 379;
assign btn_xrom = {1'b0, btn_x[9:1]};
assign btn_yrom = {1'b0, btn_y[9:1]};
assign btn_pos = (pixel_x >= 252) && (pixel_x < 640) && (pixel_y >= 379) && (pixel_y < 480);
assign btn_addr = btn_yrom * 200 + btn_xrom;
// Side's properties
assign side_x = pixel_x;
assign side_y = pixel_y;
assign side_xrom = {1'b0, side_x[9:1]};
assign side_yrom = {1'b0, side_y[9:1]};
assign side_addr = side_yrom * 320 + side_xrom;
// My car's properties
parameter car_width = 60;
parameter car_height = 100;
parameter car_offset_left = 15;
parameter car_offset_right = 5;
assign mycar_x = pixel_x - mycar_pos_x;
assign mycar_y = pixel_y - mycar_pos_y;
assign mycar_pos = (pixel_x >= mycar_pos_x + car_offset_left) &&
(pixel_x < mycar_pos_x + car_width - car_offset_right) &&
(pixel_y >= mycar_pos_y) &&
(pixel_y < mycar_pos_y + car_height);
assign mycar_addr = mycar_y * 60 + mycar_x;
// Obstacles' properties
parameter police_width = 64;
parameter police_height = 100;
parameter police_offset_left = 5;
parameter police_offset_right = 5;
assign obstacle_x[0] = pixel_x - obstacle_pos_x[0];
assign obstacle_y[0] = pixel_y - obstacle_pos_y[0] + police_height;
assign obstacle_pos0 = (pixel_x >= obstacle_pos_x[0] + police_offset_left) &&
(pixel_x < obstacle_pos_x[0] + police_width - police_offset_right) &&
(pixel_y >= {obstacle_pos_y[0] > police_height ? obstacle_pos_y[0] - police_height : 0}) &&
(pixel_y < obstacle_pos_y[0]);
assign obstacle_addr0 = obstacle_y[0] * 64 + obstacle_x[0];
assign obstacle_x[1] = pixel_x - obstacle_pos_x[1];
assign obstacle_y[1] = pixel_y - obstacle_pos_y[1] + police_height;
assign obstacle_pos1 = (pixel_x >= obstacle_pos_x[1] + police_offset_left) &&
(pixel_x < obstacle_pos_x[1] + police_width - police_offset_right) &&
(pixel_y >= {obstacle_pos_y[1] > police_height ? obstacle_pos_y[1] - police_height : 0}) &&
(pixel_y < obstacle_pos_y[1]);
assign obstacle_addr1 = obstacle_y[1] * 64 + obstacle_x[1];
assign obstacle_x[2] = pixel_x - obstacle_pos_x[2];
assign obstacle_y[2] = pixel_y - obstacle_pos_y[2] + car_height;
assign obstacle_pos2 = (pixel_x >= obstacle_pos_x[2] + car_offset_left) &&
(pixel_x < obstacle_pos_x[2] + car_width - car_offset_right) &&
(pixel_y >= {obstacle_pos_y[2] > car_height ? obstacle_pos_y[2] - car_height : 0}) &&
(pixel_y < obstacle_pos_y[2]);
assign obstacle_addr2 = obstacle_y[2] * 60 + obstacle_x[2];
assign obstacle_x[3] = pixel_x - obstacle_pos_x[3];
assign obstacle_y[3] = pixel_y - obstacle_pos_y[3] + car_height;
assign obstacle_pos3 = (pixel_x >= obstacle_pos_x[3] + car_offset_left) &&
(pixel_x < obstacle_pos_x[3] + car_width - car_offset_right) &&
(pixel_y >= {obstacle_pos_y[3] > car_height ? obstacle_pos_y[3] - car_height : 0}) &&
(pixel_y < obstacle_pos_y[3]);
assign obstacle_addr3 = obstacle_y[3] * 60 + obstacle_x[3];
assign obstacle_x[4] = pixel_x - obstacle_pos_x[4];
assign obstacle_y[4] = pixel_y - obstacle_pos_y[4] + car_height;
assign obstacle_pos4 = (pixel_x >= obstacle_pos_x[4] + car_offset_left) &&
(pixel_x < obstacle_pos_x[4] + car_width - car_offset_right) &&
(pixel_y >= {obstacle_pos_y[4] > car_height ? obstacle_pos_y[4] - car_height : 0}) &&
(pixel_y < obstacle_pos_y[4]);
assign obstacle_addr4 = obstacle_y[4] * 60 + obstacle_x[4];
// Explosion's properties
parameter explode_width = 60;
parameter explode_height = 60;
assign explode_x = pixel_x - explode_pos_x;
assign explode_y = pixel_y - explode_pos_y + explode_height * num;
assign explode_pos = (pixel_x >= explode_pos_x) && (pixel_x < explode_pos_x + explode_width) &&
(pixel_y >= explode_pos_y) && (pixel_y < explode_pos_y + explode_height);
assign explode_addr = explode_y * 60 + explode_x;
// Game-Over prompt's properties
assign game_over_x = pixel_x - 160;
assign game_over_y = pixel_y - 120;
assign game_over_pos = (pixel_x >= 160) && (pixel_x < 480) && (pixel_y >= 120) && (pixel_y < 180);
assign game_over_addr = game_over_y * 320 + game_over_x;
// Score's properties
assign score_x = pixel_x - 120;
assign score_y = pixel_y - 240;
assign score_pos = (pixel_x >= 120) && (pixel_x < 320) && (pixel_y >= 240) && (pixel_y < 300);
assign score_addr = score_y * 200 + score_x;
// Digit's properties
wire [3:0] score [0:3];
parameter digit_width = 32;
parameter digit_height = 32;
assign digit_x[0] = pixel_x - (330 + digit_width * 3);
assign digit_y[0] = pixel_y - 260 + digit_height * score[0];
assign digit_pos0 = (pixel_x >= 330 + digit_width * 3) && (pixel_x < 330 + digit_width * 4) && (pixel_y >= 260) && (pixel_y < 260 + digit_height);
assign digit_addr0 = digit_y[0] * 32 + digit_x[0];
assign digit_x[1] = pixel_x - (330 + digit_width * 2);
assign digit_y[1] = pixel_y - 260 + digit_height * score[1];
assign digit_pos1 = (pixel_x >= 330 + digit_width * 2) && (pixel_x < 330 + digit_width * 3) && (pixel_y >= 260) && (pixel_y < 260 + digit_height);
assign digit_addr1 = digit_y[1] * 32 + digit_x[1];
assign digit_x[2] = pixel_x - (330 + digit_width);
assign digit_y[2] = pixel_y - 260 + digit_height * score[2];
assign digit_pos2 = (pixel_x >= 330 + digit_width) && (pixel_x < 330 + digit_width * 2) && (pixel_y >= 260) && (pixel_y < 260 + digit_height);
assign digit_addr2 = digit_y[2] * 32 + digit_x[2];
assign digit_x[3] = pixel_x - 330;
assign digit_y[3] = pixel_y - 260 + digit_height * score[3];
assign digit_pos3 = (pixel_x >= 330) && (pixel_x < 330 + digit_width) && (pixel_y >= 260) && (pixel_y < 260 + digit_height);
assign digit_addr3 = digit_y[3] * 32 + digit_x[3];
//=============================================================================
//Collision detector
//=============================================================================
Detector collision_detector (.mycar_pos_x(mycar_pos_x), .mycar_pos_y(mycar_pos_y),
.obstacle_pos_x0(obstacle_pos_x[0]),
.obstacle_pos_x1(obstacle_pos_x[1]),
.obstacle_pos_x2(obstacle_pos_x[2]),
.obstacle_pos_x3(obstacle_pos_x[3]),
.obstacle_pos_x4(obstacle_pos_x[4]),
.obstacle_pos_y0(obstacle_pos_y[0]),
.obstacle_pos_y1(obstacle_pos_y[1]),
.obstacle_pos_y2(obstacle_pos_y[2]),
.obstacle_pos_y3(obstacle_pos_y[3]),
.obstacle_pos_y4(obstacle_pos_y[4]),
.iscollide0(iscollide0),
.iscollide1(iscollide1),
.iscollide2(iscollide2),
.iscollide3(iscollide3),
.iscollide4(iscollide4)
);
//=============================================================================
// Procedure to deal with the random generation and collision
//=============================================================================
parameter lane_x = 96;
always @ (posedge clk100 or posedge clr)
begin
if (clr)
begin
obstacle_pos_x[0] = 101;
obstacle_pos_y[0] = 100;
obstacle_pos_x[1] = 485;
obstacle_pos_y[1] = 100;
obstacle_pos_x[2] = 197;
obstacle_pos_y[2] = 100;
obstacle_pos_x[3] = 293;
obstacle_pos_y[3] = 100;
obstacle_pos_x[4] = 389;
obstacle_pos_y[4] = 100;
car_on_road = 25'b00001_00100_01000_10000_00010;
cnt <= 32'b0;
explode_visible <= 1'b0;
end
else
begin
if (status == activate)
begin
//=============================================================================
// Random generator
//=============================================================================
if (direction != 4'b0)
cnt <= cnt + 1023;
else
cnt <= cnt + 1;
if (iscollide0 || obstacle_pos_y[0] > 480 + police_height)
begin
// Clear the flag signal
if (car_on_road[ 0] == 1'b1)
car_on_road[ 0] = 1'b0;
if (car_on_road[ 5] == 1'b1)
car_on_road[ 5] = 1'b0;
if (car_on_road[10] == 1'b1)
car_on_road[10] = 1'b0;
if (car_on_road[15] == 1'b1)
car_on_road[15] = 1'b0;
if (car_on_road[20] == 1'b1)
car_on_road[20] = 1'b0;
// Set explosion position signal
if (iscollide0)
begin
explode_pos_x <= mycar_pos_x + (car_width - explode_width) / 2;
explode_pos_y <= mycar_pos_y + (car_height - explode_height) / 2;
explode_visible <= 1'b1;
end
// Recreate the next position and flag signal
if (cnt % 5 == 0 &&
(car_on_road[ 4: 0] == 5'b00010 && obstacle_pos_y[1] > police_height + police_height ||
car_on_road[ 4: 0] == 5'b00000))
begin
obstacle_pos_x[0] = 79 + (lane_x - police_width) / 2;
obstacle_pos_y[0] = 0;
car_on_road[ 0] = 1'b1;
end
else if (cnt % 5 == 1 &&
(car_on_road[ 9: 5] == 5'b00010 && obstacle_pos_y[1] > police_height + police_height ||
car_on_road[ 9: 5] == 5'b00000))
begin
obstacle_pos_x[0] = 79 + (lane_x * 3 - police_width) / 2;
obstacle_pos_y[0] = 0;
car_on_road[ 5] = 1'b1;
end
else if (cnt % 5 == 2 &&
(car_on_road[14:10] == 5'b00010 && obstacle_pos_y[1] > police_height + police_height ||
car_on_road[14:10] == 5'b00000))
begin
obstacle_pos_x[0] = 79 + (lane_x * 5 - police_width) / 2;
obstacle_pos_y[0] = 0;
car_on_road[10] = 1'b1;
end
else if (cnt % 5 == 3 &&
(car_on_road[19:15] == 5'b00010 && obstacle_pos_y[1] > police_height + police_height ||
car_on_road[19:15] == 5'b00000))
begin
obstacle_pos_x[0] = 79 + (lane_x * 7 - police_width) / 2;
obstacle_pos_y[0] = 0;
car_on_road[15] = 1'b1;
end
else if (car_on_road[24:20] == 5'b00010 && obstacle_pos_y[1] > police_height + police_height ||
car_on_road[24:20] == 5'b00000)
begin
obstacle_pos_x[0] = 79 + (lane_x * 9 - police_width) / 2;
obstacle_pos_y[0] = 0;
car_on_road[20] = 1'b1;
end
end
if (iscollide1 || obstacle_pos_y[1] > 480 + police_height)
begin
// Clear the flag signal
if (car_on_road[ 1] == 1'b1)
car_on_road[ 1] = 1'b0;
if (car_on_road[ 6] == 1'b1)
car_on_road[ 6] = 1'b0;
if (car_on_road[11] == 1'b1)
car_on_road[11] = 1'b0;
if (car_on_road[16] == 1'b1)
car_on_road[16] = 1'b0;
if (car_on_road[21] == 1'b1)
car_on_road[21] = 1'b0;
// Set explosion position signal
if (iscollide1)
begin
explode_pos_x <= mycar_pos_x + (car_width - explode_width) / 2;
explode_pos_y <= mycar_pos_y + (car_height - explode_height) / 2;
explode_visible <= 1'b1;
end
// Recreate the next position and flag signal
if (cnt % 5 == 0 &&
(car_on_road[ 4: 0] == 5'b00001 && obstacle_pos_y[0] > police_height + police_height ||
car_on_road[ 4: 0] == 5'b00000))
begin
obstacle_pos_x[1] = 79 + (lane_x - police_width) / 2;
obstacle_pos_y[1] = 0;
car_on_road[ 1] = 1'b1;
end
else if (cnt % 5 == 1 &&
(car_on_road[ 9 :5] == 5'b00001 && obstacle_pos_y[0] > police_height + police_height ||
car_on_road[ 9: 5] == 5'b00000))
begin
obstacle_pos_x[1] = 79 + (lane_x * 3 - police_width) / 2;
obstacle_pos_y[1] = 0;
car_on_road[ 6] = 1'b1;
end
else if (cnt % 5 == 2 &&
(car_on_road[14:10] == 5'b00001 && obstacle_pos_y[0] > police_height + police_height ||
car_on_road[14:10] == 5'b00000))
begin
obstacle_pos_x[1] = 79 + (lane_x * 5 - police_width) / 2;
obstacle_pos_y[1] = 0;
car_on_road[11] = 1'b1;
end
else if (cnt % 5 == 3 &&
(car_on_road[19:15] == 5'b00001 && obstacle_pos_y[0] > police_height + police_height ||
car_on_road[19:15] == 5'b00000))
begin
obstacle_pos_x[1] = 79 + (lane_x * 7 - police_width) / 2;
obstacle_pos_y[1] = 0;
car_on_road[16] = 1'b1;
end
else if (car_on_road[24:20] == 5'b00001 && obstacle_pos_y[0] > police_height + police_height ||
car_on_road[24:20] == 5'b00000)
begin
obstacle_pos_x[1] = 79 + (lane_x * 9 - police_width) / 2;
obstacle_pos_y[1] = 0;
car_on_road[21] = 1'b1;
end
end
if (iscollide2 || obstacle_pos_y[2] > 480 + car_height)
begin
// Clear the flag signal
if (car_on_road[ 2] == 1'b1)
car_on_road[ 2] = 1'b0;
if (car_on_road[ 7] == 1'b1)
car_on_road[ 7] = 1'b0;
if (car_on_road[12] == 1'b1)
car_on_road[12] = 1'b0;
if (car_on_road[17] == 1'b1)
car_on_road[17] = 1'b0;
if (car_on_road[22] == 1'b1)
car_on_road[22] = 1'b0;
// Set explosion position signal
if (iscollide2)
begin
explode_pos_x <= obstacle_pos_x[2] + (car_width - explode_width) / 2;
explode_pos_y <= obstacle_pos_y[2] + (car_height - explode_height) / 2;
explode_visible <= 1'b1;
end
// Recreate the next position and flag signal
if (cnt % 5 == 0 &&
(car_on_road[ 4: 0] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00000))
begin
obstacle_pos_x[2] = 79 + (lane_x - car_width) / 2;
obstacle_pos_y[2] = 0;
car_on_road[ 2] = 1'b1;
end
else if (cnt % 5 == 1 &&
(car_on_road[ 9: 5] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00000))
begin
obstacle_pos_x[2] = 79 + (lane_x * 3 - car_width) / 2;
obstacle_pos_y[2] = 0;
car_on_road[ 7] = 1'b1;
end
else if (cnt % 5 == 2 &&
(car_on_road[14:10] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[14:10] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[14:10] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[14:10] == 5'b00000))
begin
obstacle_pos_x[2] = 79 + (lane_x * 5 - car_width) / 2;
obstacle_pos_y[2] = 0;
car_on_road[12] = 1'b1;
end
else if (cnt % 5 == 3 &&
(car_on_road[19:15] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[19:15] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[19:15] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[19:15] == 5'b00000))
begin
obstacle_pos_x[2] = 79 + (lane_x * 7 - car_width) / 2;
obstacle_pos_y[2] = 0;
car_on_road[17] = 1'b1;
end
else if (car_on_road[24:20] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[24:20] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[24:20] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[24:20] == 5'b00000)
begin
obstacle_pos_x[2] = 79 + (lane_x * 9 - car_width) / 2;
obstacle_pos_y[2] = 0;
car_on_road[22] = 1'b1;
end
end
if (iscollide3 || obstacle_pos_y[3] > 480 + car_height)
begin
// Clear the flag signal
if (car_on_road[ 3] == 1'b1)
car_on_road[ 3] = 1'b0;
if (car_on_road[ 8] == 1'b1)
car_on_road[ 8] = 1'b0;
if (car_on_road[13] == 1'b1)
car_on_road[13] = 1'b0;
if (car_on_road[18] == 1'b1)
car_on_road[18] = 1'b0;
if (car_on_road[23] == 1'b1)
car_on_road[23] = 1'b0;
// Set explosion position signal
if (iscollide3)
begin
explode_pos_x <= obstacle_pos_x[3] + (car_width - explode_width) / 2;
explode_pos_y <= obstacle_pos_y[3] + (car_height - explode_height) / 2;
explode_visible <= 1'b1;
end
// Recreate the next position and flag signal
if (cnt % 5 == 0 &&
(car_on_road[ 4: 0] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00000))
begin
obstacle_pos_x[3] = 79 + (lane_x - car_width) / 2;
obstacle_pos_y[3] = 0;
car_on_road[ 3] = 1'b1;
end
else if (cnt % 5 == 1 &&
(car_on_road[ 9: 5] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00000))
begin
obstacle_pos_x[3] = 79 + (lane_x * 3 - car_width) / 2;
obstacle_pos_y[3] = 0;
car_on_road[ 8] = 1'b1;
end
else if (cnt % 5 == 2 &&
(car_on_road[14:10] == 5'b00001 && obstacle_pos_y[0] > car_height + police_height ||
car_on_road[14:10] == 5'b00010 && obstacle_pos_y[1] > car_height + police_height ||
car_on_road[14:10] == 5'b00100 && obstacle_pos_y[2] > car_height + police_height ||
car_on_road[14:10] == 5'b00000))
begin
obstacle_pos_x[3] = 79 + (lane_x * 5 - car_width) / 2;
obstacle_pos_y[3] = 0;
car_on_road[13] = 1'b1;
end
else if (cnt % 5 == 3 &&
(car_on_road[19:15] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[19:15] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[19:15] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[19:15] == 5'b00000))
begin
obstacle_pos_x[3] = 79 + (lane_x * 7 - car_width) / 2;
obstacle_pos_y[3] = 0;
car_on_road[18] = 1'b1;
end
else if (car_on_road[24:20] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[24:20] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[24:20] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[24:20] == 5'b00000)
begin
obstacle_pos_x[3] = 79 + (lane_x * 9 - car_width) / 2;
obstacle_pos_y[3] = 0;
car_on_road[23] = 1'b1;
end
end
if (iscollide4 || obstacle_pos_y[4] > 480 + car_height)
begin
// Clear the flag signal
if (car_on_road[ 4] == 1'b1)
car_on_road[ 4] = 1'b0;
if (car_on_road[ 9] == 1'b1)
car_on_road[ 9] = 1'b0;
if (car_on_road[14] == 1'b1)
car_on_road[14] = 1'b0;
if (car_on_road[19] == 1'b1)
car_on_road[19] = 1'b0;
if (car_on_road[24] == 1'b1)
car_on_road[24] = 1'b0;
// Set explosion position signal
if (iscollide4)
begin
explode_pos_x <= obstacle_pos_x[4] + (car_width - explode_width) / 2;
explode_pos_y <= obstacle_pos_y[4] + (car_height - explode_height) / 2;
explode_visible <= 1'b1;
end
// Recreate the next position and flag signal
if (cnt % 5 == 0 &&
(car_on_road[ 4: 0] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[ 4: 0] == 5'b00000))
begin
obstacle_pos_x[4] = 79 + (lane_x - car_width) / 2;
obstacle_pos_y[4] = 0;
car_on_road[ 4] = 1'b1;
end
else if (cnt % 5 == 1 &&
(car_on_road[ 9: 5] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[ 9: 5] == 5'b00000))
begin
obstacle_pos_x[4] = 79 + (lane_x * 3 - car_width) / 2;
obstacle_pos_y[4] = 0;
car_on_road[ 9] = 1'b1;
end
else if (cnt % 5 == 2 &&
(car_on_road[14:10] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[14:10] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[14:10] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[14:10] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[14:10] == 5'b00000))
begin
obstacle_pos_x[4] = 79 + (lane_x * 5 - car_width) / 2;
obstacle_pos_y[4] = 0;
car_on_road[14] = 1'b1;
end
else if (cnt % 5 == 3 &&
(car_on_road[19:15] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[19:15] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[19:15] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[19:15] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[19:15] == 5'b00000))
begin
obstacle_pos_x[4] = 79 + (lane_x * 7 - car_width) / 2;
obstacle_pos_y[4] = 0;
car_on_road[19] = 1'b1;
end
else if (car_on_road[24:20] == 5'b00001 && obstacle_pos_y[0] > car_height + car_height ||
car_on_road[24:20] == 5'b00010 && obstacle_pos_y[1] > car_height + car_height ||
car_on_road[24:20] == 5'b00100 && obstacle_pos_y[2] > car_height + car_height ||
car_on_road[24:20] == 5'b01000 && obstacle_pos_y[3] > car_height + car_height ||
car_on_road[24:20] == 5'b00000)
begin
obstacle_pos_x[4] = 79 + (lane_x * 9 - car_width) / 2;
obstacle_pos_y[4] = 0;
car_on_road[24] = 1'b1;
end
end
// Move obstacles
if (obstacle_pos_y[0] <= 480 + police_height)
obstacle_pos_y[0] = obstacle_pos_y[0] + 4;
if (obstacle_pos_y[1] <= 480 + police_height)
obstacle_pos_y[1] = obstacle_pos_y[1] + 4;
if (obstacle_pos_y[2] <= 480 + car_height)
obstacle_pos_y[2] = obstacle_pos_y[2] + 3;
if (obstacle_pos_y[3] <= 480 + car_height)
obstacle_pos_y[3] = obstacle_pos_y[3] + 3;
if (obstacle_pos_y[4] <= 480 + car_height)
obstacle_pos_y[4] = obstacle_pos_y[4] + 2;
end
//========================================================================
// The explosion animation
//========================================================================
// Disapear the animation
if (num == 0)
explode_visible <= 1'b0;
end
end
//=============================================================================
// Dynamic object's position calculation
//=============================================================================
// Scroll the road
always @ (posedge clk200 or posedge clr)
begin
if (clr)
begin
scroll <= 32'b0;
end
else
begin
if (status == activate)
scroll <= scroll - 2;
end
end
// Move the car and EDGE detection
always @(posedge clk800 or posedge clr)
begin
if (clr)
begin
mycar_pos_x <= 289;
mycar_pos_y <= 384;
end
else
begin
if (status == activate)
begin
if (direction == 4'b1000)
begin
if (mycar_pos_y >= 1)
mycar_pos_y <= mycar_pos_y - 1 ;
end
else if (direction == 4'b0100)
begin
if (mycar_pos_y < 380)
mycar_pos_y <= mycar_pos_y + 1;
end
else if (direction == 4'b0010)
begin
if (mycar_pos_x >= 79 - car_offset_left)
mycar_pos_x <= mycar_pos_x - 1;
end
else if (direction == 4'b0001)
begin
if (mycar_pos_x < 500 + car_offset_right)
mycar_pos_x <= mycar_pos_x + 1;
end
end
end
end
// Explosion
always @ (posedge clk50 or posedge clr)
begin
if (clr)
begin
num <= 4'b0;
end
else
begin
if (status == activate)
begin
num <= (num + 1) % 14;
if (iscollide0 || iscollide1 || iscollide2 || iscollide3 || iscollide4)
begin
num <= 1;
end
end
end
end
//==============================================================================
// Score Counter
//==============================================================================
wire plus;
Counter score_counter (
.clk(clk),
.clr(clr),
.plus(plus),
.score0(score[0]), .score1(score[1]), .score2(score[2]), .score3(score[3]),
.high_score0(high_score0), .high_score1(high_score1), .high_score2(high_score2), .high_score3(high_score3)
);
assign plus = iscollide2 || iscollide3 || iscollide4;
endmodule
|
module sha2_sec_ti2_rm0_plain_nand(
input wire a,
input wire b,
output reg q
);
wire tmp;
assign tmp = ~(a&b);
wire tmp2 = tmp;
reg tmp3;
always @*tmp3 = tmp2;
always @* q = tmp3;
endmodule
module sha2_sec_ti2_rm0_ti2_and_l0 #(
parameter NOTA = 1'b0,
parameter NOTB = 1'b0,
parameter NOTY = 1'b0
)(
input wire [1:0] i_a, //WARNING: must be uniform
input wire [1:0] i_b, //WARNING: must be uniform
output reg [1:0] o_y //WARNING: non uniform
);
wire [1:0] a = i_a^ NOTA[0];
wire [1:0] b = i_b^ NOTB[0];
wire n00,n10,n01;
wire n11;
sha2_sec_ti2_rm0_plain_nand nand00_ITK(.a(a[0]), .b(b[0]), .q(n00));
sha2_sec_ti2_rm0_plain_nand nand10_ITK(.a(a[1]), .b(b[0]), .q(n10));
sha2_sec_ti2_rm0_plain_nand nand01_ITK(.a(a[0]), .b(b[1]), .q(n01));
sha2_sec_ti2_rm0_plain_nand nand11_ITK(.a(a[1]), .b(b[1]), .q(n11));
always @* begin
o_y[0] = n00 ^ n11 ^ NOTY[0];
o_y[1] = n10 ^ n01;
end
endmodule
/*
//` default_nettype none
module sha2_sec_ti2_rm0 (
input wire i_reset,
input wire i_clk,
input wire i_sha512,
input wire i_write,//1 cycle pulse each time i_dat is valid for message input.
input wire i_write_state,//1 cycle pulse each time i_dat is valid for state input.
input wire i_read,
input wire i_init_mask,//pulse must last at least two cycles
input wire [64-1:0] i_rnd,
input wire [64-1:0] i_dat_mdat,
input wire [64-1:0] i_dat_mask,//input message and state are fed serially word by word.
output reg [64-1:0] o_dat_mdat,
output reg [64-1:0] o_dat_mask,
output reg o_run,
output reg o_valid
);
//registers
reg [16*64-1:0] w;
reg [8*64-1:0] state;
reg [8*64-1:0] state_mask;
reg [8*64-1:0] initial_state;
reg [64-1:0] initial_state_mask_seed;
reg [64-1:0] initial_state_mask;
always @* o_dat_mdat = state[7*64+:64];
always @* o_dat_mask = state_mask[7*64+:64];
function [3:0] func_prince_sbox;
input [3:0] in;
begin
case(in)
4'h0: func_prince_sbox = 4'hB;
4'h1: func_prince_sbox = 4'hF;
4'h2: func_prince_sbox = 4'h3;
4'h3: func_prince_sbox = 4'h2;
4'h4: func_prince_sbox = 4'hA;
4'h5: func_prince_sbox = 4'hC;
4'h6: func_prince_sbox = 4'h9;
4'h7: func_prince_sbox = 4'h1;
4'h8: func_prince_sbox = 4'h6;
4'h9: func_prince_sbox = 4'h7;
4'hA: func_prince_sbox = 4'h8;
4'hB: func_prince_sbox = 4'h0;
4'hC: func_prince_sbox = 4'hE;
4'hD: func_prince_sbox = 4'h5;
4'hE: func_prince_sbox = 4'hD;
4'hF: func_prince_sbox = 4'h4;
endcase
end
endfunction
function [64-1:0] func_substitution;
input [64-1:0] in;
integer i;
reg [64-1:0] out;
begin
for(i=0;i<64/4;i=i+1) begin
out[i*4+:4] = func_prince_sbox(in[i*4+:4]);
end
func_substitution = out;
end
endfunction
function [64-1:0] func_permutation;
input [64-1:0] in;
integer i;
integer base4,rank,j;
reg [64-1:0] out;
begin
for(i=0;i<64;i=i+1) begin
base4 = 4*(i/4);
rank = i-base4;
case(rank)
0: begin
if(i==3*4) j = 1;
else j = base4 + 29*4;
end
1: begin
if(i==13*4+1) j = 2;
else j = base4 + 3*4 + 1;//0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13
end
2: begin
if(i==11*4+2) j = 3;
else j = base4 + 5*4 + 2;//0,5,10,15,4,9,14,3,8,13,2,7,12,1,6,11
end
3: begin
if(i==9*4+3) j = 0;
else j = base4 + 7*4 + 3;//0,7,14,5,12,3,10,1,8,15,6,13,4,11,2,9
end
endcase
j = j % 64;
out[j] = in[i];
end
func_permutation = out;
end
endfunction
//syndrom[4] and syndrom[5] manually modified to avoid duplicate
//extended_hamming_code_96_64_f
//Compute 32 bits Error Detection Code from a 64 bits input.
//The EDC is an extended hamming code capable of detecting any 1,2 and 3 bits errors in the input data or the EDC.
//There are 18446744073709551616 valid code words out of 79228162514264337593543950336 therefore 99% of errors are detected.
//Dot graphic view: in[0]...in[63]
// syndrom[ 0]: x xx xx x (6 inputs)
// syndrom[ 1]: x x x x x x (6 inputs)
// syndrom[ 2]: x xx x x x (6 inputs)
// syndrom[ 3]: x x x x x x (6 inputs)
// syndrom[ 4]: x x x x x X (6 inputs)
// syndrom[ 5]: x xx xx X (6 inputs)
// syndrom[ 6]: x x x x x x (6 inputs)
// syndrom[ 7]: x x x x x x (6 inputs)
// syndrom[ 8]: x x x x x x (6 inputs)
// syndrom[ 9]: x x x x x x (6 inputs)
// syndrom[10]: x x x x x x (6 inputs)
// syndrom[11]: x x x xx x (6 inputs)
// syndrom[12]: x x x x x x (6 inputs)
// syndrom[13]: x x x x x x (6 inputs)
// syndrom[14]: x x x x x x (6 inputs)
// syndrom[15]: x x x x x x (6 inputs)
// syndrom[16]: x x x x x x (6 inputs)
// syndrom[17]: x x x x x x (6 inputs)
// syndrom[18]: x x x x x x (6 inputs)
// syndrom[19]: x x x x x x (6 inputs)
// syndrom[20]: x x x x x x (6 inputs)
// syndrom[21]: x x x x x x (6 inputs)
// syndrom[22]: x x x x x x (6 inputs)
// syndrom[23]: x x x x x x (6 inputs)
// syndrom[24]: x x x x xx (6 inputs)
// syndrom[25]: x x x x x x (6 inputs)
// syndrom[26]: x x x x x x (6 inputs)
// syndrom[27]: xx x x x x (6 inputs)
// syndrom[28]: x x xx xx (6 inputs)
// syndrom[29]: x x x x x x (6 inputs)
// syndrom[30]: xx x x xx (6 inputs)
// syndrom[31]: xx xx x x (6 inputs)
//Input usage report:
// input bit 0 used 3 times (syndrom bits 0 1 2)
// input bit 1 used 3 times (syndrom bits 3 4 5)
// input bit 2 used 3 times (syndrom bits 6 7 8)
// input bit 3 used 3 times (syndrom bits 9 10 11)
// input bit 4 used 3 times (syndrom bits 12 13 14)
// input bit 5 used 3 times (syndrom bits 15 16 17)
// input bit 6 used 3 times (syndrom bits 18 19 20)
// input bit 7 used 3 times (syndrom bits 21 22 23)
// input bit 8 used 3 times (syndrom bits 24 25 26)
// input bit 9 used 3 times (syndrom bits 27 28 29)
// input bit 10 used 3 times (syndrom bits 27 30 31)
// input bit 11 used 3 times (syndrom bits 28 30 31)
// input bit 12 used 3 times (syndrom bits 24 25 29)
// input bit 13 used 3 times (syndrom bits 21 22 26)
// input bit 14 used 3 times (syndrom bits 18 19 23)
// input bit 15 used 3 times (syndrom bits 15 16 20)
// input bit 16 used 3 times (syndrom bits 12 13 17)
// input bit 17 used 3 times (syndrom bits 9 10 14)
// input bit 18 used 3 times (syndrom bits 6 7 11)
// input bit 19 used 3 times (syndrom bits 3 4 8)
// input bit 20 used 3 times (syndrom bits 0 1 5)
// input bit 21 used 3 times (syndrom bits 0 2 5)
// input bit 22 used 3 times (syndrom bits 1 2 8)
// input bit 23 used 3 times (syndrom bits 3 4 11)
// input bit 24 used 3 times (syndrom bits 6 7 14)
// input bit 25 used 3 times (syndrom bits 9 10 17)
// input bit 26 used 3 times (syndrom bits 12 13 20)
// input bit 27 used 3 times (syndrom bits 15 16 23)
// input bit 28 used 3 times (syndrom bits 18 19 26)
// input bit 29 used 3 times (syndrom bits 21 22 29)
// input bit 30 used 3 times (syndrom bits 24 25 30)
// input bit 31 used 3 times (syndrom bits 27 28 31)
// input bit 32 used 3 times (syndrom bits 24 28 31)
// input bit 33 used 3 times (syndrom bits 25 27 30)
// input bit 34 used 3 times (syndrom bits 18 21 22)
// input bit 35 used 3 times (syndrom bits 19 26 29)
// input bit 36 used 3 times (syndrom bits 12 15 16)
// input bit 37 used 3 times (syndrom bits 13 20 23)
// input bit 38 used 3 times (syndrom bits 6 9 10)
// input bit 39 used 3 times (syndrom bits 7 14 17)
// input bit 40 used 3 times (syndrom bits 2 3 4)
// input bit 41 used 3 times (syndrom bits 1 8 11)
// input bit 42 used 3 times (syndrom bits 0 5 11)
// input bit 43 used 3 times (syndrom bits 0 5 8)
// input bit 44 used 3 times (syndrom bits 1 3 4)
// input bit 45 used 3 times (syndrom bits 2 7 17)
// input bit 46 used 3 times (syndrom bits 6 9 14)
// input bit 47 used 3 times (syndrom bits 10 13 23)
// input bit 48 used 3 times (syndrom bits 12 15 20)
// input bit 49 used 3 times (syndrom bits 16 19 29)
// input bit 50 used 3 times (syndrom bits 18 21 26)
// input bit 51 used 3 times (syndrom bits 22 25 27)
// input bit 52 used 3 times (syndrom bits 24 30 31)
// input bit 53 used 3 times (syndrom bits 24 28 30)
// input bit 54 used 3 times (syndrom bits 22 28 31)
// input bit 55 used 3 times (syndrom bits 25 26 27)
// input bit 56 used 3 times (syndrom bits 16 18 21)
// input bit 57 used 3 times (syndrom bits 19 20 29)
// input bit 58 used 3 times (syndrom bits 10 12 15)
// input bit 59 used 3 times (syndrom bits 13 14 23)
// input bit 60 used 3 times (syndrom bits 2 6 9)
// input bit 61 used 3 times (syndrom bits 1 7 17)
// input bit 62 used 3 times (syndrom bits 0 3 5)
// input bit 63 used 3 times (syndrom bits 4 8 11)
function [32-1:0] extended_hamming_code_96_64_f;
input [64-1:0] in;
reg [32-1:0] syndrom;
begin
syndrom[ 0] = in[ 0]^in[20]^in[21]^in[42]^in[43]^in[62];//6 inputs
syndrom[ 1] = in[ 0]^in[20]^in[22]^in[41]^in[44]^in[61];//6 inputs
syndrom[ 2] = in[ 0]^in[21]^in[22]^in[40]^in[45]^in[60];//6 inputs
syndrom[ 3] = in[ 1]^in[19]^in[23]^in[40]^in[44]^in[62];//6 inputs
syndrom[ 4] = in[ 1]^in[19]^in[23]^in[40]^in[44]^in[63];//6 inputs
syndrom[ 5] = in[ 1]^in[20]^in[21]^in[42]^in[43]^in[62];//6 inputs
syndrom[ 6] = in[ 2]^in[18]^in[24]^in[38]^in[46]^in[60];//6 inputs
syndrom[ 7] = in[ 2]^in[18]^in[24]^in[39]^in[45]^in[61];//6 inputs
syndrom[ 8] = in[ 2]^in[19]^in[22]^in[41]^in[43]^in[63];//6 inputs
syndrom[ 9] = in[ 3]^in[17]^in[25]^in[38]^in[46]^in[60];//6 inputs
syndrom[10] = in[ 3]^in[17]^in[25]^in[38]^in[47]^in[58];//6 inputs
syndrom[11] = in[ 3]^in[18]^in[23]^in[41]^in[42]^in[63];//6 inputs
syndrom[12] = in[ 4]^in[16]^in[26]^in[36]^in[48]^in[58];//6 inputs
syndrom[13] = in[ 4]^in[16]^in[26]^in[37]^in[47]^in[59];//6 inputs
syndrom[14] = in[ 4]^in[17]^in[24]^in[39]^in[46]^in[59];//6 inputs
syndrom[15] = in[ 5]^in[15]^in[27]^in[36]^in[48]^in[58];//6 inputs
syndrom[16] = in[ 5]^in[15]^in[27]^in[36]^in[49]^in[56];//6 inputs
syndrom[17] = in[ 5]^in[16]^in[25]^in[39]^in[45]^in[61];//6 inputs
syndrom[18] = in[ 6]^in[14]^in[28]^in[34]^in[50]^in[56];//6 inputs
syndrom[19] = in[ 6]^in[14]^in[28]^in[35]^in[49]^in[57];//6 inputs
syndrom[20] = in[ 6]^in[15]^in[26]^in[37]^in[48]^in[57];//6 inputs
syndrom[21] = in[ 7]^in[13]^in[29]^in[34]^in[50]^in[56];//6 inputs
syndrom[22] = in[ 7]^in[13]^in[29]^in[34]^in[51]^in[54];//6 inputs
syndrom[23] = in[ 7]^in[14]^in[27]^in[37]^in[47]^in[59];//6 inputs
syndrom[24] = in[ 8]^in[12]^in[30]^in[32]^in[52]^in[53];//6 inputs
syndrom[25] = in[ 8]^in[12]^in[30]^in[33]^in[51]^in[55];//6 inputs
syndrom[26] = in[ 8]^in[13]^in[28]^in[35]^in[50]^in[55];//6 inputs
syndrom[27] = in[ 9]^in[10]^in[31]^in[33]^in[51]^in[55];//6 inputs
syndrom[28] = in[ 9]^in[11]^in[31]^in[32]^in[53]^in[54];//6 inputs
syndrom[29] = in[ 9]^in[12]^in[29]^in[35]^in[49]^in[57];//6 inputs
syndrom[30] = in[10]^in[11]^in[30]^in[33]^in[52]^in[53];//6 inputs
syndrom[31] = in[10]^in[11]^in[31]^in[32]^in[52]^in[54];//6 inputs
extended_hamming_code_96_64_f = syndrom;
end
endfunction
function [64-1:0] func_next_mask;
input [64-1:0] seed;
input [64-1:0] key;
reg [64-1:0] mixin;
begin
mixin = func_substitution(func_permutation(seed ^ key));
func_next_mask = {extended_hamming_code_96_64_f(func_permutation(mixin)),extended_hamming_code_96_64_f(mixin)};
end
endfunction
function [63:0] func_next_initial_state_mask;
input [63:0] seed;
func_next_initial_state_mask = func_next_mask(seed,64'hE56D24FA_7BC3D5AB);
endfunction
function [63:0] func_next_wi_mask;
input [63:0] seed;
func_next_wi_mask = func_next_mask(seed,64'hB2DD568E_019A3FBD);
endfunction
wire [64-1:0] next_initial_state_mask = func_next_initial_state_mask(initial_state_mask);
wire [64-1:0] w0_mdat = w[0+:64];
reg [64-1:0] w0_mask;
wire [64-1:0] next_w0_mask = func_next_wi_mask(w0_mask);
wire [64-1:0] w1_mdat = w[1*64+:64];
reg [64-1:0] w1_mask;
wire [64-1:0] next_w1_mask = func_next_wi_mask(w1_mask);
wire [64-1:0] w6_mdat = w[6*64+:64];
reg [64-1:0] w6_mask;
wire [64-1:0] next_w6_mask = func_next_wi_mask(w6_mask);
wire [64-1:0] w14_mdat = w[14*64+:64];
reg [64-1:0] w14_mask;
wire [64-1:0] next_w14_mask = func_next_wi_mask(w14_mask);
wire [64-1:0] w15_mdat = w[15*64+:64];
reg [64-1:0] w15_mask;
wire [64-1:0] next_w15_mask = func_next_wi_mask(w15_mask);
wire [64-1:0] initial_state_write_delta_mask = initial_state_mask ^ state_mask[7*64+:64];
wire [64-1:0] initial_state_write_mdat = state[7*64+:64] ^ initial_state_write_delta_mask;
wire [64-1:0] initial_a_mask = w[7*64+:64];
wire [64-1:0] initial_b_mask = w[6*64+:64];
wire [64-1:0] initial_c_mask = w[5*64+:64];
wire [64-1:0] initial_d_mask = w[4*64+:64];
wire [64-1:0] initial_e_mask = w[3*64+:64];
wire [64-1:0] initial_f_mask = w[2*64+:64];
wire [64-1:0] initial_g_mask = w[1*64+:64];
wire [64-1:0] initial_h_mask = w[0*64+:64];
//SHA256 funcs
function [31:0] sigma0_256;
input [31:0] x;
sigma0_256 = s_256(x,2) ^ s_256(x,13) ^ s_256(x,22);
endfunction
function [31:0] sigma1_256;
input [31:0] x;
sigma1_256 = s_256(x,6) ^ s_256(x,11) ^ s_256(x,25);
endfunction
function [31:0] s_256;
input [31:0] x;
input integer n;
s_256 = (x >> n) | (x<<(32-n));
endfunction
function [31:0] gamma0_256;
input [31:0] x;
gamma0_256 = s_256(x,7) ^ s_256(x,18) ^ (x>>3);
endfunction
function [31:0] gamma1_256;
input [31:0] x;
gamma1_256 = s_256(x,17) ^ s_256(x,19) ^ (x>>10);
endfunction
//SHA512 funcs
function [63:0] sigma0;//boolean
input [63:0] x;
sigma0 = s(x,28) ^ s(x,34) ^ s(x,39);
endfunction
function [63:0] sigma1;//boolean
input [63:0] x;
sigma1 = s(x,14) ^ s(x,18) ^ s(x,41);
endfunction
function [63:0] s;//boolean
input [63:0] x;
input integer n;
s = (x >> n) | (x<<(64-n));
endfunction
function [63:0] gamma0;//boolean
input [63:0] x;
gamma0 = s(x,1) ^ s(x,8) ^ (x>>7);
endfunction
function [63:0] gamma1;//boolean
input [63:0] x;
gamma1 = s(x,61) ^ s(x,19) ^ (x>>6);
endfunction
reg state_update;
reg [7:0] step;
reg [7:0] state_step;
wire state_stage_ready = state_step == step;
wire [7:0] step_incr = step + 1'b1;
wire [7:0] step_rounds_max = i_sha512 ? 80+15+1 : 64+15+1;
wire [7:0] step_max = step_rounds_max+4;
wire [6:0] adders_width = i_sha512 ? 64 : 32;
always @(posedge i_clk,posedge i_reset) begin: CONTROL
if(i_reset) begin
step <= 0;
o_run <= 0;
o_valid <= 0;
state_update <= 0;
end else begin
if(i_write) begin
step <= step_incr;
o_valid <= 0;
if(step==15) begin
o_run <= 1'b1;
state_update <= 1'b1;
end
end else if(o_run) begin
if(state_stage_ready) begin
if(step==step_max+1'b1) begin
state_update <= 1'b0;
o_valid <= 1'b1;
o_run <= 1'b0;
end else begin
state_update <= 1'b1;
end
step <= step_incr;
end
end else if(o_valid) begin
if(step==step_max+1+8) begin
o_valid <= 0;
step <= 0;
end else if(i_read) step <= step_incr;
end else begin
state_update <= 1'b0;
end
end
end
reg [64-1:0] gamma1_out_mdat;
reg [64-1:0] gamma1_out_mask;
reg [64-1:0] gamma0_out_mdat;
reg [64-1:0] gamma0_out_mask;
reg [64-1:0] w_wi_out_mdat;
reg [64-1:0] w_wi_out_mask;
wire w_wi_adder_out_mdat;
wire w_wi_adder_out_mask;
wire [64-1:0] w_wi_delta_mask;
sha2_sec_ti2_rm0_xor #(.WIDTH(64)) u_wi_delta_mask_xor_ITK(.a(w_wi_out_mask), .b(next_w0_mask), .y(w_wi_delta_mask));
wire [64-1:0] w_wi_write_to_w0 = w_wi_out_mdat ^ w_wi_delta_mask;
wire [64-1:0] i_dat_delta_mask;
sha2_sec_ti2_rm0_xor #(.WIDTH(64)) u_dat_delta_mask_xor_ITK(.a(i_dat_mask), .b(next_w0_mask), .y(i_dat_delta_mask));
wire [64-1:0] i_dat_write_to_w0 = i_dat_mdat ^ i_dat_delta_mask;
wire [64*64-1:0] k_256 = 2048'hc67178f2bef9a3f7a4506ceb90befffa8cc7020884c8781478a5636f748f82ee682e6ff35b9cca4f4ed8aa4a391c0cb334b0bcb52748774c1e376c0819a4c116106aa070f40e3585d6990624d192e819c76c51a3c24b8b70a81a664ba2bfe8a192722c8581c2c92e766a0abb650a735453380d134d2c6dfc2e1b213827b70a851429296706ca6351d5a79147c6e00bf3bf597fc7b00327c8a831c66d983e515276f988da5cb0a9dc4a7484aa2de92c6f240ca1cc0fc19dc6efbe4786e49b69c1c19bf1749bdc06a780deb1fe72be5d74550c7dc3243185be12835b01d807aa98ab1c5ed5923f82a459f111f13956c25be9b5dba5b5c0fbcf71374491428a2f98;
wire [80*64-1:0] k = 5120'h6c44198c4a4758175fcb6fab3ad6faec597f299cfc657e2a4cc5d4becb3e42b6431d67c49c100d4c3c9ebe0a15c9bebc32caab7b40c7249328db77f523047d841b710b35131c471b113f9804bef90dae0a637dc5a2c898a606f067aa72176fbaf57d4f7fee6ed178eada7dd6cde0eb1ed186b8c721c0c207ca273eceea26619cc67178f2e372532bbef9a3f7b2c67915a4506cebde82bde990befffa23631e288cc702081a6439ec84c87814a1f0ab7278a5636f43172f60748f82ee5defb2fc682e6ff3d6b2b8a35b9cca4f7763e3734ed8aa4ae3418acb391c0cb3c5c95a6334b0bcb5e19b48a82748774cdf8eeb991e376c085141ab5319a4c116b8d2d0c8106aa07032bbd1b8f40e35855771202ad69906245565a910d192e819d6ef5218c76c51a30654be30c24b8b70d0f89791a81a664bbc423001a2bfe8a14cf1036492722c851482353b81c2c92e47edaee6766a0abb3c77b2a8650a73548baf63de53380d139d95b3df4d2c6dfc5ac42aed2e1b21385c26c92627b70a8546d22ffc142929670a0e6e7006ca6351e003826fd5a79147930aa725c6e00bf33da88fc2bf597fc7beef0ee4b00327c898fb213fa831c66d2db43210983e5152ee66dfab76f988da831153b55cb0a9dcbd41fbd44a7484aa6ea6e4832de92c6f592b0275240ca1cc77ac9c650fc19dc68b8cd5b5efbe4786384f25e3e49b69c19ef14ad2c19bf174cf6926949bdc06a725c7123580deb1fe3b1696b172be5d74f27b896f550c7dc3d5ffb4e2243185be4ee4b28c12835b0145706fbed807aa98a3030242ab1c5ed5da6d8118923f82a4af194f9b59f111f1b605d0193956c25bf348b538e9b5dba58189dbbcb5c0fbcfec4d3b2f7137449123ef65cd428a2f98d728ae22;
reg [64-1:0] initial_a,initial_b,initial_c,initial_d,initial_e,initial_f,initial_g,initial_h;
always @* {initial_a,initial_b,initial_c,initial_d,initial_e,initial_f,initial_g,initial_h} = initial_state;
reg [64-1:0] a_mdat,b_mdat,c_mdat,d_mdat,e_mdat,f_mdat,g_mdat,h_mdat;
always @* {a_mdat,b_mdat,c_mdat,d_mdat,e_mdat,f_mdat,g_mdat,h_mdat} = state;
wire [31:0] a_256_mdat = a_mdat[31:0];
wire [31:0] b_256_mdat = b_mdat[31:0];
wire [31:0] c_256_mdat = c_mdat[31:0];
wire [31:0] d_256_mdat = d_mdat[31:0];
wire [31:0] e_256_mdat = e_mdat[31:0];
wire [31:0] f_256_mdat = f_mdat[31:0];
wire [31:0] g_256_mdat = g_mdat[31:0];
wire [31:0] h_256_mdat = h_mdat[31:0];
reg [64-1:0] a_mask,b_mask,c_mask,d_mask,e_mask,f_mask,g_mask,h_mask;
always @* {a_mask,b_mask,c_mask,d_mask,e_mask,f_mask,g_mask,h_mask} = state_mask;
wire [31:0] a_256_mask = a_mask[31:0];
wire [31:0] b_256_mask = b_mask[31:0];
wire [31:0] c_256_mask = c_mask[31:0];
wire [31:0] d_256_mask = d_mask[31:0];
wire [31:0] e_256_mask = e_mask[31:0];
wire [31:0] f_256_mask = f_mask[31:0];
wire [31:0] g_256_mask = g_mask[31:0];
wire [31:0] h_256_mask = h_mask[31:0];
reg [64-1:0] ki;
wire [31:0] ki_256 = ki[0+:32];
wire [31:0] sigma1_e_256_mdat = sigma1_256(e_256_mdat);
wire [31:0] sigma1_e_256_mask = sigma1_256(e_256_mask);
wire [31:0] gamma1_256_mdat = gamma1_256(w1_mdat[0+:32]);
wire [31:0] gamma1_256_mask = gamma1_256(w1_mask[0+:32]);
wire [31:0] gamma0_256_mdat = gamma0_256(w14_mdat[0+:32]);
wire [31:0] gamma0_256_mask = gamma0_256(w14_mask);
wire [31:0] sigma0_a_256_mdat = sigma0_256(a_256_mdat);
wire [31:0] sigma0_a_256_mask = sigma0_256(a_256_mask);
wire [63:0] sigma1_e_mdat = sigma1(e_mdat);
wire [63:0] sigma1_e_mask = sigma1(e_mask);
wire [63:0] gamma1_mdat = gamma1(w1_mdat);
wire [63:0] gamma1_mask = gamma1(w1_mask);
wire [63:0] gamma0_mdat = gamma0(w14_mdat);
wire [63:0] gamma0_mask = gamma0(w14_mask);
wire [63:0] sigma0_a_mdat = sigma0(a_mdat);
wire [63:0] sigma0_a_mask = sigma0(a_mask);
reg [64-1:0] t1_adder_sigma1_mdat;
reg [64-1:0] t1_adder_sigma1_mask;
reg [6-1:0] maj_rnd_in;
wire serial_maj_mdat;
wire serial_maj_mask;
sha2_sec_ti2_rm0_masked_maj u_serial_maj(
.i_clk(i_clk),.i_rnd(maj_rnd_in),
.i_x_mdat(b_mdat[0]),.i_y_mdat(c_mdat[0]),.i_z_mdat(d_mdat[0]),
.i_x_mask(b_mask[0]),.i_y_mask(c_mask[0]),.i_z_mask(d_mask[0]),
.o_mdat(serial_maj_mdat), .o_mask(serial_maj_mask)
);
wire ch_out_mdat;
wire ch_out_mask;
reg [2-1:0] ch_rnd_in;
sha2_sec_ti2_rm0_serial_masked_ch u_ch(
.i_clk(i_clk),.i_rnd(ch_rnd_in),
.i_x_mdat(f_mdat[0]),.i_y_mdat(g_mdat[0]),.i_z_mdat(h_mdat[0]),
.i_x_mask(f_mask[0]),.i_y_mask(g_mask[0]),.i_z_mask(h_mask[0]),
.o_mdat(ch_out_mdat), .o_mask(ch_out_mask)
);
reg [64-1:0] t2_adder_sigma0_mdat;
reg [64-1:0] t2_adder_sigma0_mask;
function [63:0] rr64;
input [63:0] in;
rr64 = {in[0],in[1+:63]};
endfunction
function [63:0] sr64;
input [63:0] in;
input msb;
sr64 = {msb,in[1+:63]};
endfunction
function [64-1:0] rr32;
input [64-1:0] in;
rr32 = {in[32+:32],in[0],in[1+:31]};
endfunction
function [64-1:0] sr32;
input [64-1:0] in;
input msb;
sr32 = {in[32+:32],msb,in[1+:31]};
endfunction
function [64-1:0] rr_word;
input [64-1:0] in;
rr_word = i_sha512 ? rr64(in) : rr32(in);
endfunction
function [64-1:0] sr_word;
input [64-1:0] in;
input msb;
sr_word = i_sha512 ? sr64(in,msb) : sr32(in,msb);
endfunction
//return {mdat,mask}
function [2*64-1:0] rr_masked_word;
input [64-1:0] in_mdat;
input [64-1:0] in_mask;
rr_masked_word = {rr_word(in_mdat),rr_word(in_mask)};
endfunction
localparam A_IDX = 3'h7;
localparam B_IDX = 3'h6;
localparam C_IDX = 3'h5;
localparam D_IDX = 3'h4;
localparam E_IDX = 3'h3;
localparam F_IDX = 3'h2;
localparam G_IDX = 3'h1;
localparam H_IDX = 3'h0;
function [2*64-1:0] rr_state_word;
input [2:0] word_idx;
rr_state_word = rr_masked_word(state[word_idx*64+:64],state_mask[word_idx*64+:64]);
endfunction
wire t1_adder_out_mdat,t1_adder_out_mask;
wire t2_adder_out_mdat,t2_adder_out_mask;
wire next_a_adder_out_mdat,next_a_adder_out_mask;
wire next_e_adder_out_mdat,next_e_adder_out_mask;
wire [64-1:0] next_a = h_mdat;//t1 + t2;
wire [64-1:0] next_b = a_mdat;
wire [64-1:0] next_c = b_mdat;
wire [64-1:0] next_d = c_mdat;
wire [64-1:0] next_e = d_mdat;//d + t1;
wire [64-1:0] next_f = e_mdat;
wire [64-1:0] next_g = f_mdat;
wire [64-1:0] next_h = g_mdat;
wire [64-1:0] next_a_mask = h_mask;
wire [64-1:0] next_b_mask = a_mask;
wire [64-1:0] next_c_mask = b_mask;
wire [64-1:0] next_d_mask = c_mask;
wire [64-1:0] next_e_mask = d_mask;
wire [64-1:0] next_f_mask = e_mask;
wire [64-1:0] next_g_mask = f_mask;
wire [64-1:0] next_h_mask = g_mask;
reg [6:0] adders_step;
reg adders_load_in;
wire maj_start = adders_step == 1;
wire maj_stop = adders_step == adders_width+1;
wire ch_stop = adders_step == adders_width-1;
wire t1_adder_start = adders_step == 1;
wire t1_adder_stop = adders_step == adders_width;
wire w_wi_adder_stop = adders_step == adders_width+2;
wire t2_adder_start = adders_step == 3;
wire t2_adder_stop = adders_step == adders_width+3;
wire next_e_adder_start = adders_step == 4;
wire next_e_adder_stop = adders_step == adders_width+4;
wire next_a_adder_start = next_e_adder_start;
wire next_a_adder_stop = next_e_adder_stop;
reg t1_adder_run,t2_adder_run,next_e_adder_run,adders_run,w_wi_adder_run;
wire next_a_adder_run = next_e_adder_run;
reg [12-1:0] w_wi_adder_rnd_in;
reg [2:0] w_wi_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_4op w_wi_adder (
.i_clk(i_clk),.i_start(t1_adder_start),.i_rnd(w_wi_adder_rnd_in),.i_c_mdat(w_wi_adder_ci_rnd),.i_c_mask(w_wi_adder_ci_rnd),
.i_op0_mdat(gamma0_out_mdat[0]), .i_op1_mdat(gamma1_out_mdat[0]), .i_op2_mdat(w15_mdat[0]), .i_op3_mdat(w6_mdat[0]),
.i_op0_mask(gamma0_out_mask[0]), .i_op1_mask(gamma1_out_mask[0]), .i_op2_mask(w15_mask[0]), .i_op3_mask(w6_mask[0]),
.o_dat_mdat(w_wi_adder_out_mdat), .o_dat_mask(w_wi_adder_out_mask)
);
reg [16-1:0] t1_adder_rnd_in;
reg [3:0] t1_adder_ci_rnd;//used to inject 0 in the carry input
reg ki0_mask_rnd;
wire ki0_mdat = ki[0] ^ ki0_mask_rnd;
sha2_sec_ti2_rm0_serial_masked_add_5op t1_adder (
.i_clk(i_clk),.i_start(t1_adder_start),.i_rnd(t1_adder_rnd_in),.i_c_mdat(t1_adder_ci_rnd),.i_c_mask(t1_adder_ci_rnd),
.i_op0_mdat(a_mdat[0]), .i_op1_mdat(t1_adder_sigma1_mdat[0]), .i_op2_mdat(ch_out_mdat), .i_op3_mdat(ki0_mdat), .i_op4_mdat(w0_mdat[0]),
.i_op0_mask(a_mask[0]), .i_op1_mask(t1_adder_sigma1_mask[0]), .i_op2_mask(ch_out_mask), .i_op3_mask(ki0_mask_rnd), .i_op4_mask(w0_mask[0]),
.o_dat_mdat(t1_adder_out_mdat), .o_dat_mask(t1_adder_out_mask)
);
reg [4-1:0] next_e_adder_rnd_in;
reg next_e_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op next_e_adder (
.i_clk(i_clk),.i_start(next_e_adder_start),.i_rnd(next_e_adder_rnd_in),.i_c_mdat(next_e_adder_ci_rnd),.i_c_mask(next_e_adder_ci_rnd),
.i_op0_mdat(t1_adder_out_mdat), .i_op1_mdat(e_mdat[0]),
.i_op0_mask(t1_adder_out_mask), .i_op1_mask(e_mask[0]),
.o_dat_mdat(next_e_adder_out_mdat), .o_dat_mask(next_e_adder_out_mask)
);
reg [4-1:0] t2_adder_rnd_in;
reg t2_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op t2_adder (
.i_clk(i_clk),.i_start(t2_adder_start),.i_rnd(t2_adder_rnd_in),.i_c_mdat(t2_adder_ci_rnd),.i_c_mask(t2_adder_ci_rnd),
.i_op0_mdat(t2_adder_sigma0_mdat[0]), .i_op1_mdat(serial_maj_mdat),
.i_op0_mask(t2_adder_sigma0_mask[0]), .i_op1_mask(serial_maj_mask),
.o_dat_mdat(t2_adder_out_mdat), .o_dat_mask(t2_adder_out_mask)
);
reg [4-1:0] next_a_adder_rnd_in;
reg next_a_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op next_a_adder (
.i_clk(i_clk),.i_start(next_a_adder_start),.i_rnd(next_a_adder_rnd_in),.i_c_mdat(next_a_adder_ci_rnd),.i_c_mask(next_a_adder_ci_rnd),
.i_op0_mdat(t1_adder_out_mdat), .i_op1_mdat(t2_adder_out_mdat),
.i_op0_mask(t1_adder_out_mask), .i_op1_mask(t2_adder_out_mask),
.o_dat_mdat(next_a_adder_out_mdat), .o_dat_mask(next_a_adder_out_mask)
);
reg [4-1:0] final_a_adder_rnd_in;
reg [4-1:0] final_b_adder_rnd_in;
reg [4-1:0] final_c_adder_rnd_in;
reg [4-1:0] final_d_adder_rnd_in;
reg [4-1:0] final_e_adder_rnd_in;
reg [4-1:0] final_f_adder_rnd_in;
reg [4-1:0] final_g_adder_rnd_in;
reg [4-1:0] final_h_adder_rnd_in;
reg final_adders_start;
wire final_a_adder_out_mdat,final_a_adder_out_mask;
reg final_a_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_a_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_a_adder_ci_rnd),.i_c_mask(final_a_adder_ci_rnd),.i_rnd(final_a_adder_rnd_in),
.i_op0_mdat(a_mdat[0]), .i_op1_mdat(initial_a[0]),
.i_op0_mask(a_mask[0]), .i_op1_mask(initial_a_mask[0]),
.o_dat_mdat(final_a_adder_out_mdat), .o_dat_mask(final_a_adder_out_mask)
);
wire final_b_adder_out_mdat,final_b_adder_out_mask;
reg final_b_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_b_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_b_adder_ci_rnd),.i_c_mask(final_b_adder_ci_rnd),.i_rnd(final_b_adder_rnd_in),
.i_op0_mdat(b_mdat[0]), .i_op1_mdat(initial_b[0]),
.i_op0_mask(b_mask[0]), .i_op1_mask(initial_b_mask[0]),
.o_dat_mdat(final_b_adder_out_mdat), .o_dat_mask(final_b_adder_out_mask)
);
wire final_c_adder_out_mdat,final_c_adder_out_mask;
reg final_c_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_c_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_c_adder_ci_rnd),.i_c_mask(final_c_adder_ci_rnd),.i_rnd(final_c_adder_rnd_in),
.i_op0_mdat(c_mdat[0]), .i_op1_mdat(initial_c[0]),
.i_op0_mask(c_mask[0]), .i_op1_mask(initial_c_mask[0]),
.o_dat_mdat(final_c_adder_out_mdat), .o_dat_mask(final_c_adder_out_mask)
);
wire final_d_adder_out_mdat,final_d_adder_out_mask;
reg final_d_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_d_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_d_adder_ci_rnd),.i_c_mask(final_d_adder_ci_rnd),.i_rnd(final_d_adder_rnd_in),
.i_op0_mdat(d_mdat[0]), .i_op1_mdat(initial_d[0]),
.i_op0_mask(d_mask[0]), .i_op1_mask(initial_d_mask[0]),
.o_dat_mdat(final_d_adder_out_mdat), .o_dat_mask(final_d_adder_out_mask)
);
wire final_e_adder_out_mdat,final_e_adder_out_mask;
reg final_e_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_e_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_e_adder_ci_rnd),.i_c_mask(final_e_adder_ci_rnd),.i_rnd(final_e_adder_rnd_in),
.i_op0_mdat(e_mdat[0]), .i_op1_mdat(initial_e[0]),
.i_op0_mask(e_mask[0]), .i_op1_mask(initial_e_mask[0]),
.o_dat_mdat(final_e_adder_out_mdat), .o_dat_mask(final_e_adder_out_mask)
);
wire final_f_adder_out_mdat,final_f_adder_out_mask;
reg final_f_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_f_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_f_adder_ci_rnd),.i_c_mask(final_f_adder_ci_rnd),.i_rnd(final_f_adder_rnd_in),
.i_op0_mdat(f_mdat[0]), .i_op1_mdat(initial_f[0]),
.i_op0_mask(f_mask[0]), .i_op1_mask(initial_f_mask[0]),
.o_dat_mdat(final_f_adder_out_mdat), .o_dat_mask(final_f_adder_out_mask)
);
wire final_g_adder_out_mdat,final_g_adder_out_mask;
reg final_g_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_g_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_g_adder_ci_rnd),.i_c_mask(final_g_adder_ci_rnd),.i_rnd(final_g_adder_rnd_in),
.i_op0_mdat(g_mdat[0]), .i_op1_mdat(initial_g[0]),
.i_op0_mask(g_mask[0]), .i_op1_mask(initial_g_mask[0]),
.o_dat_mdat(final_g_adder_out_mdat), .o_dat_mask(final_g_adder_out_mask)
);
wire final_h_adder_out_mdat,final_h_adder_out_mask;
reg final_h_adder_ci_rnd;//used to inject 0 in the carry input
sha2_sec_ti2_rm0_serial_masked_add_2op final_h_adder (
.i_clk(i_clk),.i_start(final_adders_start),.i_c_mdat(final_h_adder_ci_rnd),.i_c_mask(final_h_adder_ci_rnd),.i_rnd(final_h_adder_rnd_in),
.i_op0_mdat(h_mdat[0]), .i_op1_mdat(initial_h[0]),
.i_op0_mask(h_mask[0]), .i_op1_mask(initial_h_mask[0]),
.o_dat_mdat(final_h_adder_out_mdat), .o_dat_mask(final_h_adder_out_mask)
);
reg sigma_step;
wire [64-1:0] w15_delta_mask;
sha2_sec_ti2_rm0_xor #(.WIDTH(64)) u_w15_delta_mask_xor_ITK(.a(w15_mask), .b(next_w0_mask), .y(w15_delta_mask));
wire [64-1:0] w15_write_to_w0 = w15_mdat ^ w15_delta_mask;
always @* begin
{
maj_rnd_in,
ch_rnd_in,
ki0_mask_rnd,
w_wi_adder_ci_rnd,t1_adder_ci_rnd,next_e_adder_ci_rnd,t2_adder_ci_rnd,next_a_adder_ci_rnd,
w_wi_adder_rnd_in,t1_adder_rnd_in,next_e_adder_rnd_in,t2_adder_rnd_in,next_a_adder_rnd_in
} = {{64{1'bx}},i_rnd};//x is there to make the sim fail if we have i_rnd too small
{
final_a_adder_ci_rnd,final_b_adder_ci_rnd,final_c_adder_ci_rnd,final_d_adder_ci_rnd,
final_e_adder_ci_rnd,final_f_adder_ci_rnd,final_g_adder_ci_rnd,final_h_adder_ci_rnd,
final_a_adder_rnd_in,final_b_adder_rnd_in,final_c_adder_rnd_in,final_d_adder_rnd_in,
final_e_adder_rnd_in,final_f_adder_rnd_in,final_g_adder_rnd_in,final_h_adder_rnd_in
} = {{64{1'bx}},i_rnd};//x is there to make the sim fail if we have i_rnd too small
end
reg maj_run;
reg ch_run;
always @(posedge i_clk,posedge i_reset) begin: STATE_STAGE
if(i_reset) begin
adders_step <= {7{1'b0}};
state_step <= 0;
{adders_load_in,t1_adder_run,t2_adder_run,next_e_adder_run,adders_run} <= 0;
sigma_step <= 1'b1;
ch_run <= 1'b0;
maj_run <= 1'b0;
final_adders_start <= 1'b1;
end else begin
if(state_update) begin
if(state_step==15) begin
state_step <= step;
w <= {w[0+:15*64],w15_write_to_w0};//let w schedule be 1 step ahead of the state, this way we compute w0 and state can be updated in parallel.
{w15_mask,w14_mask,w6_mask,w1_mask,w0_mask} <= {next_w15_mask,next_w14_mask,next_w6_mask,next_w1_mask,next_w0_mask};
end else if(state_step<step_rounds_max) begin
final_adders_start <= 1'b1;
case({sigma_step,adders_load_in,adders_run})
3'b100: begin
adders_load_in <= 1'b1;
sigma_step <= 1'b0;
t1_adder_sigma1_mdat <= {sigma1_e_mdat[32+:32], i_sha512 ? sigma1_e_mdat[0+:32] : sigma1_e_256_mdat};
t1_adder_sigma1_mask <= {sigma1_e_mask[32+:32], i_sha512 ? sigma1_e_mask[0+:32] : sigma1_e_256_mask};
t2_adder_sigma0_mdat <= {sigma0_a_mdat[32+:32], i_sha512 ? sigma0_a_mdat[0+:32] : sigma0_a_256_mdat};
t2_adder_sigma0_mask <= {sigma0_a_mask[32+:32], i_sha512 ? sigma0_a_mask[0+:32] : sigma0_a_256_mask};
state <= {next_a,next_b,next_c,next_d,next_e,next_f,next_g,next_h};
state_mask <= {next_a_mask,next_b_mask,next_c_mask,next_d_mask,next_e_mask,next_f_mask,next_g_mask,next_h_mask};
end
3'b010: begin
adders_load_in <= 1'b0;
adders_run <= 1'b1;
t1_adder_run <= 1'b1;
adders_step <= 1'b1;
w_wi_adder_run <= 1'b1;
//t1 operands
if(i_sha512) begin
ki <= k[(state_step-16)*64+:64];
end else begin
ki <= k_256[(state_step-16)*32+:32];
end
//wi_adder operands
gamma1_out_mdat <= i_sha512 ? gamma1_mdat : {{32{1'bx}},gamma1_256_mdat};
gamma1_out_mask <= i_sha512 ? gamma1_mask : {{32{1'bx}},gamma1_256_mask};
gamma0_out_mdat <= i_sha512 ? gamma0_mdat : {{32{1'bx}},gamma0_256_mdat};
gamma0_out_mask <= i_sha512 ? gamma0_mask : {{32{1'bx}},gamma0_256_mask};
ch_run <= 1'b1;
{state[F_IDX*64+:64],state_mask[F_IDX*64+:64]} <= rr_state_word(F_IDX);
{state[G_IDX*64+:64],state_mask[G_IDX*64+:64]} <= rr_state_word(G_IDX);
{state[H_IDX*64+:64],state_mask[H_IDX*64+:64]} <= rr_state_word(H_IDX);
end
3'b001: begin
if(next_a_adder_stop) begin
adders_run <= 1'b0;
adders_step <= {7{1'b0}};
state_step <= step;
sigma_step <= 1'b1;
end else adders_step <= adders_step + 1'b1;
if(ch_stop) ch_run <= 1'b0;
if(maj_start) maj_run <= 1'b1;
else if(maj_stop) maj_run <= 1'b0;
if(t1_adder_stop) t1_adder_run <= 1'b0;
if(w_wi_adder_stop) w_wi_adder_run <= 1'b0;
if(t2_adder_start) t2_adder_run <= 1'b1;
else if(t2_adder_stop) t2_adder_run <= 1'b0;
if(next_e_adder_start) next_e_adder_run <= 1'b1;
else if(next_e_adder_stop) next_e_adder_run <= 1'b0;
if(t1_adder_run) begin//t1 operands, w_wi operands
ki <= rr_word(ki);
t1_adder_sigma1_mdat <= rr_word(t1_adder_sigma1_mdat);
t1_adder_sigma1_mask <= rr_word(t1_adder_sigma1_mask);
w[0*64+:64] <= rr_word(w0_mdat);
w0_mask <= rr_word(w0_mask);
//w_wi operands
w[( 7-1)*64+:64] <= rr_word(w6_mdat);
w6_mask <= rr_word(w6_mask);
w[(16-1)*64+:64] <= rr_word(w15_mdat);
w15_mask <= rr_word(w15_mask);
gamma0_out_mdat <= rr_word(gamma0_out_mdat);
gamma0_out_mask <= rr_word(gamma0_out_mask);
gamma1_out_mdat <= rr_word(gamma1_out_mdat);
gamma1_out_mask <= rr_word(gamma1_out_mask);
end else begin
if(next_a_adder_stop) begin
if(state_step<32-1) w <= {w[0+:15*64],w15_write_to_w0};
else w <= {w[0+:15*64],w_wi_write_to_w0};
{w15_mask,w14_mask,w6_mask,w1_mask,w0_mask} <= {next_w15_mask,next_w14_mask,next_w6_mask,next_w1_mask,next_w0_mask};
end
end
if(w_wi_adder_run) begin
//w_wi out
w_wi_out_mdat <= sr_word(w_wi_out_mdat,w_wi_adder_out_mdat);
w_wi_out_mask <= sr_word(w_wi_out_mask,w_wi_adder_out_mask);
end
if(t1_adder_run | next_a_adder_run) begin//t1 operand / next_a out
state [A_IDX*64+:64] <= sr_word(a_mdat,next_a_adder_out_mdat);//h operand is stored in state[7*64+:64]
state_mask[A_IDX*64+:64] <= sr_word(a_mask,next_a_adder_out_mask);//h operand is stored in state[7*64+:64]
end
//t2 operands
if(t2_adder_start|t2_adder_run) begin
t2_adder_sigma0_mdat <= rr_word(t2_adder_sigma0_mdat);
t2_adder_sigma0_mask <= rr_word(t2_adder_sigma0_mask);
end
//next_e operand
if(next_e_adder_start | next_e_adder_run) begin
state [E_IDX*64+:64] <= sr_word(e_mdat,next_e_adder_out_mdat);//d operand is stored in state[3*64+:64]
state_mask[E_IDX*64+:64] <= sr_word(e_mask,next_e_adder_out_mask);//d operand is stored in state[3*64+:64]
end
if(ch_run) begin
{state[F_IDX*64+:64],state_mask[F_IDX*64+:64]} <= rr_state_word(F_IDX);
{state[G_IDX*64+:64],state_mask[G_IDX*64+:64]} <= rr_state_word(G_IDX);
{state[H_IDX*64+:64],state_mask[H_IDX*64+:64]} <= rr_state_word(H_IDX);
end
if(maj_run) begin
{state[B_IDX*64+:64],state_mask[B_IDX*64+:64]} <= rr_state_word(B_IDX);
{state[C_IDX*64+:64],state_mask[C_IDX*64+:64]} <= rr_state_word(C_IDX);
{state[D_IDX*64+:64],state_mask[D_IDX*64+:64]} <= rr_state_word(D_IDX);
end
end
endcase
initial_state_mask <= initial_state_mask_seed;
end else if(state_step<step_max) begin
w <= {w[0+:15*64],initial_state_mask};
{w15_mask,w14_mask,w6_mask,w1_mask,w0_mask} <= {next_w15_mask,next_w14_mask,next_w6_mask,next_w1_mask,next_w0_mask};//we don't use mask anymore, but still generate them to hide our activities
initial_state_mask <= next_initial_state_mask;
state_step <= step;
end else begin
final_adders_start <= 1'b0;
{w15_mask,w14_mask,w6_mask,w1_mask,w0_mask} <= {next_w15_mask,next_w14_mask,next_w6_mask,next_w1_mask,next_w0_mask};//we don't use mask anymore, but still generate them to hide our activities
state <= {
sr_word(a_mdat,final_a_adder_out_mdat),
sr_word(b_mdat,final_b_adder_out_mdat),
sr_word(c_mdat,final_c_adder_out_mdat),
sr_word(d_mdat,final_d_adder_out_mdat),
sr_word(e_mdat,final_e_adder_out_mdat),
sr_word(f_mdat,final_f_adder_out_mdat),
sr_word(g_mdat,final_g_adder_out_mdat),
sr_word(h_mdat,final_h_adder_out_mdat)
};
state_mask <= {
sr_word(a_mask,final_a_adder_out_mask),
sr_word(b_mask,final_b_adder_out_mask),
sr_word(c_mask,final_c_adder_out_mask),
sr_word(d_mask,final_d_adder_out_mask),
sr_word(e_mask,final_e_adder_out_mask),
sr_word(f_mask,final_f_adder_out_mask),
sr_word(g_mask,final_g_adder_out_mask),
sr_word(h_mask,final_h_adder_out_mask)
};
initial_state <= {
rr_word(initial_a),
rr_word(initial_b),
rr_word(initial_c),
rr_word(initial_d),
rr_word(initial_e),
rr_word(initial_f),
rr_word(initial_g),
rr_word(initial_h)
};
w <= { w[8*64+:8*64],
rr_word(w[7*64+:64]),
rr_word(w[6*64+:64]),
rr_word(w[5*64+:64]),
rr_word(w[4*64+:64]),
rr_word(w[3*64+:64]),
rr_word(w[2*64+:64]),
rr_word(w[1*64+:64]),
rr_word(w[0*64+:64])
};
if(adders_step==adders_width-1) begin
adders_step <= {7{1'b0}};
state_step <= step;
end else adders_step <= adders_step + 1'b1;
end
end else begin
adders_step <= {7{1'b0}};
if(i_write_state) begin
state <= {state[0+:7*64],i_dat_mdat^i_rnd[0+:64]};
state_mask <= {state_mask[0+:7*64],i_dat_mask^i_rnd[0+:64]};
end else if(i_read) begin
state <= {state[0+:7*64],state[7*64+:64]};
state_mask <= {state_mask[0+:7*64],state_mask[7*64+:64]};
end
if(i_write) begin
w <= {w[0+:15*64],i_dat_write_to_w0};
w0_mask <= next_w0_mask;
if(step>=1) w1_mask <= next_w1_mask;
if(step>=6) w6_mask <= next_w6_mask;
if(step>=14) w14_mask <= next_w14_mask;
if(step>=15) w15_mask <= next_w15_mask;
if(step[3]) begin//copy state to initial_state during the load of the last 8 words of the message
initial_state <= {initial_state[0+:7*64],initial_state_write_mdat};
initial_state_mask <= next_initial_state_mask;
state <= {state[0+:7*64],state[7*64+:64]};
state_mask <= {state_mask[0+:7*64],state_mask[7*64+:64]};
end
end
if(i_init_mask) begin
w0_mask <= i_rnd;
w1_mask <= i_rnd;
w6_mask <= i_rnd;
w14_mask <= i_rnd;
w15_mask <= i_rnd;
initial_state_mask_seed <= w0_mask;
initial_state_mask <= w0_mask;
end
state_step <= step;
end
end
end
wire [64-1:0] _dbg_i_dat = i_dat_mdat ^ i_dat_mask;
wire [64-1:0] _dbg_o_dat = o_dat_mdat ^ o_dat_mask;
wire [64-1:0] _dbg_w0 = w0_mdat ^ w0_mask;
wire [64-1:0] _dbg_w1 = w1_mdat ^ w1_mask;
wire [64-1:0] _dbg_w6 = w6_mdat ^ w6_mask;
wire [64-1:0] _dbg_w14 = w14_mdat ^ w14_mask;
wire [64-1:0] _dbg_w15 = w15_mdat ^ w15_mask;
wire _dbg_next_a_adder_out = next_a_adder_out_mdat ^ next_a_adder_out_mask;
wire _dbg_next_e_adder_out = next_e_adder_out_mdat ^ next_e_adder_out_mask;
wire _dbg_t1_adder_out = t1_adder_out_mdat ^ t1_adder_out_mask;
wire _dbg_t2_adder_out = t2_adder_out_mdat ^ t2_adder_out_mask;
wire [64-1:0] _dbg_a = a_mdat ^ a_mask;
wire [64-1:0] _dbg_b = b_mdat ^ b_mask;
wire [64-1:0] _dbg_c = c_mdat ^ c_mask;
wire [64-1:0] _dbg_d = d_mdat ^ d_mask;
wire [64-1:0] _dbg_e = e_mdat ^ e_mask;
wire [64-1:0] _dbg_f = f_mdat ^ f_mask;
wire [64-1:0] _dbg_g = g_mdat ^ g_mask;
wire [64-1:0] _dbg_h = h_mdat ^ h_mask;
wire [8*64-1:0] _dbg_initial_state_final_add = initial_state ^ w[0+:8*64];
wire [64-1:0] _dbg_initial_state_final_add_a = initial_a ^ initial_a_mask;
wire [64-1:0] _dbg_initial_state_final_add_b = initial_b ^ initial_b_mask;
wire [64-1:0] _dbg_initial_state_final_add_c = initial_c ^ initial_c_mask;
wire [64-1:0] _dbg_initial_state_final_add_d = initial_d ^ initial_d_mask;
wire [64-1:0] _dbg_initial_state_final_add_e = initial_e ^ initial_e_mask;
wire [64-1:0] _dbg_initial_state_final_add_f = initial_f ^ initial_f_mask;
wire [64-1:0] _dbg_initial_state_final_add_g = initial_g ^ initial_g_mask;
wire [64-1:0] _dbg_initial_state_final_add_h = initial_h ^ initial_h_mask;
reg [8*64-1:0] _dbg_initial_state;
reg [64-1:0] _dbg_initial_state_mask;
always @* begin: DGB_INITIAL_STATE
integer i;
_dbg_initial_state_mask = initial_state_mask_seed;
for(i=0;i<8;i=i+1) begin
_dbg_initial_state[(7-i)*64+:64] = initial_state[(7-i)*64+:64] ^ _dbg_initial_state_mask;
_dbg_initial_state_mask = func_next_initial_state_mask(_dbg_initial_state_mask);
end
end
reg [16*64-1:0] _dbg_w;
reg [64-1:0] _dbg_w_mask;
always @* begin: DGB_W
integer i;
_dbg_w_mask = w15_mask;
for(i=0;i<16;i=i+1) begin
_dbg_w[(15-i)*64+:64] = w[(15-i)*64+:64] ^ _dbg_w_mask;
_dbg_w_mask = func_next_wi_mask(_dbg_w_mask);
end
end
wire [64-1:0] _dbg_w0_ref = _dbg_w[0*64+:64];
wire [64-1:0] _dbg_w1_ref = _dbg_w[1*64+:64];
wire [64-1:0] _dbg_w2 = _dbg_w[2*64+:64];
wire [64-1:0] _dbg_w3 = _dbg_w[3*64+:64];
wire [64-1:0] _dbg_w4 = _dbg_w[4*64+:64];
wire [64-1:0] _dbg_w5 = _dbg_w[5*64+:64];
wire [64-1:0] _dbg_w6_ref = _dbg_w[6*64+:64];
wire [64-1:0] _dbg_w7 = _dbg_w[7*64+:64];
wire [64-1:0] _dbg_w8 = _dbg_w[8*64+:64];
wire [64-1:0] _dbg_w9 = _dbg_w[9*64+:64];
wire [64-1:0] _dbg_w10 = _dbg_w[10*64+:64];
wire [64-1:0] _dbg_w11 = _dbg_w[11*64+:64];
wire [64-1:0] _dbg_w12 = _dbg_w[12*64+:64];
wire [64-1:0] _dbg_w13 = _dbg_w[13*64+:64];
wire [64-1:0] _dbg_w14_ref = _dbg_w[14*64+:64];
wire [64-1:0] _dbg_w15_ref = _dbg_w[15*64+:64];
wire _dbg_w0_check = _dbg_w0_ref === _dbg_w0;
wire _dbg_w1_check = _dbg_w1_ref === _dbg_w1;
wire _dbg_w6_check = _dbg_w6_ref === _dbg_w6;
wire _dbg_w14_check = _dbg_w14_ref === _dbg_w14;
wire _dbg_w15_check = _dbg_w15_ref === _dbg_w15;
wire _dbg_final_a_adder_ina = a_mdat[0] ^ a_mask[0];
wire _dbg_final_a_adder_inb = initial_a[0] ^ initial_a_mask[0];
wire _dbg_final_a_adder_out = final_a_adder_out_mdat ^ final_a_adder_out_mask;
wire _dbg_final_b_adder_out = final_b_adder_out_mdat ^ final_b_adder_out_mask;
wire _dbg_final_c_adder_out = final_c_adder_out_mdat ^ final_c_adder_out_mask;
wire _dbg_final_d_adder_out = final_d_adder_out_mdat ^ final_d_adder_out_mask;
wire _dbg_final_e_adder_out = final_e_adder_out_mdat ^ final_e_adder_out_mask;
wire _dbg_final_f_adder_out = final_f_adder_out_mdat ^ final_f_adder_out_mask;
wire _dbg_final_g_adder_out = final_g_adder_out_mdat ^ final_g_adder_out_mask;
wire _dbg_final_h_adder_out = final_h_adder_out_mdat ^ final_h_adder_out_mask;
wire [31:0] _dbg_sigma1_256_e = sigma1_e_256_mdat ^ sigma1_e_256_mask;
wire [64-1:0] _dbg_sigma1_e = sigma1_e_mdat ^ sigma1_e_mask;
wire [64-1:0] _dbg_gamma1_out = gamma1_out_mdat ^ gamma1_out_mask;
wire [64-1:0] _dbg_gamma0_out = gamma0_out_mdat ^ gamma0_out_mask;
wire [64-1:0] _dbg_sigma0_a = sigma0_a_mdat ^ sigma0_a_mask;
wire [64-1:0] _dbg_t1_adder_sigma1 = t1_adder_sigma1_mdat ^ t1_adder_sigma1_mask;
wire _dbg_ch_out = ch_out_mdat ^ ch_out_mask;
wire _dbg_serial_maj = serial_maj_mdat ^ serial_maj_mask;
wire _dbg_maj = serial_maj_mdat ^ serial_maj_mask;
wire [64-1:0] _dbg_t2_adder_sigma0 = t2_adder_sigma0_mdat ^ t2_adder_sigma0_mask;
reg [64-1:0] _dbg_t1;
always @(posedge i_clk) begin
if(t1_adder_start) _dbg_t1 <= {64{1'b0}};
else _dbg_t1 <= {_dbg_t1_adder_out,_dbg_t1[1+:64-1]};
end
reg [64-1:0] _dbg_next_e;
always @(posedge i_clk) begin
if(next_e_adder_start) _dbg_next_e <= {64{1'b0}};
else _dbg_next_e <= {_dbg_next_e_adder_out,_dbg_next_e[1+:64-1]};
end
reg [64-1:0] _dbg_t2;
always @(posedge i_clk) begin
if(t2_adder_start) _dbg_t2 <= {64{1'b0}};
else _dbg_t2 <= {_dbg_t2_adder_out,_dbg_t2[1+:64-1]};
end
reg [64-1:0] _dbg_next_a;
always @(posedge i_clk) begin
if(next_a_adder_start) _dbg_next_a <= {64{1'b0}};
else _dbg_next_a <= {_dbg_next_a_adder_out,_dbg_next_a[1+:64-1]};
end
endmodule
module sha2_sec_ti2_rm0_masked_maj #(
parameter WIDTH = 1
)(
input wire i_clk,
input wire [3*2*WIDTH-1:0] i_rnd,
input wire [WIDTH-1:0] i_x_mdat,
input wire [WIDTH-1:0] i_x_mask,
input wire [WIDTH-1:0] i_y_mdat,
input wire [WIDTH-1:0] i_y_mask,
input wire [WIDTH-1:0] i_z_mdat,//all inputs must be stable during computation (2 cycles)
input wire [WIDTH-1:0] i_z_mask,
output reg [WIDTH-1:0] o_mdat,
output reg [WIDTH-1:0] o_mask
);
wire [WIDTH-1:0] x0 = i_x_mask;
wire [WIDTH-1:0] x1 = i_x_mdat;
wire [WIDTH-1:0] y0 = i_y_mask;
wire [WIDTH-1:0] y1 = i_y_mdat;
wire [WIDTH-1:0] z0 = i_z_mask;
wire [WIDTH-1:0] z1 = i_z_mdat;
wire [WIDTH-1:0] xy_out0;
wire [WIDTH-1:0] xy_out1;
wire [WIDTH-1:0] xz_out0;
wire [WIDTH-1:0] xz_out1;
wire [WIDTH-1:0] yz_out0;
wire [WIDTH-1:0] yz_out1;
genvar i;
generate
for(i=0;i<WIDTH;i=i+1) begin: BIT
wire [1:0] xi = {x1[i],x0[i]};
wire [1:0] yi = {y1[i],y0[i]};
wire [1:0] zi = {z1[i],z0[i]};
sha2_sec_ti2_rm0_ti2_and u_xy(
.i_clk(i_clk),.i_rnd(i_rnd[i*2+:2]),
.i_a(xi),
.i_b(yi),
.o_y({xy_out1[i],xy_out0[i]}));
sha2_sec_ti2_rm0_ti2_and u_xz(
.i_clk(i_clk),.i_rnd(i_rnd[2*WIDTH+i*2+:2]),
.i_a(xi),
.i_b(zi),
.o_y({xz_out1[i],xz_out0[i]}));
sha2_sec_ti2_rm0_ti2_and u_yz(
.i_clk(i_clk),.i_rnd(i_rnd[4*WIDTH+i*2+:2]),
.i_a(zi),
.i_b(yi),
.o_y({yz_out1[i],yz_out0[i]}));
end
endgenerate
always @* begin
o_mdat = xy_out0 ^ xz_out0 ^ yz_out0;
o_mask = xy_out1 ^ xz_out1 ^ yz_out1;
end
endmodule
module sha2_sec_ti2_rm0_serial_masked_ch(
input wire i_clk,
input wire [2-1:0] i_rnd,
input wire i_x_mdat,
input wire i_x_mask,
input wire i_y_mdat,
input wire i_y_mask,
input wire i_z_mdat,
input wire i_z_mask,
output reg o_mdat,
output reg o_mask
);
//ch_256 = z ^ (x & (y ^ z));
reg z_mdat_l1;
reg z_mask_l1;
wire temp0 = i_y_mdat ^ i_z_mdat;
wire temp1 = i_y_mask ^ i_z_mask;
wire x0 = i_x_mask;
wire x1 = i_x_mdat;
always @(posedge i_clk) {z_mdat_l1,z_mask_l1} <= {i_z_mdat,i_z_mask};
wire and_out0;
wire and_out1;
sha2_sec_ti2_rm0_ti2_and u(
.i_clk(i_clk),.i_rnd(i_rnd),
.i_a({x1,x0}),
.i_b({temp1,temp0}),
.o_y({and_out1,and_out0}));
always @* begin
o_mdat = and_out0 ^ z_mdat_l1;
o_mask = and_out1 ^ z_mask_l1;
end
endmodule
module sha2_sec_ti2_rm0_serial_masked_add_5op (
input wire i_clk,
input wire i_start,
input wire [16-1:0] i_rnd,
input wire [3:0] i_c_mdat,
input wire [3:0] i_c_mask,
input wire i_op0_mdat,
input wire i_op1_mdat,
input wire i_op2_mdat,
input wire i_op3_mdat,
input wire i_op4_mdat,
input wire i_op0_mask,
input wire i_op1_mask,
input wire i_op2_mask,
input wire i_op3_mask,
input wire i_op4_mask,
output reg o_dat_mdat,
output reg o_dat_mask
);
wire [1:0] op0 = {i_op0_mask,i_op0_mdat};
wire [1:0] op1 = {i_op1_mask,i_op1_mdat};
wire [1:0] op2 = {i_op2_mask,i_op2_mdat};
wire [1:0] op3 = {i_op3_mask,i_op3_mdat};
wire [1:0] op4 = {i_op4_mask,i_op4_mdat};
wire [1:0] c0 = {i_c_mask[0],i_c_mdat[0]};
wire [1:0] c1 = {i_c_mask[1],i_c_mdat[1]};
wire [1:0] c2 = {i_c_mask[2],i_c_mdat[2]};
wire [1:0] c3 = {i_c_mask[3],i_c_mdat[3]};
reg [2-1:0] op4_l1,op4_l2;
reg start_l1,start_l2;
always @(posedge i_clk) begin
op4_l1 <= op4;
op4_l2 <= op4_l1;
start_l1 <= i_start;
start_l2 <= start_l1;
end
wire [2-1:0] q01,co01;
wire [2-1:0] ci01 = i_start ? c0 : co01;
sha2_sec_ti2_rm0_masked_full_adder_ti add01(
.i_clk(i_clk),.i_rnd(i_rnd[0*4+:4]),
.i_a(op0),.i_b(op1),.i_c(ci01),
.o_q(q01), .o_c(co01));
wire [2-1:0] q23,co23;
wire [2-1:0] ci23 = i_start ? c1 : co23;
sha2_sec_ti2_rm0_masked_full_adder_ti add23(
.i_clk(i_clk),.i_rnd(i_rnd[1*4+:4]),
.i_a(op2),.i_b(op3),.i_c(ci23),
.o_q(q23), .o_c(co23));
wire [2-1:0] q03,co03;
wire [2-1:0] ci03 = start_l1 ? c2 : co03;
sha2_sec_ti2_rm0_masked_full_adder_ti add03(
.i_clk(i_clk),.i_rnd(i_rnd[2*4+:4]),
.i_a(q01),.i_b(q23),.i_c(ci03),
.o_q(q03), .o_c(co03));
wire [2-1:0] q04,co04;
wire [2-1:0] ci04 = start_l2 ? c3 : co04;
sha2_sec_ti2_rm0_masked_full_adder_ti add04(
.i_clk(i_clk),.i_rnd(i_rnd[3*4+:4]),
.i_a(op4_l2),.i_b(q03),.i_c(ci04),
.o_q(q04), .o_c(co04));
always @* begin
o_dat_mdat = q04[0];
o_dat_mask = q04[1];
end
endmodule
module sha2_sec_ti2_rm0_serial_masked_add_4op (
input wire i_clk,
input wire i_start,
input wire [12-1:0] i_rnd,
input wire [2:0] i_c_mdat,
input wire [2:0] i_c_mask,
input wire i_op0_mdat,
input wire i_op1_mdat,
input wire i_op2_mdat,
input wire i_op3_mdat,
input wire i_op0_mask,
input wire i_op1_mask,
input wire i_op2_mask,
input wire i_op3_mask,
output reg o_dat_mdat,
output reg o_dat_mask
);
wire [1:0] op0 = {i_op0_mask,i_op0_mdat};
wire [1:0] op1 = {i_op1_mask,i_op1_mdat};
wire [1:0] op2 = {i_op2_mask,i_op2_mdat};
wire [1:0] op3 = {i_op3_mask,i_op3_mdat};
wire [1:0] c0 = {i_c_mask[0],i_c_mdat[0]};
wire [1:0] c1 = {i_c_mask[1],i_c_mdat[1]};
wire [1:0] c2 = {i_c_mask[2],i_c_mdat[2]};
reg start_l1;
always @(posedge i_clk) begin
start_l1 <= i_start;
end
wire [2-1:0] q01,co01;
wire [2-1:0] ci01 = i_start ? c0 : co01;
sha2_sec_ti2_rm0_masked_full_adder_ti add01(
.i_clk(i_clk),.i_rnd(i_rnd[0*4+:4]),
.i_a(op0),.i_b(op1),.i_c(ci01),
.o_q(q01), .o_c(co01));
wire [2-1:0] q23,co23;
wire [2-1:0] ci23 = i_start ? c1 : co23;
sha2_sec_ti2_rm0_masked_full_adder_ti add23(
.i_clk(i_clk),.i_rnd(i_rnd[1*4+:4]),
.i_a(op2),.i_b(op3),.i_c(ci23),
.o_q(q23), .o_c(co23));
wire [2-1:0] q03,co03;
wire [2-1:0] ci03 = start_l1 ? c2 : co03;
sha2_sec_ti2_rm0_masked_full_adder_ti add03(
.i_clk(i_clk),.i_rnd(i_rnd[2*4+:4]),
.i_a(q01),.i_b(q23),.i_c(ci03),
.o_q(q03), .o_c(co03));
always @* begin
o_dat_mdat = q03[0];
o_dat_mask = q03[1];
end
endmodule
module sha2_sec_ti2_rm0_serial_masked_add_2op (
input wire i_clk,
input wire i_start,
input wire [4-1:0] i_rnd,
input wire i_c_mdat,
input wire i_c_mask,
input wire i_op0_mdat,
input wire i_op1_mdat,
input wire i_op0_mask,
input wire i_op1_mask,
output reg o_dat_mdat,
output reg o_dat_mask
);
wire [1:0] a = {i_op0_mask,i_op0_mdat};
wire [1:0] b = {i_op1_mask,i_op1_mdat};
wire [1:0] c = {i_c_mask,i_c_mdat};
wire [2-1:0] q,co;
wire [2-1:0] ci = i_start ? c : co;
sha2_sec_ti2_rm0_masked_full_adder_ti impl(
.i_clk(i_clk),.i_rnd(i_rnd[3:0]),
.i_a(a),.i_b(b),.i_c(ci),
.o_q(q), .o_c(co));
always @* begin
o_dat_mdat = q[0];
o_dat_mask = q[1];
end
endmodule
module sha2_sec_ti2_rm0_masked_full_adder_ti(
input wire i_clk,
input wire [2-1:0] i_a,
input wire [2-1:0] i_b,
input wire [2-1:0] i_c,
input wire [3:0] i_rnd,
output reg [2-1:0] o_q,
output reg [2-1:0] o_c
);
wire [2-1:0] x0 = i_a ^ i_b;
wire [2-1:0] n0,n1;
sha2_sec_ti2_rm0_ti2_and u0(.i_clk(i_clk), .i_a(x0), .i_b(i_c), .i_rnd(i_rnd[0+:2]), .o_y(n0));
sha2_sec_ti2_rm0_ti2_and u1(.i_clk(i_clk), .i_a(i_a), .i_b(i_b), .i_rnd(i_rnd[2+:2]), .o_y(n1));
reg [2-1:0] x0_l1;
always @(posedge i_clk) x0_l1 <= x0;
reg [2-1:0] c_l1;
always @(posedge i_clk) c_l1 <= i_c;
always @* begin
o_q = x0_l1 ^ c_l1;
o_c = n0 ^ n1;
end
endmodule
module sha2_sec_ti2_rm0_remask(
input wire [1:0] a,
input wire r,
output wire [1:0] y
);
sha2_sec_ti2_rm0_xor u0(.a(a[0]), .b(r), .y(y[0]));
sha2_sec_ti2_rm0_xor u1(.a(a[1]), .b(r), .y(y[1]));
endmodule
module sha2_sec_ti2_rm0_xor_impl #(
parameter WIDTH = 1,
parameter NOTY = 0
)(
input wire [WIDTH-1:0] a,
input wire [WIDTH-1:0] b,
output reg [WIDTH-1:0] y
);
always @* y = NOTY ^ a ^ b;
endmodule
module sha2_sec_ti2_rm0_xor #(
parameter WIDTH = 1
)(
input wire [WIDTH-1:0] a,
input wire [WIDTH-1:0] b,
output wire [WIDTH-1:0] y
);
sha2_sec_ti2_rm0_xor_impl #(.WIDTH(WIDTH)) u_ITK(.a(a), .b(b), .y(y));
endmodule
module sha2_sec_ti2_rm0_plain_and(
input wire a,
input wire b,
output reg q
);
always @* q = a&b;
endmodule
module sha2_sec_ti2_rm0_plain_nand(
input wire a,
input wire b,
output reg q
);
always @* q = ~(a&b);
endmodule
module sha2_sec_ti2_rm0_ti2_and_l0 #(
parameter NOTA = 1'b0,
parameter NOTB = 1'b0,
parameter NOTY = 1'b0
)(
input wire [1:0] i_a, //WARNING: must be uniform
input wire [1:0] i_b, //WARNING: must be uniform
output reg [1:0] o_y //WARNING: non uniform
);
wire [1:0] a = i_a^ NOTA[0];
wire [1:0] b = i_b^ NOTB[0];
wire n00,n10,n01;
wire n11;
sha2_sec_ti2_rm0_plain_nand nand00_ITK(.a(a[0]), .b(b[0]), .q(n00));
sha2_sec_ti2_rm0_plain_nand nand10_ITK(.a(a[1]), .b(b[0]), .q(n10));
sha2_sec_ti2_rm0_plain_nand nand01_ITK(.a(a[0]), .b(b[1]), .q(n01));
sha2_sec_ti2_rm0_plain_nand nand11_ITK(.a(a[1]), .b(b[1]), .q(n11));
always @* begin
o_y[0] = n00 ^ n11 ^ NOTY[0];
o_y[1] = n10 ^ n01;
end
endmodule
module sha2_sec_ti2_rm0_ti2_and_l1 #(
parameter NOTA = 1'b0,
parameter NOTB = 1'b0,
parameter NOTY = 1'b0
)(
input wire i_clk,
input wire [1:0] i_a, //WARNING: must be uniform
input wire [1:0] i_b, //WARNING: must be uniform
input wire [1:0] i_rnd,
output wire [1:0] o_y //SAFE: this is uniform (remasked)
);
wire r0 = i_rnd[0];
wire r1 = i_rnd[1];
wire [1:0] a = i_a^ NOTA[0];
wire [1:0] b = i_b^ NOTB[0];
wire n00,n10,n01,n11;
sha2_sec_ti2_rm0_plain_nand nand00_ITK(.a(a[0]), .b(b[0]), .q(n00));
sha2_sec_ti2_rm0_plain_nand nand10_ITK(.a(a[1]), .b(b[0]), .q(n10));
sha2_sec_ti2_rm0_plain_nand nand01_ITK(.a(a[0]), .b(b[1]), .q(n01));
sha2_sec_ti2_rm0_plain_nand nand11_ITK(.a(a[1]), .b(b[1]), .q(n11));
reg tmp00,tmp01,tmp10,tmp11;
wire next_tmp00,next_tmp01,next_tmp10,next_tmp11;
sha2_sec_ti2_rm0_xor_impl xor00_ITK(.a(n00), .b(r0), .y(next_tmp00));
sha2_sec_ti2_rm0_xor_impl xor01_ITK(.a(n01), .b(r1), .y(next_tmp01));
sha2_sec_ti2_rm0_xor_impl xor10_ITK(.a(n10), .b(r0), .y(next_tmp10));
sha2_sec_ti2_rm0_xor_impl xor11_ITK(.a(n11), .b(r1), .y(next_tmp11));
always @(posedge i_clk) begin
tmp00 <= next_tmp00 ^ NOTY[0];
tmp01 <= next_tmp01;
tmp10 <= next_tmp10;
tmp11 <= next_tmp11;
end
sha2_sec_ti2_rm0_xor_impl u_y0_ITK(.a(tmp00), .b(tmp01), .y(o_y[0]));
sha2_sec_ti2_rm0_xor_impl u_y1_ITK(.a(tmp10), .b(tmp11), .y(o_y[1]));
endmodule
module sha2_sec_ti2_rm0_ti2_and(
input wire i_clk,
input wire [1:0] i_a,
input wire [1:0] i_b,
input wire [1:0] i_rnd,
output wire[1:0] o_y
);
sha2_sec_ti2_rm0_ti2_and_l1 #(.NOTA(0), .NOTB(0), .NOTY(0)) impl_ITK(.i_clk(i_clk),.i_a(i_a),.i_b(i_b),.i_rnd(i_rnd),.o_y(o_y));
endmodule
//` default_nettype wire
*/
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
// Date : Sun Mar 13 07:43:22 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/SKL/Desktop/ECE532/project_work/integrated/test/project_2.srcs/sources_1/ip/dcfifo_32in_32out_8kb/dcfifo_32in_32out_8kb_funcsim.v
// Design : dcfifo_32in_32out_8kb
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "dcfifo_32in_32out_8kb,fifo_generator_v12_0,{}" *) (* core_generation_info = "dcfifo_32in_32out_8kb,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=8,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=1,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=253,C_PROG_FULL_THRESH_NEGATE_VAL=252,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=8,C_RD_DEPTH=256,C_RD_FREQ=1,C_RD_PNTR_WIDTH=8,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=2,C_WR_DEPTH=256,C_WR_FREQ=1,C_WR_PNTR_WIDTH=8,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "fifo_generator_v12_0,Vivado 2015.1" *)
(* NotValidForBitStream *)
module dcfifo_32in_32out_8kb
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
wr_data_count);
input rst;
(* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [31:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [31:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
output [1:0]wr_data_count;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [7:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [7:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "8" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "32" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "32" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "1" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "512x36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "253" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "252" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "8" *)
(* C_RD_DEPTH = "256" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "8" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "2" *)
(* C_WR_DEPTH = "256" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "8" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
dcfifo_32in_32out_8kb_fifo_generator_v12_0 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[7:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[7:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module dcfifo_32in_32out_8kb_blk_mem_gen_generic_cstr
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_8kb_blk_mem_gen_prim_width \ramloop[0].ram.r
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ),
.\gic0.gc0.count_d2_reg[7] (\gic0.gc0.count_d2_reg[7] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module dcfifo_32in_32out_8kb_blk_mem_gen_prim_width
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_8kb_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ),
.\gic0.gc0.count_d2_reg[7] (\gic0.gc0.count_d2_reg[7] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module dcfifo_32in_32out_8kb_blk_mem_gen_prim_wrapper
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input [31:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35 ;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("SDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram
(.ADDRARDADDR({1'b0,\gc0.count_d1_reg[7] ,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,\gic0.gc0.count_d2_reg[7] ,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(rd_clk),
.CLKBWRCLK(wr_clk),
.DIADI(din[15:0]),
.DIBDI(din[31:16]),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(dout[15:0]),
.DOBDO(dout[31:16]),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33 }),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35 }),
.ENARDEN(tmp_ram_rd_en),
.ENBWREN(WEBWE),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(Q),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({WEBWE,WEBWE,WEBWE,WEBWE}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module dcfifo_32in_32out_8kb_blk_mem_gen_top
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_8kb_blk_mem_gen_generic_cstr \valid.cstr
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ),
.\gic0.gc0.count_d2_reg[7] (\gic0.gc0.count_d2_reg[7] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *)
module dcfifo_32in_32out_8kb_blk_mem_gen_v8_2
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_8kb_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ),
.\gic0.gc0.count_d2_reg[7] (\gic0.gc0.count_d2_reg[7] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module dcfifo_32in_32out_8kb_blk_mem_gen_v8_2_synth
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_8kb_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ),
.\gic0.gc0.count_d2_reg[7] (\gic0.gc0.count_d2_reg[7] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module dcfifo_32in_32out_8kb_clk_x_pntrs
(ram_empty_i_reg,
WR_PNTR_RD,
ram_empty_i_reg_0,
RD_PNTR_WR,
ram_full_i,
Q,
\gic0.gc0.count_reg[7] ,
\gic0.gc0.count_d1_reg[7] ,
rst_full_gen_i,
\rd_pntr_bin_reg[0]_0 ,
\gic0.gc0.count_d2_reg[7] ,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output ram_empty_i_reg;
output [7:0]WR_PNTR_RD;
output ram_empty_i_reg_0;
output [7:0]RD_PNTR_WR;
output ram_full_i;
input [7:0]Q;
input [5:0]\gic0.gc0.count_reg[7] ;
input [7:0]\gic0.gc0.count_d1_reg[7] ;
input rst_full_gen_i;
input \rd_pntr_bin_reg[0]_0 ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [7:0]Q;
wire [7:0]RD_PNTR_WR;
wire [7:0]WR_PNTR_RD;
wire [7:0]\gic0.gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire [5:0]\gic0.gc0.count_reg[7] ;
wire \gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1 ;
wire \gsync_stage[2].wr_stg_inst_n_1 ;
wire \gsync_stage[2].wr_stg_inst_n_2 ;
wire \gsync_stage[2].wr_stg_inst_n_3 ;
wire \gsync_stage[2].wr_stg_inst_n_4 ;
wire \gsync_stage[2].wr_stg_inst_n_5 ;
wire \gsync_stage[2].wr_stg_inst_n_6 ;
wire \gsync_stage[2].wr_stg_inst_n_7 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [6:0]p_0_in;
wire [6:0]p_0_in6_out;
wire [7:7]p_0_out;
wire [7:7]p_1_out;
wire [7:0]p_2_out;
wire [7:0]p_3_out;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_full_i;
wire ram_full_i_i_2_n_0;
wire ram_full_i_i_4_n_0;
wire ram_full_i_i_6_n_0;
wire ram_full_i_i_7_n_0;
wire rd_clk;
wire \rd_pntr_bin_reg[0]_0 ;
wire [7:0]rd_pntr_gc;
wire \rd_pntr_gc[0]_i_1_n_0 ;
wire \rd_pntr_gc[1]_i_1_n_0 ;
wire \rd_pntr_gc[2]_i_1_n_0 ;
wire \rd_pntr_gc[3]_i_1_n_0 ;
wire \rd_pntr_gc[4]_i_1_n_0 ;
wire \rd_pntr_gc[5]_i_1_n_0 ;
wire \rd_pntr_gc[6]_i_1_n_0 ;
wire rst_full_gen_i;
wire wr_clk;
wire [7:0]wr_pntr_gc;
dcfifo_32in_32out_8kb_synchronizer_ff \gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.rd_clk(rd_clk));
dcfifo_32in_32out_8kb_synchronizer_ff_0 \gsync_stage[1].wr_stg_inst
(.D(p_2_out),
.Q(rd_pntr_gc),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.wr_clk(wr_clk));
dcfifo_32in_32out_8kb_synchronizer_ff_1 \gsync_stage[2].rd_stg_inst
(.D(p_3_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(p_1_out),
.rd_clk(rd_clk),
.\wr_pntr_bin_reg[6] (p_0_in));
dcfifo_32in_32out_8kb_synchronizer_ff_2 \gsync_stage[2].wr_stg_inst
(.D(p_2_out),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.out(p_0_out),
.\rd_pntr_bin_reg[6] ({\gsync_stage[2].wr_stg_inst_n_1 ,\gsync_stage[2].wr_stg_inst_n_2 ,\gsync_stage[2].wr_stg_inst_n_3 ,\gsync_stage[2].wr_stg_inst_n_4 ,\gsync_stage[2].wr_stg_inst_n_5 ,\gsync_stage[2].wr_stg_inst_n_6 ,\gsync_stage[2].wr_stg_inst_n_7 }),
.wr_clk(wr_clk));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_2
(.I0(WR_PNTR_RD[6]),
.I1(Q[6]),
.I2(WR_PNTR_RD[1]),
.I3(Q[1]),
.I4(Q[0]),
.I5(WR_PNTR_RD[0]),
.O(ram_empty_i_reg_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_3
(.I0(WR_PNTR_RD[5]),
.I1(Q[5]),
.I2(WR_PNTR_RD[4]),
.I3(Q[4]),
.I4(Q[7]),
.I5(WR_PNTR_RD[7]),
.O(ram_empty_i_reg));
LUT5 #(
.INIT(32'h55554000))
ram_full_i_i_1
(.I0(rst_full_gen_i),
.I1(ram_full_i_i_2_n_0),
.I2(\rd_pntr_bin_reg[0]_0 ),
.I3(ram_full_i_i_4_n_0),
.I4(\gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1 ),
.O(ram_full_i));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2
(.I0(RD_PNTR_WR[5]),
.I1(\gic0.gc0.count_reg[7] [3]),
.I2(RD_PNTR_WR[7]),
.I3(\gic0.gc0.count_reg[7] [5]),
.I4(\gic0.gc0.count_reg[7] [4]),
.I5(RD_PNTR_WR[6]),
.O(ram_full_i_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4
(.I0(RD_PNTR_WR[2]),
.I1(\gic0.gc0.count_reg[7] [0]),
.I2(RD_PNTR_WR[3]),
.I3(\gic0.gc0.count_reg[7] [1]),
.I4(\gic0.gc0.count_reg[7] [2]),
.I5(RD_PNTR_WR[4]),
.O(ram_full_i_i_4_n_0));
LUT6 #(
.INIT(64'h9009000000000000))
ram_full_i_i_5
(.I0(RD_PNTR_WR[7]),
.I1(\gic0.gc0.count_d1_reg[7] [7]),
.I2(RD_PNTR_WR[6]),
.I3(\gic0.gc0.count_d1_reg[7] [6]),
.I4(ram_full_i_i_6_n_0),
.I5(ram_full_i_i_7_n_0),
.O(\gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1 ));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_6
(.I0(RD_PNTR_WR[0]),
.I1(\gic0.gc0.count_d1_reg[7] [0]),
.I2(RD_PNTR_WR[1]),
.I3(\gic0.gc0.count_d1_reg[7] [1]),
.I4(\gic0.gc0.count_d1_reg[7] [2]),
.I5(RD_PNTR_WR[2]),
.O(ram_full_i_i_6_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_7
(.I0(RD_PNTR_WR[3]),
.I1(\gic0.gc0.count_d1_reg[7] [3]),
.I2(RD_PNTR_WR[4]),
.I3(\gic0.gc0.count_d1_reg[7] [4]),
.I4(\gic0.gc0.count_d1_reg[7] [5]),
.I5(RD_PNTR_WR[5]),
.O(ram_full_i_i_7_n_0));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_7 ),
.Q(RD_PNTR_WR[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_6 ),
.Q(RD_PNTR_WR[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_5 ),
.Q(RD_PNTR_WR[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_4 ),
.Q(RD_PNTR_WR[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_3 ),
.Q(RD_PNTR_WR[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_2 ),
.Q(RD_PNTR_WR[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_1 ),
.Q(RD_PNTR_WR[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_out),
.Q(RD_PNTR_WR[7]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[0]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(\rd_pntr_gc[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[1]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.O(\rd_pntr_gc[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[2]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.O(\rd_pntr_gc[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[3]_i_1
(.I0(Q[3]),
.I1(Q[4]),
.O(\rd_pntr_gc[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[4]_i_1
(.I0(Q[4]),
.I1(Q[5]),
.O(\rd_pntr_gc[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[5]_i_1
(.I0(Q[5]),
.I1(Q[6]),
.O(\rd_pntr_gc[5]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[6]_i_1
(.I0(Q[6]),
.I1(Q[7]),
.O(\rd_pntr_gc[6]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[0]_i_1_n_0 ),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[1]_i_1_n_0 ),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[2]_i_1_n_0 ),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[3]_i_1_n_0 ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[4]_i_1_n_0 ),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[5]_i_1_n_0 ),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[6]_i_1_n_0 ),
.Q(rd_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[7]),
.Q(rd_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[0]),
.Q(WR_PNTR_RD[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[1]),
.Q(WR_PNTR_RD[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[2]),
.Q(WR_PNTR_RD[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[3]),
.Q(WR_PNTR_RD[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[4]),
.Q(WR_PNTR_RD[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[5]),
.Q(WR_PNTR_RD[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[6]),
.Q(WR_PNTR_RD[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_1_out),
.Q(WR_PNTR_RD[7]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[7] [0]),
.I1(\gic0.gc0.count_d2_reg[7] [1]),
.O(p_0_in6_out[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[7] [1]),
.I1(\gic0.gc0.count_d2_reg[7] [2]),
.O(p_0_in6_out[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[7] [2]),
.I1(\gic0.gc0.count_d2_reg[7] [3]),
.O(p_0_in6_out[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[3]_i_1
(.I0(\gic0.gc0.count_d2_reg[7] [3]),
.I1(\gic0.gc0.count_d2_reg[7] [4]),
.O(p_0_in6_out[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[4]_i_1
(.I0(\gic0.gc0.count_d2_reg[7] [4]),
.I1(\gic0.gc0.count_d2_reg[7] [5]),
.O(p_0_in6_out[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[5]_i_1
(.I0(\gic0.gc0.count_d2_reg[7] [5]),
.I1(\gic0.gc0.count_d2_reg[7] [6]),
.O(p_0_in6_out[5]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[6]_i_1
(.I0(\gic0.gc0.count_d2_reg[7] [6]),
.I1(\gic0.gc0.count_d2_reg[7] [7]),
.O(p_0_in6_out[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in6_out[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in6_out[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in6_out[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in6_out[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in6_out[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in6_out[5]),
.Q(wr_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in6_out[6]),
.Q(wr_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gic0.gc0.count_d2_reg[7] [7]),
.Q(wr_pntr_gc[7]));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module dcfifo_32in_32out_8kb_fifo_generator_ramfifo
(dout,
empty,
full,
wr_data_count,
rd_en,
wr_en,
rd_clk,
wr_clk,
din,
rst);
output [31:0]dout;
output empty;
output full;
output [1:0]wr_data_count;
input rd_en;
input wr_en;
input rd_clk;
input wr_clk;
input [31:0]din;
input rst;
wire RD_RST;
wire WR_RST;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gcx.clkx_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_9 ;
wire \gntv_or_sync_fifo.gl0.wr_n_1 ;
wire \gntv_or_sync_fifo.gl0.wr_n_8 ;
wire \gwas.wsts/ram_full_i ;
wire [7:0]p_0_out;
wire p_18_out;
wire [7:0]p_1_out;
wire [7:0]p_20_out;
wire [7:0]p_8_out;
wire [7:0]p_9_out;
wire rd_clk;
wire rd_en;
wire [1:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire rst_full_gen_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
wire [7:2]wr_pntr_plus2;
wire [0:0]wr_rst_i;
dcfifo_32in_32out_8kb_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.Q(p_20_out),
.RD_PNTR_WR(p_0_out),
.WR_PNTR_RD(p_1_out),
.\gic0.gc0.count_d1_reg[7] (p_8_out),
.\gic0.gc0.count_d2_reg[7] (p_9_out),
.\gic0.gc0.count_reg[7] (wr_pntr_plus2),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (wr_rst_i),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_0 ),
.ram_empty_i_reg_0(\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.ram_full_i(\gwas.wsts/ram_full_i ),
.rd_clk(rd_clk),
.\rd_pntr_bin_reg[0]_0 (\gntv_or_sync_fifo.gl0.wr_n_1 ),
.rst_full_gen_i(rst_full_gen_i),
.wr_clk(wr_clk));
dcfifo_32in_32out_8kb_rd_logic \gntv_or_sync_fifo.gl0.rd
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (p_20_out),
.Q(RD_RST),
.WR_PNTR_RD(p_1_out),
.empty(empty),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.\wr_pntr_bin_reg[5] (\gntv_or_sync_fifo.gcx.clkx_n_0 ),
.\wr_pntr_bin_reg[6] (\gntv_or_sync_fifo.gcx.clkx_n_9 ));
dcfifo_32in_32out_8kb_wr_logic \gntv_or_sync_fifo.gl0.wr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (p_9_out),
.Q(wr_pntr_plus2),
.RD_PNTR_WR(p_0_out),
.WEBWE(\gntv_or_sync_fifo.gl0.wr_n_8 ),
.full(full),
.\gic0.gc0.count_d2_reg[7] (p_8_out),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (WR_RST),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_1 ),
.ram_full_i(\gwas.wsts/ram_full_i ),
.rst_full_ff_i(rst_full_ff_i),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
dcfifo_32in_32out_8kb_memory \gntv_or_sync_fifo.mem
(.Q(rd_rst_i[0]),
.WEBWE(\gntv_or_sync_fifo.gl0.wr_n_8 ),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[7] (p_20_out),
.\gic0.gc0.count_d2_reg[7] (p_9_out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
dcfifo_32in_32out_8kb_reset_blk_ramfifo rstblk
(.Q({RD_RST,rd_rst_i}),
.\gic0.gc0.count_reg[0] ({WR_RST,wr_rst_i}),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.rst_full_ff_i(rst_full_ff_i),
.rst_full_gen_i(rst_full_gen_i),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module dcfifo_32in_32out_8kb_fifo_generator_top
(dout,
empty,
full,
wr_data_count,
rd_en,
wr_en,
rd_clk,
wr_clk,
din,
rst);
output [31:0]dout;
output empty;
output full;
output [1:0]wr_data_count;
input rd_en;
input wr_en;
input rd_clk;
input wr_clk;
input [31:0]din;
input rst;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
dcfifo_32in_32out_8kb_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "8" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "32" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "32" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_ERROR_INJECTION_TYPE = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) (* C_FAMILY = "artix7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *) (* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) (* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) (* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) (* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) (* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *) (* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "1" *) (* C_HAS_WR_RST = "0" *) (* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) (* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) (* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) (* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "512x36" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) (* C_PROG_FULL_THRESH_ASSERT_VAL = "253" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "252" *) (* C_PROG_FULL_TYPE = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "8" *) (* C_RD_DEPTH = "256" *)
(* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "8" *) (* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "2" *) (* C_WR_DEPTH = "256" *) (* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "8" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v12_0" *)
module dcfifo_32in_32out_8kb_fifo_generator_v12_0
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [31:0]din;
input wr_en;
input rd_en;
input [7:0]prog_empty_thresh;
input [7:0]prog_empty_thresh_assert;
input [7:0]prog_empty_thresh_negate;
input [7:0]prog_full_thresh;
input [7:0]prog_full_thresh_assert;
input [7:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [31:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [7:0]data_count;
output [7:0]rd_data_count;
output [1:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [7:0]prog_empty_thresh;
wire [7:0]prog_empty_thresh_assert;
wire [7:0]prog_empty_thresh_negate;
wire [7:0]prog_full_thresh;
wire [7:0]prog_full_thresh_assert;
wire [7:0]prog_full_thresh_negate;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
wire wr_rst;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
dcfifo_32in_32out_8kb_fifo_generator_v12_0_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v12_0_synth" *)
module dcfifo_32in_32out_8kb_fifo_generator_v12_0_synth
(dout,
empty,
full,
wr_data_count,
rd_en,
wr_en,
rd_clk,
wr_clk,
din,
rst);
output [31:0]dout;
output empty;
output full;
output [1:0]wr_data_count;
input rd_en;
input wr_en;
input rd_clk;
input wr_clk;
input [31:0]din;
input rst;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
dcfifo_32in_32out_8kb_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "memory" *)
module dcfifo_32in_32out_8kb_memory
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[7] ,
\gic0.gc0.count_d2_reg[7] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [7:0]\gc0.count_d1_reg[7] ;
input [7:0]\gic0.gc0.count_d2_reg[7] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [7:0]\gc0.count_d1_reg[7] ;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_8kb_blk_mem_gen_v8_2 \gbm.gbmg.gbmga.ngecc.bmg
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[7] (\gc0.count_d1_reg[7] ),
.\gic0.gc0.count_d2_reg[7] (\gic0.gc0.count_d2_reg[7] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module dcfifo_32in_32out_8kb_rd_bin_cntr
(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
ram_empty_i_reg,
WR_PNTR_RD,
rd_en,
p_18_out,
\wr_pntr_bin_reg[6] ,
\wr_pntr_bin_reg[5] ,
E,
rd_clk,
Q);
output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
output ram_empty_i_reg;
input [7:0]WR_PNTR_RD;
input rd_en;
input p_18_out;
input \wr_pntr_bin_reg[6] ;
input \wr_pntr_bin_reg[5] ;
input [0:0]E;
input rd_clk;
input [0:0]Q;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [0:0]E;
wire [0:0]Q;
wire [7:0]WR_PNTR_RD;
wire \gc0.count[7]_i_2_n_0 ;
wire p_18_out;
wire [7:0]plusOp;
wire ram_empty_i_i_4_n_0;
wire ram_empty_i_i_5_n_0;
wire ram_empty_i_i_6_n_0;
wire ram_empty_i_i_7_n_0;
wire ram_empty_i_reg;
wire rd_clk;
wire rd_en;
wire [7:0]rd_pntr_plus1;
wire \wr_pntr_bin_reg[5] ;
wire \wr_pntr_bin_reg[6] ;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(rd_pntr_plus1[0]),
.O(plusOp[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(rd_pntr_plus1[0]),
.I1(rd_pntr_plus1[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(rd_pntr_plus1[0]),
.I1(rd_pntr_plus1[1]),
.I2(rd_pntr_plus1[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h6AAA))
\gc0.count[3]_i_1
(.I0(rd_pntr_plus1[3]),
.I1(rd_pntr_plus1[0]),
.I2(rd_pntr_plus1[1]),
.I3(rd_pntr_plus1[2]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gc0.count[4]_i_1
(.I0(rd_pntr_plus1[4]),
.I1(rd_pntr_plus1[2]),
.I2(rd_pntr_plus1[1]),
.I3(rd_pntr_plus1[0]),
.I4(rd_pntr_plus1[3]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[5]_i_1
(.I0(rd_pntr_plus1[5]),
.I1(rd_pntr_plus1[3]),
.I2(rd_pntr_plus1[0]),
.I3(rd_pntr_plus1[1]),
.I4(rd_pntr_plus1[2]),
.I5(rd_pntr_plus1[4]),
.O(plusOp[5]));
LUT5 #(
.INIT(32'h6AAAAAAA))
\gc0.count[6]_i_1
(.I0(rd_pntr_plus1[6]),
.I1(rd_pntr_plus1[4]),
.I2(\gc0.count[7]_i_2_n_0 ),
.I3(rd_pntr_plus1[3]),
.I4(rd_pntr_plus1[5]),
.O(plusOp[6]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[7]_i_1
(.I0(rd_pntr_plus1[7]),
.I1(rd_pntr_plus1[5]),
.I2(rd_pntr_plus1[3]),
.I3(\gc0.count[7]_i_2_n_0 ),
.I4(rd_pntr_plus1[4]),
.I5(rd_pntr_plus1[6]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h80))
\gc0.count[7]_i_2
(.I0(rd_pntr_plus1[2]),
.I1(rd_pntr_plus1[1]),
.I2(rd_pntr_plus1[0]),
.O(\gc0.count[7]_i_2_n_0 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(rd_pntr_plus1[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [7]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(plusOp[0]),
.PRE(Q),
.Q(rd_pntr_plus1[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(plusOp[1]),
.Q(rd_pntr_plus1[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(plusOp[2]),
.Q(rd_pntr_plus1[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(plusOp[3]),
.Q(rd_pntr_plus1[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(plusOp[4]),
.Q(rd_pntr_plus1[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(plusOp[5]),
.Q(rd_pntr_plus1[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(plusOp[6]),
.Q(rd_pntr_plus1[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(Q),
.D(plusOp[7]),
.Q(rd_pntr_plus1[7]));
LUT6 #(
.INIT(64'hFF80808080808080))
ram_empty_i_i_1
(.I0(\wr_pntr_bin_reg[6] ),
.I1(\wr_pntr_bin_reg[5] ),
.I2(ram_empty_i_i_4_n_0),
.I3(ram_empty_i_i_5_n_0),
.I4(ram_empty_i_i_6_n_0),
.I5(ram_empty_i_i_7_n_0),
.O(ram_empty_i_reg));
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [2]),
.I1(WR_PNTR_RD[2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [3]),
.I3(WR_PNTR_RD[3]),
.O(ram_empty_i_i_4_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_5
(.I0(rd_pntr_plus1[6]),
.I1(WR_PNTR_RD[6]),
.I2(rd_pntr_plus1[7]),
.I3(WR_PNTR_RD[7]),
.I4(WR_PNTR_RD[2]),
.I5(rd_pntr_plus1[2]),
.O(ram_empty_i_i_5_n_0));
LUT6 #(
.INIT(64'h0090000000000090))
ram_empty_i_i_6
(.I0(rd_pntr_plus1[5]),
.I1(WR_PNTR_RD[5]),
.I2(rd_en),
.I3(p_18_out),
.I4(WR_PNTR_RD[4]),
.I5(rd_pntr_plus1[4]),
.O(ram_empty_i_i_6_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_7
(.I0(rd_pntr_plus1[3]),
.I1(WR_PNTR_RD[3]),
.I2(rd_pntr_plus1[0]),
.I3(WR_PNTR_RD[0]),
.I4(WR_PNTR_RD[1]),
.I5(rd_pntr_plus1[1]),
.O(ram_empty_i_i_7_n_0));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module dcfifo_32in_32out_8kb_rd_logic
(empty,
p_18_out,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
rd_clk,
Q,
WR_PNTR_RD,
rd_en,
\wr_pntr_bin_reg[6] ,
\wr_pntr_bin_reg[5] );
output empty;
output p_18_out;
output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
input rd_clk;
input [0:0]Q;
input [7:0]WR_PNTR_RD;
input rd_en;
input \wr_pntr_bin_reg[6] ;
input \wr_pntr_bin_reg[5] ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [0:0]Q;
wire [7:0]WR_PNTR_RD;
wire empty;
wire p_14_out;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire rpntr_n_8;
wire \wr_pntr_bin_reg[5] ;
wire \wr_pntr_bin_reg[6] ;
dcfifo_32in_32out_8kb_rd_status_flags_as \gras.rsts
(.E(p_14_out),
.Q(Q),
.empty(empty),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.\wr_pntr_bin_reg[6] (rpntr_n_8));
dcfifo_32in_32out_8kb_rd_bin_cntr rpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ),
.E(p_14_out),
.Q(Q),
.WR_PNTR_RD(WR_PNTR_RD),
.p_18_out(p_18_out),
.ram_empty_i_reg(rpntr_n_8),
.rd_clk(rd_clk),
.rd_en(rd_en),
.\wr_pntr_bin_reg[5] (\wr_pntr_bin_reg[5] ),
.\wr_pntr_bin_reg[6] (\wr_pntr_bin_reg[6] ));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module dcfifo_32in_32out_8kb_rd_status_flags_as
(empty,
p_18_out,
E,
\wr_pntr_bin_reg[6] ,
rd_clk,
Q,
rd_en);
output empty;
output p_18_out;
output [0:0]E;
input \wr_pntr_bin_reg[6] ;
input rd_clk;
input [0:0]Q;
input rd_en;
wire [0:0]E;
wire [0:0]Q;
wire empty;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire \wr_pntr_bin_reg[6] ;
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[7]_i_1
(.I0(rd_en),
.I1(p_18_out),
.O(E));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(\wr_pntr_bin_reg[6] ),
.PRE(Q),
.Q(p_18_out));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(\wr_pntr_bin_reg[6] ),
.PRE(Q),
.Q(empty));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module dcfifo_32in_32out_8kb_reset_blk_ramfifo
(rst_full_ff_i,
rst_full_gen_i,
tmp_ram_rd_en,
Q,
\gic0.gc0.count_reg[0] ,
wr_clk,
rst,
rd_clk,
p_18_out,
rd_en);
output rst_full_ff_i;
output rst_full_gen_i;
output tmp_ram_rd_en;
output [2:0]Q;
output [1:0]\gic0.gc0.count_reg[0] ;
input wr_clk;
input rst;
input rd_clk;
input p_18_out;
input rd_en;
wire [2:0]Q;
wire [1:0]\gic0.gc0.count_reg[0] ;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire rd_rst_asreg;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
wire rst;
wire rst_d1;
wire rst_d2;
wire rst_d3;
wire rst_full_gen_i;
wire rst_rd_reg1;
wire rst_rd_reg2;
wire rst_wr_reg1;
wire rst_wr_reg2;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_rst_asreg;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
assign rst_full_ff_i = rst_d2;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1
(.I0(Q[0]),
.I1(p_18_out),
.I2(rd_en),
.O(tmp_ram_rd_en));
FDCE #(
.INIT(1'b0))
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg
(.C(wr_clk),
.CE(1'b1),
.CLR(rst),
.D(rst_d3),
.Q(rst_full_gen_i));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst),
.Q(rst_d3));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg),
.Q(rd_rst_asreg_d1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg_d1),
.Q(rd_rst_asreg_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d1),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d2),
.O(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(Q[0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(Q[1]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(Q[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg),
.Q(wr_rst_asreg_d1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg_d1),
.Q(wr_rst_asreg_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d1),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d2),
.O(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ),
.Q(\gic0.gc0.count_reg[0] [0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ),
.Q(\gic0.gc0.count_reg[0] [1]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module dcfifo_32in_32out_8kb_synchronizer_ff
(D,
Q,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [7:0]D;
input [7:0]Q;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [7:0]Q;
wire [7:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign D[7:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[7]),
.Q(Q_reg[7]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module dcfifo_32in_32out_8kb_synchronizer_ff_0
(D,
Q,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] );
output [7:0]D;
input [7:0]Q;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [7:0]Q;
wire [7:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire wr_clk;
assign D[7:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[7]),
.Q(Q_reg[7]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module dcfifo_32in_32out_8kb_synchronizer_ff_1
(out,
\wr_pntr_bin_reg[6] ,
D,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [0:0]out;
output [6:0]\wr_pntr_bin_reg[6] ;
input [7:0]D;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [7:0]D;
wire [7:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
wire [6:0]\wr_pntr_bin_reg[6] ;
assign out[0] = Q_reg[7];
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[7]),
.Q(Q_reg[7]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[0]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(Q_reg[0]),
.I3(\wr_pntr_bin_reg[6] [3]),
.O(\wr_pntr_bin_reg[6] [0]));
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(\wr_pntr_bin_reg[6] [3]),
.O(\wr_pntr_bin_reg[6] [1]));
LUT6 #(
.INIT(64'h6996966996696996))
\wr_pntr_bin[2]_i_1
(.I0(Q_reg[3]),
.I1(Q_reg[7]),
.I2(Q_reg[5]),
.I3(Q_reg[6]),
.I4(Q_reg[4]),
.I5(Q_reg[2]),
.O(\wr_pntr_bin_reg[6] [2]));
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[3]_i_1
(.I0(Q_reg[4]),
.I1(Q_reg[6]),
.I2(Q_reg[5]),
.I3(Q_reg[7]),
.I4(Q_reg[3]),
.O(\wr_pntr_bin_reg[6] [3]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[4]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[4]),
.O(\wr_pntr_bin_reg[6] [4]));
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[5]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[5]),
.I2(Q_reg[7]),
.O(\wr_pntr_bin_reg[6] [5]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[6]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[7]),
.O(\wr_pntr_bin_reg[6] [6]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module dcfifo_32in_32out_8kb_synchronizer_ff_2
(out,
\rd_pntr_bin_reg[6] ,
D,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] );
output [0:0]out;
output [6:0]\rd_pntr_bin_reg[6] ;
input [7:0]D;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [7:0]D;
wire [7:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [6:0]\rd_pntr_bin_reg[6] ;
wire wr_clk;
assign out[0] = Q_reg[7];
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[7]),
.Q(Q_reg[7]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[0]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(Q_reg[0]),
.I3(\rd_pntr_bin_reg[6] [3]),
.O(\rd_pntr_bin_reg[6] [0]));
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(\rd_pntr_bin_reg[6] [3]),
.O(\rd_pntr_bin_reg[6] [1]));
LUT6 #(
.INIT(64'h6996966996696996))
\rd_pntr_bin[2]_i_1
(.I0(Q_reg[3]),
.I1(Q_reg[7]),
.I2(Q_reg[5]),
.I3(Q_reg[6]),
.I4(Q_reg[4]),
.I5(Q_reg[2]),
.O(\rd_pntr_bin_reg[6] [2]));
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[3]_i_1
(.I0(Q_reg[4]),
.I1(Q_reg[6]),
.I2(Q_reg[5]),
.I3(Q_reg[7]),
.I4(Q_reg[3]),
.O(\rd_pntr_bin_reg[6] [3]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[4]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[4]),
.O(\rd_pntr_bin_reg[6] [4]));
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[5]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[5]),
.I2(Q_reg[7]),
.O(\rd_pntr_bin_reg[6] [5]));
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[6]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[7]),
.O(\rd_pntr_bin_reg[6] [6]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module dcfifo_32in_32out_8kb_wr_bin_cntr
(ram_full_fb_i_reg,
\wr_data_count_i_reg[7] ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
S,
Q,
\gic0.gc0.count_d2_reg[7]_0 ,
RD_PNTR_WR,
wr_en,
p_1_out,
E,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] );
output ram_full_fb_i_reg;
output [3:0]\wr_data_count_i_reg[7] ;
output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
output [3:0]S;
output [5:0]Q;
output [7:0]\gic0.gc0.count_d2_reg[7]_0 ;
input [7:0]RD_PNTR_WR;
input wr_en;
input p_1_out;
input [0:0]E;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [0:0]E;
wire [5:0]Q;
wire [7:0]RD_PNTR_WR;
wire [3:0]S;
wire \gic0.gc0.count[7]_i_2_n_0 ;
wire [7:0]\gic0.gc0.count_d2_reg[7]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire p_1_out;
wire [7:0]plusOp__0;
wire ram_full_fb_i_reg;
wire wr_clk;
wire [3:0]\wr_data_count_i_reg[7] ;
wire wr_en;
wire [1:0]wr_pntr_plus2;
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(wr_pntr_plus2[0]),
.O(plusOp__0[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(wr_pntr_plus2[0]),
.I1(wr_pntr_plus2[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1
(.I0(wr_pntr_plus2[0]),
.I1(wr_pntr_plus2[1]),
.I2(Q[0]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1
(.I0(wr_pntr_plus2[1]),
.I1(wr_pntr_plus2[0]),
.I2(Q[0]),
.I3(Q[1]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gic0.gc0.count[4]_i_1
(.I0(Q[0]),
.I1(wr_pntr_plus2[0]),
.I2(wr_pntr_plus2[1]),
.I3(Q[1]),
.I4(Q[2]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gic0.gc0.count[5]_i_1
(.I0(Q[1]),
.I1(wr_pntr_plus2[1]),
.I2(wr_pntr_plus2[0]),
.I3(Q[0]),
.I4(Q[2]),
.I5(Q[3]),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[6]_i_1
(.I0(\gic0.gc0.count[7]_i_2_n_0 ),
.I1(Q[4]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[7]_i_1
(.I0(\gic0.gc0.count[7]_i_2_n_0 ),
.I1(Q[4]),
.I2(Q[5]),
.O(plusOp__0[7]));
LUT6 #(
.INIT(64'h8000000000000000))
\gic0.gc0.count[7]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(wr_pntr_plus2[1]),
.I3(wr_pntr_plus2[0]),
.I4(Q[0]),
.I5(Q[2]),
.O(\gic0.gc0.count[7]_i_2_n_0 ));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(E),
.D(wr_pntr_plus2[0]),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.Q(\gic0.gc0.count_d2_reg[7]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(wr_pntr_plus2[1]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[0]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[4]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[5]),
.Q(\gic0.gc0.count_d2_reg[7]_0 [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[7]_0 [7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[0]),
.Q(wr_pntr_plus2[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(E),
.D(plusOp__0[1]),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.Q(wr_pntr_plus2[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[2]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[3]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[4]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[5]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[6]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[7]),
.Q(Q[5]));
LUT6 #(
.INIT(64'h0090000000000090))
ram_full_i_i_3
(.I0(RD_PNTR_WR[0]),
.I1(wr_pntr_plus2[0]),
.I2(wr_en),
.I3(p_1_out),
.I4(wr_pntr_plus2[1]),
.I5(RD_PNTR_WR[1]),
.O(ram_full_fb_i_reg));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_10
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [0]),
.I1(RD_PNTR_WR[0]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_3
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [7]),
.I1(RD_PNTR_WR[7]),
.O(\wr_data_count_i_reg[7] [3]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [6]),
.I1(RD_PNTR_WR[6]),
.O(\wr_data_count_i_reg[7] [2]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_5
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [5]),
.I1(RD_PNTR_WR[5]),
.O(\wr_data_count_i_reg[7] [1]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_6
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [4]),
.I1(RD_PNTR_WR[4]),
.O(\wr_data_count_i_reg[7] [0]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_7
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [3]),
.I1(RD_PNTR_WR[3]),
.O(S[3]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_8
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [2]),
.I1(RD_PNTR_WR[2]),
.O(S[2]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_9
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [1]),
.I1(RD_PNTR_WR[1]),
.O(S[1]));
endmodule
(* ORIG_REF_NAME = "wr_dc_as" *)
module dcfifo_32in_32out_8kb_wr_dc_as
(wr_data_count,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ,
\gic0.gc0.count_d2_reg[6] ,
S,
\gic0.gc0.count_d2_reg[7] );
output [1:0]wr_data_count;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
input [6:0]\gic0.gc0.count_d2_reg[6] ;
input [3:0]S;
input [3:0]\gic0.gc0.count_d2_reg[7] ;
wire [3:0]S;
wire [6:0]\gic0.gc0.count_d2_reg[6] ;
wire [3:0]\gic0.gc0.count_d2_reg[7] ;
wire [7:0]minusOp;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire wr_clk;
wire [1:0]wr_data_count;
wire \wr_data_count_i_reg[7]_i_1_n_1 ;
wire \wr_data_count_i_reg[7]_i_1_n_2 ;
wire \wr_data_count_i_reg[7]_i_1_n_3 ;
wire \wr_data_count_i_reg[7]_i_2_n_0 ;
wire \wr_data_count_i_reg[7]_i_2_n_1 ;
wire \wr_data_count_i_reg[7]_i_2_n_2 ;
wire \wr_data_count_i_reg[7]_i_2_n_3 ;
wire [3:3]\NLW_wr_data_count_i_reg[7]_i_1_CO_UNCONNECTED ;
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(minusOp[6]),
.Q(wr_data_count[0]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(minusOp[7]),
.Q(wr_data_count[1]));
CARRY4 \wr_data_count_i_reg[7]_i_1
(.CI(\wr_data_count_i_reg[7]_i_2_n_0 ),
.CO({\NLW_wr_data_count_i_reg[7]_i_1_CO_UNCONNECTED [3],\wr_data_count_i_reg[7]_i_1_n_1 ,\wr_data_count_i_reg[7]_i_1_n_2 ,\wr_data_count_i_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,\gic0.gc0.count_d2_reg[6] [6:4]}),
.O(minusOp[7:4]),
.S(\gic0.gc0.count_d2_reg[7] ));
CARRY4 \wr_data_count_i_reg[7]_i_2
(.CI(1'b0),
.CO({\wr_data_count_i_reg[7]_i_2_n_0 ,\wr_data_count_i_reg[7]_i_2_n_1 ,\wr_data_count_i_reg[7]_i_2_n_2 ,\wr_data_count_i_reg[7]_i_2_n_3 }),
.CYINIT(1'b1),
.DI(\gic0.gc0.count_d2_reg[6] [3:0]),
.O(minusOp[3:0]),
.S(S));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module dcfifo_32in_32out_8kb_wr_logic
(full,
ram_full_fb_i_reg,
Q,
WEBWE,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
\gic0.gc0.count_d2_reg[7] ,
wr_data_count,
ram_full_i,
wr_clk,
rst_full_ff_i,
RD_PNTR_WR,
wr_en,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] );
output full;
output ram_full_fb_i_reg;
output [5:0]Q;
output [0:0]WEBWE;
output [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
output [7:0]\gic0.gc0.count_d2_reg[7] ;
output [1:0]wr_data_count;
input ram_full_i;
input wr_clk;
input rst_full_ff_i;
input [7:0]RD_PNTR_WR;
input wr_en;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [5:0]Q;
wire [7:0]RD_PNTR_WR;
wire [0:0]WEBWE;
wire full;
wire [7:0]\gic0.gc0.count_d2_reg[7] ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire p_1_out;
wire ram_full_fb_i_reg;
wire ram_full_i;
wire rst_full_ff_i;
wire wpntr_n_1;
wire wpntr_n_13;
wire wpntr_n_14;
wire wpntr_n_15;
wire wpntr_n_16;
wire wpntr_n_2;
wire wpntr_n_3;
wire wpntr_n_4;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
dcfifo_32in_32out_8kb_wr_dc_as \gwas.gwdc0.wdc
(.S({wpntr_n_13,wpntr_n_14,wpntr_n_15,wpntr_n_16}),
.\gic0.gc0.count_d2_reg[6] (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [6:0]),
.\gic0.gc0.count_d2_reg[7] ({wpntr_n_1,wpntr_n_2,wpntr_n_3,wpntr_n_4}),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count));
dcfifo_32in_32out_8kb_wr_status_flags_as \gwas.wsts
(.E(WEBWE),
.full(full),
.p_1_out(p_1_out),
.ram_full_i(ram_full_i),
.rst_full_ff_i(rst_full_ff_i),
.wr_clk(wr_clk),
.wr_en(wr_en));
dcfifo_32in_32out_8kb_wr_bin_cntr wpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ),
.E(WEBWE),
.Q(Q),
.RD_PNTR_WR(RD_PNTR_WR),
.S({wpntr_n_13,wpntr_n_14,wpntr_n_15,wpntr_n_16}),
.\gic0.gc0.count_d2_reg[7]_0 (\gic0.gc0.count_d2_reg[7] ),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.p_1_out(p_1_out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.wr_clk(wr_clk),
.\wr_data_count_i_reg[7] ({wpntr_n_1,wpntr_n_2,wpntr_n_3,wpntr_n_4}),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module dcfifo_32in_32out_8kb_wr_status_flags_as
(full,
p_1_out,
E,
ram_full_i,
wr_clk,
rst_full_ff_i,
wr_en);
output full;
output p_1_out;
output [0:0]E;
input ram_full_i;
input wr_clk;
input rst_full_ff_i;
input wr_en;
wire [0:0]E;
wire full;
wire p_1_out;
wire ram_full_i;
wire rst_full_ff_i;
wire wr_clk;
wire wr_en;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2
(.I0(wr_en),
.I1(p_1_out),
.O(E));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_full_ff_i),
.Q(p_1_out));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_full_ff_i),
.Q(full));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SDFRTN_PP_BLACKBOX_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTN_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_PP_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire buf0_out_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/29/2016 05:57:16 AM
// Design Name:
// Module Name: Testbench_FPU_Add_Subt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Testbench_FPU_mult();
parameter PERIOD = 10;
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;//
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk;
//INPUT signals
reg rst;
reg beg_FSM;
reg ack_FSM;
//Oper_Start_in signals
reg [W-1:0] Data_X;
reg [W-1:0] Data_Y;
//reg add_subt;
//Round signals signals
reg [1:0] r_mode;
//OUTPUT SIGNALS
wire overflow_flag;
wire underflow_flag;
wire ready;
wire [W-1:0] final_result_ieee;
FPU_Multiplication_Function #(
.W(W),
.EW(EW),
.SW(SW)
) inst_FPU_Multiplication_Function (
.clk (clk),
.rst (rst),
.beg_FSM (beg_FSM),
.ack_FSM (ack_FSM),
.Data_MX (Data_X),
.Data_MY (Data_Y),
.round_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (ready),
.final_result_ieee (final_result_ieee)
);
reg [W-1:0] Array_IN_1 [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
beg_FSM = 0;
ack_FSM = 0;
Data_X = 0;
Data_Y = 0;
r_mode = 2'b00;
//Abre el archivo testbench
// FileSaveData = $fopen("vector/add_single/ResultadoXilinxFLM.txt","w");
// $readmemh("vector/add_single/Hexadecimal_A.txt", Array_IN_1);
// $readmemh("vector/add_single/Hexadecimal_B.txt", Array_IN_2);
add_subt = 0;
FileSaveData = $fopen("ResultadoXilinxFLM_MULT.txt","w");
$readmemh("Hexadecimal_A.txt", Array_IN_1);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
#100 rst = 0;
$finish;
//Add stimulus here
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
task run_Arch2;
input integer FDataO;
input integer Vector_size;
begin
rst = 0;
#15 rst = 1;
#15 rst = 0;
beg_FSM = 0;
ack_FSM = 0;
contador = 0;
repeat(Vector_size) @(negedge clk) begin
//input the new values inside the operator
Data_X = Array_IN_1[contador];
Data_Y = Array_IN_2[contador];
#(PERIOD/4) beg_FSM = 1;
//Wait for the operation ready
@(posedge ready) begin
#(PERIOD+2);
ack_FSM = 1;
#4;
$fwrite(FDataO,"%h\n",final_result_ieee);
end
@(negedge clk) begin
ack_FSM = 0;
end
contador = contador + 1;
end
$fclose(FDataO);
end
endtask
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_div_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Divide pipeline synthesizable logic
// - special input cases
// - opcode pipeline
// - sign logic
// - exception logic
// - datapath control- select lines and control logic
//
///////////////////////////////////////////////////////////////////////////////
module fpu_div_ctl (
inq_in1_51,
inq_in1_54,
inq_in1_53_0_neq_0,
inq_in1_50_0_neq_0,
inq_in1_53_32_neq_0,
inq_in1_exp_eq_0,
inq_in1_exp_neq_ffs,
inq_in2_51,
inq_in2_54,
inq_in2_53_0_neq_0,
inq_in2_50_0_neq_0,
inq_in2_53_32_neq_0,
inq_in2_exp_eq_0,
inq_in2_exp_neq_ffs,
inq_op,
div_exp1,
div_dest_rdy,
inq_rnd_mode,
inq_id,
inq_in1_63,
inq_in2_63,
inq_div,
div_exp_out,
div_frac_add_52_inva,
div_frac_add_in1_neq_0,
div_frac_out_54,
d6stg_frac_0,
d6stg_frac_1,
d6stg_frac_2,
d6stg_frac_29,
d6stg_frac_30,
d6stg_frac_31,
div_frac_out_53,
div_expadd2_12,
arst_l,
grst_l,
rclk,
div_pipe_active,
d1stg_snan_sng_in1,
d1stg_snan_dbl_in1,
d1stg_snan_sng_in2,
d1stg_snan_dbl_in2,
d1stg_step,
d1stg_dblop,
d234stg_fdiv,
d3stg_fdiv,
d4stg_fdiv,
d5stg_fdiva,
d5stg_fdivb,
d5stg_fdivs,
d5stg_fdivd,
d6stg_fdiv,
d6stg_fdivs,
d6stg_fdivd,
d7stg_fdiv,
d7stg_fdivd,
d8stg_fdiv_in,
d8stg_fdivs,
d8stg_fdivd,
div_id_out_in,
div_sign_out,
div_exc_out,
div_norm_frac_in1_dbl_norm,
div_norm_frac_in1_dbl_dnrm,
div_norm_frac_in1_sng_norm,
div_norm_frac_in1_sng_dnrm,
div_norm_frac_in2_dbl_norm,
div_norm_frac_in2_dbl_dnrm,
div_norm_frac_in2_sng_norm,
div_norm_frac_in2_sng_dnrm,
div_norm_inf,
div_norm_qnan,
div_norm_zero,
div_frac_add_in2_load,
d6stg_frac_out_shl1,
d6stg_frac_out_nosh,
div_frac_add_in1_add,
div_frac_add_in1_load,
d7stg_rndup_inv,
d7stg_to_0,
d7stg_to_0_inv,
div_frac_out_add_in1,
div_frac_out_add,
div_frac_out_shl1_dbl,
div_frac_out_shl1_sng,
div_frac_out_of,
div_frac_out_load,
div_expadd1_in1_dbl,
div_expadd1_in1_sng,
div_expadd1_in2_exp_in2_dbl,
div_expadd1_in2_exp_in2_sng,
div_exp1_expadd1,
div_exp1_0835,
div_exp1_0118,
div_exp1_zero,
div_exp1_load,
div_expadd2_in1_exp_out,
div_expadd2_no_decr_inv,
div_expadd2_cin,
div_exp_out_expadd22_inv,
div_exp_out_expadd2,
div_exp_out_of,
div_exp_out_exp_out,
div_exp_out_load,
se,
si,
so
);
parameter
FDIVS= 8'h4d,
FDIVD= 8'h4e;
input inq_in1_51; // request operand 1[51]
input inq_in1_54; // request operand 1[54]
input inq_in1_53_0_neq_0; // request operand 1[53:0]!=0
input inq_in1_50_0_neq_0; // request operand 1[50:0]!=0
input inq_in1_53_32_neq_0; // request operand 1[53:32]!=0
input inq_in1_exp_eq_0; // request operand 1[62:52]==0
input inq_in1_exp_neq_ffs; // request operand 1[62:52]!=0x7ff
input inq_in2_51; // request operand 2[51]
input inq_in2_54; // request operand 2[54]
input inq_in2_53_0_neq_0; // request operand 2[53:0]!=0
input inq_in2_50_0_neq_0; // request operand 2[50:0]!=0
input inq_in2_53_32_neq_0; // request operand 2[53:32]!=0
input inq_in2_exp_eq_0; // request operand 2[62:52]==0
input inq_in2_exp_neq_ffs; // request operand 2[62:52]!=0x7ff
input [7:0] inq_op; // request opcode to op pipes
input [12:0] div_exp1; // divide exponent- intermediate value
input div_dest_rdy; // divide result req accepted for CPX
input [1:0] inq_rnd_mode; // request rounding mode to op pipes
input [4:0] inq_id; // request ID to the operation pipes
input inq_in1_63; // request operand 1 to op pipes- sign
input inq_in2_63; // request operand 2 to op pipes- sign
input inq_div; // divide pipe request
input [12:0] div_exp_out; // divide exponent output
input div_frac_add_52_inva; // div_frac_add bit[52] inverted
input div_frac_add_in1_neq_0; // div_frac_add_in1 != 0
input div_frac_out_54; // div_frac_out bit[54]
input d6stg_frac_0; // divide fraction[0]- intermediate val
input d6stg_frac_1; // divide fraction[1]- intermediate val
input d6stg_frac_2; // divide fraction[2]- intermediate val
input d6stg_frac_29; // divide fraction[29]- intermediate val
input d6stg_frac_30; // divide fraction[30]- intermediate val
input d6stg_frac_31; // divide fraction[31]- intermediate val
input div_frac_out_53; // div_frac_out bit[53]
input div_expadd2_12; // div_expadd2 bit[12]
input arst_l; // global async. reset- asserted low
input grst_l; // global sync. reset- asserted low
input rclk; // global clock
output div_pipe_active; // div pipe is executing a valid instr
output d1stg_snan_sng_in1; // operand 1 is single signalling NaN
output d1stg_snan_dbl_in1; // operand 1 is double signalling NaN
output d1stg_snan_sng_in2; // operand 2 is single signalling NaN
output d1stg_snan_dbl_in2; // operand 2 is double signalling NaN
output d1stg_step; // divide pipe load
output d1stg_dblop; // double precision operation- d1 stg
output d234stg_fdiv; // select line to div_expadd1
output d3stg_fdiv; // divide operation- divide stage 3
output d4stg_fdiv; // divide operation- divide stage 4
output d5stg_fdiva; // divide operation- divide stage 5
output d5stg_fdivb; // divide operation- divide stage 5
output d5stg_fdivs; // divide single- divide stage 5
output d5stg_fdivd; // divide double- divide stage 5
output d6stg_fdiv; // divide operation- divide stage 6
output d6stg_fdivs; // divide single- divide stage 6
output d6stg_fdivd; // divide double- divide stage 6
output d7stg_fdiv; // divide operation- divide stage 7
output d7stg_fdivd; // divide double- divide stage 7
output d8stg_fdiv_in; // div pipe output request next cycle
output d8stg_fdivs; // divide single- divide stage 8
output d8stg_fdivd; // divide double- divide stage 8
output [9:0] div_id_out_in; // div pipe output ID next cycle
output div_sign_out; // divide sign output
output [4:0] div_exc_out; // divide pipe result- exception flags
output div_norm_frac_in1_dbl_norm; // select line to div_norm
output div_norm_frac_in1_dbl_dnrm; // select line to div_norm
output div_norm_frac_in1_sng_norm; // select line to div_norm
output div_norm_frac_in1_sng_dnrm; // select line to div_norm
output div_norm_frac_in2_dbl_norm; // select line to div_norm
output div_norm_frac_in2_dbl_dnrm; // select line to div_norm
output div_norm_frac_in2_sng_norm; // select line to div_norm
output div_norm_frac_in2_sng_dnrm; // select line to div_norm
output div_norm_inf; // select line to div_norm
output div_norm_qnan; // select line to div_norm
output div_norm_zero; // select line to div_norm
output div_frac_add_in2_load; // load enable to div_frac_add_in2
output d6stg_frac_out_shl1; // select line to d6stg_frac
output d6stg_frac_out_nosh; // select line to d6stg_frac
output div_frac_add_in1_add; // select line to div_frac_add_in1
output div_frac_add_in1_load; // load enable to div_frac_add_in1
output d7stg_rndup_inv; // no rounding increment
output d7stg_to_0; // result to max finite on overflow
output d7stg_to_0_inv; // result to infinity on overflow
output div_frac_out_add_in1; // select line to div_frac_out
output div_frac_out_add; // select line to div_frac_out
output div_frac_out_shl1_dbl; // select line to div_frac_out
output div_frac_out_shl1_sng; // select line to div_frac_out
output div_frac_out_of; // select line to div_frac_out
output div_frac_out_load; // load enable to div_frac_out
output div_expadd1_in1_dbl; // select line to div_expadd1
output div_expadd1_in1_sng; // select line to div_expadd1
output div_expadd1_in2_exp_in2_dbl; // select line to div_expadd1
output div_expadd1_in2_exp_in2_sng; //select line to div_expadd1
output div_exp1_expadd1; // select line to div_exp1
output div_exp1_0835; // select line to div_exp1
output div_exp1_0118; // select line to div_exp1
output div_exp1_zero; // select line to div_exp1
output div_exp1_load; // load enable to div_exp1
output div_expadd2_in1_exp_out; // select line to div_expadd2
output div_expadd2_no_decr_inv; // no exponent decrement
output div_expadd2_cin; // carry in to 2nd exponent adder
output div_exp_out_expadd22_inv; // select line to div_exp_out
output div_exp_out_expadd2; // select line to div_exp_out
output div_exp_out_of; // overflow to exponent output
output div_exp_out_exp_out; // select line to div_exp_out
output div_exp_out_load; // load enable to div_exp_out
input se; // scan_enable
input si; // scan in
output so; // scan out
wire reset;
wire div_frac_in1_51;
wire div_frac_in1_54;
wire div_frac_in1_53_0_neq_0;
wire div_frac_in1_50_0_neq_0;
wire div_frac_in1_53_32_neq_0;
wire div_exp_in1_exp_eq_0;
wire div_exp_in1_exp_neq_ffs;
wire div_frac_in2_51;
wire div_frac_in2_54;
wire div_frac_in2_53_0_neq_0;
wire div_frac_in2_50_0_neq_0;
wire div_frac_in2_53_32_neq_0;
wire div_exp_in2_exp_eq_0;
wire div_exp_in2_exp_neq_ffs;
wire d1stg_denorm_sng_in1;
wire d1stg_denorm_dbl_in1;
wire d1stg_denorm_sng_in2;
wire d1stg_denorm_dbl_in2;
wire d2stg_denorm_sng_in2;
wire d2stg_denorm_dbl_in2;
wire d1stg_norm_sng_in1;
wire d1stg_norm_dbl_in1;
wire d1stg_norm_sng_in2;
wire d1stg_norm_dbl_in2;
wire d2stg_norm_sng_in2;
wire d2stg_norm_dbl_in2;
wire d1stg_snan_sng_in1;
wire d1stg_snan_dbl_in1;
wire d1stg_snan_sng_in2;
wire d1stg_snan_dbl_in2;
wire d1stg_qnan_sng_in1;
wire d1stg_qnan_dbl_in1;
wire d1stg_qnan_sng_in2;
wire d1stg_qnan_dbl_in2;
wire d1stg_snan_in1;
wire d1stg_snan_in2;
wire d1stg_qnan_in1;
wire d1stg_qnan_in2;
wire d1stg_nan_sng_in1;
wire d1stg_nan_dbl_in1;
wire d1stg_nan_sng_in2;
wire d1stg_nan_dbl_in2;
wire d1stg_nan_in1;
wire d1stg_nan_in2;
wire d1stg_nan_in;
wire d2stg_snan_in1;
wire d2stg_snan_in2;
wire d2stg_qnan_in1;
wire d2stg_qnan_in2;
wire d2stg_nan_in2;
wire d2stg_nan_in;
wire d1stg_inf_sng_in1;
wire d1stg_inf_dbl_in1;
wire d1stg_inf_sng_in2;
wire d1stg_inf_dbl_in2;
wire d1stg_inf_in1;
wire d1stg_inf_in2;
wire d1stg_inf_in;
wire d1stg_2inf_in;
wire d2stg_inf_in1;
wire d2stg_inf_in2;
wire d2stg_2inf_in;
wire d1stg_infnan_sng_in1;
wire d1stg_infnan_dbl_in1;
wire d1stg_infnan_sng_in2;
wire d1stg_infnan_dbl_in2;
wire d1stg_infnan_in1;
wire d1stg_infnan_in2;
wire d1stg_infnan_in;
wire d2stg_infnan_in1;
wire d2stg_infnan_in2;
wire d2stg_infnan_in;
wire d1stg_zero_in1;
wire d1stg_zero_in2;
wire d1stg_zero_in;
wire d1stg_2zero_in;
wire d2stg_zero_in1;
wire d2stg_zero_in2;
wire d2stg_zero_in;
wire d2stg_2zero_in;
wire d1stg_hold;
wire d1stg_holda;
wire d1stg_step;
wire d1stg_stepa;
wire [7:0] d1stg_op_in;
wire [7:0] d1stg_op;
wire d1stg_div_in;
wire d1stg_div;
wire [4:0] d1stg_sngopa;
wire d1stg_dblop;
wire [4:0] d1stg_dblopa;
wire d1stg_fdiv;
wire d1stg_fdivs;
wire d1stg_fdivd;
wire [2:0] d1stg_opdec;
wire d234stg_fdiv_in;
wire [2:0] d2stg_opdec;
wire d234stg_fdiv;
wire d2stg_fdiv;
wire d2stg_fdivs;
wire d2stg_fdivd;
wire [2:0] d3stg_opdec;
wire d3stg_fdiv;
wire [2:0] d4stg_opdec;
wire d4stg_fdiv;
wire d4stg_fdivs;
wire d4stg_fdivd;
wire d5stg_step;
wire [2:0] d5stg_opdec;
wire d5stg_fdiva;
wire d5stg_fdivb_in;
wire d5stg_fdivb;
wire d5stg_fdiv;
wire d5stg_fdivs;
wire d5stg_fdivd;
wire d6stg_step;
wire [2:0] d6stg_opdec_in;
wire [2:0] d6stg_opdec;
wire d6stg_fdiv;
wire d6stg_fdivs;
wire d6stg_fdivd;
wire [2:0] d7stg_opdec;
wire d7stg_fdiv;
wire d7stg_fdivs;
wire d7stg_fdivd;
wire d8stg_fdiv_in;
wire [2:0] d8stg_opdec;
wire d8stg_fdiv;
wire d8stg_fdivs;
wire d8stg_fdivd;
wire d8stg_hold;
wire d8stg_step;
wire [1:0] d1stg_rnd_mode;
wire [4:0] d1stg_id;
wire d1stg_sign1;
wire d1stg_sign2;
wire d1stg_sign;
wire div_bkend_step;
wire [1:0] div_rnd_mode;
wire [9:0] div_id_out_in;
wire [9:0] div_id_out;
wire div_sign_out;
wire [5:0] div_cnt_plus1;
wire [5:0] div_cnt_in;
wire div_cnt_step;
wire [5:0] div_cnt;
wire div_cnt_lt_step;
wire divs_cnt_lt_23_in;
wire divs_cnt_lt_23;
wire divs_cnt_lt_23a;
wire divd_cnt_lt_52_in;
wire divd_cnt_lt_52;
wire divd_cnt_lt_52a;
wire div_exc_step;
wire div_of_mask_in;
wire div_of_mask;
wire div_nv_out_in;
wire div_nv_out;
wire div_dz_out_in;
wire div_dz_out;
wire d7stg_in_of;
wire div_of_out_tmp1_in;
wire div_of_out_tmp1;
wire div_of_out_tmp2;
wire div_out_52_inv;
wire div_of_out;
wire div_uf_out_in;
wire div_uf_out;
wire div_nx_out_in;
wire div_nx_out;
wire [4:0] div_exc_out;
wire d1stg_spc_rslt;
wire div_norm_frac_in1_dbl_norm;
wire div_norm_frac_in1_dbl_dnrm;
wire div_norm_frac_in1_sng_norm;
wire div_norm_frac_in1_sng_dnrm;
wire div_norm_frac_in2_dbl_norm;
wire div_norm_frac_in2_dbl_dnrm;
wire div_norm_frac_in2_sng_norm;
wire div_norm_frac_in2_sng_dnrm;
wire div_norm_inf;
wire div_norm_qnan;
wire div_norm_zero;
wire div_frac_add_in2_load;
wire d6stg_frac_out_shl1;
wire d6stg_frac_out_nosh;
wire div_frac_add_in1_add;
wire div_frac_add_in1_load;
wire d7stg_lsb_in;
wire d7stg_grd_in;
wire d7stg_stk_in;
wire d7stg_lsb;
wire d7stg_grd;
wire d7stg_stk;
wire d7stg_rndup;
wire d7stg_rndup_inv;
wire d7stg_to_0;
wire d7stg_to_0_inv;
wire div_frac_out_add_in1;
wire div_frac_out_add;
wire div_frac_out_shl1_dbl;
wire div_frac_out_shl1_sng;
wire div_frac_out_of;
wire div_frac_out_load;
wire div_expadd1_in1_dbl_in;
wire div_expadd1_in1_dbl;
wire div_expadd1_in1_sng_in;
wire div_expadd1_in1_sng;
wire div_expadd1_in2_exp_in2_dbl;
wire div_expadd1_in2_exp_in2_sng;
wire div_exp1_expadd1;
wire div_exp1_0835;
wire div_exp1_0118;
wire div_exp1_zero;
wire d2stg_max_exp;
wire d2stg_zero_exp;
wire div_exp1_load;
wire div_expadd2_in1_exp_out_in;
wire div_expadd2_in1_exp_out;
wire div_expadd2_no_decr_inv_in;
wire div_expadd2_no_decr_load;
wire div_expadd2_no_decr_inv;
wire div_expadd2_cin;
wire div_exp_out_zero;
wire div_exp_out_expadd22_inv;
wire div_exp_out_expadd2;
wire div_exp_out_of;
wire div_exp_out_exp_out;
wire div_exp_out_load;
wire div_pipe_active_in;
wire div_pipe_active;
dffrl_async #(1) dffrl_div_ctl (
.din (grst_l),
.clk (rclk),
.rst_l(arst_l),
.q (div_ctl_rst_l),
.se (se),
.si (),
.so ()
);
assign reset= (!div_ctl_rst_l);
///////////////////////////////////////////////////////////////////////////////
//
// Divide pipeline special input cases.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(1) i_div_frac_in1_51 (
.din (inq_in1_51),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in1_51),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in1_54 (
.din (inq_in1_54),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in1_54),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in1_53_0_neq_0 (
.din (inq_in1_53_0_neq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in1_53_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in1_50_0_neq_0 (
.din (inq_in1_50_0_neq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in1_50_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in1_53_32_neq_0 (
.din (inq_in1_53_32_neq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in1_53_32_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_exp_in1_exp_eq_0 (
.din (inq_in1_exp_eq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_exp_in1_exp_eq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_exp_in1_exp_neq_ffs (
.din (inq_in1_exp_neq_ffs),
.en (d1stg_step),
.clk (rclk),
.q (div_exp_in1_exp_neq_ffs),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in2_51 (
.din (inq_in2_51),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in2_51),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in2_54 (
.din (inq_in2_54),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in2_54),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in2_53_0_neq_0 (
.din (inq_in2_53_0_neq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in2_53_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in2_50_0_neq_0 (
.din (inq_in2_50_0_neq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in2_50_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in2_53_32_neq_0 (
.din (inq_in2_53_32_neq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in2_53_32_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_exp_in2_exp_eq_0 (
.din (inq_in2_exp_eq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_exp_in2_exp_eq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_exp_in2_exp_neq_ffs (
.din (inq_in2_exp_neq_ffs),
.en (d1stg_step),
.clk (rclk),
.q (div_exp_in2_exp_neq_ffs),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Denorm divide inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_denorm_sng_in1= div_exp_in1_exp_eq_0 && d1stg_sngopa[0];
assign d1stg_denorm_dbl_in1= div_exp_in1_exp_eq_0 && d1stg_dblopa[0];
assign d1stg_denorm_sng_in2= div_exp_in2_exp_eq_0 && d1stg_sngopa[0];
assign d1stg_denorm_dbl_in2= div_exp_in2_exp_eq_0 && d1stg_dblopa[0];
dff #(1) i_d2stg_denorm_sng_in2 (
.din (d1stg_denorm_sng_in2),
.clk (rclk),
.q (d2stg_denorm_sng_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_denorm_dbl_in2 (
.din (d1stg_denorm_dbl_in2),
.clk (rclk),
.q (d2stg_denorm_dbl_in2),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Non-denorm divide inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_norm_sng_in1= (!div_exp_in1_exp_eq_0) && d1stg_sngopa[0];
assign d1stg_norm_dbl_in1= (!div_exp_in1_exp_eq_0) && d1stg_dblopa[0];
assign d1stg_norm_sng_in2= (!div_exp_in2_exp_eq_0) && d1stg_sngopa[0];
assign d1stg_norm_dbl_in2= (!div_exp_in2_exp_eq_0) && d1stg_dblopa[0];
dff #(1) i_d2stg_norm_sng_in2 (
.din (d1stg_norm_sng_in2),
.clk (rclk),
.q (d2stg_norm_sng_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_norm_dbl_in2 (
.din (d1stg_norm_dbl_in2),
.clk (rclk),
.q (d2stg_norm_dbl_in2),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Nan divide inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_snan_sng_in1= (!div_exp_in1_exp_neq_ffs) && (!div_frac_in1_54)
&& div_frac_in1_53_32_neq_0 && d1stg_sngopa[1];
assign d1stg_snan_dbl_in1= (!div_exp_in1_exp_neq_ffs) && (!div_frac_in1_51)
&& div_frac_in1_50_0_neq_0 && d1stg_dblopa[1];
assign d1stg_snan_sng_in2= (!div_exp_in2_exp_neq_ffs) && (!div_frac_in2_54)
&& div_frac_in2_53_32_neq_0 && d1stg_sngopa[1];
assign d1stg_snan_dbl_in2= (!div_exp_in2_exp_neq_ffs) && (!div_frac_in2_51)
&& div_frac_in2_50_0_neq_0 && d1stg_dblopa[1];
assign d1stg_qnan_sng_in1= (!div_exp_in1_exp_neq_ffs) && div_frac_in1_54
&& d1stg_sngopa[1];
assign d1stg_qnan_dbl_in1= (!div_exp_in1_exp_neq_ffs) && div_frac_in1_51
&& d1stg_dblopa[1];
assign d1stg_qnan_sng_in2= (!div_exp_in2_exp_neq_ffs) && div_frac_in2_54
&& d1stg_sngopa[1];
assign d1stg_qnan_dbl_in2= (!div_exp_in2_exp_neq_ffs) && div_frac_in2_51
&& d1stg_dblopa[1];
assign d1stg_snan_in1= d1stg_snan_sng_in1 || d1stg_snan_dbl_in1;
assign d1stg_snan_in2= d1stg_snan_sng_in2 || d1stg_snan_dbl_in2;
assign d1stg_qnan_in1= d1stg_qnan_sng_in1 || d1stg_qnan_dbl_in1;
assign d1stg_qnan_in2= d1stg_qnan_sng_in2 || d1stg_qnan_dbl_in2;
assign d1stg_nan_sng_in1= (!div_exp_in1_exp_neq_ffs)
&& (div_frac_in1_54 || div_frac_in1_53_32_neq_0)
&& d1stg_sngopa[2];
assign d1stg_nan_dbl_in1= (!div_exp_in1_exp_neq_ffs)
&& (div_frac_in1_51 || div_frac_in1_50_0_neq_0)
&& d1stg_dblopa[2];
assign d1stg_nan_sng_in2= (!div_exp_in2_exp_neq_ffs)
&& (div_frac_in2_54 || div_frac_in2_53_32_neq_0)
&& d1stg_sngopa[2];
assign d1stg_nan_dbl_in2= (!div_exp_in2_exp_neq_ffs)
&& (div_frac_in2_51 || div_frac_in2_50_0_neq_0)
&& d1stg_dblopa[2];
assign d1stg_nan_in1= d1stg_nan_sng_in1 || d1stg_nan_dbl_in1;
assign d1stg_nan_in2= d1stg_nan_sng_in2 || d1stg_nan_dbl_in2;
assign d1stg_nan_in= d1stg_nan_in1 || d1stg_nan_in2;
dff #(1) i_d2stg_snan_in1 (
.din (d1stg_snan_in1),
.clk (rclk),
.q (d2stg_snan_in1),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_snan_in2 (
.din (d1stg_snan_in2),
.clk (rclk),
.q (d2stg_snan_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_qnan_in1 (
.din (d1stg_qnan_in1),
.clk (rclk),
.q (d2stg_qnan_in1),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_qnan_in2 (
.din (d1stg_qnan_in2),
.clk (rclk),
.q (d2stg_qnan_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_nan_in2 (
.din (d1stg_nan_in2),
.clk (rclk),
.q (d2stg_nan_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_nan_in (
.din (d1stg_nan_in),
.clk (rclk),
.q (d2stg_nan_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Infinity divide inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_inf_sng_in1= (!div_exp_in1_exp_neq_ffs)
&& (!div_frac_in1_54) && (!div_frac_in1_53_32_neq_0)
&& d1stg_sngopa[2];
assign d1stg_inf_dbl_in1= (!div_exp_in1_exp_neq_ffs)
&& (!div_frac_in1_51) && (!div_frac_in1_50_0_neq_0)
&& d1stg_dblopa[2];
assign d1stg_inf_sng_in2= (!div_exp_in2_exp_neq_ffs)
&& (!div_frac_in2_54) && (!div_frac_in2_53_32_neq_0)
&& d1stg_sngopa[2];
assign d1stg_inf_dbl_in2= (!div_exp_in2_exp_neq_ffs)
&& (!div_frac_in2_51) && (!div_frac_in2_50_0_neq_0)
&& d1stg_dblopa[2];
assign d1stg_inf_in1= d1stg_inf_sng_in1 || d1stg_inf_dbl_in1;
assign d1stg_inf_in2= d1stg_inf_sng_in2 || d1stg_inf_dbl_in2;
assign d1stg_inf_in= d1stg_inf_in1 || d1stg_inf_in2;
assign d1stg_2inf_in= d1stg_inf_in1 && d1stg_inf_in2;
dff #(1) i_d2stg_inf_in1 (
.din (d1stg_inf_in1),
.clk (rclk),
.q (d2stg_inf_in1),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_inf_in2 (
.din (d1stg_inf_in2),
.clk (rclk),
.q (d2stg_inf_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_2inf_in (
.din (d1stg_2inf_in),
.clk (rclk),
.q (d2stg_2inf_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Infinity/Nan divide inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_infnan_sng_in1= (!div_exp_in1_exp_neq_ffs) && d1stg_sngopa[3];
assign d1stg_infnan_dbl_in1= (!div_exp_in1_exp_neq_ffs) && d1stg_dblopa[3];
assign d1stg_infnan_sng_in2= (!div_exp_in2_exp_neq_ffs) && d1stg_sngopa[3];
assign d1stg_infnan_dbl_in2= (!div_exp_in2_exp_neq_ffs) && d1stg_dblopa[3];
assign d1stg_infnan_in1= d1stg_infnan_sng_in1 || d1stg_infnan_dbl_in1;
assign d1stg_infnan_in2= d1stg_infnan_sng_in2 || d1stg_infnan_dbl_in2;
assign d1stg_infnan_in= d1stg_infnan_in1 || d1stg_infnan_in2;
dff #(1) i_d2stg_infnan_in1 (
.din (d1stg_infnan_in1),
.clk (rclk),
.q (d2stg_infnan_in1),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_infnan_in2 (
.din (d1stg_infnan_in2),
.clk (rclk),
.q (d2stg_infnan_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_infnan_in (
.din (d1stg_infnan_in),
.clk (rclk),
.q (d2stg_infnan_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Zero divide inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_zero_in1= div_exp_in1_exp_eq_0
&& (!div_frac_in1_53_0_neq_0) && (!div_frac_in1_54);
assign d1stg_zero_in2= div_exp_in2_exp_eq_0
&& (!div_frac_in2_53_0_neq_0) && (!div_frac_in2_54);
assign d1stg_zero_in= d1stg_zero_in1 || d1stg_zero_in2;
assign d1stg_2zero_in= d1stg_zero_in1 && d1stg_zero_in2;
dff #(1) i_d2stg_zero_in1 (
.din (d1stg_zero_in1),
.clk (rclk),
.q (d2stg_zero_in1),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_zero_in2 (
.din (d1stg_zero_in2),
.clk (rclk),
.q (d2stg_zero_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_zero_in (
.din (d1stg_zero_in),
.clk (rclk),
.q (d2stg_zero_in),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_2zero_in (
.din (d1stg_2zero_in),
.clk (rclk),
.q (d2stg_2zero_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Floating point divide control pipeline.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide pipeline input.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_hold= d1stg_div
|| d234stg_fdiv
|| divs_cnt_lt_23
|| divd_cnt_lt_52;
assign d1stg_holda= d1stg_div
|| d234stg_fdiv
|| divs_cnt_lt_23a
|| divd_cnt_lt_52a;
assign d1stg_step= (!d1stg_hold);
assign d1stg_stepa= (!d1stg_holda);
assign d1stg_op_in[7:0]= ({8{d1stg_stepa}}
& (inq_op[7:0] & {8{inq_div}}));
dffr #(8) i_d1stg_op (
.din (d1stg_op_in[7:0]),
.rst (reset),
.clk (rclk),
.q (d1stg_op[7:0]),
.se (se),
.si (),
.so ()
);
assign d1stg_div_in= inq_div && d1stg_stepa;
dffr #(1) i_d1stg_div (
.din (d1stg_div_in),
.rst (reset),
.clk (rclk),
.q (d1stg_div),
.se (se),
.si (),
.so ()
);
dffe #(5) i_d1stg_sngopa (
.din ({5{inq_op[0]}}),
.en (d1stg_stepa),
.clk (rclk),
.q (d1stg_sngopa[4:0]),
.se (se),
.si (),
.so ()
);
dffe #(1) i_d1stg_dblop (
.din (inq_op[1]),
.en (d1stg_stepa),
.clk (rclk),
.q (d1stg_dblop),
.se (se),
.si (),
.so ()
);
dffe #(5) i_d1stg_dblopa (
.din ({5{inq_op[1]}}),
.en (d1stg_stepa),
.clk (rclk),
.q (d1stg_dblopa[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode decode- divide stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_fdiv= (d1stg_op[7:0]==FDIVS) || (d1stg_op[7:0]==FDIVD);
assign d1stg_fdivs= (d1stg_op[7:0]==FDIVS);
assign d1stg_fdivd= (d1stg_op[7:0]==FDIVD);
assign d1stg_opdec[2:0]= {d1stg_fdiv,
d1stg_fdivs,
d1stg_fdivd};
assign d234stg_fdiv_in= d1stg_fdiv || d2stg_fdiv || d3stg_fdiv;
dffr #(3) i_d2stg_opdec (
.din (d1stg_opdec[2:0]),
.rst (reset),
.clk (rclk),
.q (d2stg_opdec[2:0]),
.se (se),
.si (),
.so ()
);
dffr #(1) i_d234stg_fdiv (
.din (d234stg_fdiv_in),
.rst (reset),
.clk (rclk),
.q (d234stg_fdiv),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign d2stg_fdiv= d2stg_opdec[2];
assign d2stg_fdivs= d2stg_opdec[1];
assign d2stg_fdivd= d2stg_opdec[0];
dffr #(3) i_d3stg_opdec (
.din (d2stg_opdec[2:0]),
.rst (reset),
.clk (rclk),
.q (d3stg_opdec[2:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign d3stg_fdiv= d3stg_opdec[2];
//assign d3stg_fdivs= d3stg_opdec[1];
//assign d3stg_fdivd= d3stg_opdec[0];
dffr #(3) i_d4stg_opdec (
.din (d3stg_opdec[2:0]),
.rst (reset),
.clk (rclk),
.q (d4stg_opdec[2:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide stage 4.
//
///////////////////////////////////////////////////////////////////////////////
assign d4stg_fdiv= d4stg_opdec[2];
assign d4stg_fdivs= d4stg_opdec[1];
assign d4stg_fdivd= d4stg_opdec[0];
assign d5stg_step= (!d5stg_fdiv) || d6stg_step;
dffre #(3) i_d5stg_opdec (
.din (d4stg_opdec[2:0]),
.en (d5stg_step),
.rst (reset),
.clk (rclk),
.q (d5stg_opdec[2:0]),
.se (se),
.si (),
.so ()
);
dffre #(1) i_d5stg_fdiva (
.din (d4stg_fdiv),
.en (d5stg_step),
.rst (reset),
.clk (rclk),
.q (d5stg_fdiva),
.se (se),
.si (),
.so ()
);
assign d5stg_fdivb_in= ((d5stg_step && d4stg_fdiv)
|| ((!d5stg_step) && d5stg_fdiv))
&& (!reset);
dff #(1) i_d5stg_fdivb (
.din (d5stg_fdivb_in),
.clk (rclk),
.q (d5stg_fdivb),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide stage 5.
//
///////////////////////////////////////////////////////////////////////////////
assign d5stg_fdiv= d5stg_opdec[2];
assign d5stg_fdivs= d5stg_opdec[1];
assign d5stg_fdivd= d5stg_opdec[0];
assign d6stg_step= (d5stg_fdivd && (div_cnt[5:0]==6'h36))
|| (d5stg_fdivs && (div_cnt[5:0]==6'h19))
|| (d5stg_fdiv && ((({7'b0, div_cnt[5:0]}==div_exp1[12:0])
&& (div_exp1[12:0]!=13'b0))
|| (({7'b0, div_cnt[5:0]}==div_exp1[12:0])
&& (div_exp1[12:0]==13'b0)
&& d8stg_step)
|| (div_exp1[12] && d8stg_step)));
assign d6stg_opdec_in[2:0]= ({3{d6stg_step}}
& d5stg_opdec[2:0]);
dffr #(3) i_d6stg_opdec (
.din (d6stg_opdec_in[2:0]),
.rst (reset),
.clk (rclk),
.q (d6stg_opdec[2:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide stage 6.
//
///////////////////////////////////////////////////////////////////////////////
assign d6stg_fdiv= d6stg_opdec[2];
assign d6stg_fdivs= d6stg_opdec[1];
assign d6stg_fdivd= d6stg_opdec[0];
dffr #(3) i_d7stg_opdec (
.din (d6stg_opdec[2:0]),
.rst (reset),
.clk (rclk),
.q (d7stg_opdec[2:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide stage 7.
//
///////////////////////////////////////////////////////////////////////////////
assign d7stg_fdiv= d7stg_opdec[2];
assign d7stg_fdivs= d7stg_opdec[1];
assign d7stg_fdivd= d7stg_opdec[0];
assign d8stg_fdiv_in= (d8stg_step && (!reset) && d7stg_fdiv)
|| ((!d8stg_step) && (!reset) && d8stg_fdiv);
dffre #(3) i_d8stg_opdec (
.din (d7stg_opdec[2:0]),
.en (d8stg_step),
.rst (reset),
.clk (rclk),
.q (d8stg_opdec[2:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide pipeline output.
//
///////////////////////////////////////////////////////////////////////////////
assign d8stg_fdiv= d8stg_opdec[2];
assign d8stg_fdivs= d8stg_opdec[1];
assign d8stg_fdivd= d8stg_opdec[0];
assign d8stg_hold= d8stg_fdiv && (!div_dest_rdy);
assign d8stg_step= (!d8stg_hold);
// Austin update
// Power management update
assign div_pipe_active_in = // div pipe is executing a valid instr
d1stg_fdiv || d2stg_fdiv || d3stg_fdiv || d4stg_fdiv |
d5stg_fdiv || d6stg_fdiv || d7stg_fdiv || d8stg_fdiv ;
dffre #(1) i_div_pipe_active (
.din (div_pipe_active_in),
.en (1'b1),
.rst (reset),
.clk (rclk),
.q (div_pipe_active),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide information pipeline
// - rounding mode
// - ID
// - sign logic
// Front end of the pipeline.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(2) i_d1stg_rnd_mode (
.din (inq_rnd_mode[1:0]),
.en (d1stg_stepa),
.clk (rclk),
.q (d1stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe #(5) i_d1stg_id (
.din (inq_id[4:0]),
.en (d1stg_stepa),
.clk (rclk),
.q (d1stg_id[4:0]),
.se (se),
.si (),
.so ()
);
dffe #(1) i_d1stg_sign1 (
.din (inq_in1_63),
.en (d1stg_stepa),
.clk (rclk),
.q (d1stg_sign1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_d1stg_sign2 (
.din (inq_in2_63),
.en (d1stg_stepa),
.clk (rclk),
.q (d1stg_sign2),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide information pipeline
// - rounding mode
// - ID
// - sign logic
// Back end of the pipeline.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_sign= ((d1stg_sign1
&& (!d2stg_snan_in2)
&& (!(d2stg_qnan_in2 && (!d2stg_snan_in1))))
^ (d1stg_sign2
&& (!(d2stg_snan_in1 && (!d2stg_snan_in2)))
&& (!(d2stg_qnan_in1 && (!d2stg_nan_in2)))))
&& (!(d2stg_2inf_in || d2stg_2zero_in));
assign div_bkend_step= (d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step);
dffe #(2) i_div_rnd_mode (
.din (d1stg_rnd_mode[1:0]),
.en (div_bkend_step),
.clk (rclk),
.q (div_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
assign div_id_out_in[9:0]= ({10{div_bkend_step}}
& {(d1stg_id[4:2]==3'o7),
(d1stg_id[4:2]==3'o6),
(d1stg_id[4:2]==3'o5),
(d1stg_id[4:2]==3'o4),
(d1stg_id[4:2]==3'o3),
(d1stg_id[4:2]==3'o2),
(d1stg_id[4:2]==3'o1),
(d1stg_id[4:2]==3'o0),
d1stg_id[1:0]})
| ({10{(!div_bkend_step)}}
& div_id_out[9:0]);
dff #(10) i_div_id_out (
.din (div_id_out_in[9:0]),
.clk (rclk),
.q (div_id_out[9:0]),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_sign_out (
.din (d1stg_sign),
.en (div_bkend_step),
.clk (rclk),
.q (div_sign_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide counter.
//
// Tracks the number of subtraction iterations.
//
///////////////////////////////////////////////////////////////////////////////
assign div_cnt_plus1[5:0]= (div_cnt[5:0] + 6'h01);
assign div_cnt_in[5:0]= ({6{(d5stg_fdiv && d8stg_step)}}
& div_cnt_plus1[5:0])
| ({6{d4stg_fdiv}}
& 6'b0);
assign div_cnt_step= (d5stg_fdiv && d8stg_step)
|| d4stg_fdiv;
dffre #(6) i_div_cnt (
.din (div_cnt_in[5:0]),
.en (div_cnt_step),
.rst (reset),
.clk (rclk),
.q (div_cnt[5:0]),
.se (se),
.si (),
.so ()
);
assign div_cnt_lt_step= (!d5stg_fdiv) || d6stg_step || d8stg_step;
assign divs_cnt_lt_23_in= d4stg_fdivs
|| (d5stg_fdivs && (!d6stg_step) && (div_cnt_plus1[5:0]<6'h17));
dffre #(1) i_divs_cnt_lt_23 (
.din (divs_cnt_lt_23_in),
.en (div_cnt_lt_step),
.rst (reset),
.clk (rclk),
.q (divs_cnt_lt_23),
.se (se),
.si (),
.so ()
);
dffre #(1) i_divs_cnt_lt_23a (
.din (divs_cnt_lt_23_in),
.en (div_cnt_lt_step),
.rst (reset),
.clk (rclk),
.q (divs_cnt_lt_23a),
.se (se),
.si (),
.so ()
);
assign divd_cnt_lt_52_in= d4stg_fdivd
|| (d5stg_fdivd && (!d6stg_step) && (div_cnt_plus1[5:0]<6'h34));
dffre #(1) i_divd_cnt_lt_52 (
.din (divd_cnt_lt_52_in),
.en (div_cnt_lt_step),
.rst (reset),
.clk (rclk),
.q (divd_cnt_lt_52),
.se (se),
.si (),
.so ()
);
dffre #(1) i_divd_cnt_lt_52a (
.din (divd_cnt_lt_52_in),
.en (div_cnt_lt_step),
.rst (reset),
.clk (rclk),
.q (divd_cnt_lt_52a),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide exception logic.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Divide overflow exception enabled.
//
///////////////////////////////////////////////////////////////////////////////
assign div_exc_step= d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step;
assign div_of_mask_in= (!(d1stg_infnan_in || d1stg_zero_in));
dffe #(1) i_div_of_mask (
.din (div_of_mask_in),
.en (div_exc_step),
.clk (rclk),
.q (div_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide invalid exception.
//
///////////////////////////////////////////////////////////////////////////////
assign div_nv_out_in= d1stg_snan_in1 || d1stg_snan_in2 || d1stg_2inf_in
|| d1stg_2zero_in;
dffe #(1) i_div_nv_out (
.din (div_nv_out_in),
.en (div_exc_step),
.clk (rclk),
.q (div_nv_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide by zero exception.
//
///////////////////////////////////////////////////////////////////////////////
assign div_dz_out_in= d1stg_zero_in2 && (!d1stg_zero_in1)
&& (!d1stg_infnan_in1);
dffe #(1) i_div_dz_out (
.din (div_dz_out_in),
.en (div_exc_step),
.clk (rclk),
.q (div_dz_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide overflow exception.
//
///////////////////////////////////////////////////////////////////////////////
assign d7stg_in_of= ((!div_exp_out[12])
&& d7stg_fdivd
&& (div_exp_out[11] || (&div_exp_out[10:0]))
&& div_of_mask)
|| ((!div_exp_out[12])
&& d7stg_fdivs
&& ((|div_exp_out[11:8]) || (&div_exp_out[7:0]))
&& div_of_mask);
assign div_of_out_tmp1_in= ((!div_exp_out[12])
&& d7stg_fdivd
&& (&div_exp_out[10:1])
&& d7stg_rndup
&& div_of_mask)
|| ((!div_exp_out[12])
&& d7stg_fdivs
&& (&div_exp_out[7:1])
&& d7stg_rndup
&& div_of_mask);
dffe #(1) i_div_of_out_tmp1 (
.din (div_of_out_tmp1_in),
.en (d7stg_fdiv),
.clk (rclk),
.q (div_of_out_tmp1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_of_out_tmp2 (
.din (d7stg_in_of),
.en (d7stg_fdiv),
.clk (rclk),
.q (div_of_out_tmp2),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_out_52_inv (
.din (div_frac_add_52_inva),
.en (d7stg_fdiv),
.clk (rclk),
.q (div_out_52_inv),
// Austin update
// include se pin
.se (se),
.si (),
.so ()
);
assign div_of_out= div_of_out_tmp2
|| (div_of_out_tmp1 && (!div_out_52_inv));
///////////////////////////////////////////////////////////////////////////////
//
// Divide underflow exception.
//
///////////////////////////////////////////////////////////////////////////////
assign div_uf_out_in= ((!(|div_exp_out[11:0]))
&& (div_frac_add_in1_neq_0
|| d7stg_grd
|| d7stg_stk)
&& div_of_mask)
|| (div_exp_out[12]
&& div_of_mask);
dffe #(1) i_div_uf_out (
.din (div_uf_out_in),
.en (d7stg_fdiv),
.clk (rclk),
.q (div_uf_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide inexact exception.
//
///////////////////////////////////////////////////////////////////////////////
assign div_nx_out_in= d7stg_grd || d7stg_stk;
dffe #(1) i_div_nx_out (
.din (div_nx_out_in),
.en (d7stg_fdiv),
.clk (rclk),
.q (div_nx_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide exception output.
//
///////////////////////////////////////////////////////////////////////////////
// Austin update
// Overflow is always accompanied by inexact.
// Previously this was handled within the FFU.
// assign div_exc_out[4:0]= {div_nv_out, div_of_out, div_uf_out, div_dz_out,
// div_nx_out};
assign div_exc_out[4:0] =
{div_nv_out,
div_of_out,
div_uf_out,
div_dz_out,
(div_nx_out || div_of_out)}; // Overflow is always accompanied by inexact
///////////////////////////////////////////////////////////////////////////////
//
// Divide pipeline control logic.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- divide normalization and special input injection.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_spc_rslt= (d1stg_inf_in || d1stg_zero_in) && (!d1stg_nan_in);
assign div_norm_frac_in1_dbl_norm= d1stg_fdiv && d1stg_norm_dbl_in1
&& (!d1stg_snan_dbl_in2)
&& ((!d1stg_qnan_dbl_in2) || d1stg_snan_dbl_in1)
&& (!d1stg_spc_rslt);
assign div_norm_frac_in1_dbl_dnrm= d1stg_fdiv && d1stg_denorm_dbl_in1
&& (!d1stg_snan_dbl_in2)
&& (!d1stg_qnan_dbl_in2)
&& (!d1stg_spc_rslt);
assign div_norm_frac_in1_sng_norm= d1stg_fdiv && d1stg_norm_sng_in1
&& (!d1stg_snan_sng_in2)
&& ((!d1stg_qnan_sng_in2) || d1stg_snan_sng_in1)
&& (!d1stg_spc_rslt);
assign div_norm_frac_in1_sng_dnrm= d1stg_fdiv && d1stg_denorm_sng_in1
&& (!d1stg_snan_sng_in2)
&& (!d1stg_qnan_sng_in2)
&& (!d1stg_spc_rslt);
assign div_norm_frac_in2_dbl_norm= (d2stg_fdiv && d2stg_norm_dbl_in2
&& (!d2stg_infnan_in) && (!d2stg_zero_in))
|| (d1stg_fdiv && d1stg_snan_dbl_in2)
|| (d1stg_fdiv && d1stg_qnan_dbl_in2 && (!d1stg_snan_dbl_in1));
assign div_norm_frac_in2_dbl_dnrm= d2stg_fdiv && d2stg_denorm_dbl_in2
&& (!d2stg_infnan_in) && (!d2stg_zero_in);
assign div_norm_frac_in2_sng_norm= (d2stg_fdiv && d2stg_norm_sng_in2
&& (!d2stg_infnan_in) && (!d2stg_zero_in))
|| (d1stg_fdiv && d1stg_snan_sng_in2)
|| (d1stg_fdiv && d1stg_qnan_sng_in2 && (!d1stg_snan_sng_in1));
assign div_norm_frac_in2_sng_dnrm= d2stg_fdiv && d2stg_denorm_sng_in2
&& (!d2stg_infnan_in) && (!d2stg_zero_in);
assign div_norm_inf= (d2stg_fdiv && (d2stg_infnan_in || d2stg_zero_in))
|| (d1stg_fdiv && ((d1stg_inf_in1 && (!d1stg_infnan_in2))
|| (d1stg_zero_in2 && (!d1stg_infnan_in1)
&& (!d1stg_zero_in1))));
assign div_norm_qnan= d1stg_fdiv && (d1stg_2inf_in || d1stg_2zero_in);
assign div_norm_zero= d1stg_fdiv
&& ((d1stg_inf_in2 && (!d1stg_infnan_in1))
|| (d1stg_zero_in1 && (!d1stg_infnan_in2)
&& (!d1stg_zero_in2)));
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- divide left shift.
//
///////////////////////////////////////////////////////////////////////////////
assign div_frac_add_in2_load= d4stg_fdiv || d6stg_fdiv;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- divide adder/subtractor 2nd input.
//
///////////////////////////////////////////////////////////////////////////////
assign d6stg_frac_out_shl1= (!div_frac_out_54) && (!div_exp_out[12])
&& (div_exp_out[11:1]!=11'b0);
assign d6stg_frac_out_nosh= (!d6stg_frac_out_shl1);
assign div_frac_add_in1_add= d5stg_fdiv && (!div_exp1[12]) && d8stg_step;
assign div_frac_add_in1_load= d4stg_fdiv
|| (d5stg_fdiv && (!div_exp1[12]) && d8stg_step)
|| d6stg_fdiv;
///////////////////////////////////////////////////////////////////////////////
//
// Divide rounding bits.
//
///////////////////////////////////////////////////////////////////////////////
assign d7stg_lsb_in= (d6stg_fdivd && d6stg_frac_2)
|| ((!d6stg_fdivd) && d6stg_frac_31);
assign d7stg_grd_in= (d6stg_fdivd && d6stg_frac_1)
|| ((!d6stg_fdivd) && d6stg_frac_30);
assign d7stg_stk_in= (d6stg_fdivd && d6stg_frac_0)
|| ((!d6stg_fdivd) && d6stg_frac_29)
|| div_frac_add_in1_neq_0;
dffe #(1) i_d7stg_lsb (
.din (d7stg_lsb_in),
.en (d6stg_fdiv),
.clk (rclk),
.q (d7stg_lsb),
.se (se),
.si (),
.so ()
);
dffe #(1) i_d7stg_grd (
.din (d7stg_grd_in),
.en (d6stg_fdiv),
.clk (rclk),
.q (d7stg_grd),
.se (se),
.si (),
.so ()
);
dffe #(1) i_d7stg_stk (
.din (d7stg_stk_in),
.en (d6stg_fdiv),
.clk (rclk),
.q (d7stg_stk),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- divide adder/subtractor and fraction output register.
//
///////////////////////////////////////////////////////////////////////////////
assign d7stg_rndup= ((div_rnd_mode[1:0]==2'b10) && (!div_sign_out)
&& (d7stg_grd || d7stg_stk))
|| ((div_rnd_mode[1:0]==2'b11) && div_sign_out
&& (d7stg_grd || d7stg_stk))
|| ((div_rnd_mode[1:0]==2'b00)
&& ((d7stg_grd && d7stg_stk)
|| (d7stg_grd && (!d7stg_stk) && d7stg_lsb)));
assign d7stg_rndup_inv= (!d7stg_rndup);
assign d7stg_to_0= (div_rnd_mode[1:0]==2'b01)
|| ((div_rnd_mode[1:0]==2'b10) && div_sign_out)
|| ((div_rnd_mode[1:0]==2'b11) && (!div_sign_out));
assign d7stg_to_0_inv= (!d7stg_to_0);
assign div_frac_out_add_in1= d7stg_fdiv && (!d7stg_rndup) && (!d7stg_in_of);
assign div_frac_out_add= d7stg_fdiv && d7stg_rndup && (!d7stg_in_of);
assign div_frac_out_shl1_dbl= d5stg_fdivd && (!div_exp1[12]) && d8stg_step;
assign div_frac_out_shl1_sng= d5stg_fdivs && (!div_exp1[12]) && d8stg_step;
assign div_frac_out_of= d7stg_fdiv && d7stg_in_of;
assign div_frac_out_load= d4stg_fdiv
|| d7stg_fdiv
|| div_frac_out_shl1_dbl
|| div_frac_out_shl1_sng;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- divide exponent adder in the front end of the divide pipe.
//
///////////////////////////////////////////////////////////////////////////////
assign div_expadd1_in1_dbl_in= ((d1stg_stepa && inq_op[1])
|| ((!d1stg_stepa) && d1stg_dblopa[4]))
&& (!((d1stg_fdiv || d2stg_fdiv || d3stg_fdiv) && (!reset)));
dff #(1) i_div_expadd1_in1_dbl (
.din (div_expadd1_in1_dbl_in),
.clk (rclk),
.q (div_expadd1_in1_dbl),
.se (se),
.si (),
.so ()
);
assign div_expadd1_in1_sng_in= ((d1stg_stepa && inq_op[0])
|| ((!d1stg_stepa) && d1stg_sngopa[4]))
&& (!((d1stg_fdiv || d2stg_fdiv || d3stg_fdiv) && (!reset)));
dff #(1) i_div_expadd1_in1_sng (
.din (div_expadd1_in1_sng_in),
.clk (rclk),
.q (div_expadd1_in1_sng),
.se (se),
.si (),
.so ()
);
assign div_expadd1_in2_exp_in2_dbl= d2stg_fdivd;
assign div_expadd1_in2_exp_in2_sng= d2stg_fdivs;
assign div_exp1_expadd1= d1stg_fdiv
|| (d2stg_fdiv && (!d2stg_infnan_in) && (!d2stg_zero_in))
|| d3stg_fdiv
|| d4stg_fdiv;
assign div_exp1_0835= d2stg_fdivd && d2stg_max_exp;
assign div_exp1_0118= d2stg_fdivs && d2stg_max_exp;
assign div_exp1_zero= d2stg_fdiv && d2stg_zero_exp;
assign d2stg_max_exp= d2stg_nan_in || d2stg_inf_in1 || d2stg_zero_in2;
assign d2stg_zero_exp= (d2stg_inf_in2 && (!d2stg_infnan_in1))
|| (d2stg_zero_in1 && (!d2stg_infnan_in2) && (!d2stg_zero_in2));
assign div_exp1_load= d1stg_fdiv || d2stg_fdiv || d3stg_fdiv || d4stg_fdiv;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- divide exponent adder in the back end of the divide pipe.
//
///////////////////////////////////////////////////////////////////////////////
assign div_expadd2_in1_exp_out_in= d6stg_opdec_in[2] || d6stg_fdiv;
dffr #(1) i_div_expadd2_in1_exp_out (
.din (div_expadd2_in1_exp_out_in),
.rst (reset),
.clk (rclk),
.q (div_expadd2_in1_exp_out),
.se (se),
.si (),
.so ()
);
assign div_expadd2_no_decr_inv_in= (!(div_frac_out_53
|| (div_exp1[11:0]==(({12{(!d5stg_fdivs)}} & 12'h035)
| ({12{d5stg_fdivs}} & 12'h018)))
|| div_expadd2_12));
assign div_expadd2_no_decr_load= d5stg_fdiv && d8stg_step;
dffe #(1) i_div_expadd2_no_decr_inv (
.din (div_expadd2_no_decr_inv_in),
.en (div_expadd2_no_decr_load),
.clk (rclk),
.q (div_expadd2_no_decr_inv),
.se (se),
.si (),
.so ()
);
assign div_expadd2_cin= d5stg_fdiv || d7stg_fdiv;
assign div_exp_out_zero= d7stg_fdiv && div_exp_out[12];
assign div_exp_out_expadd22_inv= (!(d6stg_fdiv
|| (d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step)));
assign div_exp_out_expadd2= ((d7stg_fdiv && d7stg_rndup && (!d7stg_in_of))
|| (d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step)
|| d6stg_fdiv)
&& (!div_exp_out_zero);
assign div_exp_out_of= d7stg_fdiv && d7stg_in_of;
assign div_exp_out_exp_out= d7stg_fdiv
&& (!d7stg_in_of)
&& (!div_exp_out_zero);
assign div_exp_out_load= (d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step)
|| d6stg_fdiv
|| d7stg_fdiv;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3B_1_V
`define SKY130_FD_SC_HD__OR3B_1_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3b_1 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3b_1 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3B_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EBUFN_TB_V
`define SKY130_FD_SC_HS__EBUFN_TB_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__ebufn.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 A = 1'b1;
#120 TE_B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 A = 1'b0;
#200 TE_B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 TE_B = 1'b1;
#320 A = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 TE_B = 1'bx;
#400 A = 1'bx;
end
sky130_fd_sc_hs__ebufn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EBUFN_TB_V
|
`timescale 1ns / 1ps
`include "hal/WcaPortDefs.h" //grab register addresses.
// Name: WcaPortController.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaPortController(
input wire reset,
input wire enable,
output wire [(NBITS_ADDR+2):0] portCtrl, // Port State Control bits {addr[NBITS_ADDR:0], read, write, clk }
input wire [1:0] portCmd, // Port Command ID
//Port Interface
output wire [(NBITS_ADDR+1):0] pifCtrl, // {addr[NBITS_ADDR:0], iocmd[1:0] }
input wire [6:0] pifStatus // I/O Status {fifo_full[0], fifo_empty[0], ioBusy, ioState[2:0], clk}
);
parameter COUNT_PORTS = 1;
parameter NBITS_ADDR = 2;
parameter ADDR_MODE = 0;
parameter ADDR_OVERRIDE = 0;
`define PORT_ADDR_MODE_SEQUENTIAL 0
`define PORT_ADDR_MODE_FIXED 1
//State machine states.
`define S_IDLE 3'h0 //Idling state Fixed addressing mode only.
`define S_ADDR 3'h0 //Addressing state. Sequential addressing mode only.
`define S_ADDR_WAIT1 3'h1 //Addressing wait state #1. Sequential addressing mode only.
`define S_ADDR_WAIT2 3'h2 //Addressing wait state #2. Sequential addressing mode only.
`define S_ADDR_WAIT3 3'h3 //Addressing wait state #3. Sequential addressing mode only.
`define S_CMD 3'h4 //Command Initation
`define S_CMD_WAIT1 3'h5 //Wait for IF to settle #1
`define S_CMD_WAIT2 3'h6 //Wait for IF to settle #2
`define S_WAIT_COMPLETE 3'h7 //Wait for Command Completion.
`define ADDR_INCREMENT 2'h1; //Increment address by one.
reg [NBITS_ADDR-1:0] addr;
reg [2:0] cmdState;
reg [1:0] cmd;
wire read;
wire write;
//Map Inputs to Outputs.
assign read = pifStatus[3:1] == `PIFSTAT_READ;
assign write = pifStatus[3:1] == `PIFSTAT_WRITE;
assign pifCtrl = { addr, cmd};
assign portCtrl[NBITS_ADDR+2: 1] = {addr, read, write};
WcaPassthrough pthruClk(.a(pifStatus[0]), .b(portCtrl[0]));
//Control processing of port data based on count.
generate if( ADDR_MODE == `PORT_ADDR_MODE_SEQUENTIAL)
begin
always @(posedge pifStatus[0])
begin :PIFCMD_STATE_MACHINE
if( reset)
begin
addr <= COUNT_PORTS-1;
cmdState <= `S_ADDR;
cmd <= `PIFCMD_IDLE;
end
else
//State machine performs addressing, command, and wait processing.
case (cmdState)
`S_ADDR:
begin
cmd <= `PIFCMD_IDLE;
if( enable)
begin
cmdState <= `S_ADDR_WAIT1;
if( addr == COUNT_PORTS-1) addr <= 0;
else addr <= addr + `ADDR_INCREMENT;
end
end
`S_ADDR_WAIT1: //Wait one for address to settle.
begin
cmdState <= `S_ADDR_WAIT2;
end
`S_ADDR_WAIT2: //Wait another for address to settle.
begin
cmdState <= `S_ADDR_WAIT3;
end
`S_ADDR_WAIT3: //Wait another for address to settle.
begin
cmdState <= `S_CMD;
end
`S_CMD:
begin
cmd <= portCmd;
if( portCmd != `PIFCMD_IDLE)
begin
cmdState <= `S_CMD_WAIT1;
end
else
begin
cmdState <= `S_ADDR;
end
end
`S_CMD_WAIT1: //Wait one clock for the IF to catch up.
begin
cmdState <= `S_CMD_WAIT2;
end
`S_CMD_WAIT2: //Wait another clock for the IF to catch up.
begin
cmdState <= `S_WAIT_COMPLETE;
end
`S_WAIT_COMPLETE:
begin
cmd <= `PIFCMD_IDLE;
if( ~pifStatus[4] ) //if no longer busy, return to idle.
cmdState <= `S_ADDR;
end
endcase
end
end
//*******************************************************************************
// FIXED ADDRESSING MODE.
//*******************************************************************************
else if( ADDR_MODE == `PORT_ADDR_MODE_FIXED)
begin
always @(posedge pifStatus[0])
begin :PIFCMD_STATE_MACHINE
if( reset)
begin
addr <= ADDR_OVERRIDE;
cmdState <= `S_IDLE;
cmd <= `PIFCMD_IDLE;
end
else
//State machine performs addressing, command, and wait processing.
case (cmdState)
`S_IDLE:
begin
cmd <= `PIFCMD_IDLE;
if( enable)
cmdState <= `S_CMD;
end
`S_CMD:
begin
cmd <= portCmd;
if( portCmd != `PIFCMD_IDLE)
begin
cmdState <= `S_CMD_WAIT1;
end
else
begin
cmdState <= `S_IDLE;
end
end
`S_CMD_WAIT1: //Wait one clock for the IF to catch up.
begin
cmdState <= `S_CMD_WAIT2;
end
`S_CMD_WAIT2: //Wait another clock for the IF to catch up.
begin
cmdState <= `S_WAIT_COMPLETE;
end
`S_WAIT_COMPLETE:
begin
cmd <= `PIFCMD_IDLE;
if( ~pifStatus[4] ) //if no longer busy, return to idle.
cmdState <= `S_ADDR;
end
endcase
end
end
endgenerate
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
module FifoBuffer(
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full);
input [31 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [31 : 0] dout;
output empty;
output full;
wire full_wire, wr_ack_wire;
async_fifo buffer_fifo (.din(din), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), .wr_en(wr_en), .dout(dout), .full(full_wire), .wr_ack(wr_ack_wire), .empty(empty) );
defparam buffer_fifo.FIFO_WIDTH = 32;
defparam buffer_fifo.FIFO_DEPTH = 10;
defparam buffer_fifo.DEVICE = "7SERIES" ;
defparam buffer_fifo.FIFO_RAM_TYPE = "BLOCKRAM";
// defparam buffer_fifo.OPTIMIZE = "POWER";
assign full = full_wire;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface, note that overrange is independent of data path,
// software will not be able to relate overrange to a specific sample!
// Alternative is to concatenate sample value and or status for data.
`timescale 1ns/100ps
module axi_ad9652_if (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// interface outputs
adc_clk,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status,
// processor control signals
adc_ddr_edgesel,
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked);
// This parameter controls the buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [15:0] adc_data_in_p;
input [15:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
output [15:0] adc_data_a;
output [15:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// processor control signals
input adc_ddr_edgesel;
// delay control signals
input up_clk;
input [16:0] up_dld;
input [84:0] up_dwdata;
output [84:0] up_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg adc_status = 'd0;
reg [15:0] adc_data_p = 'd0;
reg [15:0] adc_data_n = 'd0;
reg [15:0] adc_data_p_d = 'd0;
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg adc_or_p_d = 'd0;
reg [15:0] adc_data_a = 'd0;
reg [15:0] adc_data_b = 'd0;
reg adc_or_a = 'd0;
reg adc_or_b = 'd0;
// internal signals
wire [15:0] adc_data_p_s;
wire [15:0] adc_data_n_s;
wire adc_or_p_s;
wire adc_or_n_s;
genvar l_inst;
// two data pin modes are supported-
// mux - across clock edges (rising or falling edges),
// mux - within clock edges (lower 7 bits and upper 7 bits)
always @(posedge adc_clk) begin
adc_status <= 1'b1;
adc_data_p <= adc_data_p_s;
adc_data_n <= adc_data_n_s;
adc_data_p_d <= adc_data_p;
adc_or_p <= adc_or_p_s;
adc_or_n <= adc_or_n_s;
adc_or_p_d <= adc_or_p;
end
always @(posedge adc_clk) begin
if (adc_ddr_edgesel == 1'b1) begin
adc_data_a <= adc_data_p_d;
adc_data_b <= adc_data_n;
adc_or_a <= adc_or_p_d;
adc_or_b <= adc_or_n;
end else begin
adc_data_a <= adc_data_n;
adc_data_b <= adc_data_p;
adc_or_a <= adc_or_n;
adc_or_b <= adc_or_p;
end
end
// data interface
generate
for (l_inst = 0; l_inst <= 15; l_inst = l_inst + 1) begin : g_adc_if
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
.rx_data_in_n (adc_data_in_n[l_inst]),
.rx_data_p (adc_data_p_s[l_inst]),
.rx_data_n (adc_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_dld[l_inst]),
.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
endgenerate
// over-range interface
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
.rx_data_in_n (adc_or_in_n),
.rx_data_p (adc_or_p_s),
.rx_data_n (adc_or_n_s),
.up_clk (up_clk),
.up_dld (up_dld[16]),
.up_dwdata (up_dwdata[84:80]),
.up_drdata (up_drdata[84:80]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked));
// clock
ad_lvds_clk #(
.BUFTYPE (PCORE_BUFTYPE))
i_adc_clk (
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),
.clk (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*------------------------------------------------------------------------
Purpose
- Data serializing;
- bit staffing;
- nrzi encoding;
- remote wakeup signaling.
------------------------------------------------------------------------*/
module usb_encoder (
input clk,
input rst0_async,
input rst0_sync,
//USB
output reg dtx_plus,
output reg dtx_minus,
output reg dtx_oe,
//DECODER
input usb_interpack,
//ENCFIFO
input encfifo_wr,
input encfifo_wdata,
output encfifo_full,
input remote_wakeup,
input speed
);
wire usb_j;
wire usb_k;
wire encfifo_empty;
reg encfifo_rd;
wire encfifo_rdata;
reg[17:0] counter;
reg[2:0] stuffbit;
reg[3:0] enc_state;
localparam ENC_IDLE=4'd0,
ENC_TIME1=4'd1,
ENC_DRIVE=4'd2,
ENC_STUFF=4'd3,
ENC_SE0=4'd4,
ENC_TIME2=4'd5,
ENC_DRIVEJ=4'd6,
ENC_TIME3=4'd7,
ENC_DRIVEK=4'd8;
usb_fifo_sync #(.ADDR_WIDTH(1'd1),.WDATA_WIDTH(1'd0),.RDATA_WIDTH(1'd0))
i_encfifo
(
.clk(clk),
.rst0_async(rst0_async),
.rst0_sync(rst0_sync),
.wr_en(encfifo_wr),
.wr_data(encfifo_wdata),
.rd_en(encfifo_rd),
.rd_data(encfifo_rdata),
.fifo_full(encfifo_full),
.fifo_empty(encfifo_empty)
);
assign usb_j= speed ? 1'b1 : 1'b0;
assign usb_k= speed ? 1'b0 : 1'b1;
always @(posedge clk, negedge rst0_async)
begin
if(!rst0_async)
begin
dtx_plus<=1'b1;
dtx_minus<=1'b0;
dtx_oe<=1'b0;
encfifo_rd<=1'b0;
counter<=18'd0;
stuffbit<=3'd0;
enc_state<=ENC_IDLE;
end
else if(!rst0_sync)
begin
dtx_plus<=1'b1;
dtx_minus<=1'b0;
dtx_oe<=1'b0;
encfifo_rd<=1'b0;
counter<=18'd0;
stuffbit<=3'd0;
enc_state<=ENC_IDLE;
end
else
begin
case(enc_state)
ENC_IDLE:
begin
stuffbit<=3'd0;
counter<=18'd0;
encfifo_rd<=1'b0;
dtx_plus<= usb_j;
dtx_minus<= ~usb_j;
dtx_oe<= (!encfifo_empty & usb_interpack) |
remote_wakeup ? 1'b1 : 1'b0;
enc_state<= remote_wakeup ? ENC_DRIVEK :
!encfifo_empty & usb_interpack ? ENC_TIME1 :
enc_state;
end
ENC_TIME1:
begin
counter<= counter+1'b1;
encfifo_rd<= counter==18'd2 & stuffbit!=3'd6 &
!encfifo_empty ? 1'b1 :
1'b0;
enc_state<= counter==18'd2 & stuffbit==3'd6 ? ENC_STUFF :
counter==18'd2 & encfifo_empty ? ENC_SE0 :
counter==18'd2 ? ENC_DRIVE :
enc_state;
end
ENC_DRIVE:
begin
counter<=18'd0;
encfifo_rd<=1'b0;
stuffbit<= encfifo_rdata ? stuffbit+1'b1 : 3'd0;
dtx_plus<= encfifo_rdata ? dtx_plus : ~dtx_plus;
dtx_minus<= encfifo_rdata ? ~dtx_plus : dtx_plus;
enc_state<= ENC_TIME1;
end
ENC_STUFF:
begin
counter<=18'd0;
stuffbit<=3'd0;
dtx_plus<= ~dtx_plus;
dtx_minus<= dtx_plus;
enc_state<= ENC_TIME1;
end
ENC_SE0:
begin
counter<=18'd0;
dtx_plus<=1'b0;
dtx_minus<=1'b0;
enc_state<= ENC_TIME2;
end
ENC_TIME2:
begin
counter<= counter+1'b1;
enc_state<= counter==18'd6 ? ENC_DRIVEJ :
enc_state;
end
ENC_DRIVEJ:
begin
counter<=18'd0;
dtx_plus<= usb_j;
dtx_minus<= ~usb_j;
enc_state<= ENC_TIME3;
end
ENC_TIME3:
begin
counter<= counter+1'b1;
enc_state<= counter==18'd2 ? ENC_IDLE :
enc_state;
end
ENC_DRIVEK:
begin
counter<= counter+1'b1;
dtx_plus<= usb_k;
dtx_minus<= ~usb_k;
//REMOTE WAKEUP SIGNALING:
// ~145000 CYCLES ~2,9ms (FULL SPEED)
// ~18000 CYCLES ~3ms (LOW SPEED)
enc_state<= (speed & counter==18'd145000) |
(!speed & counter==18'd18000) ? ENC_IDLE : enc_state;
end
default:
begin
dtx_plus<=1'b1;
dtx_minus<=1'b0;
dtx_oe<=1'b0;
encfifo_rd<=1'b0;
counter<=18'd0;
stuffbit<=3'd0;
enc_state<=ENC_IDLE;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSRECEIVER_M_V
`define SKY130_FD_SC_LP__BUSRECEIVER_M_V
/**
* busreceiver: Bus signal receiver.
*
* Verilog wrapper for busreceiver with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busreceiver.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busreceiver_m (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__busreceiver base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busreceiver_m (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__busreceiver base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSRECEIVER_M_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD2_TB_V
`define SKY130_FD_SC_HS__DLYGATE4SD2_TB_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlygate4sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__dlygate4sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD2_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXTP_1_V
`define SKY130_FD_SC_LS__SDFXTP_1_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfxtp_1 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXTP_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22A_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O22A_BEHAVIORAL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o22a (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22A_BEHAVIORAL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// CLK_DIV2.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao ([email protected]) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:20 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
//////////////////////////////////////////////////////////////////////
// This file can only used for simulation .
// You need to replace it with your own element according to technology
//////////////////////////////////////////////////////////////////////
module CLK_DIV2 (
input Reset,
input IN,
output reg OUT
);
always @ (posedge IN or posedge Reset)
if (Reset)
OUT <=0;
else
OUT <=!OUT;
endmodule
|
// file: timer_tb.v
//
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED)
module timer_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [2:1] COUNT;
reg COUNTER_RESET = 0;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
timer_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EBUFN_LP2_V
`define SKY130_FD_SC_LP__EBUFN_LP2_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size for low power (alternative).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ebufn_lp2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ebufn_lp2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EBUFN_LP2_V
|
`define SMV
`include "assertionFabricVerified.v"
/*
* File: assertionFabricVerified_tb.v
* Verification driver for assertionFabricVerified.v
* Includes assertions for verification
*
*/
module main();
// Inputs to DUT
reg clk;
reg rst;
reg enable;
reg [31:0] bakedInAssertions;
reg [`ROUTING_INPUT_BITS-1:0] routingInput;
reg [4:0] routingBlock_0_inputSelect;
reg [4:0] routingBlock_1_inputSelect;
reg [4:0] routingBlock_2_inputSelect;
reg [4:0] routingBlock_3_inputSelect;
reg [4:0] routingBlock_4_inputSelect;
reg [4:0] routingBlock_5_inputSelect;
reg [4:0] routingBlock_6_inputSelect;
reg [4:0] routingBlock_7_inputSelect;
reg [4:0] routingBlock_8_inputSelect;
reg [4:0] routingBlock_9_inputSelect;
reg [4:0] routingBlock_10_inputSelect;
reg [4:0] routingBlock_11_inputSelect;
reg [4:0] routingBlock_12_inputSelect;
reg [4:0] routingBlock_13_inputSelect;
reg [4:0] routingBlock_14_inputSelect;
reg [4:0] routingBlock_15_inputSelect;
reg [4:0] routingBlock_16_inputSelect;
reg [4:0] routingBlock_17_inputSelect;
reg [4:0] routingBlock_18_inputSelect;
reg [4:0] routingBlock_19_inputSelect;
reg [31:0] logicBlock_0_maskA;
reg [31:0] logicBlock_0_maskB;
reg [31:0] logicBlock_0_constant;
reg logicBlock_0_opBMux;
reg [2:0] logicBlock_0_resultMux;
reg [31:0] logicBlock_1_maskA;
reg [31:0] logicBlock_1_maskB;
reg [31:0] logicBlock_1_constant;
reg logicBlock_1_opBMux;
reg [2:0] logicBlock_1_resultMux;
reg [31:0] logicBlock_2_maskA;
reg [31:0] logicBlock_2_maskB;
reg [31:0] logicBlock_2_constant;
reg logicBlock_2_opBMux;
reg [2:0] logicBlock_2_resultMux;
reg [31:0] logicBlock_3_maskA;
reg [31:0] logicBlock_3_maskB;
reg [31:0] logicBlock_3_constant;
reg logicBlock_3_opBMux;
reg [2:0] logicBlock_3_resultMux;
reg [31:0] logicBlock_4_maskA;
reg [31:0] logicBlock_4_maskB;
reg [31:0] logicBlock_4_constant;
reg logicBlock_4_opBMux;
reg [2:0] logicBlock_4_resultMux;
reg [31:0] logicBlock_5_maskA;
reg [31:0] logicBlock_5_maskB;
reg [31:0] logicBlock_5_constant;
reg logicBlock_5_opBMux;
reg [2:0] logicBlock_5_resultMux;
reg [31:0] logicBlock_6_maskA;
reg [31:0] logicBlock_6_maskB;
reg [31:0] logicBlock_6_constant;
reg logicBlock_6_opBMux;
reg [2:0] logicBlock_6_resultMux;
reg [31:0] logicBlock_7_maskA;
reg [31:0] logicBlock_7_maskB;
reg [31:0] logicBlock_7_constant;
reg logicBlock_7_opBMux;
reg [2:0] logicBlock_7_resultMux;
reg [31:0] logicBlock_8_maskA;
reg [31:0] logicBlock_8_maskB;
reg [31:0] logicBlock_8_constant;
reg logicBlock_8_opBMux;
reg [2:0] logicBlock_8_resultMux;
reg [31:0] logicBlock_9_maskA;
reg [31:0] logicBlock_9_maskB;
reg [31:0] logicBlock_9_constant;
reg logicBlock_9_opBMux;
reg [2:0] logicBlock_9_resultMux;
reg [2:0] assertionBlock_0_num_cks;
reg [1:0] assertionBlock_0_select;
reg assertionBlock_0_res_sel;
reg [2:0] assertionBlock_1_num_cks;
reg [1:0] assertionBlock_1_select;
reg assertionBlock_1_res_sel;
reg [2:0] assertionBlock_2_num_cks;
reg [1:0] assertionBlock_2_select;
reg assertionBlock_2_res_sel;
reg [2:0] assertionBlock_3_num_cks;
reg [1:0] assertionBlock_3_select;
reg assertionBlock_3_res_sel;
reg [2:0] assertionBlock_4_num_cks;
reg [1:0] assertionBlock_4_select;
reg assertionBlock_4_res_sel;
// Outputs of DUT
wire assertionViolated;
wire [31:0] assertionsViolated;
assertionFabric af_t(.clk(clk),
.rst(rst),
.enable(rst),
.bakedInAssertions(bakedInAssertions),
.routingInput(routingInput),
.routingBlock_0_inputSelect(routingBlock_0_inputSelect),
.routingBlock_1_inputSelect(routingBlock_1_inputSelect),
.routingBlock_2_inputSelect(routingBlock_2_inputSelect),
.routingBlock_3_inputSelect(routingBlock_3_inputSelect),
.routingBlock_4_inputSelect(routingBlock_4_inputSelect),
.routingBlock_5_inputSelect(routingBlock_5_inputSelect),
.routingBlock_6_inputSelect(routingBlock_6_inputSelect),
.routingBlock_7_inputSelect(routingBlock_7_inputSelect),
.routingBlock_8_inputSelect(routingBlock_8_inputSelect),
.routingBlock_9_inputSelect(routingBlock_9_inputSelect),
.routingBlock_10_inputSelect(routingBlock_10_inputSelect),
.routingBlock_11_inputSelect(routingBlock_11_inputSelect),
.routingBlock_12_inputSelect(routingBlock_12_inputSelect),
.routingBlock_13_inputSelect(routingBlock_13_inputSelect),
.routingBlock_14_inputSelect(routingBlock_14_inputSelect),
.routingBlock_15_inputSelect(routingBlock_15_inputSelect),
.routingBlock_16_inputSelect(routingBlock_16_inputSelect),
.routingBlock_17_inputSelect(routingBlock_17_inputSelect),
.routingBlock_18_inputSelect(routingBlock_18_inputSelect),
.routingBlock_19_inputSelect(routingBlock_19_inputSelect),
.logicBlock_0_maskA(logicBlock_0_maskA),
.logicBlock_0_maskB(logicBlock_0_maskB),
.logicBlock_0_constant(logicBlock_0_constant),
.logicBlock_0_opBMux(logicBlock_0_opBMux),
.logicBlock_0_resultMux(logicBlock_0_resultMux),
.logicBlock_1_maskA(logicBlock_1_maskA),
.logicBlock_1_maskB(logicBlock_1_maskB),
.logicBlock_1_constant(logicBlock_1_constant),
.logicBlock_1_opBMux(logicBlock_1_opBMux),
.logicBlock_1_resultMux(logicBlock_1_resultMux),
.logicBlock_2_maskA(logicBlock_2_maskA),
.logicBlock_2_maskB(logicBlock_2_maskB),
.logicBlock_2_constant(logicBlock_2_constant),
.logicBlock_2_opBMux(logicBlock_2_opBMux),
.logicBlock_2_resultMux(logicBlock_2_resultMux),
.logicBlock_3_maskA(logicBlock_3_maskA),
.logicBlock_3_maskB(logicBlock_3_maskB),
.logicBlock_3_constant(logicBlock_3_constant),
.logicBlock_3_opBMux(logicBlock_3_opBMux),
.logicBlock_3_resultMux(logicBlock_3_resultMux),
.logicBlock_4_maskA(logicBlock_4_maskA),
.logicBlock_4_maskB(logicBlock_4_maskB),
.logicBlock_4_constant(logicBlock_4_constant),
.logicBlock_4_opBMux(logicBlock_4_opBMux),
.logicBlock_4_resultMux(logicBlock_4_resultMux),
.logicBlock_5_maskA(logicBlock_5_maskA),
.logicBlock_5_maskB(logicBlock_5_maskB),
.logicBlock_5_constant(logicBlock_5_constant),
.logicBlock_5_opBMux(logicBlock_5_opBMux),
.logicBlock_5_resultMux(logicBlock_5_resultMux),
.logicBlock_6_maskA(logicBlock_6_maskA),
.logicBlock_6_maskB(logicBlock_6_maskB),
.logicBlock_6_constant(logicBlock_6_constant),
.logicBlock_6_opBMux(logicBlock_6_opBMux),
.logicBlock_6_resultMux(logicBlock_6_resultMux),
.logicBlock_7_maskA(logicBlock_7_maskA),
.logicBlock_7_maskB(logicBlock_7_maskB),
.logicBlock_7_constant(logicBlock_7_constant),
.logicBlock_7_opBMux(logicBlock_7_opBMux),
.logicBlock_7_resultMux(logicBlock_7_resultMux),
.logicBlock_8_maskA(logicBlock_8_maskA),
.logicBlock_8_maskB(logicBlock_8_maskB),
.logicBlock_8_constant(logicBlock_8_constant),
.logicBlock_8_opBMux(logicBlock_8_opBMux),
.logicBlock_8_resultMux(logicBlock_8_resultMux),
.logicBlock_9_maskA(logicBlock_9_maskA),
.logicBlock_9_maskB(logicBlock_9_maskB),
.logicBlock_9_constant(logicBlock_9_constant),
.logicBlock_9_opBMux(logicBlock_9_opBMux),
.logicBlock_9_resultMux(logicBlock_9_resultMux),
.assertionBlock_0_num_cks(assertionBlock_0_num_cks),
.assertionBlock_0_select(assertionBlock_0_select),
.assertionBlock_0_res_sel(assertionBlock_0_res_sel),
.assertionBlock_1_num_cks(assertionBlock_1_num_cks),
.assertionBlock_1_select(assertionBlock_1_select),
.assertionBlock_1_res_sel(assertionBlock_1_res_sel),
.assertionBlock_2_num_cks(assertionBlock_2_num_cks),
.assertionBlock_2_select(assertionBlock_2_select),
.assertionBlock_2_res_sel(assertionBlock_2_res_sel),
.assertionBlock_3_num_cks(assertionBlock_3_num_cks),
.assertionBlock_3_select(assertionBlock_3_select),
.assertionBlock_3_res_sel(assertionBlock_3_res_sel),
.assertionBlock_4_num_cks(assertionBlock_4_num_cks),
.assertionBlock_4_select(assertionBlock_4_select),
.assertionBlock_4_res_sel(assertionBlock_4_res_sel),
.assertionViolated(assertionViolated),
.assertionsViolated(assertionsViolated));
initial begin
clk =0;
rst=1;
enable=0;
bakedInAssertions=0;
routingInput=0;
routingBlock_0_inputSelect=0;
routingBlock_1_inputSelect=0;
routingBlock_2_inputSelect=0;
routingBlock_3_inputSelect=0;
routingBlock_4_inputSelect=0;
routingBlock_5_inputSelect=0;
routingBlock_6_inputSelect=0;
routingBlock_7_inputSelect=0;
routingBlock_8_inputSelect=0;
routingBlock_9_inputSelect=0;
routingBlock_10_inputSelect=0;
routingBlock_11_inputSelect=0;
routingBlock_12_inputSelect=0;
routingBlock_13_inputSelect=0;
routingBlock_14_inputSelect=0;
routingBlock_15_inputSelect=0;
routingBlock_16_inputSelect=0;
routingBlock_17_inputSelect=0;
routingBlock_18_inputSelect=0;
routingBlock_19_inputSelect=0;
logicBlock_0_maskA=0;
logicBlock_0_maskB=0;
logicBlock_0_constant=0;
logicBlock_0_opBMux=0;
logicBlock_0_resultMux=0;
logicBlock_1_maskA=0;
logicBlock_1_maskB=0;
logicBlock_1_constant=0;
logicBlock_1_opBMux=0;
logicBlock_1_resultMux=0;
logicBlock_2_maskA=0;
logicBlock_2_maskB=0;
logicBlock_2_constant=0;
logicBlock_2_opBMux=0;
logicBlock_2_resultMux=0;
logicBlock_3_maskA=0;
logicBlock_3_maskB=0;
logicBlock_3_constant=0;
logicBlock_3_opBMux=0;
logicBlock_3_resultMux=0;
logicBlock_4_maskA=0;
logicBlock_4_maskB=0;
logicBlock_4_constant=0;
logicBlock_4_opBMux=0;
logicBlock_4_resultMux=0;
logicBlock_5_maskA=0;
logicBlock_5_maskB=0;
logicBlock_5_constant=0;
logicBlock_5_opBMux=0;
logicBlock_5_resultMux=0;
logicBlock_6_maskA=0;
logicBlock_6_maskB=0;
logicBlock_6_constant=0;
logicBlock_6_opBMux=0;
logicBlock_6_resultMux=0;
logicBlock_7_maskA=0;
logicBlock_7_maskB=0;
logicBlock_7_constant=0;
logicBlock_7_opBMux=0;
logicBlock_7_resultMux=0;
logicBlock_8_maskA=0;
logicBlock_8_maskB=0;
logicBlock_8_constant=0;
logicBlock_8_opBMux=0;
logicBlock_8_resultMux=0;
logicBlock_9_maskA=0;
logicBlock_9_maskB=0;
logicBlock_9_constant=0;
logicBlock_9_opBMux=0;
logicBlock_9_resultMux=0;
assertionBlock_0_num_cks=0;
assertionBlock_0_select=0;
assertionBlock_0_res_sel=0;
assertionBlock_1_num_cks=0;
assertionBlock_1_select=0;
assertionBlock_1_res_sel=0;
assertionBlock_2_num_cks=0;
assertionBlock_2_select=0;
assertionBlock_2_res_sel=0;
assertionBlock_3_num_cks=0;
assertionBlock_3_select=0;
assertionBlock_3_res_sel=0;
assertionBlock_4_num_cks=0;
assertionBlock_4_select=0;
assertionBlock_4_res_sel=0;
end // initial
always begin
clk = #5 !clk;
end
endmodule // main
/* *************** SMV Assertions *****************
//SMV-Assertions
#If any of the configuration data is invalid, no asserts will fire. Start easy. any internal configInvalid signals -> no assert
no_asserts_for_invalid_assertionBlock_configuration : assert \rst -> X(G(((\af_t .\assertionBlock_0_configInvalid ) || (\af_t .\assertionBlock_1_configInvalid ) || (\af_t .\assertionBlock_2_configInvalid ) || (\af_t .\assertionBlock_3_configInvalid ) || (\af_t .\assertionBlock_4_configInvalid )) -> ~\assertionViolated ));
no_asserts_for_invalid_logicBlock_configuration : assert \rst -> X(G((\af_t .\logicBlock_0_configInvalid || \af_t .\logicBlock_1_configInvalid || \af_t .\logicBlock_2_configInvalid || \af_t .\logicBlock_3_configInvalid || \af_t .\logicBlock_4_configInvalid || \af_t .\logicBlock_5_configInvalid || \af_t .\logicBlock_6_configInvalid || \af_t .\logicBlock_7_configInvalid || \af_t .\logicBlock_8_configInvalid || \af_t .\logicBlock_9_configInvalid ) -> ~\assertionViolated ));
no_asserts_for_invalid_routingBlock_configuration : assert \rst -> X(G((\af_t .\routingBlock_0_configInvalid || \af_t .\routingBlock_1_configInvalid || \af_t .\routingBlock_2_configInvalid || \af_t .\routingBlock_3_configInvalid || \af_t .\routingBlock_4_configInvalid || \af_t .\routingBlock_5_configInvalid || \af_t .\routingBlock_6_configInvalid || \af_t .\routingBlock_7_configInvalid || \af_t .\routingBlock_8_configInvalid || \af_t .\routingBlock_9_configInvalid || \af_t .\routingBlock_10_configInvalid || \af_t .\routingBlock_11_configInvalid || \af_t .\routingBlock_12_configInvalid || \af_t .\routingBlock_13_configInvalid || \af_t .\routingBlock_14_configInvalid || \af_t .\routingBlock_15_configInvalid || \af_t .\routingBlock_16_configInvalid || \af_t .\routingBlock_17_configInvalid || \af_t .\routingBlock_18_configInvalid || \af_t .\routingBlock_19_configInvalid ) -> ~\assertionViolated ));
using \af_t .\routingBlock_0_configInvalid //free ,\af_t .\routingBlock_1_configInvalid //free ,\af_t .\routingBlock_2_configInvalid //free ,\af_t .\routingBlock_3_configInvalid //free ,\af_t .\routingBlock_4_configInvalid //free ,\af_t .\routingBlock_5_configInvalid //free ,\af_t .\routingBlock_6_configInvalid //free ,\af_t .\routingBlock_7_configInvalid //free ,\af_t .\routingBlock_8_configInvalid //free ,\af_t .\routingBlock_9_configInvalid //free ,\af_t .\routingBlock_10_configInvalid //free ,\af_t .\routingBlock_11_configInvalid //free ,\af_t .\routingBlock_12_configInvalid //free ,\af_t .\routingBlock_13_configInvalid //free ,\af_t .\routingBlock_14_configInvalid //free ,\af_t .\routingBlock_15_configInvalid //free ,\af_t .\routingBlock_16_configInvalid //free ,\af_t .\routingBlock_17_configInvalid //free ,\af_t .\routingBlock_18_configInvalid //free ,\af_t .\routingBlock_19_configInvalid //free ,\af_t .\routingBlock_0_result //free ,\af_t .\routingBlock_1_result //free ,\af_t .\routingBlock_2_result //free ,\af_t .\routingBlock_3_result //free ,\af_t .\routingBlock_4_result //free ,\af_t .\routingBlock_5_result //free ,\af_t .\routingBlock_6_result //free ,\af_t .\routingBlock_7_result //free ,\af_t .\routingBlock_8_result //free ,\af_t .\routingBlock_9_result //free ,\af_t .\routingBlock_10_result //free ,\af_t .\routingBlock_11_result //free ,\af_t .\routingBlock_12_result //free ,\af_t .\routingBlock_13_result //free ,\af_t .\routingBlock_14_result //free ,\af_t .\routingBlock_15_result //free ,\af_t .\routingBlock_16_result //free ,\af_t .\routingBlock_17_result //free ,\af_t .\routingBlock_18_result //free ,\af_t .\routingBlock_19_result //free prove \no_asserts_for_invalid_logicBlock_configuration ,\no_asserts_for_invalid_assertionBlock_configuration ,\no_asserts_for_invalid_routingBlock_configuration ;
//SMV-Assertions
*/
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
`define checkhw(gotv,w,expv) do if (gotv[(w)*32+:$bits(expv)] !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv[(w)*32+:32]), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
bit [4*32-1:0] w4 = {32'h7c709753, 32'hbc8f6059, 32'h3b0db464, 32'h721a8fad};
bit [8*32-2:0] w8m = {31'h7146e1bf, 32'ha8549e42, 32'hca6960bd, 32'h191b7f9b, 32'h93d79866, 32'hf4489e2b, 32'h8e9a3236, 32'h1d2a2d1d};
bit [8*32-1:0] w8 = {32'hc211addc, 32'he5d4a057, 32'h5cbf88fe, 32'h42cf42e2, 32'heb584263, 32'ha585f118, 32'h231531c8, 32'hc73f7b06};
bit [8*32-0:0] w8p = {1'b1, 32'h096aa54b, 32'h48aae18e, 32'hf9502cea, 32'h518c8b61, 32'h9e8641a2, 32'h0dc0249c, 32'hd421a87a, 32'hb8ee9199};
bit [9*32-1:0] w9 = {32'hca800ac1,
32'h0de4823a, 32'ha51663ac, 32'h96351446, 32'h6b0bbcd5, 32'h4a64b530, 32'h4967d59a, 32'hfcc17292, 32'h57926621};
bit [16*32-2:0] w16m = {31'h77ad72c7, 32'h73aa9cbb, 32'h7ecf026d, 32'h985a3ed2, 32'hfe961c1d, 32'h7a01df72, 32'h79e13d71, 32'hb69e2e32,
32'h09fcbc45, 32'hcfd738c1, 32'hc197ac7c, 32'hc316d727, 32'h903034e4, 32'h92a047d1, 32'h6a5357af, 32'ha82ce9c8};
bit [16*32-1:0] w16 = {32'he49548a7, 32'ha02336a2, 32'h2bb48f0d, 32'h9974e098, 32'h34ae644f, 32'hca46dc2c, 32'h9f71a468, 32'h64ae043e,
32'h7bc94d66, 32'h57aba588, 32'h5b9bb4fe, 32'hb87ed644, 32'hd34b5b20, 32'h712928de, 32'h4bdbd28e, 32'ha0576784};
bit [16*32-0:0] w16p = {1'b1, 32'hd278a306, 32'h374ce262, 32'hb608c88e, 32'h43d3e446, 32'h42e26866, 32'h44c31148, 32'hd3db659f, 32'hb3b84b2e,
32'h1aa7a184, 32'h73b28538, 32'h6384e801, 32'h98d58e00, 32'h9c1d1429, 32'hb407730e, 32'he974c1fd, 32'he787c302};
bit [17*32-1:0] w17 = {32'hf1e322ac,
32'hbbdbd761, 32'h760fe07d, 32'h3808cb28, 32'haf313051, 32'h37dc63b9, 32'hdddb418b, 32'he65a9d64, 32'hc1b6ab23,
32'h11131ac1, 32'h0050e0bc, 32'h442e3754, 32'h0eb4556e, 32'hd153064b, 32'h41349f97, 32'hb6f4149f, 32'h34bb1fb1};
function [7:0] bytehash (input [32*32-1:0] data);
integer i;
bytehash = 0;
for (i=0; i<32*32; ++i) begin
bytehash = {bytehash[0], bytehash[7:1]} ^ data[i +: 8];
end
return bytehash;
endfunction
// Aggregate outputs into a single result vector
// verilator lint_off WIDTH
wire [63:0] result = (bytehash(w4)
^ bytehash(w8m)
^ bytehash(w8)
^ bytehash(w8p)
^ bytehash(w9)
^ bytehash(w16m)
^ bytehash(w16)
^ bytehash(w16p)
^ bytehash(w17));
// verilator lint_on WIDTH
`define EXPECTED_SUM 64'hb6fdb64085fc17f5
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
// verilator lint_off SELRANGE
`checkhw(w4,3,32'h7c709753);
`checkhw(w4,2,32'hbc8f6059);
`checkhw(w4,1,32'h3b0db464);
`checkhw(w4,0,32'h721a8fad);
`checkhw(w8m,7,31'h7146e1bf);
`checkhw(w8m,6,32'ha8549e42);
`checkhw(w8m,5,32'hca6960bd);
`checkhw(w8m,4,32'h191b7f9b);
`checkhw(w8m,3,32'h93d79866);
`checkhw(w8m,2,32'hf4489e2b);
`checkhw(w8m,1,32'h8e9a3236);
`checkhw(w8m,0,32'h1d2a2d1d);
`checkhw(w8,7,32'hc211addc);
`checkhw(w8,6,32'he5d4a057);
`checkhw(w8,5,32'h5cbf88fe);
`checkhw(w8,4,32'h42cf42e2);
`checkhw(w8,3,32'heb584263);
`checkhw(w8,2,32'ha585f118);
`checkhw(w8,1,32'h231531c8);
`checkhw(w8,0,32'hc73f7b06);
`checkhw(w8p,8,1'b1);
`checkhw(w8p,7,32'h096aa54b);
`checkhw(w8p,6,32'h48aae18e);
`checkhw(w8p,5,32'hf9502cea);
`checkhw(w8p,4,32'h518c8b61);
`checkhw(w8p,3,32'h9e8641a2);
`checkhw(w8p,2,32'h0dc0249c);
`checkhw(w8p,1,32'hd421a87a);
`checkhw(w8p,0,32'hb8ee9199);
`checkhw(w9,8,32'hca800ac1);
`checkhw(w9,7,32'h0de4823a);
`checkhw(w9,6,32'ha51663ac);
`checkhw(w9,5,32'h96351446);
`checkhw(w9,4,32'h6b0bbcd5);
`checkhw(w9,3,32'h4a64b530);
`checkhw(w9,2,32'h4967d59a);
`checkhw(w9,1,32'hfcc17292);
`checkhw(w9,0,32'h57926621);
`checkhw(w16m,15,31'h77ad72c7);
`checkhw(w16m,14,32'h73aa9cbb);
`checkhw(w16m,13,32'h7ecf026d);
`checkhw(w16m,12,32'h985a3ed2);
`checkhw(w16m,11,32'hfe961c1d);
`checkhw(w16m,10,32'h7a01df72);
`checkhw(w16m,9,32'h79e13d71);
`checkhw(w16m,8,32'hb69e2e32);
`checkhw(w16m,7,32'h09fcbc45);
`checkhw(w16m,6,32'hcfd738c1);
`checkhw(w16m,5,32'hc197ac7c);
`checkhw(w16m,4,32'hc316d727);
`checkhw(w16m,3,32'h903034e4);
`checkhw(w16m,2,32'h92a047d1);
`checkhw(w16m,1,32'h6a5357af);
`checkhw(w16m,0,32'ha82ce9c8);
// verilator lint_on SELRANGE
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
w4 = w4 >>> 1;
w8m = w8m >>> 1;
w8 = w8 >>> 1;
w8p = w8p >>> 1;
w9 = w9 >>> 1;
w16m = w16m >>> 1;
w16 = w16 >>> 1;
w16p = w16p >>> 1;
w17 = w17 >>> 1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:44:23 03/16/2014
// Design Name:
// Module Name: LC3_computer_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LC3_computer_top(
input clk,
input reset,
input LD_char,
input [7:0] I_char,
output [15:0] DDR,
output WR_DDR
);
wire [39:0] CONTROL;
wire [15:0] DATABUS;
/*REGFILE-RELATIVE INPUT*/
wire [1:0] SR1MUX;
wire [1:0] DRMUX;
/*ALU-RELATIVE INPUT*/
wire [1:0] ALUK;
wire SR2MUX;
/*ADDRESS-RELATIVE INPUT*/
wire ADDR1MUX;
wire [1:0] ADDR2MUX;
wire [1:0] PCMUX;
wire MARMUX;
/*PSR-RELATIVE INPUT*/
wire Set_Priv;
wire PSRMUX;
/*INT-RELATIVE INPUT*/
wire [7:0] INTV;
wire [1:0] VectorMUX;
wire [1:0] SPMUX;
wire [2:0] Int_Priority;
/*GATES*/
wire GateALU;
wire GatePSR;
wire GateSP;
wire GateVector;
wire GateMARMUX;
wire GatePC;
wire GatePCsubtract1;
/*LOAD SIGNAL*/
wire LD_REG;
wire LD_IR;
wire LD_PC;
wire LD_CC;
wire LD_Priv;
wire LD_Priority;
wire LD_Vector;
wire LD_SavedUSP;
wire LD_SavedSSP;
/*STATE MACHINE OUTPUT*/
wire INT;
wire [2:0] CC;
wire [15:0] IR;
wire Priv;
wire BEN;
assign Set_Priv=1'b0;
assign R_W=CONTROL[1];
assign MIO_EN=CONTROL[2];
assign ALUK=CONTROL[4:3];
assign PSRMUX=CONTROL[5];
assign VectorMUX=CONTROL[7:6];
assign MARMUX=CONTROL[8];
assign SPMUX=CONTROL[10:9];
assign ADDR2MUX=CONTROL[12:11];
assign ADDR1MUX=CONTROL[13];
assign SR1MUX= CONTROL[15:14];
assign DRMUX= CONTROL[17:16];
assign PCMUX= CONTROL[19:18];
assign GateSP= CONTROL[20];
assign GatePSR= CONTROL[21];
assign GatePCsubtract1=CONTROL[22];
assign GateVector=CONTROL[23];
assign GateMARMUX=CONTROL[24];
assign GateALU= CONTROL[25];
assign GateMDR= CONTROL[26];
assign GatePC= CONTROL[27];
assign LD_Vector=CONTROL[28];
assign LD_SavedUSP=CONTROL[29];
assign LD_SavedSSP=CONTROL[30];
assign LD_Priv =CONTROL[31];
assign LD_Priority=CONTROL[32];
assign LD_PC =CONTROL[33];
assign LD_CC =CONTROL[34];
assign LD_REG =CONTROL[35];
assign LD_BEN =CONTROL[36];
assign LD_IR =CONTROL[37];
assign LD_MDR =CONTROL[38];
assign LD_MAR =CONTROL[39];
/*instance of StateMachine*/
wire R;
LC3_FSM instance_fsm(
.clk (clk),
.reset (reset),
.Priv (Priv),
.BEN (BEN),
.IR (IR[15:11]),
.R (R),
.INT (INT),
.CONTROL (CONTROL)
);
/*instance of datapath*/
LC3_datapath inst_datapath0(
/*GENERAL INPUT*/
.clk(clk),
.reset(reset),
.DATABUS(DATABUS),
/*REGFILE-RELATIVE INPUT*/
.SR1MUX(SR1MUX),
.DRMUX(DRMUX),
/*ALU-RELATIVE INPUT*/
.ALUK(ALUK),
/*ADDRESS-RELATIVE INPUT*/
.ADDR1MUX(ADDR1MUX),
.ADDR2MUX(ADDR2MUX),
.PCMUX(PCMUX),
.MARMUX(MARMUX),
/*PSR-RELATIVE INPUT*/
.Set_Priv(Set_Priv),
.PSRMUX(PSRMUX),
/*INT-RELATIVE INPUT*/
.INTV(INTV),
.VectorMUX(VectorMUX),
.SPMUX(SPMUX),
.Int_Priority(Int_Priority),
/*GATES*/
.GateALU(GateALU),
.GatePSR(GatePSR),
.GateSP(GateSP),
.GateVector(GateVector),
.GateMARMUX(GateMARMUX),
.GatePC(GatePC),
.GatePCsubtract1(GatePCsubtract1),
/*LOAD SIGNAL*/
.LD_BEN(LD_BEN),
.LD_REG(LD_REG),
.LD_IR(LD_IR),
.LD_PC(LD_PC),
.LD_CC(LD_CC),
.LD_Priv(LD_Priv),
.LD_Priority(LD_Priority),
.LD_Vector(LD_Vector),
.LD_SavedUSP(LD_SavedUSP),
.LD_SavedSSP(LD_SavedSSP),
/*DATABUS OUTPUT*/
.ALUbus_out (DATABUS),
.PSRbus_out (DATABUS),
.SPbus_out (DATABUS),
.Vector_bus_out(DATABUS),
.MARbus_out (DATABUS),
.PCbus_out(DATABUS),
.PCsubtract1_bus_out(DATABUS),
/*STATE MACHINE OUTPUT*/
.INT(INT),
.IR_reg(IR),
.Priv_reg(Priv),
.BEN_reg(BEN)
);
/*instance of MIO*/
LC3_MIO inst_memory_io(
.clk (clk),
.reset (reset),
.DATABUS (DATABUS),
.MIO_EN (MIO_EN),
.R_W (R_W),
.LD_MAR (LD_MAR),
.LD_MDR (LD_MDR),
.GateMDR (GateMDR),
.MDRbus_out (DATABUS),
.KB_INT (KB_INT),
.R (R),
.LD_char (LD_char),
.I_char (I_char),
.DDR (DDR),
.WR_DDR (WR_DDR)
);
/*instance of interrupt controler*/
LC3_int_controller inst_int_controller(
.KB_INT (KB_INT),
.INT_Priority (Int_Priority),
.INTV (INTV)
);
endmodule
|
`include "probador_Rx.v"
`include "Rx_Module.v"
module test_bench_Rxt;
//cables de comunicacion entre modulos
wire clock;
wire reset;
wire start;
wire [7:0] RX_BUF_FRAME_TYPE; //B2..0 110b: Received Cable Reset
wire [15:0] ALERT; //B3 Hard Reset
wire [7:0] RECEIVE_DETECT;
wire [7:0] RECEIVE_BYTE_COUNT;
wire tx_State_Machine_ACTIVE;
wire unexpected_GoodCRC;
wire cC_Busy, cC_IDLE;
wire [7:0] data_In;
wire [15:0] ALERTo;
wire [7:0] RECEIVE_BYTE_COUNTo;
wire GoodCRC_to_PHYo;
wire [7:0] DIR_WRITEo;
wire [7:0] DATA_to_Buffero;
//instancia del probador
probador_Rx p_Rx(.CLK(clock),
.reset(reset),
.Start(start),
.iRX_BUF_FRAME_TYPE(RX_BUF_FRAME_TYPE),
.iALERT(ALERT),
.iRECEIVE_DETECT(RECEIVE_DETECT),
.iRECEIVE_BYTE_COUNT(RECEIVE_BYTE_COUNT),
.Tx_State_Machine_ACTIVE(tx_State_Machine_ACTIVE),
.Unexpected_GoodCRC(unexpected_GoodCRC),
.CC_Busy(cC_Busy),
.CC_IDLE(cC_IDLE),
.Data_In(data_In),
.oALERT(ALERTo),
.oRECEIVE_BYTE_COUNT(RECEIVE_BYTE_COUNTo),
.oGoodCRC_to_PHY(GoodCRC_to_PHYo),
.oDIR_WRITE(DIR_WRITEo),
.oDATA_to_Buffer(DATA_to_Buffero)
);
//instancia del registro
Rx_Module maquinita_Rx (.CLK(clock),
.reset(reset),
.Start(start),
.iRX_BUF_FRAME_TYPE(RX_BUF_FRAME_TYPE),
.iALERT(ALERT),
.iRECEIVE_DETECT(RECEIVE_DETECT),
.iRECEIVE_BYTE_COUNT(RECEIVE_BYTE_COUNT),
.Tx_State_Machine_ACTIVE(tx_State_Machine_ACTIVE),
.Unexpected_GoodCRC(unexpected_GoodCRC),
.CC_Busy(cC_Busy),
.CC_IDLE(cC_IDLE),
.Data_In(data_In),
.oALERT(ALERTo),
.oRECEIVE_BYTE_COUNT(RECEIVE_BYTE_COUNTo),
.oGoodCRC_to_PHY(GoodCRC_to_PHYo),
.oDIR_WRITE(DIR_WRITEo),
.oDATA_to_Buffer(DATA_to_Buffero)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB16TO1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__MUXB16TO1_FUNCTIONAL_PP_V
/**
* muxb16to1: Buffered 16-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__muxb16to1 (
Z ,
D ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input [15:0] D ;
input [15:0] S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_d0 ;
wire pwrgood_pp1_out_s0 ;
wire pwrgood_pp2_out_d1 ;
wire pwrgood_pp3_out_s1 ;
wire pwrgood_pp4_out_d2 ;
wire pwrgood_pp5_out_s2 ;
wire pwrgood_pp6_out_d3 ;
wire pwrgood_pp7_out_s3 ;
wire pwrgood_pp8_out_d4 ;
wire pwrgood_pp9_out_s4 ;
wire pwrgood_pp10_out_d5 ;
wire pwrgood_pp11_out_s5 ;
wire pwrgood_pp12_out_d6 ;
wire pwrgood_pp13_out_s6 ;
wire pwrgood_pp14_out_d7 ;
wire pwrgood_pp15_out_s7 ;
wire pwrgood_pp16_out_d8 ;
wire pwrgood_pp17_out_s8 ;
wire pwrgood_pp18_out_d9 ;
wire pwrgood_pp19_out_s9 ;
wire pwrgood_pp20_out_d10;
wire pwrgood_pp21_out_s10;
wire pwrgood_pp22_out_d11;
wire pwrgood_pp23_out_s11;
wire pwrgood_pp24_out_d12;
wire pwrgood_pp25_out_s12;
wire pwrgood_pp26_out_d13;
wire pwrgood_pp27_out_s13;
wire pwrgood_pp28_out_d14;
wire pwrgood_pp29_out_s14;
wire pwrgood_pp30_out_d15;
wire pwrgood_pp31_out_s15;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_d0 , D[0], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_s0 , S[0], VPWR, VGND );
bufif1 bufif10 (Z , !pwrgood_pp0_out_d0, pwrgood_pp1_out_s0 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp2 (pwrgood_pp2_out_d1 , D[1], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp3 (pwrgood_pp3_out_s1 , S[1], VPWR, VGND );
bufif1 bufif11 (Z , !pwrgood_pp2_out_d1, pwrgood_pp3_out_s1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp4 (pwrgood_pp4_out_d2 , D[2], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp5 (pwrgood_pp5_out_s2 , S[2], VPWR, VGND );
bufif1 bufif12 (Z , !pwrgood_pp4_out_d2, pwrgood_pp5_out_s2 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp6 (pwrgood_pp6_out_d3 , D[3], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp7 (pwrgood_pp7_out_s3 , S[3], VPWR, VGND );
bufif1 bufif13 (Z , !pwrgood_pp6_out_d3, pwrgood_pp7_out_s3 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp8 (pwrgood_pp8_out_d4 , D[4], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp9 (pwrgood_pp9_out_s4 , S[4], VPWR, VGND );
bufif1 bufif14 (Z , !pwrgood_pp8_out_d4, pwrgood_pp9_out_s4 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp10 (pwrgood_pp10_out_d5 , D[5], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp11 (pwrgood_pp11_out_s5 , S[5], VPWR, VGND );
bufif1 bufif15 (Z , !pwrgood_pp10_out_d5, pwrgood_pp11_out_s5 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp12 (pwrgood_pp12_out_d6 , D[6], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp13 (pwrgood_pp13_out_s6 , S[6], VPWR, VGND );
bufif1 bufif16 (Z , !pwrgood_pp12_out_d6, pwrgood_pp13_out_s6 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp14 (pwrgood_pp14_out_d7 , D[7], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp15 (pwrgood_pp15_out_s7 , S[7], VPWR, VGND );
bufif1 bufif17 (Z , !pwrgood_pp14_out_d7, pwrgood_pp15_out_s7 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp16 (pwrgood_pp16_out_d8 , D[8], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp17 (pwrgood_pp17_out_s8 , S[8], VPWR, VGND );
bufif1 bufif18 (Z , !pwrgood_pp16_out_d8, pwrgood_pp17_out_s8 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp18 (pwrgood_pp18_out_d9 , D[9], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp19 (pwrgood_pp19_out_s9 , S[9], VPWR, VGND );
bufif1 bufif19 (Z , !pwrgood_pp18_out_d9, pwrgood_pp19_out_s9 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp20 (pwrgood_pp20_out_d10, D[10], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp21 (pwrgood_pp21_out_s10, S[10], VPWR, VGND );
bufif1 bufif110 (Z , !pwrgood_pp20_out_d10, pwrgood_pp21_out_s10);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp22 (pwrgood_pp22_out_d11, D[11], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp23 (pwrgood_pp23_out_s11, S[11], VPWR, VGND );
bufif1 bufif111 (Z , !pwrgood_pp22_out_d11, pwrgood_pp23_out_s11);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp24 (pwrgood_pp24_out_d12, D[12], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp25 (pwrgood_pp25_out_s12, S[12], VPWR, VGND );
bufif1 bufif112 (Z , !pwrgood_pp24_out_d12, pwrgood_pp25_out_s12);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp26 (pwrgood_pp26_out_d13, D[13], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp27 (pwrgood_pp27_out_s13, S[13], VPWR, VGND );
bufif1 bufif113 (Z , !pwrgood_pp26_out_d13, pwrgood_pp27_out_s13);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp28 (pwrgood_pp28_out_d14, D[14], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp29 (pwrgood_pp29_out_s14, S[14], VPWR, VGND );
bufif1 bufif114 (Z , !pwrgood_pp28_out_d14, pwrgood_pp29_out_s14);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp30 (pwrgood_pp30_out_d15, D[15], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp31 (pwrgood_pp31_out_s15, S[15], VPWR, VGND );
bufif1 bufif115 (Z , !pwrgood_pp30_out_d15, pwrgood_pp31_out_s15);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB16TO1_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:58:37 09/29/2014
// Design Name: fifo
// Module Name: C:/ece4743/projects/lab7_solution/tb_fifo.v
// Project Name: lab7_solution
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: fifo
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_fifo;
// Inputs
reg clk;
reg reset;
reg sclr;
reg wren;
reg rden;
reg [7:0] din;
// Outputs
wire full;
wire empty;
wire [7:0] dout;
// Instantiate the Unit Under Test (UUT)
fifo uut (
.clk(clk),
.reset(reset),
.sclr(sclr),
.wren(wren),
.rden(rden),
.full(full),
.empty(empty),
.din(din),
.dout(dout)
);
initial begin
clk = 0;
#100 //reset delay
forever #30 clk = ~clk;
end
integer errors;
integer writeval;
integer fd;
integer count,status;
reg[8*100:1] aline;
integer i_sclr, i_wren, i_wdata, i_rden, i_rdata, i_full, i_empty;
initial begin
// Initialize Inputs
#1
clk = 0;
reset = 1;
sclr = 0;
wren = 0;
rden = 0;
din = 0;
errors = 0;
count = 0;
fd = $fopen("fifo_vectors.txt","r");
// Wait 100 ns for global reset to finish
#100;
reset = 0;
@(posedge clk);
while ($fgets(aline,fd)) begin
if (count != 0) begin
status = $sscanf(aline,"%x %x %x %x %x %x %x",i_sclr,i_wren, i_wdata, i_rden, i_rdata, i_full, i_empty);
sclr = i_sclr;
wren = i_wren;
din = i_wdata;
rden = i_rden;
@(negedge clk);
if (i_rden) begin
if (i_rdata == dout) begin
$display("%d Pass: dout: %x",count,dout);
end else begin
$display("%d FAIL: dout: %x(%x)",count,dout,i_rdata);
errors = errors+1;
end
end //end if (i_rden)
if (i_full == full) $display("%d Pass: full: %x",count,full);
else begin
$display("%d FAIL: full: %x (%x)",count,full,i_full);
errors = errors+1;
end
if (i_empty == empty) $display("%d Pass: empty: %x",count,empty);
else begin
$display("%d FAIL: empty: %x (%x)",count,empty,i_empty);
errors = errors+1;
end
end //end if (aline)
count = count + 1;
end //end while
if (errors == 0) begin
$display("(%t)PASSED: All vectors passed",$time());
end else begin
$display("(%t)FAILED: %d vectors failed",$time(),errors);
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / OBUFDS_GTM_ADV
// /___/ /\ Filename : OBUFDS_GTM_ADV.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OBUFDS_GTM_ADV #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter integer REFCLK_ICNTL_TX = 0,
parameter [1:0] RXRECCLK_SEL = 2'b00
)(
output O,
output OB,
input CEB,
input [3:0] I
);
// define constants
localparam MODULE_NAME = "OBUFDS_GTM_ADV";
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFDS_GTM_ADV_dr.v"
`else
reg [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
reg [31:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX;
reg [1:0] RXRECCLK_SEL_REG = RXRECCLK_SEL;
`endif
`ifdef XIL_XECLIB
wire [3:0] REFCLK_ICNTL_TX_BIN;
`else
reg [3:0] REFCLK_ICNTL_TX_BIN;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
reg glblGTS = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
tri0 glblGTS = glbl.GTS;
`endif
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG[3:0];
`else
always @ (trig_attr) begin
#1;
REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG[3:0];
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((REFCLK_ICNTL_TX_REG != 0) &&
(REFCLK_ICNTL_TX_REG != 1) &&
(REFCLK_ICNTL_TX_REG != 3) &&
(REFCLK_ICNTL_TX_REG != 7) &&
(REFCLK_ICNTL_TX_REG != 15))) begin
$display("Error: [Unisim %s-102] REFCLK_ICNTL_TX attribute is set to %d. Legal values for this attribute are 0, 1, 3, 7 or 15. Instance: %m", MODULE_NAME, REFCLK_ICNTL_TX_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
// begin behavioral model
reg I_sel = 1'b0;
// =====================
// Generate I_sel
// =====================
always @(*) begin
case (RXRECCLK_SEL_REG)
2'b00: I_sel <= I[0];
2'b01: I_sel <= I[1];
2'b10: I_sel <= I[2];
2'b11: I_sel <= I[3];
default : I_sel <= I[0];
endcase
end
// =====================
// Generate O
// =====================
assign O = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : I_sel;
assign OB = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : ~I_sel;
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(CEB => O) = (0:0:0, 0:0:0);
(CEB => OB) = (0:0:0, 0:0:0);
(I[0] => O) = (0:0:0, 0:0:0);
(I[0] => OB) = (0:0:0, 0:0:0);
(I[1] => O) = (0:0:0, 0:0:0);
(I[1] => OB) = (0:0:0, 0:0:0);
(I[2] => O) = (0:0:0, 0:0:0);
(I[2] => OB) = (0:0:0, 0:0:0);
(I[3] => O) = (0:0:0, 0:0:0);
(I[3] => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
// end behavioral model
endmodule
`endcelldefine
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file RD_DATA_FIFO.v when simulating
// the core, RD_DATA_FIFO. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module RD_DATA_FIFO(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
prog_full
);
input rst;
input wr_clk;
input rd_clk;
input [255 : 0] din;
input wr_en;
input rd_en;
output [255 : 0] dout;
output full;
output empty;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(256),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(256),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(386),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(385),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(9),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.PROG_FULL(prog_full),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
/*******************************************************
MIST32 GCI Special Memory : Device Using
Make : 2011/09/27
Update : 2011/0
*******************************************************/
`default_nettype none
module gci_std_display_device_special_memory
#(
parameter USEMEMSIZE = 32'h00000000,
parameter PRIORITY = 32'h00000000,
parameter DEVICECAT = 32'h00000000
)(
//System
input wire iCLOCK,
input wire inRESET,
//Special Addr Access
input wire iSPECIAL_REQ,
input wire iSPECIAL_RW,
input wire [7:0] iSPECIAL_ADDR,
input wire [31:0] iSPECIAL_DATA,
output wire [31:0] oSPECIAL_DATA
);
integer i;
reg [31:0] b_mem[0:255];
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
for(i = 0; i < 256; i = i + 1)begin
if(i == 0)begin
//USEMEMSIZE
b_mem[i] <= USEMEMSIZE;
end
else if(i == 1)begin
//PRIORITY
b_mem[i] <= PRIORITY;
end
else begin
//Other
b_mem[i] <= 32'h00000000;
end
end
end
else begin
if(iSPECIAL_REQ && iSPECIAL_RW)begin
b_mem [iSPECIAL_ADDR] <= iSPECIAL_ADDR;
end
end
end //always
assign oSPECIAL_DATA = b_mem[iSPECIAL_ADDR];
endmodule
`default_nettype wire
|
module add_tb;
parameter N_BITS_A = 3;
parameter BIN_PT_A = 1;
parameter N_BITS_B = 4;
parameter BIN_PT_B = 3;
parameter N_BITS_OUT = 6;
parameter BIN_PT_OUT = 3;
reg [N_BITS_A-1:0] a;
reg [N_BITS_B-1:0] b;
wire [N_BITS_OUT-1:0] sum;
initial begin
a = 3'b0_0_0; // 0
b = 4'b0_001; // + 1/8
// 1/8
#10
a = 3'b1_1_1; // -1/2
b = 4'b0_001; // + 1/8
// -3/8
#5
a = 3'b1_1_0; // -1
b = 4'b1_100; // + -1/2
// -3/2
#5
a = 3'b0_1_1; // 3/2
b = 4'b1_110; // + -1/4
// 5/4
#10 ;
$finish;
end //initial
add #(.N_BITS_A(N_BITS_A),
.BIN_PT_A(BIN_PT_A),
.N_BITS_B(N_BITS_B),
.BIN_PT_B(BIN_PT_B)) a0 (a, b, sum);
initial begin
$monitor("%t, a = \t(%d,%d)b'%b\t a_padded = \t(%d,%d)b'%b\n%t, b = \t(%d,%d)b'%b\t b_padded = \t(%d,%d)b'%b\n%t, sum = \t\t\t\t\t(%d,%d)b'%b", $time, N_BITS_A, BIN_PT_A, a, N_BITS_OUT, BIN_PT_OUT, a0.a_padded, $time, N_BITS_B, BIN_PT_B, b, N_BITS_OUT, BIN_PT_OUT, a0.b_padded, $time, N_BITS_OUT, BIN_PT_OUT, sum);
end
endmodule //add_tb
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_impctl_upclk.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_impctl_upclk(int_sclk ,l2clk ,synced_upd_imped ,updclk ,
reset_l ,oe_out ,bypass ,avgcntr_rst ,so_l ,hard_reset_n ,si_l ,se
,global_reset_n );
output updclk ;
output oe_out ;
output bypass ;
output avgcntr_rst ;
output so_l ;
output global_reset_n ;
input int_sclk ;
input l2clk ;
input synced_upd_imped ;
input reset_l ;
input hard_reset_n ;
input si_l ;
input se ;
wire [9:0] scan_data ;
wire [7:0] ucarry ;
wire [7:0] next_ucount ;
wire [7:0] ucount ;
wire net183 ;
wire net184 ;
wire net106 ;
wire net187 ;
wire net72 ;
wire net74 ;
wire net190 ;
wire net78 ;
wire net193 ;
wire net112 ;
wire net80 ;
wire net82 ;
wire net88 ;
wire net121 ;
wire int_avgcntr_rst ;
wire net91 ;
wire net94 ;
wire net97 ;
wire osflag_n ;
wire net164 ;
wire net166 ;
wire net168 ;
wire scan_in ;
wire scan_out ;
wire net178 ;
wire osflag ;
wire oneshot_trig ;
wire net181 ;
bw_u1_soffr_4x I226 (
.q (osflag_n ),
.so (scan_data[9] ),
.ck (l2clk ),
.d (net187 ),
.se (se ),
.sd (scan_in ),
.r_l (hard_reset_n ) );
bw_u1_xor2_4x I218_7_ (
.z (next_ucount[7] ),
.a (ucarry[6] ),
.b (ucount[7] ) );
bw_u1_inv_5x I228 (
.z (int_avgcntr_rst ),
.a (net72 ) );
bw_u1_soffr_4x I229 (
.q (avgcntr_rst ),
.so (scan_data[8] ),
.ck (l2clk ),
.d (int_avgcntr_rst ),
.se (se ),
.sd (scan_data[9] ),
.r_l (global_reset_n ) );
bw_u1_inv_5x I234 (
.z (scan_in ),
.a (si_l ) );
bw_u1_soffr_4x I217_4_ (
.q (ucount[4] ),
.so (scan_data[4] ),
.ck (l2clk ),
.d (next_ucount[4] ),
.se (se ),
.sd (scan_data[5] ),
.r_l (global_reset_n ) );
bw_u1_xor2_4x I218_6_ (
.z (next_ucount[6] ),
.a (ucarry[5] ),
.b (ucount[6] ) );
bw_u1_nand2_7x I241 (
.z (net106 ),
.a (net121 ),
.b (net164 ) );
bw_u1_nor2_4x I242 (
.z (net121 ),
.a (net168 ),
.b (synced_upd_imped ) );
bw_u1_soffr_4x I217_3_ (
.q (ucount[3] ),
.so (scan_data[3] ),
.ck (l2clk ),
.d (next_ucount[3] ),
.se (se ),
.sd (scan_data[4] ),
.r_l (global_reset_n ) );
bw_u1_xor2_4x I218_5_ (
.z (next_ucount[5] ),
.a (ucarry[4] ),
.b (ucount[5] ) );
bw_u1_nand2_2x I245 (
.z (net94 ),
.a (osflag ),
.b (oneshot_trig ) );
bw_u1_inv_4x I246 (
.z (net168 ),
.a (net94 ) );
bw_u1_nand2_2x I248 (
.z (net91 ),
.a (hard_reset_n ),
.b (reset_l ) );
bw_u1_inv_4x I249 (
.z (net164 ),
.a (net91 ) );
bw_u1_inv_20x I252 (
.z (global_reset_n ),
.a (net106 ) );
bw_u1_nand2_4x I253 (
.z (net190 ),
.a (int_sclk ),
.b (ucount[0] ) );
bw_u1_soffr_4x I217_2_ (
.q (ucount[2] ),
.so (scan_data[2] ),
.ck (l2clk ),
.d (next_ucount[2] ),
.se (se ),
.sd (scan_data[3] ),
.r_l (global_reset_n ) );
bw_u1_xor2_4x I218_4_ (
.z (next_ucount[4] ),
.a (ucarry[3] ),
.b (ucount[4] ) );
bw_u1_nor2_6x I255 (
.z (oneshot_trig ),
.a (net181 ),
.b (net193 ) );
bw_u1_nand2_4x I256 (
.z (net181 ),
.a (ucount[2] ),
.b (ucount[3] ) );
bw_u1_nor2_2x I257 (
.z (ucarry[7] ),
.a (net97 ),
.b (net112 ) );
bw_u1_nand2_7x I258 (
.z (oe_out ),
.a (net97 ),
.b (net178 ) );
bw_u1_inv_5x I259 (
.z (bypass ),
.a (osflag_n ) );
bw_u1_inv_4x I260 (
.z (net166 ),
.a (ucarry[7] ) );
bw_u1_inv_4x I163 (
.z (ucarry[0] ),
.a (net190 ) );
bw_u1_inv_2x I261 (
.z (net74 ),
.a (oneshot_trig ) );
bw_u1_nand2_4x I164 (
.z (net193 ),
.a (ucarry[0] ),
.b (ucount[1] ) );
bw_u1_inv_2x I262 (
.z (net72 ),
.a (ucarry[5] ) );
bw_u1_inv_4x I165 (
.z (ucarry[1] ),
.a (net193 ) );
bw_u1_soffr_4x I217_1_ (
.q (ucount[1] ),
.so (scan_data[1] ),
.ck (l2clk ),
.d (next_ucount[1] ),
.se (se ),
.sd (scan_data[2] ),
.r_l (global_reset_n ) );
bw_u1_inv_2x I166 (
.z (net82 ),
.a (ucount[2] ) );
bw_u1_xor2_4x I218_3_ (
.z (next_ucount[3] ),
.a (ucarry[2] ),
.b (ucount[3] ) );
bw_u1_nor2_4x I167 (
.z (ucarry[2] ),
.a (net82 ),
.b (net193 ) );
bw_u1_nor2_4x I175 (
.z (ucarry[6] ),
.a (net78 ),
.b (net112 ) );
bw_u1_soffr_4x I217_0_ (
.q (ucount[0] ),
.so (scan_data[0] ),
.ck (l2clk ),
.d (next_ucount[0] ),
.se (se ),
.sd (scan_data[1] ),
.r_l (global_reset_n ) );
bw_u1_xor2_4x I218_2_ (
.z (next_ucount[2] ),
.a (ucarry[1] ),
.b (ucount[2] ) );
bw_u1_inv_5x I179 (
.z (ucarry[5] ),
.a (net112 ) );
bw_u1_inv_2x I180 (
.z (net78 ),
.a (ucount[6] ) );
bw_u1_inv_4x I205 (
.z (ucarry[3] ),
.a (net74 ) );
bw_u1_xor2_4x I218_1_ (
.z (next_ucount[1] ),
.a (ucarry[0] ),
.b (ucount[1] ) );
bw_u1_inv_4x I187 (
.z (ucarry[4] ),
.a (net88 ) );
bw_u1_soffr_4x I217_7_ (
.q (ucount[7] ),
.so (scan_data[7] ),
.ck (l2clk ),
.d (next_ucount[7] ),
.se (se ),
.sd (scan_data[8] ),
.r_l (global_reset_n ) );
bw_u1_nand2_5x I207 (
.z (net97 ),
.a (ucount[6] ),
.b (ucount[7] ) );
bw_u1_inv_4x I208 (
.z (net178 ),
.a (bypass ) );
bw_u1_nand3_4x I189 (
.z (net112 ),
.a (oneshot_trig ),
.b (ucount[4] ),
.c (ucount[5] ) );
bw_u1_nand2_4x I211 (
.z (net184 ),
.a (net166 ),
.b (net183 ) );
bw_u1_nand2_2x I212 (
.z (net183 ),
.a (bypass ),
.b (int_sclk ) );
bw_u1_soffr_4x I217_6_ (
.q (ucount[6] ),
.so (scan_data[6] ),
.ck (l2clk ),
.d (next_ucount[6] ),
.se (se ),
.sd (scan_data[7] ),
.r_l (global_reset_n ) );
bw_u1_xor2_4x I218_0_ (
.z (next_ucount[0] ),
.a (int_sclk ),
.b (ucount[0] ) );
bw_u1_nand2_2x I196 (
.z (net88 ),
.a (oneshot_trig ),
.b (ucount[4] ) );
bw_u1_inv_5x I198 (
.z (so_l ),
.a (scan_out ) );
bw_u1_soffr_4x I199 (
.q (updclk ),
.so (scan_out ),
.ck (l2clk ),
.d (net184 ),
.se (se ),
.sd (scan_data[0] ),
.r_l (global_reset_n ) );
bw_u1_nand2_4x I223 (
.z (net187 ),
.a (osflag ),
.b (net80 ) );
bw_u1_inv_2x I224 (
.z (net80 ),
.a (oneshot_trig ) );
bw_u1_soffr_4x I217_5_ (
.q (ucount[5] ),
.so (scan_data[5] ),
.ck (l2clk ),
.d (next_ucount[5] ),
.se (se ),
.sd (scan_data[6] ),
.r_l (global_reset_n ) );
bw_u1_inv_2x I225 (
.z (osflag ),
.a (osflag_n ) );
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ciop_iob.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`timescale 1ps/1ps
module ciop_iob(
// Outputs
iob_pcx_stall_pq, iob_jbi_mondo_nack, iob_jbi_mondo_ack,
iob_jbi_dbg_lo_vld, iob_jbi_dbg_lo_data, iob_jbi_dbg_hi_vld,
iob_jbi_dbg_hi_data, iob_io_dbg_en, iob_io_dbg_data,
iob_ctu_coreavail, iob_cpx_req_cq, iob_cpx_data_ca, iob_clk_tr,
iob_clk_l2_tr, iob_clk_data, iob_clk_stall, iob_clk_vld,
iob_dram02_data, iob_dram02_stall, iob_dram02_vld,
iob_dram13_data, iob_dram13_stall, iob_dram13_vld,
iob_jbi_pio_data, iob_jbi_pio_stall, iob_jbi_pio_vld,
iob_jbi_spi_data, iob_jbi_spi_stall, iob_jbi_spi_vld,
iob_tap_data, iob_tap_stall, iob_tap_vld, iob_scanout,
iob_io_dbg_ck_p, iob_io_dbg_ck_n,
// Inputs
pcx_iob_data_rdy_px2, pcx_iob_data_px2, l2_dbgbus_23,
l2_dbgbus_01, jbus_grst_l, jbus_gdbginit_l, jbus_gclk,
jbus_arst_l, jbus_adbginit_l, jbi_iob_mondo_vld,
jbi_iob_mondo_data, io_trigin, io_temp_trig, global_shift_enable,
efc_iob_sernum2_dshift, efc_iob_sernum1_dshift,
efc_iob_sernum0_dshift, efc_iob_fusestat_dshift,
efc_iob_fuse_data, efc_iob_fuse_clk2, efc_iob_fuse_clk1,
efc_iob_coreavail_dshift, dbg_en_23, dbg_en_01,
ctu_tst_short_chain, ctu_tst_scanmode, ctu_tst_scan_disable,
ctu_tst_pre_grst_l, ctu_tst_macrotest, ctu_iob_wake_thr,
cpx_iob_grant_cx2, cmp_grst_l, cmp_gdbginit_l, cmp_gclk,
cmp_arst_l, cmp_adbginit_l, clspine_jbus_tx_sync,
clspine_jbus_rx_sync, clspine_iob_resetstat_wr,
clspine_iob_resetstat, clk_iob_cken, clk_iob_data, clk_iob_stall,
clk_iob_vld, dram02_iob_data, dram02_iob_stall, dram02_iob_vld,
dram13_iob_data, dram13_iob_stall, dram13_iob_vld,
jbi_iob_pio_data, jbi_iob_pio_stall, jbi_iob_pio_vld,
jbi_iob_spi_data, jbi_iob_spi_stall, jbi_iob_spi_vld,
tap_iob_data, tap_iob_stall, tap_iob_vld, iob_scanin,
spc0_inst_done, pc_w0, spc1_inst_done, pc_w1, spc2_inst_done,
pc_w2, spc3_inst_done, pc_w3, spc4_inst_done, pc_w4,
spc5_inst_done, pc_w5, spc6_inst_done, pc_w6, spc7_inst_done,
pc_w7
);
input clk_iob_cken; // To bw_clk_cl_iobdg_cmp of bw_clk_cl_iobdg_cmp.v, ...
input [`IOB_RESET_STAT_WIDTH-1:0]clspine_iob_resetstat;// To iobdg_ctrl of iobdg_ctrl.v
input clspine_iob_resetstat_wr;// To iobdg_ctrl of iobdg_ctrl.v
input clspine_jbus_rx_sync; // To cluster_header_sync of cluster_header_sync.v
input clspine_jbus_tx_sync; // To cluster_header_sync of cluster_header_sync.v
input cmp_adbginit_l; // To bw_clk_cl_iobdg_cmp of bw_clk_cl_iobdg_cmp.v
input cmp_arst_l; // To bw_clk_cl_iobdg_cmp of bw_clk_cl_iobdg_cmp.v
input cmp_gclk; // To bw_clk_cl_iobdg_cmp of bw_clk_cl_iobdg_cmp.v, ...
input cmp_gdbginit_l; // To bw_clk_cl_iobdg_cmp of bw_clk_cl_iobdg_cmp.v
input cmp_grst_l; // To bw_clk_cl_iobdg_cmp of bw_clk_cl_iobdg_cmp.v
input [`IOB_CPU_WIDTH-1:0]cpx_iob_grant_cx2; // To i2c of i2c.v
input ctu_iob_wake_thr; // To iobdg_ctrl of iobdg_ctrl.v
input ctu_tst_macrotest; // To test_stub_scan of test_stub_scan.v
input ctu_tst_pre_grst_l; // To test_stub_scan of test_stub_scan.v
input ctu_tst_scan_disable; // To test_stub_scan of test_stub_scan.v
input ctu_tst_scanmode; // To test_stub_scan of test_stub_scan.v
input ctu_tst_short_chain; // To test_stub_scan of test_stub_scan.v
input dbg_en_01; // To iobdg_dbg of iobdg_dbg.v
input dbg_en_23; // To iobdg_dbg of iobdg_dbg.v
input efc_iob_coreavail_dshift;// To iobdg_ctrl of iobdg_ctrl.v
input efc_iob_fuse_clk1; // To iobdg_ctrl of iobdg_ctrl.v
input efc_iob_fuse_clk2; // To iobdg_ctrl of iobdg_ctrl.v
input efc_iob_fuse_data; // To iobdg_ctrl of iobdg_ctrl.v
input efc_iob_fusestat_dshift;// To iobdg_ctrl of iobdg_ctrl.v
input efc_iob_sernum0_dshift; // To iobdg_ctrl of iobdg_ctrl.v
input efc_iob_sernum1_dshift; // To iobdg_ctrl of iobdg_ctrl.v
input efc_iob_sernum2_dshift; // To iobdg_ctrl of iobdg_ctrl.v
input global_shift_enable; // To test_stub_scan of test_stub_scan.v
input io_temp_trig; // To iobdg_ctrl of iobdg_ctrl.v
input io_trigin; // To iobdg_dbg of iobdg_dbg.v
input [`JBI_IOB_MONDO_BUS_WIDTH-1:0]jbi_iob_mondo_data;// To i2c of i2c.v
input jbi_iob_mondo_vld; // To i2c of i2c.v
input jbus_adbginit_l; // To bw_clk_cl_iobdg_jbus of bw_clk_cl_iobdg_jbus.v
input jbus_arst_l; // To bw_clk_cl_iobdg_jbus of bw_clk_cl_iobdg_jbus.v, ...
input jbus_gclk; // To bw_clk_cl_iobdg_jbus of bw_clk_cl_iobdg_jbus.v
input jbus_gdbginit_l; // To bw_clk_cl_iobdg_jbus of bw_clk_cl_iobdg_jbus.v
input jbus_grst_l; // To bw_clk_cl_iobdg_jbus of bw_clk_cl_iobdg_jbus.v
input [39:0] l2_dbgbus_01; // To iobdg_dbg of iobdg_dbg.v
input [39:0] l2_dbgbus_23; // To iobdg_dbg of iobdg_dbg.v
input [`PCX_WIDTH-1:0]pcx_iob_data_px2; // To c2i of c2i.v
input pcx_iob_data_rdy_px2; // To c2i of c2i.v
input spc0_inst_done;
input [48:0] pc_w0;
input spc1_inst_done;
input [48:0] pc_w1;
input spc2_inst_done;
input [48:0] pc_w2;
input spc3_inst_done;
input [48:0] pc_w3;
input spc4_inst_done;
input [48:0] pc_w4;
input spc5_inst_done;
input [48:0] pc_w5;
input spc6_inst_done;
input [48:0] pc_w6;
input spc7_inst_done;
input [48:0] pc_w7;
output iob_clk_l2_tr; // From iobdg_dbg of iobdg_dbg.v
output iob_clk_tr; // From iobdg_dbg of iobdg_dbg.v
output [`CPX_WIDTH-1:0]iob_cpx_data_ca; // From i2c of i2c.v
output [`IOB_CPU_WIDTH-1:0]iob_cpx_req_cq; // From i2c of i2c.v
output [`IOB_CPU_WIDTH-1:0]iob_ctu_coreavail;// From iobdg_ctrl of iobdg_ctrl.v
output [39:0] iob_io_dbg_data; // From iobdg_dbg of iobdg_dbg.v
output iob_io_dbg_en; // From iobdg_dbg of iobdg_dbg.v
output [47:0] iob_jbi_dbg_hi_data; // From iobdg_dbg of iobdg_dbg.v
output iob_jbi_dbg_hi_vld; // From iobdg_dbg of iobdg_dbg.v
output [47:0] iob_jbi_dbg_lo_data; // From iobdg_dbg of iobdg_dbg.v
output iob_jbi_dbg_lo_vld; // From iobdg_dbg of iobdg_dbg.v
output iob_jbi_mondo_ack; // From i2c of i2c.v
output iob_jbi_mondo_nack; // From i2c of i2c.v
output iob_pcx_stall_pq; // From c2i of c2i.v
input [`CLK_IOB_WIDTH-1:0]clk_iob_data; // To i2c of i2c.v
input clk_iob_stall; // To c2i of c2i.v
input clk_iob_vld; // To i2c of i2c.v
input [`DRAM_IOB_WIDTH-1:0]dram02_iob_data; // To i2c of i2c.v
input dram02_iob_stall; // To c2i of c2i.v
input dram02_iob_vld; // To i2c of i2c.v
input [`DRAM_IOB_WIDTH-1:0]dram13_iob_data; // To i2c of i2c.v
input dram13_iob_stall; // To c2i of c2i.v
input dram13_iob_vld; // To i2c of i2c.v
input [`JBI_IOB_WIDTH-1:0]jbi_iob_pio_data; // To i2c of i2c.v
input jbi_iob_pio_stall; // To c2i of c2i.v
input jbi_iob_pio_vld; // To i2c of i2c.v
input [`SPI_IOB_WIDTH-1:0]jbi_iob_spi_data; // To i2c of i2c.v
input jbi_iob_spi_stall; // To c2i of c2i.v
input jbi_iob_spi_vld; // To i2c of i2c.v
input [`TAP_IOB_WIDTH-1:0]tap_iob_data; // To c2i of c2i.v
input tap_iob_stall; // To i2c of i2c.v
input tap_iob_vld; // To c2i of c2i.v
output [`IOB_CLK_WIDTH-1:0]iob_clk_data; // From c2i of c2i.v
output iob_clk_stall; // From i2c of i2c.v
output iob_clk_vld; // From c2i of c2i.v
output [`IOB_DRAM_WIDTH-1:0]iob_dram02_data; // From c2i of c2i.v
output iob_dram02_stall; // From i2c of i2c.v
output iob_dram02_vld; // From c2i of c2i.v
output [`IOB_DRAM_WIDTH-1:0]iob_dram13_data; // From c2i of c2i.v
output iob_dram13_stall; // From i2c of i2c.v
output iob_dram13_vld; // From c2i of c2i.v
output [`IOB_JBI_WIDTH-1:0]iob_jbi_pio_data; // From c2i of c2i.v
output iob_jbi_pio_stall; // From i2c of i2c.v
output iob_jbi_pio_vld; // From c2i of c2i.v
output [`IOB_SPI_WIDTH-1:0]iob_jbi_spi_data; // From c2i of c2i.v
output iob_jbi_spi_stall; // From i2c of i2c.v
output iob_jbi_spi_vld; // From c2i of c2i.v
output [`IOB_TAP_WIDTH-1:0]iob_tap_data; // From i2c of i2c.v
output iob_tap_stall; // From c2i of c2i.v
output iob_tap_vld; // From i2c of i2c.v
input iob_scanin;
output iob_scanout;
output [2:0] iob_io_dbg_ck_p;
output [2:0] iob_io_dbg_ck_n;
//temp. memory.
reg [`IOB_CPU_WIDTH-1:0] cpx_req;
reg [`CPX_WIDTH-1:0] cpx_data;
reg pio_vld;
reg [`IOB_JBI_WIDTH-1:0] pio_data;
//jbi ucb
reg [3:0] jspi_data;
reg jspi_stall;
reg jspi_vld;
//iob and dram interface
reg [3:0] dram02_data;
reg dram02_vld;
reg [3:0] dram13_data;
reg dram13_vld;
wire iob_pcx_stall_pq;
wire iob_jbi_pio_stall;
wire iob_jbi_dbg_hi_vld;
wire iob_jbi_dbg_lo_vld;
wire iob_jbi_mondo_ack;
wire iob_jbi_mondo_nack;
wire iob_clk_stall;
wire iob_clk_vld;
wire iob_clspine_stall;
wire iob_clspine_vld;
wire iob_dram02_stall;
wire iob_dram02_vld;
wire iob_dram13_stall;
wire iob_dram13_vld;
wire iob_jbi_spi_stall;
wire iob_jbi_spi_vld;
wire iob_tap_stall;
wire iob_tap_vld;
// input signals
wire [`PCX_WIDTH-1:0] pcx_iob_data = pcx_iob_data_px2;
wire [`IOB_CPU_WIDTH-1:0] cpx_iob_grant = cpx_iob_grant_cx2;
wire spc0_inst_done_buf = spc0_inst_done;
wire [48:0] pc_w0_buf = pc_w0;
wire spc1_inst_done_buf = spc1_inst_done;
wire [48:0] pc_w1_buf = pc_w1;
wire spc2_inst_done_buf = spc2_inst_done;
wire [48:0] pc_w2_buf = pc_w2;
wire spc3_inst_done_buf = spc3_inst_done;
wire [48:0] pc_w3_buf = pc_w3;
wire spc4_inst_done_buf = spc4_inst_done;
wire [48:0] pc_w4_buf = pc_w4;
wire spc5_inst_done_buf = spc5_inst_done;
wire [48:0] pc_w5_buf = pc_w5;
wire spc6_inst_done_buf = spc6_inst_done;
wire [48:0] pc_w6_buf = pc_w6;
wire spc7_inst_done_buf = spc7_inst_done;
wire [48:0] pc_w7_buf = pc_w7;
//drive signals.
assign iob_pcx_stall_pq = 0;
assign iob_jbi_pio_stall = 0;
assign iob_cpx_req_cq = cpx_req;
assign iob_cpx_data_ca = cpx_data;
assign iob_jbi_pio_vld = pio_vld;
assign iob_jbi_pio_data = pio_data;
assign iob_jbi_dbg_hi_vld = 0;
assign iob_jbi_dbg_lo_vld = 0;
assign iob_jbi_mondo_ack = 0;
assign iob_jbi_mondo_nack = 0;
assign iob_clk_stall = 0;
assign iob_clk_vld = 0;
assign iob_clspine_stall = 0;
assign iob_clspine_vld = 0;
assign iob_dram02_stall = 0;
assign iob_dram02_vld = dram02_vld;
assign iob_dram02_data = dram02_data;
assign iob_dram13_stall = 0;
assign iob_dram13_vld = dram13_vld;
assign iob_dram13_data = dram13_data;
assign iob_jbi_spi_stall = 0;
assign iob_jbi_spi_vld = 0;
assign iob_tap_stall = 0;
assign iob_tap_vld = 0;
//jbi ucb interface here
assign iob_jbi_spi_stall = 0;
assign iob_jbi_spi_vld = jspi_vld;
assign iob_jbi_spi_data = jspi_data;
//Start here
reg ok_iob;
initial
begin
ok_iob = 0;
cpx_req = 0;
cpx_data = 0;
pio_vld = 0;
//iob and dram interface
dram02_data = 0;
dram02_vld = 0;
dram13_data = 0;
dram13_vld = 0;
//jbi
jspi_vld = 0;
jspi_data = 0;
$init_iob_model();
//repeat(1)@(posedge jbus_grst_l);//wait for the push butten reset.
repeat(1)@(posedge ctu_iob_wake_thr);
//repeat(4)@(posedge jbus_gclk);//Delay issuing wakeup interrupt to let ccx come out of reset.
ok_iob = 1;
end
//cmp clock domain
always @(negedge cmp_gclk)
begin
if(ok_iob)begin
$iob_cdriver(//input to pli
//pcx packet from core
pcx_iob_data,
//cpx request from iob
cpx_req,
cpx_data,
//grand and request
cpx_iob_grant,
//pc event
spc0_inst_done_buf,
pc_w0_buf,
spc1_inst_done_buf,
pc_w1_buf,
spc2_inst_done_buf,
pc_w2_buf,
spc3_inst_done_buf,
pc_w3_buf,
spc4_inst_done_buf,
pc_w4_buf,
spc5_inst_done_buf,
pc_w5_buf,
spc6_inst_done_buf,
pc_w6_buf,
spc7_inst_done_buf,
pc_w7_buf
);
end // if (ok_iob)
end // always @ (posedge cmp_gclk)
//jbus clock domain
always @(posedge jbus_gclk)begin
if(ok_iob)begin
$iob_jdriver(
pio_vld, pio_data,
//dram and iob interface
//output from pli
dram02_iob_stall, dram02_vld, dram02_data,
dram13_iob_stall, dram13_vld, dram13_data,
//input to pli.
dram02_iob_vld, dram02_iob_data,
dram13_iob_vld, dram13_iob_data,
//pio input 13-14
jbi_iob_pio_vld, jbi_iob_pio_data,
//jbi interface
//out from pli 13-15
jbi_iob_spi_stall, jspi_vld, jspi_data,
//in to pli 16-17
jbi_iob_spi_vld, jbi_iob_spi_data
);
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_axi_basic_rx_pipeline.v
// Version : 1.3
// //
// Description: //
// TRN to AXI RX pipeline. Converts received data from TRN protocol to AXI. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// axi_basic_rx_pipeline //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_3_axi_basic_rx_pipeline #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
// AXI RX
//-----------
output reg [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output reg m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output reg [21:0] m_axis_rx_tuser, // RX user signals
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output reg trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// Null Inputs
//-----------
input null_rx_tvalid, // NULL generated tvalid
input null_rx_tlast, // NULL generated tlast
input [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep
input null_rdst_rdy, // NULL generated rdst_rdy
input [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires and regs for creating AXI signals
wire [4:0] is_sof;
wire [4:0] is_sof_prev;
wire [4:0] is_eof;
wire [4:0] is_eof_prev;
reg [KEEP_WIDTH-1:0] reg_tkeep;
wire [KEEP_WIDTH-1:0] tkeep;
wire [KEEP_WIDTH-1:0] tkeep_prev;
reg reg_tlast;
wire rsrc_rdy_filtered;
// Wires and regs for previous value buffer
wire [C_DATA_WIDTH-1:0] trn_rd_DW_swapped;
reg [C_DATA_WIDTH-1:0] trn_rd_prev;
wire data_hold;
reg data_prev;
reg trn_reof_prev;
reg [REM_WIDTH-1:0] trn_rrem_prev;
reg trn_rsrc_rdy_prev;
reg trn_rsrc_dsc_prev;
reg trn_rsof_prev;
reg [6:0] trn_rbar_hit_prev;
reg trn_rerrfwd_prev;
reg trn_recrc_err_prev;
// Null packet handling signals
reg null_mux_sel;
reg trn_in_packet;
wire dsc_flag;
wire dsc_detect;
reg reg_dsc_detect;
reg trn_rsrc_dsc_d;
// Create "filtered" version of rsrc_rdy, where discontinued SOFs are removed.
assign rsrc_rdy_filtered = trn_rsrc_rdy &&
(trn_in_packet || (trn_rsof && !trn_rsrc_dsc));
//----------------------------------------------------------------------------//
// Previous value buffer //
// --------------------- //
// We are inserting a pipeline stage in between TRN and AXI, which causes //
// some issues with handshaking signals m_axis_rx_tready/trn_rdst_rdy. The //
// added cycle of latency in the path causes the user design to fall behind //
// the TRN interface whenever it throttles. //
// //
// To avoid loss of data, we must keep the previous value of all trn_r* //
// signals in case the user throttles. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_rd_prev <= #TCQ {C_DATA_WIDTH{1'b0}};
trn_rsof_prev <= #TCQ 1'b0;
trn_rrem_prev <= #TCQ {REM_WIDTH{1'b0}};
trn_rsrc_rdy_prev <= #TCQ 1'b0;
trn_rbar_hit_prev <= #TCQ 7'h00;
trn_rerrfwd_prev <= #TCQ 1'b0;
trn_recrc_err_prev <= #TCQ 1'b0;
trn_reof_prev <= #TCQ 1'b0;
trn_rsrc_dsc_prev <= #TCQ 1'b0;
end
else begin
// prev buffer works by checking trn_rdst_rdy. When trn_rdst_rdy is
// asserted, a new value is present on the interface.
if(trn_rdst_rdy) begin
trn_rd_prev <= #TCQ trn_rd_DW_swapped;
trn_rsof_prev <= #TCQ trn_rsof;
trn_rrem_prev <= #TCQ trn_rrem;
trn_rbar_hit_prev <= #TCQ trn_rbar_hit;
trn_rerrfwd_prev <= #TCQ trn_rerrfwd;
trn_recrc_err_prev <= #TCQ trn_recrc_err;
trn_rsrc_rdy_prev <= #TCQ rsrc_rdy_filtered;
trn_reof_prev <= #TCQ trn_reof;
trn_rsrc_dsc_prev <= #TCQ trn_rsrc_dsc || dsc_flag;
end
end
end
//----------------------------------------------------------------------------//
// Create TDATA //
//----------------------------------------------------------------------------//
// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN
// 128-bit: 64-bit: 32-bit:
// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0
// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0
// TRN DW2 maps to AXI DW1
// TRN DW3 maps to AXI DW0
generate
if(C_DATA_WIDTH == 128) begin : rd_DW_swap_128
assign trn_rd_DW_swapped = {trn_rd[31:0],
trn_rd[63:32],
trn_rd[95:64],
trn_rd[127:96]};
end
else if(C_DATA_WIDTH == 64) begin : rd_DW_swap_64
assign trn_rd_DW_swapped = {trn_rd[31:0], trn_rd[63:32]};
end
else begin : rd_DW_swap_32
assign trn_rd_DW_swapped = trn_rd;
end
endgenerate
// Create special buffer which locks in the proper value of TDATA depending
// on whether the user is throttling or not. This buffer has three states:
//
// HOLD state: TDATA maintains its current value
// - the user has throttled the PCIe block
// PREVIOUS state: the buffer provides the previous value on trn_rd
// - the user has finished throttling, and is a little behind
// the PCIe block
// CURRENT state: the buffer passes the current value on trn_rd
// - the user is caught up and ready to receive the latest
// data from the PCIe block
always @(posedge user_clk) begin
if(user_rst) begin
m_axis_rx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
end
else begin
if(!data_hold) begin
// PREVIOUS state
if(data_prev) begin
m_axis_rx_tdata <= #TCQ trn_rd_prev;
end
// CURRENT state
else begin
m_axis_rx_tdata <= #TCQ trn_rd_DW_swapped;
end
end
// else HOLD state
end
end
// Logic to instruct pipeline to hold its value
assign data_hold = (!m_axis_rx_tready && m_axis_rx_tvalid);
// Logic to instruct pipeline to use previous bus values. Always use previous
// value after holding a value.
always @(posedge user_clk) begin
if(user_rst) begin
data_prev <= #TCQ 1'b0;
end
else begin
data_prev <= #TCQ data_hold;
end
end
//----------------------------------------------------------------------------//
// Create TVALID, TLAST, tkeep, TUSER //
// ----------------------------------- //
// Use the same strategy for these signals as for TDATA, except here we need //
// an extra provision for null packets. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
m_axis_rx_tvalid <= #TCQ 1'b0;
reg_tlast <= #TCQ 1'b0;
reg_tkeep <= #TCQ {KEEP_WIDTH{1'b1}};
m_axis_rx_tuser <= #TCQ 22'h0;
end
else begin
if(!data_hold) begin
// If in a null packet, use null generated value
if(null_mux_sel) begin
m_axis_rx_tvalid <= #TCQ null_rx_tvalid;
reg_tlast <= #TCQ null_rx_tlast;
reg_tkeep <= #TCQ null_rx_tkeep;
m_axis_rx_tuser <= #TCQ {null_is_eof, 17'h0000};
end
// PREVIOUS state
else if(data_prev) begin
m_axis_rx_tvalid <= #TCQ (trn_rsrc_rdy_prev || dsc_flag);
reg_tlast <= #TCQ trn_reof_prev;
reg_tkeep <= #TCQ tkeep_prev;
m_axis_rx_tuser <= #TCQ {is_eof_prev, // TUSER bits [21:17]
2'b00, // TUSER bits [16:15]
is_sof_prev, // TUSER bits [14:10]
1'b0, // TUSER bit [9]
trn_rbar_hit_prev, // TUSER bits [8:2]
trn_rerrfwd_prev, // TUSER bit [1]
trn_recrc_err_prev}; // TUSER bit [0]
end
// CURRENT state
else begin
m_axis_rx_tvalid <= #TCQ (rsrc_rdy_filtered || dsc_flag);
reg_tlast <= #TCQ trn_reof;
reg_tkeep <= #TCQ tkeep;
m_axis_rx_tuser <= #TCQ {is_eof, // TUSER bits [21:17]
2'b00, // TUSER bits [16:15]
is_sof, // TUSER bits [14:10]
1'b0, // TUSER bit [9]
trn_rbar_hit, // TUSER bits [8:2]
trn_rerrfwd, // TUSER bit [1]
trn_recrc_err}; // TUSER bit [0]
end
end
// else HOLD state
end
end
// Hook up TLAST and tkeep depending on interface width
generate
// For 128-bit interface, don't pass TLAST and tkeep to user (is_eof and
// is_data passed to user instead). reg_tlast is still used internally.
if(C_DATA_WIDTH == 128) begin : tlast_tkeep_hookup_128
assign m_axis_rx_tlast = 1'b0;
assign m_axis_rx_tkeep = {KEEP_WIDTH{1'b1}};
end
// For 64/32-bit interface, pass TLAST to user.
else begin : tlast_tkeep_hookup_64_32
assign m_axis_rx_tlast = reg_tlast;
assign m_axis_rx_tkeep = reg_tkeep;
end
endgenerate
//----------------------------------------------------------------------------//
// Create tkeep //
// ------------ //
// Convert RREM to STRB. Here, we are converting the encoding method for the //
// location of the EOF from TRN flavor (rrem) to AXI (tkeep). //
// //
// NOTE: for each configuration, we need two values of tkeep, the current and //
// previous values. The need for these two values is described below. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : rrem_to_tkeep_128
// TLAST and tkeep not used in 128-bit interface. is_sof and is_eof used
// instead.
assign tkeep = 16'h0000;
assign tkeep_prev = 16'h0000;
end
else if(C_DATA_WIDTH == 64) begin : rrem_to_tkeep_64
// 64-bit interface: contains 2 DWORDs per cycle, for a total of 8 bytes
// - tkeep has only two possible values here, 0xFF or 0x0F
assign tkeep = trn_rrem ? 8'hFF : 8'h0F;
assign tkeep_prev = trn_rrem_prev ? 8'hFF : 8'h0F;
end
else begin : rrem_to_tkeep_32
// 32-bit interface: contains 1 DWORD per cycle, for a total of 4 bytes
// - tkeep is always 0xF in this case, due to the nature of the PCIe block
assign tkeep = 4'hF;
assign tkeep_prev = 4'hF;
end
endgenerate
//----------------------------------------------------------------------------//
// Create is_sof //
// ------------- //
// is_sof is a signal to the user indicating the location of SOF in TDATA . //
// Due to inherent 64-bit alignment of packets from the block, the only //
// possible values are: //
// Value Valid data widths //
// 5'b11000 (sof @ byte 8) 128 //
// 5'b10000 (sof @ byte 0) 128, 64, 32 //
// 5'b00000 (sof not present) 128, 64, 32 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : is_sof_128
assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable
(trn_rsof && !trn_rrem[1]), // bit 3: sof @ byte 8?
3'b000}; // bit 2-0: hardwired 0
assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
(trn_rsof_prev && !trn_rrem_prev[1]), // bit 3
3'b000}; // bit 2-0
end
else begin : is_sof_64_32
assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable
4'b0000}; // bit 3-0: hardwired 0
assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
4'b0000}; // bit 3-0
end
endgenerate
//----------------------------------------------------------------------------//
// Create is_eof //
// ------------- //
// is_eof is a signal to the user indicating the location of EOF in TDATA . //
// Due to DWORD granularity of packets from the block, the only //
// possible values are: //
// Value Valid data widths //
// 5'b11111 (eof @ byte 15) 128 //
// 5'b11011 (eof @ byte 11) 128 //
// 5'b10111 (eof @ byte 7) 128, 64 //
// 5'b10011 (eof @ byte 3)` 128, 64, 32 //
// 5'b00011 (eof not present) 128, 64, 32 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : is_eof_128
assign is_eof = {trn_reof, // bit 4: enable
trn_rrem, // bit 3-2: encoded eof loc rom block
2'b11}; // bit 1-0: hardwired 1
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
trn_rrem_prev, // bit 3-2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
end
else if(C_DATA_WIDTH == 64) begin : is_eof_64
assign is_eof = {trn_reof, // bit 4: enable
1'b0, // bit 3: hardwired 0
trn_rrem, // bit 2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
1'b0, // bit 3: hardwired 0
trn_rrem_prev, // bit 2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
end
else begin : is_eof_32
assign is_eof = {trn_reof, // bit 4: enable
4'b0011}; // bit 3-0: hardwired to byte 3
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
4'b0011}; // bit 3-0: hardwired to byte 3
end
endgenerate
//----------------------------------------------------------------------------//
// Create trn_rdst_rdy //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_rdst_rdy <= #TCQ 1'b0;
end
else begin
// If in a null packet, use null generated value
if(null_mux_sel && m_axis_rx_tready) begin
trn_rdst_rdy <= #TCQ null_rdst_rdy;
end
// If a discontinue needs to be serviced, throttle the block until we are
// ready to pad out the packet.
else if(dsc_flag) begin
trn_rdst_rdy <= #TCQ 1'b0;
end
// If in a packet, pass user back-pressure directly to block
else if(m_axis_rx_tvalid) begin
trn_rdst_rdy <= #TCQ m_axis_rx_tready;
end
// If idle, default to no back-pressure. We need to default to the
// "ready to accept data" state to make sure we catch the first
// clock of data of a new packet.
else begin
trn_rdst_rdy <= #TCQ 1'b1;
end
end
end
//----------------------------------------------------------------------------//
// Create null_mux_sel //
// null_mux_sel is the signal used to detect a discontinue situation and //
// mux in the null packet generated in rx_null_gen. Only mux in null data //
// when not at the beginningof a packet. SOF discontinues do not require //
// padding, as the whole packet is simply squashed instead. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
null_mux_sel <= #TCQ 1'b0;
end
else begin
// NULL packet done
if(null_mux_sel && null_rx_tlast && m_axis_rx_tready)
begin
null_mux_sel <= #TCQ 1'b0;
end
// Discontinue detected and we're in packet, so switch to NULL packet
else if(dsc_flag && !data_hold) begin
null_mux_sel <= #TCQ 1'b1;
end
end
end
//----------------------------------------------------------------------------//
// Create discontinue tracking signals //
//----------------------------------------------------------------------------//
// Create signal trn_in_packet, which is needed to validate trn_rsrc_dsc. We
// should ignore trn_rsrc_dsc when it's asserted out-of-packet.
always @(posedge user_clk) begin
if(user_rst) begin
trn_in_packet <= #TCQ 1'b0;
end
else begin
if(trn_rsof && !trn_reof && rsrc_rdy_filtered && trn_rdst_rdy)
begin
trn_in_packet <= #TCQ 1'b1;
end
else if(trn_rsrc_dsc) begin
trn_in_packet <= #TCQ 1'b0;
end
else if(trn_reof && !trn_rsof && trn_rsrc_rdy && trn_rdst_rdy) begin
trn_in_packet <= #TCQ 1'b0;
end
end
end
// Create dsc_flag, which identifies and stores mid-packet discontinues that
// require null packet padding. This signal is edge sensitive to trn_rsrc_dsc,
// to make sure we don't service the same dsc twice in the event that
// trn_rsrc_dsc stays asserted for longer than it takes to pad out the packet.
assign dsc_detect = trn_rsrc_dsc && !trn_rsrc_dsc_d && trn_in_packet &&
(!trn_rsof || trn_reof) && !(trn_rdst_rdy && trn_reof);
always @(posedge user_clk) begin
if(user_rst) begin
reg_dsc_detect <= #TCQ 1'b0;
trn_rsrc_dsc_d <= #TCQ 1'b0;
end
else begin
if(dsc_detect) begin
reg_dsc_detect <= #TCQ 1'b1;
end
else if(null_mux_sel) begin
reg_dsc_detect <= #TCQ 1'b0;
end
trn_rsrc_dsc_d <= #TCQ trn_rsrc_dsc;
end
end
assign dsc_flag = dsc_detect || reg_dsc_detect;
//----------------------------------------------------------------------------//
// Create np_counter (V6 128-bit only). This counter tells the V6 128-bit //
// interface core how many NP packets have left the RX pipeline. The V6 //
// 128-bit interface uses this count to perform rnp_ok modulation. //
//----------------------------------------------------------------------------//
generate
if(C_FAMILY == "V6" && C_DATA_WIDTH == 128) begin : np_cntr_to_128_enabled
reg [2:0] reg_np_counter;
// Look for NP packets beginning on lower (i.e. unaligned) start
wire mrd_lower = (!(|m_axis_rx_tdata[92:88]) && !m_axis_rx_tdata[94]);
wire mrd_lk_lower = (m_axis_rx_tdata[92:88] == 5'b00001);
wire io_rdwr_lower = (m_axis_rx_tdata[92:88] == 5'b00010);
wire cfg_rdwr_lower = (m_axis_rx_tdata[92:89] == 4'b0010);
wire atomic_lower = ((&m_axis_rx_tdata[91:90]) && m_axis_rx_tdata[94]);
wire np_pkt_lower = (mrd_lower ||
mrd_lk_lower ||
io_rdwr_lower ||
cfg_rdwr_lower ||
atomic_lower) && m_axis_rx_tuser[13];
// Look for NP packets beginning on upper (i.e. aligned) start
wire mrd_upper = (!(|m_axis_rx_tdata[28:24]) && !m_axis_rx_tdata[30]);
wire mrd_lk_upper = (m_axis_rx_tdata[28:24] == 5'b00001);
wire io_rdwr_upper = (m_axis_rx_tdata[28:24] == 5'b00010);
wire cfg_rdwr_upper = (m_axis_rx_tdata[28:25] == 4'b0010);
wire atomic_upper = ((&m_axis_rx_tdata[27:26]) && m_axis_rx_tdata[30]);
wire np_pkt_upper = (mrd_upper ||
mrd_lk_upper ||
io_rdwr_upper ||
cfg_rdwr_upper ||
atomic_upper) && !m_axis_rx_tuser[13];
wire pkt_accepted =
m_axis_rx_tuser[14] && m_axis_rx_tready && m_axis_rx_tvalid;
// Increment counter whenever an NP packet leaves the RX pipeline
always @(posedge user_clk) begin
if (user_rst) begin
reg_np_counter <= #TCQ 0;
end
else begin
if((np_pkt_lower || np_pkt_upper) && pkt_accepted)
begin
reg_np_counter <= #TCQ reg_np_counter + 3'h1;
end
end
end
assign np_counter = reg_np_counter;
end
else begin : np_cntr_to_128_disabled
assign np_counter = 3'h0;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21OI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A21OI_BLACKBOX_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21oi (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21OI_BLACKBOX_V
|
// File: processor.v
// Generated by MyHDL 0.9dev
// Date: Mon Jan 27 10:01:23 2014
`timescale 1ns/10ps
module processor (
clk,
reset,
buttons,
leds,
rx,
tx,
memoryaddr,
memoryin,
memoryout,
romrden,
ramrden,
ramwren,
fifodata,
fifore,
fifowe,
fifoempty,
fifofull,
fifoq
);
// clk (Ibool) -- The clock
// reset (IReset) -- Reset Signal
// buttons (I4) -- 4 input buttons
// leds (O4) -- 4 output LEDS
// rx (Ibool) -- input from rs232
// tx (Obool) -- output from rs232
// memoryaddr (O16) -- memory addr
// memoryin (I32) -- memory read
// memoryout (O32) -- memory write
// romrden (Obool) -- rom-readenable
// ramrden (Obool) -- ram-readenable
// ramwren (Obool) -- ram-writeenable
// fifodata (O8) -- fifo data in
// fifore (Obool) -- enable reading from fifo
// fifowe (Obool) -- enable writing to fifo
// fifoempty (Ibool) -- indicates, that fifo is empty
// fifofull (Ibool) -- indicates, that the fifo is full
// fifoq (I8) -- fifo data out
//
// baudrate -- the baudrate for the rs232
// enCache -- enable cache or not
// interesting -- A list with interesting signals will be returned
input clk;
input reset;
input [3:0] buttons;
output [3:0] leds;
reg [3:0] leds;
input rx;
output tx;
reg tx;
output [15:0] memoryaddr;
reg [15:0] memoryaddr;
input [31:0] memoryin;
wire [31:0] memoryin;
output [31:0] memoryout;
reg [31:0] memoryout;
output romrden;
wire romrden;
output ramrden;
wire ramrden;
output ramwren;
wire ramwren;
output [7:0] fifodata;
reg [7:0] fifodata;
output fifore;
wire fifore;
output fifowe;
reg fifowe;
input fifoempty;
input fifofull;
input [7:0] fifoq;
wire [3:0] irSource;
reg enJump;
reg enCall;
reg [31:0] rgX;
reg [31:0] rgY;
reg bufOp2;
reg cIn;
reg bufClk;
reg bufRy;
wire [31:0] pcOut;
reg rstreadybit;
wire [31:0] bbus;
reg readybit;
reg enReg;
wire [23:0] irImm24;
reg nIn;
wire [3:0] irSource2;
reg bufAddr;
wire irSup;
reg bufRsr;
reg mmuBuf;
reg enPc;
reg addrymux1;
reg addrymux0;
wire [3:0] irAluop;
wire [4:0] irJumpOp;
reg enRst;
reg bufPC;
reg bufBut;
reg bufAddr14;
reg enAlu;
wire [6:0] irPrefix;
wire irOp1;
wire irOp2;
reg zIn;
reg bufAlu;
reg enSup;
wire nOut;
wire cOut;
wire [3:0] irDest;
reg enMmu;
wire vOut;
reg enIr;
wire zOut;
reg enLed;
reg pmux;
reg vIn;
reg jumpResult;
wire [15:0] irImm16;
reg Memory_csO;
reg Memory_csA;
reg [31:0] Memory_mmuOut;
reg Memory_enW;
reg Memory_enO;
wire [31:0] Memory_mmuTristate_o;
reg [7:0] Memory_Mmu_waitingtimer;
reg [1:0] Memory_Mmu_state;
reg [31:0] Memory_Mmu_in_data;
reg Memory_Mmu_with_data;
reg [31:0] IO_ioOut;
wire [31:0] IO_ioTristate_o;
reg [3:0] IO_io_ledBuffer;
reg [3:0] RS232_reader_bitCnt;
reg [0:0] RS232_reader_state;
reg [10:0] RS232_reader_clkCnt;
reg [7:0] RS232_reader_data;
reg [3:0] RS232_writer_bitCnt;
reg [0:0] RS232_writer_state;
reg [31:0] RS232_writer_clkCnt;
reg [7:0] RS232_writer_data;
wire [31:0] RS232_readerTristate_o;
wire [31:0] ClkBuf_clkOut;
reg [31:0] ClkBuf_clock_data;
wire [31:0] ClkBuf_clkTristate_o;
wire [31:0] AddrBuf_addrMuxOut;
wire [31:0] AddrBuf_addOut;
wire [31:0] AddrBuf_addrTristate_o;
wire [31:0] Op2Buf_op2muxOut;
wire [31:0] Op2Buf_op2tristate_o;
wire [31:0] Addr14Buf_addr14;
wire [31:0] Addr14Buf_plusminusMuxOut;
wire [31:0] Addr14Buf_addr14tristate_o;
wire [31:0] PC_pcTristate_o;
reg [31:0] PC_pc_data;
wire [31:0] ALU_BmuxOut;
reg [31:0] ALU_aluRes;
wire [31:0] ALU_aluTristate_o;
reg [3:0] RegisterBank_zMuxOut;
reg [3:0] RegisterBank_yMuxOut;
wire [31:0] RegisterBank_ryTristate_o;
wire StatusFlags_sUp;
reg [0:0] StatusFlags_V_data;
reg [0:0] StatusFlags_C_data;
reg [0:0] StatusFlags_N_data;
reg [0:0] StatusFlags_Z_data;
wire CPU_ffavail;
reg [3:0] CPU_Cpu_substate;
reg [4:0] CPU_Cpu_state;
wire [31:0] IR_ir2idecoder;
reg [31:0] IR_ir_data;
reg [31:0] RegisterBank_rb_reg_data [0:16-1];
assign bbus = RegisterBank_ryTristate_o;
assign bbus = ALU_aluTristate_o;
assign bbus = PC_pcTristate_o;
assign bbus = Addr14Buf_addr14tristate_o;
assign bbus = Op2Buf_op2tristate_o;
assign bbus = AddrBuf_addrTristate_o;
assign bbus = ClkBuf_clkTristate_o;
assign bbus = RS232_readerTristate_o;
assign bbus = IO_ioTristate_o;
assign bbus = Memory_mmuTristate_o;
function integer MYHDL31_calc;
input [4-1:0] opc;
input [32-1:0] first;
input [32-1:0] second;
input [1-1:0] c;
begin: MYHDL51_RETURN
case (opc)
'h0: begin
MYHDL31_calc = (first + second);
disable MYHDL51_RETURN;
end
'h1: begin
MYHDL31_calc = ((first + second) + c);
disable MYHDL51_RETURN;
end
'h4: begin
MYHDL31_calc = ($signed({1'b0, first}) - $signed({1'b0, second}));
disable MYHDL51_RETURN;
end
'h5: begin
MYHDL31_calc = (($signed({1'b0, first}) - $signed({1'b0, second})) - c);
disable MYHDL51_RETURN;
end
'h6: begin
MYHDL31_calc = ($signed({1'b0, second}) - $signed({1'b0, first}));
disable MYHDL51_RETURN;
end
'h7: begin
MYHDL31_calc = ((second + c) - first);
disable MYHDL51_RETURN;
end
'h2: begin
MYHDL31_calc = (first * second);
disable MYHDL51_RETURN;
end
'h3: begin
MYHDL31_calc = (first & (~second));
disable MYHDL51_RETURN;
end
'h8: begin
MYHDL31_calc = (first & second);
disable MYHDL51_RETURN;
end
'h9: begin
MYHDL31_calc = (first | second);
disable MYHDL51_RETURN;
end
'ha: begin
MYHDL31_calc = (first ^ second);
disable MYHDL51_RETURN;
end
'hb: begin
MYHDL31_calc = (first | (~second));
disable MYHDL51_RETURN;
end
'hc: begin
if ((second < 32) !== 1) begin
$display("*** AssertionError ***");
end
MYHDL31_calc = (first << second);
disable MYHDL51_RETURN;
end
'hd: begin
if ((second < 32) !== 1) begin
$display("*** AssertionError ***");
end
MYHDL31_calc = $signed($signed(first) >>> second);
disable MYHDL51_RETURN;
end
'he: begin
if ((second < 32) !== 1) begin
$display("*** AssertionError ***");
end
MYHDL31_calc = (first >>> second);
disable MYHDL51_RETURN;
end
default: begin
if ((second < 32) !== 1) begin
$display("*** AssertionError ***");
end
MYHDL31_calc = (($signed({1'b0, first}) << (32 - $signed({1'b0, second}))) | (first >>> second));
disable MYHDL51_RETURN;
end
endcase
end
endfunction
assign CPU_ffavail = (!fifoempty);
assign fifore = bufRsr;
always @(posedge clk, negedge reset) begin: PROCESSOR_CPU_CPU_LOGIC
if (reset == 0) begin
enJump <= 0;
bufAddr14 <= 0;
CPU_Cpu_substate <= 0;
enCall <= 0;
enPc <= 0;
enReg <= 0;
bufAddr <= 0;
enMmu <= 0;
bufRy <= 0;
bufBut <= 0;
bufClk <= 0;
CPU_Cpu_state <= 5'b00001;
mmuBuf <= 0;
addrymux1 <= 0;
addrymux0 <= 0;
enAlu <= 0;
bufPC <= 0;
bufOp2 <= 0;
pmux <= 0;
bufAlu <= 0;
enIr <= 0;
enRst <= 0;
enLed <= 0;
enSup <= 0;
bufRsr <= 0;
end
else begin
addrymux1 <= 1'b0;
addrymux0 <= 1'b0;
pmux <= 1'b0;
bufAddr <= 1'b0;
bufOp2 <= 1'b0;
bufAddr14 <= 1'b0;
bufRy <= 1'b0;
bufAlu <= 1'b0;
bufPC <= 1'b0;
bufClk <= 1'b0;
bufBut <= 1'b0;
bufRsr <= 1'b0;
enAlu <= 1'b0;
enIr <= 1'b0;
enPc <= 1'b0;
enReg <= 1'b0;
enSup <= 1'b0;
enJump <= 1'b0;
enCall <= 1'b0;
enLed <= 1'b0;
enRst <= 1'b0;
enMmu <= 1'b0;
mmuBuf <= 1'b0;
case (CPU_Cpu_state)
5'b00000: begin
if ((irPrefix[7-1:5] == 0)) begin
CPU_Cpu_state <= 5'b00011;
end
else if ((irPrefix[7-1:5] == 1)) begin
CPU_Cpu_state <= 5'b00100;
end
else if ((irPrefix[7-1:4] == 4)) begin
CPU_Cpu_state <= 5'b00101;
end
else if ((irPrefix[7-1:4] == 5)) begin
CPU_Cpu_state <= 5'b00110;
end
else if ((irPrefix[7-1:4] == 6)) begin
CPU_Cpu_state <= 5'b00111;
end
else if ((irPrefix[7-1:2] == 28)) begin
CPU_Cpu_state <= 5'b01000;
end
else if ((irPrefix[7-1:2] == 29)) begin
CPU_Cpu_state <= 5'b01001;
end
else if ((irPrefix[7-1:1] == 60)) begin
CPU_Cpu_state <= 5'b01010;
end
else if ((irPrefix[7-1:1] == 61)) begin
CPU_Cpu_state <= 5'b01011;
end
else if ((irPrefix[7-1:0] == 124)) begin
CPU_Cpu_state <= 5'b01101;
end
else if ((irPrefix[7-1:0] == 125)) begin
CPU_Cpu_state <= 5'b01100;
end
else if ((irPrefix[7-1:0] == 126)) begin
CPU_Cpu_state <= 5'b01110;
end
else if ((irPrefix[7-1:0] == 127)) begin
CPU_Cpu_state <= 5'b01111;
end
else begin
CPU_Cpu_state <= 5'b10001;
end
end
5'b00001: begin
if (((!readybit) && (CPU_Cpu_substate == 0))) begin
// pass
end
else begin
if ((CPU_Cpu_substate == 0)) begin
enMmu <= 1'b1;
bufPC <= 1'b1;
CPU_Cpu_substate <= (CPU_Cpu_substate + 1);
end
else if ((CPU_Cpu_substate == 1)) begin
CPU_Cpu_substate <= (CPU_Cpu_substate + 1);
end
else if ((!readybit)) begin
// pass
end
else if (readybit) begin
mmuBuf <= 1'b1;
enIr <= 1'b1;
CPU_Cpu_substate <= 0;
CPU_Cpu_state <= 5'b00010;
end
end
end
5'b00010: begin
enPc <= 1'b1;
CPU_Cpu_state <= 5'b00000;
end
5'b00011: begin
enAlu <= 1'b1;
bufAlu <= 1'b1;
enReg <= 1'b1;
enSup <= 1'b1;
CPU_Cpu_state <= 5'b00001;
end
5'b00100: begin
enJump <= 1'b1;
enPc <= 1'b1;
CPU_Cpu_state <= 5'b00001;
end
5'b00101: begin
if (((!readybit) && (CPU_Cpu_substate == 0))) begin
// pass
end
else begin
if ((CPU_Cpu_substate == 0)) begin
enMmu <= 1'b1;
bufAddr <= 1'b1;
CPU_Cpu_substate <= (CPU_Cpu_substate + 1);
end
else if ((CPU_Cpu_substate == 1)) begin
CPU_Cpu_substate <= (CPU_Cpu_substate + 1);
end
else if ((!readybit)) begin
// pass
end
else if (readybit) begin
mmuBuf <= 1'b1;
enReg <= 1'b1;
CPU_Cpu_substate <= 0;
CPU_Cpu_state <= 5'b00001;
end
end
end
5'b00110: begin
if (((!readybit) && (CPU_Cpu_substate == 0))) begin
// pass
end
else begin
case (CPU_Cpu_substate)
'h0: begin
addrymux0 <= 1'b1;
addrymux1 <= 1'b1;
bufRy <= 1'b1;
enMmu <= 1'b1;
end
'h1: begin
CPU_Cpu_substate <= 1;
bufOp2 <= 1'b1;
enMmu <= 1'b1;
CPU_Cpu_substate <= 0;
CPU_Cpu_state <= 5'b00001;
end
endcase
end
end
5'b00111: begin
enReg <= 1'b1;
bufAddr <= 1'b1;
CPU_Cpu_state <= 5'b00001;
end
5'b01000: begin
if (((!readybit) && (CPU_Cpu_substate == 0))) begin
// pass
end
else begin
case (CPU_Cpu_substate)
'h0: begin
addrymux1 <= 1'b1;
pmux <= 1'b0;
enReg <= 1'b1;
bufAddr14 <= 1'b1;
CPU_Cpu_substate <= 1;
end
'h1: begin
addrymux1 <= 1'b1;
bufRy <= 1'b1;
enMmu <= 1'b1;
CPU_Cpu_substate <= 2;
end
'h2: begin
bufOp2 <= 1'b1;
enMmu <= 1'b1;
CPU_Cpu_substate <= 0;
CPU_Cpu_state <= 5'b00001;
end
endcase
end
end
5'b01001: begin
if (((!readybit) && (CPU_Cpu_substate == 0))) begin
// pass
end
else begin
if ((CPU_Cpu_substate == 0)) begin
addrymux1 <= 1'b1;
bufRy <= 1'b1;
enMmu <= 1'b1;
CPU_Cpu_substate <= 1;
end
else if ((CPU_Cpu_substate == 1)) begin
addrymux1 <= 1'b1;
pmux <= 1'b1;
enReg <= 1'b1;
bufAddr14 <= 1'b1;
CPU_Cpu_substate <= 2;
end
else if ((!readybit)) begin
// pass
end
else if (readybit) begin
mmuBuf <= 1'b1;
addrymux1 <= 1'b1;
addrymux0 <= 1'b1;
enReg <= 1'b1;
CPU_Cpu_substate <= 0;
CPU_Cpu_state <= 5'b00001;
end
end
end
5'b01010: begin
case (CPU_Cpu_substate)
'h0: begin
bufPC <= 1'b1;
addrymux0 <= 1'b1;
enReg <= 1'b1;
CPU_Cpu_substate <= 1;
end
'h1: begin
enCall <= 1'b1;
enPc <= 1'b1;
CPU_Cpu_substate <= 0;
CPU_Cpu_state <= 5'b00001;
end
endcase
end
5'b01011: begin
bufClk <= 1'b1;
addrymux0 <= 1'b1;
addrymux1 <= 1'b1;
enReg <= 1'b1;
CPU_Cpu_state <= 5'b00001;
end
5'b01100: begin
enLed <= 1'b1;
bufOp2 <= 1'b1;
CPU_Cpu_state <= 5'b00001;
end
5'b01101: begin
addrymux0 <= 1'b1;
addrymux1 <= 1'b1;
enReg <= 1'b1;
bufBut <= 1'b1;
CPU_Cpu_state <= 5'b00001;
end
5'b01110: begin
if (CPU_ffavail) begin
bufRsr <= 1'b1;
addrymux0 <= 1'b1;
addrymux1 <= 1'b1;
enReg <= 1'b1;
CPU_Cpu_state <= 5'b00001;
end
end
5'b01111: begin
if ((CPU_Cpu_substate <= 2)) begin
enRst <= 1'b1;
bufOp2 <= 1'b1;
CPU_Cpu_substate <= (CPU_Cpu_substate + 1);
end
else if (rstreadybit) begin
CPU_Cpu_substate <= 0;
CPU_Cpu_state <= 5'b00001;
end
end
5'b10000: begin
CPU_Cpu_state <= 5'b10000;
end
default: begin
if (1'b0 !== 1) begin
$display("*** AssertionError ***");
end
end
endcase
end
end
assign Addr14Buf_plusminusMuxOut = pmux ? 4 : (-4);
assign Addr14Buf_addr14 = ($signed(Addr14Buf_plusminusMuxOut) + $signed(rgY));
assign Addr14Buf_addr14tristate_o = bufAddr14 ? Addr14Buf_addr14 : 'bz;
assign ClkBuf_clkTristate_o = bufClk ? ClkBuf_clkOut : 'bz;
always @(posedge clk, negedge reset) begin: PROCESSOR_CLKBUF_CLOCK_WRITE
if (reset == 0) begin
ClkBuf_clock_data <= 0;
end
else begin
ClkBuf_clock_data <= 1 ? (ClkBuf_clock_data + 1) : ClkBuf_clock_data;
end
end
assign ClkBuf_clkOut = ClkBuf_clock_data;
always @(posedge clk, negedge reset) begin: PROCESSOR_PC_PC_WRITE
if (reset == 0) begin
PC_pc_data <= 0;
end
else begin
if (enPc) begin
if ((!(enCall || enJump))) begin
PC_pc_data <= (PC_pc_data + 4);
end
else if ((enCall || (enJump && jumpResult))) begin
PC_pc_data <= irOp1 ? ($signed({1'b0, PC_pc_data}) + $signed(irImm24)) : rgY;
end
end
end
end
assign pcOut = PC_pc_data;
assign PC_pcTristate_o = bufPC ? pcOut : 'bz;
assign AddrBuf_addOut = ($signed(pcOut) + $signed(irImm24));
assign AddrBuf_addrMuxOut = irOp1 ? AddrBuf_addOut : rgY;
assign AddrBuf_addrTristate_o = bufAddr ? AddrBuf_addrMuxOut : 'bz;
assign RS232_readerTristate_o = bufRsr ? fifoq : 'bz;
always @(posedge clk, negedge reset) begin: PROCESSOR_RS232_READER_LOGIC
if (reset == 0) begin
fifowe <= 0;
fifodata <= 0;
RS232_reader_bitCnt <= 0;
RS232_reader_state <= 1'b0;
RS232_reader_clkCnt <= 0;
RS232_reader_data <= 0;
end
else begin
if ((RS232_reader_clkCnt > 0)) begin
RS232_reader_clkCnt <= (RS232_reader_clkCnt - 1);
end
else begin
case (RS232_reader_state)
1'b0: begin
if ((!rx)) begin
RS232_reader_data <= 0;
RS232_reader_bitCnt <= 8;
RS232_reader_clkCnt <= 1301;
fifowe <= 1'b0;
RS232_reader_state <= 1'b1;
end
end
1'b1: begin
RS232_reader_clkCnt <= 867;
if ((RS232_reader_bitCnt > 0)) begin
RS232_reader_data <= ($signed({1'b0, RS232_reader_data}) | ($signed({1'b0, rx}) << (8 - $signed({1'b0, RS232_reader_bitCnt}))));
RS232_reader_bitCnt <= (RS232_reader_bitCnt - 1);
end
else begin
fifodata <= RS232_reader_data;
fifowe <= 1'b1;
RS232_reader_state <= 1'b0;
end
end
endcase
end
end
end
always @(posedge clk, negedge reset) begin: PROCESSOR_RS232_WRITER_LOGIC
if (reset == 0) begin
tx <= 1;
RS232_writer_bitCnt <= 0;
RS232_writer_state <= 1'b0;
RS232_writer_clkCnt <= 0;
RS232_writer_data <= 0;
rstreadybit <= 1;
end
else begin
if ((RS232_writer_clkCnt > 0)) begin
RS232_writer_clkCnt <= (RS232_writer_clkCnt - 1);
end
else begin
tx <= 1'b1;
case (RS232_writer_state)
1'b0: begin
if (enRst) begin
RS232_writer_data <= bbus[8-1:0];
RS232_writer_clkCnt <= 867;
rstreadybit <= 1'b0;
RS232_writer_bitCnt <= 8;
tx <= 1'b0;
RS232_writer_state <= 1'b1;
end
else begin
rstreadybit <= 1'b1;
end
end
1'b1: begin
if ((RS232_writer_bitCnt > 0)) begin
tx <= RS232_writer_data[(8 - $signed({1'b0, RS232_writer_bitCnt}))];
RS232_writer_bitCnt <= (RS232_writer_bitCnt - 1);
RS232_writer_clkCnt <= 867;
end
else begin
tx <= 1'b1;
RS232_writer_clkCnt <= 1301;
RS232_writer_state <= 1'b0;
end
end
endcase
end
end
end
always @(vOut, zOut, irJumpOp, cOut, nOut) begin: PROCESSOR_JUMPUNIT_JU_LOGIC
reg result;
result = 1'b0;
if (irJumpOp[4]) begin
result = (result || (zOut != 0));
end
if (irJumpOp[3]) begin
result = (result || (nOut != 0));
end
if (irJumpOp[2]) begin
result = (result || (cOut != 0));
end
if (irJumpOp[1]) begin
result = (result || (vOut != 0));
end
if (irJumpOp[0]) begin
result = (!result);
end
jumpResult = result;
end
assign StatusFlags_sUp = (irSup & enSup);
always @(posedge clk, negedge reset) begin: PROCESSOR_STATUSFLAGS_Z_WRITE
if (reset == 0) begin
StatusFlags_Z_data <= 0;
end
else begin
if (StatusFlags_sUp) begin
StatusFlags_Z_data <= zIn;
end
end
end
assign zOut = StatusFlags_Z_data;
always @(posedge clk, negedge reset) begin: PROCESSOR_STATUSFLAGS_N_WRITE
if (reset == 0) begin
StatusFlags_N_data <= 0;
end
else begin
if (StatusFlags_sUp) begin
StatusFlags_N_data <= nIn;
end
end
end
assign nOut = StatusFlags_N_data;
always @(posedge clk, negedge reset) begin: PROCESSOR_STATUSFLAGS_C_WRITE
if (reset == 0) begin
StatusFlags_C_data <= 0;
end
else begin
if (StatusFlags_sUp) begin
StatusFlags_C_data <= cIn;
end
end
end
assign cOut = StatusFlags_C_data;
always @(posedge clk, negedge reset) begin: PROCESSOR_STATUSFLAGS_V_WRITE
if (reset == 0) begin
StatusFlags_V_data <= 0;
end
else begin
if (StatusFlags_sUp) begin
StatusFlags_V_data <= vIn;
end
end
end
assign vOut = StatusFlags_V_data;
assign ALU_BmuxOut = irOp2 ? irImm16 : rgY;
always @(rgX, ALU_BmuxOut, enAlu, cOut, irAluop) begin: PROCESSOR_ALU_ALU_LOGIC
reg [32-1:0] alu_res;
integer result;
zIn = 1'b0;
nIn = 1'b0;
cIn = 1'b0;
vIn = 1'b0;
ALU_aluRes = 0;
if (enAlu) begin
result = MYHDL31_calc(irAluop, rgX, ALU_BmuxOut, cOut);
alu_res = result[32-1:0];
zIn = (alu_res == 0);
nIn = alu_res[(32 - 1)];
cIn = ((result & 34'h100000000) != 0);
vIn = ((rgX[(32 - 1)] == ALU_BmuxOut[(32 - 1)]) && (rgX[(32 - 1)] == (!alu_res[(32 - 1)])));
ALU_aluRes = alu_res;
end
end
assign ALU_aluTristate_o = bufAlu ? ALU_aluRes : 'bz;
assign romrden = (Memory_enO & Memory_csO);
assign ramrden = (Memory_enO & Memory_csA);
assign ramwren = (Memory_enW & Memory_csA);
always @(posedge clk, negedge reset) begin: PROCESSOR_MEMORY_MMU_WRITE
if (reset == 0) begin
memoryaddr <= 0;
Memory_enW <= 0;
Memory_enO <= 0;
Memory_Mmu_waitingtimer <= 0;
Memory_Mmu_state <= 2'b00;
memoryout <= 0;
Memory_csA <= 0;
readybit <= 1;
Memory_csO <= 0;
Memory_Mmu_with_data <= 0;
Memory_Mmu_in_data <= 0;
end
else begin
if (enMmu) begin
case (Memory_Mmu_state)
2'b00: begin
readybit <= 1'b0;
memoryaddr <= bbus[16-1:0];
Memory_csA <= bbus[31];
Memory_csO <= (!bbus[31]);
Memory_Mmu_state <= 2'b01;
end
2'b01: begin
if ((Memory_csA != 0) !== 1) begin
$display("*** AssertionError ***");
end
Memory_csA <= 1'b1;
Memory_csO <= 1'b0;
Memory_Mmu_with_data <= 1'b1;
Memory_Mmu_in_data <= bbus;
end
default: begin
$write("Something went wrong! (Did you read the protocoll?)");
$write("\n");
end
endcase
end
else if ((Memory_Mmu_state == 2'b01)) begin
if ((!(Memory_enO && Memory_enW)) !== 1) begin
$display("*** AssertionError ***");
end
if ((!Memory_Mmu_with_data)) begin
Memory_enO <= 1'b1;
if ((Memory_Mmu_waitingtimer == 2)) begin
Memory_Mmu_in_data <= memoryin;
Memory_Mmu_state <= 2'b10;
end
end
else begin
Memory_enW <= 1'b1;
memoryout <= Memory_Mmu_in_data;
if ((Memory_Mmu_waitingtimer == 2)) begin
Memory_Mmu_state <= 2'b10;
end
end
Memory_Mmu_waitingtimer <= (Memory_Mmu_waitingtimer + 1);
end
else if ((Memory_Mmu_state == 2'b10)) begin
Memory_Mmu_waitingtimer <= 0;
Memory_Mmu_with_data <= 1'b0;
Memory_enO <= 1'b0;
Memory_enW <= 1'b0;
readybit <= 1'b1;
Memory_Mmu_state <= 2'b00;
end
end
end
always @(posedge readybit) begin: PROCESSOR_MEMORY_MMU_READ
Memory_mmuOut <= Memory_Mmu_in_data;
end
assign Memory_mmuTristate_o = mmuBuf ? Memory_mmuOut : 'bz;
always @(posedge clk, negedge reset) begin: PROCESSOR_IR_IR_WRITE
if (reset == 0) begin
IR_ir_data <= 0;
end
else begin
if (enIr) begin
IR_ir_data <= bbus;
end
end
end
assign IR_ir2idecoder = IR_ir_data;
assign irAluop = IR_ir2idecoder[25-1:21];
assign irDest = IR_ir2idecoder[29-1:25];
assign irSource = IR_ir2idecoder[21-1:17];
assign irOp1 = IR_ir2idecoder[24];
assign irOp2 = IR_ir2idecoder[16];
assign irSource2 = IR_ir2idecoder[4-1:0];
assign irImm24 = IR_ir2idecoder[24-1:0];
assign irImm16 = IR_ir2idecoder[16-1:0];
assign irSup = IR_ir2idecoder[29];
assign irPrefix = IR_ir2idecoder[32-1:25];
assign irJumpOp = IR_ir2idecoder[30-1:25];
always @(posedge clk, negedge reset) begin: PROCESSOR_IO_IO_LOGIC
if (reset == 0) begin
IO_io_ledBuffer <= 0;
leds <= 15;
IO_ioOut <= 0;
end
else begin
if (enLed) begin
IO_io_ledBuffer <= bbus[4-1:0];
end
IO_ioOut <= (~buttons);
leds <= (~IO_io_ledBuffer);
end
end
assign IO_ioTristate_o = bufBut ? IO_ioOut : 'bz;
always @(addrymux1, addrymux0, irDest, irSource2) begin: PROCESSOR_REGISTERBANK_YMUX_LOGIC
if ((!addrymux1)) begin
if ((!addrymux0)) begin
RegisterBank_yMuxOut = irSource2;
end
else begin
RegisterBank_yMuxOut = 15;
end
end
else begin
if ((!addrymux0)) begin
RegisterBank_yMuxOut = 14;
end
else begin
RegisterBank_yMuxOut = irDest;
end
end
end
always @(addrymux1, addrymux0, irSource2, irDest) begin: PROCESSOR_REGISTERBANK_ZMUX_LOGIC
if ((!addrymux1)) begin
if ((!addrymux0)) begin
RegisterBank_zMuxOut = irDest;
end
else begin
RegisterBank_zMuxOut = 15;
end
end
else begin
if ((!addrymux0)) begin
RegisterBank_zMuxOut = 14;
end
else begin
RegisterBank_zMuxOut = irSource2;
end
end
end
always @(posedge clk, negedge reset) begin: PROCESSOR_REGISTERBANK_RB_WRITE
if (reset == 0) begin
RegisterBank_rb_reg_data[0] <= 0;
RegisterBank_rb_reg_data[1] <= 0;
RegisterBank_rb_reg_data[2] <= 0;
RegisterBank_rb_reg_data[3] <= 0;
RegisterBank_rb_reg_data[4] <= 0;
RegisterBank_rb_reg_data[5] <= 0;
RegisterBank_rb_reg_data[6] <= 0;
RegisterBank_rb_reg_data[7] <= 0;
RegisterBank_rb_reg_data[8] <= 0;
RegisterBank_rb_reg_data[9] <= 0;
RegisterBank_rb_reg_data[10] <= 0;
RegisterBank_rb_reg_data[11] <= 0;
RegisterBank_rb_reg_data[12] <= 0;
RegisterBank_rb_reg_data[13] <= 0;
RegisterBank_rb_reg_data[14] <= 0;
RegisterBank_rb_reg_data[15] <= 0;
end
else begin
if ((irSource < 16) !== 1) begin
$display("*** AssertionError ***");
end
if ((RegisterBank_yMuxOut < 16) !== 1) begin
$display("*** AssertionError ***");
end
if ((RegisterBank_zMuxOut < 16) !== 1) begin
$display("*** AssertionError ***");
end
if ((enReg && (!(1 && (RegisterBank_zMuxOut == 0))))) begin
RegisterBank_rb_reg_data[RegisterBank_zMuxOut] <= bbus[32-1:0];
end
end
end
always @(RegisterBank_rb_reg_data[0], RegisterBank_rb_reg_data[1], RegisterBank_rb_reg_data[2], RegisterBank_rb_reg_data[3], RegisterBank_rb_reg_data[4], RegisterBank_rb_reg_data[5], RegisterBank_rb_reg_data[6], RegisterBank_rb_reg_data[7], RegisterBank_rb_reg_data[8], RegisterBank_rb_reg_data[9], RegisterBank_rb_reg_data[10], RegisterBank_rb_reg_data[11], RegisterBank_rb_reg_data[12], RegisterBank_rb_reg_data[13], RegisterBank_rb_reg_data[14], RegisterBank_rb_reg_data[15], irSource, RegisterBank_yMuxOut) begin: PROCESSOR_REGISTERBANK_RB_READ
if ((irSource < 16) !== 1) begin
$display("*** AssertionError ***");
end
if ((RegisterBank_yMuxOut < 16) !== 1) begin
$display("*** AssertionError ***");
end
if ((RegisterBank_yMuxOut < 16) !== 1) begin
$display("*** AssertionError ***");
end
rgX = RegisterBank_rb_reg_data[irSource];
rgY = RegisterBank_rb_reg_data[RegisterBank_yMuxOut];
end
assign RegisterBank_ryTristate_o = bufRy ? rgY : 'bz;
assign Op2Buf_op2muxOut = irOp1 ? irImm24 : rgY;
assign Op2Buf_op2tristate_o = bufOp2 ? Op2Buf_op2muxOut : 'bz;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_rx.v
// Version : 1.8
//--
//--------------------------------------------------------------------------------
`include "board_common.v"
`define EXPECT_FINISH_CHECK board.RP.tx_usrapp.expect_finish_check
module pci_exp_usrapp_rx #(
parameter C_DATA_WIDTH = 64,
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1
)
(
trn_rdst_rdy_n,
trn_rnp_ok_n,
trn_rd,
trn_rrem_n,
trn_rsof_n,
trn_reof_n,
trn_rsrc_rdy_n,
trn_rsrc_dsc_n,
trn_rerrfwd_n,
trn_rbar_hit_n,
trn_clk,
trn_reset_n,
trn_lnk_up_n
);
output trn_rdst_rdy_n;
output trn_rnp_ok_n;
input [C_DATA_WIDTH-1:0] trn_rd;
input [REM_WIDTH-1:0] trn_rrem_n;
input trn_rsof_n;
input trn_reof_n;
input trn_rsrc_rdy_n;
input trn_rsrc_dsc_n;
input trn_rerrfwd_n;
input [6 : 0] trn_rbar_hit_n;
input trn_clk;
input trn_reset_n;
input trn_lnk_up_n;
parameter Tcq = 1;
/* Output variables */
reg trn_rdst_rdy_n, next_trn_rdst_rdy_n;
reg trn_rnp_ok_n, next_trn_rnp_ok_n;
/* Local variables */
reg [4:0] trn_rx_state, next_trn_rx_state;
reg trn_rx_in_frame, next_trn_rx_in_frame;
reg trn_rx_in_channel, next_trn_rx_in_channel;
reg [31:0] next_trn_rx_timeout;
/* State variables */
`define TRN_RX_RESET 5'b00001
`define TRN_RX_DOWN 5'b00010
`define TRN_RX_IDLE 5'b00100
`define TRN_RX_ACTIVE 5'b01000
`define TRN_RX_SRC_DSC 5'b10000
/* Transaction Receive User Interface State Machine */
generate
if (C_DATA_WIDTH == 64) begin : trn_rx_sm_64
always @(posedge trn_clk or negedge trn_reset_n) begin
if (trn_reset_n == 1'b0) begin
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
end else begin
case (trn_rx_state)
`TRN_RX_RESET : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
end
`TRN_RX_DOWN : begin
if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else begin
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end
end
`TRN_RX_IDLE : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else begin
if ( (trn_rsof_n == 1'b0) &&
(trn_rsrc_rdy_n == 1'b0) &&
(trn_rdst_rdy_n == 1'b0) ) begin
board.RP.com_usrapp.TSK_READ_DATA(0, `RX_LOG, trn_rd, trn_rrem_n);
trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
end else begin
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end
end
end
`TRN_RX_ACTIVE : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else if ( (trn_rsrc_rdy_n == 1'b0) &&
(trn_reof_n == 1'b0) &&
(trn_rdst_rdy_n == 1'b0) ) begin
board.RP.com_usrapp.TSK_READ_DATA(1, `RX_LOG, trn_rd, trn_rrem_n);
board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end else if ( (trn_rsrc_rdy_n == 1'b0) &&
(trn_rdst_rdy_n == 1'b0) ) begin
board.RP.com_usrapp.TSK_READ_DATA(0, `RX_LOG, trn_rd, trn_rrem_n);
trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
end else if ( (trn_rsrc_rdy_n == 1'b0) &&
(trn_reof_n == 1'b0) &&
(trn_rsrc_dsc_n == 1'b0) ) begin
board.RP.com_usrapp.TSK_READ_DATA(1, `RX_LOG, trn_rd, trn_rrem_n);
board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
trn_rx_state <= #(Tcq) `TRN_RX_SRC_DSC;
end else begin
trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
end
end
`TRN_RX_SRC_DSC : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else begin
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end
end
endcase
end
end
end
else if (C_DATA_WIDTH == 128) begin : trn_rx_sm_128
always @(posedge trn_clk or negedge trn_reset_n) begin
if (trn_reset_n == 1'b0) begin
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
end else begin
case (trn_rx_state)
`TRN_RX_RESET : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
end
`TRN_RX_DOWN : begin
if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else begin
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end
end
`TRN_RX_IDLE : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else begin
// single TLP in a Data Beat Case
if ( (trn_rsof_n == 1'b0) &&
(trn_rsrc_rdy_n == 1'b0) &&
(trn_rdst_rdy_n == 1'b0) ) begin
board.RP.com_usrapp.TSK_READ_DATA_128(~trn_rsof_n, ~trn_reof_n, `RX_LOG, trn_rd, trn_rrem_n);
if ( (trn_rsof_n == 1'b0) && (trn_reof_n == 1'b0)) begin
board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end else begin
trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
end
end else begin
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end
end
end
`TRN_RX_ACTIVE : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else if ( (trn_rsrc_rdy_n == 1'b0) &&
(trn_rdst_rdy_n == 1'b0) ) begin
case ({trn_rsof_n, trn_reof_n})
// Data Stream - both sof & eof de-asserted
2'b11 : begin
board.RP.com_usrapp.TSK_READ_DATA_128(0, 0, `RX_LOG, trn_rd, trn_rrem_n);
trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
end
// EOF scenario. Not a straddle case
2'b10 : begin
board.RP.com_usrapp.TSK_READ_DATA_128(0, 1, `RX_LOG, trn_rd, trn_rrem_n);
board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end
2'b00 : begin
board.RP.com_usrapp.TSK_READ_DATA_128(0, 1, `RX_LOG, trn_rd, trn_rrem_n);
board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
board.RP.com_usrapp.TSK_READ_DATA_128(1, 0, `RX_LOG, trn_rd, trn_rrem_n);
trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
end
//2'b01 is not a valid option as the TRN_RX_ACTIVE case is only entered when we have seen an SOF but not an EOF, in the TRN_RX_IDLE state
endcase
end else if ( (trn_rsrc_rdy_n == 1'b0) &&
(trn_reof_n == 1'b0) &&
(trn_rsrc_dsc_n == 1'b0) ) begin
board.RP.com_usrapp.TSK_READ_DATA_128(0, 1, `RX_LOG, trn_rd, trn_rrem_n);
board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
trn_rx_state <= #(Tcq) `TRN_RX_SRC_DSC;
end else begin
trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
end
end
`TRN_RX_SRC_DSC : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else begin
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end
end
endcase
end
end
end
endgenerate
reg [1:0] trn_rdst_rdy_toggle_count;
reg [8:0] trn_rnp_ok_toggle_count;
always @(posedge trn_clk or negedge trn_reset_n) begin
if (trn_reset_n == 1'b0) begin
trn_rnp_ok_n <= #(Tcq) 1'b0;
trn_rdst_rdy_n <= #(Tcq) 1'b0;
trn_rdst_rdy_toggle_count <= #(Tcq) $random;
trn_rnp_ok_toggle_count <= #(Tcq) $random;
end else begin
if (trn_rnp_ok_toggle_count == 0) begin
trn_rnp_ok_n <= #(Tcq) !trn_rnp_ok_n;
trn_rnp_ok_toggle_count <= #(Tcq) $random;
end else begin
//trn_rnp_ok_toggle_count <= #(Tcq) trn_rnp_ok_toggle_count - 1;
end
if (trn_rdst_rdy_toggle_count == 0) begin
//trn_rdst_rdy_n <= #(Tcq) !trn_rdst_rdy_n;
trn_rdst_rdy_toggle_count <= #(Tcq) $random;
end else begin
//trn_rdst_rdy_toggle_count <= trn_rdst_rdy_toggle_count - 1;
end
end
end
reg [31:0] sim_timeout;
initial
begin
sim_timeout = `TRN_RX_TIMEOUT;
end
/* Transaction Receive Timeout */
always @(trn_clk or trn_rsof_n or trn_rsrc_rdy_n) begin
if (next_trn_rx_timeout == 0) begin
if(!`EXPECT_FINISH_CHECK)
$display("[%t] : TEST FAILED --- Haven't Received All Expected TLPs", $realtime);
$finish(2);
end
if ((trn_rsof_n == 1'b0) && (trn_rsrc_rdy_n == 1'b0)) begin
next_trn_rx_timeout = sim_timeout;
end else begin
if (trn_lnk_up_n == 1'b0)
next_trn_rx_timeout = next_trn_rx_timeout - 1'b1;
end
end
endmodule // pci_exp_usrapp_rx
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9643 (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// delay interface
delay_clk,
// dma interface
adc_clk,
adc_valid_0,
adc_enable_0,
adc_data_0,
adc_valid_1,
adc_enable_1,
adc_data_1,
adc_dovf,
adc_dunf,
up_adc_gpio_in,
up_adc_gpio_out,
adc_rst,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay interface
input delay_clk;
// dma interface
output adc_clk;
output adc_valid_0;
output adc_enable_0;
output [15:0] adc_data_0;
output adc_valid_1;
output adc_enable_1;
output [15:0] adc_data_1;
input adc_dovf;
input adc_dunf;
input [31:0] up_adc_gpio_in;
output [31:0] up_adc_gpio_out;
output adc_rst;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
wire delay_rst;
// internal signals
wire [13:0] adc_data_a_s;
wire [13:0] adc_data_b_s;
wire adc_or_a_s;
wire adc_or_b_s;
wire [15:0] adc_dcfilter_data_a_s;
wire [15:0] adc_dcfilter_data_b_s;
wire [15:0] adc_channel_data_a_s;
wire [15:0] adc_channel_data_b_s;
wire [ 1:0] up_status_pn_err_s;
wire [ 1:0] up_status_pn_oos_s;
wire [ 1:0] up_status_or_s;
wire adc_ddr_edgesel_s;
wire adc_pin_mode_s;
wire adc_status_s;
wire [14:0] up_dld_s;
wire [74:0] up_dwdata_s;
wire [74:0] up_drdata_s;
wire delay_locked_s;
wire [31:0] up_rdata_s[0:3];
wire up_rack_s[0:3];
wire up_wack_s[0:3];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// dma interface
assign adc_valid_0 = 1'b1;
assign adc_valid_1 = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= up_status_pn_err_s[0] | up_status_pn_err_s[1];
up_status_pn_oos <= up_status_pn_oos_s[0] | up_status_pn_oos_s[1];
up_status_or <= up_status_or_s[0] | up_status_or_s[1];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3];
end
end
// channel
axi_ad9643_channel #(
.IQSEL(0),
.CHID(0),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
.adc_or (adc_or_a_s),
.adc_dcfilter_data_out (adc_dcfilter_data_a_s),
.adc_dcfilter_data_in (adc_dcfilter_data_b_s),
.adc_iqcor_data (adc_data_0),
.adc_enable (adc_enable_0),
.up_adc_pn_err (up_status_pn_err_s[0]),
.up_adc_pn_oos (up_status_pn_oos_s[0]),
.up_adc_or (up_status_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// channel
axi_ad9643_channel #(
.IQSEL(1),
.CHID(1),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
.adc_or (adc_or_b_s),
.adc_dcfilter_data_out (adc_dcfilter_data_b_s),
.adc_dcfilter_data_in (adc_dcfilter_data_a_s),
.adc_iqcor_data (adc_data_1),
.adc_enable (adc_enable_1),
.up_adc_pn_err (up_status_pn_err_s[1]),
.up_adc_pn_oos (up_status_pn_oos_s[1]),
.up_adc_or (up_status_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// main (device interface)
axi_ad9643_if #(
.PCORE_BUFTYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_clk (adc_clk),
.adc_data_a (adc_data_a_s),
.adc_data_b (adc_data_b_s),
.adc_or_a (adc_or_a_s),
.adc_or_b (adc_or_b_s),
.adc_status (adc_status_s),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (adc_pin_mode_s),
.up_clk (up_clk),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (adc_pin_mode_s),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (up_adc_gpio_in),
.up_adc_gpio_out (up_adc_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// adc delay control
up_delay_cntrl #(.IO_WIDTH(15), .IO_BASEADDR(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// MBT 11/9/2014
//
// Synchronous 1-port ram.
// Only one read or one write may be done per cycle.
`define bsg_mem_1rw_sync_macro_bit(words,bits,lgEls,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc40_1rw_lg``lgEls``_w``bits``_m``mux mem \
(.A ( addr_i ) \
,.D ( data_i ) \
,.BWEB ( ~w_mask_i ) \
,.WEB ( ~w_i ) \
,.CEB ( ~v_i ) \
,.CLK ( clk_i ) \
,.Q ( data_o ) \
,.DELAY ( 2'b0 ) \
,.TEST ( 2'b0 )); \
end
`define bsg_mem_1rf_sync_macro_bit(words,bits,lgEls,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc40_1rf_lg``lgEls``_w``bits``_m``mux mem \
(.A ( addr_i ) \
,.D ( data_i ) \
,.BWEB ( ~w_mask_i ) \
,.WEB ( ~w_i ) \
,.CEB ( ~v_i ) \
,.CLK ( clk_i ) \
,.Q ( data_o ) \
,.DELAY ( 2'b0 )); \
end
module bsg_mem_1rw_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p))
(input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input [addr_width_lp-1:0] addr_i
, input v_i
, input [width_p-1:0] w_mask_i
, input w_i
, output [width_p-1:0] data_o
);
wire unused = reset_i;
// we use a 2 port RF because the 1 port RF
// does not support bit-level masking for 80-bit width
// alternatively we could instantiate 2 40-bit 1rw RF's
`bsg_mem_1rf_sync_macro_bit(256,4,8,4) else
`bsg_mem_1rf_sync_macro_bit(256,30,8,2) else
`bsg_mem_1rf_sync_macro_bit(256,32,8,2) else
`bsg_mem_1rf_sync_macro_bit(256,34,8,2) else
`bsg_mem_1rf_sync_macro_bit(256,36,8,2) else
`bsg_mem_1rw_sync_macro_bit(64,80,6,1) else
bsg_mem_1rw_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p(els_p)
) synth
(.*);
// synopsys translate_off
always_ff @(posedge clk_i)
if (v_i)
assert (addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", addr_i, els_p);
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit)
|
// Implements I2C from the Zynq PS
module parallella_i2c
(/*AUTOARG*/
// Outputs
I2C_SDA_I, I2C_SCL_I,
// Inouts
I2C_SDA, I2C_SCL,
// Inputs
I2C_SDA_O, I2C_SDA_T, I2C_SCL_O, I2C_SCL_T
);
input I2C_SDA_O;
input I2C_SDA_T;
output I2C_SDA_I;
input I2C_SCL_O;
input I2C_SCL_T;
output I2C_SCL_I;
inout I2C_SDA;
inout I2C_SCL;
`ifdef PORTABLE
wire I2C_SDA = I2C_SDA_T ? 1'bZ : I2C_SDA_O;
wire I2C_SDA_I = I2C_SDA;
wire I2C_SCL = I2C_SCL_T ? 1'bZ : I2C_SCL_O;
wire I2C_SCL_I = I2C_SCL;
`else
IOBUF #(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_sda (
.O(I2C_SDA_I), // Buffer output
.IO(I2C_SDA), // Buffer inout port (connect directly to top-level port)
.I(I2C_SDA_O), // Buffer input
.T(I2C_SDA_T) // 3-state enable input, high=input, low=output
);
IOBUF #(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_inst (
.O(I2C_SCL_I), // Buffer output
.IO(I2C_SCL), // Buffer inout port (connect directly to top-level port)
.I(I2C_SCL_O), // Buffer input
.T(I2C_SCL_T) // 3-state enable input, high=input, low=output
);
`endif
endmodule // parallella_i2c
/*
File: parallella_i2c
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013-2015 Adapteva, Inc.
Contributed by Fred Huettig
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 11:16:06 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/dds/dds_stub.v
// Design : dds
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0,Vivado 2014.1" *)
module dds(aclk, s_axis_phase_tvalid, s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata, m_axis_phase_tvalid, m_axis_phase_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[39:0],m_axis_data_tvalid,m_axis_data_tdata[31:0],m_axis_phase_tvalid,m_axis_phase_tdata[39:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [39:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [31:0]m_axis_data_tdata;
output m_axis_phase_tvalid;
output [39:0]m_axis_phase_tdata;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Yermy Benavides Solano
//
// Create Date: 22:59:01 05/16/2016
// Design Name:
// Module Name: signal_control_rtc_generator
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module signal_control_rtc_generator(
input wire clk,
input wire reset,
input wire in_escribir_leer,
input wire en_funcion,
output reg reg_a_d, //Senales de control RTC
output reg reg_cs,
output reg reg_wr,
output reg reg_rd,
output reg out_direccion_dato,
output wire flag_done
);
/////parametros de estado
localparam
espera = 1'b1,
leer_escribir = 1'b0;
// Bits del contador para generar una señal periódica de (2^N)*10ns
localparam N = 5;
// Declaración de señales
reg [N-1:0] q_reg;
reg [N-1:0] q_next;
reg state_reg, state_next;
reg reset_count;
//Descripción del comportamiento
//=============================================
// Contador para generar un pulso de(2^N)*10ns
//=============================================
always @(posedge clk, posedge reset_count)
begin
if (reset_count) q_reg <= 0;
else q_reg <= q_next;
end
always@*
begin
q_next <= q_reg + 1'b1;
end
// Pulso de salida
assign flag_done = (q_reg == 23) ? 1'b1 : 1'b0;//Tbandera fin de proseso
///logica secuencial
always @(posedge clk, posedge reset)
begin
if (reset)
state_reg <= espera;
else
state_reg <= state_next;
end
// Lógica de estado siguiente y salida
always@*
begin
state_next = state_reg; // default state: the same
case(state_reg)
espera:
begin
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
reset_count = 1'b1;
if(en_funcion) state_next = leer_escribir;
else state_next = espera;
end
leer_escribir:
begin
reset_count = 1'b0;
//Proseso de lectura_escritura
case(q_reg)
5'd0: begin //inicia
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_rd = 1'b1;
reg_wr = 1'b1;
out_direccion_dato = 1'b0;
end
5'd1: begin // baja salida a_d
reg_a_d = 1'b0;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd2: begin// baja cs con wr o rd incio de manipulacion del bis de datos
reg_a_d = 1'b0;
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd3: begin
reg_a_d = 1'b0;
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd4: begin
reg_a_d = 1'b0;
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd5: begin
reg_a_d = 1'b0;
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd6: begin
reg_a_d = 1'b0;
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd7: begin
reg_a_d = 1'b0;
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd8: begin
reg_a_d = 1'b0;
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd9:begin
reg_a_d = 1'b0;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd10: begin
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd11: begin
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd12: begin
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd13: begin
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd14: begin
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd15: begin
reg_a_d = 1'b1;
out_direccion_dato = 1'b1;
if (in_escribir_leer)begin
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
end
else begin
reg_cs = 1'b0;
reg_wr = 1'b1;
reg_rd = 1'b0;
end
end
5'd16:begin
reg_a_d = 1'b1;
out_direccion_dato = 1'b1;
if (in_escribir_leer)begin
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
end
else begin
reg_cs = 1'b0;
reg_wr = 1'b1;
reg_rd = 1'b0;
end
end
5'd17:begin
reg_a_d = 1'b1;
out_direccion_dato = 1'b1;
if (in_escribir_leer)begin
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
end
else begin
reg_cs = 1'b0;
reg_wr = 1'b1;
reg_rd = 1'b0;
end
end
5'd18:begin
reg_a_d = 1'b1;
out_direccion_dato = 1'b1;
if (in_escribir_leer)begin
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
end
else begin
reg_cs = 1'b0;
reg_wr = 1'b1;
reg_rd = 1'b0;
end
end
5'd19: begin
reg_a_d = 1'b1;
out_direccion_dato = 1'b1;
if (in_escribir_leer)begin
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
end
else begin
reg_cs = 1'b0;
reg_wr = 1'b1;
reg_rd = 1'b0;
end
end
5'd20: begin
reg_a_d = 1'b1;
out_direccion_dato = 1'b1;
if (in_escribir_leer)begin
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
end
else begin
reg_cs = 1'b0;
reg_wr = 1'b1;
reg_rd = 1'b0;
end
end
5'd21: begin
reg_a_d = 1'b1;
out_direccion_dato = 1'b1;
if (in_escribir_leer)begin
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
end
else begin
reg_cs = 1'b0;
reg_wr = 1'b1;
reg_rd = 1'b0;
end end
5'd22: begin reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b1;
end
5'd23:
begin reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
state_next = espera;
end
default: begin
state_next = leer_escribir;
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_rd = 1'b1;
reg_wr = 1'b1;
out_direccion_dato = 1'b0;
end
endcase
end
default: begin
state_next = espera;
reg_cs = 1'd1;
reg_a_d = 1'd1;
reg_wr = 1'd1;
reg_rd = 1'd1;
out_direccion_dato = 1'd0;
end
endcase
end
endmodule
|
// hub_mem
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module hub_mem
(
input clk_cog,
input ena_bus,
input w,
input [3:0] wb,
input [13:0] a,
input [31:0] d,
output [31:0] q
);
// 8192 x 32 ram with byte-write enables ($0000..$7FFF)
reg [7:0] ram3 [8191:0];
reg [7:0] ram2 [8191:0];
reg [7:0] ram1 [8191:0];
reg [7:0] ram0 [8191:0];
reg [7:0] ram_q3;
reg [7:0] ram_q2;
reg [7:0] ram_q1;
reg [7:0] ram_q0;
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[3])
ram3[a[12:0]] <= d[31:24];
if (ena_bus && !a[13])
ram_q3 <= ram3[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[2])
ram2[a[12:0]] <= d[23:16];
if (ena_bus && !a[13])
ram_q2 <= ram2[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[1])
ram1[a[12:0]] <= d[15:8];
if (ena_bus && !a[13])
ram_q1 <= ram1[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[0])
ram0[a[12:0]] <= d[7:0];
if (ena_bus && !a[13])
ram_q0 <= ram0[a[12:0]];
end
// 4096 x 32 rom containing character definitions ($8000..$BFFF)
(* ram_init_file = "hub_rom_low.hex" *) reg [31:0] rom_low [4095:0];
reg [31:0] rom_low_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b10)
rom_low_q <= rom_low[a[11:0]];
// 4096 x 32 rom containing sin table, log table, booter, and interpreter ($C000..$FFFF)
(* ram_init_file = "hub_rom_high.hex" *) reg [31:0] rom_high [4095:0];
reg [31:0] rom_high_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b11)
rom_high_q <= rom_high[a[11:0]];
// memory output mux
reg [1:0] mem;
always @(posedge clk_cog)
if (ena_bus)
mem <= a[13:12];
assign q = !mem[1] ? {ram_q3, ram_q2, ram_q1, ram_q0}
// : !mem[0] ? rom_low_q // comment out this line for DE0-Nano (sacrifices character rom to fit device)
: rom_high_q;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__AND2_FUNCTIONAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFSTP_SYMBOL_V
`define SKY130_FD_SC_LP__SRSDFSTP_SYMBOL_V
/**
* srsdfstp: Scan flop with sleep mode, inverted set, non-inverted
* clock, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srsdfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFSTP_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iobdg_1r1w_rf32.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg_1r1w_rf32
// Description: 1r1w regfile emulated using FF's.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module iobdg_1r1w_rf32 (/*AUTOARG*/
// Outputs
dout,
// Inputs
rd_clk, wr_clk, rd_a, wr_a, din, wen_l
);
parameter REG_WIDTH = 64;
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
input rd_clk;
input wr_clk;
input [4:0] rd_a;
input [4:0] wr_a;
input [REG_WIDTH-1:0] din;
input wen_l;
output [REG_WIDTH-1:0] dout;
wire [4:0] wr_a_d1;
wire [REG_WIDTH-1:0] din_d1;
wire wen_l_d1;
wire [31:0] wr_a_dec_d1;
wire [31:0] wen_dec_d1;
wire [REG_WIDTH-1:0] line0;
wire [REG_WIDTH-1:0] line1;
wire [REG_WIDTH-1:0] line2;
wire [REG_WIDTH-1:0] line3;
wire [REG_WIDTH-1:0] line4;
wire [REG_WIDTH-1:0] line5;
wire [REG_WIDTH-1:0] line6;
wire [REG_WIDTH-1:0] line7;
wire [REG_WIDTH-1:0] line8;
wire [REG_WIDTH-1:0] line9;
wire [REG_WIDTH-1:0] line10;
wire [REG_WIDTH-1:0] line11;
wire [REG_WIDTH-1:0] line12;
wire [REG_WIDTH-1:0] line13;
wire [REG_WIDTH-1:0] line14;
wire [REG_WIDTH-1:0] line15;
wire [REG_WIDTH-1:0] line16;
wire [REG_WIDTH-1:0] line17;
wire [REG_WIDTH-1:0] line18;
wire [REG_WIDTH-1:0] line19;
wire [REG_WIDTH-1:0] line20;
wire [REG_WIDTH-1:0] line21;
wire [REG_WIDTH-1:0] line22;
wire [REG_WIDTH-1:0] line23;
wire [REG_WIDTH-1:0] line24;
wire [REG_WIDTH-1:0] line25;
wire [REG_WIDTH-1:0] line26;
wire [REG_WIDTH-1:0] line27;
wire [REG_WIDTH-1:0] line28;
wire [REG_WIDTH-1:0] line29;
wire [REG_WIDTH-1:0] line30;
wire [REG_WIDTH-1:0] line31;
wire [4:0] rd_a_d1;
reg [REG_WIDTH-1:0] dout;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
// Flop write address, write data and write enable
dff_ns #(5) wr_a_d1_ff (.din(wr_a),
.clk(wr_clk),
.q(wr_a_d1));
dff_ns #(REG_WIDTH) din_d1_ff (.din(din),
.clk(wr_clk),
.q(din_d1));
dff_ns #(1) wen_l_d1_ff (.din(wen_l),
.clk(wr_clk),
.q(wen_l_d1));
assign wr_a_dec_d1 = 1'b1 << wr_a_d1;
assign wen_dec_d1 = {32{~wen_l_d1}} & wr_a_dec_d1;
// FF's for storage
dffe_ns #(REG_WIDTH) line0_ff (.din(din_d1),.en(wen_dec_d1[0]),.clk(wr_clk),.q(line0));
dffe_ns #(REG_WIDTH) line1_ff (.din(din_d1),.en(wen_dec_d1[1]),.clk(wr_clk),.q(line1));
dffe_ns #(REG_WIDTH) line2_ff (.din(din_d1),.en(wen_dec_d1[2]),.clk(wr_clk),.q(line2));
dffe_ns #(REG_WIDTH) line3_ff (.din(din_d1),.en(wen_dec_d1[3]),.clk(wr_clk),.q(line3));
dffe_ns #(REG_WIDTH) line4_ff (.din(din_d1),.en(wen_dec_d1[4]),.clk(wr_clk),.q(line4));
dffe_ns #(REG_WIDTH) line5_ff (.din(din_d1),.en(wen_dec_d1[5]),.clk(wr_clk),.q(line5));
dffe_ns #(REG_WIDTH) line6_ff (.din(din_d1),.en(wen_dec_d1[6]),.clk(wr_clk),.q(line6));
dffe_ns #(REG_WIDTH) line7_ff (.din(din_d1),.en(wen_dec_d1[7]),.clk(wr_clk),.q(line7));
dffe_ns #(REG_WIDTH) line8_ff (.din(din_d1),.en(wen_dec_d1[8]),.clk(wr_clk),.q(line8));
dffe_ns #(REG_WIDTH) line9_ff (.din(din_d1),.en(wen_dec_d1[9]),.clk(wr_clk),.q(line9));
dffe_ns #(REG_WIDTH) line10_ff (.din(din_d1),.en(wen_dec_d1[10]),.clk(wr_clk),.q(line10));
dffe_ns #(REG_WIDTH) line11_ff (.din(din_d1),.en(wen_dec_d1[11]),.clk(wr_clk),.q(line11));
dffe_ns #(REG_WIDTH) line12_ff (.din(din_d1),.en(wen_dec_d1[12]),.clk(wr_clk),.q(line12));
dffe_ns #(REG_WIDTH) line13_ff (.din(din_d1),.en(wen_dec_d1[13]),.clk(wr_clk),.q(line13));
dffe_ns #(REG_WIDTH) line14_ff (.din(din_d1),.en(wen_dec_d1[14]),.clk(wr_clk),.q(line14));
dffe_ns #(REG_WIDTH) line15_ff (.din(din_d1),.en(wen_dec_d1[15]),.clk(wr_clk),.q(line15));
dffe_ns #(REG_WIDTH) line16_ff (.din(din_d1),.en(wen_dec_d1[16]),.clk(wr_clk),.q(line16));
dffe_ns #(REG_WIDTH) line17_ff (.din(din_d1),.en(wen_dec_d1[17]),.clk(wr_clk),.q(line17));
dffe_ns #(REG_WIDTH) line18_ff (.din(din_d1),.en(wen_dec_d1[18]),.clk(wr_clk),.q(line18));
dffe_ns #(REG_WIDTH) line19_ff (.din(din_d1),.en(wen_dec_d1[19]),.clk(wr_clk),.q(line19));
dffe_ns #(REG_WIDTH) line20_ff (.din(din_d1),.en(wen_dec_d1[20]),.clk(wr_clk),.q(line20));
dffe_ns #(REG_WIDTH) line21_ff (.din(din_d1),.en(wen_dec_d1[21]),.clk(wr_clk),.q(line21));
dffe_ns #(REG_WIDTH) line22_ff (.din(din_d1),.en(wen_dec_d1[22]),.clk(wr_clk),.q(line22));
dffe_ns #(REG_WIDTH) line23_ff (.din(din_d1),.en(wen_dec_d1[23]),.clk(wr_clk),.q(line23));
dffe_ns #(REG_WIDTH) line24_ff (.din(din_d1),.en(wen_dec_d1[24]),.clk(wr_clk),.q(line24));
dffe_ns #(REG_WIDTH) line25_ff (.din(din_d1),.en(wen_dec_d1[25]),.clk(wr_clk),.q(line25));
dffe_ns #(REG_WIDTH) line26_ff (.din(din_d1),.en(wen_dec_d1[26]),.clk(wr_clk),.q(line26));
dffe_ns #(REG_WIDTH) line27_ff (.din(din_d1),.en(wen_dec_d1[27]),.clk(wr_clk),.q(line27));
dffe_ns #(REG_WIDTH) line28_ff (.din(din_d1),.en(wen_dec_d1[28]),.clk(wr_clk),.q(line28));
dffe_ns #(REG_WIDTH) line29_ff (.din(din_d1),.en(wen_dec_d1[29]),.clk(wr_clk),.q(line29));
dffe_ns #(REG_WIDTH) line30_ff (.din(din_d1),.en(wen_dec_d1[30]),.clk(wr_clk),.q(line30));
dffe_ns #(REG_WIDTH) line31_ff (.din(din_d1),.en(wen_dec_d1[31]),.clk(wr_clk),.q(line31));
// Flop read address
dff_ns #(5) rd_a_d1_ff (.din(rd_a),
.clk(rd_clk),
.q(rd_a_d1));
// Mux out read data
always @(/*AUTOSENSE*/line0 or line1 or line10 or line11 or line12
or line13 or line14 or line15 or line16 or line17
or line18 or line19 or line2 or line20 or line21 or line22
or line23 or line24 or line25 or line26 or line27
or line28 or line29 or line3 or line30 or line31 or line4
or line5 or line6 or line7 or line8 or line9 or rd_a_d1) begin
case (rd_a_d1)
5'd0: dout = line0;
5'd1: dout = line1;
5'd2: dout = line2;
5'd3: dout = line3;
5'd4: dout = line4;
5'd5: dout = line5;
5'd6: dout = line6;
5'd7: dout = line7;
5'd8: dout = line8;
5'd9: dout = line9;
5'd10: dout = line10;
5'd11: dout = line11;
5'd12: dout = line12;
5'd13: dout = line13;
5'd14: dout = line14;
5'd15: dout = line15;
5'd16: dout = line16;
5'd17: dout = line17;
5'd18: dout = line18;
5'd19: dout = line19;
5'd20: dout = line20;
5'd21: dout = line21;
5'd22: dout = line22;
5'd23: dout = line23;
5'd24: dout = line24;
5'd25: dout = line25;
5'd26: dout = line26;
5'd27: dout = line27;
5'd28: dout = line28;
5'd29: dout = line29;
5'd30: dout = line30;
5'd31: dout = line31;
default: dout = {REG_WIDTH{1'bx}};
endcase // case(rd_a_d1)
end
endmodule // iobdg_1r1w_rf32
// Local Variables:
// verilog-auto-sense-defines-constant:t
// End:
|
// wasca_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module wasca_mm_interconnect_0 (
input wire altpll_1_c0_clk, // altpll_1_c0.clk
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset, // altpll_1_inclk_interface_reset_reset_bridge_in_reset.reset
input wire buffered_spi_0_reset_reset_bridge_in_reset_reset, // buffered_spi_0_reset_reset_bridge_in_reset.reset
input wire nios2_gen2_0_reset_reset_bridge_in_reset_reset, // nios2_gen2_0_reset_reset_bridge_in_reset.reset
input wire [26:0] nios2_gen2_0_data_master_address, // nios2_gen2_0_data_master.address
output wire nios2_gen2_0_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_gen2_0_data_master_byteenable, // .byteenable
input wire nios2_gen2_0_data_master_read, // .read
output wire [31:0] nios2_gen2_0_data_master_readdata, // .readdata
input wire nios2_gen2_0_data_master_write, // .write
input wire [31:0] nios2_gen2_0_data_master_writedata, // .writedata
input wire nios2_gen2_0_data_master_debugaccess, // .debugaccess
input wire [19:0] nios2_gen2_0_instruction_master_address, // nios2_gen2_0_instruction_master.address
output wire nios2_gen2_0_instruction_master_waitrequest, // .waitrequest
input wire nios2_gen2_0_instruction_master_read, // .read
output wire [31:0] nios2_gen2_0_instruction_master_readdata, // .readdata
output wire [7:0] abus_avalon_sdram_bridge_0_avalon_regs_address, // abus_avalon_sdram_bridge_0_avalon_regs.address
output wire abus_avalon_sdram_bridge_0_avalon_regs_write, // .write
output wire abus_avalon_sdram_bridge_0_avalon_regs_read, // .read
input wire [15:0] abus_avalon_sdram_bridge_0_avalon_regs_readdata, // .readdata
output wire [15:0] abus_avalon_sdram_bridge_0_avalon_regs_writedata, // .writedata
input wire abus_avalon_sdram_bridge_0_avalon_regs_readdatavalid, // .readdatavalid
input wire abus_avalon_sdram_bridge_0_avalon_regs_waitrequest, // .waitrequest
output wire [25:0] abus_avalon_sdram_bridge_0_avalon_sdram_address, // abus_avalon_sdram_bridge_0_avalon_sdram.address
output wire abus_avalon_sdram_bridge_0_avalon_sdram_write, // .write
output wire abus_avalon_sdram_bridge_0_avalon_sdram_read, // .read
input wire [15:0] abus_avalon_sdram_bridge_0_avalon_sdram_readdata, // .readdata
output wire [15:0] abus_avalon_sdram_bridge_0_avalon_sdram_writedata, // .writedata
output wire [1:0] abus_avalon_sdram_bridge_0_avalon_sdram_byteenable, // .byteenable
input wire abus_avalon_sdram_bridge_0_avalon_sdram_readdatavalid, // .readdatavalid
input wire abus_avalon_sdram_bridge_0_avalon_sdram_waitrequest, // .waitrequest
output wire [7:0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address, // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave.address
output wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write, // .write
output wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read, // .read
input wire [31:0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata, // .readdata
output wire [31:0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata, // .writedata
output wire [3:0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable, // .byteenable
input wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest, // .waitrequest
output wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect, // .chipselect
output wire [1:0] altpll_1_pll_slave_address, // altpll_1_pll_slave.address
output wire altpll_1_pll_slave_write, // .write
output wire altpll_1_pll_slave_read, // .read
input wire [31:0] altpll_1_pll_slave_readdata, // .readdata
output wire [31:0] altpll_1_pll_slave_writedata, // .writedata
output wire [1:0] audio_0_avalon_audio_slave_address, // audio_0_avalon_audio_slave.address
output wire audio_0_avalon_audio_slave_write, // .write
output wire audio_0_avalon_audio_slave_read, // .read
input wire [31:0] audio_0_avalon_audio_slave_readdata, // .readdata
output wire [31:0] audio_0_avalon_audio_slave_writedata, // .writedata
output wire audio_0_avalon_audio_slave_chipselect, // .chipselect
output wire [13:0] buffered_spi_0_avalon_address, // buffered_spi_0_avalon.address
output wire buffered_spi_0_avalon_write, // .write
output wire buffered_spi_0_avalon_read, // .read
input wire [15:0] buffered_spi_0_avalon_readdata, // .readdata
output wire [15:0] buffered_spi_0_avalon_writedata, // .writedata
input wire buffered_spi_0_avalon_readdatavalid, // .readdatavalid
input wire buffered_spi_0_avalon_waitrequest, // .waitrequest
output wire [8:0] nios2_gen2_0_debug_mem_slave_address, // nios2_gen2_0_debug_mem_slave.address
output wire nios2_gen2_0_debug_mem_slave_write, // .write
output wire nios2_gen2_0_debug_mem_slave_read, // .read
input wire [31:0] nios2_gen2_0_debug_mem_slave_readdata, // .readdata
output wire [31:0] nios2_gen2_0_debug_mem_slave_writedata, // .writedata
output wire [3:0] nios2_gen2_0_debug_mem_slave_byteenable, // .byteenable
input wire nios2_gen2_0_debug_mem_slave_waitrequest, // .waitrequest
output wire nios2_gen2_0_debug_mem_slave_debugaccess, // .debugaccess
output wire [15:0] onchip_flash_0_data_address, // onchip_flash_0_data.address
output wire onchip_flash_0_data_read, // .read
input wire [31:0] onchip_flash_0_data_readdata, // .readdata
output wire [3:0] onchip_flash_0_data_burstcount, // .burstcount
input wire onchip_flash_0_data_readdatavalid, // .readdatavalid
input wire onchip_flash_0_data_waitrequest, // .waitrequest
output wire [11:0] onchip_memory2_0_s1_address, // onchip_memory2_0_s1.address
output wire onchip_memory2_0_s1_write, // .write
input wire [31:0] onchip_memory2_0_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_0_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_0_s1_byteenable, // .byteenable
output wire onchip_memory2_0_s1_chipselect, // .chipselect
output wire onchip_memory2_0_s1_clken, // .clken
output wire [2:0] uart_0_s1_address, // uart_0_s1.address
output wire uart_0_s1_write, // .write
output wire uart_0_s1_read, // .read
input wire [15:0] uart_0_s1_readdata, // .readdata
output wire [15:0] uart_0_s1_writedata, // .writedata
output wire uart_0_s1_begintransfer, // .begintransfer
output wire uart_0_s1_chipselect // .chipselect
);
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_data_master_agent:av_waitrequest -> nios2_gen2_0_data_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_data_master_agent:av_readdata -> nios2_gen2_0_data_master_translator:uav_readdata
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_data_master_translator:uav_debugaccess -> nios2_gen2_0_data_master_agent:av_debugaccess
wire [26:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_data_master_translator:uav_address -> nios2_gen2_0_data_master_agent:av_address
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_data_master_translator:uav_read -> nios2_gen2_0_data_master_agent:av_read
wire [3:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_data_master_translator:uav_byteenable -> nios2_gen2_0_data_master_agent:av_byteenable
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_data_master_agent:av_readdatavalid -> nios2_gen2_0_data_master_translator:uav_readdatavalid
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_data_master_translator:uav_lock -> nios2_gen2_0_data_master_agent:av_lock
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_data_master_translator:uav_write -> nios2_gen2_0_data_master_agent:av_write
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_data_master_translator:uav_writedata -> nios2_gen2_0_data_master_agent:av_writedata
wire [2:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_data_master_translator:uav_burstcount -> nios2_gen2_0_data_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> nios2_gen2_0_data_master_agent:rp_valid
wire [107:0] rsp_mux_src_data; // rsp_mux:src_data -> nios2_gen2_0_data_master_agent:rp_data
wire rsp_mux_src_ready; // nios2_gen2_0_data_master_agent:rp_ready -> rsp_mux:src_ready
wire [9:0] rsp_mux_src_channel; // rsp_mux:src_channel -> nios2_gen2_0_data_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> nios2_gen2_0_data_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> nios2_gen2_0_data_master_agent:rp_endofpacket
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_instruction_master_agent:av_waitrequest -> nios2_gen2_0_instruction_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_instruction_master_agent:av_readdata -> nios2_gen2_0_instruction_master_translator:uav_readdata
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_instruction_master_translator:uav_debugaccess -> nios2_gen2_0_instruction_master_agent:av_debugaccess
wire [26:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_instruction_master_translator:uav_address -> nios2_gen2_0_instruction_master_agent:av_address
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_instruction_master_translator:uav_read -> nios2_gen2_0_instruction_master_agent:av_read
wire [3:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_instruction_master_translator:uav_byteenable -> nios2_gen2_0_instruction_master_agent:av_byteenable
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_instruction_master_agent:av_readdatavalid -> nios2_gen2_0_instruction_master_translator:uav_readdatavalid
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_instruction_master_translator:uav_lock -> nios2_gen2_0_instruction_master_agent:av_lock
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_instruction_master_translator:uav_write -> nios2_gen2_0_instruction_master_agent:av_write
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_instruction_master_translator:uav_writedata -> nios2_gen2_0_instruction_master_agent:av_writedata
wire [2:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_instruction_master_translator:uav_burstcount -> nios2_gen2_0_instruction_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_gen2_0_instruction_master_agent:rp_valid
wire [107:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_gen2_0_instruction_master_agent:rp_data
wire rsp_mux_001_src_ready; // nios2_gen2_0_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [9:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_gen2_0_instruction_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_gen2_0_instruction_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_gen2_0_instruction_master_agent:rp_endofpacket
wire [15:0] buffered_spi_0_avalon_agent_m0_readdata; // buffered_spi_0_avalon_translator:uav_readdata -> buffered_spi_0_avalon_agent:m0_readdata
wire buffered_spi_0_avalon_agent_m0_waitrequest; // buffered_spi_0_avalon_translator:uav_waitrequest -> buffered_spi_0_avalon_agent:m0_waitrequest
wire buffered_spi_0_avalon_agent_m0_debugaccess; // buffered_spi_0_avalon_agent:m0_debugaccess -> buffered_spi_0_avalon_translator:uav_debugaccess
wire [26:0] buffered_spi_0_avalon_agent_m0_address; // buffered_spi_0_avalon_agent:m0_address -> buffered_spi_0_avalon_translator:uav_address
wire [1:0] buffered_spi_0_avalon_agent_m0_byteenable; // buffered_spi_0_avalon_agent:m0_byteenable -> buffered_spi_0_avalon_translator:uav_byteenable
wire buffered_spi_0_avalon_agent_m0_read; // buffered_spi_0_avalon_agent:m0_read -> buffered_spi_0_avalon_translator:uav_read
wire buffered_spi_0_avalon_agent_m0_readdatavalid; // buffered_spi_0_avalon_translator:uav_readdatavalid -> buffered_spi_0_avalon_agent:m0_readdatavalid
wire buffered_spi_0_avalon_agent_m0_lock; // buffered_spi_0_avalon_agent:m0_lock -> buffered_spi_0_avalon_translator:uav_lock
wire [15:0] buffered_spi_0_avalon_agent_m0_writedata; // buffered_spi_0_avalon_agent:m0_writedata -> buffered_spi_0_avalon_translator:uav_writedata
wire buffered_spi_0_avalon_agent_m0_write; // buffered_spi_0_avalon_agent:m0_write -> buffered_spi_0_avalon_translator:uav_write
wire [1:0] buffered_spi_0_avalon_agent_m0_burstcount; // buffered_spi_0_avalon_agent:m0_burstcount -> buffered_spi_0_avalon_translator:uav_burstcount
wire buffered_spi_0_avalon_agent_rf_source_valid; // buffered_spi_0_avalon_agent:rf_source_valid -> buffered_spi_0_avalon_agent_rsp_fifo:in_valid
wire [90:0] buffered_spi_0_avalon_agent_rf_source_data; // buffered_spi_0_avalon_agent:rf_source_data -> buffered_spi_0_avalon_agent_rsp_fifo:in_data
wire buffered_spi_0_avalon_agent_rf_source_ready; // buffered_spi_0_avalon_agent_rsp_fifo:in_ready -> buffered_spi_0_avalon_agent:rf_source_ready
wire buffered_spi_0_avalon_agent_rf_source_startofpacket; // buffered_spi_0_avalon_agent:rf_source_startofpacket -> buffered_spi_0_avalon_agent_rsp_fifo:in_startofpacket
wire buffered_spi_0_avalon_agent_rf_source_endofpacket; // buffered_spi_0_avalon_agent:rf_source_endofpacket -> buffered_spi_0_avalon_agent_rsp_fifo:in_endofpacket
wire buffered_spi_0_avalon_agent_rsp_fifo_out_valid; // buffered_spi_0_avalon_agent_rsp_fifo:out_valid -> buffered_spi_0_avalon_agent:rf_sink_valid
wire [90:0] buffered_spi_0_avalon_agent_rsp_fifo_out_data; // buffered_spi_0_avalon_agent_rsp_fifo:out_data -> buffered_spi_0_avalon_agent:rf_sink_data
wire buffered_spi_0_avalon_agent_rsp_fifo_out_ready; // buffered_spi_0_avalon_agent:rf_sink_ready -> buffered_spi_0_avalon_agent_rsp_fifo:out_ready
wire buffered_spi_0_avalon_agent_rsp_fifo_out_startofpacket; // buffered_spi_0_avalon_agent_rsp_fifo:out_startofpacket -> buffered_spi_0_avalon_agent:rf_sink_startofpacket
wire buffered_spi_0_avalon_agent_rsp_fifo_out_endofpacket; // buffered_spi_0_avalon_agent_rsp_fifo:out_endofpacket -> buffered_spi_0_avalon_agent:rf_sink_endofpacket
wire [31:0] audio_0_avalon_audio_slave_agent_m0_readdata; // audio_0_avalon_audio_slave_translator:uav_readdata -> audio_0_avalon_audio_slave_agent:m0_readdata
wire audio_0_avalon_audio_slave_agent_m0_waitrequest; // audio_0_avalon_audio_slave_translator:uav_waitrequest -> audio_0_avalon_audio_slave_agent:m0_waitrequest
wire audio_0_avalon_audio_slave_agent_m0_debugaccess; // audio_0_avalon_audio_slave_agent:m0_debugaccess -> audio_0_avalon_audio_slave_translator:uav_debugaccess
wire [26:0] audio_0_avalon_audio_slave_agent_m0_address; // audio_0_avalon_audio_slave_agent:m0_address -> audio_0_avalon_audio_slave_translator:uav_address
wire [3:0] audio_0_avalon_audio_slave_agent_m0_byteenable; // audio_0_avalon_audio_slave_agent:m0_byteenable -> audio_0_avalon_audio_slave_translator:uav_byteenable
wire audio_0_avalon_audio_slave_agent_m0_read; // audio_0_avalon_audio_slave_agent:m0_read -> audio_0_avalon_audio_slave_translator:uav_read
wire audio_0_avalon_audio_slave_agent_m0_readdatavalid; // audio_0_avalon_audio_slave_translator:uav_readdatavalid -> audio_0_avalon_audio_slave_agent:m0_readdatavalid
wire audio_0_avalon_audio_slave_agent_m0_lock; // audio_0_avalon_audio_slave_agent:m0_lock -> audio_0_avalon_audio_slave_translator:uav_lock
wire [31:0] audio_0_avalon_audio_slave_agent_m0_writedata; // audio_0_avalon_audio_slave_agent:m0_writedata -> audio_0_avalon_audio_slave_translator:uav_writedata
wire audio_0_avalon_audio_slave_agent_m0_write; // audio_0_avalon_audio_slave_agent:m0_write -> audio_0_avalon_audio_slave_translator:uav_write
wire [2:0] audio_0_avalon_audio_slave_agent_m0_burstcount; // audio_0_avalon_audio_slave_agent:m0_burstcount -> audio_0_avalon_audio_slave_translator:uav_burstcount
wire audio_0_avalon_audio_slave_agent_rf_source_valid; // audio_0_avalon_audio_slave_agent:rf_source_valid -> audio_0_avalon_audio_slave_agent_rsp_fifo:in_valid
wire [108:0] audio_0_avalon_audio_slave_agent_rf_source_data; // audio_0_avalon_audio_slave_agent:rf_source_data -> audio_0_avalon_audio_slave_agent_rsp_fifo:in_data
wire audio_0_avalon_audio_slave_agent_rf_source_ready; // audio_0_avalon_audio_slave_agent_rsp_fifo:in_ready -> audio_0_avalon_audio_slave_agent:rf_source_ready
wire audio_0_avalon_audio_slave_agent_rf_source_startofpacket; // audio_0_avalon_audio_slave_agent:rf_source_startofpacket -> audio_0_avalon_audio_slave_agent_rsp_fifo:in_startofpacket
wire audio_0_avalon_audio_slave_agent_rf_source_endofpacket; // audio_0_avalon_audio_slave_agent:rf_source_endofpacket -> audio_0_avalon_audio_slave_agent_rsp_fifo:in_endofpacket
wire audio_0_avalon_audio_slave_agent_rsp_fifo_out_valid; // audio_0_avalon_audio_slave_agent_rsp_fifo:out_valid -> audio_0_avalon_audio_slave_agent:rf_sink_valid
wire [108:0] audio_0_avalon_audio_slave_agent_rsp_fifo_out_data; // audio_0_avalon_audio_slave_agent_rsp_fifo:out_data -> audio_0_avalon_audio_slave_agent:rf_sink_data
wire audio_0_avalon_audio_slave_agent_rsp_fifo_out_ready; // audio_0_avalon_audio_slave_agent:rf_sink_ready -> audio_0_avalon_audio_slave_agent_rsp_fifo:out_ready
wire audio_0_avalon_audio_slave_agent_rsp_fifo_out_startofpacket; // audio_0_avalon_audio_slave_agent_rsp_fifo:out_startofpacket -> audio_0_avalon_audio_slave_agent:rf_sink_startofpacket
wire audio_0_avalon_audio_slave_agent_rsp_fifo_out_endofpacket; // audio_0_avalon_audio_slave_agent_rsp_fifo:out_endofpacket -> audio_0_avalon_audio_slave_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> audio_0_avalon_audio_slave_agent:cp_valid
wire [107:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> audio_0_avalon_audio_slave_agent:cp_data
wire cmd_mux_001_src_ready; // audio_0_avalon_audio_slave_agent:cp_ready -> cmd_mux_001:src_ready
wire [9:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> audio_0_avalon_audio_slave_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> audio_0_avalon_audio_slave_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> audio_0_avalon_audio_slave_agent:cp_endofpacket
wire [15:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_readdata; // abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_readdata -> abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_readdata
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_waitrequest; // abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_waitrequest -> abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_waitrequest
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_debugaccess; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_debugaccess -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_debugaccess
wire [26:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_address; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_address -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_address
wire [1:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_byteenable; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_byteenable -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_byteenable
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_read; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_read -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_read
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_readdatavalid; // abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_readdatavalid -> abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_readdatavalid
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_lock; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_lock -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_lock
wire [15:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_writedata; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_writedata -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_writedata
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_write; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_write -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_write
wire [1:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_burstcount; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_burstcount -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_burstcount
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_valid; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_source_valid -> abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:in_valid
wire [90:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_data; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_source_data -> abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:in_data
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_ready; // abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:in_ready -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_source_ready
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_startofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_source_startofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:in_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_endofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_source_endofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:in_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_valid; // abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:out_valid -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_sink_valid
wire [90:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_data; // abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:out_data -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_sink_data
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_ready; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_sink_ready -> abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:out_ready
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_startofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:out_startofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_sink_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_endofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:out_endofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_sink_endofpacket
wire [31:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_readdata; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_readdata -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_readdata
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_waitrequest; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_waitrequest -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_waitrequest
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_debugaccess; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_debugaccess -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_debugaccess
wire [26:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_address; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_address -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_address
wire [3:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_byteenable; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_byteenable -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_byteenable
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_read; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_read -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_read
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_readdatavalid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_readdatavalid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_readdatavalid
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_lock; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_lock -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_lock
wire [31:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_writedata; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_writedata -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_writedata
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_write; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_write -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_write
wire [2:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_burstcount; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_burstcount -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_burstcount
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_valid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_source_valid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:in_valid
wire [108:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_data; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_source_data -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:in_data
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_ready; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:in_ready -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_source_ready
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_startofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_source_startofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:in_startofpacket
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_endofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_source_endofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:in_endofpacket
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_valid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:out_valid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_sink_valid
wire [108:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_data; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:out_data -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_sink_data
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_ready; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_sink_ready -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:out_ready
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_startofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:out_startofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_sink_startofpacket
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_endofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:out_endofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:cp_valid
wire [107:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:cp_data
wire cmd_mux_003_src_ready; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:cp_ready -> cmd_mux_003:src_ready
wire [9:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:cp_endofpacket
wire [15:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_readdata; // abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_readdata -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_readdata
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_waitrequest; // abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_waitrequest -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_waitrequest
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_debugaccess; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_debugaccess -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_debugaccess
wire [26:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_address; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_address -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_address
wire [1:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_byteenable; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_byteenable -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_byteenable
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_read; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_read -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_read
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_readdatavalid; // abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_readdatavalid -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_readdatavalid
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_lock; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_lock -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_lock
wire [15:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_writedata; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_writedata -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_writedata
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_write; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_write -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_write
wire [1:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_burstcount; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_burstcount -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_burstcount
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_valid; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_source_valid -> abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:in_valid
wire [90:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_data; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_source_data -> abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:in_data
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_ready; // abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:in_ready -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_source_ready
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_startofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_source_startofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:in_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_endofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_source_endofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:in_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_valid; // abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:out_valid -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_sink_valid
wire [90:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_data; // abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:out_data -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_sink_data
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_ready; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_sink_ready -> abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:out_ready
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_startofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:out_startofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_sink_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_endofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:out_endofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_sink_endofpacket
wire [31:0] onchip_flash_0_data_agent_m0_readdata; // onchip_flash_0_data_translator:uav_readdata -> onchip_flash_0_data_agent:m0_readdata
wire onchip_flash_0_data_agent_m0_waitrequest; // onchip_flash_0_data_translator:uav_waitrequest -> onchip_flash_0_data_agent:m0_waitrequest
wire onchip_flash_0_data_agent_m0_debugaccess; // onchip_flash_0_data_agent:m0_debugaccess -> onchip_flash_0_data_translator:uav_debugaccess
wire [26:0] onchip_flash_0_data_agent_m0_address; // onchip_flash_0_data_agent:m0_address -> onchip_flash_0_data_translator:uav_address
wire [3:0] onchip_flash_0_data_agent_m0_byteenable; // onchip_flash_0_data_agent:m0_byteenable -> onchip_flash_0_data_translator:uav_byteenable
wire onchip_flash_0_data_agent_m0_read; // onchip_flash_0_data_agent:m0_read -> onchip_flash_0_data_translator:uav_read
wire onchip_flash_0_data_agent_m0_readdatavalid; // onchip_flash_0_data_translator:uav_readdatavalid -> onchip_flash_0_data_agent:m0_readdatavalid
wire onchip_flash_0_data_agent_m0_lock; // onchip_flash_0_data_agent:m0_lock -> onchip_flash_0_data_translator:uav_lock
wire [31:0] onchip_flash_0_data_agent_m0_writedata; // onchip_flash_0_data_agent:m0_writedata -> onchip_flash_0_data_translator:uav_writedata
wire onchip_flash_0_data_agent_m0_write; // onchip_flash_0_data_agent:m0_write -> onchip_flash_0_data_translator:uav_write
wire [5:0] onchip_flash_0_data_agent_m0_burstcount; // onchip_flash_0_data_agent:m0_burstcount -> onchip_flash_0_data_translator:uav_burstcount
wire onchip_flash_0_data_agent_rf_source_valid; // onchip_flash_0_data_agent:rf_source_valid -> onchip_flash_0_data_agent_rsp_fifo:in_valid
wire [108:0] onchip_flash_0_data_agent_rf_source_data; // onchip_flash_0_data_agent:rf_source_data -> onchip_flash_0_data_agent_rsp_fifo:in_data
wire onchip_flash_0_data_agent_rf_source_ready; // onchip_flash_0_data_agent_rsp_fifo:in_ready -> onchip_flash_0_data_agent:rf_source_ready
wire onchip_flash_0_data_agent_rf_source_startofpacket; // onchip_flash_0_data_agent:rf_source_startofpacket -> onchip_flash_0_data_agent_rsp_fifo:in_startofpacket
wire onchip_flash_0_data_agent_rf_source_endofpacket; // onchip_flash_0_data_agent:rf_source_endofpacket -> onchip_flash_0_data_agent_rsp_fifo:in_endofpacket
wire onchip_flash_0_data_agent_rsp_fifo_out_valid; // onchip_flash_0_data_agent_rsp_fifo:out_valid -> onchip_flash_0_data_agent:rf_sink_valid
wire [108:0] onchip_flash_0_data_agent_rsp_fifo_out_data; // onchip_flash_0_data_agent_rsp_fifo:out_data -> onchip_flash_0_data_agent:rf_sink_data
wire onchip_flash_0_data_agent_rsp_fifo_out_ready; // onchip_flash_0_data_agent:rf_sink_ready -> onchip_flash_0_data_agent_rsp_fifo:out_ready
wire onchip_flash_0_data_agent_rsp_fifo_out_startofpacket; // onchip_flash_0_data_agent_rsp_fifo:out_startofpacket -> onchip_flash_0_data_agent:rf_sink_startofpacket
wire onchip_flash_0_data_agent_rsp_fifo_out_endofpacket; // onchip_flash_0_data_agent_rsp_fifo:out_endofpacket -> onchip_flash_0_data_agent:rf_sink_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> onchip_flash_0_data_agent:cp_valid
wire [107:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> onchip_flash_0_data_agent:cp_data
wire cmd_mux_005_src_ready; // onchip_flash_0_data_agent:cp_ready -> cmd_mux_005:src_ready
wire [9:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> onchip_flash_0_data_agent:cp_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> onchip_flash_0_data_agent:cp_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> onchip_flash_0_data_agent:cp_endofpacket
wire [31:0] altpll_1_pll_slave_agent_m0_readdata; // altpll_1_pll_slave_translator:uav_readdata -> altpll_1_pll_slave_agent:m0_readdata
wire altpll_1_pll_slave_agent_m0_waitrequest; // altpll_1_pll_slave_translator:uav_waitrequest -> altpll_1_pll_slave_agent:m0_waitrequest
wire altpll_1_pll_slave_agent_m0_debugaccess; // altpll_1_pll_slave_agent:m0_debugaccess -> altpll_1_pll_slave_translator:uav_debugaccess
wire [26:0] altpll_1_pll_slave_agent_m0_address; // altpll_1_pll_slave_agent:m0_address -> altpll_1_pll_slave_translator:uav_address
wire [3:0] altpll_1_pll_slave_agent_m0_byteenable; // altpll_1_pll_slave_agent:m0_byteenable -> altpll_1_pll_slave_translator:uav_byteenable
wire altpll_1_pll_slave_agent_m0_read; // altpll_1_pll_slave_agent:m0_read -> altpll_1_pll_slave_translator:uav_read
wire altpll_1_pll_slave_agent_m0_readdatavalid; // altpll_1_pll_slave_translator:uav_readdatavalid -> altpll_1_pll_slave_agent:m0_readdatavalid
wire altpll_1_pll_slave_agent_m0_lock; // altpll_1_pll_slave_agent:m0_lock -> altpll_1_pll_slave_translator:uav_lock
wire [31:0] altpll_1_pll_slave_agent_m0_writedata; // altpll_1_pll_slave_agent:m0_writedata -> altpll_1_pll_slave_translator:uav_writedata
wire altpll_1_pll_slave_agent_m0_write; // altpll_1_pll_slave_agent:m0_write -> altpll_1_pll_slave_translator:uav_write
wire [2:0] altpll_1_pll_slave_agent_m0_burstcount; // altpll_1_pll_slave_agent:m0_burstcount -> altpll_1_pll_slave_translator:uav_burstcount
wire altpll_1_pll_slave_agent_rf_source_valid; // altpll_1_pll_slave_agent:rf_source_valid -> altpll_1_pll_slave_agent_rsp_fifo:in_valid
wire [108:0] altpll_1_pll_slave_agent_rf_source_data; // altpll_1_pll_slave_agent:rf_source_data -> altpll_1_pll_slave_agent_rsp_fifo:in_data
wire altpll_1_pll_slave_agent_rf_source_ready; // altpll_1_pll_slave_agent_rsp_fifo:in_ready -> altpll_1_pll_slave_agent:rf_source_ready
wire altpll_1_pll_slave_agent_rf_source_startofpacket; // altpll_1_pll_slave_agent:rf_source_startofpacket -> altpll_1_pll_slave_agent_rsp_fifo:in_startofpacket
wire altpll_1_pll_slave_agent_rf_source_endofpacket; // altpll_1_pll_slave_agent:rf_source_endofpacket -> altpll_1_pll_slave_agent_rsp_fifo:in_endofpacket
wire altpll_1_pll_slave_agent_rsp_fifo_out_valid; // altpll_1_pll_slave_agent_rsp_fifo:out_valid -> altpll_1_pll_slave_agent:rf_sink_valid
wire [108:0] altpll_1_pll_slave_agent_rsp_fifo_out_data; // altpll_1_pll_slave_agent_rsp_fifo:out_data -> altpll_1_pll_slave_agent:rf_sink_data
wire altpll_1_pll_slave_agent_rsp_fifo_out_ready; // altpll_1_pll_slave_agent:rf_sink_ready -> altpll_1_pll_slave_agent_rsp_fifo:out_ready
wire altpll_1_pll_slave_agent_rsp_fifo_out_startofpacket; // altpll_1_pll_slave_agent_rsp_fifo:out_startofpacket -> altpll_1_pll_slave_agent:rf_sink_startofpacket
wire altpll_1_pll_slave_agent_rsp_fifo_out_endofpacket; // altpll_1_pll_slave_agent_rsp_fifo:out_endofpacket -> altpll_1_pll_slave_agent:rf_sink_endofpacket
wire altpll_1_pll_slave_agent_rdata_fifo_src_valid; // altpll_1_pll_slave_agent:rdata_fifo_src_valid -> altpll_1_pll_slave_agent_rdata_fifo:in_valid
wire [33:0] altpll_1_pll_slave_agent_rdata_fifo_src_data; // altpll_1_pll_slave_agent:rdata_fifo_src_data -> altpll_1_pll_slave_agent_rdata_fifo:in_data
wire altpll_1_pll_slave_agent_rdata_fifo_src_ready; // altpll_1_pll_slave_agent_rdata_fifo:in_ready -> altpll_1_pll_slave_agent:rdata_fifo_src_ready
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> altpll_1_pll_slave_agent:cp_valid
wire [107:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> altpll_1_pll_slave_agent:cp_data
wire cmd_mux_006_src_ready; // altpll_1_pll_slave_agent:cp_ready -> cmd_mux_006:src_ready
wire [9:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> altpll_1_pll_slave_agent:cp_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> altpll_1_pll_slave_agent:cp_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> altpll_1_pll_slave_agent:cp_endofpacket
wire [31:0] onchip_memory2_0_s1_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
wire onchip_memory2_0_s1_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
wire onchip_memory2_0_s1_agent_m0_debugaccess; // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [26:0] onchip_memory2_0_s1_agent_m0_address; // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire [3:0] onchip_memory2_0_s1_agent_m0_byteenable; // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_agent_m0_read; // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire onchip_memory2_0_s1_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
wire onchip_memory2_0_s1_agent_m0_lock; // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire [31:0] onchip_memory2_0_s1_agent_m0_writedata; // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire onchip_memory2_0_s1_agent_m0_write; // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire [2:0] onchip_memory2_0_s1_agent_m0_burstcount; // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire onchip_memory2_0_s1_agent_rf_source_valid; // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
wire [108:0] onchip_memory2_0_s1_agent_rf_source_data; // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_agent_rf_source_ready; // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
wire onchip_memory2_0_s1_agent_rf_source_startofpacket; // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_0_s1_agent_rf_source_endofpacket; // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
wire [108:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
wire onchip_memory2_0_s1_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_007_src_valid; // cmd_mux_007:src_valid -> onchip_memory2_0_s1_agent:cp_valid
wire [107:0] cmd_mux_007_src_data; // cmd_mux_007:src_data -> onchip_memory2_0_s1_agent:cp_data
wire cmd_mux_007_src_ready; // onchip_memory2_0_s1_agent:cp_ready -> cmd_mux_007:src_ready
wire [9:0] cmd_mux_007_src_channel; // cmd_mux_007:src_channel -> onchip_memory2_0_s1_agent:cp_channel
wire cmd_mux_007_src_startofpacket; // cmd_mux_007:src_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
wire cmd_mux_007_src_endofpacket; // cmd_mux_007:src_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
wire [31:0] uart_0_s1_agent_m0_readdata; // uart_0_s1_translator:uav_readdata -> uart_0_s1_agent:m0_readdata
wire uart_0_s1_agent_m0_waitrequest; // uart_0_s1_translator:uav_waitrequest -> uart_0_s1_agent:m0_waitrequest
wire uart_0_s1_agent_m0_debugaccess; // uart_0_s1_agent:m0_debugaccess -> uart_0_s1_translator:uav_debugaccess
wire [26:0] uart_0_s1_agent_m0_address; // uart_0_s1_agent:m0_address -> uart_0_s1_translator:uav_address
wire [3:0] uart_0_s1_agent_m0_byteenable; // uart_0_s1_agent:m0_byteenable -> uart_0_s1_translator:uav_byteenable
wire uart_0_s1_agent_m0_read; // uart_0_s1_agent:m0_read -> uart_0_s1_translator:uav_read
wire uart_0_s1_agent_m0_readdatavalid; // uart_0_s1_translator:uav_readdatavalid -> uart_0_s1_agent:m0_readdatavalid
wire uart_0_s1_agent_m0_lock; // uart_0_s1_agent:m0_lock -> uart_0_s1_translator:uav_lock
wire [31:0] uart_0_s1_agent_m0_writedata; // uart_0_s1_agent:m0_writedata -> uart_0_s1_translator:uav_writedata
wire uart_0_s1_agent_m0_write; // uart_0_s1_agent:m0_write -> uart_0_s1_translator:uav_write
wire [2:0] uart_0_s1_agent_m0_burstcount; // uart_0_s1_agent:m0_burstcount -> uart_0_s1_translator:uav_burstcount
wire uart_0_s1_agent_rf_source_valid; // uart_0_s1_agent:rf_source_valid -> uart_0_s1_agent_rsp_fifo:in_valid
wire [108:0] uart_0_s1_agent_rf_source_data; // uart_0_s1_agent:rf_source_data -> uart_0_s1_agent_rsp_fifo:in_data
wire uart_0_s1_agent_rf_source_ready; // uart_0_s1_agent_rsp_fifo:in_ready -> uart_0_s1_agent:rf_source_ready
wire uart_0_s1_agent_rf_source_startofpacket; // uart_0_s1_agent:rf_source_startofpacket -> uart_0_s1_agent_rsp_fifo:in_startofpacket
wire uart_0_s1_agent_rf_source_endofpacket; // uart_0_s1_agent:rf_source_endofpacket -> uart_0_s1_agent_rsp_fifo:in_endofpacket
wire uart_0_s1_agent_rsp_fifo_out_valid; // uart_0_s1_agent_rsp_fifo:out_valid -> uart_0_s1_agent:rf_sink_valid
wire [108:0] uart_0_s1_agent_rsp_fifo_out_data; // uart_0_s1_agent_rsp_fifo:out_data -> uart_0_s1_agent:rf_sink_data
wire uart_0_s1_agent_rsp_fifo_out_ready; // uart_0_s1_agent:rf_sink_ready -> uart_0_s1_agent_rsp_fifo:out_ready
wire uart_0_s1_agent_rsp_fifo_out_startofpacket; // uart_0_s1_agent_rsp_fifo:out_startofpacket -> uart_0_s1_agent:rf_sink_startofpacket
wire uart_0_s1_agent_rsp_fifo_out_endofpacket; // uart_0_s1_agent_rsp_fifo:out_endofpacket -> uart_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_008_src_valid; // cmd_mux_008:src_valid -> uart_0_s1_agent:cp_valid
wire [107:0] cmd_mux_008_src_data; // cmd_mux_008:src_data -> uart_0_s1_agent:cp_data
wire cmd_mux_008_src_ready; // uart_0_s1_agent:cp_ready -> cmd_mux_008:src_ready
wire [9:0] cmd_mux_008_src_channel; // cmd_mux_008:src_channel -> uart_0_s1_agent:cp_channel
wire cmd_mux_008_src_startofpacket; // cmd_mux_008:src_startofpacket -> uart_0_s1_agent:cp_startofpacket
wire cmd_mux_008_src_endofpacket; // cmd_mux_008:src_endofpacket -> uart_0_s1_agent:cp_endofpacket
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_readdata; // nios2_gen2_0_debug_mem_slave_translator:uav_readdata -> nios2_gen2_0_debug_mem_slave_agent:m0_readdata
wire nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest; // nios2_gen2_0_debug_mem_slave_translator:uav_waitrequest -> nios2_gen2_0_debug_mem_slave_agent:m0_waitrequest
wire nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess; // nios2_gen2_0_debug_mem_slave_agent:m0_debugaccess -> nios2_gen2_0_debug_mem_slave_translator:uav_debugaccess
wire [26:0] nios2_gen2_0_debug_mem_slave_agent_m0_address; // nios2_gen2_0_debug_mem_slave_agent:m0_address -> nios2_gen2_0_debug_mem_slave_translator:uav_address
wire [3:0] nios2_gen2_0_debug_mem_slave_agent_m0_byteenable; // nios2_gen2_0_debug_mem_slave_agent:m0_byteenable -> nios2_gen2_0_debug_mem_slave_translator:uav_byteenable
wire nios2_gen2_0_debug_mem_slave_agent_m0_read; // nios2_gen2_0_debug_mem_slave_agent:m0_read -> nios2_gen2_0_debug_mem_slave_translator:uav_read
wire nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid; // nios2_gen2_0_debug_mem_slave_translator:uav_readdatavalid -> nios2_gen2_0_debug_mem_slave_agent:m0_readdatavalid
wire nios2_gen2_0_debug_mem_slave_agent_m0_lock; // nios2_gen2_0_debug_mem_slave_agent:m0_lock -> nios2_gen2_0_debug_mem_slave_translator:uav_lock
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_writedata; // nios2_gen2_0_debug_mem_slave_agent:m0_writedata -> nios2_gen2_0_debug_mem_slave_translator:uav_writedata
wire nios2_gen2_0_debug_mem_slave_agent_m0_write; // nios2_gen2_0_debug_mem_slave_agent:m0_write -> nios2_gen2_0_debug_mem_slave_translator:uav_write
wire [2:0] nios2_gen2_0_debug_mem_slave_agent_m0_burstcount; // nios2_gen2_0_debug_mem_slave_agent:m0_burstcount -> nios2_gen2_0_debug_mem_slave_translator:uav_burstcount
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_valid; // nios2_gen2_0_debug_mem_slave_agent:rf_source_valid -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_valid
wire [108:0] nios2_gen2_0_debug_mem_slave_agent_rf_source_data; // nios2_gen2_0_debug_mem_slave_agent:rf_source_data -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_data
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_ready; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_gen2_0_debug_mem_slave_agent:rf_source_ready
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_startofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_endofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_valid
wire [108:0] nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready; // nios2_gen2_0_debug_mem_slave_agent:rf_sink_ready -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_ready
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_endofpacket
wire cmd_mux_009_src_valid; // cmd_mux_009:src_valid -> nios2_gen2_0_debug_mem_slave_agent:cp_valid
wire [107:0] cmd_mux_009_src_data; // cmd_mux_009:src_data -> nios2_gen2_0_debug_mem_slave_agent:cp_data
wire cmd_mux_009_src_ready; // nios2_gen2_0_debug_mem_slave_agent:cp_ready -> cmd_mux_009:src_ready
wire [9:0] cmd_mux_009_src_channel; // cmd_mux_009:src_channel -> nios2_gen2_0_debug_mem_slave_agent:cp_channel
wire cmd_mux_009_src_startofpacket; // cmd_mux_009:src_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_startofpacket
wire cmd_mux_009_src_endofpacket; // cmd_mux_009:src_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_endofpacket
wire nios2_gen2_0_data_master_agent_cp_valid; // nios2_gen2_0_data_master_agent:cp_valid -> router:sink_valid
wire [107:0] nios2_gen2_0_data_master_agent_cp_data; // nios2_gen2_0_data_master_agent:cp_data -> router:sink_data
wire nios2_gen2_0_data_master_agent_cp_ready; // router:sink_ready -> nios2_gen2_0_data_master_agent:cp_ready
wire nios2_gen2_0_data_master_agent_cp_startofpacket; // nios2_gen2_0_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire nios2_gen2_0_data_master_agent_cp_endofpacket; // nios2_gen2_0_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [107:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [9:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire nios2_gen2_0_instruction_master_agent_cp_valid; // nios2_gen2_0_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [107:0] nios2_gen2_0_instruction_master_agent_cp_data; // nios2_gen2_0_instruction_master_agent:cp_data -> router_001:sink_data
wire nios2_gen2_0_instruction_master_agent_cp_ready; // router_001:sink_ready -> nios2_gen2_0_instruction_master_agent:cp_ready
wire nios2_gen2_0_instruction_master_agent_cp_startofpacket; // nios2_gen2_0_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire nios2_gen2_0_instruction_master_agent_cp_endofpacket; // nios2_gen2_0_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [107:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [9:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire buffered_spi_0_avalon_agent_rp_valid; // buffered_spi_0_avalon_agent:rp_valid -> router_002:sink_valid
wire [89:0] buffered_spi_0_avalon_agent_rp_data; // buffered_spi_0_avalon_agent:rp_data -> router_002:sink_data
wire buffered_spi_0_avalon_agent_rp_ready; // router_002:sink_ready -> buffered_spi_0_avalon_agent:rp_ready
wire buffered_spi_0_avalon_agent_rp_startofpacket; // buffered_spi_0_avalon_agent:rp_startofpacket -> router_002:sink_startofpacket
wire buffered_spi_0_avalon_agent_rp_endofpacket; // buffered_spi_0_avalon_agent:rp_endofpacket -> router_002:sink_endofpacket
wire audio_0_avalon_audio_slave_agent_rp_valid; // audio_0_avalon_audio_slave_agent:rp_valid -> router_003:sink_valid
wire [107:0] audio_0_avalon_audio_slave_agent_rp_data; // audio_0_avalon_audio_slave_agent:rp_data -> router_003:sink_data
wire audio_0_avalon_audio_slave_agent_rp_ready; // router_003:sink_ready -> audio_0_avalon_audio_slave_agent:rp_ready
wire audio_0_avalon_audio_slave_agent_rp_startofpacket; // audio_0_avalon_audio_slave_agent:rp_startofpacket -> router_003:sink_startofpacket
wire audio_0_avalon_audio_slave_agent_rp_endofpacket; // audio_0_avalon_audio_slave_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [107:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [9:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_valid; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rp_valid -> router_004:sink_valid
wire [89:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_data; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rp_data -> router_004:sink_data
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_ready; // router_004:sink_ready -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rp_ready
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_startofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rp_startofpacket -> router_004:sink_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_endofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rp_endofpacket -> router_004:sink_endofpacket
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_valid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rp_valid -> router_005:sink_valid
wire [107:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_data; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rp_data -> router_005:sink_data
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_ready; // router_005:sink_ready -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rp_ready
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_startofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rp_startofpacket -> router_005:sink_startofpacket
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_endofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire [107:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire [9:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_valid; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rp_valid -> router_006:sink_valid
wire [89:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_data; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rp_data -> router_006:sink_data
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_ready; // router_006:sink_ready -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rp_ready
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_startofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rp_startofpacket -> router_006:sink_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_endofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rp_endofpacket -> router_006:sink_endofpacket
wire onchip_flash_0_data_agent_rp_valid; // onchip_flash_0_data_agent:rp_valid -> router_007:sink_valid
wire [107:0] onchip_flash_0_data_agent_rp_data; // onchip_flash_0_data_agent:rp_data -> router_007:sink_data
wire onchip_flash_0_data_agent_rp_ready; // router_007:sink_ready -> onchip_flash_0_data_agent:rp_ready
wire onchip_flash_0_data_agent_rp_startofpacket; // onchip_flash_0_data_agent:rp_startofpacket -> router_007:sink_startofpacket
wire onchip_flash_0_data_agent_rp_endofpacket; // onchip_flash_0_data_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire [107:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire [9:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire altpll_1_pll_slave_agent_rp_valid; // altpll_1_pll_slave_agent:rp_valid -> router_008:sink_valid
wire [107:0] altpll_1_pll_slave_agent_rp_data; // altpll_1_pll_slave_agent:rp_data -> router_008:sink_data
wire altpll_1_pll_slave_agent_rp_ready; // router_008:sink_ready -> altpll_1_pll_slave_agent:rp_ready
wire altpll_1_pll_slave_agent_rp_startofpacket; // altpll_1_pll_slave_agent:rp_startofpacket -> router_008:sink_startofpacket
wire altpll_1_pll_slave_agent_rp_endofpacket; // altpll_1_pll_slave_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_006:sink_valid
wire [107:0] router_008_src_data; // router_008:src_data -> rsp_demux_006:sink_data
wire router_008_src_ready; // rsp_demux_006:sink_ready -> router_008:src_ready
wire [9:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_006:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire onchip_memory2_0_s1_agent_rp_valid; // onchip_memory2_0_s1_agent:rp_valid -> router_009:sink_valid
wire [107:0] onchip_memory2_0_s1_agent_rp_data; // onchip_memory2_0_s1_agent:rp_data -> router_009:sink_data
wire onchip_memory2_0_s1_agent_rp_ready; // router_009:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
wire onchip_memory2_0_s1_agent_rp_startofpacket; // onchip_memory2_0_s1_agent:rp_startofpacket -> router_009:sink_startofpacket
wire onchip_memory2_0_s1_agent_rp_endofpacket; // onchip_memory2_0_s1_agent:rp_endofpacket -> router_009:sink_endofpacket
wire router_009_src_valid; // router_009:src_valid -> rsp_demux_007:sink_valid
wire [107:0] router_009_src_data; // router_009:src_data -> rsp_demux_007:sink_data
wire router_009_src_ready; // rsp_demux_007:sink_ready -> router_009:src_ready
wire [9:0] router_009_src_channel; // router_009:src_channel -> rsp_demux_007:sink_channel
wire router_009_src_startofpacket; // router_009:src_startofpacket -> rsp_demux_007:sink_startofpacket
wire router_009_src_endofpacket; // router_009:src_endofpacket -> rsp_demux_007:sink_endofpacket
wire uart_0_s1_agent_rp_valid; // uart_0_s1_agent:rp_valid -> router_010:sink_valid
wire [107:0] uart_0_s1_agent_rp_data; // uart_0_s1_agent:rp_data -> router_010:sink_data
wire uart_0_s1_agent_rp_ready; // router_010:sink_ready -> uart_0_s1_agent:rp_ready
wire uart_0_s1_agent_rp_startofpacket; // uart_0_s1_agent:rp_startofpacket -> router_010:sink_startofpacket
wire uart_0_s1_agent_rp_endofpacket; // uart_0_s1_agent:rp_endofpacket -> router_010:sink_endofpacket
wire router_010_src_valid; // router_010:src_valid -> rsp_demux_008:sink_valid
wire [107:0] router_010_src_data; // router_010:src_data -> rsp_demux_008:sink_data
wire router_010_src_ready; // rsp_demux_008:sink_ready -> router_010:src_ready
wire [9:0] router_010_src_channel; // router_010:src_channel -> rsp_demux_008:sink_channel
wire router_010_src_startofpacket; // router_010:src_startofpacket -> rsp_demux_008:sink_startofpacket
wire router_010_src_endofpacket; // router_010:src_endofpacket -> rsp_demux_008:sink_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_valid; // nios2_gen2_0_debug_mem_slave_agent:rp_valid -> router_011:sink_valid
wire [107:0] nios2_gen2_0_debug_mem_slave_agent_rp_data; // nios2_gen2_0_debug_mem_slave_agent:rp_data -> router_011:sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rp_ready; // router_011:sink_ready -> nios2_gen2_0_debug_mem_slave_agent:rp_ready
wire nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_startofpacket -> router_011:sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_endofpacket -> router_011:sink_endofpacket
wire router_011_src_valid; // router_011:src_valid -> rsp_demux_009:sink_valid
wire [107:0] router_011_src_data; // router_011:src_data -> rsp_demux_009:sink_data
wire router_011_src_ready; // rsp_demux_009:sink_ready -> router_011:src_ready
wire [9:0] router_011_src_channel; // router_011:src_channel -> rsp_demux_009:sink_channel
wire router_011_src_startofpacket; // router_011:src_startofpacket -> rsp_demux_009:sink_startofpacket
wire router_011_src_endofpacket; // router_011:src_endofpacket -> rsp_demux_009:sink_endofpacket
wire buffered_spi_0_avalon_burst_adapter_source0_valid; // buffered_spi_0_avalon_burst_adapter:source0_valid -> buffered_spi_0_avalon_agent:cp_valid
wire [89:0] buffered_spi_0_avalon_burst_adapter_source0_data; // buffered_spi_0_avalon_burst_adapter:source0_data -> buffered_spi_0_avalon_agent:cp_data
wire buffered_spi_0_avalon_burst_adapter_source0_ready; // buffered_spi_0_avalon_agent:cp_ready -> buffered_spi_0_avalon_burst_adapter:source0_ready
wire [9:0] buffered_spi_0_avalon_burst_adapter_source0_channel; // buffered_spi_0_avalon_burst_adapter:source0_channel -> buffered_spi_0_avalon_agent:cp_channel
wire buffered_spi_0_avalon_burst_adapter_source0_startofpacket; // buffered_spi_0_avalon_burst_adapter:source0_startofpacket -> buffered_spi_0_avalon_agent:cp_startofpacket
wire buffered_spi_0_avalon_burst_adapter_source0_endofpacket; // buffered_spi_0_avalon_burst_adapter:source0_endofpacket -> buffered_spi_0_avalon_agent:cp_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_valid; // abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:source0_valid -> abus_avalon_sdram_bridge_0_avalon_regs_agent:cp_valid
wire [89:0] abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_data; // abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:source0_data -> abus_avalon_sdram_bridge_0_avalon_regs_agent:cp_data
wire abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_ready; // abus_avalon_sdram_bridge_0_avalon_regs_agent:cp_ready -> abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:source0_ready
wire [9:0] abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_channel; // abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:source0_channel -> abus_avalon_sdram_bridge_0_avalon_regs_agent:cp_channel
wire abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_startofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:source0_startofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_agent:cp_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_endofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:source0_endofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_agent:cp_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_valid; // abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:source0_valid -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:cp_valid
wire [89:0] abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_data; // abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:source0_data -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:cp_data
wire abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_ready; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:cp_ready -> abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:source0_ready
wire [9:0] abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_channel; // abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:source0_channel -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:cp_channel
wire abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_startofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:source0_startofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:cp_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_endofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:source0_endofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [107:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [9:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [107:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [9:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [107:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [9:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [107:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [9:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire [107:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire [9:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire [107:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire [9:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src7_valid; // cmd_demux:src7_valid -> cmd_mux_007:sink0_valid
wire [107:0] cmd_demux_src7_data; // cmd_demux:src7_data -> cmd_mux_007:sink0_data
wire cmd_demux_src7_ready; // cmd_mux_007:sink0_ready -> cmd_demux:src7_ready
wire [9:0] cmd_demux_src7_channel; // cmd_demux:src7_channel -> cmd_mux_007:sink0_channel
wire cmd_demux_src7_startofpacket; // cmd_demux:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
wire cmd_demux_src7_endofpacket; // cmd_demux:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
wire cmd_demux_src8_valid; // cmd_demux:src8_valid -> cmd_mux_008:sink0_valid
wire [107:0] cmd_demux_src8_data; // cmd_demux:src8_data -> cmd_mux_008:sink0_data
wire cmd_demux_src8_ready; // cmd_mux_008:sink0_ready -> cmd_demux:src8_ready
wire [9:0] cmd_demux_src8_channel; // cmd_demux:src8_channel -> cmd_mux_008:sink0_channel
wire cmd_demux_src8_startofpacket; // cmd_demux:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
wire cmd_demux_src8_endofpacket; // cmd_demux:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_005:sink1_valid
wire [107:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_005:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux_005:sink1_ready -> cmd_demux_001:src0_ready
wire [9:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_005:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_005:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_005:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_007:sink1_valid
wire [107:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_007:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_007:sink1_ready -> cmd_demux_001:src1_ready
wire [9:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_007:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_007:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_007:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_009:sink0_valid
wire [107:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_009:sink0_data
wire cmd_demux_001_src2_ready; // cmd_mux_009:sink0_ready -> cmd_demux_001:src2_ready
wire [9:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_009:sink0_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_009:sink0_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_009:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [107:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [9:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [107:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [9:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [107:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [9:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [107:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [9:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire [107:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire [9:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire [107:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire [9:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_005_src1_valid; // rsp_demux_005:src1_valid -> rsp_mux_001:sink0_valid
wire [107:0] rsp_demux_005_src1_data; // rsp_demux_005:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_005_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_005:src1_ready
wire [9:0] rsp_demux_005_src1_channel; // rsp_demux_005:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_005_src1_startofpacket; // rsp_demux_005:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_005_src1_endofpacket; // rsp_demux_005:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_007_src0_valid; // rsp_demux_007:src0_valid -> rsp_mux:sink7_valid
wire [107:0] rsp_demux_007_src0_data; // rsp_demux_007:src0_data -> rsp_mux:sink7_data
wire rsp_demux_007_src0_ready; // rsp_mux:sink7_ready -> rsp_demux_007:src0_ready
wire [9:0] rsp_demux_007_src0_channel; // rsp_demux_007:src0_channel -> rsp_mux:sink7_channel
wire rsp_demux_007_src0_startofpacket; // rsp_demux_007:src0_startofpacket -> rsp_mux:sink7_startofpacket
wire rsp_demux_007_src0_endofpacket; // rsp_demux_007:src0_endofpacket -> rsp_mux:sink7_endofpacket
wire rsp_demux_007_src1_valid; // rsp_demux_007:src1_valid -> rsp_mux_001:sink1_valid
wire [107:0] rsp_demux_007_src1_data; // rsp_demux_007:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_007_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_007:src1_ready
wire [9:0] rsp_demux_007_src1_channel; // rsp_demux_007:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_007_src1_startofpacket; // rsp_demux_007:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_007_src1_endofpacket; // rsp_demux_007:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_008_src0_valid; // rsp_demux_008:src0_valid -> rsp_mux:sink8_valid
wire [107:0] rsp_demux_008_src0_data; // rsp_demux_008:src0_data -> rsp_mux:sink8_data
wire rsp_demux_008_src0_ready; // rsp_mux:sink8_ready -> rsp_demux_008:src0_ready
wire [9:0] rsp_demux_008_src0_channel; // rsp_demux_008:src0_channel -> rsp_mux:sink8_channel
wire rsp_demux_008_src0_startofpacket; // rsp_demux_008:src0_startofpacket -> rsp_mux:sink8_startofpacket
wire rsp_demux_008_src0_endofpacket; // rsp_demux_008:src0_endofpacket -> rsp_mux:sink8_endofpacket
wire rsp_demux_009_src0_valid; // rsp_demux_009:src0_valid -> rsp_mux_001:sink2_valid
wire [107:0] rsp_demux_009_src0_data; // rsp_demux_009:src0_data -> rsp_mux_001:sink2_data
wire rsp_demux_009_src0_ready; // rsp_mux_001:sink2_ready -> rsp_demux_009:src0_ready
wire [9:0] rsp_demux_009_src0_channel; // rsp_demux_009:src0_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_009_src0_startofpacket; // rsp_demux_009:src0_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_009_src0_endofpacket; // rsp_demux_009:src0_endofpacket -> rsp_mux_001:sink2_endofpacket
wire router_002_src_valid; // router_002:src_valid -> buffered_spi_0_avalon_rsp_width_adapter:in_valid
wire [89:0] router_002_src_data; // router_002:src_data -> buffered_spi_0_avalon_rsp_width_adapter:in_data
wire router_002_src_ready; // buffered_spi_0_avalon_rsp_width_adapter:in_ready -> router_002:src_ready
wire [9:0] router_002_src_channel; // router_002:src_channel -> buffered_spi_0_avalon_rsp_width_adapter:in_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> buffered_spi_0_avalon_rsp_width_adapter:in_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> buffered_spi_0_avalon_rsp_width_adapter:in_endofpacket
wire buffered_spi_0_avalon_rsp_width_adapter_src_valid; // buffered_spi_0_avalon_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire [107:0] buffered_spi_0_avalon_rsp_width_adapter_src_data; // buffered_spi_0_avalon_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire buffered_spi_0_avalon_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> buffered_spi_0_avalon_rsp_width_adapter:out_ready
wire [9:0] buffered_spi_0_avalon_rsp_width_adapter_src_channel; // buffered_spi_0_avalon_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
wire buffered_spi_0_avalon_rsp_width_adapter_src_startofpacket; // buffered_spi_0_avalon_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire buffered_spi_0_avalon_rsp_width_adapter_src_endofpacket; // buffered_spi_0_avalon_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:in_valid
wire [89:0] router_004_src_data; // router_004:src_data -> abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:in_data
wire router_004_src_ready; // abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:in_ready -> router_004:src_ready
wire [9:0] router_004_src_channel; // router_004:src_channel -> abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:in_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:in_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:in_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_valid; // abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:out_valid -> rsp_demux_002:sink_valid
wire [107:0] abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_data; // abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:out_data -> rsp_demux_002:sink_data
wire abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_ready; // rsp_demux_002:sink_ready -> abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:out_ready
wire [9:0] abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_channel; // abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:out_channel -> rsp_demux_002:sink_channel
wire abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_startofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:out_startofpacket -> rsp_demux_002:sink_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_endofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:out_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:in_valid
wire [89:0] router_006_src_data; // router_006:src_data -> abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:in_data
wire router_006_src_ready; // abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:in_ready -> router_006:src_ready
wire [9:0] router_006_src_channel; // router_006:src_channel -> abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:in_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:in_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:in_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_valid; // abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:out_valid -> rsp_demux_004:sink_valid
wire [107:0] abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_data; // abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:out_data -> rsp_demux_004:sink_data
wire abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_ready; // rsp_demux_004:sink_ready -> abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:out_ready
wire [9:0] abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_channel; // abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:out_channel -> rsp_demux_004:sink_channel
wire abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_startofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:out_startofpacket -> rsp_demux_004:sink_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_endofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:out_endofpacket -> rsp_demux_004:sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> buffered_spi_0_avalon_cmd_width_adapter:in_valid
wire [107:0] cmd_mux_src_data; // cmd_mux:src_data -> buffered_spi_0_avalon_cmd_width_adapter:in_data
wire cmd_mux_src_ready; // buffered_spi_0_avalon_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire [9:0] cmd_mux_src_channel; // cmd_mux:src_channel -> buffered_spi_0_avalon_cmd_width_adapter:in_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> buffered_spi_0_avalon_cmd_width_adapter:in_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> buffered_spi_0_avalon_cmd_width_adapter:in_endofpacket
wire buffered_spi_0_avalon_cmd_width_adapter_src_valid; // buffered_spi_0_avalon_cmd_width_adapter:out_valid -> buffered_spi_0_avalon_burst_adapter:sink0_valid
wire [89:0] buffered_spi_0_avalon_cmd_width_adapter_src_data; // buffered_spi_0_avalon_cmd_width_adapter:out_data -> buffered_spi_0_avalon_burst_adapter:sink0_data
wire buffered_spi_0_avalon_cmd_width_adapter_src_ready; // buffered_spi_0_avalon_burst_adapter:sink0_ready -> buffered_spi_0_avalon_cmd_width_adapter:out_ready
wire [9:0] buffered_spi_0_avalon_cmd_width_adapter_src_channel; // buffered_spi_0_avalon_cmd_width_adapter:out_channel -> buffered_spi_0_avalon_burst_adapter:sink0_channel
wire buffered_spi_0_avalon_cmd_width_adapter_src_startofpacket; // buffered_spi_0_avalon_cmd_width_adapter:out_startofpacket -> buffered_spi_0_avalon_burst_adapter:sink0_startofpacket
wire buffered_spi_0_avalon_cmd_width_adapter_src_endofpacket; // buffered_spi_0_avalon_cmd_width_adapter:out_endofpacket -> buffered_spi_0_avalon_burst_adapter:sink0_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:in_valid
wire [107:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:in_data
wire cmd_mux_002_src_ready; // abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:in_ready -> cmd_mux_002:src_ready
wire [9:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:in_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:in_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:in_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_valid; // abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:out_valid -> abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:sink0_valid
wire [89:0] abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_data; // abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:out_data -> abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:sink0_data
wire abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_ready; // abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:sink0_ready -> abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:out_ready
wire [9:0] abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_channel; // abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:out_channel -> abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:sink0_channel
wire abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_startofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:out_startofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:sink0_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_endofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:out_endofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:sink0_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:in_valid
wire [107:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:in_data
wire cmd_mux_004_src_ready; // abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:in_ready -> cmd_mux_004:src_ready
wire [9:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:in_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:in_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:in_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_valid; // abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:out_valid -> abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:sink0_valid
wire [89:0] abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_data; // abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:out_data -> abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:sink0_data
wire abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_ready; // abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:sink0_ready -> abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:out_ready
wire [9:0] abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_channel; // abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:out_channel -> abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:sink0_channel
wire abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_startofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:out_startofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:sink0_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_endofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:out_endofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> crosser:in_valid
wire [107:0] cmd_demux_src6_data; // cmd_demux:src6_data -> crosser:in_data
wire cmd_demux_src6_ready; // crosser:in_ready -> cmd_demux:src6_ready
wire [9:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> crosser:in_channel
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> crosser:in_startofpacket
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> crosser:in_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux_006:sink0_valid
wire [107:0] crosser_out_data; // crosser:out_data -> cmd_mux_006:sink0_data
wire crosser_out_ready; // cmd_mux_006:sink0_ready -> crosser:out_ready
wire [9:0] crosser_out_channel; // crosser:out_channel -> cmd_mux_006:sink0_channel
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux_006:sink0_startofpacket
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux_006:sink0_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> crosser_001:in_valid
wire [107:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> crosser_001:in_data
wire rsp_demux_006_src0_ready; // crosser_001:in_ready -> rsp_demux_006:src0_ready
wire [9:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> crosser_001:in_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> crosser_001:in_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> crosser_001:in_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> rsp_mux:sink6_valid
wire [107:0] crosser_001_out_data; // crosser_001:out_data -> rsp_mux:sink6_data
wire crosser_001_out_ready; // rsp_mux:sink6_ready -> crosser_001:out_ready
wire [9:0] crosser_001_out_channel; // crosser_001:out_channel -> rsp_mux:sink6_channel
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> rsp_mux:sink6_startofpacket
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> rsp_mux:sink6_endofpacket
wire buffered_spi_0_avalon_agent_rdata_fifo_src_valid; // buffered_spi_0_avalon_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [17:0] buffered_spi_0_avalon_agent_rdata_fifo_src_data; // buffered_spi_0_avalon_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire buffered_spi_0_avalon_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> buffered_spi_0_avalon_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> buffered_spi_0_avalon_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> buffered_spi_0_avalon_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // buffered_spi_0_avalon_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> buffered_spi_0_avalon_agent:rdata_fifo_sink_error
wire audio_0_avalon_audio_slave_agent_rdata_fifo_src_valid; // audio_0_avalon_audio_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] audio_0_avalon_audio_slave_agent_rdata_fifo_src_data; // audio_0_avalon_audio_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire audio_0_avalon_audio_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> audio_0_avalon_audio_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> audio_0_avalon_audio_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> audio_0_avalon_audio_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // audio_0_avalon_audio_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> audio_0_avalon_audio_slave_agent:rdata_fifo_sink_error
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_valid; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [17:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_data; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rdata_fifo_sink_error
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_valid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_data; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rdata_fifo_sink_error
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_valid; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
wire [17:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_data; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rdata_fifo_src_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rdata_fifo_sink_error
wire onchip_flash_0_data_agent_rdata_fifo_src_valid; // onchip_flash_0_data_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
wire [33:0] onchip_flash_0_data_agent_rdata_fifo_src_data; // onchip_flash_0_data_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
wire onchip_flash_0_data_agent_rdata_fifo_src_ready; // avalon_st_adapter_005:in_0_ready -> onchip_flash_0_data_agent:rdata_fifo_src_ready
wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> onchip_flash_0_data_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> onchip_flash_0_data_agent:rdata_fifo_sink_data
wire avalon_st_adapter_005_out_0_ready; // onchip_flash_0_data_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> onchip_flash_0_data_agent:rdata_fifo_sink_error
wire altpll_1_pll_slave_agent_rdata_fifo_out_valid; // altpll_1_pll_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter_006:in_0_valid
wire [33:0] altpll_1_pll_slave_agent_rdata_fifo_out_data; // altpll_1_pll_slave_agent_rdata_fifo:out_data -> avalon_st_adapter_006:in_0_data
wire altpll_1_pll_slave_agent_rdata_fifo_out_ready; // avalon_st_adapter_006:in_0_ready -> altpll_1_pll_slave_agent_rdata_fifo:out_ready
wire avalon_st_adapter_006_out_0_valid; // avalon_st_adapter_006:out_0_valid -> altpll_1_pll_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_006_out_0_data; // avalon_st_adapter_006:out_0_data -> altpll_1_pll_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_006_out_0_ready; // altpll_1_pll_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
wire [0:0] avalon_st_adapter_006_out_0_error; // avalon_st_adapter_006:out_0_error -> altpll_1_pll_slave_agent:rdata_fifo_sink_error
wire onchip_memory2_0_s1_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_007:in_0_valid
wire [33:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_007:in_0_data
wire onchip_memory2_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_007:in_0_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_007_out_0_valid; // avalon_st_adapter_007:out_0_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_007_out_0_data; // avalon_st_adapter_007:out_0_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_007_out_0_ready; // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_007:out_0_ready
wire [0:0] avalon_st_adapter_007_out_0_error; // avalon_st_adapter_007:out_0_error -> onchip_memory2_0_s1_agent:rdata_fifo_sink_error
wire uart_0_s1_agent_rdata_fifo_src_valid; // uart_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_008:in_0_valid
wire [33:0] uart_0_s1_agent_rdata_fifo_src_data; // uart_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_008:in_0_data
wire uart_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_008:in_0_ready -> uart_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_008_out_0_valid; // avalon_st_adapter_008:out_0_valid -> uart_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_008_out_0_data; // avalon_st_adapter_008:out_0_data -> uart_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_008_out_0_ready; // uart_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_008:out_0_ready
wire [0:0] avalon_st_adapter_008_out_0_error; // avalon_st_adapter_008:out_0_error -> uart_0_s1_agent:rdata_fifo_sink_error
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_009:in_0_valid
wire [33:0] nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_009:in_0_data
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_009:in_0_ready -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_009_out_0_valid; // avalon_st_adapter_009:out_0_valid -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_009_out_0_data; // avalon_st_adapter_009:out_0_data -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_009_out_0_ready; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_009:out_0_ready
wire [0:0] avalon_st_adapter_009_out_0_error; // avalon_st_adapter_009:out_0_error -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) nios2_gen2_0_data_master_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.av_read (nios2_gen2_0_data_master_read), // .read
.av_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.av_write (nios2_gen2_0_data_master_write), // .write
.av_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_gen2_0_instruction_master_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_gen2_0_instruction_master_read), // .read
.av_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) buffered_spi_0_avalon_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (buffered_spi_0_avalon_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (buffered_spi_0_avalon_agent_m0_burstcount), // .burstcount
.uav_read (buffered_spi_0_avalon_agent_m0_read), // .read
.uav_write (buffered_spi_0_avalon_agent_m0_write), // .write
.uav_waitrequest (buffered_spi_0_avalon_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (buffered_spi_0_avalon_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (buffered_spi_0_avalon_agent_m0_byteenable), // .byteenable
.uav_readdata (buffered_spi_0_avalon_agent_m0_readdata), // .readdata
.uav_writedata (buffered_spi_0_avalon_agent_m0_writedata), // .writedata
.uav_lock (buffered_spi_0_avalon_agent_m0_lock), // .lock
.uav_debugaccess (buffered_spi_0_avalon_agent_m0_debugaccess), // .debugaccess
.av_address (buffered_spi_0_avalon_address), // avalon_anti_slave_0.address
.av_write (buffered_spi_0_avalon_write), // .write
.av_read (buffered_spi_0_avalon_read), // .read
.av_readdata (buffered_spi_0_avalon_readdata), // .readdata
.av_writedata (buffered_spi_0_avalon_writedata), // .writedata
.av_readdatavalid (buffered_spi_0_avalon_readdatavalid), // .readdatavalid
.av_waitrequest (buffered_spi_0_avalon_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) audio_0_avalon_audio_slave_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (audio_0_avalon_audio_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (audio_0_avalon_audio_slave_agent_m0_burstcount), // .burstcount
.uav_read (audio_0_avalon_audio_slave_agent_m0_read), // .read
.uav_write (audio_0_avalon_audio_slave_agent_m0_write), // .write
.uav_waitrequest (audio_0_avalon_audio_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (audio_0_avalon_audio_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (audio_0_avalon_audio_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (audio_0_avalon_audio_slave_agent_m0_readdata), // .readdata
.uav_writedata (audio_0_avalon_audio_slave_agent_m0_writedata), // .writedata
.uav_lock (audio_0_avalon_audio_slave_agent_m0_lock), // .lock
.uav_debugaccess (audio_0_avalon_audio_slave_agent_m0_debugaccess), // .debugaccess
.av_address (audio_0_avalon_audio_slave_address), // avalon_anti_slave_0.address
.av_write (audio_0_avalon_audio_slave_write), // .write
.av_read (audio_0_avalon_audio_slave_read), // .read
.av_readdata (audio_0_avalon_audio_slave_readdata), // .readdata
.av_writedata (audio_0_avalon_audio_slave_writedata), // .writedata
.av_chipselect (audio_0_avalon_audio_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) abus_avalon_sdram_bridge_0_avalon_regs_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_burstcount), // .burstcount
.uav_read (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_read), // .read
.uav_write (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_write), // .write
.uav_waitrequest (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_byteenable), // .byteenable
.uav_readdata (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_readdata), // .readdata
.uav_writedata (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_writedata), // .writedata
.uav_lock (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_lock), // .lock
.uav_debugaccess (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_debugaccess), // .debugaccess
.av_address (abus_avalon_sdram_bridge_0_avalon_regs_address), // avalon_anti_slave_0.address
.av_write (abus_avalon_sdram_bridge_0_avalon_regs_write), // .write
.av_read (abus_avalon_sdram_bridge_0_avalon_regs_read), // .read
.av_readdata (abus_avalon_sdram_bridge_0_avalon_regs_readdata), // .readdata
.av_writedata (abus_avalon_sdram_bridge_0_avalon_regs_writedata), // .writedata
.av_readdatavalid (abus_avalon_sdram_bridge_0_avalon_regs_readdatavalid), // .readdatavalid
.av_waitrequest (abus_avalon_sdram_bridge_0_avalon_regs_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_burstcount), // .burstcount
.uav_read (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_read), // .read
.uav_write (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_write), // .write
.uav_waitrequest (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_readdata), // .readdata
.uav_writedata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_writedata), // .writedata
.uav_lock (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_lock), // .lock
.uav_debugaccess (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_debugaccess), // .debugaccess
.av_address (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address), // avalon_anti_slave_0.address
.av_write (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write), // .write
.av_read (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read), // .read
.av_readdata (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata), // .readdata
.av_writedata (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata), // .writedata
.av_byteenable (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable), // .byteenable
.av_waitrequest (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest), // .waitrequest
.av_chipselect (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (26),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (1),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (25),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) abus_avalon_sdram_bridge_0_avalon_sdram_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_burstcount), // .burstcount
.uav_read (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_read), // .read
.uav_write (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_write), // .write
.uav_waitrequest (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_byteenable), // .byteenable
.uav_readdata (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_readdata), // .readdata
.uav_writedata (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_writedata), // .writedata
.uav_lock (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_lock), // .lock
.uav_debugaccess (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_debugaccess), // .debugaccess
.av_address (abus_avalon_sdram_bridge_0_avalon_sdram_address), // avalon_anti_slave_0.address
.av_write (abus_avalon_sdram_bridge_0_avalon_sdram_write), // .write
.av_read (abus_avalon_sdram_bridge_0_avalon_sdram_read), // .read
.av_readdata (abus_avalon_sdram_bridge_0_avalon_sdram_readdata), // .readdata
.av_writedata (abus_avalon_sdram_bridge_0_avalon_sdram_writedata), // .writedata
.av_byteenable (abus_avalon_sdram_bridge_0_avalon_sdram_byteenable), // .byteenable
.av_readdatavalid (abus_avalon_sdram_bridge_0_avalon_sdram_readdatavalid), // .readdatavalid
.av_waitrequest (abus_avalon_sdram_bridge_0_avalon_sdram_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (16),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (4),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (6),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_flash_0_data_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_flash_0_data_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_flash_0_data_agent_m0_burstcount), // .burstcount
.uav_read (onchip_flash_0_data_agent_m0_read), // .read
.uav_write (onchip_flash_0_data_agent_m0_write), // .write
.uav_waitrequest (onchip_flash_0_data_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_flash_0_data_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_flash_0_data_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_flash_0_data_agent_m0_readdata), // .readdata
.uav_writedata (onchip_flash_0_data_agent_m0_writedata), // .writedata
.uav_lock (onchip_flash_0_data_agent_m0_lock), // .lock
.uav_debugaccess (onchip_flash_0_data_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_flash_0_data_address), // avalon_anti_slave_0.address
.av_read (onchip_flash_0_data_read), // .read
.av_readdata (onchip_flash_0_data_readdata), // .readdata
.av_burstcount (onchip_flash_0_data_burstcount), // .burstcount
.av_readdatavalid (onchip_flash_0_data_readdatavalid), // .readdatavalid
.av_waitrequest (onchip_flash_0_data_waitrequest), // .waitrequest
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_byteenable (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) altpll_1_pll_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (altpll_1_pll_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (altpll_1_pll_slave_agent_m0_burstcount), // .burstcount
.uav_read (altpll_1_pll_slave_agent_m0_read), // .read
.uav_write (altpll_1_pll_slave_agent_m0_write), // .write
.uav_waitrequest (altpll_1_pll_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (altpll_1_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (altpll_1_pll_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (altpll_1_pll_slave_agent_m0_readdata), // .readdata
.uav_writedata (altpll_1_pll_slave_agent_m0_writedata), // .writedata
.uav_lock (altpll_1_pll_slave_agent_m0_lock), // .lock
.uav_debugaccess (altpll_1_pll_slave_agent_m0_debugaccess), // .debugaccess
.av_address (altpll_1_pll_slave_address), // avalon_anti_slave_0.address
.av_write (altpll_1_pll_slave_write), // .write
.av_read (altpll_1_pll_slave_read), // .read
.av_readdata (altpll_1_pll_slave_readdata), // .readdata
.av_writedata (altpll_1_pll_slave_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (12),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_write), // .write
.av_readdata (onchip_memory2_0_s1_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) uart_0_s1_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (uart_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (uart_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (uart_0_s1_agent_m0_read), // .read
.uav_write (uart_0_s1_agent_m0_write), // .write
.uav_waitrequest (uart_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (uart_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (uart_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (uart_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (uart_0_s1_agent_m0_writedata), // .writedata
.uav_lock (uart_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (uart_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (uart_0_s1_address), // avalon_anti_slave_0.address
.av_write (uart_0_s1_write), // .write
.av_read (uart_0_s1_read), // .read
.av_readdata (uart_0_s1_readdata), // .readdata
.av_writedata (uart_0_s1_writedata), // .writedata
.av_begintransfer (uart_0_s1_begintransfer), // .begintransfer
.av_chipselect (uart_0_s1_chipselect), // .chipselect
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_gen2_0_debug_mem_slave_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.uav_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (nios2_gen2_0_debug_mem_slave_write), // .write
.av_read (nios2_gen2_0_debug_mem_slave_read), // .read
.av_readdata (nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.av_writedata (nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.av_byteenable (nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_QOS_H (86),
.PKT_QOS_L (86),
.PKT_DATA_SIDEBAND_H (84),
.PKT_DATA_SIDEBAND_L (84),
.PKT_ADDR_SIDEBAND_H (83),
.PKT_ADDR_SIDEBAND_L (83),
.PKT_BURST_TYPE_H (82),
.PKT_BURST_TYPE_L (81),
.PKT_CACHE_H (102),
.PKT_CACHE_L (99),
.PKT_THREAD_ID_H (95),
.PKT_THREAD_ID_L (95),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_EXCLUSIVE (68),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.ST_DATA_W (108),
.ST_CHANNEL_W (10),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_data_master_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_QOS_H (86),
.PKT_QOS_L (86),
.PKT_DATA_SIDEBAND_H (84),
.PKT_DATA_SIDEBAND_L (84),
.PKT_ADDR_SIDEBAND_H (83),
.PKT_ADDR_SIDEBAND_L (83),
.PKT_BURST_TYPE_H (82),
.PKT_BURST_TYPE_L (81),
.PKT_CACHE_H (102),
.PKT_CACHE_L (99),
.PKT_THREAD_ID_H (95),
.PKT_THREAD_ID_L (95),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_EXCLUSIVE (68),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.ST_DATA_W (108),
.ST_CHANNEL_W (10),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_instruction_master_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (89),
.PKT_ORI_BURST_SIZE_L (87),
.PKT_RESPONSE_STATUS_H (86),
.PKT_RESPONSE_STATUS_L (85),
.PKT_BURST_SIZE_H (62),
.PKT_BURST_SIZE_L (60),
.PKT_TRANS_LOCK (49),
.PKT_BEGIN_BURST (67),
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BURSTWRAP_H (59),
.PKT_BURSTWRAP_L (57),
.PKT_BYTE_CNT_H (56),
.PKT_BYTE_CNT_L (51),
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_POSTED (46),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (69),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (73),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (90),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) buffered_spi_0_avalon_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (buffered_spi_0_avalon_agent_m0_address), // m0.address
.m0_burstcount (buffered_spi_0_avalon_agent_m0_burstcount), // .burstcount
.m0_byteenable (buffered_spi_0_avalon_agent_m0_byteenable), // .byteenable
.m0_debugaccess (buffered_spi_0_avalon_agent_m0_debugaccess), // .debugaccess
.m0_lock (buffered_spi_0_avalon_agent_m0_lock), // .lock
.m0_readdata (buffered_spi_0_avalon_agent_m0_readdata), // .readdata
.m0_readdatavalid (buffered_spi_0_avalon_agent_m0_readdatavalid), // .readdatavalid
.m0_read (buffered_spi_0_avalon_agent_m0_read), // .read
.m0_waitrequest (buffered_spi_0_avalon_agent_m0_waitrequest), // .waitrequest
.m0_writedata (buffered_spi_0_avalon_agent_m0_writedata), // .writedata
.m0_write (buffered_spi_0_avalon_agent_m0_write), // .write
.rp_endofpacket (buffered_spi_0_avalon_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (buffered_spi_0_avalon_agent_rp_ready), // .ready
.rp_valid (buffered_spi_0_avalon_agent_rp_valid), // .valid
.rp_data (buffered_spi_0_avalon_agent_rp_data), // .data
.rp_startofpacket (buffered_spi_0_avalon_agent_rp_startofpacket), // .startofpacket
.cp_ready (buffered_spi_0_avalon_burst_adapter_source0_ready), // cp.ready
.cp_valid (buffered_spi_0_avalon_burst_adapter_source0_valid), // .valid
.cp_data (buffered_spi_0_avalon_burst_adapter_source0_data), // .data
.cp_startofpacket (buffered_spi_0_avalon_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (buffered_spi_0_avalon_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (buffered_spi_0_avalon_burst_adapter_source0_channel), // .channel
.rf_sink_ready (buffered_spi_0_avalon_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (buffered_spi_0_avalon_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (buffered_spi_0_avalon_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (buffered_spi_0_avalon_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (buffered_spi_0_avalon_agent_rsp_fifo_out_data), // .data
.rf_source_ready (buffered_spi_0_avalon_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (buffered_spi_0_avalon_agent_rf_source_valid), // .valid
.rf_source_startofpacket (buffered_spi_0_avalon_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (buffered_spi_0_avalon_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (buffered_spi_0_avalon_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (buffered_spi_0_avalon_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (buffered_spi_0_avalon_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (buffered_spi_0_avalon_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (91),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) buffered_spi_0_avalon_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (buffered_spi_0_avalon_agent_rf_source_data), // in.data
.in_valid (buffered_spi_0_avalon_agent_rf_source_valid), // .valid
.in_ready (buffered_spi_0_avalon_agent_rf_source_ready), // .ready
.in_startofpacket (buffered_spi_0_avalon_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (buffered_spi_0_avalon_agent_rf_source_endofpacket), // .endofpacket
.out_data (buffered_spi_0_avalon_agent_rsp_fifo_out_data), // out.data
.out_valid (buffered_spi_0_avalon_agent_rsp_fifo_out_valid), // .valid
.out_ready (buffered_spi_0_avalon_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (buffered_spi_0_avalon_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (buffered_spi_0_avalon_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) audio_0_avalon_audio_slave_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (audio_0_avalon_audio_slave_agent_m0_address), // m0.address
.m0_burstcount (audio_0_avalon_audio_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (audio_0_avalon_audio_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (audio_0_avalon_audio_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (audio_0_avalon_audio_slave_agent_m0_lock), // .lock
.m0_readdata (audio_0_avalon_audio_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (audio_0_avalon_audio_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (audio_0_avalon_audio_slave_agent_m0_read), // .read
.m0_waitrequest (audio_0_avalon_audio_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (audio_0_avalon_audio_slave_agent_m0_writedata), // .writedata
.m0_write (audio_0_avalon_audio_slave_agent_m0_write), // .write
.rp_endofpacket (audio_0_avalon_audio_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (audio_0_avalon_audio_slave_agent_rp_ready), // .ready
.rp_valid (audio_0_avalon_audio_slave_agent_rp_valid), // .valid
.rp_data (audio_0_avalon_audio_slave_agent_rp_data), // .data
.rp_startofpacket (audio_0_avalon_audio_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (audio_0_avalon_audio_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (audio_0_avalon_audio_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (audio_0_avalon_audio_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (audio_0_avalon_audio_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (audio_0_avalon_audio_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (audio_0_avalon_audio_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (audio_0_avalon_audio_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (audio_0_avalon_audio_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (audio_0_avalon_audio_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (audio_0_avalon_audio_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (audio_0_avalon_audio_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (audio_0_avalon_audio_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (audio_0_avalon_audio_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) audio_0_avalon_audio_slave_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (audio_0_avalon_audio_slave_agent_rf_source_data), // in.data
.in_valid (audio_0_avalon_audio_slave_agent_rf_source_valid), // .valid
.in_ready (audio_0_avalon_audio_slave_agent_rf_source_ready), // .ready
.in_startofpacket (audio_0_avalon_audio_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (audio_0_avalon_audio_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (audio_0_avalon_audio_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (audio_0_avalon_audio_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (audio_0_avalon_audio_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (audio_0_avalon_audio_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (audio_0_avalon_audio_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (89),
.PKT_ORI_BURST_SIZE_L (87),
.PKT_RESPONSE_STATUS_H (86),
.PKT_RESPONSE_STATUS_L (85),
.PKT_BURST_SIZE_H (62),
.PKT_BURST_SIZE_L (60),
.PKT_TRANS_LOCK (49),
.PKT_BEGIN_BURST (67),
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BURSTWRAP_H (59),
.PKT_BURSTWRAP_L (57),
.PKT_BYTE_CNT_H (56),
.PKT_BYTE_CNT_L (51),
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_POSTED (46),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (69),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (73),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (90),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) abus_avalon_sdram_bridge_0_avalon_regs_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_address), // m0.address
.m0_burstcount (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_burstcount), // .burstcount
.m0_byteenable (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_byteenable), // .byteenable
.m0_debugaccess (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_debugaccess), // .debugaccess
.m0_lock (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_lock), // .lock
.m0_readdata (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_readdata), // .readdata
.m0_readdatavalid (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_readdatavalid), // .readdatavalid
.m0_read (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_read), // .read
.m0_waitrequest (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_waitrequest), // .waitrequest
.m0_writedata (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_writedata), // .writedata
.m0_write (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_write), // .write
.rp_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_ready), // .ready
.rp_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_valid), // .valid
.rp_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_data), // .data
.rp_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_startofpacket), // .startofpacket
.cp_ready (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_ready), // cp.ready
.cp_valid (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_valid), // .valid
.cp_data (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_data), // .data
.cp_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_channel), // .channel
.rf_sink_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_data), // .data
.rf_source_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_valid), // .valid
.rf_source_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (91),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_data), // in.data
.in_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_valid), // .valid
.in_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_ready), // .ready
.in_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_endofpacket), // .endofpacket
.out_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_data), // out.data
.out_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_valid), // .valid
.out_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_address), // m0.address
.m0_burstcount (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_lock), // .lock
.m0_readdata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_read), // .read
.m0_waitrequest (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_writedata), // .writedata
.m0_write (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_write), // .write
.rp_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_ready), // .ready
.rp_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_valid), // .valid
.rp_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_data), // .data
.rp_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_data), // in.data
.in_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_valid), // .valid
.in_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_ready), // .ready
.in_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (89),
.PKT_ORI_BURST_SIZE_L (87),
.PKT_RESPONSE_STATUS_H (86),
.PKT_RESPONSE_STATUS_L (85),
.PKT_BURST_SIZE_H (62),
.PKT_BURST_SIZE_L (60),
.PKT_TRANS_LOCK (49),
.PKT_BEGIN_BURST (67),
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BURSTWRAP_H (59),
.PKT_BURSTWRAP_L (57),
.PKT_BYTE_CNT_H (56),
.PKT_BYTE_CNT_L (51),
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_POSTED (46),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (69),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (73),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (90),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) abus_avalon_sdram_bridge_0_avalon_sdram_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_address), // m0.address
.m0_burstcount (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_burstcount), // .burstcount
.m0_byteenable (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_byteenable), // .byteenable
.m0_debugaccess (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_debugaccess), // .debugaccess
.m0_lock (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_lock), // .lock
.m0_readdata (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_readdata), // .readdata
.m0_readdatavalid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_readdatavalid), // .readdatavalid
.m0_read (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_read), // .read
.m0_waitrequest (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_waitrequest), // .waitrequest
.m0_writedata (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_writedata), // .writedata
.m0_write (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_write), // .write
.rp_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_ready), // .ready
.rp_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_valid), // .valid
.rp_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_data), // .data
.rp_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_startofpacket), // .startofpacket
.cp_ready (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_ready), // cp.ready
.cp_valid (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_valid), // .valid
.cp_data (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_data), // .data
.cp_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_channel), // .channel
.rf_sink_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_data), // .data
.rf_source_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_valid), // .valid
.rf_source_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (91),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_data), // in.data
.in_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_valid), // .valid
.in_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_ready), // .ready
.in_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_endofpacket), // .endofpacket
.out_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_data), // out.data
.out_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_valid), // .valid
.out_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (6),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_flash_0_data_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_flash_0_data_agent_m0_address), // m0.address
.m0_burstcount (onchip_flash_0_data_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_flash_0_data_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_flash_0_data_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_flash_0_data_agent_m0_lock), // .lock
.m0_readdata (onchip_flash_0_data_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_flash_0_data_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_flash_0_data_agent_m0_read), // .read
.m0_waitrequest (onchip_flash_0_data_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_flash_0_data_agent_m0_writedata), // .writedata
.m0_write (onchip_flash_0_data_agent_m0_write), // .write
.rp_endofpacket (onchip_flash_0_data_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_flash_0_data_agent_rp_ready), // .ready
.rp_valid (onchip_flash_0_data_agent_rp_valid), // .valid
.rp_data (onchip_flash_0_data_agent_rp_data), // .data
.rp_startofpacket (onchip_flash_0_data_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (onchip_flash_0_data_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_flash_0_data_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_flash_0_data_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_flash_0_data_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_flash_0_data_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_flash_0_data_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_flash_0_data_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_flash_0_data_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_flash_0_data_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_flash_0_data_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error
.rdata_fifo_src_ready (onchip_flash_0_data_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_flash_0_data_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_flash_0_data_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_flash_0_data_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_flash_0_data_agent_rf_source_data), // in.data
.in_valid (onchip_flash_0_data_agent_rf_source_valid), // .valid
.in_ready (onchip_flash_0_data_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_flash_0_data_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_flash_0_data_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_flash_0_data_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_flash_0_data_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_flash_0_data_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_flash_0_data_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_flash_0_data_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) altpll_1_pll_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (altpll_1_pll_slave_agent_m0_address), // m0.address
.m0_burstcount (altpll_1_pll_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (altpll_1_pll_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (altpll_1_pll_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (altpll_1_pll_slave_agent_m0_lock), // .lock
.m0_readdata (altpll_1_pll_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (altpll_1_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (altpll_1_pll_slave_agent_m0_read), // .read
.m0_waitrequest (altpll_1_pll_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (altpll_1_pll_slave_agent_m0_writedata), // .writedata
.m0_write (altpll_1_pll_slave_agent_m0_write), // .write
.rp_endofpacket (altpll_1_pll_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (altpll_1_pll_slave_agent_rp_ready), // .ready
.rp_valid (altpll_1_pll_slave_agent_rp_valid), // .valid
.rp_data (altpll_1_pll_slave_agent_rp_data), // .data
.rp_startofpacket (altpll_1_pll_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (altpll_1_pll_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (altpll_1_pll_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (altpll_1_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (altpll_1_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (altpll_1_pll_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (altpll_1_pll_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (altpll_1_pll_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (altpll_1_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (altpll_1_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (altpll_1_pll_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_006_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_006_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_006_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_006_out_0_error), // .error
.rdata_fifo_src_ready (altpll_1_pll_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (altpll_1_pll_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (altpll_1_pll_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altpll_1_pll_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (altpll_1_pll_slave_agent_rf_source_data), // in.data
.in_valid (altpll_1_pll_slave_agent_rf_source_valid), // .valid
.in_ready (altpll_1_pll_slave_agent_rf_source_ready), // .ready
.in_startofpacket (altpll_1_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (altpll_1_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (altpll_1_pll_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (altpll_1_pll_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (altpll_1_pll_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (altpll_1_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (altpll_1_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altpll_1_pll_slave_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (altpll_1_pll_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (altpll_1_pll_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (altpll_1_pll_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (altpll_1_pll_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (altpll_1_pll_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (altpll_1_pll_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_memory2_0_s1_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_007_src_ready), // cp.ready
.cp_valid (cmd_mux_007_src_valid), // .valid
.cp_data (cmd_mux_007_src_data), // .data
.cp_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_007_src_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_007_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_007_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_007_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_007_out_0_error), // .error
.rdata_fifo_src_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) uart_0_s1_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (uart_0_s1_agent_m0_address), // m0.address
.m0_burstcount (uart_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (uart_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (uart_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (uart_0_s1_agent_m0_lock), // .lock
.m0_readdata (uart_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (uart_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (uart_0_s1_agent_m0_read), // .read
.m0_waitrequest (uart_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (uart_0_s1_agent_m0_writedata), // .writedata
.m0_write (uart_0_s1_agent_m0_write), // .write
.rp_endofpacket (uart_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (uart_0_s1_agent_rp_ready), // .ready
.rp_valid (uart_0_s1_agent_rp_valid), // .valid
.rp_data (uart_0_s1_agent_rp_data), // .data
.rp_startofpacket (uart_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_008_src_ready), // cp.ready
.cp_valid (cmd_mux_008_src_valid), // .valid
.cp_data (cmd_mux_008_src_data), // .data
.cp_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_008_src_channel), // .channel
.rf_sink_ready (uart_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (uart_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (uart_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (uart_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (uart_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (uart_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (uart_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (uart_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (uart_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (uart_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_008_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_008_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_008_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_008_out_0_error), // .error
.rdata_fifo_src_ready (uart_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (uart_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (uart_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) uart_0_s1_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (uart_0_s1_agent_rf_source_data), // in.data
.in_valid (uart_0_s1_agent_rf_source_valid), // .valid
.in_ready (uart_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (uart_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (uart_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (uart_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (uart_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (uart_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (uart_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (uart_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) nios2_gen2_0_debug_mem_slave_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_009_src_ready), // cp.ready
.cp_valid (cmd_mux_009_src_valid), // .valid
.cp_data (cmd_mux_009_src_data), // .data
.cp_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_009_src_channel), // .channel
.rf_sink_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_009_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_009_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_009_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_009_out_0_error), // .error
.rdata_fifo_src_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_gen2_0_debug_mem_slave_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
wasca_mm_interconnect_0_router router (
.sink_ready (nios2_gen2_0_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_data_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_001 router_001 (
.sink_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_002 router_002 (
.sink_ready (buffered_spi_0_avalon_agent_rp_ready), // sink.ready
.sink_valid (buffered_spi_0_avalon_agent_rp_valid), // .valid
.sink_data (buffered_spi_0_avalon_agent_rp_data), // .data
.sink_startofpacket (buffered_spi_0_avalon_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (buffered_spi_0_avalon_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_003 router_003 (
.sink_ready (audio_0_avalon_audio_slave_agent_rp_ready), // sink.ready
.sink_valid (audio_0_avalon_audio_slave_agent_rp_valid), // .valid
.sink_data (audio_0_avalon_audio_slave_agent_rp_data), // .data
.sink_startofpacket (audio_0_avalon_audio_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (audio_0_avalon_audio_slave_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_002 router_004 (
.sink_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_ready), // sink.ready
.sink_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_valid), // .valid
.sink_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_data), // .data
.sink_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_003 router_005 (
.sink_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_ready), // sink.ready
.sink_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_valid), // .valid
.sink_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_data), // .data
.sink_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_002 router_006 (
.sink_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_ready), // sink.ready
.sink_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_valid), // .valid
.sink_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_data), // .data
.sink_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_007 router_007 (
.sink_ready (onchip_flash_0_data_agent_rp_ready), // sink.ready
.sink_valid (onchip_flash_0_data_agent_rp_valid), // .valid
.sink_data (onchip_flash_0_data_agent_rp_data), // .data
.sink_startofpacket (onchip_flash_0_data_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_flash_0_data_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_003 router_008 (
.sink_ready (altpll_1_pll_slave_agent_rp_ready), // sink.ready
.sink_valid (altpll_1_pll_slave_agent_rp_valid), // .valid
.sink_data (altpll_1_pll_slave_agent_rp_data), // .data
.sink_startofpacket (altpll_1_pll_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (altpll_1_pll_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_007 router_009 (
.sink_ready (onchip_memory2_0_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_009_src_ready), // src.ready
.src_valid (router_009_src_valid), // .valid
.src_data (router_009_src_data), // .data
.src_channel (router_009_src_channel), // .channel
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_003 router_010 (
.sink_ready (uart_0_s1_agent_rp_ready), // sink.ready
.sink_valid (uart_0_s1_agent_rp_valid), // .valid
.sink_data (uart_0_s1_agent_rp_data), // .data
.sink_startofpacket (uart_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (uart_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_010_src_ready), // src.ready
.src_valid (router_010_src_valid), // .valid
.src_data (router_010_src_data), // .data
.src_channel (router_010_src_channel), // .channel
.src_startofpacket (router_010_src_startofpacket), // .startofpacket
.src_endofpacket (router_010_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_011 router_011 (
.sink_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_011_src_ready), // src.ready
.src_valid (router_011_src_valid), // .valid
.src_data (router_011_src_data), // .data
.src_channel (router_011_src_channel), // .channel
.src_startofpacket (router_011_src_startofpacket), // .startofpacket
.src_endofpacket (router_011_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (67),
.PKT_BYTE_CNT_H (56),
.PKT_BYTE_CNT_L (51),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (62),
.PKT_BURST_SIZE_L (60),
.PKT_BURST_TYPE_H (64),
.PKT_BURST_TYPE_L (63),
.PKT_BURSTWRAP_H (59),
.PKT_BURSTWRAP_L (57),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (90),
.ST_CHANNEL_W (10),
.OUT_BYTE_CNT_H (52),
.OUT_BURSTWRAP_H (59),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (7),
.BURSTWRAP_CONST_VALUE (7),
.ADAPTER_VERSION ("13.1")
) buffered_spi_0_avalon_burst_adapter (
.clk (altpll_1_c0_clk), // cr0.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (buffered_spi_0_avalon_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (buffered_spi_0_avalon_cmd_width_adapter_src_data), // .data
.sink0_channel (buffered_spi_0_avalon_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (buffered_spi_0_avalon_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (buffered_spi_0_avalon_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (buffered_spi_0_avalon_cmd_width_adapter_src_ready), // .ready
.source0_valid (buffered_spi_0_avalon_burst_adapter_source0_valid), // source0.valid
.source0_data (buffered_spi_0_avalon_burst_adapter_source0_data), // .data
.source0_channel (buffered_spi_0_avalon_burst_adapter_source0_channel), // .channel
.source0_startofpacket (buffered_spi_0_avalon_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (buffered_spi_0_avalon_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (buffered_spi_0_avalon_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (67),
.PKT_BYTE_CNT_H (56),
.PKT_BYTE_CNT_L (51),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (62),
.PKT_BURST_SIZE_L (60),
.PKT_BURST_TYPE_H (64),
.PKT_BURST_TYPE_L (63),
.PKT_BURSTWRAP_H (59),
.PKT_BURSTWRAP_L (57),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (90),
.ST_CHANNEL_W (10),
.OUT_BYTE_CNT_H (52),
.OUT_BURSTWRAP_H (59),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (7),
.BURSTWRAP_CONST_VALUE (7),
.ADAPTER_VERSION ("13.1")
) abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter (
.clk (altpll_1_c0_clk), // cr0.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_data), // .data
.sink0_channel (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_ready), // .ready
.source0_valid (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_valid), // source0.valid
.source0_data (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_data), // .data
.source0_channel (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_channel), // .channel
.source0_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (67),
.PKT_BYTE_CNT_H (56),
.PKT_BYTE_CNT_L (51),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (62),
.PKT_BURST_SIZE_L (60),
.PKT_BURST_TYPE_H (64),
.PKT_BURST_TYPE_L (63),
.PKT_BURSTWRAP_H (59),
.PKT_BURSTWRAP_L (57),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (90),
.ST_CHANNEL_W (10),
.OUT_BYTE_CNT_H (51),
.OUT_BURSTWRAP_H (59),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (7),
.BURSTWRAP_CONST_VALUE (7),
.ADAPTER_VERSION ("13.1")
) abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter (
.clk (altpll_1_c0_clk), // cr0.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_data), // .data
.sink0_channel (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_ready), // .ready
.source0_valid (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_valid), // source0.valid
.source0_data (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_data), // .data
.source0_channel (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_channel), // .channel
.source0_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_ready) // .ready
);
wasca_mm_interconnect_0_cmd_demux cmd_demux (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.src7_ready (cmd_demux_src7_ready), // src7.ready
.src7_valid (cmd_demux_src7_valid), // .valid
.src7_data (cmd_demux_src7_data), // .data
.src7_channel (cmd_demux_src7_channel), // .channel
.src7_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
.src8_ready (cmd_demux_src8_ready), // src8.ready
.src8_valid (cmd_demux_src8_valid), // .valid
.src8_data (cmd_demux_src8_data), // .data
.src8_channel (cmd_demux_src8_channel), // .channel
.src8_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
.src8_endofpacket (cmd_demux_src8_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux (
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux_002 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux_003 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_005 cmd_mux_005 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_005 cmd_mux_007 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_007_src_ready), // src.ready
.src_valid (cmd_mux_007_src_valid), // .valid
.src_data (cmd_mux_007_src_data), // .data
.src_channel (cmd_mux_007_src_channel), // .channel
.src_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src7_ready), // sink0.ready
.sink0_valid (cmd_demux_src7_valid), // .valid
.sink0_channel (cmd_demux_src7_channel), // .channel
.sink0_data (cmd_demux_src7_data), // .data
.sink0_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux_008 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_008_src_ready), // src.ready
.src_valid (cmd_mux_008_src_valid), // .valid
.src_data (cmd_mux_008_src_data), // .data
.src_channel (cmd_mux_008_src_channel), // .channel
.src_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src8_ready), // sink0.ready
.sink0_valid (cmd_demux_src8_valid), // .valid
.sink0_channel (cmd_demux_src8_channel), // .channel
.sink0_data (cmd_demux_src8_data), // .data
.sink0_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src8_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux_009 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_009_src_ready), // src.ready
.src_valid (cmd_mux_009_src_valid), // .valid
.src_data (cmd_mux_009_src_data), // .data
.src_channel (cmd_mux_009_src_channel), // .channel
.src_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src2_valid), // .valid
.sink0_channel (cmd_demux_001_src2_channel), // .channel
.sink0_data (cmd_demux_001_src2_data), // .data
.sink0_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux (
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (buffered_spi_0_avalon_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (buffered_spi_0_avalon_rsp_width_adapter_src_channel), // .channel
.sink_data (buffered_spi_0_avalon_rsp_width_adapter_src_data), // .data
.sink_startofpacket (buffered_spi_0_avalon_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (buffered_spi_0_avalon_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (buffered_spi_0_avalon_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux_002 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_channel), // .channel
.sink_data (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_data), // .data
.sink_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux_003 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_channel), // .channel
.sink_data (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_data), // .data
.sink_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_005 rsp_demux_005 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_005_src1_ready), // src1.ready
.src1_valid (rsp_demux_005_src1_valid), // .valid
.src1_data (rsp_demux_005_src1_data), // .data
.src1_channel (rsp_demux_005_src1_channel), // .channel
.src1_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_005_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_006 rsp_demux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_005 rsp_demux_007 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_009_src_ready), // sink.ready
.sink_channel (router_009_src_channel), // .channel
.sink_data (router_009_src_data), // .data
.sink_startofpacket (router_009_src_startofpacket), // .startofpacket
.sink_endofpacket (router_009_src_endofpacket), // .endofpacket
.sink_valid (router_009_src_valid), // .valid
.src0_ready (rsp_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_demux_007_src0_valid), // .valid
.src0_data (rsp_demux_007_src0_data), // .data
.src0_channel (rsp_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_007_src1_ready), // src1.ready
.src1_valid (rsp_demux_007_src1_valid), // .valid
.src1_data (rsp_demux_007_src1_data), // .data
.src1_channel (rsp_demux_007_src1_channel), // .channel
.src1_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_007_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux_008 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_010_src_ready), // sink.ready
.sink_channel (router_010_src_channel), // .channel
.sink_data (router_010_src_data), // .data
.sink_startofpacket (router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (router_010_src_endofpacket), // .endofpacket
.sink_valid (router_010_src_valid), // .valid
.src0_ready (rsp_demux_008_src0_ready), // src0.ready
.src0_valid (rsp_demux_008_src0_valid), // .valid
.src0_data (rsp_demux_008_src0_data), // .data
.src0_channel (rsp_demux_008_src0_channel), // .channel
.src0_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_008_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux_009 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_011_src_ready), // sink.ready
.sink_channel (router_011_src_channel), // .channel
.sink_data (router_011_src_data), // .data
.sink_startofpacket (router_011_src_startofpacket), // .startofpacket
.sink_endofpacket (router_011_src_endofpacket), // .endofpacket
.sink_valid (router_011_src_valid), // .valid
.src0_ready (rsp_demux_009_src0_ready), // src0.ready
.src0_valid (rsp_demux_009_src0_valid), // .valid
.src0_data (rsp_demux_009_src0_data), // .data
.src0_channel (rsp_demux_009_src0_channel), // .channel
.src0_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_009_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_mux rsp_mux (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (crosser_001_out_ready), // sink6.ready
.sink6_valid (crosser_001_out_valid), // .valid
.sink6_channel (crosser_001_out_channel), // .channel
.sink6_data (crosser_001_out_data), // .data
.sink6_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink6_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.sink7_ready (rsp_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_demux_007_src0_valid), // .valid
.sink7_channel (rsp_demux_007_src0_channel), // .channel
.sink7_data (rsp_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.sink8_ready (rsp_demux_008_src0_ready), // sink8.ready
.sink8_valid (rsp_demux_008_src0_valid), // .valid
.sink8_channel (rsp_demux_008_src0_channel), // .channel
.sink8_data (rsp_demux_008_src0_data), // .data
.sink8_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.sink8_endofpacket (rsp_demux_008_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_005_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_005_src1_valid), // .valid
.sink0_channel (rsp_demux_005_src1_channel), // .channel
.sink0_data (rsp_demux_005_src1_data), // .data
.sink0_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_005_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_007_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_007_src1_valid), // .valid
.sink1_channel (rsp_demux_007_src1_channel), // .channel
.sink1_data (rsp_demux_007_src1_data), // .data
.sink1_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_007_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_009_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_009_src0_valid), // .valid
.sink2_channel (rsp_demux_009_src0_channel), // .channel
.sink2_data (rsp_demux_009_src0_data), // .data
.sink2_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_009_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (44),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (56),
.IN_PKT_BYTE_CNT_L (51),
.IN_PKT_TRANS_COMPRESSED_READ (45),
.IN_PKT_TRANS_WRITE (47),
.IN_PKT_BURSTWRAP_H (59),
.IN_PKT_BURSTWRAP_L (57),
.IN_PKT_BURST_SIZE_H (62),
.IN_PKT_BURST_SIZE_L (60),
.IN_PKT_RESPONSE_STATUS_H (86),
.IN_PKT_RESPONSE_STATUS_L (85),
.IN_PKT_TRANS_EXCLUSIVE (50),
.IN_PKT_BURST_TYPE_H (64),
.IN_PKT_BURST_TYPE_L (63),
.IN_PKT_ORI_BURST_SIZE_L (87),
.IN_PKT_ORI_BURST_SIZE_H (89),
.IN_ST_DATA_W (90),
.OUT_PKT_ADDR_H (62),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (74),
.OUT_PKT_BYTE_CNT_L (69),
.OUT_PKT_TRANS_COMPRESSED_READ (63),
.OUT_PKT_BURST_SIZE_H (80),
.OUT_PKT_BURST_SIZE_L (78),
.OUT_PKT_RESPONSE_STATUS_H (104),
.OUT_PKT_RESPONSE_STATUS_L (103),
.OUT_PKT_TRANS_EXCLUSIVE (68),
.OUT_PKT_BURST_TYPE_H (82),
.OUT_PKT_BURST_TYPE_L (81),
.OUT_PKT_ORI_BURST_SIZE_L (105),
.OUT_PKT_ORI_BURST_SIZE_H (107),
.OUT_ST_DATA_W (108),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) buffered_spi_0_avalon_rsp_width_adapter (
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_002_src_valid), // sink.valid
.in_channel (router_002_src_channel), // .channel
.in_startofpacket (router_002_src_startofpacket), // .startofpacket
.in_endofpacket (router_002_src_endofpacket), // .endofpacket
.in_ready (router_002_src_ready), // .ready
.in_data (router_002_src_data), // .data
.out_endofpacket (buffered_spi_0_avalon_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (buffered_spi_0_avalon_rsp_width_adapter_src_data), // .data
.out_channel (buffered_spi_0_avalon_rsp_width_adapter_src_channel), // .channel
.out_valid (buffered_spi_0_avalon_rsp_width_adapter_src_valid), // .valid
.out_ready (buffered_spi_0_avalon_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (buffered_spi_0_avalon_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (44),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (56),
.IN_PKT_BYTE_CNT_L (51),
.IN_PKT_TRANS_COMPRESSED_READ (45),
.IN_PKT_TRANS_WRITE (47),
.IN_PKT_BURSTWRAP_H (59),
.IN_PKT_BURSTWRAP_L (57),
.IN_PKT_BURST_SIZE_H (62),
.IN_PKT_BURST_SIZE_L (60),
.IN_PKT_RESPONSE_STATUS_H (86),
.IN_PKT_RESPONSE_STATUS_L (85),
.IN_PKT_TRANS_EXCLUSIVE (50),
.IN_PKT_BURST_TYPE_H (64),
.IN_PKT_BURST_TYPE_L (63),
.IN_PKT_ORI_BURST_SIZE_L (87),
.IN_PKT_ORI_BURST_SIZE_H (89),
.IN_ST_DATA_W (90),
.OUT_PKT_ADDR_H (62),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (74),
.OUT_PKT_BYTE_CNT_L (69),
.OUT_PKT_TRANS_COMPRESSED_READ (63),
.OUT_PKT_BURST_SIZE_H (80),
.OUT_PKT_BURST_SIZE_L (78),
.OUT_PKT_RESPONSE_STATUS_H (104),
.OUT_PKT_RESPONSE_STATUS_L (103),
.OUT_PKT_TRANS_EXCLUSIVE (68),
.OUT_PKT_BURST_TYPE_H (82),
.OUT_PKT_BURST_TYPE_L (81),
.OUT_PKT_ORI_BURST_SIZE_L (105),
.OUT_PKT_ORI_BURST_SIZE_H (107),
.OUT_ST_DATA_W (108),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_004_src_valid), // sink.valid
.in_channel (router_004_src_channel), // .channel
.in_startofpacket (router_004_src_startofpacket), // .startofpacket
.in_endofpacket (router_004_src_endofpacket), // .endofpacket
.in_ready (router_004_src_ready), // .ready
.in_data (router_004_src_data), // .data
.out_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_data), // .data
.out_channel (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_channel), // .channel
.out_valid (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_valid), // .valid
.out_ready (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (44),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (56),
.IN_PKT_BYTE_CNT_L (51),
.IN_PKT_TRANS_COMPRESSED_READ (45),
.IN_PKT_TRANS_WRITE (47),
.IN_PKT_BURSTWRAP_H (59),
.IN_PKT_BURSTWRAP_L (57),
.IN_PKT_BURST_SIZE_H (62),
.IN_PKT_BURST_SIZE_L (60),
.IN_PKT_RESPONSE_STATUS_H (86),
.IN_PKT_RESPONSE_STATUS_L (85),
.IN_PKT_TRANS_EXCLUSIVE (50),
.IN_PKT_BURST_TYPE_H (64),
.IN_PKT_BURST_TYPE_L (63),
.IN_PKT_ORI_BURST_SIZE_L (87),
.IN_PKT_ORI_BURST_SIZE_H (89),
.IN_ST_DATA_W (90),
.OUT_PKT_ADDR_H (62),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (74),
.OUT_PKT_BYTE_CNT_L (69),
.OUT_PKT_TRANS_COMPRESSED_READ (63),
.OUT_PKT_BURST_SIZE_H (80),
.OUT_PKT_BURST_SIZE_L (78),
.OUT_PKT_RESPONSE_STATUS_H (104),
.OUT_PKT_RESPONSE_STATUS_L (103),
.OUT_PKT_TRANS_EXCLUSIVE (68),
.OUT_PKT_BURST_TYPE_H (82),
.OUT_PKT_BURST_TYPE_L (81),
.OUT_PKT_ORI_BURST_SIZE_L (105),
.OUT_PKT_ORI_BURST_SIZE_H (107),
.OUT_ST_DATA_W (108),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_006_src_valid), // sink.valid
.in_channel (router_006_src_channel), // .channel
.in_startofpacket (router_006_src_startofpacket), // .startofpacket
.in_endofpacket (router_006_src_endofpacket), // .endofpacket
.in_ready (router_006_src_ready), // .ready
.in_data (router_006_src_data), // .data
.out_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_data), // .data
.out_channel (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_channel), // .channel
.out_valid (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_valid), // .valid
.out_ready (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (62),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (74),
.IN_PKT_BYTE_CNT_L (69),
.IN_PKT_TRANS_COMPRESSED_READ (63),
.IN_PKT_TRANS_WRITE (65),
.IN_PKT_BURSTWRAP_H (77),
.IN_PKT_BURSTWRAP_L (75),
.IN_PKT_BURST_SIZE_H (80),
.IN_PKT_BURST_SIZE_L (78),
.IN_PKT_RESPONSE_STATUS_H (104),
.IN_PKT_RESPONSE_STATUS_L (103),
.IN_PKT_TRANS_EXCLUSIVE (68),
.IN_PKT_BURST_TYPE_H (82),
.IN_PKT_BURST_TYPE_L (81),
.IN_PKT_ORI_BURST_SIZE_L (105),
.IN_PKT_ORI_BURST_SIZE_H (107),
.IN_ST_DATA_W (108),
.OUT_PKT_ADDR_H (44),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (56),
.OUT_PKT_BYTE_CNT_L (51),
.OUT_PKT_TRANS_COMPRESSED_READ (45),
.OUT_PKT_BURST_SIZE_H (62),
.OUT_PKT_BURST_SIZE_L (60),
.OUT_PKT_RESPONSE_STATUS_H (86),
.OUT_PKT_RESPONSE_STATUS_L (85),
.OUT_PKT_TRANS_EXCLUSIVE (50),
.OUT_PKT_BURST_TYPE_H (64),
.OUT_PKT_BURST_TYPE_L (63),
.OUT_PKT_ORI_BURST_SIZE_L (87),
.OUT_PKT_ORI_BURST_SIZE_H (89),
.OUT_ST_DATA_W (90),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) buffered_spi_0_avalon_cmd_width_adapter (
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (buffered_spi_0_avalon_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (buffered_spi_0_avalon_cmd_width_adapter_src_data), // .data
.out_channel (buffered_spi_0_avalon_cmd_width_adapter_src_channel), // .channel
.out_valid (buffered_spi_0_avalon_cmd_width_adapter_src_valid), // .valid
.out_ready (buffered_spi_0_avalon_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (buffered_spi_0_avalon_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (62),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (74),
.IN_PKT_BYTE_CNT_L (69),
.IN_PKT_TRANS_COMPRESSED_READ (63),
.IN_PKT_TRANS_WRITE (65),
.IN_PKT_BURSTWRAP_H (77),
.IN_PKT_BURSTWRAP_L (75),
.IN_PKT_BURST_SIZE_H (80),
.IN_PKT_BURST_SIZE_L (78),
.IN_PKT_RESPONSE_STATUS_H (104),
.IN_PKT_RESPONSE_STATUS_L (103),
.IN_PKT_TRANS_EXCLUSIVE (68),
.IN_PKT_BURST_TYPE_H (82),
.IN_PKT_BURST_TYPE_L (81),
.IN_PKT_ORI_BURST_SIZE_L (105),
.IN_PKT_ORI_BURST_SIZE_H (107),
.IN_ST_DATA_W (108),
.OUT_PKT_ADDR_H (44),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (56),
.OUT_PKT_BYTE_CNT_L (51),
.OUT_PKT_TRANS_COMPRESSED_READ (45),
.OUT_PKT_BURST_SIZE_H (62),
.OUT_PKT_BURST_SIZE_L (60),
.OUT_PKT_RESPONSE_STATUS_H (86),
.OUT_PKT_RESPONSE_STATUS_L (85),
.OUT_PKT_TRANS_EXCLUSIVE (50),
.OUT_PKT_BURST_TYPE_H (64),
.OUT_PKT_BURST_TYPE_L (63),
.OUT_PKT_ORI_BURST_SIZE_L (87),
.OUT_PKT_ORI_BURST_SIZE_H (89),
.OUT_ST_DATA_W (90),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_002_src_valid), // sink.valid
.in_channel (cmd_mux_002_src_channel), // .channel
.in_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_002_src_ready), // .ready
.in_data (cmd_mux_002_src_data), // .data
.out_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_data), // .data
.out_channel (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_channel), // .channel
.out_valid (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_valid), // .valid
.out_ready (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (62),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (74),
.IN_PKT_BYTE_CNT_L (69),
.IN_PKT_TRANS_COMPRESSED_READ (63),
.IN_PKT_TRANS_WRITE (65),
.IN_PKT_BURSTWRAP_H (77),
.IN_PKT_BURSTWRAP_L (75),
.IN_PKT_BURST_SIZE_H (80),
.IN_PKT_BURST_SIZE_L (78),
.IN_PKT_RESPONSE_STATUS_H (104),
.IN_PKT_RESPONSE_STATUS_L (103),
.IN_PKT_TRANS_EXCLUSIVE (68),
.IN_PKT_BURST_TYPE_H (82),
.IN_PKT_BURST_TYPE_L (81),
.IN_PKT_ORI_BURST_SIZE_L (105),
.IN_PKT_ORI_BURST_SIZE_H (107),
.IN_ST_DATA_W (108),
.OUT_PKT_ADDR_H (44),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (56),
.OUT_PKT_BYTE_CNT_L (51),
.OUT_PKT_TRANS_COMPRESSED_READ (45),
.OUT_PKT_BURST_SIZE_H (62),
.OUT_PKT_BURST_SIZE_L (60),
.OUT_PKT_RESPONSE_STATUS_H (86),
.OUT_PKT_RESPONSE_STATUS_L (85),
.OUT_PKT_TRANS_EXCLUSIVE (50),
.OUT_PKT_BURST_TYPE_H (64),
.OUT_PKT_BURST_TYPE_L (63),
.OUT_PKT_ORI_BURST_SIZE_L (87),
.OUT_PKT_ORI_BURST_SIZE_H (89),
.OUT_ST_DATA_W (90),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_004_src_valid), // sink.valid
.in_channel (cmd_mux_004_src_channel), // .channel
.in_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_004_src_ready), // .ready
.in_data (cmd_mux_004_src_data), // .data
.out_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_data), // .data
.out_channel (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_channel), // .channel
.out_valid (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_valid), // .valid
.out_ready (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (108),
.BITS_PER_SYMBOL (108),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (10),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (altpll_1_c0_clk), // in_clk.clk
.in_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src6_ready), // in.ready
.in_valid (cmd_demux_src6_valid), // .valid
.in_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.in_channel (cmd_demux_src6_channel), // .channel
.in_data (cmd_demux_src6_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (108),
.BITS_PER_SYMBOL (108),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (10),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (altpll_1_c0_clk), // out_clk.clk
.out_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_006_src0_ready), // in.ready
.in_valid (rsp_demux_006_src0_valid), // .valid
.in_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_006_src0_channel), // .channel
.in_data (rsp_demux_006_src0_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
wasca_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (buffered_spi_0_avalon_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (buffered_spi_0_avalon_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (buffered_spi_0_avalon_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (audio_0_avalon_audio_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (audio_0_avalon_audio_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (audio_0_avalon_audio_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_005 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_flash_0_data_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_flash_0_data_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_flash_0_data_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_005_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_006 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (altpll_1_pll_slave_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (altpll_1_pll_slave_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (altpll_1_pll_slave_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_006_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_006_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_006_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_006_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_007 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_007_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_007_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_007_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_007_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_008 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (uart_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (uart_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (uart_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_008_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_008_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_008_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_008_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_009 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_009_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_009_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_009_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_009_out_0_error) // .error
);
endmodule
|
`include "alink_define.v"
module tx_phy(
input clk ,
input rst ,
input reg_flush ,
input reg_scan ,
input tx_phy_start ,
input [31:0] tx_phy_sel ,
output tx_phy_done ,
input [31:0] tx_dout ,//TxFIFO data input
output tx_rd_en ,//TxFIFO pop
output reg task_id_vld ,
output reg [31:0] rx_phy_sel ,
output reg [31:0] task_id_h ,
output reg [31:0] task_id_l ,
output reg [31:0] reg_tout ,
output [`PHY_NUM-1:0] TX_P ,
output [`PHY_NUM-1:0] TX_N
);
/*
__
tx_phy_start _____| |_____________________________________
_____ __ _____________________________________
tx_phy_sel _____|0 |_________________dont care___________
__
tx_phy_done ________________________________________| |__
__
task_id_vld _________________| |_________________________
_________________ __ _________________________
[rx_phy_sel _________________|0_|_________________________
task_id_h
task_id_l]
*/
parameter IDLE = 2'd0 ;
parameter TASK = 2'd1 ;
parameter HASH = 2'd2 ;
parameter NONCE= 2'd3 ;
//----------------------------------------------
// Alink.clock.tick
//----------------------------------------------
reg [2:0] cur_state ;
reg [2:0] nxt_state ;
reg [4:0] word_cnt ;
reg [3:0] timing_cnt ;
reg hash_pop ;
reg [31:0] tx_buf_flg ;
reg [31:0] tx_buf ;
reg [2:0] tx_rd_en_cnt ;
reg [31:0] reg_step ;
always @ ( posedge clk ) begin
if( rst || cur_state == IDLE )
tx_rd_en_cnt <= 3'b0 ;
else if( tx_rd_en && cur_state == TASK )
tx_rd_en_cnt <= tx_rd_en_cnt + 3'b1 ;
end
always @ ( posedge clk ) begin
if( rst )
timing_cnt <= 4'b0 ;
else if( timing_cnt == `TX_PHY_TIMING )
timing_cnt <= 4'b0 ;
else if( cur_state == HASH || cur_state == NONCE )
timing_cnt <= timing_cnt + 4'b1 ;
else
timing_cnt <= 4'b0 ;
end
wire tick = ( timing_cnt == `TX_PHY_TIMING ) ;
reg nonce_over_flow ;
//----------------------------------------------
// FSM
//----------------------------------------------
always @ ( posedge clk ) begin
if( rst )
cur_state <= IDLE ;
else
cur_state <= nxt_state ;
end
always @ ( * ) begin
nxt_state = cur_state ;
case( cur_state )
IDLE : if( tx_phy_start ) nxt_state = TASK ;
TASK : if( tx_rd_en_cnt == `TX_TASKID_LEN-1 ) nxt_state = HASH ;
HASH : if( word_cnt == `TX_DATA_LEN-1 && ~|tx_buf_flg ) nxt_state = NONCE ;
NONCE: if( nonce_over_flow&&tick ) nxt_state = IDLE ;
endcase
end
assign tx_phy_done = (cur_state == NONCE)&&(nxt_state == IDLE) ;
//----------------------------------------------
// TASK.ID
//----------------------------------------------
always @ ( posedge clk ) begin
if( cur_state == IDLE && nxt_state == TASK ) begin
rx_phy_sel <= tx_phy_sel ;
end
if( cur_state == TASK && tx_rd_en_cnt == 2'd0 ) task_id_h <= tx_dout ;
if( cur_state == TASK && tx_rd_en_cnt == 2'd1 ) task_id_l <= tx_dout ;
if( cur_state == TASK && tx_rd_en_cnt == 2'd2 ) reg_step <= tx_dout ;
if( cur_state == TASK && tx_rd_en_cnt == 2'd3 ) reg_tout <= tx_dout ;
if( rst )
task_id_vld <= 1'b0 ;
else if( cur_state == TASK && nxt_state == HASH )
task_id_vld <= 1'b1 ;
else
task_id_vld <= 1'b0 ;
end
wire [31:0] scan_nonce = task_id_l ;
wire [7:0] scan_no = task_id_h[7:0] ;
reg [7:0] scan_cnt ;
//----------------------------------------------
// Shifter
//----------------------------------------------
always @ ( posedge clk ) begin
if( rst || cur_state == IDLE )
word_cnt <= 5'b0 ;
else if( cur_state == HASH && ~|tx_buf_flg )
word_cnt <= word_cnt + 5'b1 ;
end
assign tx_rd_en = ( cur_state == TASK ) || ( hash_pop ) ;
reg TX_Px ;
reg TX_Nx ;
always @ ( posedge clk or posedge rst ) begin
if( rst || (cur_state == NONCE && nxt_state == IDLE) || reg_flush ) begin
TX_Px <= 1'b1 ;
TX_Nx <= 1'b1 ;
end else if( cur_state == IDLE && nxt_state == TASK ) begin //START
TX_Px <= 1'b0 ;
TX_Nx <= 1'b0 ;
end else if( cur_state == HASH || cur_state == NONCE ) begin
if( ~TX_Px && ~TX_Nx && tick ) begin
TX_Px <= tx_buf[0]?1'b1:1'b0 ;
TX_Nx <= (~tx_buf[0])?1'b1:1'b0 ;
end else if( tick ) begin
TX_Px <= 1'b0 ;
TX_Nx <= 1'b0 ;
end
end
end
genvar i;
generate
for(i = 0; i < `PHY_NUM; i = i + 1) begin
assign {TX_P[i],TX_N[i]} = rx_phy_sel[i] ? {TX_Px,TX_Nx} : 2'b11 ;
end
endgenerate
reg [32:0] nonce_buf ;
always @ ( posedge clk or posedge rst ) begin
if( rst ) begin
hash_pop <= 1'b0 ;
end else if( cur_state == IDLE && nxt_state == TASK ) begin
hash_pop <= 1'b0 ;
end else if( ~TX_Px && ~TX_Nx && tick ) begin
hash_pop <= 1'b0 ;
end else if( cur_state == TASK && nxt_state == HASH ) begin
hash_pop <= 1'b1 ;
end else if( cur_state == HASH && nxt_state != NONCE && ~|tx_buf_flg ) begin
hash_pop <= 1'b1 ;
end else begin
hash_pop <= 1'b0 ;
end
end
always @ ( posedge clk or posedge rst ) begin
if( rst ) begin
tx_buf <= 32'b0 ;
nonce_over_flow <= 1'b0 ;
nonce_buf <= 33'b0 ;
scan_cnt <= 8'b0 ;
end else if( cur_state == IDLE && nxt_state == TASK ) begin
nonce_over_flow <= 1'b0 ;
nonce_buf <= 33'b0 ;
scan_cnt <= 8'b0 ;
end else if( ~TX_Px && ~TX_Nx && tick ) begin
tx_buf <= {1'b0,tx_buf[31:1]} ;
end else if( hash_pop ) begin
tx_buf <= tx_dout ;
end else if( cur_state == HASH && nxt_state == NONCE ) begin
tx_buf <= (reg_scan && (scan_no == scan_cnt)) ? scan_nonce : {32{reg_scan}} | 32'b0 ;
nonce_buf <= nonce_buf + {1'b0,reg_step} ;
scan_cnt <= reg_scan + scan_cnt ;
end else if( cur_state == NONCE && ~|tx_buf_flg ) begin
tx_buf <= (reg_scan && (scan_no == scan_cnt)) ? scan_nonce : {32{reg_scan}} | nonce_buf[31:0] ;
nonce_buf <= nonce_buf + {1'b0,reg_step} ;
nonce_over_flow <= ((nonce_buf)>33'hffff_ffff) ? 1'b1:1'b0 ;
scan_cnt <= reg_scan + scan_cnt ;
end
end
always @ ( posedge clk or posedge rst ) begin
if( rst || cur_state == IDLE ) begin
tx_buf_flg <= 32'hffffffff ;
end else if( ~TX_Px && ~TX_Nx && tick ) begin
tx_buf_flg <= {1'b0,tx_buf_flg[31:1]} ;
end else if( (cur_state == HASH || cur_state == NONCE) && ~|tx_buf_flg ) begin
tx_buf_flg <= 32'hffffffff ;
end
end
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn bus buffered bridge.
*
*/
module rcn_bridge_buf
(
input rst,
input clk,
input [68:0] main_rcn_in,
output [68:0] main_rcn_out,
input [68:0] sub_rcn_in,
output [68:0] sub_rcn_out
);
parameter ID_MASK = 0;
parameter ID_BASE = 1;
parameter ADDR_MASK = 0;
parameter ADDR_BASE = 1;
wire [5:0] my_id_mask = ID_MASK;
wire [5:0] my_id_base = ID_BASE;
wire [23:0] my_addr_mask = ADDR_MASK;
wire [23:0] my_addr_base = ADDR_BASE;
reg [68:0] main_rin;
reg [68:0] main_rout;
reg [68:0] sub_rin;
reg [68:0] sub_rout;
assign main_rcn_out = main_rout;
assign sub_rcn_out = sub_rout;
wire [68:0] sub_fifo_in;
wire sub_fifo_push;
wire sub_fifo_full;
wire [68:0] sub_fifo_out;
wire sub_fifo_pop;
wire sub_fifo_empty;
wire [68:0] main_fifo_in;
wire main_fifo_push;
wire main_fifo_full;
wire [68:0] main_fifo_out;
wire main_fifo_pop;
wire main_fifo_empty;
always @ (posedge clk or posedge rst)
if (rst)
begin
main_rin <= 69'd0;
main_rout <= 69'd0;
sub_rin <= 69'd0;
sub_rout <= 69'd0;
end
else
begin
main_rin <= main_rcn_in;
main_rout <= (sub_fifo_pop) ? sub_fifo_out :
(main_fifo_push) ? 69'd0 : main_rin;
sub_rin <= sub_rcn_in;
sub_rout <= (main_fifo_pop) ? main_fifo_out :
(sub_fifo_push) ? 69'd0 : sub_rin;
end
wire main_id_match = ((main_rin[65:60] & my_id_mask) == my_id_base);
wire main_addr_match = ((main_rin[55:34] & my_addr_mask[23:2]) == my_addr_base[23:2]);
assign main_fifo_push = !main_fifo_full && main_rin[68] &&
((main_rin[67] && main_addr_match) ||
(!main_rin[67] && main_id_match));
assign main_fifo_pop = !main_fifo_empty && (!sub_rin[68] || sub_fifo_push);
rcn_fifo main_fifo
(
.rst(rst),
.clk(clk),
.rcn_in(main_rin),
.push(main_fifo_push),
.full(main_fifo_full),
.rcn_out(main_fifo_out),
.pop(main_fifo_pop),
.empty(main_fifo_empty)
);
wire sub_id_match = ((sub_rin[65:60] & my_id_mask) == my_id_base);
wire sub_addr_match = ((sub_rin[55:34] & my_addr_mask[23:2]) == my_addr_base[23:2]);
assign sub_fifo_push = !sub_fifo_full && sub_rin[68] &&
((sub_rin[67] && !sub_addr_match) ||
(!sub_rin[67] && !sub_id_match));
assign sub_fifo_pop = !sub_fifo_empty && (!main_rin[68] || main_fifo_push);
rcn_fifo sub_fifo
(
.rst(rst),
.clk(clk),
.rcn_in(sub_rin),
.push(sub_fifo_push),
.full(sub_fifo_full),
.rcn_out(sub_fifo_out),
.pop(sub_fifo_pop),
.empty(sub_fifo_empty)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O21BA_BEHAVIORAL_PP_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BA_BEHAVIORAL_PP_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9122_core (
// dac interface
dac_div_clk,
dac_rst,
dac_frame_i0,
dac_data_i0,
dac_frame_i1,
dac_data_i1,
dac_frame_i2,
dac_data_i2,
dac_frame_i3,
dac_data_i3,
dac_frame_q0,
dac_data_q0,
dac_frame_q1,
dac_data_q1,
dac_frame_q2,
dac_data_q2,
dac_frame_q3,
dac_data_q3,
dac_status,
// master/slave
dac_enable_out,
dac_enable_in,
// vdma interface
vdma_clk,
vdma_fs,
vdma_valid,
vdma_data,
vdma_ready,
// mmcm reset
mmcm_rst,
// drp interface
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ack_t,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter PCORE_ID = 0;
// dac interface
input dac_div_clk;
output dac_rst;
output dac_frame_i0;
output [15:0] dac_data_i0;
output dac_frame_i1;
output [15:0] dac_data_i1;
output dac_frame_i2;
output [15:0] dac_data_i2;
output dac_frame_i3;
output [15:0] dac_data_i3;
output dac_frame_q0;
output [15:0] dac_data_q0;
output dac_frame_q1;
output [15:0] dac_data_q1;
output dac_frame_q2;
output [15:0] dac_data_q2;
output dac_frame_q3;
output [15:0] dac_data_q3;
input dac_status;
// master/slave
output dac_enable_out;
input dac_enable_in;
// vdma interface
input vdma_clk;
output vdma_fs;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
// mmcm reset
output mmcm_rst;
// drp interface
output drp_rst;
output drp_sel;
output drp_wr;
output [11:0] drp_addr;
output [15:0] drp_wdata;
input [15:0] drp_rdata;
input drp_ack_t;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal registers
reg dac_enable = 'd0;
reg [15:0] dac_data_i0 = 'd0;
reg [15:0] dac_data_i1 = 'd0;
reg [15:0] dac_data_i2 = 'd0;
reg [15:0] dac_data_i3 = 'd0;
reg [15:0] dac_data_q0 = 'd0;
reg [15:0] dac_data_q1 = 'd0;
reg [15:0] dac_data_q2 = 'd0;
reg [15:0] dac_data_q3 = 'd0;
reg dac_frame_i0 = 'd0;
reg dac_frame_i1 = 'd0;
reg dac_frame_i2 = 'd0;
reg dac_frame_i3 = 'd0;
reg dac_frame_q0 = 'd0;
reg dac_frame_q1 = 'd0;
reg dac_frame_q2 = 'd0;
reg dac_frame_q3 = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
// internal clock and resets
wire vdma_rst;
// internal signals
wire dac_enable_s;
wire dac_frame_s;
wire dac_datafmt_s;
wire [ 3:0] dac_datasel_s;
wire [15:0] dac_dds_data_0_0_s;
wire [15:0] dac_dds_data_0_1_s;
wire [15:0] dac_dds_data_0_2_s;
wire [15:0] dac_dds_data_0_3_s;
wire [15:0] dac_dds_data_1_0_s;
wire [15:0] dac_dds_data_1_1_s;
wire [15:0] dac_dds_data_1_2_s;
wire [15:0] dac_dds_data_1_3_s;
wire [63:0] dac_vdma_data_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire [31:0] vdma_frmcnt_s;
wire [31:0] up_rdata_0_s;
wire up_ack_0_s;
wire [31:0] up_rdata_1_s;
wire up_ack_1_s;
wire [31:0] up_rdata_2_s;
wire up_ack_2_s;
wire [31:0] up_rdata_3_s;
wire up_ack_3_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
// master/slave (clocks must be synchronous)
assign dac_enable_s = (PCORE_ID == 0) ? dac_enable_out : dac_enable_in;
always @(posedge dac_div_clk) begin
dac_enable <= dac_enable_s;
end
// dac outputs
always @(posedge dac_div_clk) begin
if (dac_datasel_s[3:1] == 3'd1) begin
dac_data_i0 <= dac_vdma_data_s[15: 0];
dac_data_i1 <= dac_vdma_data_s[15: 0];
dac_data_i2 <= dac_vdma_data_s[47:32];
dac_data_i3 <= dac_vdma_data_s[47:32];
dac_data_q0 <= dac_vdma_data_s[31:16];
dac_data_q1 <= dac_vdma_data_s[31:16];
dac_data_q2 <= dac_vdma_data_s[63:48];
dac_data_q3 <= dac_vdma_data_s[63:48];
end else begin
dac_data_i0 <= dac_dds_data_0_0_s;
dac_data_i1 <= dac_dds_data_0_1_s;
dac_data_i2 <= dac_dds_data_0_2_s;
dac_data_i3 <= dac_dds_data_0_3_s;
dac_data_q0 <= dac_dds_data_1_0_s;
dac_data_q1 <= dac_dds_data_1_1_s;
dac_data_q2 <= dac_dds_data_1_2_s;
dac_data_q3 <= dac_dds_data_1_3_s;
end
if (dac_datasel_s[0] == 3'd1) begin
dac_frame_i0 <= 1'b1;
dac_frame_i1 <= 1'b0;
dac_frame_i2 <= 1'b1;
dac_frame_i3 <= 1'b0;
dac_frame_q0 <= 1'b1;
dac_frame_q1 <= 1'b0;
dac_frame_q2 <= 1'b1;
dac_frame_q3 <= 1'b0;
end else begin
dac_frame_i0 <= dac_frame_s;
dac_frame_i1 <= 1'b0;
dac_frame_i2 <= 1'b0;
dac_frame_i3 <= 1'b0;
dac_frame_q0 <= dac_frame_s;
dac_frame_q1 <= 1'b0;
dac_frame_q2 <= 1'b0;
dac_frame_q3 <= 1'b0;
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s;
up_ack <= up_ack_s | up_ack_0_s | up_ack_1_s;
end
end
// dac channel
axi_ad9122_channel #(.CHID(0)) i_channel_0 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_data_0 (dac_dds_data_0_0_s),
.dac_dds_data_1 (dac_dds_data_0_1_s),
.dac_dds_data_2 (dac_dds_data_0_2_s),
.dac_dds_data_3 (dac_dds_data_0_3_s),
.dac_dds_enable (dac_enable),
.dac_dds_format (dac_datafmt_s),
.dac_dds_pattenb (dac_datasel_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_0_s),
.up_ack (up_ack_0_s));
// dac channel
axi_ad9122_channel #(.CHID(1)) i_channel_1 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_data_0 (dac_dds_data_1_0_s),
.dac_dds_data_1 (dac_dds_data_1_1_s),
.dac_dds_data_2 (dac_dds_data_1_2_s),
.dac_dds_data_3 (dac_dds_data_1_3_s),
.dac_dds_enable (dac_enable),
.dac_dds_format (dac_datafmt_s),
.dac_dds_pattenb (dac_datasel_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_1_s),
.up_ack (up_ack_1_s));
// dac vdma
vdma_core #(.DATA_WIDTH(64)) i_vdma_core (
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_fs (vdma_fs),
.vdma_valid (vdma_valid),
.vdma_data (vdma_data),
.vdma_ready (vdma_ready),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_rd (dac_enable),
.dac_valid (),
.dac_data (dac_vdma_data_s),
.vdma_frmcnt (vdma_frmcnt_s));
// dac common processor interface
up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common (
.mmcm_rst (mmcm_rst),
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_out),
.dac_frame (dac_frame_s),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.dac_datafmt (dac_datafmt_s),
.dac_datasel (dac_datasel_s),
.dac_datarate (),
.dac_clk_ratio (32'd4),
.dac_status (dac_status),
.drp_clk (up_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ack_t (drp_ack_t),
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_frmcnt (vdma_frmcnt_s),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd3),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//UART Version 3
/*
Distributed under the MIT license.
Copyright (c) 2014 Cospan Design LLC
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "project_defines.v"
`timescale 1 ns/1 ps
`define PRESCALER_COUNT 16
`define BIT_LENGTH 8
`define FULL_PERIOD (`PRESCALER_COUNT )
`define HALF_PERIOD (`PRESCALER_COUNT / 2)
module uart_v3 #(
parameter DEFAULT_BAUDRATE = 115200
)(
input clk,
input rst,
output reg tx,
input transmit,
input [7:0] tx_byte,
output is_transmitting,
input rx,
output reg rx_error,
output reg [7:0] rx_byte,
output reg received,
output is_receiving,
output [31:0] prescaler, //output this so the user can use it to calculate a baudrate
input set_clock_div,
input [31:0] user_clock_div,
output [31:0] default_clock_div
);
//Local Parameters
//Receive State Machine
localparam RX_IDLE = 0;
localparam RX_CHECK_START = 1;
localparam RX_READING = 2;
localparam RX_CHECK_STOP = 3;
localparam RX_DELAY_RESTART = 4;
localparam RX_ERROR = 5;
localparam RX_RECEIVED = 6;
//Transmit State Machine
localparam TX_IDLE = 0;
localparam TX_SENDING = 1;
localparam TX_FINISHED = 2;
//Registers/Wires
//Receive Register
reg [2:0] rx_state;
reg [3:0] rx_bit_count;
reg [7:0] rx_data;
reg [31:0] rx_clock_div;
reg [31:0] rx_clock_div_count;
reg [31:0] rx_prescaler_count;
//Transmit Register
reg [2:0] tx_state;
reg [3:0] tx_bit_count;
reg [7:0] tx_data;
reg [31:0] tx_clock_div;
reg [31:0] tx_prescaler_count;
reg [31:0] tx_clock_div_count;
//Submodules
//Asynchronous Logic
assign prescaler = `CLOCK_RATE / (`PRESCALER_COUNT);
assign default_clock_div = `CLOCK_RATE / (`PRESCALER_COUNT * DEFAULT_BAUDRATE);
assign is_receiving = (rx_state != RX_IDLE);
assign is_transmitting = (tx_state != TX_IDLE);
//Synchronous Logic
always @ (posedge clk) begin
if (rst || set_clock_div) begin
rx_state <= RX_IDLE;
rx_bit_count <= 0;
rx_clock_div_count <= 0;
rx_clock_div <= `FULL_PERIOD;
rx_data <= 0;
rx_byte <= 0;
rx_error <= 0;
if (set_clock_div) begin
rx_clock_div <= user_clock_div;
end
else begin
rx_clock_div <= default_clock_div;
end
end
else begin
//Strobed
received <= 0;
rx_error <= 0;
//have we passed the clock divider count
rx_clock_div_count <= rx_clock_div_count + 1;
if (rx_clock_div_count >= rx_clock_div) begin
rx_prescaler_count <= rx_prescaler_count + 1;
rx_clock_div_count <= 0;
end
//Receive State Machine
case (rx_state)
RX_IDLE: begin
//--*__ __|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|-- --
rx_prescaler_count <= 0;
rx_data <= 0;
rx_bit_count <= 0;
if (!rx) begin
rx_state <= RX_CHECK_START;
end
else begin
rx_clock_div_count <= 0;
end
end
RX_CHECK_START: begin
//--|__*__|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|-- --
if (rx_prescaler_count >= (`HALF_PERIOD)) begin
rx_prescaler_count <= 0;
if (!rx) begin
rx_state <= RX_READING;
end
else begin
rx_state <= RX_IDLE;
end
end
end
RX_READING: begin
//--|__ __|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|-- --
if (rx_prescaler_count >= (`FULL_PERIOD)) begin
rx_data <= {rx, rx_data[7:1]};
rx_prescaler_count <= 0;
if (rx_bit_count >= 7) begin
//Finished
rx_state <= RX_CHECK_STOP;
end
else begin
rx_bit_count <= rx_bit_count + 1;
end
end
end
RX_CHECK_STOP: begin
//--|__ __|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|--*--
if (rx_prescaler_count >= (`FULL_PERIOD)) begin
if (rx) begin
rx_byte <= rx_data;
//$display ("FOUND DATA!!!: %h", rx_data);
received <= 1;
rx_state <= RX_IDLE;
end
else begin
rx_error <= 1;
rx_state <= RX_IDLE;
end
end
end
default: begin
rx_state <= RX_IDLE;
end
endcase
end
end
always @ (posedge clk) begin
if (rst || set_clock_div) begin
tx <= 1;
tx_state <= TX_IDLE;
tx_data <= 0;
tx_bit_count <= 0;
tx_clock_div_count <= 0;
tx_prescaler_count <= 0;
if (set_clock_div) begin
tx_clock_div <= user_clock_div;
end
else begin
tx_clock_div <= default_clock_div;
end
end
else begin
//have we passed the clock divider count
tx_clock_div_count <= tx_clock_div_count + 1;
if (tx_clock_div_count >= tx_clock_div) begin
tx_prescaler_count <= tx_prescaler_count + 1;
tx_clock_div_count <= 0;
end
case (tx_state)
TX_IDLE: begin
tx <= 1;
tx_clock_div_count <= 1;
tx_prescaler_count <= 0;
if (transmit) begin
tx <= 0;
tx_data <= tx_byte;
tx_bit_count <= 0;
tx_state <= TX_SENDING;
end
end
TX_SENDING: begin
if (tx_prescaler_count >= (`FULL_PERIOD)) begin
tx_prescaler_count <= 0;
if (tx_bit_count < 8) begin
tx <= tx_data[0];
tx_data <= {1'b0, tx_data[7:1]};
tx_bit_count <= tx_bit_count + 1;
end
else begin
tx <= 1;
tx_state <= TX_FINISHED;
end
end
end
TX_FINISHED: begin
if (tx_prescaler_count >= (`FULL_PERIOD)) begin
tx_state <= TX_IDLE;
end
end
default: begin
tx_state <= TX_IDLE;
end
endcase
end
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: gen_task_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module gen_task_fifo #(
parameter DWIDTH = 32,
parameter AWIDTH = 8
)(
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [DWIDTH-1:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [DWIDTH-1:0] q;
output [AWIDTH-1:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [DWIDTH-1:0] sub_wire2;
wire [AWIDTH-1:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [DWIDTH-1:0] q = sub_wire2[DWIDTH-1:0];
wire [AWIDTH-1:0] usedw = sub_wire3[AWIDTH-1:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.usedw (sub_wire3),
.almost_empty (),
.almost_full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Cyclone IV GX",
scfifo_component.lpm_numwords = 2**AWIDTH,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = DWIDTH,
scfifo_component.lpm_widthu = AWIDTH,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL gen_task_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gen_task_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gen_task_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gen_task_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gen_task_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gen_task_fifo_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
module erx_io (/*AUTOARG*/
// Outputs
rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
rx_lclk_div4, rx_frame_par, rx_data_par, ecfg_rx_datain,
// Inputs
reset, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n,
rxi_data_p, rxi_data_n, rx_wr_wait, rx_rd_wait, ecfg_rx_enable,
ecfg_rx_gpio_enable, ecfg_dataout
);
parameter IOSTD_ELINK = "LVDS_25";
//###########
//# eLink pins
//###########
input reset; // Reset (from ecfg)
//###########
//# eLink pins
//###########
input rxi_lclk_p, rxi_lclk_n; //link rx clock input
input rxi_frame_p, rxi_frame_n; //link rx frame signal
input [7:0] rxi_data_p, rxi_data_n; //link rx data
output rxo_wr_wait_p,rxo_wr_wait_n; //link rx write pushback output
output rxo_rd_wait_p,rxo_rd_wait_n; //link rx read pushback output
//#############
//# Fabric interface, 1/8 bit rate of eLink
//#############
output rx_lclk_div4; // Parallel clock output (slow)
output [7:0] rx_frame_par;
output [63:0] rx_data_par;
input rx_wr_wait;
input rx_rd_wait;
//#############
//# Configuration bits
//#############
input ecfg_rx_enable; //enable signal for rx
input ecfg_rx_gpio_enable; //forces rx wait pins to constants
input [1:0] ecfg_dataout; //rd_wait, wr_wait for GPIO mode
output [8:0] ecfg_rx_datain; //gpio data in (data in and frame)
//############
//# REGS
//############
reg [63:0] rx_data_par; // output registers
reg [7:0] rx_frame_par;
//############
//# WIRES
//############
wire [7:0] rx_data; // High-speed serial data
wire rx_frame; // serial frame
wire serdes_reset;
//################################
//# Input Buffers Instantiation
//################################
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rxdata[7:0]
(.I (rxi_data_p[7:0]),
.IB (rxi_data_n[7:0]),
.O (rx_data[7:0]));
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rx_frame
(.I (rxi_frame_p),
.IB (rxi_frame_n),
.O (rx_frame));
//#####################
//# Clock Buffers
//#####################
wire rx_lclk; // Single-ended clock
wire rx_lclk_s; // Serial clock after BUFIO
IBUFGDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rxlclk
(.I (rxi_lclk_p),
.IB (rxi_lclk_n),
.O (rx_lclk));
BUFIO bufio_rxlclk
(.I (rx_lclk),
.O (rx_lclk_s));
// BUFR generates the slow clock
BUFR
#(.SIM_DEVICE("7SERIES"),
.BUFR_DIVIDE("4"))
clkout_bufr
(.O (rx_lclk_div4),
.CE(1'b1),
.CLR(reset),
.I (rx_lclk));
//#############################
//# Deserializer instantiations
//#############################
wire [63:0] rx_data_des;
wire [7:0] rx_frame_des;
wire rx_lclk_sn = ~rx_lclk_s;//TODO: Not important, only for MEMORY_QDR mode?
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_serdes
ISERDESE2
#(
.DATA_RATE("DDR"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
.DYN_CLK_INV_EN("FALSE"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.INIT_Q3(1'b0),
.INIT_Q4(1'b0),
.INTERFACE_TYPE("NETWORKING"),
// MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
.IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
.NUM_CE(2), // Number of clock enables (1,2)
.OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
.SRVAL_Q1(1'b0),
.SRVAL_Q2(1'b0),
.SRVAL_Q3(1'b0),
.SRVAL_Q4(1'b0)
)
ISERDESE2_rxdata
(
.O(), // 1-bit output: Combinatorial output
// Q1 - Q8: 1-bit (each) output: Registered data outputs
.Q1(rx_data_des[i]), // Last data in?
.Q2(rx_data_des[i+8]),
.Q3(rx_data_des[i+16]),
.Q4(rx_data_des[i+24]),
.Q5(rx_data_des[i+32]),
.Q6(rx_data_des[i+40]),
.Q7(rx_data_des[i+48]),
.Q8(rx_data_des[i+56]), // First data in?
// SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
.SHIFTOUT1(),
.SHIFTOUT2(),
.BITSLIP(1'b0), // 1-bit input: The BITSLIP pin performs a Bitslip operation
// synchronous to CLKDIV when asserted (active High). Subsequently, the data
// seen on the Q1 to Q8 output ports will shift, as in a barrel-shifter
// operation, one position every time Bitslip is invoked. DDR operation is
// different from SDR.
// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
.CE1(1'b1),
.CE2(1'b1),
.CLKDIVP(1'b0), // 1-bit input: TBD
// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
.CLK(rx_lclk_s), // 1-bit input: High-speed clock
.CLKB(rx_lclk_sn), // 1-bit input: High-speed secondary clock
.CLKDIV(rx_lclk_div4), // 1-bit input: Divided clock
.OCLK(1'b0), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
.DYNCLKDIVSEL(1'b0), // 1-bit input: Dynamic CLKDIV inversion
.DYNCLKSEL(1'b0), // 1-bit input: Dynamic CLK/CLKB inversion
// Input Data: 1-bit (each) input: ISERDESE2 data input ports
.D(rx_data[i]), // 1-bit input: Data input
.DDLY(1'b0), // 1-bit input: Serial data from IDELAYE2
.OFB(1'b0), // 1-bit input: Data feedback from OSERDESE2
.OCLKB(1'b0), // 1-bit input: High speed negative edge output clock
.RST(serdes_reset), // 1-bit input: Active high asynchronous reset
// SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0)
);
end // block: gen_serdes
endgenerate
ISERDESE2
#(
.DATA_RATE("DDR"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
.DYN_CLK_INV_EN("FALSE"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.INIT_Q3(1'b0),
.INIT_Q4(1'b0),
.INTERFACE_TYPE("NETWORKING"),
// MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
.IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
.NUM_CE(2), // Number of clock enables (1,2)
.OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
.SRVAL_Q1(1'b0),
.SRVAL_Q2(1'b0),
.SRVAL_Q3(1'b0),
.SRVAL_Q4(1'b0)
)
ISERDESE2_rx_frame
(
.O(), // 1-bit output: Combinatorial output
// Q1 - Q8: 1-bit (each) output: Registered data outputs
.Q1(rx_frame_des[0]),
.Q2(rx_frame_des[1]),
.Q3(rx_frame_des[2]),
.Q4(rx_frame_des[3]),
.Q5(rx_frame_des[4]),
.Q6(rx_frame_des[5]),
.Q7(rx_frame_des[6]),
.Q8(rx_frame_des[7]),
// SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
.SHIFTOUT1(),
.SHIFTOUT2(),
.BITSLIP(1'b0), // 1-bit input: The BITSLIP pin performs a Bitslip operation
// synchronous to CLKDIV when asserted (active High). Subsequently, the data
// seen on the Q1 to Q8 output ports will shift, as in a barrel-shifter
// operation, one position every time Bitslip is invoked. DDR operation is
// different from SDR.
// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
.CE1(1'b1),
.CE2(1'b1),
.CLKDIVP(1'b0), // 1-bit input: TBD
// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
.CLK(rx_lclk_s), // 1-bit input: High-speed clock
.CLKB(rx_lclk_sn), // 1-bit input: High-speed secondary clock
.CLKDIV(rx_lclk_div4), // 1-bit input: Divided clock
.OCLK(1'b0), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
.DYNCLKDIVSEL(1'b0), // 1-bit input: Dynamic CLKDIV inversion
.DYNCLKSEL(1'b0), // 1-bit input: Dynamic CLK/CLKB inversion
// Input Data: 1-bit (each) input: ISERDESE2 data input ports
.D(rx_frame), // 1-bit input: Data input
.DDLY(1'b0), // 1-bit input: Serial data from IDELAYE2
.OFB(1'b0), // 1-bit input: Data feedback from OSERDESE2
.OCLKB(1'b0), // 1-bit input: High speed negative edge output clock
.RST(serdes_reset), // 1-bit input: Active high asynchronous reset
// SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0)
);
// Sync control signals into our RX clock domain
reg [1:0] rxenb_sync;
wire rxenb = rxenb_sync[0];
assign serdes_reset = ~rxenb;
reg [1:0] rxgpio_sync;
wire rxgpio = rxgpio_sync[0];
// Register outputs once for good measure, then mux in loopback data if enabled
reg [63:0] rx_data_reg;
reg [7:0] rx_frame_reg;
wire rxreset = reset | ~ecfg_rx_enable;
always @ (posedge rx_lclk_div4 or posedge rxreset)
begin
if(rxreset)
rxenb_sync[1:0] <= 'd0;
else
rxenb_sync[1:0] <= {1'b1, rxenb_sync[1]};
end
//TODO: Is this the right place for the enable signal?
always @ (posedge rx_lclk_div4)
begin
rxgpio_sync <= {ecfg_rx_gpio_enable, rxgpio_sync[1]};
rx_data_reg[63:0] <= rx_data_des[63:0];
rx_data_par[63:0] <= rx_data_reg[63:0];
rx_frame_reg[7:0] <= rx_frame_des[7:0] & {8{rxenb}} & {8{~rxgpio}};
rx_frame_par[7:0] <= rx_frame_reg[7:0];
end
//#############
//# GPIO mode inputs
//#############
reg [8:0] datain_reg;
reg [8:0] ecfg_rx_datain;
always @ (posedge rx_lclk_div4)
begin
datain_reg[8] <= rx_frame_par[0];
datain_reg[7:0] <= rx_data[7:0];
ecfg_rx_datain[8:0] <= datain_reg[8:0];
end
//#############
//# Wait signals (asynchronous)
//#############
wire rd_wait = rxgpio ? ecfg_dataout[0] : rx_rd_wait;
wire wr_wait = rxgpio ? ecfg_dataout[1] : rx_wr_wait;
OBUFDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("SLOW")
) OBUFDS_RXWRWAIT
(
.O(rxo_wr_wait_p),
.OB(rxo_wr_wait_n),
.I(wr_wait)
);
OBUFDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("SLOW")
) OBUFDS_RXRDWAIT
(
.O(rxo_rd_wait_p),
.OB(rxo_rd_wait_n),
.I(rd_wait)
);
endmodule // erx_io
/*
File: e_rx_io.v
This file is part of the Parallella Project .
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <[email protected]>
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
// File : ../RTL/hostController/directcontrol.v
// Generated : 11/10/06 05:37:19
// From : ../RTL/hostController/directcontrol.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// directControl
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
module directControl (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, clk, directControlEn, directControlLineState, rst);
input HCTxPortGnt;
input HCTxPortRdy;
input clk;
input directControlEn;
input [1:0] directControlLineState;
input rst;
output [7:0] HCTxPortCntl;
output [7:0] HCTxPortData;
output HCTxPortReq;
output HCTxPortWEn;
reg [7:0] HCTxPortCntl, next_HCTxPortCntl;
reg [7:0] HCTxPortData, next_HCTxPortData;
wire HCTxPortGnt;
wire HCTxPortRdy;
reg HCTxPortReq, next_HCTxPortReq;
reg HCTxPortWEn, next_HCTxPortWEn;
wire clk;
wire directControlEn;
wire [1:0] directControlLineState;
wire rst;
// BINARY ENCODED state machine: drctCntl
// State codes definitions:
`define START_DC 3'b000
`define CHK_DRCT_CNTL 3'b001
`define DRCT_CNTL_WAIT_GNT 3'b010
`define DRCT_CNTL_CHK_LOOP 3'b011
`define DRCT_CNTL_WAIT_RDY 3'b100
`define IDLE_FIN 3'b101
`define IDLE_WAIT_GNT 3'b110
`define IDLE_WAIT_RDY 3'b111
reg [2:0] CurrState_drctCntl;
reg [2:0] NextState_drctCntl;
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
//--------------------------------------------------------------------
// Machine: drctCntl
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (directControlLineState or directControlEn or HCTxPortGnt or HCTxPortRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_drctCntl)
begin : drctCntl_NextState
NextState_drctCntl <= CurrState_drctCntl;
// Set default values for outputs and signals
next_HCTxPortReq <= HCTxPortReq;
next_HCTxPortWEn <= HCTxPortWEn;
next_HCTxPortData <= HCTxPortData;
next_HCTxPortCntl <= HCTxPortCntl;
case (CurrState_drctCntl)
`START_DC:
NextState_drctCntl <= `CHK_DRCT_CNTL;
`CHK_DRCT_CNTL:
if (directControlEn == 1'b1)
begin
NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
next_HCTxPortReq <= 1'b1;
end
else
begin
NextState_drctCntl <= `IDLE_WAIT_GNT;
next_HCTxPortReq <= 1'b1;
end
`DRCT_CNTL_WAIT_GNT:
if (HCTxPortGnt == 1'b1)
NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
`DRCT_CNTL_CHK_LOOP:
begin
next_HCTxPortWEn <= 1'b0;
if (directControlEn == 1'b0)
begin
NextState_drctCntl <= `CHK_DRCT_CNTL;
next_HCTxPortReq <= 1'b0;
end
else
NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
end
`DRCT_CNTL_WAIT_RDY:
if (HCTxPortRdy == 1'b1)
begin
NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
next_HCTxPortWEn <= 1'b1;
next_HCTxPortData <= {6'b000000, directControlLineState};
next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
end
`IDLE_FIN:
begin
next_HCTxPortWEn <= 1'b0;
next_HCTxPortReq <= 1'b0;
NextState_drctCntl <= `CHK_DRCT_CNTL;
end
`IDLE_WAIT_GNT:
if (HCTxPortGnt == 1'b1)
NextState_drctCntl <= `IDLE_WAIT_RDY;
`IDLE_WAIT_RDY:
if (HCTxPortRdy == 1'b1)
begin
NextState_drctCntl <= `IDLE_FIN;
next_HCTxPortWEn <= 1'b1;
next_HCTxPortData <= 8'h00;
next_HCTxPortCntl <= `TX_IDLE;
end
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : drctCntl_CurrentState
if (rst)
CurrState_drctCntl <= `START_DC;
else
CurrState_drctCntl <= NextState_drctCntl;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : drctCntl_RegOutput
if (rst)
begin
HCTxPortCntl <= 8'h00;
HCTxPortData <= 8'h00;
HCTxPortWEn <= 1'b0;
HCTxPortReq <= 1'b0;
end
else
begin
HCTxPortCntl <= next_HCTxPortCntl;
HCTxPortData <= next_HCTxPortData;
HCTxPortWEn <= next_HCTxPortWEn;
HCTxPortReq <= next_HCTxPortReq;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAH_2_V
`define SKY130_FD_SC_LS__FAH_2_V
/**
* fah: Full adder.
*
* Verilog wrapper for fah with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fah.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fah_2 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fah_2 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAH_2_V
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * CNRS-Ecole Polytechnique-INRIA Futurs-Universite Paris Sud *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(*i $Id$ i*)
(** Properties of decidable propositions *)
Definition decidable (P:Prop) := P \/ ~ P.
Theorem dec_not_not : forall P:Prop, decidable P -> (~ P -> False) -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_True : decidable True.
Proof.
unfold decidable; auto.
Qed.
Theorem dec_False : decidable False.
Proof.
unfold decidable, not; auto.
Qed.
Theorem dec_or :
forall A B:Prop, decidable A -> decidable B -> decidable (A \/ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_and :
forall A B:Prop, decidable A -> decidable B -> decidable (A /\ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_not : forall A:Prop, decidable A -> decidable (~ A).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_imp :
forall A B:Prop, decidable A -> decidable B -> decidable (A -> B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_iff :
forall A B:Prop, decidable A -> decidable B -> decidable (A<->B).
Proof.
unfold decidable; tauto.
Qed.
Theorem not_not : forall P:Prop, decidable P -> ~ ~ P -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_or : forall A B:Prop, ~ (A \/ B) -> ~ A /\ ~ B.
Proof.
tauto.
Qed.
Theorem not_and : forall A B:Prop, decidable A -> ~ (A /\ B) -> ~ A \/ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_imp : forall A B:Prop, decidable A -> ~ (A -> B) -> A /\ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem imp_simp : forall A B:Prop, decidable A -> (A -> B) -> ~ A \/ B.
Proof.
unfold decidable; tauto.
Qed.
(** Results formulated with iff, used in FSetDecide.
Negation are expanded since it is unclear whether setoid rewrite
will always perform conversion. *)
(** We begin with lemmas that, when read from left to right,
can be understood as ways to eliminate uses of [not]. *)
Theorem not_true_iff : (True -> False) <-> False.
Proof.
tauto.
Qed.
Theorem not_false_iff : (False -> False) <-> True.
Proof.
tauto.
Qed.
Theorem not_not_iff : forall A:Prop, decidable A ->
(((A -> False) -> False) <-> A).
Proof.
unfold decidable; tauto.
Qed.
Theorem contrapositive : forall A B:Prop, decidable A ->
(((A -> False) -> (B -> False)) <-> (B -> A)).
Proof.
unfold decidable; tauto.
Qed.
Lemma or_not_l_iff_1 : forall A B: Prop, decidable A ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_l_iff_2 : forall A B: Prop, decidable B ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_1 : forall A B: Prop, decidable A ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_2 : forall A B: Prop, decidable B ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma imp_not_l : forall A B: Prop, decidable A ->
(((A -> False) -> B) <-> (A \/ B)).
Proof.
unfold decidable. tauto.
Qed.
(** Moving Negations Around:
We have four lemmas that, when read from left to right,
describe how to push negations toward the leaves of a
proposition and, when read from right to left, describe
how to pull negations toward the top of a proposition. *)
Theorem not_or_iff : forall A B:Prop,
(A \/ B -> False) <-> (A -> False) /\ (B -> False).
Proof.
tauto.
Qed.
Lemma not_and_iff : forall A B:Prop,
(A /\ B -> False) <-> (A -> B -> False).
Proof.
tauto.
Qed.
Lemma not_imp_iff : forall A B:Prop, decidable A ->
(((A -> B) -> False) <-> A /\ (B -> False)).
Proof.
unfold decidable. tauto.
Qed.
Lemma not_imp_rev_iff : forall A B : Prop, decidable A ->
(((A -> B) -> False) <-> (B -> False) /\ A).
Proof.
unfold decidable. tauto.
Qed.
(** With the following hint database, we can leverage [auto] to check
decidability of propositions. *)
Hint Resolve dec_True dec_False dec_or dec_and dec_imp dec_not dec_iff
: decidable_prop.
(** [solve_decidable using lib] will solve goals about the
decidability of a proposition, assisted by an auxiliary
database of lemmas. The database is intended to contain
lemmas stating the decidability of base propositions,
(e.g., the decidability of equality on a particular
inductive type). *)
Tactic Notation "solve_decidable" "using" ident(db) :=
match goal with
| |- decidable _ =>
solve [ auto 100 with decidable_prop db ]
end.
Tactic Notation "solve_decidable" :=
solve_decidable using core.
|
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