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//======================================================================
//
// tb_aes_key_mem.v
// ----------------
// Testbench for the AES key memory module.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module tb_aes_key_mem();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter SHOW_SBOX = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
parameter AES_128_BIT_KEY = 0;
parameter AES_256_BIT_KEY = 1;
parameter AES_128_NUM_ROUNDS = 10;
parameter AES_256_NUM_ROUNDS = 14;
parameter AES_DECIPHER = 1'b0;
parameter AES_ENCIPHER = 1'b1;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg [255 : 0] tb_key;
reg tb_keylen;
reg tb_init;
reg [3 : 0] tb_round;
wire [127 : 0] tb_round_key;
wire tb_ready;
wire [31 : 0] tb_sboxw;
wire [31 : 0] tb_new_sboxw;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
aes_key_mem dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.key(tb_key),
.keylen(tb_keylen),
.init(tb_init),
.round(tb_round),
.round_key(tb_round_key),
.ready(tb_ready),
.sboxw(tb_sboxw),
.new_sboxw(tb_new_sboxw)
);
// The DUT requirees Sboxes.
aes_sbox sbox(.sboxw(tb_sboxw), .new_sboxw(tb_new_sboxw));
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
$display("key = 0x%032x", dut.key);
$display("keylen = 0x%01x, init = 0x%01x, ready = 0x%01x",
dut.keylen, dut.init, dut.ready);
$display("round = 0x%02x", dut.round);
$display("round_key = 0x%016x", dut.round_key);
$display("");
$display("Internal states:");
$display("key_mem_ctrl = 0x%01x, round_key_update = 0x%01x, round_ctr_reg = 0x%01x, rcon_reg = 0x%01x",
dut.key_mem_ctrl_reg, dut.round_key_update, dut.round_ctr_reg, dut.rcon_reg);
$display("prev_key0_reg = 0x%016x, prev_key0_new = 0x%016x, prev_key0_we = 0x%01x",
dut.prev_key0_reg, dut.prev_key0_new, dut.prev_key0_we);
$display("prev_key1_reg = 0x%016x, prev_key1_new = 0x%016x, prev_key1_we = 0x%01x",
dut.prev_key1_reg, dut.prev_key1_new, dut.prev_key1_we);
$display("w0 = 0x%04x, w1 = 0x%04x, w2 = 0x%04x, w3 = 0x%04x",
dut.round_key_gen.w0, dut.round_key_gen.w1,
dut.round_key_gen.w2, dut.round_key_gen.w3);
$display("w4 = 0x%04x, w5 = 0x%04x, w6 = 0x%04x, w7 = 0x%04x",
dut.round_key_gen.w4, dut.round_key_gen.w5,
dut.round_key_gen.w6, dut.round_key_gen.w7);
$display("sboxw = 0x%04x, new_sboxw = 0x%04x, rconw = 0x%04x",
dut.sboxw, dut.new_sboxw, dut.round_key_gen.rconw);
$display("tw = 0x%04x, trw = 0x%04x", dut.round_key_gen.tw, dut.round_key_gen.trw);
$display("key_mem_new = 0x%016x, key_mem_we = 0x%01x",
dut.key_mem_new, dut.key_mem_we);
$display("");
if (SHOW_SBOX)
begin
$display("Sbox functionality:");
$display("sboxw = 0x%08x", sbox.sboxw);
$display("tmp_new_sbox0 = 0x%02x, tmp_new_sbox1 = 0x%02x, tmp_new_sbox2 = 0x%02x, tmp_new_sbox3",
sbox.tmp_new_sbox0, sbox.tmp_new_sbox1, sbox.tmp_new_sbox2, sbox.tmp_new_sbox3);
$display("new_sboxw = 0x%08x", sbox.new_sboxw);
$display("");
end
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_key = {8{32'h00000000}};
tb_keylen = 0;
tb_init = 0;
tb_round = 4'h0;
end
endtask // init_sim
//----------------------------------------------------------------
// wait_ready()
//
// Wait for the ready flag in the dut to be set.
//
// Note: It is the callers responsibility to call the function
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
task wait_ready;
begin
while (!tb_ready)
begin
#(CLK_PERIOD);
end
end
endtask // wait_ready
//----------------------------------------------------------------
// check_key()
//
// Check a given key in the dut key memory against a given
// expected key.
//----------------------------------------------------------------
task check_key(input [3 : 0] key_nr, input [127 : 0] expected);
begin
tb_round = key_nr;
#(CLK_PERIOD);
if (tb_round_key == expected)
begin
$display("** key 0x%01x matched expected round key.", key_nr);
$display("** Got: 0x%016x **", tb_round_key);
end
else
begin
$display("** Error: key 0x%01x did not match expected round key. **", key_nr);
$display("** Expected: 0x%016x **", expected);
$display("** Got: 0x%016x **", tb_round_key);
error_ctr = error_ctr + 1;
end
$display("");
end
endtask // check_key
//----------------------------------------------------------------
// test_key_128()
//
// Test 128 bit keys. Due to array problems, the result check
// is fairly ugly.
//----------------------------------------------------------------
task test_key_128(input [255 : 0] key,
input [127 : 0] expected00,
input [127 : 0] expected01,
input [127 : 0] expected02,
input [127 : 0] expected03,
input [127 : 0] expected04,
input [127 : 0] expected05,
input [127 : 0] expected06,
input [127 : 0] expected07,
input [127 : 0] expected08,
input [127 : 0] expected09,
input [127 : 0] expected10
);
begin
$display("** Testing with 128-bit key 0x%16x", key[255 : 128]);
$display("");
tb_key = key;
tb_keylen = AES_128_BIT_KEY;
tb_init = 1;
#(2 * CLK_PERIOD);
tb_init = 0;
wait_ready();
check_key(4'h0, expected00);
check_key(4'h1, expected01);
check_key(4'h2, expected02);
check_key(4'h3, expected03);
check_key(4'h4, expected04);
check_key(4'h5, expected05);
check_key(4'h6, expected06);
check_key(4'h7, expected07);
check_key(4'h8, expected08);
check_key(4'h9, expected09);
check_key(4'ha, expected10);
tc_ctr = tc_ctr + 1;
end
endtask // test_key_128
//----------------------------------------------------------------
// test_key_256()
//
// Test 256 bit keys. Due to array problems, the result check
// is fairly ugly.
//----------------------------------------------------------------
task test_key_256(input [255 : 0] key,
input [127 : 0] expected00,
input [127 : 0] expected01,
input [127 : 0] expected02,
input [127 : 0] expected03,
input [127 : 0] expected04,
input [127 : 0] expected05,
input [127 : 0] expected06,
input [127 : 0] expected07,
input [127 : 0] expected08,
input [127 : 0] expected09,
input [127 : 0] expected10,
input [127 : 0] expected11,
input [127 : 0] expected12,
input [127 : 0] expected13,
input [127 : 0] expected14
);
begin
$display("** Testing with 256-bit key 0x%32x", key[255 : 000]);
$display("");
tb_key = key;
tb_keylen = AES_256_BIT_KEY;
tb_init = 1;
#(2 * CLK_PERIOD);
tb_init = 0;
wait_ready();
check_key(4'h0, expected00);
check_key(4'h1, expected01);
check_key(4'h2, expected02);
check_key(4'h3, expected03);
check_key(4'h4, expected04);
check_key(4'h5, expected05);
check_key(4'h6, expected06);
check_key(4'h7, expected07);
check_key(4'h8, expected08);
check_key(4'h9, expected09);
check_key(4'ha, expected10);
check_key(4'hb, expected11);
check_key(4'hc, expected12);
check_key(4'hd, expected13);
check_key(4'he, expected14);
tc_ctr = tc_ctr + 1;
end
endtask // test_key_256
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// aes_key_mem_test
// The main test functionality.
//----------------------------------------------------------------
initial
begin : aes_key_mem_test
reg [255 : 0] key128_0;
reg [255 : 0] key128_1;
reg [255 : 0] key128_2;
reg [255 : 0] key128_3;
reg [255 : 0] nist_key128;
reg [255 : 0] key256_0;
reg [255 : 0] key256_1;
reg [255 : 0] key256_2;
reg [255 : 0] nist_key256;
reg [127 : 0] expected_00;
reg [127 : 0] expected_01;
reg [127 : 0] expected_02;
reg [127 : 0] expected_03;
reg [127 : 0] expected_04;
reg [127 : 0] expected_05;
reg [127 : 0] expected_06;
reg [127 : 0] expected_07;
reg [127 : 0] expected_08;
reg [127 : 0] expected_09;
reg [127 : 0] expected_10;
reg [127 : 0] expected_11;
reg [127 : 0] expected_12;
reg [127 : 0] expected_13;
reg [127 : 0] expected_14;
$display(" -= Testbench for aes key mem started =-");
$display(" =====================================");
$display("");
init_sim();
dump_dut_state();
reset_dut();
$display("State after reset:");
dump_dut_state();
$display("");
#(100 *CLK_PERIOD);
// AES-128 test case 1 key and expected values.
key128_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
expected_00 = 128'h00000000000000000000000000000000;
expected_01 = 128'h62636363626363636263636362636363;
expected_02 = 128'h9b9898c9f9fbfbaa9b9898c9f9fbfbaa;
expected_03 = 128'h90973450696ccffaf2f457330b0fac99;
expected_04 = 128'hee06da7b876a1581759e42b27e91ee2b;
expected_05 = 128'h7f2e2b88f8443e098dda7cbbf34b9290;
expected_06 = 128'hec614b851425758c99ff09376ab49ba7;
expected_07 = 128'h217517873550620bacaf6b3cc61bf09b;
expected_08 = 128'h0ef903333ba9613897060a04511dfa9f;
expected_09 = 128'hb1d4d8e28a7db9da1d7bb3de4c664941;
expected_10 = 128'hb4ef5bcb3e92e21123e951cf6f8f188e;
test_key_128(key128_0,
expected_00, expected_01, expected_02, expected_03,
expected_04, expected_05, expected_06, expected_07,
expected_08, expected_09, expected_10);
// AES-128 test case 2 key and expected values.
key128_1 = 256'hffffffffffffffffffffffffffffffff00000000000000000000000000000000;
expected_00 = 128'hffffffffffffffffffffffffffffffff;
expected_01 = 128'he8e9e9e917161616e8e9e9e917161616;
expected_02 = 128'hadaeae19bab8b80f525151e6454747f0;
expected_03 = 128'h090e2277b3b69a78e1e7cb9ea4a08c6e;
expected_04 = 128'he16abd3e52dc2746b33becd8179b60b6;
expected_05 = 128'he5baf3ceb766d488045d385013c658e6;
expected_06 = 128'h71d07db3c6b6a93bc2eb916bd12dc98d;
expected_07 = 128'he90d208d2fbb89b6ed5018dd3c7dd150;
expected_08 = 128'h96337366b988fad054d8e20d68a5335d;
expected_09 = 128'h8bf03f233278c5f366a027fe0e0514a3;
expected_10 = 128'hd60a3588e472f07b82d2d7858cd7c326;
test_key_128(key128_1,
expected_00, expected_01, expected_02, expected_03,
expected_04, expected_05, expected_06, expected_07,
expected_08, expected_09, expected_10);
// AES-128 test case 3 key and expected values.
key128_2 = 256'h000102030405060708090a0b0c0d0e0f00000000000000000000000000000000;
expected_00 = 128'h000102030405060708090a0b0c0d0e0f;
expected_01 = 128'hd6aa74fdd2af72fadaa678f1d6ab76fe;
expected_02 = 128'hb692cf0b643dbdf1be9bc5006830b3fe;
expected_03 = 128'hb6ff744ed2c2c9bf6c590cbf0469bf41;
expected_04 = 128'h47f7f7bc95353e03f96c32bcfd058dfd;
expected_05 = 128'h3caaa3e8a99f9deb50f3af57adf622aa;
expected_06 = 128'h5e390f7df7a69296a7553dc10aa31f6b;
expected_07 = 128'h14f9701ae35fe28c440adf4d4ea9c026;
expected_08 = 128'h47438735a41c65b9e016baf4aebf7ad2;
expected_09 = 128'h549932d1f08557681093ed9cbe2c974e;
expected_10 = 128'h13111d7fe3944a17f307a78b4d2b30c5;
test_key_128(key128_2,
expected_00, expected_01, expected_02, expected_03,
expected_04, expected_05, expected_06, expected_07,
expected_08, expected_09, expected_10);
// AES-128 test case 4 key and expected values.
key128_3 = 256'h6920e299a5202a6d656e636869746f2a00000000000000000000000000000000;
expected_00 = 128'h6920e299a5202a6d656e636869746f2a;
expected_01 = 128'hfa8807605fa82d0d3ac64e6553b2214f;
expected_02 = 128'hcf75838d90ddae80aa1be0e5f9a9c1aa;
expected_03 = 128'h180d2f1488d0819422cb6171db62a0db;
expected_04 = 128'hbaed96ad323d173910f67648cb94d693;
expected_05 = 128'h881b4ab2ba265d8baad02bc36144fd50;
expected_06 = 128'hb34f195d096944d6a3b96f15c2fd9245;
expected_07 = 128'ha7007778ae6933ae0dd05cbbcf2dcefe;
expected_08 = 128'hff8bccf251e2ff5c5c32a3e7931f6d19;
expected_09 = 128'h24b7182e7555e77229674495ba78298c;
expected_10 = 128'hae127cdadb479ba8f220df3d4858f6b1;
test_key_128(key128_3,
expected_00, expected_01, expected_02, expected_03,
expected_04, expected_05, expected_06, expected_07,
expected_08, expected_09, expected_10);
// NIST AES-128 test case.
nist_key128 = 256'h2b7e151628aed2a6abf7158809cf4f3c00000000000000000000000000000000;
expected_00 = 128'h2b7e151628aed2a6abf7158809cf4f3c;
expected_01 = 128'ha0fafe1788542cb123a339392a6c7605;
expected_02 = 128'hf2c295f27a96b9435935807a7359f67f;
expected_03 = 128'h3d80477d4716fe3e1e237e446d7a883b;
expected_04 = 128'hef44a541a8525b7fb671253bdb0bad00;
expected_05 = 128'hd4d1c6f87c839d87caf2b8bc11f915bc;
expected_06 = 128'h6d88a37a110b3efddbf98641ca0093fd;
expected_07 = 128'h4e54f70e5f5fc9f384a64fb24ea6dc4f;
expected_08 = 128'head27321b58dbad2312bf5607f8d292f;
expected_09 = 128'hac7766f319fadc2128d12941575c006e;
expected_10 = 128'hd014f9a8c9ee2589e13f0cc8b6630ca6;
$display("Testing the NIST AES-128 key.");
test_key_128(nist_key128,
expected_00, expected_01, expected_02, expected_03,
expected_04, expected_05, expected_06, expected_07,
expected_08, expected_09, expected_10);
// AES-256 test case 1 key and expected values.
key256_0 = 256'h000000000000000000000000000000000000000000000000000000000000000;
expected_00 = 128'h00000000000000000000000000000000;
expected_01 = 128'h00000000000000000000000000000000;
expected_02 = 128'h62636363626363636263636362636363;
expected_03 = 128'haafbfbfbaafbfbfbaafbfbfbaafbfbfb;
expected_04 = 128'h6f6c6ccf0d0f0fac6f6c6ccf0d0f0fac;
expected_05 = 128'h7d8d8d6ad77676917d8d8d6ad7767691;
expected_06 = 128'h5354edc15e5be26d31378ea23c38810e;
expected_07 = 128'h968a81c141fcf7503c717a3aeb070cab;
expected_08 = 128'h9eaa8f28c0f16d45f1c6e3e7cdfe62e9;
expected_09 = 128'h2b312bdf6acddc8f56bca6b5bdbbaa1e;
expected_10 = 128'h6406fd52a4f79017553173f098cf1119;
expected_11 = 128'h6dbba90b0776758451cad331ec71792f;
expected_12 = 128'he7b0e89c4347788b16760b7b8eb91a62;
expected_13 = 128'h74ed0ba1739b7e252251ad14ce20d43b;
expected_14 = 128'h10f80a1753bf729c45c979e7cb706385;
test_key_256(key256_0,
expected_00, expected_01, expected_02, expected_03,
expected_04, expected_05, expected_06, expected_07,
expected_08, expected_09, expected_10, expected_11,
expected_12, expected_13, expected_14);
// AES-256 test case 2 key and expected values.
key256_1 = 256'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff;
expected_00 = 128'hffffffffffffffffffffffffffffffff;
expected_01 = 128'hffffffffffffffffffffffffffffffff;
expected_02 = 128'he8e9e9e917161616e8e9e9e917161616;
expected_03 = 128'h0fb8b8b8f04747470fb8b8b8f0474747;
expected_04 = 128'h4a4949655d5f5f73b5b6b69aa2a0a08c;
expected_05 = 128'h355858dcc51f1f9bcaa7a7233ae0e064;
expected_06 = 128'hafa80ae5f2f755964741e30ce5e14380;
expected_07 = 128'heca0421129bf5d8ae318faa9d9f81acd;
expected_08 = 128'he60ab7d014fde24653bc014ab65d42ca;
expected_09 = 128'ha2ec6e658b5333ef684bc946b1b3d38b;
expected_10 = 128'h9b6c8a188f91685edc2d69146a702bde;
expected_11 = 128'ha0bd9f782beeac9743a565d1f216b65a;
expected_12 = 128'hfc22349173b35ccfaf9e35dbc5ee1e05;
expected_13 = 128'h0695ed132d7b41846ede24559cc8920f;
expected_14 = 128'h546d424f27de1e8088402b5b4dae355e;
test_key_256(key256_1,
expected_00, expected_01, expected_02, expected_03,
expected_04, expected_05, expected_06, expected_07,
expected_08, expected_09, expected_10, expected_11,
expected_12, expected_13, expected_14);
// AES-256 test case 3 key and expected values.
key256_2 = 256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f;
expected_00 = 128'h000102030405060708090a0b0c0d0e0f;
expected_01 = 128'h101112131415161718191a1b1c1d1e1f;
expected_02 = 128'ha573c29fa176c498a97fce93a572c09c;
expected_03 = 128'h1651a8cd0244beda1a5da4c10640bade;
expected_04 = 128'hae87dff00ff11b68a68ed5fb03fc1567;
expected_05 = 128'h6de1f1486fa54f9275f8eb5373b8518d;
expected_06 = 128'hc656827fc9a799176f294cec6cd5598b;
expected_07 = 128'h3de23a75524775e727bf9eb45407cf39;
expected_08 = 128'h0bdc905fc27b0948ad5245a4c1871c2f;
expected_09 = 128'h45f5a66017b2d387300d4d33640a820a;
expected_10 = 128'h7ccff71cbeb4fe5413e6bbf0d261a7df;
expected_11 = 128'hf01afafee7a82979d7a5644ab3afe640;
expected_12 = 128'h2541fe719bf500258813bbd55a721c0a;
expected_13 = 128'h4e5a6699a9f24fe07e572baacdf8cdea;
expected_14 = 128'h24fc79ccbf0979e9371ac23c6d68de36;
test_key_256(key256_2,
expected_00, expected_01, expected_02, expected_03,
expected_04, expected_05, expected_06, expected_07,
expected_08, expected_09, expected_10, expected_11,
expected_12, expected_13, expected_14);
nist_key256 = 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4;
expected_00 = 128'h603deb1015ca71be2b73aef0857d7781;
expected_01 = 128'h1f352c073b6108d72d9810a30914dff4;
expected_02 = 128'h9ba354118e6925afa51a8b5f2067fcde;
expected_03 = 128'ha8b09c1a93d194cdbe49846eb75d5b9a;
expected_04 = 128'hd59aecb85bf3c917fee94248de8ebe96;
expected_05 = 128'hb5a9328a2678a647983122292f6c79b3;
expected_06 = 128'h812c81addadf48ba24360af2fab8b464;
expected_07 = 128'h98c5bfc9bebd198e268c3ba709e04214;
expected_08 = 128'h68007bacb2df331696e939e46c518d80;
expected_09 = 128'hc814e20476a9fb8a5025c02d59c58239;
expected_10 = 128'hde1369676ccc5a71fa2563959674ee15;
expected_11 = 128'h5886ca5d2e2f31d77e0af1fa27cf73c3;
expected_12 = 128'h749c47ab18501ddae2757e4f7401905a;
expected_13 = 128'hcafaaae3e4d59b349adf6acebd10190d;
expected_14 = 128'hfe4890d1e6188d0b046df344706c631e;
test_key_256(nist_key256,
expected_00, expected_01, expected_02, expected_03,
expected_04, expected_05, expected_06, expected_07,
expected_08, expected_09, expected_10, expected_11,
expected_12, expected_13, expected_14);
display_test_result();
$display("");
$display("*** AES core simulation done. ***");
$finish;
end // aes_key_mem_test
endmodule // tb_aes_key_mem
//======================================================================
// EOF tb_aes_key_mem.v
//======================================================================
|
/*
DCPU16 Verilog Implementation
Copyright (C) 2012 Shawn Tan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as
published by the Free Software Foundation, either version 3 of the
License, or (at your option) any later version. This program is
distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU Lesser General Public
License along with this program. If not, see
<http://www.gnu.org/licenses/>. */
/*
MEMORY BUS
Handles *all* the memory control signals for both F-BUS and A-BUS.
*/
module dcpu16_mbus (/*AUTOARG*/
// Outputs
g_adr, g_stb, g_wre, f_adr, f_stb, f_wre, ena, wpc, regA, regB,
// Inputs
g_dti, g_ack, f_dti, f_ack, bra, CC, regR, rrd, ireg, regO, pha,
clk, rst
);
// Simplified Wishbone
output [15:0] g_adr;
output g_stb,
g_wre;
input [15:0] g_dti;
input g_ack;
// Simplified Wishbone
output [15:0] f_adr;
output f_stb,
f_wre;
input [15:0] f_dti;
input f_ack;
// internal
output ena;
output wpc;
output [15:0] regA,
regB;
input bra;
input CC;
input [15:0] regR;
input [15:0] rrd;
input [15:0] ireg;
input [15:0] regO;
input [1:0] pha;
input clk,
rst;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [15:0] f_adr;
reg f_stb;
reg f_wre;
reg [15:0] g_adr;
reg g_stb;
reg [15:0] regA;
reg [15:0] regB;
reg wpc;
// End of automatics
reg wsp;
reg [15:0] regSP,
regPC;
assign ena = (f_stb ~^ f_ack) & (g_stb ~^ g_ack); // pipe stall
// repeated decoder
wire [5:0] decA, decB;
wire [3:0] decO;
assign {decB, decA, decO} = ireg;
/*
0x00-0x07: register (A, B, C, X, Y, Z, I or J, in that order)
0x08-0x0f: [register]
` 0x10-0x17: [next word + register]
0x18: POP / [SP++]
0x19: PEEK / [SP]
0x1a: PUSH / [--SP]
0x1b: SP
0x1c: PC
0x1d: O
0x1e: [next word]
0x1f: next word (literal)
0x20-0x3f: literal value 0x00-0x1f (literal)
*/
// decode EA
wire Fjsr = (ireg [4:0] == 5'h10);
wire [5:0] ed = (pha[0]) ? decB : decA;
wire Eind = (ed[5:3] == 3'o1); // [R]
wire Enwr = (ed[5:3] == 3'o2); // [[PC++] + R]
wire Epop = (ed[5:0] == 6'h18); // [SP++]
wire Epek = (ed[5:0] == 6'h19); // [SP]
wire Epsh = (ed[5:0] == 6'h1A); // [--SP]
wire Ersp = (ed[5:0] == 6'h1B); // SP
wire Erpc = (ed[5:0] == 6'h1C); // PC
wire Erro = (ed[5:0] == 6'h1D); // O
wire Enwi = (ed[5:0] == 6'h1E); // [PC++]
wire Esht = ed[5]; // xXX
wire [5:0] fg = (pha[0]) ? decA : decB;
wire Fdir = (fg[5:3] == 3'o0); // R
wire Find = (fg[5:3] == 3'o1); // [R]
wire Fnwr = (fg[5:3] == 3'o2); // [[PC++] + R]
wire Fspi = (fg[5:0] == 6'h18); // [SP++]
wire Fspr = (fg[5:0] == 6'h19); // [SP]
wire Fspd = (fg[5:0] == 6'h1A); // [--SP]
wire Frsp = (fg[5:0] == 6'h1B); // SP
wire Frpc = (fg[5:0] == 6'h1C); // PC
wire Fnwi = (fg[5:0] == 6'h1E); // [PC++]
wire Fnwl = (fg[5:0] == 6'h1F); // PC++
// PROGRAMME COUNTER - loadable binary up counter
reg [15:0] rpc;
reg lpc;
always @(posedge clk)
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
regPC <= 16'h0;
wpc <= 1'h0;
// End of automatics
end else if (ena) begin
if (lpc)
regPC <= rpc;
else
regPC <= regPC + 1;
case (pha)
2'o1: wpc <= Frpc & CC;
default: wpc <= wpc;
endcase // case (pha)
end // if (ena)
always @(/*AUTOSENSE*/Fnwi or Fnwl or Fnwr or bra or pha or regB
or regPC or regR or wpc) begin
case (pha)
2'o1: rpc <= (wpc) ? regR :
(bra) ? regB :
regPC;
default: rpc <= regPC;
endcase // case (pha)
case (pha)
2'o3: lpc <= ~(Fnwr | Fnwi | Fnwl);
2'o0: lpc <= ~(Fnwr | Fnwi | Fnwl);
2'o1: lpc <= 1'b1;
default: lpc <= 1'b0;
endcase // case (pha)
end // always @ (...
// STACK POINTER - loadable binary up/down counter
reg [15:0] _rSP;
reg lsp;
reg [15:0] rsp;
always @(posedge clk)
if (rst) begin
regSP <= 16'hFFFF;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
_rSP <= 16'h0;
wsp <= 1'h0;
// End of automatics
end else if (ena) begin
_rSP <= regSP; // backup SP
if (lsp) // manipulate SP
regSP <= rsp;
else if (fg[1] | Fjsr)
regSP <= regSP - 1;
else
regSP <= regSP + 1;
case (pha) // write to SP
2'o1: wsp <= Frsp & CC;
default: wsp <= wsp;
endcase // case (pha)
end // if (ena)
always @(/*AUTOSENSE*/Fjsr or Fspd or Fspi or pha or regR or regSP
or wsp) begin
case (pha)
2'o3: lsp <= ~(Fspi | Fspd | Fjsr);
2'o0: lsp <= ~(Fspi | Fspd);
default: lsp <= 1'b1;
endcase // case (pha)
case (pha)
2'o1: rsp <= (wsp) ? regR :
regSP;
default: rsp <= regSP;
endcase // case (pha)
end // always @ (...
// EA CALCULATOR
wire [15:0] nwr = rrd + g_dti; // FIXME: Reduce this and combine with other ALU
reg [15:0] ea,
eb;
reg [15:0] ec; // Calculated EA
always @(posedge clk)
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
ea <= 16'h0;
eb <= 16'h0;
// End of automatics
end else if (ena) begin
case (pha)
2'o0: ea <= (Fjsr) ? regSP : ec;
default: ea <= ea;
endcase // case (pha)
case (pha)
2'o1: eb <= ec;
default: eb <= eb;
endcase // case (pha)
end // if (ena)
always @(/*AUTOSENSE*/Eind or Enwi or Enwr or Epek or Epop or Epsh
or _rSP or g_dti or nwr or regSP or rrd) begin
ec <= (Eind) ? rrd :
(Enwr) ? nwr :
//(Fjsr) ? decSP :
(Epsh) ? regSP :
(Epop | Epek) ? _rSP :
(Enwi) ? g_dti :
16'hX;
end
// G-BUS
assign g_wre = 1'b0;
always @(posedge clk)
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
g_adr <= 16'h0;
g_stb <= 1'h0;
// End of automatics
end else if (ena) begin
case (pha)
2'o1: g_adr <= ea;
2'o2: g_adr <= eb;
default: g_adr <= regPC;
endcase // case (pha)
case (pha)
2'o3: g_stb <= Fnwr | Fnwi | Fnwl;
2'o0: g_stb <= Fnwr | Fnwi | Fnwl;
2'o1: g_stb <= Find | Fnwr | Fspr | Fspi | Fspd | Fnwi;
2'o2: g_stb <= Find | Fnwr | Fspr | Fspi | Fspd | Fnwi;
endcase // case (pha)
end // if (ena)
// F-BUS
reg [15:0] _adr;
reg _stb, _wre;
always @(posedge clk)
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
_adr <= 16'h0;
_stb <= 1'h0;
_wre <= 1'h0;
// End of automatics
end else if (ena) begin
case (pha)
2'o2: begin
_adr <= g_adr;
_stb <= g_stb | Fjsr;
end
default:begin
_adr <= _adr;
_stb <= _stb;
end
endcase // case (pha)
case (pha)
2'o1: _wre <= Find | Fnwr | Fspr | Fspi | Fspd | Fnwi | Fjsr;
default: _wre <= _wre;
endcase // case (pha)
end // if (ena)
always @(posedge clk)
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
f_adr <= 16'h0;
f_stb <= 1'h0;
f_wre <= 1'h0;
// End of automatics
end else if (ena) begin
case (pha)
2'o1: f_adr <= (wpc) ? regR :
(bra) ? regB :
regPC;
2'o0: f_adr <= _adr;
default: f_adr <= 16'hX;
endcase // case (pha)
case (pha)
2'o1: {f_stb,f_wre} <= (Fjsr) ? 2'o0 : 2'o2;
2'o0: {f_stb,f_wre} <= {_stb, _wre & CC};
default: {f_stb,f_wre} <= 2'o0;
endcase // case (pha)
end // if (ena)
// REG-A/REG-B
reg _rd;
reg [15:0] opr;
always @(posedge clk)
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
_rd <= 1'h0;
// End of automatics
end else if (ena)
case (pha)
2'o1: _rd <= Fdir;
2'o2: _rd <= Fdir;
default: _rd <= 1'b0;
endcase // case (pha)
always @(posedge clk)
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
regA <= 16'h0;
regB <= 16'h0;
// End of automatics
end else if (ena) begin
case (pha)
2'o0: regA <= opr;
2'o2: regA <= (g_stb) ? g_dti :
(Fjsr) ? regPC :
(_rd) ? rrd :
regA;
default: regA <= regA;
endcase // case (pha)
case (pha)
2'o1: regB <= opr;
2'o3: regB <= (g_stb) ? g_dti :
(_rd) ? rrd :
regB;
default: regB <= regB;
endcase // case (pha)
end // if (ena)
always @(/*AUTOSENSE*/Erpc or Erro or Ersp or Esht or ed or g_dti
or g_stb or regO or regPC or regSP) begin
opr <= (g_stb) ? g_dti :
(Ersp) ? regSP :
(Erpc) ? regPC :
(Erro) ? regO :
(Esht) ? {11'd0,ed[4:0]} :
16'hX;
end
endmodule // dcpu16_mbus
|
// megafunction wizard: %ROM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: FROM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 243 01/31/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module FROM (
address_a,
address_b,
clock_a,
clock_b,
q_a,
q_b);
input [7:0] address_a;
input [7:0] address_b;
input clock_a;
input clock_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] sub_wire1;
wire sub_wire2 = 1'h0;
wire [15:0] sub_wire3 = 16'h0;
wire [15:0] q_b = sub_wire0[15:0];
wire [15:0] q_a = sub_wire1[15:0];
altsyncram altsyncram_component (
.clock0 (clock_a),
.wren_a (sub_wire2),
.address_b (address_b),
.clock1 (clock_b),
.data_b (sub_wire3),
.wren_b (sub_wire2),
.address_a (address_a),
.data_a (sub_wire3),
.q_b (sub_wire0),
.q_a (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus (),
.rden_a (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.init_file = "FROM.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "FROM.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INIT_FILE STRING "FROM.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]"
// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 GND 0 0 16 0
// Retrieval info: CONNECT: @data_b 0 0 16 0 GND 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL FROM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FROM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FROM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FROM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FROM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FROM_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 14
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_14_top,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_ds_2,axi_dwidth_converter_v2_1_14_top,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_ds_2,axi_dwidth_converter_v2_1_14_top,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=64,C_M_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=256,\
C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_ds_2 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [12 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [12 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 13, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [12 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [12 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 13, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_14_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(13),
.C_S_AXI_DATA_WIDTH(64),
.C_M_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(256),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_SYMBOL_V
`define SKY130_FD_SC_HVL__OR2_SYMBOL_V
/**
* or2: 2-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__or2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_SYMBOL_V
|
/*
Copyright (C) 2016 Cedric Orban
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1 ns/1ps
module node_tb();
reg clk = 0;
reg [2:0] weight = 0;
reg [7:0] dataIn = 0;
wire dataOut;
node UUT(
.clk (clk),
.en (1'b1),
.weight (weight),
.dataIn (dataIn),
.dataOut (dataOut)
);
always
#5 clk = ~clk;
always begin
dataIn = 8'd5;
#50 weight = 3'd1;
#50 weight = 3'd2;
#50 weight = 3'd3;
#50 weight = 3'd4;
#50 weight = 3'd5;
#50 weight = 3'd6;
#50 weight = 3'd7;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD3_SYMBOL_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD3_SYMBOL_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv3sd3 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD3_SYMBOL_V
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
wire [width-1:0] dec_test_expr = test_expr - {{width-1{1'b0}},1'b1};
wire zoh_test_expr = ((test_expr & dec_test_expr) == {width{1'b0}});
wire valid_test_expr = ((test_expr ^ test_expr) == {width{1'b0}});
`endif
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
reg fire_2state;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_2state <= 1'b0;
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression contains more than 1 asserted bits");
fire_2state <= ovl_fire_2state_f(property_type);
end
else begin
fire_2state <= 1'b0;
end
end
end
assign fire_2state_1 = !zoh_test_expr;
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
reg fire_xcheck_1;
reg fire_xcheck;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_xcheck <= 1'b0;
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
fire_xcheck <= ovl_fire_xcheck_f(property_type);
end
else begin
fire_xcheck <= 1'b0;
end
end
end
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`else
wire fire_2state = 1'b0;
wire fire_xcheck = 1'b0;
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
// Auxiliary logic
reg [width-1:0] one_hots_checked;
reg [width-1:0] prev_one_hots_checked;
reg [width-1:0] prev_test_expr;
always @ (posedge clk) begin
prev_test_expr <= test_expr; // deliberately not reset
if (`OVL_RESET_SIGNAL == 1'b0) begin
one_hots_checked <= {width{1'b0}};
prev_one_hots_checked <= {width{1'b0}};
end
else begin
if (valid_test_expr && zoh_test_expr) begin
one_hots_checked <= one_hots_checked | test_expr;
end
prev_one_hots_checked <= one_hots_checked;
end
end
wire fire_cover_1, fire_cover_2, fire_cover_3;
reg fire_cover;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_cover <= 1'b0;
end
else begin
if (fire_cover_1) begin
ovl_cover_t("test_expr_change covered"); // sanity
end
if (fire_cover_2) begin
ovl_cover_t("all_one_hots_checked covered"); // corner
end
if (fire_cover_3) begin
ovl_cover_t("test_expr_all_zeros covered"); // corner
end
if (fire_cover_1 || fire_cover_2 || fire_cover_3) begin
fire_cover <= 1'b1;
end
else begin
fire_cover <= 1'b0;
end
end
end
assign fire_cover_1 = ((OVL_COVER_SANITY_ON > 0) && (test_expr != prev_test_expr));
assign fire_cover_2 = ((OVL_COVER_CORNER_ON > 0) && (one_hots_checked == {width{1'b1}}) && (one_hots_checked != prev_one_hots_checked));
assign fire_cover_3 = ((OVL_COVER_CORNER_ON > 0) && (test_expr == {width{1'b0}}) && (prev_test_expr != {width{1'b0}}));
`else
wire fire_cover = 1'b0;
`endif // OVL_COVER_ON
|
// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3
// Component : VexRiscv
// Git hash : 7de06b1f9dd600f033d09829432d24e646eeef37
`define Input2Kind_binary_sequential_type [0:0]
`define Input2Kind_binary_sequential_RS 1'b0
`define Input2Kind_binary_sequential_IMM_I 1'b1
`define EnvCtrlEnum_binary_sequential_type [1:0]
`define EnvCtrlEnum_binary_sequential_NONE 2'b00
`define EnvCtrlEnum_binary_sequential_XRET 2'b01
`define EnvCtrlEnum_binary_sequential_ECALL 2'b10
`define BranchCtrlEnum_binary_sequential_type [1:0]
`define BranchCtrlEnum_binary_sequential_INC 2'b00
`define BranchCtrlEnum_binary_sequential_B 2'b01
`define BranchCtrlEnum_binary_sequential_JAL 2'b10
`define BranchCtrlEnum_binary_sequential_JALR 2'b11
`define ShiftCtrlEnum_binary_sequential_type [1:0]
`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00
`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01
`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10
`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11
`define AluBitwiseCtrlEnum_binary_sequential_type [1:0]
`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00
`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01
`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10
`define Src2CtrlEnum_binary_sequential_type [1:0]
`define Src2CtrlEnum_binary_sequential_RS 2'b00
`define Src2CtrlEnum_binary_sequential_IMI 2'b01
`define Src2CtrlEnum_binary_sequential_IMS 2'b10
`define Src2CtrlEnum_binary_sequential_PC 2'b11
`define AluCtrlEnum_binary_sequential_type [1:0]
`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00
`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01
`define AluCtrlEnum_binary_sequential_BITWISE 2'b10
`define Src1CtrlEnum_binary_sequential_type [1:0]
`define Src1CtrlEnum_binary_sequential_RS 2'b00
`define Src1CtrlEnum_binary_sequential_IMU 2'b01
`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10
`define Src1CtrlEnum_binary_sequential_URS1 2'b11
module VexRiscv (
input [31:0] externalResetVector,
input timerInterrupt,
input softwareInterrupt,
input [31:0] externalInterruptArray,
output CfuPlugin_bus_cmd_valid,
input CfuPlugin_bus_cmd_ready,
output [9:0] CfuPlugin_bus_cmd_payload_function_id,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_0,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_1,
input CfuPlugin_bus_rsp_valid,
output CfuPlugin_bus_rsp_ready,
input [31:0] CfuPlugin_bus_rsp_payload_outputs_0,
output reg iBusWishbone_CYC,
output reg iBusWishbone_STB,
input iBusWishbone_ACK,
output iBusWishbone_WE,
output [29:0] iBusWishbone_ADR,
input [31:0] iBusWishbone_DAT_MISO,
output [31:0] iBusWishbone_DAT_MOSI,
output [3:0] iBusWishbone_SEL,
input iBusWishbone_ERR,
output [2:0] iBusWishbone_CTI,
output [1:0] iBusWishbone_BTE,
output dBusWishbone_CYC,
output dBusWishbone_STB,
input dBusWishbone_ACK,
output dBusWishbone_WE,
output [29:0] dBusWishbone_ADR,
input [31:0] dBusWishbone_DAT_MISO,
output [31:0] dBusWishbone_DAT_MOSI,
output [3:0] dBusWishbone_SEL,
input dBusWishbone_ERR,
output [2:0] dBusWishbone_CTI,
output [1:0] dBusWishbone_BTE,
input clk,
input reset
);
wire IBusCachedPlugin_cache_io_flush;
wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck;
wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved;
wire IBusCachedPlugin_cache_io_cpu_decode_isValid;
wire IBusCachedPlugin_cache_io_cpu_decode_isStuck;
wire IBusCachedPlugin_cache_io_cpu_decode_isUser;
reg IBusCachedPlugin_cache_io_cpu_fill_valid;
wire dataCache_1_io_cpu_execute_isValid;
wire [31:0] dataCache_1_io_cpu_execute_address;
wire dataCache_1_io_cpu_memory_isValid;
wire [31:0] dataCache_1_io_cpu_memory_address;
reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess;
reg dataCache_1_io_cpu_writeBack_isValid;
wire dataCache_1_io_cpu_writeBack_isUser;
wire [31:0] dataCache_1_io_cpu_writeBack_storeData;
wire [31:0] dataCache_1_io_cpu_writeBack_address;
wire dataCache_1_io_cpu_writeBack_fence_SW;
wire dataCache_1_io_cpu_writeBack_fence_SR;
wire dataCache_1_io_cpu_writeBack_fence_SO;
wire dataCache_1_io_cpu_writeBack_fence_SI;
wire dataCache_1_io_cpu_writeBack_fence_PW;
wire dataCache_1_io_cpu_writeBack_fence_PR;
wire dataCache_1_io_cpu_writeBack_fence_PO;
wire dataCache_1_io_cpu_writeBack_fence_PI;
wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM;
wire dataCache_1_io_cpu_flush_valid;
wire dataCache_1_io_mem_cmd_ready;
reg [31:0] _zz_RegFilePlugin_regFile_port0;
reg [31:0] _zz_RegFilePlugin_regFile_port1;
wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
wire IBusCachedPlugin_cache_io_cpu_decode_error;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuException;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
wire IBusCachedPlugin_cache_io_mem_cmd_valid;
wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
wire dataCache_1_io_cpu_execute_haltIt;
wire dataCache_1_io_cpu_execute_refilling;
wire dataCache_1_io_cpu_memory_isWrite;
wire dataCache_1_io_cpu_writeBack_haltIt;
wire [31:0] dataCache_1_io_cpu_writeBack_data;
wire dataCache_1_io_cpu_writeBack_mmuException;
wire dataCache_1_io_cpu_writeBack_unalignedAccess;
wire dataCache_1_io_cpu_writeBack_accessError;
wire dataCache_1_io_cpu_writeBack_isWrite;
wire dataCache_1_io_cpu_writeBack_keepMemRspData;
wire dataCache_1_io_cpu_writeBack_exclusiveOk;
wire dataCache_1_io_cpu_flush_ready;
wire dataCache_1_io_cpu_redo;
wire dataCache_1_io_mem_cmd_valid;
wire dataCache_1_io_mem_cmd_payload_wr;
wire dataCache_1_io_mem_cmd_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_payload_size;
wire dataCache_1_io_mem_cmd_payload_last;
wire [51:0] _zz_memory_MUL_LOW;
wire [51:0] _zz_memory_MUL_LOW_1;
wire [51:0] _zz_memory_MUL_LOW_2;
wire [51:0] _zz_memory_MUL_LOW_3;
wire [32:0] _zz_memory_MUL_LOW_4;
wire [51:0] _zz_memory_MUL_LOW_5;
wire [49:0] _zz_memory_MUL_LOW_6;
wire [51:0] _zz_memory_MUL_LOW_7;
wire [49:0] _zz_memory_MUL_LOW_8;
wire [31:0] _zz_execute_SHIFT_RIGHT;
wire [32:0] _zz_execute_SHIFT_RIGHT_1;
wire [32:0] _zz_execute_SHIFT_RIGHT_2;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2;
wire _zz_decode_LEGAL_INSTRUCTION_3;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4;
wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8;
wire _zz_decode_LEGAL_INSTRUCTION_9;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10;
wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14;
wire _zz_decode_LEGAL_INSTRUCTION_15;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16;
wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17;
wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1;
reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6;
wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc;
wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1;
wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2;
wire [19:0] _zz__zz_2;
wire [11:0] _zz__zz_4;
wire [31:0] _zz__zz_6;
wire [31:0] _zz__zz_6_1;
wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload;
wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted;
wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2;
wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6;
wire [26:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18;
wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33;
wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45;
wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62;
wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94;
wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119;
wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132;
wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160;
wire _zz_RegFilePlugin_regFile_port;
wire _zz_decode_RegFilePlugin_rs1Data;
wire _zz_RegFilePlugin_regFile_port_1;
wire _zz_decode_RegFilePlugin_rs2Data;
wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA;
wire [2:0] _zz__zz_execute_SRC1;
wire [4:0] _zz__zz_execute_SRC1_1;
wire [11:0] _zz__zz_execute_SRC2_3;
wire [31:0] _zz_execute_SrcPlugin_addSub;
wire [31:0] _zz_execute_SrcPlugin_addSub_1;
wire [31:0] _zz_execute_SrcPlugin_addSub_2;
wire [31:0] _zz_execute_SrcPlugin_addSub_3;
wire [31:0] _zz_execute_SrcPlugin_addSub_4;
wire [31:0] _zz_execute_SrcPlugin_addSub_5;
wire [31:0] _zz_execute_SrcPlugin_addSub_6;
wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2;
wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2;
wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2;
wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4;
wire _zz_execute_BranchPlugin_branch_src2_6;
wire _zz_execute_BranchPlugin_branch_src2_7;
wire _zz_execute_BranchPlugin_branch_src2_8;
wire [2:0] _zz_execute_BranchPlugin_branch_src2_9;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1;
wire _zz_when;
wire _zz_when_1;
wire [65:0] _zz_writeBack_MulPlugin_result;
wire [65:0] _zz_writeBack_MulPlugin_result_1;
wire [31:0] _zz__zz_decode_RS2_2;
wire [31:0] _zz__zz_decode_RS2_2_1;
wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext;
wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator;
wire [32:0] _zz_memory_DivPlugin_div_result_1;
wire [32:0] _zz_memory_DivPlugin_div_result_2;
wire [32:0] _zz_memory_DivPlugin_div_result_3;
wire [32:0] _zz_memory_DivPlugin_div_result_4;
wire [0:0] _zz_memory_DivPlugin_div_result_5;
wire [32:0] _zz_memory_DivPlugin_rs1_2;
wire [0:0] _zz_memory_DivPlugin_rs1_3;
wire [31:0] _zz_memory_DivPlugin_rs2_1;
wire [0:0] _zz_memory_DivPlugin_rs2_2;
wire [9:0] _zz_execute_CfuPlugin_functionsIds_0;
wire [26:0] _zz_iBusWishbone_ADR_1;
wire [51:0] memory_MUL_LOW;
wire writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire execute_CfuPlugin_CFU_IN_FLIGHT;
wire [33:0] memory_MUL_HH;
wire [33:0] execute_MUL_HH;
wire [33:0] execute_MUL_HL;
wire [33:0] execute_MUL_LH;
wire [31:0] execute_MUL_LL;
wire [31:0] execute_SHIFT_RIGHT;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire [31:0] memory_MEMORY_STORE_DATA_RF;
wire [31:0] execute_MEMORY_STORE_DATA_RF;
wire decode_CSR_READ_OPCODE;
wire decode_CSR_WRITE_OPCODE;
wire decode_PREDICTION_HAD_BRANCHED2;
wire decode_SRC2_FORCE_ZERO;
wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
wire decode_CfuPlugin_CFU_ENABLE;
wire decode_IS_RS2_SIGNED;
wire decode_IS_RS1_SIGNED;
wire decode_IS_DIV;
wire memory_IS_MUL;
wire execute_IS_MUL;
wire decode_IS_MUL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1;
wire decode_IS_CSR;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
wire decode_SRC_LESS_UNSIGNED;
wire decode_MEMORY_MANAGMENT;
wire memory_MEMORY_WR;
wire decode_MEMORY_WR;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1;
wire decode_MEMORY_FORCE_CONSTISTENCY;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire [31:0] memory_PC;
reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire memory_CfuPlugin_CFU_IN_FLIGHT;
wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire execute_CfuPlugin_CFU_ENABLE;
wire execute_IS_RS1_SIGNED;
wire execute_IS_DIV;
wire execute_IS_RS2_SIGNED;
wire memory_IS_DIV;
wire writeBack_IS_MUL;
wire [33:0] writeBack_MUL_HH;
wire [51:0] writeBack_MUL_LOW;
wire [33:0] memory_MUL_HL;
wire [33:0] memory_MUL_LH;
wire [31:0] memory_MUL_LL;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire execute_IS_CSR;
wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL;
wire [31:0] execute_BRANCH_CALC;
wire execute_BRANCH_DO;
wire [31:0] execute_PC;
wire execute_PREDICTION_HAD_BRANCHED2;
(* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ;
wire execute_BRANCH_COND_RESULT;
wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL;
wire decode_RS2_USE;
wire decode_RS1_USE;
reg [31:0] _zz_decode_RS2;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire [31:0] memory_INSTRUCTION;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_RS2;
reg [31:0] decode_RS1;
wire [31:0] memory_SHIFT_RIGHT;
reg [31:0] _zz_decode_RS2_1;
wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC2_FORCE_ZERO;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_execute_SRC2;
wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL;
wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL;
wire decode_SRC_USE_SUB_LESS;
wire decode_SRC_ADD_ZERO;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL;
wire [31:0] execute_SRC2;
wire [31:0] execute_SRC1;
wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL;
wire [31:0] _zz_lastStageRegFileWrite_payload_address;
wire _zz_lastStageRegFileWrite_valid;
reg _zz_1;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire decode_LEGAL_INSTRUCTION;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1;
reg [31:0] _zz_decode_RS2_2;
wire writeBack_MEMORY_WR;
wire [31:0] writeBack_MEMORY_STORE_DATA_RF;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire writeBack_MEMORY_ENABLE;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire memory_MEMORY_ENABLE;
wire execute_MEMORY_FORCE_CONSTISTENCY;
wire execute_MEMORY_MANAGMENT;
(* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ;
wire execute_MEMORY_WR;
wire [31:0] execute_SRC_ADD;
wire execute_MEMORY_ENABLE;
wire [31:0] execute_INSTRUCTION;
wire decode_MEMORY_ENABLE;
wire decode_FLUSH_ALL;
reg IBusCachedPlugin_rsp_issueDetected_4;
reg IBusCachedPlugin_rsp_issueDetected_3;
reg IBusCachedPlugin_rsp_issueDetected_2;
reg IBusCachedPlugin_rsp_issueDetected_1;
wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1;
wire [31:0] decode_INSTRUCTION;
reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT;
wire [31:0] decode_PC;
wire [31:0] writeBack_PC;
wire [31:0] writeBack_INSTRUCTION;
reg decode_arbitration_haltItself;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushIt;
reg decode_arbitration_flushNext;
wire decode_arbitration_isValid;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
reg execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
wire execute_arbitration_flushIt;
reg execute_arbitration_flushNext;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
wire memory_arbitration_flushIt;
wire memory_arbitration_flushNext;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
reg writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
reg writeBack_arbitration_flushIt;
reg writeBack_arbitration_flushNext;
reg writeBack_arbitration_isValid;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring;
wire [31:0] lastStageInstruction /* verilator public */ ;
wire [31:0] lastStagePc /* verilator public */ ;
wire lastStageIsValid /* verilator public */ ;
wire lastStageIsFiring /* verilator public */ ;
reg IBusCachedPlugin_fetcherHalt;
reg IBusCachedPlugin_incomingInstruction;
wire IBusCachedPlugin_predictionJumpInterface_valid;
(* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ;
reg IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire IBusCachedPlugin_decodePrediction_rsp_wasWrong;
wire IBusCachedPlugin_pcValids_0;
wire IBusCachedPlugin_pcValids_1;
wire IBusCachedPlugin_pcValids_2;
wire IBusCachedPlugin_pcValids_3;
reg IBusCachedPlugin_decodeExceptionPort_valid;
reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
wire IBusCachedPlugin_mmuBus_cmd_0_isValid;
wire IBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire IBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire IBusCachedPlugin_mmuBus_rsp_isPaging;
wire IBusCachedPlugin_mmuBus_rsp_allowRead;
wire IBusCachedPlugin_mmuBus_rsp_allowWrite;
wire IBusCachedPlugin_mmuBus_rsp_allowExecute;
wire IBusCachedPlugin_mmuBus_rsp_exception;
wire IBusCachedPlugin_mmuBus_rsp_refilling;
wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire IBusCachedPlugin_mmuBus_end;
wire IBusCachedPlugin_mmuBus_busy;
wire dBus_cmd_valid;
wire dBus_cmd_ready;
wire dBus_cmd_payload_wr;
wire dBus_cmd_payload_uncached;
wire [31:0] dBus_cmd_payload_address;
wire [31:0] dBus_cmd_payload_data;
wire [3:0] dBus_cmd_payload_mask;
wire [2:0] dBus_cmd_payload_size;
wire dBus_cmd_payload_last;
wire dBus_rsp_valid;
wire dBus_rsp_payload_last;
wire [31:0] dBus_rsp_payload_data;
wire dBus_rsp_payload_error;
wire DBusCachedPlugin_mmuBus_cmd_0_isValid;
wire DBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire DBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire DBusCachedPlugin_mmuBus_rsp_isPaging;
wire DBusCachedPlugin_mmuBus_rsp_allowRead;
wire DBusCachedPlugin_mmuBus_rsp_allowWrite;
wire DBusCachedPlugin_mmuBus_rsp_allowExecute;
wire DBusCachedPlugin_mmuBus_rsp_exception;
wire DBusCachedPlugin_mmuBus_rsp_refilling;
wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire DBusCachedPlugin_mmuBus_end;
wire DBusCachedPlugin_mmuBus_busy;
reg DBusCachedPlugin_redoBranch_valid;
wire [31:0] DBusCachedPlugin_redoBranch_payload;
reg DBusCachedPlugin_exceptionBus_valid;
reg [3:0] DBusCachedPlugin_exceptionBus_payload_code;
wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr;
wire decodeExceptionPort_valid;
wire [3:0] decodeExceptionPort_payload_code;
wire [31:0] decodeExceptionPort_payload_badAddr;
wire BranchPlugin_jumpInterface_valid;
wire [31:0] BranchPlugin_jumpInterface_payload;
reg BranchPlugin_branchExceptionPort_valid;
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
wire [31:0] CsrPlugin_csrMapping_readDataSignal;
wire [31:0] CsrPlugin_csrMapping_readDataInit;
wire [31:0] CsrPlugin_csrMapping_writeDataSignal;
wire CsrPlugin_csrMapping_allowCsrSignal;
wire CsrPlugin_csrMapping_hazardFree;
wire CsrPlugin_inWfi /* verilator public */ ;
wire CsrPlugin_thirdPartyWake;
reg CsrPlugin_jumpInterface_valid;
reg [31:0] CsrPlugin_jumpInterface_payload;
wire CsrPlugin_exceptionPendings_0;
wire CsrPlugin_exceptionPendings_1;
wire CsrPlugin_exceptionPendings_2;
wire CsrPlugin_exceptionPendings_3;
wire externalInterrupt;
wire contextSwitching;
reg [1:0] CsrPlugin_privilege;
wire CsrPlugin_forceMachineWire;
reg CsrPlugin_selfException_valid;
reg [3:0] CsrPlugin_selfException_payload_code;
wire [31:0] CsrPlugin_selfException_payload_badAddr;
wire CsrPlugin_allowInterrupts;
wire CsrPlugin_allowException;
wire CsrPlugin_allowEbreakException;
wire IBusCachedPlugin_externalFlush;
wire IBusCachedPlugin_jump_pcLoad_valid;
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4;
wire IBusCachedPlugin_fetchPc_output_valid;
wire IBusCachedPlugin_fetchPc_output_ready;
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusCachedPlugin_fetchPc_correction;
reg IBusCachedPlugin_fetchPc_correctionReg;
wire IBusCachedPlugin_fetchPc_output_fire;
wire IBusCachedPlugin_fetchPc_corrected;
reg IBusCachedPlugin_fetchPc_pcRegPropagate;
reg IBusCachedPlugin_fetchPc_booted;
reg IBusCachedPlugin_fetchPc_inc;
wire when_Fetcher_l131;
wire IBusCachedPlugin_fetchPc_output_fire_1;
wire when_Fetcher_l131_1;
reg [31:0] IBusCachedPlugin_fetchPc_pc;
wire IBusCachedPlugin_fetchPc_redo_valid;
wire [31:0] IBusCachedPlugin_fetchPc_redo_payload;
reg IBusCachedPlugin_fetchPc_flushed;
wire when_Fetcher_l158;
reg IBusCachedPlugin_iBusRsp_redoFetch;
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
wire IBusCachedPlugin_iBusRsp_stages_1_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_1_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_1_halt;
wire IBusCachedPlugin_iBusRsp_stages_2_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_2_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_2_halt;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire IBusCachedPlugin_iBusRsp_flush;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg IBusCachedPlugin_iBusRsp_readyForError;
wire IBusCachedPlugin_iBusRsp_output_valid;
wire IBusCachedPlugin_iBusRsp_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc;
wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
wire IBusCachedPlugin_iBusRsp_output_payload_isRvc;
wire when_Fetcher_l240;
wire when_Fetcher_l320;
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
wire when_Fetcher_l329;
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
wire when_Fetcher_l329_1;
reg IBusCachedPlugin_injector_nextPcCalc_valids_2;
wire when_Fetcher_l329_2;
reg IBusCachedPlugin_injector_nextPcCalc_valids_3;
wire when_Fetcher_l329_3;
reg IBusCachedPlugin_injector_nextPcCalc_valids_4;
wire when_Fetcher_l329_4;
wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1;
wire _zz_2;
reg [10:0] _zz_3;
wire _zz_4;
reg [18:0] _zz_5;
reg _zz_6;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload;
reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3;
wire iBus_cmd_valid;
wire iBus_cmd_ready;
reg [31:0] iBus_cmd_payload_address;
wire [2:0] iBus_cmd_payload_size;
wire iBus_rsp_valid;
wire [31:0] iBus_rsp_payload_data;
wire iBus_rsp_payload_error;
wire [31:0] _zz_IBusCachedPlugin_rspCounter;
reg [31:0] IBusCachedPlugin_rspCounter;
wire IBusCachedPlugin_s0_tightlyCoupledHit;
reg IBusCachedPlugin_s1_tightlyCoupledHit;
reg IBusCachedPlugin_s2_tightlyCoupledHit;
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
wire IBusCachedPlugin_rsp_issueDetected;
reg IBusCachedPlugin_rsp_redoFetch;
wire when_IBusCachedPlugin_l239;
wire when_IBusCachedPlugin_l244;
wire when_IBusCachedPlugin_l250;
wire when_IBusCachedPlugin_l256;
wire when_IBusCachedPlugin_l267;
wire dataCache_1_io_mem_cmd_s2mPipe_valid;
reg dataCache_1_io_mem_cmd_s2mPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_last;
reg dataCache_1_io_mem_cmd_rValid;
reg dataCache_1_io_mem_cmd_rData_wr;
reg dataCache_1_io_mem_cmd_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_rData_size;
reg dataCache_1_io_mem_cmd_rData_last;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
reg dataCache_1_io_mem_cmd_s2mPipe_rValid;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_last;
wire when_Stream_l342;
wire [31:0] _zz_DBusCachedPlugin_rspCounter;
reg [31:0] DBusCachedPlugin_rspCounter;
wire when_DBusCachedPlugin_l303;
wire [1:0] execute_DBusCachedPlugin_size;
reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF;
wire dataCache_1_io_cpu_flush_isStall;
wire when_DBusCachedPlugin_l343;
wire when_DBusCachedPlugin_l359;
wire when_DBusCachedPlugin_l386;
wire when_DBusCachedPlugin_l438;
wire when_DBusCachedPlugin_l458;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3;
reg [31:0] writeBack_DBusCachedPlugin_rspShifted;
wire [31:0] writeBack_DBusCachedPlugin_rspRf;
wire [1:0] switch_Misc_l200;
wire _zz_writeBack_DBusCachedPlugin_rspFormated;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1;
wire _zz_writeBack_DBusCachedPlugin_rspFormated_2;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3;
reg [31:0] writeBack_DBusCachedPlugin_rspFormated;
wire when_DBusCachedPlugin_l484;
wire [33:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
wire when_RegFilePlugin_l63;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg lastStageRegFileWrite_valid /* verilator public */ ;
reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
reg _zz_7;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_execute_REGFILE_WRITE_DATA;
reg [31:0] _zz_execute_SRC1;
wire _zz_execute_SRC2_1;
reg [19:0] _zz_execute_SRC2_2;
wire _zz_execute_SRC2_3;
reg [19:0] _zz_execute_SRC2_4;
reg [31:0] _zz_execute_SRC2_5;
reg [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
wire [4:0] execute_FullBarrelShifterPlugin_amplitude;
reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed;
wire [31:0] execute_FullBarrelShifterPlugin_reversed;
reg [31:0] _zz_decode_RS2_3;
reg HazardSimplePlugin_src0Hazard;
reg HazardSimplePlugin_src1Hazard;
wire HazardSimplePlugin_writeBackWrites_valid;
wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address;
wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data;
reg HazardSimplePlugin_writeBackBuffer_valid;
reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address;
reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data;
wire HazardSimplePlugin_addr0Match;
wire HazardSimplePlugin_addr1Match;
wire when_HazardSimplePlugin_l47;
wire when_HazardSimplePlugin_l48;
wire when_HazardSimplePlugin_l51;
wire when_HazardSimplePlugin_l45;
wire when_HazardSimplePlugin_l57;
wire when_HazardSimplePlugin_l58;
wire when_HazardSimplePlugin_l48_1;
wire when_HazardSimplePlugin_l51_1;
wire when_HazardSimplePlugin_l45_1;
wire when_HazardSimplePlugin_l57_1;
wire when_HazardSimplePlugin_l58_1;
wire when_HazardSimplePlugin_l48_2;
wire when_HazardSimplePlugin_l51_2;
wire when_HazardSimplePlugin_l45_2;
wire when_HazardSimplePlugin_l57_2;
wire when_HazardSimplePlugin_l58_2;
wire when_HazardSimplePlugin_l105;
wire when_HazardSimplePlugin_l108;
wire when_HazardSimplePlugin_l113;
wire execute_BranchPlugin_eq;
wire [2:0] switch_Misc_l200_1;
reg _zz_execute_BRANCH_COND_RESULT;
reg _zz_execute_BRANCH_COND_RESULT_1;
wire _zz_execute_BranchPlugin_missAlignedTarget;
reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1;
wire _zz_execute_BranchPlugin_missAlignedTarget_2;
reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3;
wire _zz_execute_BranchPlugin_missAlignedTarget_4;
reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5;
reg _zz_execute_BranchPlugin_missAlignedTarget_6;
wire execute_BranchPlugin_missAlignedTarget;
reg [31:0] execute_BranchPlugin_branch_src1;
reg [31:0] execute_BranchPlugin_branch_src2;
wire _zz_execute_BranchPlugin_branch_src2;
reg [19:0] _zz_execute_BranchPlugin_branch_src2_1;
wire _zz_execute_BranchPlugin_branch_src2_2;
reg [10:0] _zz_execute_BranchPlugin_branch_src2_3;
wire _zz_execute_BranchPlugin_branch_src2_4;
reg [18:0] _zz_execute_BranchPlugin_branch_src2_5;
wire [31:0] execute_BranchPlugin_branchAdder;
wire when_BranchPlugin_l296;
wire [1:0] CsrPlugin_misa_base;
wire [25:0] CsrPlugin_misa_extensions;
reg [1:0] CsrPlugin_mtvec_mode;
reg [29:0] CsrPlugin_mtvec_base;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mtval;
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire _zz_when_CsrPlugin_l952;
wire _zz_when_CsrPlugin_l952_1;
wire _zz_when_CsrPlugin_l952_2;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire when_CsrPlugin_l909;
wire when_CsrPlugin_l909_1;
wire when_CsrPlugin_l909_2;
wire when_CsrPlugin_l909_3;
wire when_CsrPlugin_l922;
reg CsrPlugin_interrupt_valid;
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
wire when_CsrPlugin_l946;
wire when_CsrPlugin_l952;
wire when_CsrPlugin_l952_1;
wire when_CsrPlugin_l952_2;
wire CsrPlugin_exception;
wire CsrPlugin_lastStageWasWfi;
reg CsrPlugin_pipelineLiberator_pcValids_0;
reg CsrPlugin_pipelineLiberator_pcValids_1;
reg CsrPlugin_pipelineLiberator_pcValids_2;
wire CsrPlugin_pipelineLiberator_active;
wire when_CsrPlugin_l980;
wire when_CsrPlugin_l980_1;
wire when_CsrPlugin_l980_2;
wire when_CsrPlugin_l985;
reg CsrPlugin_pipelineLiberator_done;
wire when_CsrPlugin_l991;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_hadException /* verilator public */ ;
reg [1:0] CsrPlugin_targetPrivilege;
reg [3:0] CsrPlugin_trapCause;
reg [1:0] CsrPlugin_xtvec_mode;
reg [29:0] CsrPlugin_xtvec_base;
wire when_CsrPlugin_l1019;
wire when_CsrPlugin_l1064;
wire [1:0] switch_CsrPlugin_l1068;
reg execute_CsrPlugin_wfiWake;
wire when_CsrPlugin_l1116;
wire execute_CsrPlugin_blockedBySideEffects;
reg execute_CsrPlugin_illegalAccess;
reg execute_CsrPlugin_illegalInstruction;
wire when_CsrPlugin_l1136;
wire when_CsrPlugin_l1137;
wire when_CsrPlugin_l1144;
reg execute_CsrPlugin_writeInstruction;
reg execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [31:0] execute_CsrPlugin_readToWriteData;
wire switch_Misc_l200_2;
reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal;
wire when_CsrPlugin_l1176;
wire when_CsrPlugin_l1180;
wire [11:0] execute_CsrPlugin_csrAddress;
reg execute_MulPlugin_aSigned;
reg execute_MulPlugin_bSigned;
wire [31:0] execute_MulPlugin_a;
wire [31:0] execute_MulPlugin_b;
wire [1:0] switch_MulPlugin_l87;
wire [15:0] execute_MulPlugin_aULow;
wire [15:0] execute_MulPlugin_bULow;
wire [16:0] execute_MulPlugin_aSLow;
wire [16:0] execute_MulPlugin_bSLow;
wire [16:0] execute_MulPlugin_aHigh;
wire [16:0] execute_MulPlugin_bHigh;
wire [65:0] writeBack_MulPlugin_result;
wire when_MulPlugin_l147;
wire [1:0] switch_MulPlugin_l148;
reg [32:0] memory_DivPlugin_rs1;
reg [31:0] memory_DivPlugin_rs2;
reg [64:0] memory_DivPlugin_accumulator;
wire memory_DivPlugin_frontendOk;
reg memory_DivPlugin_div_needRevert;
reg memory_DivPlugin_div_counter_willIncrement;
reg memory_DivPlugin_div_counter_willClear;
reg [5:0] memory_DivPlugin_div_counter_valueNext;
reg [5:0] memory_DivPlugin_div_counter_value;
wire memory_DivPlugin_div_counter_willOverflowIfInc;
wire memory_DivPlugin_div_counter_willOverflow;
reg memory_DivPlugin_div_done;
wire when_MulDivIterativePlugin_l126;
wire when_MulDivIterativePlugin_l126_1;
reg [31:0] memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l128;
wire when_MulDivIterativePlugin_l129;
wire when_MulDivIterativePlugin_l132;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] memory_DivPlugin_div_stage_0_outNumerator;
wire when_MulDivIterativePlugin_l151;
wire [31:0] _zz_memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l162;
wire _zz_memory_DivPlugin_rs2;
wire _zz_memory_DivPlugin_rs1;
reg [32:0] _zz_memory_DivPlugin_rs1_1;
reg [31:0] externalInterruptArray_regNext;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1;
wire execute_CfuPlugin_schedule;
reg execute_CfuPlugin_hold;
reg execute_CfuPlugin_fired;
wire CfuPlugin_bus_cmd_fire;
wire when_CfuPlugin_l171;
wire when_CfuPlugin_l175;
wire [9:0] execute_CfuPlugin_functionsIds_0;
wire _zz_CfuPlugin_bus_cmd_payload_inputs_1;
reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1;
reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
wire CfuPlugin_bus_rsp_rsp_valid;
reg CfuPlugin_bus_rsp_rsp_ready;
wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0;
reg CfuPlugin_bus_rsp_rValid;
reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0;
wire when_CfuPlugin_l208;
wire when_Pipeline_l124;
reg [31:0] decode_to_execute_PC;
wire when_Pipeline_l124_1;
reg [31:0] execute_to_memory_PC;
wire when_Pipeline_l124_2;
reg [31:0] memory_to_writeBack_PC;
wire when_Pipeline_l124_3;
reg [31:0] decode_to_execute_INSTRUCTION;
wire when_Pipeline_l124_4;
reg [31:0] execute_to_memory_INSTRUCTION;
wire when_Pipeline_l124_5;
reg [31:0] memory_to_writeBack_INSTRUCTION;
wire when_Pipeline_l124_6;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
wire when_Pipeline_l124_7;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
wire when_Pipeline_l124_8;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
wire when_Pipeline_l124_9;
reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
wire when_Pipeline_l124_10;
reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL;
wire when_Pipeline_l124_11;
reg decode_to_execute_SRC_USE_SUB_LESS;
wire when_Pipeline_l124_12;
reg decode_to_execute_MEMORY_ENABLE;
wire when_Pipeline_l124_13;
reg execute_to_memory_MEMORY_ENABLE;
wire when_Pipeline_l124_14;
reg memory_to_writeBack_MEMORY_ENABLE;
wire when_Pipeline_l124_15;
reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL;
wire when_Pipeline_l124_16;
reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL;
wire when_Pipeline_l124_17;
reg decode_to_execute_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_18;
reg execute_to_memory_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_19;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_20;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
wire when_Pipeline_l124_21;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_22;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_23;
reg decode_to_execute_MEMORY_WR;
wire when_Pipeline_l124_24;
reg execute_to_memory_MEMORY_WR;
wire when_Pipeline_l124_25;
reg memory_to_writeBack_MEMORY_WR;
wire when_Pipeline_l124_26;
reg decode_to_execute_MEMORY_MANAGMENT;
wire when_Pipeline_l124_27;
reg decode_to_execute_SRC_LESS_UNSIGNED;
wire when_Pipeline_l124_28;
reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL;
wire when_Pipeline_l124_29;
reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL;
wire when_Pipeline_l124_30;
reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL;
wire when_Pipeline_l124_31;
reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL;
wire when_Pipeline_l124_32;
reg decode_to_execute_IS_CSR;
wire when_Pipeline_l124_33;
reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL;
wire when_Pipeline_l124_34;
reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL;
wire when_Pipeline_l124_35;
reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL;
wire when_Pipeline_l124_36;
reg decode_to_execute_IS_MUL;
wire when_Pipeline_l124_37;
reg execute_to_memory_IS_MUL;
wire when_Pipeline_l124_38;
reg memory_to_writeBack_IS_MUL;
wire when_Pipeline_l124_39;
reg decode_to_execute_IS_DIV;
wire when_Pipeline_l124_40;
reg execute_to_memory_IS_DIV;
wire when_Pipeline_l124_41;
reg decode_to_execute_IS_RS1_SIGNED;
wire when_Pipeline_l124_42;
reg decode_to_execute_IS_RS2_SIGNED;
wire when_Pipeline_l124_43;
reg decode_to_execute_CfuPlugin_CFU_ENABLE;
wire when_Pipeline_l124_44;
reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire when_Pipeline_l124_45;
reg [31:0] decode_to_execute_RS1;
wire when_Pipeline_l124_46;
reg [31:0] decode_to_execute_RS2;
wire when_Pipeline_l124_47;
reg decode_to_execute_SRC2_FORCE_ZERO;
wire when_Pipeline_l124_48;
reg decode_to_execute_PREDICTION_HAD_BRANCHED2;
wire when_Pipeline_l124_49;
reg decode_to_execute_CSR_WRITE_OPCODE;
wire when_Pipeline_l124_50;
reg decode_to_execute_CSR_READ_OPCODE;
wire when_Pipeline_l124_51;
reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_52;
reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_53;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_54;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_55;
reg [31:0] execute_to_memory_SHIFT_RIGHT;
wire when_Pipeline_l124_56;
reg [31:0] execute_to_memory_MUL_LL;
wire when_Pipeline_l124_57;
reg [33:0] execute_to_memory_MUL_LH;
wire when_Pipeline_l124_58;
reg [33:0] execute_to_memory_MUL_HL;
wire when_Pipeline_l124_59;
reg [33:0] execute_to_memory_MUL_HH;
wire when_Pipeline_l124_60;
reg [33:0] memory_to_writeBack_MUL_HH;
wire when_Pipeline_l124_61;
reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_62;
reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_63;
reg [51:0] memory_to_writeBack_MUL_LOW;
wire when_Pipeline_l151;
wire when_Pipeline_l154;
wire when_Pipeline_l151_1;
wire when_Pipeline_l154_1;
wire when_Pipeline_l151_2;
wire when_Pipeline_l154_2;
wire when_CsrPlugin_l1264;
reg execute_CsrPlugin_csr_3264;
wire when_CsrPlugin_l1264_1;
reg execute_CsrPlugin_csr_768;
wire when_CsrPlugin_l1264_2;
reg execute_CsrPlugin_csr_836;
wire when_CsrPlugin_l1264_3;
reg execute_CsrPlugin_csr_772;
wire when_CsrPlugin_l1264_4;
reg execute_CsrPlugin_csr_773;
wire when_CsrPlugin_l1264_5;
reg execute_CsrPlugin_csr_833;
wire when_CsrPlugin_l1264_6;
reg execute_CsrPlugin_csr_834;
wire when_CsrPlugin_l1264_7;
reg execute_CsrPlugin_csr_835;
wire when_CsrPlugin_l1264_8;
reg execute_CsrPlugin_csr_2816;
wire when_CsrPlugin_l1264_9;
reg execute_CsrPlugin_csr_2944;
wire when_CsrPlugin_l1264_10;
reg execute_CsrPlugin_csr_3008;
wire when_CsrPlugin_l1264_11;
reg execute_CsrPlugin_csr_4032;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12;
wire when_CsrPlugin_l1297;
wire when_CsrPlugin_l1302;
reg [2:0] _zz_iBusWishbone_ADR;
wire when_InstructionCache_l239;
reg _zz_iBus_rsp_valid;
reg [31:0] iBusWishbone_DAT_MISO_regNext;
reg [2:0] _zz_dBus_cmd_ready;
wire _zz_dBus_cmd_ready_1;
wire _zz_dBus_cmd_ready_2;
wire _zz_dBus_cmd_ready_3;
wire _zz_dBus_cmd_ready_4;
wire _zz_dBus_cmd_ready_5;
reg _zz_dBus_rsp_valid;
reg [31:0] dBusWishbone_DAT_MISO_regNext;
`ifndef SYNTHESIS
reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string;
reg [39:0] decode_ENV_CTRL_string;
reg [39:0] _zz_decode_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string;
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string;
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_decode_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string;
reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] memory_ENV_CTRL_string;
reg [39:0] _zz_memory_ENV_CTRL_string;
reg [39:0] execute_ENV_CTRL_string;
reg [39:0] _zz_execute_ENV_CTRL_string;
reg [39:0] writeBack_ENV_CTRL_string;
reg [39:0] _zz_writeBack_ENV_CTRL_string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_execute_BRANCH_CTRL_string;
reg [71:0] memory_SHIFT_CTRL_string;
reg [71:0] _zz_memory_SHIFT_CTRL_string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_execute_SHIFT_CTRL_string;
reg [23:0] execute_SRC2_CTRL_string;
reg [23:0] _zz_execute_SRC2_CTRL_string;
reg [95:0] execute_SRC1_CTRL_string;
reg [95:0] _zz_execute_SRC1_CTRL_string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_execute_ALU_CTRL_string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_decode_ENV_CTRL_1_string;
reg [31:0] _zz_decode_BRANCH_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_1_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string;
reg [23:0] _zz_decode_SRC2_CTRL_1_string;
reg [63:0] _zz_decode_ALU_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_1_string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_decode_BRANCH_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_2_string;
reg [63:0] _zz_decode_ALU_CTRL_2_string;
reg [23:0] _zz_decode_SRC2_CTRL_2_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string;
reg [71:0] _zz_decode_SHIFT_CTRL_2_string;
reg [31:0] _zz_decode_BRANCH_CTRL_2_string;
reg [39:0] _zz_decode_ENV_CTRL_2_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string;
reg [95:0] decode_to_execute_SRC1_CTRL_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
reg [23:0] decode_to_execute_SRC2_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [71:0] execute_to_memory_SHIFT_CTRL_string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
reg [39:0] decode_to_execute_ENV_CTRL_string;
reg [39:0] execute_to_memory_ENV_CTRL_string;
reg [39:0] memory_to_writeBack_ENV_CTRL_string;
reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
`endif
(* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00);
assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00);
assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5));
assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3));
assign _zz_memory_MUL_LOW_2 = 52'h0;
assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL};
assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4};
assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16);
assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6};
assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16);
assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8};
assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude);
assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0];
assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001);
assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00};
assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1};
assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101);
assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100);
assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS;
assign _zz__zz_execute_SRC1 = 3'b100;
assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15];
assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4));
assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3));
assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1;
assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6);
assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001;
assign _zz_execute_SrcPlugin_addSub_6 = 32'h0;
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100;
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01);
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01);
assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW};
assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32);
assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0];
assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32];
assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement;
assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1};
assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2};
assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])};
assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2;
assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3;
assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4);
assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert;
assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5};
assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1;
assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3};
assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2;
assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2};
assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]};
assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5);
assign _zz_decode_RegFilePlugin_rs1Data = 1'b1;
assign _zz_decode_RegFilePlugin_rs2Data = 1'b1;
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3};
assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0];
assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1];
assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f;
assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f);
assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073;
assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073);
assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063);
assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f;
assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f);
assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003;
assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063);
assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f);
assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f;
assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f);
assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013;
assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033);
assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033);
assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}};
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7];
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3) == 32'h02000030) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19}}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 32'h02004074;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (decode_INSTRUCTION & 32'h10003050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = (decode_INSTRUCTION & 32'h00001050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = 32'h00001050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00002050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00002050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = (decode_INSTRUCTION & 32'h00007034);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = 32'h00005010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h02007064);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = 32'h00007034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h02007054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = 32'h00001000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = (decode_INSTRUCTION & 32'h00003000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = 32'h00002000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48) == 32'h00004004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00005000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = 32'h00004054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73}} != 6'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = 32'h00000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000064;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = (decode_INSTRUCTION & 32'h00000038);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = (decode_INSTRUCTION & 32'h00403040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69) == 32'h00000008);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = 6'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = 32'h00000008;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = (decode_INSTRUCTION & 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = (decode_INSTRUCTION & 32'h00004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = 32'h00004020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79) == 32'h00000010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = 32'h00002030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = (decode_INSTRUCTION & 32'h00001030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92) == 32'h00002020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = (decode_INSTRUCTION & 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = 32'h00001010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = (decode_INSTRUCTION & 32'h00000070);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123) == 32'h00004010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133} != 4'b0000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = 32'h00000030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = 32'h02000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = 32'h02002060;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = 32'h02003020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = (decode_INSTRUCTION & 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = 32'h00004014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = (decode_INSTRUCTION & 32'h00006014);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = 32'h00000044;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = (decode_INSTRUCTION & 32'h00000018);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = 32'h00000058;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148) == 32'h40000030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159) == 32'h00001004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = 32'h00002014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = 32'h40000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = 32'h00000014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = (decode_INSTRUCTION & 32'h00000044);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = 32'h00000004;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = 32'h00005054;
assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7];
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs1Data) begin
_zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs2Data) begin
_zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
always @(posedge clk) begin
if(_zz_1) begin
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
end
InstructionCache IBusCachedPlugin_cache (
.io_flush (IBusCachedPlugin_cache_io_flush ), //i
.io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i
.io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o
.io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i
.io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i
.io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i
.io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i
.io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i
.io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o
.io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i
.io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o
.io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i
.io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i
.io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i
.io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o
.io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o
.io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o
.io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o
.io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o
.io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o
.io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i
.io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i
.io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i
.io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (iBus_cmd_ready ), //i
.io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o
.io_mem_rsp_valid (iBus_rsp_valid ), //i
.io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
DataCache dataCache_1 (
.io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i
.io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i
.io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o
.io_cpu_execute_args_wr (execute_MEMORY_WR ), //i
.io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i
.io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i
.io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o
.io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i
.io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i
.io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o
.io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i
.io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i
.io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i
.io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i
.io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i
.io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o
.io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o
.io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i
.io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o
.io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i
.io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o
.io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o
.io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o
.io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o
.io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i
.io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i
.io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i
.io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i
.io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i
.io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i
.io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i
.io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i
.io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i
.io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o
.io_cpu_redo (dataCache_1_io_cpu_redo ), //o
.io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i
.io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o
.io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i
.io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o
.io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o
.io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o
.io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o
.io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o
.io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o
.io_mem_rsp_valid (dBus_rsp_valid ), //i
.io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i
.io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
always @(*) begin
case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6)
2'b00 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload;
end
2'b01 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload;
end
2'b10 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload;
end
default : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_1)
2'b00 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0;
end
2'b01 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1;
end
2'b10 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_3)
1'b0 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
`ifndef SYNTHESIS
always @(*) begin
case(decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL";
default : decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL";
default : _zz_decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC ";
default : _zz_decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL";
default : memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL";
default : _zz_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL";
default : execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL";
default : _zz_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL";
default : writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR";
default : _zz_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 ";
default : memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC ";
default : execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC ";
default : _zz_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 ";
default : execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR";
default : _zz_decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_2)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_2_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_2)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_2_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_2)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC ";
default : _zz_decode_SRC2_CTRL_2_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_2)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_2)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_2_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_2)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR";
default : _zz_decode_BRANCH_CTRL_2_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_2)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL";
default : _zz_decode_ENV_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
default : decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL";
default : decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL";
default : execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
`endif
assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7));
assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired);
assign memory_MUL_HH = execute_to_memory_MUL_HH;
assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow));
assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow);
assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT;
assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA;
assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF;
assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF;
assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20);
assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0))));
assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch;
assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32];
assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31];
assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30];
assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29];
assign memory_IS_MUL = execute_to_memory_IS_MUL;
assign execute_IS_MUL = decode_to_execute_IS_MUL;
assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28];
assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1;
assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1;
assign decode_ENV_CTRL = _zz_decode_ENV_CTRL;
assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1;
assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25];
assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1;
assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1;
assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1;
assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17];
assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16];
assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR;
assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13];
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12];
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11];
assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1;
assign decode_ALU_CTRL = _zz_decode_ALU_CTRL;
assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1;
assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL;
assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1;
assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0;
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004);
assign memory_PC = execute_to_memory_PC;
always @(*) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT;
if(memory_arbitration_isStuck) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
always @(*) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT;
if(execute_arbitration_isStuck) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE;
assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
assign execute_IS_DIV = decode_to_execute_IS_DIV;
assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
assign memory_IS_DIV = execute_to_memory_IS_DIV;
assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL;
assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH;
assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW;
assign memory_MUL_HL = execute_to_memory_MUL_HL;
assign memory_MUL_LH = execute_to_memory_MUL_LH;
assign memory_MUL_LL = execute_to_memory_MUL_LL;
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign memory_ENV_CTRL = _zz_memory_ENV_CTRL;
assign execute_ENV_CTRL = _zz_execute_ENV_CTRL;
assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL;
assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0};
assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
assign execute_PC = decode_to_execute_PC;
assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1;
assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL;
assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15];
assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5];
always @(*) begin
_zz_decode_RS2 = execute_REGFILE_WRITE_DATA;
if(when_CsrPlugin_l1176) begin
_zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal;
end
end
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
always @(*) begin
decode_RS2 = decode_RegFilePlugin_rs2Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr1Match) begin
decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l51) begin
decode_RS2 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l51_1) begin
decode_RS2 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l51_2) begin
decode_RS2 = _zz_decode_RS2;
end
end
end
end
always @(*) begin
decode_RS1 = decode_RegFilePlugin_rs1Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr0Match) begin
decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l48) begin
decode_RS1 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l48_1) begin
decode_RS1 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l48_2) begin
decode_RS1 = _zz_decode_RS2;
end
end
end
end
assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT;
always @(*) begin
_zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA;
if(memory_arbitration_isValid) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_SLL_1 : begin
_zz_decode_RS2_1 = _zz_decode_RS2_3;
end
`ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin
_zz_decode_RS2_1 = memory_SHIFT_RIGHT;
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l128) begin
_zz_decode_RS2_1 = memory_DivPlugin_div_result;
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
_zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0;
end
end
assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL;
assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_execute_SRC2 = execute_PC;
assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL;
assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL;
assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3];
assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20];
assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub;
assign execute_SRC_LESS = execute_SrcPlugin_less;
assign execute_ALU_CTRL = _zz_execute_ALU_CTRL;
assign execute_SRC2 = _zz_execute_SRC2_5;
assign execute_SRC1 = _zz_execute_SRC1;
assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL;
assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION;
assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID;
always @(*) begin
_zz_1 = 1'b0;
if(lastStageRegFileWrite_valid) begin
_zz_1 = 1'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data);
always @(*) begin
decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10];
if(when_RegFilePlugin_l63) begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
end
assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0);
always @(*) begin
_zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA;
if(when_DBusCachedPlugin_l484) begin
_zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated;
end
if(when_MulPlugin_l147) begin
case(switch_MulPlugin_l148)
2'b00 : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2;
end
default : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1;
end
endcase
end
end
assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR;
assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR;
assign execute_SRC_ADD = execute_SrcPlugin_addSub;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4];
assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0];
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3;
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_rsp_issueDetected_4 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2;
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_issueDetected_3 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_rsp_issueDetected_2 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_issueDetected_1 = 1'b1;
end
end
assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1;
assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
always @(*) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT;
if(BranchPlugin_jumpInterface_valid) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload;
end
end
always @(*) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload;
end
end
assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
always @(*) begin
decode_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l303) begin
decode_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
decode_arbitration_haltByOther = 1'b0;
if(when_HazardSimplePlugin_l113) begin
decode_arbitration_haltByOther = 1'b1;
end
if(CsrPlugin_pipelineLiberator_active) begin
decode_arbitration_haltByOther = 1'b1;
end
if(when_CsrPlugin_l1116) begin
decode_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
decode_arbitration_removeIt = 1'b0;
if(_zz_when) begin
decode_arbitration_removeIt = 1'b1;
end
if(decode_arbitration_isFlushed) begin
decode_arbitration_removeIt = 1'b1;
end
end
assign decode_arbitration_flushIt = 1'b0;
always @(*) begin
decode_arbitration_flushNext = 1'b0;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
decode_arbitration_flushNext = 1'b1;
end
if(_zz_when) begin
decode_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l343) begin
execute_arbitration_haltItself = 1'b1;
end
if(when_CsrPlugin_l1180) begin
if(execute_CsrPlugin_blockedBySideEffects) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CfuPlugin_l175) begin
execute_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltByOther = 1'b0;
if(when_DBusCachedPlugin_l359) begin
execute_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
execute_arbitration_removeIt = 1'b0;
if(_zz_when_1) begin
execute_arbitration_removeIt = 1'b1;
end
if(execute_arbitration_isFlushed) begin
execute_arbitration_removeIt = 1'b1;
end
end
assign execute_arbitration_flushIt = 1'b0;
always @(*) begin
execute_arbitration_flushNext = 1'b0;
if(BranchPlugin_jumpInterface_valid) begin
execute_arbitration_flushNext = 1'b1;
end
if(_zz_when_1) begin
execute_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
memory_arbitration_haltItself = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l129) begin
memory_arbitration_haltItself = 1'b1;
end
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
if(when_CfuPlugin_l208) begin
memory_arbitration_haltItself = 1'b1;
end
end
end
assign memory_arbitration_haltByOther = 1'b0;
always @(*) begin
memory_arbitration_removeIt = 1'b0;
if(memory_arbitration_isFlushed) begin
memory_arbitration_removeIt = 1'b1;
end
end
assign memory_arbitration_flushIt = 1'b0;
assign memory_arbitration_flushNext = 1'b0;
always @(*) begin
writeBack_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l458) begin
writeBack_arbitration_haltItself = 1'b1;
end
end
assign writeBack_arbitration_haltByOther = 1'b0;
always @(*) begin
writeBack_arbitration_removeIt = 1'b0;
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_removeIt = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
writeBack_arbitration_removeIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushIt = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushNext = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1019) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1064) begin
writeBack_arbitration_flushNext = 1'b1;
end
end
assign lastStageInstruction = writeBack_INSTRUCTION;
assign lastStagePc = writeBack_PC;
assign lastStageIsValid = writeBack_arbitration_isValid;
assign lastStageIsFiring = writeBack_arbitration_isFiring;
always @(*) begin
IBusCachedPlugin_fetcherHalt = 1'b0;
if(when_CsrPlugin_l922) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1019) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1064) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_incomingInstruction = 1'b0;
if(when_Fetcher_l240) begin
IBusCachedPlugin_incomingInstruction = 1'b1;
end
end
assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0;
assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit;
assign CsrPlugin_inWfi = 1'b0;
assign CsrPlugin_thirdPartyWake = 1'b0;
always @(*) begin
CsrPlugin_jumpInterface_valid = 1'b0;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
if(when_CsrPlugin_l1064) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00};
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
end
default : begin
end
endcase
end
end
assign CsrPlugin_forceMachineWire = 1'b0;
assign CsrPlugin_allowInterrupts = 1'b1;
assign CsrPlugin_allowException = 1'b1;
assign CsrPlugin_allowEbreakException = 1'b1;
assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000);
assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}};
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1));
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3];
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
always @(*) begin
IBusCachedPlugin_fetchPc_correction = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
end
assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg);
always @(*) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0;
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1;
end
end
assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate);
assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready);
always @(*) begin
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc);
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
end
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
end
always @(*) begin
IBusCachedPlugin_fetchPc_flushed = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
end
assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate));
assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted);
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc;
always @(*) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b0;
if(IBusCachedPlugin_rsp_redoFetch) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b1;
end
end
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0;
if(IBusCachedPlugin_mmuBus_busy) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt);
assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0;
if(when_IBusCachedPlugin_l267) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt);
assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch;
assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch);
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg;
assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
if(when_Fetcher_l320) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
end
end
assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid);
assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0);
assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready));
assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready));
assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck);
assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck);
assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck);
assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1;
assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2;
assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3;
assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4;
assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck);
assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid;
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11];
always @(*) begin
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
end
always @(*) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31]));
if(_zz_6) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0;
end
end
assign _zz_2 = _zz__zz_2[19];
always @(*) begin
_zz_3[10] = _zz_2;
_zz_3[9] = _zz_2;
_zz_3[8] = _zz_2;
_zz_3[7] = _zz_2;
_zz_3[6] = _zz_2;
_zz_3[5] = _zz_2;
_zz_3[4] = _zz_2;
_zz_3[3] = _zz_2;
_zz_3[2] = _zz_2;
_zz_3[1] = _zz_2;
_zz_3[0] = _zz_2;
end
assign _zz_4 = _zz__zz_4[11];
always @(*) begin
_zz_5[18] = _zz_4;
_zz_5[17] = _zz_4;
_zz_5[16] = _zz_4;
_zz_5[15] = _zz_4;
_zz_5[14] = _zz_4;
_zz_5[13] = _zz_4;
_zz_5[12] = _zz_4;
_zz_5[11] = _zz_4;
_zz_5[10] = _zz_4;
_zz_5[9] = _zz_4;
_zz_5[8] = _zz_4;
_zz_5[7] = _zz_4;
_zz_5[6] = _zz_4;
_zz_5[5] = _zz_4;
_zz_5[4] = _zz_4;
_zz_5[3] = _zz_4;
_zz_5[2] = _zz_4;
_zz_5[1] = _zz_4;
_zz_5[0] = _zz_4;
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_6 = _zz__zz_6[1];
end
default : begin
_zz_6 = _zz__zz_6_1[1];
end
endcase
end
assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch);
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
end
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
end
assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}));
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
always @(*) begin
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
end
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid;
assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush);
assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00);
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
assign IBusCachedPlugin_rsp_issueDetected = 1'b0;
always @(*) begin
IBusCachedPlugin_rsp_redoFetch = 1'b0;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling));
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001;
end
end
assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00};
assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected));
assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1));
assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2));
assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3));
assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt);
assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid;
assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready;
assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data;
assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload;
assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL);
assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last);
always @(*) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
if(when_Stream_l342) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1;
end
end
assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid);
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last;
assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready;
assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE);
assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12];
assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD;
always @(*) begin
case(execute_DBusCachedPlugin_size)
2'b00 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0];
end
endcase
end
assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT);
assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready));
assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt);
assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid);
assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE);
assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA;
assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid;
assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck;
assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address;
assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
always @(*) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess;
if(when_DBusCachedPlugin_l386) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1;
end
end
assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite));
always @(*) begin
dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
if(writeBack_arbitration_haltByOther) begin
dataCache_1_io_cpu_writeBack_isValid = 1'b0;
end
end
assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00);
assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA;
assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF;
always @(*) begin
DBusCachedPlugin_redoBranch_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_redoBranch_valid = 1'b1;
end
end
end
assign DBusCachedPlugin_redoBranch_payload = writeBack_PC;
always @(*) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
end
end
end
assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA;
always @(*) begin
DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code};
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101);
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1};
end
end
end
assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt);
assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0];
assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8];
assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16];
assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24];
always @(*) begin
writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted;
writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2;
writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2;
writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3;
end
assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0];
assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12];
assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0];
end
assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0];
end
always @(*) begin
case(switch_Misc_l200)
2'b00 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1;
end
2'b01 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3;
end
default : begin
writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf;
end
endcase
end
assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign IBusCachedPlugin_mmuBus_busy = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign DBusCachedPlugin_mmuBus_busy = 1'b0;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}};
assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1];
assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2;
assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6];
assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2;
assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8];
assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2;
assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18];
assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2;
assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21];
assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2;
assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23];
assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2;
assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26];
assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33 : 33];
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION));
assign decodeExceptionPort_payload_code = 4'b0010;
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0);
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0;
assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1;
always @(*) begin
lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
if(_zz_7) begin
lastStageRegFileWrite_valid = 1'b1;
end
end
always @(*) begin
lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
if(_zz_7) begin
lastStageRegFileWrite_payload_address = 5'h0;
end
end
always @(*) begin
lastStageRegFileWrite_payload_data = _zz_decode_RS2_2;
if(_zz_7) begin
lastStageRegFileWrite_payload_data = 32'h0;
end
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_BITWISE : begin
_zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_binary_sequential_SLT_SLTU : begin
_zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA};
end
default : begin
_zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB;
end
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC1 = execute_RS1;
end
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin
_zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1};
end
`Src1CtrlEnum_binary_sequential_IMU : begin
_zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0};
end
default : begin
_zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1};
end
endcase
end
assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_SRC2_2[19] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[18] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[17] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[16] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[15] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[14] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[13] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[12] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[11] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[10] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[9] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[8] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[7] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[6] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[5] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[4] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[3] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[2] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[1] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[0] = _zz_execute_SRC2_1;
end
assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11];
always @(*) begin
_zz_execute_SRC2_4[19] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[18] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[17] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[16] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[15] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[14] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[13] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[12] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[11] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[10] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[9] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[8] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[7] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[6] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[5] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[4] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[3] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[2] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[1] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[0] = _zz_execute_SRC2_3;
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC2_5 = execute_RS2;
end
`Src2CtrlEnum_binary_sequential_IMI : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_binary_sequential_IMS : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_execute_SRC2_5 = _zz_execute_SRC2;
end
endcase
end
always @(*) begin
execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub;
if(execute_SRC2_FORCE_ZERO) begin
execute_SrcPlugin_addSub = execute_SRC1;
end
end
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0];
always @(*) begin
_zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31];
_zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30];
_zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29];
_zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28];
_zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27];
_zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26];
_zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25];
_zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24];
_zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23];
_zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22];
_zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21];
_zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20];
_zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19];
_zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18];
_zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17];
_zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16];
_zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15];
_zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14];
_zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13];
_zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12];
_zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11];
_zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10];
_zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9];
_zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8];
_zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7];
_zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6];
_zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5];
_zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4];
_zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3];
_zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2];
_zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1];
_zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0];
end
assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1);
always @(*) begin
_zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31];
_zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30];
_zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29];
_zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28];
_zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27];
_zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26];
_zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25];
_zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24];
_zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23];
_zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22];
_zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21];
_zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20];
_zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19];
_zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18];
_zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17];
_zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16];
_zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15];
_zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14];
_zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13];
_zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12];
_zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11];
_zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10];
_zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9];
_zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8];
_zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7];
_zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6];
_zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5];
_zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4];
_zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3];
_zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2];
_zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1];
_zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0];
end
always @(*) begin
HazardSimplePlugin_src0Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l48) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l48_1) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l48_2) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l105) begin
HazardSimplePlugin_src0Hazard = 1'b0;
end
end
always @(*) begin
HazardSimplePlugin_src1Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l51) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l51_1) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l51_2) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l108) begin
HazardSimplePlugin_src1Hazard = 1'b0;
end
end
assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2;
assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]);
assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l47 = 1'b1;
assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47));
assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE));
assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE));
assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE);
assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE);
assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard));
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12];
always @(*) begin
casez(switch_Misc_l200_1)
3'b000 : begin
_zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq;
end
3'b001 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq);
end
3'b1?1 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS);
end
default : begin
_zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS;
end
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b0;
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
default : begin
_zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT;
end
endcase
end
assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]);
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1];
end
default : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1];
end
endcase
end
assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6);
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src1 = execute_RS1;
end
default : begin
execute_BranchPlugin_branch_src1 = execute_PC;
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]};
end
default : begin
execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0});
if(execute_PREDICTION_HAD_BRANCHED2) begin
execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9};
end
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2;
end
assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4;
end
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0));
assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC;
always @(*) begin
BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1]));
if(when_BranchPlugin_l296) begin
BranchPlugin_branchExceptionPort_valid = 1'b0;
end
end
assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000;
assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC;
assign when_BranchPlugin_l296 = 1'b0;
assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid;
always @(*) begin
CsrPlugin_privilege = 2'b11;
if(CsrPlugin_forceMachineWire) begin
CsrPlugin_privilege = 2'b11;
end
end
assign CsrPlugin_misa_base = 2'b01;
assign CsrPlugin_misa_extensions = 26'h0000042;
assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11;
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0];
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0];
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
end
if(decode_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
end
if(execute_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
if(memory_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
end
end
assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck);
assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000);
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11));
assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0));
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
assign CsrPlugin_lastStageWasWfi = 1'b0;
assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid);
assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt);
always @(*) begin
CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2;
if(when_CsrPlugin_l991) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
if(CsrPlugin_hadException) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
end
assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000);
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
always @(*) begin
CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
if(CsrPlugin_hadException) begin
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
end
end
always @(*) begin
CsrPlugin_trapCause = CsrPlugin_interrupt_code;
if(CsrPlugin_hadException) begin
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
end
end
always @(*) begin
CsrPlugin_xtvec_mode = 2'bxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
end
default : begin
end
endcase
end
always @(*) begin
CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
end
default : begin
end
endcase
end
assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump);
assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28];
assign contextSwitching = CsrPlugin_jumpInterface_valid;
assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000);
assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0);
always @(*) begin
execute_CsrPlugin_illegalAccess = 1'b1;
if(execute_CsrPlugin_csr_3264) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_768) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_836) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_772) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_773) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_833) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_834) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_835) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2816) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2944) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3008) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_4032) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(CsrPlugin_csrMapping_allowCsrSignal) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_illegalAccess = 1'b1;
end
if(when_CsrPlugin_l1302) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_illegalInstruction = 1'b0;
if(when_CsrPlugin_l1136) begin
if(when_CsrPlugin_l1137) begin
execute_CsrPlugin_illegalInstruction = 1'b1;
end
end
end
always @(*) begin
CsrPlugin_selfException_valid = 1'b0;
if(when_CsrPlugin_l1144) begin
CsrPlugin_selfException_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_selfException_payload_code = 4'bxxxx;
if(when_CsrPlugin_l1144) begin
case(CsrPlugin_privilege)
2'b00 : begin
CsrPlugin_selfException_payload_code = 4'b1000;
end
default : begin
CsrPlugin_selfException_payload_code = 4'b1011;
end
endcase
end
end
assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]);
assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL));
always @(*) begin
execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_writeInstruction = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_readInstruction = 1'b0;
end
end
assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck));
assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck));
assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects);
assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal;
assign switch_Misc_l200_2 = execute_INSTRUCTION[13];
always @(*) begin
case(switch_Misc_l200_2)
1'b0 : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1;
end
default : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
end
endcase
end
assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal;
assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR);
assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0));
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
assign execute_MulPlugin_a = execute_RS1;
assign execute_MulPlugin_b = execute_RS2;
assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12];
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_aSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_aSigned = 1'b1;
end
default : begin
execute_MulPlugin_aSigned = 1'b0;
end
endcase
end
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_bSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_bSigned = 1'b0;
end
default : begin
execute_MulPlugin_bSigned = 1'b0;
end
endcase
end
assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0];
assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0];
assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]};
assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]};
assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]};
assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]};
assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1));
assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL);
assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12];
assign memory_DivPlugin_frontendOk = 1'b1;
always @(*) begin
memory_DivPlugin_div_counter_willIncrement = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_div_counter_willIncrement = 1'b1;
end
end
end
always @(*) begin
memory_DivPlugin_div_counter_willClear = 1'b0;
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_div_counter_willClear = 1'b1;
end
end
assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21);
assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement);
always @(*) begin
if(memory_DivPlugin_div_counter_willOverflow) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end else begin
memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext);
end
if(memory_DivPlugin_div_counter_willClear) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end
end
assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20);
assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck);
assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV);
assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done));
assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done));
assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0];
assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]};
assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator);
assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1);
assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0];
assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20);
assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]);
assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck);
assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED);
assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
always @(*) begin
_zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
_zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1;
end
assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext);
assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0);
assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE);
assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready);
assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers);
assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired));
assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready));
assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1;
assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2;
end
default : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]};
end
endcase
end
assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0);
always @(*) begin
CfuPlugin_bus_rsp_rsp_ready = 1'b0;
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers);
end
end
assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid);
assign when_Pipeline_l124 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack));
assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL;
assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1;
assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL;
assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL;
assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1;
assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL;
assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1;
assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL;
assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL;
assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1;
assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL;
assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL;
assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1;
assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck);
assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL;
assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck);
assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL;
assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL;
assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL;
assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck);
assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL;
assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL;
assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL;
assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL;
assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1;
assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck);
assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL;
assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck);
assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL;
assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck);
assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL;
assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck);
assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck);
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000));
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000));
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00));
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0));
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt);
assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck);
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0;
if(execute_CsrPlugin_csr_3264) begin
_zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000;
_zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0;
if(execute_CsrPlugin_csr_768) begin
_zz_CsrPlugin_csrMapping_readDataInit_3[12 : 11] = CsrPlugin_mstatus_MPP;
_zz_CsrPlugin_csrMapping_readDataInit_3[7 : 7] = CsrPlugin_mstatus_MPIE;
_zz_CsrPlugin_csrMapping_readDataInit_3[3 : 3] = CsrPlugin_mstatus_MIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0;
if(execute_CsrPlugin_csr_836) begin
_zz_CsrPlugin_csrMapping_readDataInit_4[11 : 11] = CsrPlugin_mip_MEIP;
_zz_CsrPlugin_csrMapping_readDataInit_4[7 : 7] = CsrPlugin_mip_MTIP;
_zz_CsrPlugin_csrMapping_readDataInit_4[3 : 3] = CsrPlugin_mip_MSIP;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0;
if(execute_CsrPlugin_csr_772) begin
_zz_CsrPlugin_csrMapping_readDataInit_5[11 : 11] = CsrPlugin_mie_MEIE;
_zz_CsrPlugin_csrMapping_readDataInit_5[7 : 7] = CsrPlugin_mie_MTIE;
_zz_CsrPlugin_csrMapping_readDataInit_5[3 : 3] = CsrPlugin_mie_MSIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0;
if(execute_CsrPlugin_csr_833) begin
_zz_CsrPlugin_csrMapping_readDataInit_6[31 : 0] = CsrPlugin_mepc;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0;
if(execute_CsrPlugin_csr_834) begin
_zz_CsrPlugin_csrMapping_readDataInit_7[31 : 31] = CsrPlugin_mcause_interrupt;
_zz_CsrPlugin_csrMapping_readDataInit_7[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0;
if(execute_CsrPlugin_csr_835) begin
_zz_CsrPlugin_csrMapping_readDataInit_8[31 : 0] = CsrPlugin_mtval;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0;
if(execute_CsrPlugin_csr_2816) begin
_zz_CsrPlugin_csrMapping_readDataInit_9[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0;
if(execute_CsrPlugin_csr_2944) begin
_zz_CsrPlugin_csrMapping_readDataInit_10[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0;
if(execute_CsrPlugin_csr_3008) begin
_zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0;
if(execute_CsrPlugin_csr_4032) begin
_zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1;
end
end
assign CsrPlugin_csrMapping_readDataInit = ((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7) | (_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9))) | ((_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11) | _zz_CsrPlugin_csrMapping_readDataInit_12));
assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]);
assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR));
assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR};
assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010);
assign iBusWishbone_BTE = 2'b00;
assign iBusWishbone_SEL = 4'b1111;
assign iBusWishbone_WE = 1'b0;
assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
always @(*) begin
iBusWishbone_CYC = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_CYC = 1'b1;
end
end
always @(*) begin
iBusWishbone_STB = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_STB = 1'b1;
end
end
assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000));
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
assign iBus_rsp_valid = _zz_iBus_rsp_valid;
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
assign iBus_rsp_payload_error = 1'b0;
assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101);
assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid;
assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr;
assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111));
assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4));
assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2);
assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000);
assign dBusWishbone_BTE = 2'b00;
assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111);
assign dBusWishbone_WE = _zz_dBus_cmd_ready_3;
assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data;
assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK);
assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1;
assign dBusWishbone_STB = _zz_dBus_cmd_ready_1;
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
assign dBus_rsp_payload_error = 1'b0;
always @(posedge clk) begin
if(reset) begin
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
IBusCachedPlugin_fetchPc_booted <= 1'b0;
IBusCachedPlugin_fetchPc_inc <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter;
IBusCachedPlugin_rspCounter <= 32'h0;
dataCache_1_io_mem_cmd_rValid <= 1'b0;
dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0;
DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter;
DBusCachedPlugin_rspCounter <= 32'h0;
_zz_7 <= 1'b1;
HazardSimplePlugin_writeBackBuffer_valid <= 1'b0;
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= 1'b0;
CsrPlugin_mstatus_MPP <= 2'b11;
CsrPlugin_mie_MEIE <= 1'b0;
CsrPlugin_mie_MTIE <= 1'b0;
CsrPlugin_mie_MSIE <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
CsrPlugin_interrupt_valid <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
CsrPlugin_hadException <= 1'b0;
execute_CsrPlugin_wfiWake <= 1'b0;
memory_DivPlugin_div_counter_value <= 6'h0;
_zz_CsrPlugin_csrMapping_readDataInit <= 32'h0;
execute_CfuPlugin_hold <= 1'b0;
execute_CfuPlugin_fired <= 1'b0;
CfuPlugin_bus_rsp_rValid <= 1'b0;
execute_arbitration_isValid <= 1'b0;
memory_arbitration_isValid <= 1'b0;
writeBack_arbitration_isValid <= 1'b0;
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0;
_zz_iBusWishbone_ADR <= 3'b000;
_zz_iBus_rsp_valid <= 1'b0;
_zz_dBus_cmd_ready <= 3'b000;
_zz_dBus_rsp_valid <= 1'b0;
end else begin
if(IBusCachedPlugin_fetchPc_correction) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_output_fire) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
end
IBusCachedPlugin_fetchPc_booted <= 1'b1;
if(when_Fetcher_l131) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_output_fire_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b1;
end
if(when_Fetcher_l131_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(when_Fetcher_l158) begin
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
end
if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0));
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
end
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush));
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
end
if(when_Fetcher_l329) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(when_Fetcher_l329_1) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(when_Fetcher_l329_2) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(when_Fetcher_l329_3) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(when_Fetcher_l329_4) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(iBus_rsp_valid) begin
IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001);
end
if(dataCache_1_io_mem_cmd_valid) begin
dataCache_1_io_mem_cmd_rValid <= 1'b1;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_rValid <= 1'b0;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid;
end
if(dBus_rsp_valid) begin
DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001);
end
_zz_7 <= 1'b0;
HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid;
if(when_CsrPlugin_l909) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
end
if(when_CsrPlugin_l909_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
end
if(when_CsrPlugin_l909_2) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
end
if(when_CsrPlugin_l909_3) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
end
CsrPlugin_interrupt_valid <= 1'b0;
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
end
if(CsrPlugin_pipelineLiberator_active) begin
if(when_CsrPlugin_l980) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1;
end
if(when_CsrPlugin_l980_1) begin
CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0;
end
if(when_CsrPlugin_l980_2) begin
CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1;
end
end
if(when_CsrPlugin_l985) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
end
if(CsrPlugin_interruptJump) begin
CsrPlugin_interrupt_valid <= 1'b0;
end
CsrPlugin_hadException <= CsrPlugin_exception;
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
end
default : begin
end
endcase
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_mstatus_MPP <= 2'b00;
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
CsrPlugin_mstatus_MPIE <= 1'b1;
end
default : begin
end
endcase
end
execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake);
memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext;
if(execute_CfuPlugin_schedule) begin
execute_CfuPlugin_hold <= 1'b1;
end
if(CfuPlugin_bus_cmd_ready) begin
execute_CfuPlugin_hold <= 1'b0;
end
if(CfuPlugin_bus_cmd_fire) begin
execute_CfuPlugin_fired <= 1'b1;
end
if(when_CfuPlugin_l171) begin
execute_CfuPlugin_fired <= 1'b0;
end
if(CfuPlugin_bus_rsp_valid) begin
CfuPlugin_bus_rsp_rValid <= 1'b1;
end
if(CfuPlugin_bus_rsp_rsp_ready) begin
CfuPlugin_bus_rsp_rValid <= 1'b0;
end
if(when_Pipeline_l124_61) begin
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l151) begin
execute_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154) begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(when_Pipeline_l151_1) begin
memory_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_1) begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(when_Pipeline_l151_2) begin
writeBack_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_2) begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
if(execute_CsrPlugin_csr_768) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11];
CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_772) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11];
CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_3008) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(when_InstructionCache_l239) begin
if(iBusWishbone_ACK) begin
_zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001);
end
end
_zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK);
if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin
_zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001);
if(_zz_dBus_cmd_ready_4) begin
_zz_dBus_cmd_ready <= 3'b000;
end
end
_zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK);
end
end
always @(posedge clk) begin
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload;
end
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
end
if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin
IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit;
end
if(dataCache_1_io_mem_cmd_ready) begin
dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr;
dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached;
dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address;
dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data;
dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask;
dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size;
dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address;
dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data;
dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size;
dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last;
end
HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address;
HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data;
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
CsrPlugin_mip_MSIP <= softwareInterrupt;
CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001);
if(writeBack_arbitration_isFiring) begin
CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001);
end
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
end
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr);
end
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code;
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr;
end
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_code <= 4'b0111;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_code <= 4'b0011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_code <= 4'b1011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
end
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
CsrPlugin_mepc <= writeBack_PC;
if(CsrPlugin_hadException) begin
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
end
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l126) begin
memory_DivPlugin_div_done <= 1'b1;
end
if(when_MulDivIterativePlugin_l126_1) begin
memory_DivPlugin_div_done <= 1'b0;
end
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator;
memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder;
if(when_MulDivIterativePlugin_l151) begin
memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0];
end
end
end
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_accumulator <= 65'h0;
memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2);
memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1);
memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13]))));
end
externalInterruptArray_regNext <= externalInterruptArray;
if(CfuPlugin_bus_rsp_ready) begin
CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0;
end
if(when_Pipeline_l124) begin
decode_to_execute_PC <= decode_PC;
end
if(when_Pipeline_l124_1) begin
execute_to_memory_PC <= _zz_execute_SRC2;
end
if(when_Pipeline_l124_2) begin
memory_to_writeBack_PC <= memory_PC;
end
if(when_Pipeline_l124_3) begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if(when_Pipeline_l124_4) begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if(when_Pipeline_l124_5) begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if(when_Pipeline_l124_6) begin
decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_7) begin
execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_8) begin
memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_9) begin
decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY;
end
if(when_Pipeline_l124_10) begin
decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL;
end
if(when_Pipeline_l124_11) begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if(when_Pipeline_l124_12) begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if(when_Pipeline_l124_13) begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if(when_Pipeline_l124_14) begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
end
if(when_Pipeline_l124_15) begin
decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL;
end
if(when_Pipeline_l124_16) begin
decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL;
end
if(when_Pipeline_l124_17) begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_18) begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_19) begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_20) begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if(when_Pipeline_l124_21) begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_22) begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_23) begin
decode_to_execute_MEMORY_WR <= decode_MEMORY_WR;
end
if(when_Pipeline_l124_24) begin
execute_to_memory_MEMORY_WR <= execute_MEMORY_WR;
end
if(when_Pipeline_l124_25) begin
memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR;
end
if(when_Pipeline_l124_26) begin
decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT;
end
if(when_Pipeline_l124_27) begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if(when_Pipeline_l124_28) begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL;
end
if(when_Pipeline_l124_29) begin
decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL;
end
if(when_Pipeline_l124_30) begin
execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL;
end
if(when_Pipeline_l124_31) begin
decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL;
end
if(when_Pipeline_l124_32) begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if(when_Pipeline_l124_33) begin
decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL;
end
if(when_Pipeline_l124_34) begin
execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL;
end
if(when_Pipeline_l124_35) begin
memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL;
end
if(when_Pipeline_l124_36) begin
decode_to_execute_IS_MUL <= decode_IS_MUL;
end
if(when_Pipeline_l124_37) begin
execute_to_memory_IS_MUL <= execute_IS_MUL;
end
if(when_Pipeline_l124_38) begin
memory_to_writeBack_IS_MUL <= memory_IS_MUL;
end
if(when_Pipeline_l124_39) begin
decode_to_execute_IS_DIV <= decode_IS_DIV;
end
if(when_Pipeline_l124_40) begin
execute_to_memory_IS_DIV <= execute_IS_DIV;
end
if(when_Pipeline_l124_41) begin
decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
end
if(when_Pipeline_l124_42) begin
decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
end
if(when_Pipeline_l124_43) begin
decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE;
end
if(when_Pipeline_l124_44) begin
decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
end
if(when_Pipeline_l124_45) begin
decode_to_execute_RS1 <= decode_RS1;
end
if(when_Pipeline_l124_46) begin
decode_to_execute_RS2 <= decode_RS2;
end
if(when_Pipeline_l124_47) begin
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
end
if(when_Pipeline_l124_48) begin
decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2;
end
if(when_Pipeline_l124_49) begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if(when_Pipeline_l124_50) begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if(when_Pipeline_l124_51) begin
execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_52) begin
memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_53) begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2;
end
if(when_Pipeline_l124_54) begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1;
end
if(when_Pipeline_l124_55) begin
execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT;
end
if(when_Pipeline_l124_56) begin
execute_to_memory_MUL_LL <= execute_MUL_LL;
end
if(when_Pipeline_l124_57) begin
execute_to_memory_MUL_LH <= execute_MUL_LH;
end
if(when_Pipeline_l124_58) begin
execute_to_memory_MUL_HL <= execute_MUL_HL;
end
if(when_Pipeline_l124_59) begin
execute_to_memory_MUL_HH <= execute_MUL_HH;
end
if(when_Pipeline_l124_60) begin
memory_to_writeBack_MUL_HH <= memory_MUL_HH;
end
if(when_Pipeline_l124_62) begin
memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l124_63) begin
memory_to_writeBack_MUL_LOW <= memory_MUL_LOW;
end
if(when_CsrPlugin_l1264) begin
execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0);
end
if(when_CsrPlugin_l1264_1) begin
execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300);
end
if(when_CsrPlugin_l1264_2) begin
execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344);
end
if(when_CsrPlugin_l1264_3) begin
execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304);
end
if(when_CsrPlugin_l1264_4) begin
execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305);
end
if(when_CsrPlugin_l1264_5) begin
execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341);
end
if(when_CsrPlugin_l1264_6) begin
execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342);
end
if(when_CsrPlugin_l1264_7) begin
execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343);
end
if(when_CsrPlugin_l1264_8) begin
execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00);
end
if(when_CsrPlugin_l1264_9) begin
execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80);
end
if(when_CsrPlugin_l1264_10) begin
execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0);
end
if(when_CsrPlugin_l1264_11) begin
execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0);
end
if(execute_CsrPlugin_csr_836) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_773) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2];
CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0];
end
end
if(execute_CsrPlugin_csr_833) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO;
end
endmodule
module DataCache (
input io_cpu_execute_isValid,
input [31:0] io_cpu_execute_address,
output reg io_cpu_execute_haltIt,
input io_cpu_execute_args_wr,
input [1:0] io_cpu_execute_args_size,
input io_cpu_execute_args_totalyConsistent,
output io_cpu_execute_refilling,
input io_cpu_memory_isValid,
input io_cpu_memory_isStuck,
output io_cpu_memory_isWrite,
input [31:0] io_cpu_memory_address,
input [31:0] io_cpu_memory_mmuRsp_physicalAddress,
input io_cpu_memory_mmuRsp_isIoAccess,
input io_cpu_memory_mmuRsp_isPaging,
input io_cpu_memory_mmuRsp_allowRead,
input io_cpu_memory_mmuRsp_allowWrite,
input io_cpu_memory_mmuRsp_allowExecute,
input io_cpu_memory_mmuRsp_exception,
input io_cpu_memory_mmuRsp_refilling,
input io_cpu_memory_mmuRsp_bypassTranslation,
input io_cpu_writeBack_isValid,
input io_cpu_writeBack_isStuck,
input io_cpu_writeBack_isUser,
output reg io_cpu_writeBack_haltIt,
output io_cpu_writeBack_isWrite,
input [31:0] io_cpu_writeBack_storeData,
output reg [31:0] io_cpu_writeBack_data,
input [31:0] io_cpu_writeBack_address,
output io_cpu_writeBack_mmuException,
output io_cpu_writeBack_unalignedAccess,
output reg io_cpu_writeBack_accessError,
output io_cpu_writeBack_keepMemRspData,
input io_cpu_writeBack_fence_SW,
input io_cpu_writeBack_fence_SR,
input io_cpu_writeBack_fence_SO,
input io_cpu_writeBack_fence_SI,
input io_cpu_writeBack_fence_PW,
input io_cpu_writeBack_fence_PR,
input io_cpu_writeBack_fence_PO,
input io_cpu_writeBack_fence_PI,
input [3:0] io_cpu_writeBack_fence_FM,
output io_cpu_writeBack_exclusiveOk,
output reg io_cpu_redo,
input io_cpu_flush_valid,
output io_cpu_flush_ready,
output reg io_mem_cmd_valid,
input io_mem_cmd_ready,
output reg io_mem_cmd_payload_wr,
output io_mem_cmd_payload_uncached,
output reg [31:0] io_mem_cmd_payload_address,
output [31:0] io_mem_cmd_payload_data,
output [3:0] io_mem_cmd_payload_mask,
output reg [2:0] io_mem_cmd_payload_size,
output io_mem_cmd_payload_last,
input io_mem_rsp_valid,
input io_mem_rsp_payload_last,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [21:0] _zz_ways_0_tags_port0;
reg [31:0] _zz_ways_0_data_port0;
wire [21:0] _zz_ways_0_tags_port;
wire [9:0] _zz_stage0_dataColisions;
wire [9:0] _zz__zz_stageA_dataColisions;
wire [0:0] _zz_when;
wire [2:0] _zz_loader_counter_valueNext;
wire [0:0] _zz_loader_counter_valueNext_1;
wire [1:0] _zz_loader_waysAllocator;
reg _zz_1;
reg _zz_2;
wire haltCpu;
reg tagsReadCmd_valid;
reg [6:0] tagsReadCmd_payload;
reg tagsWriteCmd_valid;
reg [0:0] tagsWriteCmd_payload_way;
reg [6:0] tagsWriteCmd_payload_address;
reg tagsWriteCmd_payload_data_valid;
reg tagsWriteCmd_payload_data_error;
reg [19:0] tagsWriteCmd_payload_data_address;
reg tagsWriteLastCmd_valid;
reg [0:0] tagsWriteLastCmd_payload_way;
reg [6:0] tagsWriteLastCmd_payload_address;
reg tagsWriteLastCmd_payload_data_valid;
reg tagsWriteLastCmd_payload_data_error;
reg [19:0] tagsWriteLastCmd_payload_data_address;
reg dataReadCmd_valid;
reg [9:0] dataReadCmd_payload;
reg dataWriteCmd_valid;
reg [0:0] dataWriteCmd_payload_way;
reg [9:0] dataWriteCmd_payload_address;
reg [31:0] dataWriteCmd_payload_data;
reg [3:0] dataWriteCmd_payload_mask;
wire _zz_ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_error;
wire [19:0] ways_0_tagsReadRsp_address;
wire [21:0] _zz_ways_0_tagsReadRsp_valid_1;
wire _zz_ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRsp;
wire when_DataCache_l634;
wire when_DataCache_l637;
wire when_DataCache_l656;
wire rspSync;
wire rspLast;
reg memCmdSent;
wire io_mem_cmd_fire;
wire when_DataCache_l678;
reg [3:0] _zz_stage0_mask;
wire [3:0] stage0_mask;
wire [0:0] stage0_dataColisions;
wire [0:0] stage0_wayInvalidate;
wire stage0_isAmo;
wire when_DataCache_l763;
reg stageA_request_wr;
reg [1:0] stageA_request_size;
reg stageA_request_totalyConsistent;
wire when_DataCache_l763_1;
reg [3:0] stageA_mask;
wire stageA_isAmo;
wire stageA_isLrsc;
wire [0:0] stageA_wayHits;
wire when_DataCache_l763_2;
reg [0:0] stageA_wayInvalidate;
wire when_DataCache_l763_3;
reg [0:0] stage0_dataColisions_regNextWhen;
wire [0:0] _zz_stageA_dataColisions;
wire [0:0] stageA_dataColisions;
wire when_DataCache_l814;
reg stageB_request_wr;
reg [1:0] stageB_request_size;
reg stageB_request_totalyConsistent;
reg stageB_mmuRspFreeze;
wire when_DataCache_l816;
reg [31:0] stageB_mmuRsp_physicalAddress;
reg stageB_mmuRsp_isIoAccess;
reg stageB_mmuRsp_isPaging;
reg stageB_mmuRsp_allowRead;
reg stageB_mmuRsp_allowWrite;
reg stageB_mmuRsp_allowExecute;
reg stageB_mmuRsp_exception;
reg stageB_mmuRsp_refilling;
reg stageB_mmuRsp_bypassTranslation;
wire when_DataCache_l813;
reg stageB_tagsReadRsp_0_valid;
reg stageB_tagsReadRsp_0_error;
reg [19:0] stageB_tagsReadRsp_0_address;
wire when_DataCache_l813_1;
reg [31:0] stageB_dataReadRsp_0;
wire when_DataCache_l812;
reg [0:0] stageB_wayInvalidate;
wire stageB_consistancyHazard;
wire when_DataCache_l812_1;
reg [0:0] stageB_dataColisions;
wire when_DataCache_l812_2;
reg stageB_unaligned;
wire when_DataCache_l812_3;
reg [0:0] stageB_waysHitsBeforeInvalidate;
wire [0:0] stageB_waysHits;
wire stageB_waysHit;
wire [31:0] stageB_dataMux;
wire when_DataCache_l812_4;
reg [3:0] stageB_mask;
reg stageB_loaderValid;
wire [31:0] stageB_ioMemRspMuxed;
reg stageB_flusher_waitDone;
wire stageB_flusher_hold;
reg [7:0] stageB_flusher_counter;
wire when_DataCache_l842;
wire when_DataCache_l848;
reg stageB_flusher_start;
wire stageB_isAmo;
wire stageB_isAmoCached;
wire stageB_isExternalLsrc;
wire stageB_isExternalAmo;
wire [31:0] stageB_requestDataBypass;
reg stageB_cpuWriteToCache;
wire when_DataCache_l911;
wire stageB_badPermissions;
wire stageB_loadStoreFault;
wire stageB_bypassCache;
wire when_DataCache_l980;
wire when_DataCache_l989;
wire when_DataCache_l994;
wire when_DataCache_l1005;
wire when_DataCache_l1017;
wire when_DataCache_l976;
wire when_DataCache_l1051;
wire when_DataCache_l1060;
reg loader_valid;
reg loader_counter_willIncrement;
wire loader_counter_willClear;
reg [2:0] loader_counter_valueNext;
reg [2:0] loader_counter_value;
wire loader_counter_willOverflowIfInc;
wire loader_counter_willOverflow;
reg [0:0] loader_waysAllocator;
reg loader_error;
wire loader_kill;
reg loader_killReg;
wire when_DataCache_l1075;
wire loader_done;
wire when_DataCache_l1103;
reg loader_valid_regNext;
wire when_DataCache_l1107;
wire when_DataCache_l1110;
(* ram_style = "block" *) reg [21:0] ways_0_tags [0:127];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023];
reg [7:0] _zz_ways_0_datasymbol_read;
reg [7:0] _zz_ways_0_datasymbol_read_1;
reg [7:0] _zz_ways_0_datasymbol_read_2;
reg [7:0] _zz_ways_0_datasymbol_read_3;
assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0);
assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0);
assign _zz_when = 1'b1;
assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement;
assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1};
assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]};
assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}};
always @(posedge clk) begin
if(_zz_ways_0_tagsReadRsp_valid) begin
_zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(*) begin
_zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read};
end
always @(posedge clk) begin
if(_zz_ways_0_dataReadRspMem) begin
_zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload];
end
end
always @(posedge clk) begin
if(dataWriteCmd_payload_mask[0] && _zz_1) begin
ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0];
end
if(dataWriteCmd_payload_mask[1] && _zz_1) begin
ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8];
end
if(dataWriteCmd_payload_mask[2] && _zz_1) begin
ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16];
end
if(dataWriteCmd_payload_mask[3] && _zz_1) begin
ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(when_DataCache_l637) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(when_DataCache_l634) begin
_zz_2 = 1'b1;
end
end
assign haltCpu = 1'b0;
assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck));
assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0;
assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0];
assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1];
assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2];
assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck));
assign ways_0_dataReadRspMem = _zz_ways_0_data_port0;
assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0];
assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]);
assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]);
always @(*) begin
tagsReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
tagsReadCmd_valid = 1'b1;
end
end
always @(*) begin
tagsReadCmd_payload = 7'bxxxxxxx;
if(when_DataCache_l656) begin
tagsReadCmd_payload = io_cpu_execute_address[11 : 5];
end
end
always @(*) begin
dataReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
dataReadCmd_valid = 1'b1;
end
end
always @(*) begin
dataReadCmd_payload = 10'bxxxxxxxxxx;
if(when_DataCache_l656) begin
dataReadCmd_payload = io_cpu_execute_address[11 : 2];
end
end
always @(*) begin
tagsWriteCmd_valid = 1'b0;
if(when_DataCache_l842) begin
tagsWriteCmd_valid = 1'b1;
end
if(when_DataCache_l1051) begin
tagsWriteCmd_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_valid = 1'b1;
end
end
always @(*) begin
tagsWriteCmd_payload_way = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_way = 1'b1;
end
if(loader_done) begin
tagsWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
tagsWriteCmd_payload_address = 7'bxxxxxxx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_address = stageB_flusher_counter[6:0];
end
if(loader_done) begin
tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5];
end
end
always @(*) begin
tagsWriteCmd_payload_data_valid = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_data_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg));
end
end
always @(*) begin
tagsWriteCmd_payload_data_error = 1'bx;
if(loader_done) begin
tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error));
end
end
always @(*) begin
tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx;
if(loader_done) begin
tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12];
end
end
always @(*) begin
dataWriteCmd_valid = 1'b0;
if(stageB_cpuWriteToCache) begin
if(when_DataCache_l911) begin
dataWriteCmd_valid = 1'b1;
end
end
if(when_DataCache_l1051) begin
dataWriteCmd_valid = 1'b0;
end
if(when_DataCache_l1075) begin
dataWriteCmd_valid = 1'b1;
end
end
always @(*) begin
dataWriteCmd_payload_way = 1'bx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_way = stageB_waysHits;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
dataWriteCmd_payload_address = 10'bxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2];
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value};
end
end
always @(*) begin
dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_data = io_mem_rsp_payload_data;
end
end
always @(*) begin
dataWriteCmd_payload_mask = 4'bxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_mask = 4'b0000;
if(_zz_when[0]) begin
dataWriteCmd_payload_mask[3 : 0] = stageB_mask;
end
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_mask = 4'b1111;
end
end
assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck));
always @(*) begin
io_cpu_execute_haltIt = 1'b0;
if(when_DataCache_l842) begin
io_cpu_execute_haltIt = 1'b1;
end
end
assign rspSync = 1'b1;
assign rspLast = 1'b1;
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck);
always @(*) begin
_zz_stage0_mask = 4'bxxxx;
case(io_cpu_execute_args_size)
2'b00 : begin
_zz_stage0_mask = 4'b0001;
end
2'b01 : begin
_zz_stage0_mask = 4'b0011;
end
2'b10 : begin
_zz_stage0_mask = 4'b1111;
end
default : begin
end
endcase
end
assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]);
assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stage0_wayInvalidate = 1'b0;
assign stage0_isAmo = 1'b0;
assign when_DataCache_l763 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck);
assign io_cpu_memory_isWrite = stageA_request_wr;
assign stageA_isAmo = 1'b0;
assign stageA_isLrsc = 1'b0;
assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid);
assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck);
assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions);
assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_mmuRspFreeze = 1'b0;
if(when_DataCache_l1110) begin
stageB_mmuRspFreeze = 1'b1;
end
end
assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze));
assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck);
assign stageB_consistancyHazard = 1'b0;
assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck);
assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate));
assign stageB_waysHit = (stageB_waysHits != 1'b0);
assign stageB_dataMux = stageB_dataReadRsp_0;
assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_loaderValid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
if(io_mem_cmd_ready) begin
stageB_loaderValid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
stageB_loaderValid = 1'b0;
end
end
assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0];
always @(*) begin
io_cpu_writeBack_haltIt = 1'b1;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
if(when_DataCache_l980) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end else begin
if(when_DataCache_l989) begin
if(when_DataCache_l994) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
assign stageB_flusher_hold = 1'b0;
assign when_DataCache_l842 = (! stageB_flusher_counter[7]);
assign when_DataCache_l848 = (! stageB_flusher_hold);
assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]);
assign stageB_isAmo = 1'b0;
assign stageB_isAmoCached = 1'b0;
assign stageB_isExternalLsrc = 1'b0;
assign stageB_isExternalAmo = 1'b0;
assign stageB_requestDataBypass = io_cpu_writeBack_storeData;
always @(*) begin
stageB_cpuWriteToCache = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
stageB_cpuWriteToCache = 1'b1;
end
end
end
end
end
assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit);
assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)));
assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions));
always @(*) begin
io_cpu_redo = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
if(when_DataCache_l1005) begin
io_cpu_redo = 1'b1;
end
end
end
end
end
if(when_DataCache_l1060) begin
io_cpu_redo = 1'b1;
end
if(when_DataCache_l1107) begin
io_cpu_redo = 1'b1;
end
end
always @(*) begin
io_cpu_writeBack_accessError = 1'b0;
if(stageB_bypassCache) begin
io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error);
end else begin
io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging)));
end
end
assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging);
assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned);
assign io_cpu_writeBack_isWrite = stageB_request_wr;
always @(*) begin
io_mem_cmd_valid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
io_mem_cmd_valid = (! memCmdSent);
end else begin
if(when_DataCache_l989) begin
if(stageB_request_wr) begin
io_mem_cmd_valid = 1'b1;
end
end else begin
if(when_DataCache_l1017) begin
io_mem_cmd_valid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_mem_cmd_valid = 1'b0;
end
end
always @(*) begin
io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_address[4 : 0] = 5'h0;
end
end
end
end
end
assign io_mem_cmd_payload_last = 1'b1;
always @(*) begin
io_mem_cmd_payload_wr = stageB_request_wr;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_wr = 1'b0;
end
end
end
end
end
assign io_mem_cmd_payload_mask = stageB_mask;
assign io_mem_cmd_payload_data = stageB_requestDataBypass;
assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess;
always @(*) begin
io_mem_cmd_payload_size = {1'd0, stageB_request_size};
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_size = 3'b101;
end
end
end
end
end
assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo);
assign io_cpu_writeBack_keepMemRspData = 1'b0;
assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready);
assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached)));
assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready);
assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0));
assign when_DataCache_l1017 = (! memCmdSent);
assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc);
always @(*) begin
if(stageB_bypassCache) begin
io_cpu_writeBack_data = stageB_ioMemRspMuxed;
end else begin
io_cpu_writeBack_data = stageB_dataMux;
end
end
assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess);
assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard));
always @(*) begin
loader_counter_willIncrement = 1'b0;
if(when_DataCache_l1075) begin
loader_counter_willIncrement = 1'b1;
end
end
assign loader_counter_willClear = 1'b0;
assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111);
assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement);
always @(*) begin
loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext);
if(loader_counter_willClear) begin
loader_counter_valueNext = 3'b000;
end
end
assign loader_kill = 1'b0;
assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast);
assign loader_done = loader_counter_willOverflow;
assign when_DataCache_l1103 = (! loader_valid);
assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext));
assign io_cpu_execute_refilling = loader_valid;
assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid);
always @(posedge clk) begin
tagsWriteLastCmd_valid <= tagsWriteCmd_valid;
tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way;
tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address;
tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid;
tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error;
tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address;
if(when_DataCache_l763) begin
stageA_request_wr <= io_cpu_execute_args_wr;
stageA_request_size <= io_cpu_execute_args_size;
stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent;
end
if(when_DataCache_l763_1) begin
stageA_mask <= stage0_mask;
end
if(when_DataCache_l763_2) begin
stageA_wayInvalidate <= stage0_wayInvalidate;
end
if(when_DataCache_l763_3) begin
stage0_dataColisions_regNextWhen <= stage0_dataColisions;
end
if(when_DataCache_l814) begin
stageB_request_wr <= stageA_request_wr;
stageB_request_size <= stageA_request_size;
stageB_request_totalyConsistent <= stageA_request_totalyConsistent;
end
if(when_DataCache_l816) begin
stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress;
stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess;
stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging;
stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead;
stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite;
stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute;
stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception;
stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling;
stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation;
end
if(when_DataCache_l813) begin
stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid;
stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error;
stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address;
end
if(when_DataCache_l813_1) begin
stageB_dataReadRsp_0 <= ways_0_dataReadRsp;
end
if(when_DataCache_l812) begin
stageB_wayInvalidate <= stageA_wayInvalidate;
end
if(when_DataCache_l812_1) begin
stageB_dataColisions <= stageA_dataColisions;
end
if(when_DataCache_l812_2) begin
stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00);
end
if(when_DataCache_l812_3) begin
stageB_waysHitsBeforeInvalidate <= stageA_wayHits;
end
if(when_DataCache_l812_4) begin
stageB_mask <= stageA_mask;
end
loader_valid_regNext <= loader_valid;
end
always @(posedge clk) begin
if(reset) begin
memCmdSent <= 1'b0;
stageB_flusher_waitDone <= 1'b0;
stageB_flusher_counter <= 8'h0;
stageB_flusher_start <= 1'b1;
loader_valid <= 1'b0;
loader_counter_value <= 3'b000;
loader_waysAllocator <= 1'b1;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end else begin
if(io_mem_cmd_fire) begin
memCmdSent <= 1'b1;
end
if(when_DataCache_l678) begin
memCmdSent <= 1'b0;
end
if(io_cpu_flush_ready) begin
stageB_flusher_waitDone <= 1'b0;
end
if(when_DataCache_l842) begin
if(when_DataCache_l848) begin
stageB_flusher_counter <= (stageB_flusher_counter + 8'h01);
end
end
stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo));
if(stageB_flusher_start) begin
stageB_flusher_waitDone <= 1'b1;
stageB_flusher_counter <= 8'h0;
end
`ifndef SYNTHESIS
`ifdef FORMAL
assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck)));
`else
if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin
$display("ERROR writeBack stuck by another plugin is not allowed");
end
`endif
`endif
if(stageB_loaderValid) begin
loader_valid <= 1'b1;
end
loader_counter_value <= loader_counter_valueNext;
if(loader_kill) begin
loader_killReg <= 1'b1;
end
if(when_DataCache_l1075) begin
loader_error <= (loader_error || io_mem_rsp_payload_error);
end
if(loader_done) begin
loader_valid <= 1'b0;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end
if(when_DataCache_l1103) begin
loader_waysAllocator <= _zz_loader_waysAllocator[0:0];
end
end
end
endmodule
module InstructionCache (
input io_flush,
input io_cpu_prefetch_isValid,
output reg io_cpu_prefetch_haltIt,
input [31:0] io_cpu_prefetch_pc,
input io_cpu_fetch_isValid,
input io_cpu_fetch_isStuck,
input io_cpu_fetch_isRemoved,
input [31:0] io_cpu_fetch_pc,
output [31:0] io_cpu_fetch_data,
input [31:0] io_cpu_fetch_mmuRsp_physicalAddress,
input io_cpu_fetch_mmuRsp_isIoAccess,
input io_cpu_fetch_mmuRsp_isPaging,
input io_cpu_fetch_mmuRsp_allowRead,
input io_cpu_fetch_mmuRsp_allowWrite,
input io_cpu_fetch_mmuRsp_allowExecute,
input io_cpu_fetch_mmuRsp_exception,
input io_cpu_fetch_mmuRsp_refilling,
input io_cpu_fetch_mmuRsp_bypassTranslation,
output [31:0] io_cpu_fetch_physicalAddress,
input io_cpu_decode_isValid,
input io_cpu_decode_isStuck,
input [31:0] io_cpu_decode_pc,
output [31:0] io_cpu_decode_physicalAddress,
output [31:0] io_cpu_decode_data,
output io_cpu_decode_cacheMiss,
output io_cpu_decode_error,
output io_cpu_decode_mmuRefilling,
output io_cpu_decode_mmuException,
input io_cpu_decode_isUser,
input io_cpu_fill_valid,
input [31:0] io_cpu_fill_payload,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [2:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [31:0] _zz_banks_0_port1;
reg [21:0] _zz_ways_0_tags_port1;
wire [21:0] _zz_ways_0_tags_port;
reg _zz_1;
reg _zz_2;
reg lineLoader_fire;
reg lineLoader_valid;
(* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ;
reg lineLoader_hadError;
reg lineLoader_flushPending;
reg [7:0] lineLoader_flushCounter;
wire when_InstructionCache_l338;
reg _zz_when_InstructionCache_l342;
wire when_InstructionCache_l342;
wire when_InstructionCache_l351;
reg lineLoader_cmdSent;
wire io_mem_cmd_fire;
wire when_Utils_l357;
reg lineLoader_wayToAllocate_willIncrement;
wire lineLoader_wayToAllocate_willClear;
wire lineLoader_wayToAllocate_willOverflowIfInc;
wire lineLoader_wayToAllocate_willOverflow;
(* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ;
wire lineLoader_write_tag_0_valid;
wire [6:0] lineLoader_write_tag_0_payload_address;
wire lineLoader_write_tag_0_payload_data_valid;
wire lineLoader_write_tag_0_payload_data_error;
wire [19:0] lineLoader_write_tag_0_payload_data_address;
wire lineLoader_write_data_0_valid;
wire [9:0] lineLoader_write_data_0_payload_address;
wire [31:0] lineLoader_write_data_0_payload_data;
wire when_InstructionCache_l401;
wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem;
wire _zz_fetchStage_read_banksValue_0_dataMem_1;
wire [31:0] fetchStage_read_banksValue_0_dataMem;
wire [31:0] fetchStage_read_banksValue_0_data;
wire [6:0] _zz_fetchStage_read_waysValues_0_tag_valid;
wire _zz_fetchStage_read_waysValues_0_tag_valid_1;
wire fetchStage_read_waysValues_0_tag_valid;
wire fetchStage_read_waysValues_0_tag_error;
wire [19:0] fetchStage_read_waysValues_0_tag_address;
wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2;
wire fetchStage_hit_hits_0;
wire fetchStage_hit_valid;
wire fetchStage_hit_error;
wire [31:0] fetchStage_hit_data;
wire [31:0] fetchStage_hit_word;
wire when_InstructionCache_l435;
reg [31:0] io_cpu_fetch_data_regNextWhen;
wire when_InstructionCache_l459;
reg [31:0] decodeStage_mmuRsp_physicalAddress;
reg decodeStage_mmuRsp_isIoAccess;
reg decodeStage_mmuRsp_isPaging;
reg decodeStage_mmuRsp_allowRead;
reg decodeStage_mmuRsp_allowWrite;
reg decodeStage_mmuRsp_allowExecute;
reg decodeStage_mmuRsp_exception;
reg decodeStage_mmuRsp_refilling;
reg decodeStage_mmuRsp_bypassTranslation;
wire when_InstructionCache_l459_1;
reg decodeStage_hit_valid;
wire when_InstructionCache_l459_2;
reg decodeStage_hit_error;
(* ram_style = "block" *) reg [31:0] banks_0 [0:1023];
(* ram_style = "block" *) reg [21:0] ways_0_tags [0:127];
assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
always @(posedge clk) begin
if(_zz_1) begin
banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin
_zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin
_zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(lineLoader_write_data_0_valid) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(lineLoader_write_tag_0_valid) begin
_zz_2 = 1'b1;
end
end
always @(*) begin
lineLoader_fire = 1'b0;
if(io_mem_rsp_valid) begin
if(when_InstructionCache_l401) begin
lineLoader_fire = 1'b1;
end
end
end
always @(*) begin
io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
if(when_InstructionCache_l338) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(when_InstructionCache_l342) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(io_flush) begin
io_cpu_prefetch_haltIt = 1'b1;
end
end
assign when_InstructionCache_l338 = (! lineLoader_flushCounter[7]);
assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342);
assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0};
assign io_mem_cmd_payload_size = 3'b101;
assign when_Utils_l357 = (! lineLoader_valid);
always @(*) begin
lineLoader_wayToAllocate_willIncrement = 1'b0;
if(when_Utils_l357) begin
lineLoader_wayToAllocate_willIncrement = 1'b1;
end
end
assign lineLoader_wayToAllocate_willClear = 1'b0;
assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7]));
assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]);
assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7];
assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12];
assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1);
assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex};
assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111);
assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2];
assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck);
assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1;
assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0];
assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 5];
assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck);
assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1;
assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0];
assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1];
assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2];
assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12]));
assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0);
assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
assign fetchStage_hit_data = fetchStage_read_banksValue_0_data;
assign fetchStage_hit_word = fetchStage_hit_data;
assign io_cpu_fetch_data = fetchStage_hit_word;
assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen;
assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress;
assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))));
assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling;
assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)));
assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
always @(posedge clk) begin
if(reset) begin
lineLoader_valid <= 1'b0;
lineLoader_hadError <= 1'b0;
lineLoader_flushPending <= 1'b1;
lineLoader_cmdSent <= 1'b0;
lineLoader_wordIndex <= 3'b000;
end else begin
if(lineLoader_fire) begin
lineLoader_valid <= 1'b0;
end
if(lineLoader_fire) begin
lineLoader_hadError <= 1'b0;
end
if(io_cpu_fill_valid) begin
lineLoader_valid <= 1'b1;
end
if(io_flush) begin
lineLoader_flushPending <= 1'b1;
end
if(when_InstructionCache_l351) begin
lineLoader_flushPending <= 1'b0;
end
if(io_mem_cmd_fire) begin
lineLoader_cmdSent <= 1'b1;
end
if(lineLoader_fire) begin
lineLoader_cmdSent <= 1'b0;
end
if(io_mem_rsp_valid) begin
lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001);
if(io_mem_rsp_payload_error) begin
lineLoader_hadError <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if(io_cpu_fill_valid) begin
lineLoader_address <= io_cpu_fill_payload;
end
if(when_InstructionCache_l338) begin
lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01);
end
_zz_when_InstructionCache_l342 <= lineLoader_flushCounter[7];
if(when_InstructionCache_l351) begin
lineLoader_flushCounter <= 8'h0;
end
if(when_InstructionCache_l435) begin
io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data;
end
if(when_InstructionCache_l459) begin
decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress;
decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess;
decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging;
decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead;
decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite;
decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute;
decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception;
decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling;
decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation;
end
if(when_InstructionCache_l459_1) begin
decodeStage_hit_valid <= fetchStage_hit_valid;
end
if(when_InstructionCache_l459_2) begin
decodeStage_hit_error <= fetchStage_hit_error;
end
end
endmodule
|
/*** Defines ***/
/*System because it's special*/
`define OPC_SYS 5'b110000;
module decode_32(
input[31:0] insn_in, //input instruction
input reset_in, //input reset line
input clk_in, //input clock
input[31:0] insn_pc_in, //input program counter address
input stall_in, //input stall signal
/*Operand output connections*/
output reg [4:0] reg_select_out, //output register bank select
output reg [4:0] rsa_out, //output of register a address
output reg [4:0] rsb_out, //output of register b address
output reg [4:0] rd_out, //output of destination register address
output reg [20:0] imm_out, //output of immediate value
//using largest immediate value
//size
/*Control Signals*/
output reg [3:0] aluop_out,
output reg jlnk_out,
output reg pc_change_rel_out,
output reg pc_change_abs_out,
output reg mem_read_out,
output reg mem_write_out,
/*Flag outputs*/
output reg nri_flg_out, //output of 'not real instruction' flag
output reg [1:0] branch_funct_out, //branch function; taken from the funct field
output reg stall_out,
/*System instruction signals*/
output reg memsync_out,
output reg syscall_out,
output reg pem_inc_req_out,
output reg pem_dec_req_out,
output reg [7:0] sysreg_addr_out, //for reading and writing to system registers
output reg [7:0] sysreg_data_out,
input [7:0] sysreg_data_in,
/* Misc. Outputs*/
output reg [31:0] insn_pc_out,
/*Co-processor connections*/
output reg [30:0] cp_insn_out
);
/* Pipeline information */
localparam PIPELINE_LENGTH = 5;
localparam PIPELINEL_2 = $clog2(PIPELINE_LENGTH);
/*Defining opcodes to make things easier*/
localparam OPC_INT = 5'b010011;
localparam OPC_IMM = 5'b010110;
localparam OPC_LI = 5'b010000;
localparam OPC_BRANCH = 5'b001101;
localparam OPC_JMP = 5'b001100;
localparam OPC_JLNK = 5'b000100;
localparam OPC_LD = 5'b011110;
localparam OPC_ST = 5'b011101;
/*Wire connections*/
wire[5:0] opcode_w;
wire[4:0] rsa_addr_w;
wire[4:0] rsb_addr_w;
wire[4:0] rd_addr_w;
wire[3:0] aluop_w;
/*Funct Variants*/
wire[1:0] funct_ld_w;
wire[1:0] funct_st_w;
wire[3:0] dsel_li_w;
wire[1:0] funct_b_w;
wire[7:0] funct_sys_w;
/*Immediate Variants*/
wire[11:0] imm_i_w;
wire[13:0] imm_ld_w;
wire[15:0] imm_li_w;
wire[13:0] imm_st_w;
wire[20:0] imm_j_w;
wire[13:0] imm_b_w;
wire[7:0] imm_sys_w;
/*OPCode generated signals*/
/*Resouce usage*/
wire use_alu_w;
wire is_cp_insn_w; //is coprocessor instruction
wire pc_change_w; //instruction can change the pc
wire mem_access_w;
wire pc_link_w; //jump that requires linking to ra
wire sys_insn_w;
/*secondary calculated resource usage*/
wire mem_read_req_w;
wire mem_write_req_w;
wire pc_abs_w;
wire pc_rel_w;
wire memsync_w;
/*ALU op signal selection*/
wire aluop_intsig_w; // integer/register operation field used
wire aluop_addsig_w; // fixed add operation
wire aluop_bsig_w; // branch operation decode value
/*Operand usage*/
wire use_rd_w;
wire use_rsa_w;
wire use_rsb_w;
wire use_imm_w;
wire [4:0] imm_sel_w;
/*Assignments*/
assign opcode_w = insn_in[31:26];
assign rsa_addr_w = insn_in[20:16];
assign rsb_addr_w = insn_in[15:11];
assign rd_addr_w = insn_in[25:21];
assign aluop_w = insn_in[3:0];
assign funct_ld_w = insn_in[15:14];
assign funct_st_w = insn_in[25:24];
assign dsel_li_w = insn_in[20:16];
assign funct_b_w = insn_in[1:0];
assign funct_sys_w = insn_in[15:8];
assign imm_i_w = insn_in[15:4];
assign imm_ld_w = insn_in[13:0];
assign imm_li_w = insn_in[15:0];
assign imm_st_w = {insn_in[13:11],insn_in[10:0]};
assign imm_j_w = {insn_in[25:21],insn_in[15:0]};
assign imm_b_w = {insn_in[25:21],insn_in[10:2]};
assign imm_sys_w = insn_in[7:0];
assign imm_sel_w = (use_imm_w) ?opcode_w[4:0] : 5'b0; //if using immediate, need to determine output
assign is_cp_insn_w = opcode_w[5];
assign pc_change_w = ~opcode_w[4];
assign mem_access_w = opcode_w[4] & opcode_w[3];
assign pc_link_w = ~(opcode_w[4] | opcode_w[3]);
assign sys_insn_w = is_cp_insn_w & opcode_w[4];
assign memsync_w = (sys_insn_w && ( (funct_sys_w & 8'h04) || (funct_sys_w & 8'b0 ) )); //if sync or syscall, need to sync memory
assign use_rd_w = (opcode_w[1] | opcode_w[0]) & (~opcode_w[2] | opcode_w[1]);
assign use_rsa_w = (opcode_w[2] | opcode_w[1]);
assign use_rsb_w = (opcode_w[2] & opcode_w[0]) | ( opcode_w[1] & opcode_w[0] );
assign use_imm_w = (opcode_w[2] | ~opcode_w[1]);
assign aluop_intsig_w = (opcode_w[4] & opcode_w[1]) & ~(opcode_w[5] & opcode_w[3]) & (opcode_w[2] ^ opcode_w[0]); //used for imm and int
assign aluop_addsig_w = pc_rel_w;//used for jump (relative)
assign aluop_bsig_w = (pc_change_w) & (use_rsb_w); //is a branch
/*Memory read/write signal creation*/
/*use_rsb has simpler gate usage, which is better than using use_rd for
* determining read or writes */
assign mem_write_req_w = (mem_access_w & use_rsb_w); //store instructions use rsb, not rd
assign mem_read_req_w = (mem_access_w & ~use_rsb_w); //load instructions use rd, not rsb
assign pc_rel_w = (pc_change_w & ( (opcode_w[2:0] && 3'b101) || (rsa_addr_w == (5'b0)) ) ); //not jr/jrl or branch
assign pc_abs_w = (pc_change_w & ~( (opcode_w[2:0] && 3'b101) || (rsa_addr_w == (5'b0)) ) );
/* Internal registers*/
reg [PIPELINEL_2 - 1 : 0] memstall_count; //counter for stalls in pipeline
/*** LOGIC SECTION ****/
always@(~reset_in or stall_in) begin //while in reset or stalling
reg_select_out <= 5'b0; //output register bank select
rsa_out <= 5'b0; //output of register a address
rsb_out <= 5'b0; //output of register b address
rd_out <= 5'b0; //output of destination register address
imm_out <= 21'b0; //output of immediate value
//using largest immediate value
//size
aluop_out <= 4'b0;
jlnk_out <= 1'b0;
pc_change_rel_out <= 1'b0;
pc_change_abs_out <= 1'b0;
mem_read_out <= 1'b0;
mem_write_out <= 1'b0;
nri_flg_out <= 1'b0; //output of 'not real instruction' flag
branch_funct_out <= 2'b0; //branch function; taken from the funct field
memsync_out <= 1'b0;
syscall_out <= 1'b0;
pem_inc_req_out <= 1'b0;
pem_dec_req_out <= 1'b0;
sysreg_addr_out <= 8'b0;
sysreg_data_out <= 8'b0;
insn_pc_out <= 32'h0;
cp_insn_out <= 32'h0;
stall_out <= 1'b0;
end
always@(posedge clk_in, reset_in, ~stall_in) begin //make sure that reset has to be high for this to work
/*** Determining ALUOP value ***/
if (aluop_intsig_w) begin //uses ALUOP field
aluop_out = aluop_w;
end else if (aluop_addsig_w) begin //just add, so jumps
aluop_out = 4'b0000;
end else if (aluop_bsig_w) begin //branches, so need to decode the funct field
aluop_out = 4'b1100; //like compare insn, but does different things
end else begin
aluop_out = 4'b1111; //unused code, use as nop? need to define in documentation
end
/*Branch funct assignment*/
branch_funct_out = (aluop_bsig_w) ? (funct_b_w) : (2'b0);
/*Co-processor instruction output to co-processor decode*/
cp_insn_out <= (is_cp_insn_w) ? insn_in : 30'b0; //if is a co-processor instruction, output instruction to
//co-processor decoder
/*Memory access signal output*/
mem_write_out <= mem_write_req_w;
mem_read_out <= mem_read_req_w;
pc_change_rel_out <= pc_rel_w;
pc_change_abs_out <= pc_abs_w;
/*Register selection and outputs*/
if(imm_sel_w == OPC_LI) begin //determine which register bank to use, from DSEL
reg_select_out <= { 1'b0, dsel_li_w}; //lower 2 bits determine file, upper two bits determine signed, upper or lower 16 bits
end else if(sys_insn_w && ( funct_sys_w & (8'h02 ))) begin //if system instruction, need to check if accessing system registers, last two bits matter here
reg_select_out <= 5'b10000; //upper most bit is for accessing special purpose registers; maps to memory address to make 8 bit registers easier
end else begin //everything else should just use general purpose register file
reg_select_out <= 5'b0;
end
rsa_out <= (use_rsa_w) ? rsa_addr_w : 5'b0;
rsb_out <= (use_rsb_w) ? rsb_addr_w : 5'b0;
rd_out <= (use_rd_w ) ? rd_addr_w : 5'b0;
insn_pc_out <= insn_pc_in; //may need to alter this value, but unsure so leave it
/*** Selecting immediate values ***/
if(!is_cp_insn_w) begin
case (imm_sel_w) //figure out what immediate value to use
OPC_IMM: imm_out <= {9'b0 ,imm_i_w};
OPC_LD: imm_out <= {7'b0, imm_ld_w};
OPC_ST: imm_out <= {7'b0, imm_st_w};
OPC_LI: imm_out <= {6'b0, imm_li_w};
OPC_JMP: imm_out <= imm_j_w;
OPC_JLNK: imm_out <= imm_j_w;
OPC_BRANCH: imm_out <= {7'b0, imm_b_w};
default: imm_out <= 21'b0; //this may be redundant or cause errors, not sure yet
endcase
/*co processor instruction immediates; right now just system insn due to direct
* affects on main core pipeline */
end else if(opcode_w[5] & opcode_w[4] & ~(opcode_w[3] | opcode_w[2] | opcode_w[1] | opcode_w[0] ) )begin
/*just system instructions*/
imm_out <= imm_sys_w;
end else begin
imm_out <= 21'b0; //no immediate, default to 0's
end
/*System decoding*/
if( sys_insn_w) begin //if actually a system instruction
case (funct_sys_w)
8'h00: begin //system call
syscall_out <= 1'b1;
memsync_out <= 1'b0;
pem_inc_req_out <= 1'b0;
pem_dec_req_out <= 1'b0;
end
// 8'h01: begin //system return
// end
8'h04: begin //memory sync
syscall_out <= 1'b0;
memsync_out <= 1'b1;
pem_inc_req_out <= 1'b0;
pem_dec_req_out <= 1'b0;
stall_out <= 1'b1;
end
default: begin
syscall_out <= 1'b0;
memsync_out <= 1'b0;
pem_inc_req_out <= 1'b0;
pem_dec_req_out <= 1'b0;
end
endcase
end
/* Ensure stall_out from memory sync doesn't make the pipeline get stuck */
if(memsync_w) begin
if(memstall_count > PIPELINE_LENGTH) begin
memstall_count <= 0;
memsync_out <= 1'b0;
end
else begin
memstall_count = memstall_count + 1;
end
end
end
endmodule
|
/* This file is part of JT51.
JT51 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-4-2017
*/
module jt51_phrom
(
input [4:0] addr,
input clk,
input cen,
output reg [45:0] ph
);
reg [45:0] sinetable[31:0];
initial
begin
sinetable[5'd0 ] = 46'b0001100000100100010001000010101010101001010010;
sinetable[5'd1 ] = 46'b0001100000110100000100000010010001001101000001;
sinetable[5'd2 ] = 46'b0001100000110100000100110010001011001101100000;
sinetable[5'd3 ] = 46'b0001110000010000000000110010110001001101110010;
sinetable[5'd4 ] = 46'b0001110000010000001100000010111010001101101001;
sinetable[5'd5 ] = 46'b0001110000010100001001100010000000101101111010;
sinetable[5'd6 ] = 46'b0001110000010100001101100010010011001101011010;
sinetable[5'd7 ] = 46'b0001110000011100000101010010111000101111111100;
sinetable[5'd8 ] = 46'b0001110000111000000001110010101110001101110111;
sinetable[5'd9 ] = 46'b0001110000111000010100111000011101011010100110;
sinetable[5'd10] = 46'b0001110000111100011000011000111100001001111010;
sinetable[5'd11] = 46'b0001110000111100011100111001101011001001110111;
sinetable[5'd12] = 46'b0100100001010000010001011001001000111010110111;
sinetable[5'd13] = 46'b0100100001010100010001001001110001111100101010;
sinetable[5'd14] = 46'b0100100001010100010101101101111110100101000110;
sinetable[5'd15] = 46'b0100100011100000001000011001010110101101111001;
sinetable[5'd16] = 46'b0100100011100100001000101011100101001011101111;
sinetable[5'd17] = 46'b0100100011101100000111011010000001011010110001;
sinetable[5'd18] = 46'b0100110011001000000111101010000010111010111111;
sinetable[5'd19] = 46'b0100110011001100001011011110101110110110000001;
sinetable[5'd20] = 46'b0100110011101000011010111011001010001101110001;
sinetable[5'd21] = 46'b0100110011101101011010110101111001010100001111;
sinetable[5'd22] = 46'b0111000010000001010111000101010101010110010111;
sinetable[5'd23] = 46'b0111000010000101010111110111110101010010111011;
sinetable[5'd24] = 46'b0111000010110101101000101100001000010000011001;
sinetable[5'd25] = 46'b0111010010011001100100011110100100010010010010;
sinetable[5'd26] = 46'b0111010010111010100101100101000000110100100011;
sinetable[5'd27] = 46'b1010000010011010101101011101100001110010011010;
sinetable[5'd28] = 46'b1010000010111111111100100111010100010000111001;
sinetable[5'd29] = 46'b1010010111110100110010001100111001010110100000;
sinetable[5'd30] = 46'b1011010111010011111011011110000100110010100001;
sinetable[5'd31] = 46'b1110011011110001111011100111100001110110100111;
end
always @ (posedge clk) if(cen)
ph <= sinetable[addr];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SRDLRTP_BEHAVIORAL_PP_V
/**
* srdlrtp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pkg_sn/sky130_fd_sc_lp__udp_dlatch_pr_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__srdlrtp (
Q ,
RESET_B,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_lp__udp_dlatch$PR_pp$PKG$sN dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( SLEEP_B === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
bufif1 bufif10 (Q , buf_Q, VPWR );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLRTP_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21OI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A21OI_FUNCTIONAL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a21oi (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21OI_FUNCTIONAL_V
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_31x128.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1.30 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module sfifo_31x128 (
data,
wrreq,
rdreq,
clock,
aclr,
q,
full,
empty,
usedw,
almost_full);
input [30:0] data;
input wrreq;
input rdreq;
input clock;
input aclr;
output [30:0] q;
output full;
output empty;
output [6:0] usedw;
output almost_full;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "31"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "3"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "31"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "3"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: USED_PORT: data 0 0 31 0 INPUT NODEFVAL data[30..0]
// Retrieval info: USED_PORT: q 0 0 31 0 OUTPUT NODEFVAL q[30..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw[6..0]
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: CONNECT: @data 0 0 31 0 data 0 0 31 0
// Retrieval info: CONNECT: q 0 0 31 0 @q 0 0 31 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128_wave*.jpg FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_TB_V
`define SKY130_FD_SC_HS__SDFSTP_TB_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfstp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 SCD = 1'b1;
#180 SCE = 1'b1;
#200 SET_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 SCD = 1'b0;
#300 SCE = 1'b0;
#320 SET_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SET_B = 1'b1;
#440 SCE = 1'b1;
#460 SCD = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SET_B = 1'bx;
#560 SCE = 1'bx;
#580 SCD = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__sdfstp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_TB_V
|
module AUDIO_DAC ( // Memory Side
oFLASH_ADDR,iFLASH_DATA,
oSDRAM_ADDR,iSDRAM_DATA,
oSRAM_ADDR,iSRAM_DATA,
// Audio Side
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
// Control Signals
iSrc_Select,
iCLK_18_4,
iRST_N );
parameter REF_CLK = 18432000; // 18.432 MHz
parameter SAMPLE_RATE = 48000; // 48 KHz
parameter DATA_WIDTH = 16; // 16 Bits
parameter CHANNEL_NUM = 2; // Dual Channel
parameter SIN_SAMPLE_DATA = 48;
parameter FLASH_DATA_NUM = 1048576; // 1 MWords
parameter SDRAM_DATA_NUM = 4194304; // 4 MWords
parameter SRAM_DATA_NUM = 262144; // 256 KWords
parameter FLASH_ADDR_WIDTH= 20; // 20 Address Line
parameter SDRAM_ADDR_WIDTH= 22; // 22 Address Line
parameter SRAM_ADDR_WIDTH= 18; // 18 Address Line
parameter FLASH_DATA_WIDTH= 8; // 8 Bits
parameter SDRAM_DATA_WIDTH= 16; // 16 Bits
parameter SRAM_DATA_WIDTH= 16; // 16 Bits
//////////// Input Source Number //////////////
parameter SIN_SANPLE = 0;
parameter FLASH_DATA = 1;
parameter SDRAM_DATA = 2;
parameter SRAM_DATA = 3;
//////////////////////////////////////////////////
// Memory Side
output [FLASH_ADDR_WIDTH-1:0] oFLASH_ADDR;
input [FLASH_DATA_WIDTH-1:0] iFLASH_DATA;
output [SDRAM_ADDR_WIDTH:0] oSDRAM_ADDR;
input [SDRAM_DATA_WIDTH-1:0] iSDRAM_DATA;
output [SRAM_ADDR_WIDTH:0] oSRAM_ADDR;
input [SRAM_DATA_WIDTH-1:0] iSRAM_DATA;
// Audio Side
output oAUD_DATA;
output oAUD_LRCK;
output reg oAUD_BCK;
// Control Signals
input [1:0] iSrc_Select;
input iCLK_18_4;
input iRST_N;
// Internal Registers and Wires
reg [3:0] BCK_DIV;
reg [8:0] LRCK_1X_DIV;
reg [7:0] LRCK_2X_DIV;
reg [6:0] LRCK_4X_DIV;
reg [3:0] SEL_Cont;
//////// DATA Counter ////////
reg [5:0] SIN_Cont;
reg [FLASH_ADDR_WIDTH-1:0] FLASH_Cont;
reg [SDRAM_ADDR_WIDTH-1:0] SDRAM_Cont;
reg [SRAM_ADDR_WIDTH-1:0] SRAM_Cont;
////////////////////////////////////
reg [DATA_WIDTH-1:0] Sin_Out;
reg [DATA_WIDTH-1:0] FLASH_Out;
reg [DATA_WIDTH-1:0] SDRAM_Out;
reg [DATA_WIDTH-1:0] SRAM_Out;
reg [DATA_WIDTH-1:0] FLASH_Out_Tmp;
reg [DATA_WIDTH-1:0] SDRAM_Out_Tmp;
reg [DATA_WIDTH-1:0] SRAM_Out_Tmp;
reg LRCK_1X;
reg LRCK_2X;
reg LRCK_4X;
//////////// AUD_BCK Generator //////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
BCK_DIV <= 0;
oAUD_BCK <= 0;
end
else
begin
if(BCK_DIV >= REF_CLK/(SAMPLE_RATE*DATA_WIDTH*CHANNEL_NUM*2)-1 )
begin
BCK_DIV <= 0;
oAUD_BCK <= ~oAUD_BCK;
end
else
BCK_DIV <= BCK_DIV+1;
end
end
//////////////////////////////////////////////////
//////////// AUD_LRCK Generator //////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
LRCK_1X_DIV <= 0;
LRCK_2X_DIV <= 0;
LRCK_4X_DIV <= 0;
LRCK_1X <= 0;
LRCK_2X <= 0;
LRCK_4X <= 0;
end
else
begin
// LRCK 1X
if(LRCK_1X_DIV >= REF_CLK/(SAMPLE_RATE*2)-1 )
begin
LRCK_1X_DIV <= 0;
LRCK_1X <= ~LRCK_1X;
end
else
LRCK_1X_DIV <= LRCK_1X_DIV+1;
// LRCK 2X
if(LRCK_2X_DIV >= REF_CLK/(SAMPLE_RATE*4)-1 )
begin
LRCK_2X_DIV <= 0;
LRCK_2X <= ~LRCK_2X;
end
else
LRCK_2X_DIV <= LRCK_2X_DIV+1;
// LRCK 4X
if(LRCK_4X_DIV >= REF_CLK/(SAMPLE_RATE*8)-1 )
begin
LRCK_4X_DIV <= 0;
LRCK_4X <= ~LRCK_4X;
end
else
LRCK_4X_DIV <= LRCK_4X_DIV+1;
end
end
assign oAUD_LRCK = LRCK_1X;
//////////////////////////////////////////////////
////////// Sin LUT ADDR Generator //////////////
always@(negedge LRCK_1X or negedge iRST_N)
begin
if(!iRST_N)
SIN_Cont <= 0;
else
begin
if(SIN_Cont < SIN_SAMPLE_DATA-1 )
SIN_Cont <= SIN_Cont+1;
else
SIN_Cont <= 0;
end
end
//////////////////////////////////////////////////
////////// FLASH ADDR Generator //////////////
always@(negedge LRCK_4X or negedge iRST_N)
begin
if(!iRST_N)
FLASH_Cont <= 0;
else
begin
if(FLASH_Cont < FLASH_DATA_NUM-1 )
FLASH_Cont <= FLASH_Cont+1;
else
FLASH_Cont <= 0;
end
end
assign oFLASH_ADDR = FLASH_Cont;
//////////////////////////////////////////////////
////////// FLASH DATA Reorder //////////////
always@(posedge LRCK_4X or negedge iRST_N)
begin
if(!iRST_N)
FLASH_Out_Tmp <= 0;
else
begin
if(FLASH_Cont[0])
FLASH_Out_Tmp[15:8] <= iFLASH_DATA;
else
FLASH_Out_Tmp[7:0] <= iFLASH_DATA;
end
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
FLASH_Out <= 0;
else
FLASH_Out <= FLASH_Out_Tmp;
end
//////////////////////////////////////////////////
////////// SDRAM ADDR Generator //////////////
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SDRAM_Cont <= 0;
else
begin
if(SDRAM_Cont < SDRAM_DATA_NUM-1 )
SDRAM_Cont <= SDRAM_Cont+1;
else
SDRAM_Cont <= 0;
end
end
assign oSDRAM_ADDR = SDRAM_Cont;
//////////////////////////////////////////////////
////////// SDRAM DATA Latch //////////////
always@(posedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SDRAM_Out_Tmp <= 0;
else
SDRAM_Out_Tmp <= iSDRAM_DATA;
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SDRAM_Out <= 0;
else
SDRAM_Out <= SDRAM_Out_Tmp;
end
//////////////////////////////////////////////////
//////////// SRAM ADDR Generator ////////////
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SRAM_Cont <= 0;
else
begin
if(SRAM_Cont < SRAM_DATA_NUM-1 )
SRAM_Cont <= SRAM_Cont+1;
else
SRAM_Cont <= 0;
end
end
assign oSRAM_ADDR = SRAM_Cont;
//////////////////////////////////////////////////
////////// SRAM DATA Latch //////////////
always@(posedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SRAM_Out_Tmp <= 0;
else
SRAM_Out_Tmp <= iSRAM_DATA;
end
always@(negedge LRCK_2X or negedge iRST_N)
begin
if(!iRST_N)
SRAM_Out <= 0;
else
SRAM_Out <= SRAM_Out_Tmp;
end
//////////////////////////////////////////////////
////////// 16 Bits PISO MSB First //////////////
always@(negedge oAUD_BCK or negedge iRST_N)
begin
if(!iRST_N)
SEL_Cont <= 0;
else
SEL_Cont <= SEL_Cont+1;
end
assign oAUD_DATA = (iSrc_Select==SIN_SANPLE) ? Sin_Out[~SEL_Cont] :
(iSrc_Select==FLASH_DATA) ? FLASH_Out[~SEL_Cont]:
(iSrc_Select==SDRAM_DATA) ? SDRAM_Out[~SEL_Cont]:
SRAM_Out[~SEL_Cont] ;
//////////////////////////////////////////////////
//////////// Sin Wave ROM Table //////////////
always@(SIN_Cont)
begin
case(SIN_Cont)
0 : Sin_Out <= 0 ;
1 : Sin_Out <= 4276 ;
2 : Sin_Out <= 8480 ;
3 : Sin_Out <= 12539 ;
4 : Sin_Out <= 16383 ;
5 : Sin_Out <= 19947 ;
6 : Sin_Out <= 23169 ;
7 : Sin_Out <= 25995 ;
8 : Sin_Out <= 28377 ;
9 : Sin_Out <= 30272 ;
10 : Sin_Out <= 31650 ;
11 : Sin_Out <= 32486 ;
12 : Sin_Out <= 32767 ;
13 : Sin_Out <= 32486 ;
14 : Sin_Out <= 31650 ;
15 : Sin_Out <= 30272 ;
16 : Sin_Out <= 28377 ;
17 : Sin_Out <= 25995 ;
18 : Sin_Out <= 23169 ;
19 : Sin_Out <= 19947 ;
20 : Sin_Out <= 16383 ;
21 : Sin_Out <= 12539 ;
22 : Sin_Out <= 8480 ;
23 : Sin_Out <= 4276 ;
24 : Sin_Out <= 0 ;
25 : Sin_Out <= 61259 ;
26 : Sin_Out <= 57056 ;
27 : Sin_Out <= 52997 ;
28 : Sin_Out <= 49153 ;
29 : Sin_Out <= 45589 ;
30 : Sin_Out <= 42366 ;
31 : Sin_Out <= 39540 ;
32 : Sin_Out <= 37159 ;
33 : Sin_Out <= 35263 ;
34 : Sin_Out <= 33885 ;
35 : Sin_Out <= 33049 ;
36 : Sin_Out <= 32768 ;
37 : Sin_Out <= 33049 ;
38 : Sin_Out <= 33885 ;
39 : Sin_Out <= 35263 ;
40 : Sin_Out <= 37159 ;
41 : Sin_Out <= 39540 ;
42 : Sin_Out <= 42366 ;
43 : Sin_Out <= 45589 ;
44 : Sin_Out <= 49152 ;
45 : Sin_Out <= 52997 ;
46 : Sin_Out <= 57056 ;
47 : Sin_Out <= 61259 ;
default :
Sin_Out <= 0 ;
endcase
end
//////////////////////////////////////////////////
endmodule
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-2-2017
*/
module jt12_csr( // Circular Shift Register + input mux
input rst,
input clk,
input clk_en /* synthesis direct_enable */,
input [ 7:0] din,
input [43:0] shift_in,
output [43:0] shift_out,
input up_tl,
input up_dt1,
input up_ks_ar,
input up_amen_dr,
input up_sr,
input up_sl_rr,
input up_ssgeg,
input update_op_I,
input update_op_II,
input update_op_IV
);
localparam regop_width=44;
reg [regop_width-1:0] regop_in;
jt12_sh_rst #(.width(regop_width),.stages(12)) u_regch(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( regop_in ),
.drop ( shift_out )
);
wire up_tl_op = up_tl & update_op_IV;
wire up_dt1_op = up_dt1 & update_op_I;
wire up_mul_op = up_dt1 & update_op_II;
wire up_ks_op = up_ks_ar & update_op_II;
wire up_ar_op = up_ks_ar & update_op_I;
wire up_amen_op = up_amen_dr& update_op_IV;
wire up_dr_op = up_amen_dr& update_op_I;
wire up_sr_op = up_sr & update_op_I;
wire up_sl_op = up_sl_rr & update_op_I;
wire up_rr_op = up_sl_rr & update_op_I;
wire up_ssg_op = up_ssgeg & update_op_I;
always @(*)
regop_in = {
up_tl_op ? din[6:0] : shift_in[43:37], // 7
up_dt1_op ? din[6:4] : shift_in[36:34], // 3
up_mul_op ? din[3:0] : shift_in[33:30], // 4
up_ks_op ? din[7:6] : shift_in[29:28], // 2
up_ar_op ? din[4:0] : shift_in[27:23], // 5
up_amen_op ? din[7] : shift_in[ 22], // 1
up_dr_op ? din[4:0] : shift_in[21:17], // 5
up_sr_op ? din[4:0] : shift_in[16:12], // 5
up_sl_op ? din[7:4] : shift_in[11: 8], // 4
up_rr_op ? din[3:0] : shift_in[ 7: 4], // 4
up_ssg_op ? din[3:0] : shift_in[ 3: 0] // 4
};
endmodule // jt12_reg
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__MUX2_FUNCTIONAL_PP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to10_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2_FUNCTIONAL_PP_V
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// RDY_set_verbosity O 1 const
// RDY_show_PLIC_state O 1 const
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1 reg
// RDY_set_addr_map O 1 const
// axi4_slave_awready O 1 reg
// axi4_slave_wready O 1 reg
// axi4_slave_bvalid O 1 reg
// axi4_slave_bid O 16 reg
// axi4_slave_bresp O 2 reg
// axi4_slave_arready O 1 reg
// axi4_slave_rvalid O 1 reg
// axi4_slave_rid O 16 reg
// axi4_slave_rdata O 64 reg
// axi4_slave_rresp O 2 reg
// axi4_slave_rlast O 1 reg
// v_targets_0_m_eip O 1
// v_targets_1_m_eip O 1
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// set_addr_map_addr_base I 64 reg
// set_addr_map_addr_lim I 64 reg
// axi4_slave_awvalid I 1
// axi4_slave_awid I 16 reg
// axi4_slave_awaddr I 64 reg
// axi4_slave_awlen I 8 reg
// axi4_slave_awsize I 3 reg
// axi4_slave_awburst I 2 reg
// axi4_slave_awlock I 1 reg
// axi4_slave_awcache I 4 reg
// axi4_slave_awprot I 3 reg
// axi4_slave_awqos I 4 reg
// axi4_slave_awregion I 4 reg
// axi4_slave_wvalid I 1
// axi4_slave_wdata I 64 reg
// axi4_slave_wstrb I 8 reg
// axi4_slave_wlast I 1 reg
// axi4_slave_bready I 1
// axi4_slave_arvalid I 1
// axi4_slave_arid I 16 reg
// axi4_slave_araddr I 64 reg
// axi4_slave_arlen I 8 reg
// axi4_slave_arsize I 3 reg
// axi4_slave_arburst I 2 reg
// axi4_slave_arlock I 1 reg
// axi4_slave_arcache I 4 reg
// axi4_slave_arprot I 3 reg
// axi4_slave_arqos I 4 reg
// axi4_slave_arregion I 4 reg
// axi4_slave_rready I 1
// v_sources_0_m_interrupt_req_set_not_clear I 1
// v_sources_1_m_interrupt_req_set_not_clear I 1
// v_sources_2_m_interrupt_req_set_not_clear I 1
// v_sources_3_m_interrupt_req_set_not_clear I 1
// v_sources_4_m_interrupt_req_set_not_clear I 1
// v_sources_5_m_interrupt_req_set_not_clear I 1
// v_sources_6_m_interrupt_req_set_not_clear I 1
// v_sources_7_m_interrupt_req_set_not_clear I 1
// v_sources_8_m_interrupt_req_set_not_clear I 1
// v_sources_9_m_interrupt_req_set_not_clear I 1
// v_sources_10_m_interrupt_req_set_not_clear I 1
// v_sources_11_m_interrupt_req_set_not_clear I 1
// v_sources_12_m_interrupt_req_set_not_clear I 1
// v_sources_13_m_interrupt_req_set_not_clear I 1
// v_sources_14_m_interrupt_req_set_not_clear I 1
// v_sources_15_m_interrupt_req_set_not_clear I 1
// EN_set_verbosity I 1
// EN_show_PLIC_state I 1 unused
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_set_addr_map I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkPLIC_16_2_7(CLK,
RST_N,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
EN_show_PLIC_state,
RDY_show_PLIC_state,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
set_addr_map_addr_base,
set_addr_map_addr_lim,
EN_set_addr_map,
RDY_set_addr_map,
axi4_slave_awvalid,
axi4_slave_awid,
axi4_slave_awaddr,
axi4_slave_awlen,
axi4_slave_awsize,
axi4_slave_awburst,
axi4_slave_awlock,
axi4_slave_awcache,
axi4_slave_awprot,
axi4_slave_awqos,
axi4_slave_awregion,
axi4_slave_awready,
axi4_slave_wvalid,
axi4_slave_wdata,
axi4_slave_wstrb,
axi4_slave_wlast,
axi4_slave_wready,
axi4_slave_bvalid,
axi4_slave_bid,
axi4_slave_bresp,
axi4_slave_bready,
axi4_slave_arvalid,
axi4_slave_arid,
axi4_slave_araddr,
axi4_slave_arlen,
axi4_slave_arsize,
axi4_slave_arburst,
axi4_slave_arlock,
axi4_slave_arcache,
axi4_slave_arprot,
axi4_slave_arqos,
axi4_slave_arregion,
axi4_slave_arready,
axi4_slave_rvalid,
axi4_slave_rid,
axi4_slave_rdata,
axi4_slave_rresp,
axi4_slave_rlast,
axi4_slave_rready,
v_sources_0_m_interrupt_req_set_not_clear,
v_sources_1_m_interrupt_req_set_not_clear,
v_sources_2_m_interrupt_req_set_not_clear,
v_sources_3_m_interrupt_req_set_not_clear,
v_sources_4_m_interrupt_req_set_not_clear,
v_sources_5_m_interrupt_req_set_not_clear,
v_sources_6_m_interrupt_req_set_not_clear,
v_sources_7_m_interrupt_req_set_not_clear,
v_sources_8_m_interrupt_req_set_not_clear,
v_sources_9_m_interrupt_req_set_not_clear,
v_sources_10_m_interrupt_req_set_not_clear,
v_sources_11_m_interrupt_req_set_not_clear,
v_sources_12_m_interrupt_req_set_not_clear,
v_sources_13_m_interrupt_req_set_not_clear,
v_sources_14_m_interrupt_req_set_not_clear,
v_sources_15_m_interrupt_req_set_not_clear,
v_targets_0_m_eip,
v_targets_1_m_eip);
input CLK;
input RST_N;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method show_PLIC_state
input EN_show_PLIC_state;
output RDY_show_PLIC_state;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method set_addr_map
input [63 : 0] set_addr_map_addr_base;
input [63 : 0] set_addr_map_addr_lim;
input EN_set_addr_map;
output RDY_set_addr_map;
// action method axi4_slave_m_awvalid
input axi4_slave_awvalid;
input [15 : 0] axi4_slave_awid;
input [63 : 0] axi4_slave_awaddr;
input [7 : 0] axi4_slave_awlen;
input [2 : 0] axi4_slave_awsize;
input [1 : 0] axi4_slave_awburst;
input axi4_slave_awlock;
input [3 : 0] axi4_slave_awcache;
input [2 : 0] axi4_slave_awprot;
input [3 : 0] axi4_slave_awqos;
input [3 : 0] axi4_slave_awregion;
// value method axi4_slave_m_awready
output axi4_slave_awready;
// action method axi4_slave_m_wvalid
input axi4_slave_wvalid;
input [63 : 0] axi4_slave_wdata;
input [7 : 0] axi4_slave_wstrb;
input axi4_slave_wlast;
// value method axi4_slave_m_wready
output axi4_slave_wready;
// value method axi4_slave_m_bvalid
output axi4_slave_bvalid;
// value method axi4_slave_m_bid
output [15 : 0] axi4_slave_bid;
// value method axi4_slave_m_bresp
output [1 : 0] axi4_slave_bresp;
// value method axi4_slave_m_buser
// action method axi4_slave_m_bready
input axi4_slave_bready;
// action method axi4_slave_m_arvalid
input axi4_slave_arvalid;
input [15 : 0] axi4_slave_arid;
input [63 : 0] axi4_slave_araddr;
input [7 : 0] axi4_slave_arlen;
input [2 : 0] axi4_slave_arsize;
input [1 : 0] axi4_slave_arburst;
input axi4_slave_arlock;
input [3 : 0] axi4_slave_arcache;
input [2 : 0] axi4_slave_arprot;
input [3 : 0] axi4_slave_arqos;
input [3 : 0] axi4_slave_arregion;
// value method axi4_slave_m_arready
output axi4_slave_arready;
// value method axi4_slave_m_rvalid
output axi4_slave_rvalid;
// value method axi4_slave_m_rid
output [15 : 0] axi4_slave_rid;
// value method axi4_slave_m_rdata
output [63 : 0] axi4_slave_rdata;
// value method axi4_slave_m_rresp
output [1 : 0] axi4_slave_rresp;
// value method axi4_slave_m_rlast
output axi4_slave_rlast;
// value method axi4_slave_m_ruser
// action method axi4_slave_m_rready
input axi4_slave_rready;
// action method v_sources_0_m_interrupt_req
input v_sources_0_m_interrupt_req_set_not_clear;
// action method v_sources_1_m_interrupt_req
input v_sources_1_m_interrupt_req_set_not_clear;
// action method v_sources_2_m_interrupt_req
input v_sources_2_m_interrupt_req_set_not_clear;
// action method v_sources_3_m_interrupt_req
input v_sources_3_m_interrupt_req_set_not_clear;
// action method v_sources_4_m_interrupt_req
input v_sources_4_m_interrupt_req_set_not_clear;
// action method v_sources_5_m_interrupt_req
input v_sources_5_m_interrupt_req_set_not_clear;
// action method v_sources_6_m_interrupt_req
input v_sources_6_m_interrupt_req_set_not_clear;
// action method v_sources_7_m_interrupt_req
input v_sources_7_m_interrupt_req_set_not_clear;
// action method v_sources_8_m_interrupt_req
input v_sources_8_m_interrupt_req_set_not_clear;
// action method v_sources_9_m_interrupt_req
input v_sources_9_m_interrupt_req_set_not_clear;
// action method v_sources_10_m_interrupt_req
input v_sources_10_m_interrupt_req_set_not_clear;
// action method v_sources_11_m_interrupt_req
input v_sources_11_m_interrupt_req_set_not_clear;
// action method v_sources_12_m_interrupt_req
input v_sources_12_m_interrupt_req_set_not_clear;
// action method v_sources_13_m_interrupt_req
input v_sources_13_m_interrupt_req_set_not_clear;
// action method v_sources_14_m_interrupt_req
input v_sources_14_m_interrupt_req_set_not_clear;
// action method v_sources_15_m_interrupt_req
input v_sources_15_m_interrupt_req_set_not_clear;
// value method v_targets_0_m_eip
output v_targets_0_m_eip;
// value method v_targets_1_m_eip
output v_targets_1_m_eip;
// signals for module outputs
wire [63 : 0] axi4_slave_rdata;
wire [15 : 0] axi4_slave_bid, axi4_slave_rid;
wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp;
wire RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_set_addr_map,
RDY_set_verbosity,
RDY_show_PLIC_state,
axi4_slave_arready,
axi4_slave_awready,
axi4_slave_bvalid,
axi4_slave_rlast,
axi4_slave_rvalid,
axi4_slave_wready,
v_targets_0_m_eip,
v_targets_1_m_eip;
// register m_cfg_verbosity
reg [3 : 0] m_cfg_verbosity;
wire [3 : 0] m_cfg_verbosity$D_IN;
wire m_cfg_verbosity$EN;
// register m_rg_addr_base
reg [63 : 0] m_rg_addr_base;
wire [63 : 0] m_rg_addr_base$D_IN;
wire m_rg_addr_base$EN;
// register m_rg_addr_lim
reg [63 : 0] m_rg_addr_lim;
wire [63 : 0] m_rg_addr_lim$D_IN;
wire m_rg_addr_lim$EN;
// register m_vrg_source_busy_0
reg m_vrg_source_busy_0;
reg m_vrg_source_busy_0$D_IN;
wire m_vrg_source_busy_0$EN;
// register m_vrg_source_busy_1
reg m_vrg_source_busy_1;
reg m_vrg_source_busy_1$D_IN;
wire m_vrg_source_busy_1$EN;
// register m_vrg_source_busy_10
reg m_vrg_source_busy_10;
reg m_vrg_source_busy_10$D_IN;
wire m_vrg_source_busy_10$EN;
// register m_vrg_source_busy_11
reg m_vrg_source_busy_11;
reg m_vrg_source_busy_11$D_IN;
wire m_vrg_source_busy_11$EN;
// register m_vrg_source_busy_12
reg m_vrg_source_busy_12;
reg m_vrg_source_busy_12$D_IN;
wire m_vrg_source_busy_12$EN;
// register m_vrg_source_busy_13
reg m_vrg_source_busy_13;
reg m_vrg_source_busy_13$D_IN;
wire m_vrg_source_busy_13$EN;
// register m_vrg_source_busy_14
reg m_vrg_source_busy_14;
reg m_vrg_source_busy_14$D_IN;
wire m_vrg_source_busy_14$EN;
// register m_vrg_source_busy_15
reg m_vrg_source_busy_15;
reg m_vrg_source_busy_15$D_IN;
wire m_vrg_source_busy_15$EN;
// register m_vrg_source_busy_16
reg m_vrg_source_busy_16;
reg m_vrg_source_busy_16$D_IN;
wire m_vrg_source_busy_16$EN;
// register m_vrg_source_busy_2
reg m_vrg_source_busy_2;
reg m_vrg_source_busy_2$D_IN;
wire m_vrg_source_busy_2$EN;
// register m_vrg_source_busy_3
reg m_vrg_source_busy_3;
reg m_vrg_source_busy_3$D_IN;
wire m_vrg_source_busy_3$EN;
// register m_vrg_source_busy_4
reg m_vrg_source_busy_4;
reg m_vrg_source_busy_4$D_IN;
wire m_vrg_source_busy_4$EN;
// register m_vrg_source_busy_5
reg m_vrg_source_busy_5;
reg m_vrg_source_busy_5$D_IN;
wire m_vrg_source_busy_5$EN;
// register m_vrg_source_busy_6
reg m_vrg_source_busy_6;
reg m_vrg_source_busy_6$D_IN;
wire m_vrg_source_busy_6$EN;
// register m_vrg_source_busy_7
reg m_vrg_source_busy_7;
reg m_vrg_source_busy_7$D_IN;
wire m_vrg_source_busy_7$EN;
// register m_vrg_source_busy_8
reg m_vrg_source_busy_8;
reg m_vrg_source_busy_8$D_IN;
wire m_vrg_source_busy_8$EN;
// register m_vrg_source_busy_9
reg m_vrg_source_busy_9;
reg m_vrg_source_busy_9$D_IN;
wire m_vrg_source_busy_9$EN;
// register m_vrg_source_ip_0
reg m_vrg_source_ip_0;
wire m_vrg_source_ip_0$D_IN, m_vrg_source_ip_0$EN;
// register m_vrg_source_ip_1
reg m_vrg_source_ip_1;
wire m_vrg_source_ip_1$D_IN, m_vrg_source_ip_1$EN;
// register m_vrg_source_ip_10
reg m_vrg_source_ip_10;
wire m_vrg_source_ip_10$D_IN, m_vrg_source_ip_10$EN;
// register m_vrg_source_ip_11
reg m_vrg_source_ip_11;
wire m_vrg_source_ip_11$D_IN, m_vrg_source_ip_11$EN;
// register m_vrg_source_ip_12
reg m_vrg_source_ip_12;
wire m_vrg_source_ip_12$D_IN, m_vrg_source_ip_12$EN;
// register m_vrg_source_ip_13
reg m_vrg_source_ip_13;
wire m_vrg_source_ip_13$D_IN, m_vrg_source_ip_13$EN;
// register m_vrg_source_ip_14
reg m_vrg_source_ip_14;
wire m_vrg_source_ip_14$D_IN, m_vrg_source_ip_14$EN;
// register m_vrg_source_ip_15
reg m_vrg_source_ip_15;
wire m_vrg_source_ip_15$D_IN, m_vrg_source_ip_15$EN;
// register m_vrg_source_ip_16
reg m_vrg_source_ip_16;
wire m_vrg_source_ip_16$D_IN, m_vrg_source_ip_16$EN;
// register m_vrg_source_ip_2
reg m_vrg_source_ip_2;
wire m_vrg_source_ip_2$D_IN, m_vrg_source_ip_2$EN;
// register m_vrg_source_ip_3
reg m_vrg_source_ip_3;
wire m_vrg_source_ip_3$D_IN, m_vrg_source_ip_3$EN;
// register m_vrg_source_ip_4
reg m_vrg_source_ip_4;
wire m_vrg_source_ip_4$D_IN, m_vrg_source_ip_4$EN;
// register m_vrg_source_ip_5
reg m_vrg_source_ip_5;
wire m_vrg_source_ip_5$D_IN, m_vrg_source_ip_5$EN;
// register m_vrg_source_ip_6
reg m_vrg_source_ip_6;
wire m_vrg_source_ip_6$D_IN, m_vrg_source_ip_6$EN;
// register m_vrg_source_ip_7
reg m_vrg_source_ip_7;
wire m_vrg_source_ip_7$D_IN, m_vrg_source_ip_7$EN;
// register m_vrg_source_ip_8
reg m_vrg_source_ip_8;
wire m_vrg_source_ip_8$D_IN, m_vrg_source_ip_8$EN;
// register m_vrg_source_ip_9
reg m_vrg_source_ip_9;
wire m_vrg_source_ip_9$D_IN, m_vrg_source_ip_9$EN;
// register m_vrg_source_prio_0
reg [2 : 0] m_vrg_source_prio_0;
wire [2 : 0] m_vrg_source_prio_0$D_IN;
wire m_vrg_source_prio_0$EN;
// register m_vrg_source_prio_1
reg [2 : 0] m_vrg_source_prio_1;
wire [2 : 0] m_vrg_source_prio_1$D_IN;
wire m_vrg_source_prio_1$EN;
// register m_vrg_source_prio_10
reg [2 : 0] m_vrg_source_prio_10;
wire [2 : 0] m_vrg_source_prio_10$D_IN;
wire m_vrg_source_prio_10$EN;
// register m_vrg_source_prio_11
reg [2 : 0] m_vrg_source_prio_11;
wire [2 : 0] m_vrg_source_prio_11$D_IN;
wire m_vrg_source_prio_11$EN;
// register m_vrg_source_prio_12
reg [2 : 0] m_vrg_source_prio_12;
wire [2 : 0] m_vrg_source_prio_12$D_IN;
wire m_vrg_source_prio_12$EN;
// register m_vrg_source_prio_13
reg [2 : 0] m_vrg_source_prio_13;
wire [2 : 0] m_vrg_source_prio_13$D_IN;
wire m_vrg_source_prio_13$EN;
// register m_vrg_source_prio_14
reg [2 : 0] m_vrg_source_prio_14;
wire [2 : 0] m_vrg_source_prio_14$D_IN;
wire m_vrg_source_prio_14$EN;
// register m_vrg_source_prio_15
reg [2 : 0] m_vrg_source_prio_15;
wire [2 : 0] m_vrg_source_prio_15$D_IN;
wire m_vrg_source_prio_15$EN;
// register m_vrg_source_prio_16
reg [2 : 0] m_vrg_source_prio_16;
wire [2 : 0] m_vrg_source_prio_16$D_IN;
wire m_vrg_source_prio_16$EN;
// register m_vrg_source_prio_2
reg [2 : 0] m_vrg_source_prio_2;
wire [2 : 0] m_vrg_source_prio_2$D_IN;
wire m_vrg_source_prio_2$EN;
// register m_vrg_source_prio_3
reg [2 : 0] m_vrg_source_prio_3;
wire [2 : 0] m_vrg_source_prio_3$D_IN;
wire m_vrg_source_prio_3$EN;
// register m_vrg_source_prio_4
reg [2 : 0] m_vrg_source_prio_4;
wire [2 : 0] m_vrg_source_prio_4$D_IN;
wire m_vrg_source_prio_4$EN;
// register m_vrg_source_prio_5
reg [2 : 0] m_vrg_source_prio_5;
wire [2 : 0] m_vrg_source_prio_5$D_IN;
wire m_vrg_source_prio_5$EN;
// register m_vrg_source_prio_6
reg [2 : 0] m_vrg_source_prio_6;
wire [2 : 0] m_vrg_source_prio_6$D_IN;
wire m_vrg_source_prio_6$EN;
// register m_vrg_source_prio_7
reg [2 : 0] m_vrg_source_prio_7;
wire [2 : 0] m_vrg_source_prio_7$D_IN;
wire m_vrg_source_prio_7$EN;
// register m_vrg_source_prio_8
reg [2 : 0] m_vrg_source_prio_8;
wire [2 : 0] m_vrg_source_prio_8$D_IN;
wire m_vrg_source_prio_8$EN;
// register m_vrg_source_prio_9
reg [2 : 0] m_vrg_source_prio_9;
wire [2 : 0] m_vrg_source_prio_9$D_IN;
wire m_vrg_source_prio_9$EN;
// register m_vrg_target_threshold_0
reg [2 : 0] m_vrg_target_threshold_0;
wire [2 : 0] m_vrg_target_threshold_0$D_IN;
wire m_vrg_target_threshold_0$EN;
// register m_vrg_target_threshold_1
reg [2 : 0] m_vrg_target_threshold_1;
wire [2 : 0] m_vrg_target_threshold_1$D_IN;
wire m_vrg_target_threshold_1$EN;
// register m_vvrg_ie_0_0
reg m_vvrg_ie_0_0;
wire m_vvrg_ie_0_0$D_IN, m_vvrg_ie_0_0$EN;
// register m_vvrg_ie_0_1
reg m_vvrg_ie_0_1;
wire m_vvrg_ie_0_1$D_IN, m_vvrg_ie_0_1$EN;
// register m_vvrg_ie_0_10
reg m_vvrg_ie_0_10;
wire m_vvrg_ie_0_10$D_IN, m_vvrg_ie_0_10$EN;
// register m_vvrg_ie_0_11
reg m_vvrg_ie_0_11;
wire m_vvrg_ie_0_11$D_IN, m_vvrg_ie_0_11$EN;
// register m_vvrg_ie_0_12
reg m_vvrg_ie_0_12;
wire m_vvrg_ie_0_12$D_IN, m_vvrg_ie_0_12$EN;
// register m_vvrg_ie_0_13
reg m_vvrg_ie_0_13;
wire m_vvrg_ie_0_13$D_IN, m_vvrg_ie_0_13$EN;
// register m_vvrg_ie_0_14
reg m_vvrg_ie_0_14;
wire m_vvrg_ie_0_14$D_IN, m_vvrg_ie_0_14$EN;
// register m_vvrg_ie_0_15
reg m_vvrg_ie_0_15;
wire m_vvrg_ie_0_15$D_IN, m_vvrg_ie_0_15$EN;
// register m_vvrg_ie_0_16
reg m_vvrg_ie_0_16;
wire m_vvrg_ie_0_16$D_IN, m_vvrg_ie_0_16$EN;
// register m_vvrg_ie_0_2
reg m_vvrg_ie_0_2;
wire m_vvrg_ie_0_2$D_IN, m_vvrg_ie_0_2$EN;
// register m_vvrg_ie_0_3
reg m_vvrg_ie_0_3;
wire m_vvrg_ie_0_3$D_IN, m_vvrg_ie_0_3$EN;
// register m_vvrg_ie_0_4
reg m_vvrg_ie_0_4;
wire m_vvrg_ie_0_4$D_IN, m_vvrg_ie_0_4$EN;
// register m_vvrg_ie_0_5
reg m_vvrg_ie_0_5;
wire m_vvrg_ie_0_5$D_IN, m_vvrg_ie_0_5$EN;
// register m_vvrg_ie_0_6
reg m_vvrg_ie_0_6;
wire m_vvrg_ie_0_6$D_IN, m_vvrg_ie_0_6$EN;
// register m_vvrg_ie_0_7
reg m_vvrg_ie_0_7;
wire m_vvrg_ie_0_7$D_IN, m_vvrg_ie_0_7$EN;
// register m_vvrg_ie_0_8
reg m_vvrg_ie_0_8;
wire m_vvrg_ie_0_8$D_IN, m_vvrg_ie_0_8$EN;
// register m_vvrg_ie_0_9
reg m_vvrg_ie_0_9;
wire m_vvrg_ie_0_9$D_IN, m_vvrg_ie_0_9$EN;
// register m_vvrg_ie_1_0
reg m_vvrg_ie_1_0;
wire m_vvrg_ie_1_0$D_IN, m_vvrg_ie_1_0$EN;
// register m_vvrg_ie_1_1
reg m_vvrg_ie_1_1;
wire m_vvrg_ie_1_1$D_IN, m_vvrg_ie_1_1$EN;
// register m_vvrg_ie_1_10
reg m_vvrg_ie_1_10;
wire m_vvrg_ie_1_10$D_IN, m_vvrg_ie_1_10$EN;
// register m_vvrg_ie_1_11
reg m_vvrg_ie_1_11;
wire m_vvrg_ie_1_11$D_IN, m_vvrg_ie_1_11$EN;
// register m_vvrg_ie_1_12
reg m_vvrg_ie_1_12;
wire m_vvrg_ie_1_12$D_IN, m_vvrg_ie_1_12$EN;
// register m_vvrg_ie_1_13
reg m_vvrg_ie_1_13;
wire m_vvrg_ie_1_13$D_IN, m_vvrg_ie_1_13$EN;
// register m_vvrg_ie_1_14
reg m_vvrg_ie_1_14;
wire m_vvrg_ie_1_14$D_IN, m_vvrg_ie_1_14$EN;
// register m_vvrg_ie_1_15
reg m_vvrg_ie_1_15;
wire m_vvrg_ie_1_15$D_IN, m_vvrg_ie_1_15$EN;
// register m_vvrg_ie_1_16
reg m_vvrg_ie_1_16;
wire m_vvrg_ie_1_16$D_IN, m_vvrg_ie_1_16$EN;
// register m_vvrg_ie_1_2
reg m_vvrg_ie_1_2;
wire m_vvrg_ie_1_2$D_IN, m_vvrg_ie_1_2$EN;
// register m_vvrg_ie_1_3
reg m_vvrg_ie_1_3;
wire m_vvrg_ie_1_3$D_IN, m_vvrg_ie_1_3$EN;
// register m_vvrg_ie_1_4
reg m_vvrg_ie_1_4;
wire m_vvrg_ie_1_4$D_IN, m_vvrg_ie_1_4$EN;
// register m_vvrg_ie_1_5
reg m_vvrg_ie_1_5;
wire m_vvrg_ie_1_5$D_IN, m_vvrg_ie_1_5$EN;
// register m_vvrg_ie_1_6
reg m_vvrg_ie_1_6;
wire m_vvrg_ie_1_6$D_IN, m_vvrg_ie_1_6$EN;
// register m_vvrg_ie_1_7
reg m_vvrg_ie_1_7;
wire m_vvrg_ie_1_7$D_IN, m_vvrg_ie_1_7$EN;
// register m_vvrg_ie_1_8
reg m_vvrg_ie_1_8;
wire m_vvrg_ie_1_8$D_IN, m_vvrg_ie_1_8$EN;
// register m_vvrg_ie_1_9
reg m_vvrg_ie_1_9;
wire m_vvrg_ie_1_9$D_IN, m_vvrg_ie_1_9$EN;
// ports of submodule m_f_reset_reqs
wire m_f_reset_reqs$CLR,
m_f_reset_reqs$DEQ,
m_f_reset_reqs$EMPTY_N,
m_f_reset_reqs$ENQ,
m_f_reset_reqs$FULL_N;
// ports of submodule m_f_reset_rsps
wire m_f_reset_rsps$CLR,
m_f_reset_rsps$DEQ,
m_f_reset_rsps$EMPTY_N,
m_f_reset_rsps$ENQ,
m_f_reset_rsps$FULL_N;
// ports of submodule m_slave_xactor_f_rd_addr
wire [108 : 0] m_slave_xactor_f_rd_addr$D_IN,
m_slave_xactor_f_rd_addr$D_OUT;
wire m_slave_xactor_f_rd_addr$CLR,
m_slave_xactor_f_rd_addr$DEQ,
m_slave_xactor_f_rd_addr$EMPTY_N,
m_slave_xactor_f_rd_addr$ENQ,
m_slave_xactor_f_rd_addr$FULL_N;
// ports of submodule m_slave_xactor_f_rd_data
wire [82 : 0] m_slave_xactor_f_rd_data$D_IN, m_slave_xactor_f_rd_data$D_OUT;
wire m_slave_xactor_f_rd_data$CLR,
m_slave_xactor_f_rd_data$DEQ,
m_slave_xactor_f_rd_data$EMPTY_N,
m_slave_xactor_f_rd_data$ENQ,
m_slave_xactor_f_rd_data$FULL_N;
// ports of submodule m_slave_xactor_f_wr_addr
wire [108 : 0] m_slave_xactor_f_wr_addr$D_IN,
m_slave_xactor_f_wr_addr$D_OUT;
wire m_slave_xactor_f_wr_addr$CLR,
m_slave_xactor_f_wr_addr$DEQ,
m_slave_xactor_f_wr_addr$EMPTY_N,
m_slave_xactor_f_wr_addr$ENQ,
m_slave_xactor_f_wr_addr$FULL_N;
// ports of submodule m_slave_xactor_f_wr_data
wire [72 : 0] m_slave_xactor_f_wr_data$D_IN, m_slave_xactor_f_wr_data$D_OUT;
wire m_slave_xactor_f_wr_data$CLR,
m_slave_xactor_f_wr_data$DEQ,
m_slave_xactor_f_wr_data$EMPTY_N,
m_slave_xactor_f_wr_data$ENQ,
m_slave_xactor_f_wr_data$FULL_N;
// ports of submodule m_slave_xactor_f_wr_resp
wire [17 : 0] m_slave_xactor_f_wr_resp$D_IN, m_slave_xactor_f_wr_resp$D_OUT;
wire m_slave_xactor_f_wr_resp$CLR,
m_slave_xactor_f_wr_resp$DEQ,
m_slave_xactor_f_wr_resp$EMPTY_N,
m_slave_xactor_f_wr_resp$ENQ,
m_slave_xactor_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_m_rl_process_rd_req,
CAN_FIRE_RL_m_rl_process_wr_req,
CAN_FIRE_RL_m_rl_reset,
CAN_FIRE_axi4_slave_m_arvalid,
CAN_FIRE_axi4_slave_m_awvalid,
CAN_FIRE_axi4_slave_m_bready,
CAN_FIRE_axi4_slave_m_rready,
CAN_FIRE_axi4_slave_m_wvalid,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_set_addr_map,
CAN_FIRE_set_verbosity,
CAN_FIRE_show_PLIC_state,
CAN_FIRE_v_sources_0_m_interrupt_req,
CAN_FIRE_v_sources_10_m_interrupt_req,
CAN_FIRE_v_sources_11_m_interrupt_req,
CAN_FIRE_v_sources_12_m_interrupt_req,
CAN_FIRE_v_sources_13_m_interrupt_req,
CAN_FIRE_v_sources_14_m_interrupt_req,
CAN_FIRE_v_sources_15_m_interrupt_req,
CAN_FIRE_v_sources_1_m_interrupt_req,
CAN_FIRE_v_sources_2_m_interrupt_req,
CAN_FIRE_v_sources_3_m_interrupt_req,
CAN_FIRE_v_sources_4_m_interrupt_req,
CAN_FIRE_v_sources_5_m_interrupt_req,
CAN_FIRE_v_sources_6_m_interrupt_req,
CAN_FIRE_v_sources_7_m_interrupt_req,
CAN_FIRE_v_sources_8_m_interrupt_req,
CAN_FIRE_v_sources_9_m_interrupt_req,
WILL_FIRE_RL_m_rl_process_rd_req,
WILL_FIRE_RL_m_rl_process_wr_req,
WILL_FIRE_RL_m_rl_reset,
WILL_FIRE_axi4_slave_m_arvalid,
WILL_FIRE_axi4_slave_m_awvalid,
WILL_FIRE_axi4_slave_m_bready,
WILL_FIRE_axi4_slave_m_rready,
WILL_FIRE_axi4_slave_m_wvalid,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_set_addr_map,
WILL_FIRE_set_verbosity,
WILL_FIRE_show_PLIC_state,
WILL_FIRE_v_sources_0_m_interrupt_req,
WILL_FIRE_v_sources_10_m_interrupt_req,
WILL_FIRE_v_sources_11_m_interrupt_req,
WILL_FIRE_v_sources_12_m_interrupt_req,
WILL_FIRE_v_sources_13_m_interrupt_req,
WILL_FIRE_v_sources_14_m_interrupt_req,
WILL_FIRE_v_sources_15_m_interrupt_req,
WILL_FIRE_v_sources_1_m_interrupt_req,
WILL_FIRE_v_sources_2_m_interrupt_req,
WILL_FIRE_v_sources_3_m_interrupt_req,
WILL_FIRE_v_sources_4_m_interrupt_req,
WILL_FIRE_v_sources_5_m_interrupt_req,
WILL_FIRE_v_sources_6_m_interrupt_req,
WILL_FIRE_v_sources_7_m_interrupt_req,
WILL_FIRE_v_sources_8_m_interrupt_req,
WILL_FIRE_v_sources_9_m_interrupt_req;
// inputs to muxes for submodule ports
wire MUX_m_vrg_source_busy_0$write_1__SEL_1,
MUX_m_vrg_source_busy_0$write_1__SEL_2,
MUX_m_vrg_source_busy_1$write_1__SEL_1,
MUX_m_vrg_source_busy_1$write_1__SEL_2,
MUX_m_vrg_source_busy_10$write_1__SEL_1,
MUX_m_vrg_source_busy_10$write_1__SEL_2,
MUX_m_vrg_source_busy_11$write_1__SEL_1,
MUX_m_vrg_source_busy_11$write_1__SEL_2,
MUX_m_vrg_source_busy_12$write_1__SEL_1,
MUX_m_vrg_source_busy_12$write_1__SEL_2,
MUX_m_vrg_source_busy_13$write_1__SEL_1,
MUX_m_vrg_source_busy_13$write_1__SEL_2,
MUX_m_vrg_source_busy_14$write_1__SEL_1,
MUX_m_vrg_source_busy_14$write_1__SEL_2,
MUX_m_vrg_source_busy_15$write_1__SEL_1,
MUX_m_vrg_source_busy_15$write_1__SEL_2,
MUX_m_vrg_source_busy_16$write_1__SEL_1,
MUX_m_vrg_source_busy_16$write_1__SEL_2,
MUX_m_vrg_source_busy_2$write_1__SEL_1,
MUX_m_vrg_source_busy_2$write_1__SEL_2,
MUX_m_vrg_source_busy_3$write_1__SEL_1,
MUX_m_vrg_source_busy_3$write_1__SEL_2,
MUX_m_vrg_source_busy_4$write_1__SEL_1,
MUX_m_vrg_source_busy_4$write_1__SEL_2,
MUX_m_vrg_source_busy_5$write_1__SEL_1,
MUX_m_vrg_source_busy_5$write_1__SEL_2,
MUX_m_vrg_source_busy_6$write_1__SEL_1,
MUX_m_vrg_source_busy_6$write_1__SEL_2,
MUX_m_vrg_source_busy_7$write_1__SEL_1,
MUX_m_vrg_source_busy_7$write_1__SEL_2,
MUX_m_vrg_source_busy_8$write_1__SEL_1,
MUX_m_vrg_source_busy_8$write_1__SEL_2,
MUX_m_vrg_source_busy_9$write_1__SEL_1,
MUX_m_vrg_source_busy_9$write_1__SEL_2,
MUX_m_vrg_source_prio_0$write_1__SEL_1,
MUX_m_vrg_source_prio_1$write_1__SEL_1,
MUX_m_vrg_source_prio_10$write_1__SEL_1,
MUX_m_vrg_source_prio_11$write_1__SEL_1,
MUX_m_vrg_source_prio_12$write_1__SEL_1,
MUX_m_vrg_source_prio_13$write_1__SEL_1,
MUX_m_vrg_source_prio_14$write_1__SEL_1,
MUX_m_vrg_source_prio_15$write_1__SEL_1,
MUX_m_vrg_source_prio_16$write_1__SEL_1,
MUX_m_vrg_source_prio_2$write_1__SEL_1,
MUX_m_vrg_source_prio_3$write_1__SEL_1,
MUX_m_vrg_source_prio_4$write_1__SEL_1,
MUX_m_vrg_source_prio_5$write_1__SEL_1,
MUX_m_vrg_source_prio_6$write_1__SEL_1,
MUX_m_vrg_source_prio_7$write_1__SEL_1,
MUX_m_vrg_source_prio_8$write_1__SEL_1,
MUX_m_vrg_source_prio_9$write_1__SEL_1,
MUX_m_vrg_target_threshold_0$write_1__SEL_1,
MUX_m_vrg_target_threshold_1$write_1__SEL_1,
MUX_m_vvrg_ie_0_0$write_1__SEL_1,
MUX_m_vvrg_ie_0_0$write_1__VAL_1,
MUX_m_vvrg_ie_0_1$write_1__SEL_1,
MUX_m_vvrg_ie_0_1$write_1__VAL_1,
MUX_m_vvrg_ie_0_10$write_1__SEL_1,
MUX_m_vvrg_ie_0_10$write_1__VAL_1,
MUX_m_vvrg_ie_0_11$write_1__SEL_1,
MUX_m_vvrg_ie_0_11$write_1__VAL_1,
MUX_m_vvrg_ie_0_12$write_1__SEL_1,
MUX_m_vvrg_ie_0_12$write_1__VAL_1,
MUX_m_vvrg_ie_0_13$write_1__SEL_1,
MUX_m_vvrg_ie_0_13$write_1__VAL_1,
MUX_m_vvrg_ie_0_14$write_1__SEL_1,
MUX_m_vvrg_ie_0_14$write_1__VAL_1,
MUX_m_vvrg_ie_0_15$write_1__SEL_1,
MUX_m_vvrg_ie_0_15$write_1__VAL_1,
MUX_m_vvrg_ie_0_16$write_1__SEL_1,
MUX_m_vvrg_ie_0_16$write_1__VAL_1,
MUX_m_vvrg_ie_0_2$write_1__SEL_1,
MUX_m_vvrg_ie_0_2$write_1__VAL_1,
MUX_m_vvrg_ie_0_3$write_1__SEL_1,
MUX_m_vvrg_ie_0_3$write_1__VAL_1,
MUX_m_vvrg_ie_0_4$write_1__SEL_1,
MUX_m_vvrg_ie_0_4$write_1__VAL_1,
MUX_m_vvrg_ie_0_5$write_1__SEL_1,
MUX_m_vvrg_ie_0_5$write_1__VAL_1,
MUX_m_vvrg_ie_0_6$write_1__SEL_1,
MUX_m_vvrg_ie_0_6$write_1__VAL_1,
MUX_m_vvrg_ie_0_7$write_1__SEL_1,
MUX_m_vvrg_ie_0_7$write_1__VAL_1,
MUX_m_vvrg_ie_0_8$write_1__SEL_1,
MUX_m_vvrg_ie_0_8$write_1__VAL_1,
MUX_m_vvrg_ie_0_9$write_1__SEL_1,
MUX_m_vvrg_ie_0_9$write_1__VAL_1,
MUX_m_vvrg_ie_1_0$write_1__SEL_1,
MUX_m_vvrg_ie_1_0$write_1__VAL_1,
MUX_m_vvrg_ie_1_1$write_1__SEL_1,
MUX_m_vvrg_ie_1_1$write_1__VAL_1,
MUX_m_vvrg_ie_1_10$write_1__SEL_1,
MUX_m_vvrg_ie_1_10$write_1__VAL_1,
MUX_m_vvrg_ie_1_11$write_1__SEL_1,
MUX_m_vvrg_ie_1_11$write_1__VAL_1,
MUX_m_vvrg_ie_1_12$write_1__SEL_1,
MUX_m_vvrg_ie_1_12$write_1__VAL_1,
MUX_m_vvrg_ie_1_13$write_1__SEL_1,
MUX_m_vvrg_ie_1_13$write_1__VAL_1,
MUX_m_vvrg_ie_1_14$write_1__SEL_1,
MUX_m_vvrg_ie_1_14$write_1__VAL_1,
MUX_m_vvrg_ie_1_15$write_1__SEL_1,
MUX_m_vvrg_ie_1_15$write_1__VAL_1,
MUX_m_vvrg_ie_1_16$write_1__SEL_1,
MUX_m_vvrg_ie_1_16$write_1__VAL_1,
MUX_m_vvrg_ie_1_2$write_1__SEL_1,
MUX_m_vvrg_ie_1_2$write_1__VAL_1,
MUX_m_vvrg_ie_1_3$write_1__SEL_1,
MUX_m_vvrg_ie_1_3$write_1__VAL_1,
MUX_m_vvrg_ie_1_4$write_1__SEL_1,
MUX_m_vvrg_ie_1_4$write_1__VAL_1,
MUX_m_vvrg_ie_1_5$write_1__SEL_1,
MUX_m_vvrg_ie_1_5$write_1__VAL_1,
MUX_m_vvrg_ie_1_6$write_1__SEL_1,
MUX_m_vvrg_ie_1_6$write_1__VAL_1,
MUX_m_vvrg_ie_1_7$write_1__SEL_1,
MUX_m_vvrg_ie_1_7$write_1__VAL_1,
MUX_m_vvrg_ie_1_8$write_1__SEL_1,
MUX_m_vvrg_ie_1_8$write_1__VAL_1,
MUX_m_vvrg_ie_1_9$write_1__SEL_1,
MUX_m_vvrg_ie_1_9$write_1__VAL_1;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h86246;
reg [31 : 0] v__h86441;
reg [31 : 0] v__h86636;
reg [31 : 0] v__h86831;
reg [31 : 0] v__h87026;
reg [31 : 0] v__h87221;
reg [31 : 0] v__h87416;
reg [31 : 0] v__h87611;
reg [31 : 0] v__h87806;
reg [31 : 0] v__h88001;
reg [31 : 0] v__h88196;
reg [31 : 0] v__h88391;
reg [31 : 0] v__h88586;
reg [31 : 0] v__h88781;
reg [31 : 0] v__h88976;
reg [31 : 0] v__h89171;
reg [31 : 0] v__h5962;
reg [31 : 0] v__h13331;
reg [31 : 0] v__h13514;
reg [31 : 0] v__h13730;
reg [31 : 0] v__h13976;
reg [31 : 0] v__h18445;
reg [31 : 0] v__h24057;
reg [31 : 0] v__h26355;
reg [31 : 0] v__h26568;
reg [31 : 0] v__h26773;
reg [31 : 0] v__h27053;
reg [31 : 0] v__h27284;
reg [31 : 0] v__h28359;
reg [31 : 0] v__h28531;
reg [31 : 0] v__h76647;
reg [31 : 0] v__h76947;
reg [31 : 0] v__h77579;
reg [31 : 0] v__h77673;
reg [31 : 0] v__h77844;
reg [31 : 0] v__h78064;
reg [31 : 0] v__h85245;
reg [31 : 0] v__h85351;
reg [31 : 0] v__h85478;
reg [31 : 0] v__h5956;
reg [31 : 0] v__h13325;
reg [31 : 0] v__h13508;
reg [31 : 0] v__h13724;
reg [31 : 0] v__h13970;
reg [31 : 0] v__h18439;
reg [31 : 0] v__h24051;
reg [31 : 0] v__h26349;
reg [31 : 0] v__h26562;
reg [31 : 0] v__h26767;
reg [31 : 0] v__h27047;
reg [31 : 0] v__h27278;
reg [31 : 0] v__h28353;
reg [31 : 0] v__h28525;
reg [31 : 0] v__h76641;
reg [31 : 0] v__h76941;
reg [31 : 0] v__h77573;
reg [31 : 0] v__h77667;
reg [31 : 0] v__h77838;
reg [31 : 0] v__h78058;
reg [31 : 0] v__h85239;
reg [31 : 0] v__h85345;
reg [31 : 0] v__h85472;
reg [31 : 0] v__h86240;
reg [31 : 0] v__h86435;
reg [31 : 0] v__h86630;
reg [31 : 0] v__h86825;
reg [31 : 0] v__h87020;
reg [31 : 0] v__h87215;
reg [31 : 0] v__h87410;
reg [31 : 0] v__h87605;
reg [31 : 0] v__h87800;
reg [31 : 0] v__h87995;
reg [31 : 0] v__h88190;
reg [31 : 0] v__h88385;
reg [31 : 0] v__h88580;
reg [31 : 0] v__h88775;
reg [31 : 0] v__h88970;
reg [31 : 0] v__h89165;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] y_avValue_fst__h26466;
reg [2 : 0] x__h13769, x__h24096;
reg [1 : 0] v__h76713, y_avValue_snd__h26467;
reg CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8,
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47,
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48,
SEL_ARR_SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_ETC___d2878,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235,
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514,
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515,
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520;
wire [63 : 0] addr_offset__h13465,
addr_offset__h27245,
rdata___1__h26714,
rdata__h26520,
v__h13689,
v__h13934,
v__h18403,
v__h24016,
v__h24251,
v__h25556,
x__h26677,
y_avValue_fst__h26433,
y_avValue_fst__h26445,
y_avValue_fst__h26461,
y_avValue_fst__h26477,
y_avValue_fst__h26482,
y_avValue_fst__h26493,
y_avValue_fst__h26498,
y_avValue_fst__h26512;
wire [31 : 0] v_ie__h18406,
v_ip__h13937,
wdata32__h27246,
x__h23928,
x__h76716;
wire [9 : 0] source_id__h15937,
source_id__h16044,
source_id__h16117,
source_id__h16190,
source_id__h16263,
source_id__h16336,
source_id__h16409,
source_id__h16482,
source_id__h16555,
source_id__h16628,
source_id__h16701,
source_id__h16774,
source_id__h16847,
source_id__h16920,
source_id__h16993,
source_id__h17066,
source_id__h17139,
source_id__h17212,
source_id__h17285,
source_id__h17358,
source_id__h17431,
source_id__h17504,
source_id__h17577,
source_id__h17650,
source_id__h17723,
source_id__h17796,
source_id__h17869,
source_id__h17942,
source_id__h18015,
source_id__h18088,
source_id__h18161,
source_id__h20405,
source_id__h20581,
source_id__h20689,
source_id__h20797,
source_id__h20905,
source_id__h21013,
source_id__h21121,
source_id__h21229,
source_id__h21337,
source_id__h21445,
source_id__h21553,
source_id__h21661,
source_id__h21769,
source_id__h21877,
source_id__h21985,
source_id__h22093,
source_id__h22201,
source_id__h22309,
source_id__h22417,
source_id__h22525,
source_id__h22633,
source_id__h22741,
source_id__h22849,
source_id__h22957,
source_id__h23065,
source_id__h23173,
source_id__h23281,
source_id__h23389,
source_id__h23497,
source_id__h23605,
source_id__h23713,
source_id__h30233,
source_id__h31729,
source_id__h33225,
source_id__h34721,
source_id__h36217,
source_id__h37713,
source_id__h39209,
source_id__h40705,
source_id__h42201,
source_id__h43697,
source_id__h45193,
source_id__h46689,
source_id__h48185,
source_id__h49681,
source_id__h51177,
source_id__h52673,
source_id__h54169,
source_id__h55665,
source_id__h57161,
source_id__h58657,
source_id__h60153,
source_id__h61649,
source_id__h63145,
source_id__h64641,
source_id__h66137,
source_id__h67633,
source_id__h69129,
source_id__h70625,
source_id__h72121,
source_id__h73617,
source_id__h75113,
source_id_base__h13893,
source_id_base__h28620;
wire [4 : 0] IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3078,
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3172,
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667,
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3080,
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3174,
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669,
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3082,
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3176,
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671,
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3070,
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3164,
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659,
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3072,
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3166,
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661,
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3074,
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3168,
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663,
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3076,
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3170,
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665,
b__h81741,
b__h83895,
max_id__h24210;
wire [2 : 0] IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3037,
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3131,
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615,
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3042,
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3136,
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622,
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3047,
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3141,
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629,
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3052,
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3146,
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636,
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3057,
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3151,
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643,
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3062,
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3156,
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d2992,
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3086,
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552,
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d2997,
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3091,
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559,
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3002,
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3096,
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566,
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3007,
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3101,
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573,
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3012,
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3106,
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580,
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3017,
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3111,
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587,
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3022,
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3116,
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594,
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3027,
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3121,
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601,
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3032,
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3126,
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608,
a__h81740,
a__h83894;
wire [1 : 0] rresp__h26521,
v__h27250,
v__h27435,
v__h27448,
v__h28425,
v__h28444,
v__h28597,
v__h28616,
v__h76750,
y_avValue_snd__h26446,
y_avValue_snd__h26462,
y_avValue_snd__h26478,
y_avValue_snd__h26483,
y_avValue_snd__h26494,
y_avValue_snd__h26499,
y_avValue_snd__h26513;
wire IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d748,
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750,
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2874,
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2950,
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952,
NOT_m_cfg_verbosity_read_ULE_1_5___d16,
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248,
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538,
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695,
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d733,
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2844,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2857,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2868,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2923,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2935,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d826,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d880,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d892,
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956,
NOT_m_vrg_source_busy_10_983_284_AND_NOT_m_cfg_ETC___d3288,
NOT_m_vrg_source_busy_11_984_292_AND_NOT_m_cfg_ETC___d3296,
NOT_m_vrg_source_busy_12_985_300_AND_NOT_m_cfg_ETC___d3304,
NOT_m_vrg_source_busy_13_986_308_AND_NOT_m_cfg_ETC___d3312,
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_dfoo320,
_dfoo321,
_dfoo322,
_dfoo323,
_dfoo324,
_dfoo325,
_dfoo326,
_dfoo327,
_dfoo328,
_dfoo329,
_dfoo33,
_dfoo330,
_dfoo331,
_dfoo332,
_dfoo333,
_dfoo334,
_dfoo335,
_dfoo336,
_dfoo337,
_dfoo338,
_dfoo339,
_dfoo34,
_dfoo340,
_dfoo342,
_dfoo344,
_dfoo346,
_dfoo348,
_dfoo35,
_dfoo350,
_dfoo352,
_dfoo354,
_dfoo356,
_dfoo358,
_dfoo36,
_dfoo360,
_dfoo362,
_dfoo364,
_dfoo366,
_dfoo368,
_dfoo37,
_dfoo370,
_dfoo372,
_dfoo374,
_dfoo376,
_dfoo378,
_dfoo38,
_dfoo380,
_dfoo382,
_dfoo384,
_dfoo386,
_dfoo388,
_dfoo39,
_dfoo390,
_dfoo392,
_dfoo394,
_dfoo396,
_dfoo398,
_dfoo4,
_dfoo40,
_dfoo400,
_dfoo402,
_dfoo404,
_dfoo406,
_dfoo408,
_dfoo409,
_dfoo41,
_dfoo410,
_dfoo411,
_dfoo412,
_dfoo413,
_dfoo414,
_dfoo415,
_dfoo416,
_dfoo417,
_dfoo418,
_dfoo419,
_dfoo42,
_dfoo420,
_dfoo421,
_dfoo422,
_dfoo423,
_dfoo424,
_dfoo425,
_dfoo426,
_dfoo427,
_dfoo428,
_dfoo429,
_dfoo43,
_dfoo430,
_dfoo431,
_dfoo432,
_dfoo433,
_dfoo434,
_dfoo435,
_dfoo436,
_dfoo437,
_dfoo438,
_dfoo439,
_dfoo44,
_dfoo440,
_dfoo441,
_dfoo442,
_dfoo443,
_dfoo444,
_dfoo445,
_dfoo446,
_dfoo447,
_dfoo448,
_dfoo449,
_dfoo45,
_dfoo450,
_dfoo451,
_dfoo452,
_dfoo453,
_dfoo454,
_dfoo455,
_dfoo456,
_dfoo457,
_dfoo458,
_dfoo459,
_dfoo46,
_dfoo460,
_dfoo461,
_dfoo462,
_dfoo463,
_dfoo464,
_dfoo465,
_dfoo466,
_dfoo467,
_dfoo468,
_dfoo469,
_dfoo47,
_dfoo470,
_dfoo471,
_dfoo472,
_dfoo473,
_dfoo474,
_dfoo475,
_dfoo476,
_dfoo478,
_dfoo48,
_dfoo480,
_dfoo482,
_dfoo484,
_dfoo486,
_dfoo488,
_dfoo49,
_dfoo490,
_dfoo492,
_dfoo494,
_dfoo496,
_dfoo498,
_dfoo5,
_dfoo50,
_dfoo500,
_dfoo502,
_dfoo504,
_dfoo506,
_dfoo508,
_dfoo51,
_dfoo510,
_dfoo512,
_dfoo514,
_dfoo516,
_dfoo518,
_dfoo52,
_dfoo520,
_dfoo522,
_dfoo524,
_dfoo526,
_dfoo528,
_dfoo53,
_dfoo530,
_dfoo532,
_dfoo534,
_dfoo536,
_dfoo538,
_dfoo54,
_dfoo540,
_dfoo542,
_dfoo544,
_dfoo545,
_dfoo546,
_dfoo547,
_dfoo548,
_dfoo549,
_dfoo55,
_dfoo550,
_dfoo551,
_dfoo552,
_dfoo553,
_dfoo554,
_dfoo555,
_dfoo556,
_dfoo557,
_dfoo558,
_dfoo559,
_dfoo56,
_dfoo560,
_dfoo561,
_dfoo562,
_dfoo563,
_dfoo564,
_dfoo565,
_dfoo566,
_dfoo567,
_dfoo568,
_dfoo569,
_dfoo57,
_dfoo570,
_dfoo571,
_dfoo572,
_dfoo573,
_dfoo574,
_dfoo575,
_dfoo576,
_dfoo577,
_dfoo578,
_dfoo579,
_dfoo58,
_dfoo580,
_dfoo581,
_dfoo582,
_dfoo583,
_dfoo584,
_dfoo585,
_dfoo586,
_dfoo587,
_dfoo588,
_dfoo589,
_dfoo59,
_dfoo590,
_dfoo591,
_dfoo592,
_dfoo593,
_dfoo594,
_dfoo595,
_dfoo596,
_dfoo597,
_dfoo598,
_dfoo599,
_dfoo6,
_dfoo60,
_dfoo600,
_dfoo601,
_dfoo602,
_dfoo603,
_dfoo604,
_dfoo605,
_dfoo606,
_dfoo607,
_dfoo608,
_dfoo609,
_dfoo61,
_dfoo610,
_dfoo611,
_dfoo612,
_dfoo614,
_dfoo616,
_dfoo618,
_dfoo62,
_dfoo620,
_dfoo622,
_dfoo624,
_dfoo626,
_dfoo628,
_dfoo63,
_dfoo630,
_dfoo632,
_dfoo634,
_dfoo636,
_dfoo638,
_dfoo64,
_dfoo640,
_dfoo642,
_dfoo644,
_dfoo646,
_dfoo648,
_dfoo65,
_dfoo650,
_dfoo652,
_dfoo654,
_dfoo656,
_dfoo658,
_dfoo66,
_dfoo660,
_dfoo662,
_dfoo664,
_dfoo666,
_dfoo668,
_dfoo67,
_dfoo670,
_dfoo672,
_dfoo674,
_dfoo676,
_dfoo678,
_dfoo68,
_dfoo680,
_dfoo681,
_dfoo682,
_dfoo683,
_dfoo684,
_dfoo685,
_dfoo686,
_dfoo687,
_dfoo688,
_dfoo689,
_dfoo690,
_dfoo691,
_dfoo692,
_dfoo693,
_dfoo694,
_dfoo695,
_dfoo696,
_dfoo697,
_dfoo698,
_dfoo699,
_dfoo7,
_dfoo70,
_dfoo700,
_dfoo701,
_dfoo702,
_dfoo703,
_dfoo704,
_dfoo705,
_dfoo706,
_dfoo707,
_dfoo708,
_dfoo709,
_dfoo710,
_dfoo711,
_dfoo712,
_dfoo713,
_dfoo714,
_dfoo715,
_dfoo716,
_dfoo717,
_dfoo718,
_dfoo719,
_dfoo72,
_dfoo720,
_dfoo721,
_dfoo722,
_dfoo723,
_dfoo724,
_dfoo725,
_dfoo726,
_dfoo727,
_dfoo728,
_dfoo729,
_dfoo730,
_dfoo731,
_dfoo732,
_dfoo733,
_dfoo734,
_dfoo735,
_dfoo736,
_dfoo737,
_dfoo738,
_dfoo739,
_dfoo74,
_dfoo740,
_dfoo741,
_dfoo742,
_dfoo743,
_dfoo744,
_dfoo745,
_dfoo746,
_dfoo747,
_dfoo748,
_dfoo750,
_dfoo752,
_dfoo754,
_dfoo756,
_dfoo758,
_dfoo76,
_dfoo760,
_dfoo762,
_dfoo764,
_dfoo766,
_dfoo768,
_dfoo770,
_dfoo772,
_dfoo774,
_dfoo776,
_dfoo778,
_dfoo78,
_dfoo780,
_dfoo782,
_dfoo784,
_dfoo786,
_dfoo788,
_dfoo790,
_dfoo792,
_dfoo794,
_dfoo796,
_dfoo798,
_dfoo8,
_dfoo80,
_dfoo800,
_dfoo802,
_dfoo804,
_dfoo806,
_dfoo808,
_dfoo810,
_dfoo812,
_dfoo814,
_dfoo816,
_dfoo817,
_dfoo818,
_dfoo819,
_dfoo82,
_dfoo820,
_dfoo821,
_dfoo822,
_dfoo823,
_dfoo824,
_dfoo825,
_dfoo826,
_dfoo827,
_dfoo828,
_dfoo829,
_dfoo830,
_dfoo831,
_dfoo832,
_dfoo833,
_dfoo834,
_dfoo835,
_dfoo836,
_dfoo837,
_dfoo838,
_dfoo839,
_dfoo84,
_dfoo840,
_dfoo841,
_dfoo842,
_dfoo843,
_dfoo844,
_dfoo845,
_dfoo846,
_dfoo847,
_dfoo848,
_dfoo849,
_dfoo850,
_dfoo851,
_dfoo852,
_dfoo853,
_dfoo854,
_dfoo855,
_dfoo856,
_dfoo857,
_dfoo858,
_dfoo859,
_dfoo86,
_dfoo860,
_dfoo861,
_dfoo862,
_dfoo863,
_dfoo864,
_dfoo865,
_dfoo866,
_dfoo867,
_dfoo868,
_dfoo869,
_dfoo870,
_dfoo871,
_dfoo872,
_dfoo873,
_dfoo874,
_dfoo875,
_dfoo876,
_dfoo877,
_dfoo878,
_dfoo879,
_dfoo88,
_dfoo880,
_dfoo881,
_dfoo882,
_dfoo883,
_dfoo884,
_dfoo886,
_dfoo888,
_dfoo890,
_dfoo892,
_dfoo894,
_dfoo896,
_dfoo898,
_dfoo9,
_dfoo90,
_dfoo900,
_dfoo902,
_dfoo904,
_dfoo906,
_dfoo908,
_dfoo910,
_dfoo912,
_dfoo914,
_dfoo916,
_dfoo918,
_dfoo92,
_dfoo920,
_dfoo922,
_dfoo924,
_dfoo926,
_dfoo928,
_dfoo930,
_dfoo932,
_dfoo934,
_dfoo936,
_dfoo938,
_dfoo94,
_dfoo940,
_dfoo942,
_dfoo944,
_dfoo946,
_dfoo948,
_dfoo950,
_dfoo952,
_dfoo953,
_dfoo954,
_dfoo955,
_dfoo956,
_dfoo957,
_dfoo958,
_dfoo959,
_dfoo96,
_dfoo960,
_dfoo961,
_dfoo962,
_dfoo963,
_dfoo964,
_dfoo965,
_dfoo966,
_dfoo967,
_dfoo968,
_dfoo969,
_dfoo970,
_dfoo971,
_dfoo972,
_dfoo973,
_dfoo974,
_dfoo975,
_dfoo976,
_dfoo977,
_dfoo978,
_dfoo979,
_dfoo98,
_dfoo980,
_dfoo981,
_dfoo982,
_dfoo983,
_dfoo984,
_dfoo985,
_dfoo986,
_dfoo987,
_dfoo988,
_dfoo989,
_dfoo990,
_dfoo991,
_dfoo992,
_dfoo993,
_dfoo994,
_dfoo995,
_dfoo996,
_dfoo997,
_dfoo998,
_dfoo999,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2860,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2862,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d837,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d839,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d841,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d843,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d845,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d847,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d849,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d851,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d853,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d855,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d857,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d859,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d861,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d863,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d865,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d867,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d869,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895,
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931,
m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3036,
m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3130,
m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614,
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3041,
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3135,
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621,
m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3046,
m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3140,
m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628,
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3051,
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3145,
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635,
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d686,
m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3056,
m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3150,
m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642,
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3061,
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3155,
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649,
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3066,
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3160,
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656,
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d689,
m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551,
m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d2996,
m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3090,
m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558,
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3001,
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3095,
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565,
m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3006,
m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3100,
m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572,
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3011,
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3105,
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579,
m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3016,
m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3110,
m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586,
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3021,
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3115,
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593,
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d680,
m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3026,
m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3120,
m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600,
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3031,
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3125,
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607,
m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method show_PLIC_state
assign RDY_show_PLIC_state = 1'd1 ;
assign CAN_FIRE_show_PLIC_state = 1'd1 ;
assign WILL_FIRE_show_PLIC_state = EN_show_PLIC_state ;
// action method server_reset_request_put
assign RDY_server_reset_request_put = m_f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_reset_request_put = m_f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get = m_f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get = m_f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method set_addr_map
assign RDY_set_addr_map = 1'd1 ;
assign CAN_FIRE_set_addr_map = 1'd1 ;
assign WILL_FIRE_set_addr_map = EN_set_addr_map ;
// action method axi4_slave_m_awvalid
assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ;
// value method axi4_slave_m_awready
assign axi4_slave_awready = m_slave_xactor_f_wr_addr$FULL_N ;
// action method axi4_slave_m_wvalid
assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ;
// value method axi4_slave_m_wready
assign axi4_slave_wready = m_slave_xactor_f_wr_data$FULL_N ;
// value method axi4_slave_m_bvalid
assign axi4_slave_bvalid = m_slave_xactor_f_wr_resp$EMPTY_N ;
// value method axi4_slave_m_bid
assign axi4_slave_bid = m_slave_xactor_f_wr_resp$D_OUT[17:2] ;
// value method axi4_slave_m_bresp
assign axi4_slave_bresp = m_slave_xactor_f_wr_resp$D_OUT[1:0] ;
// action method axi4_slave_m_bready
assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ;
// action method axi4_slave_m_arvalid
assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ;
// value method axi4_slave_m_arready
assign axi4_slave_arready = m_slave_xactor_f_rd_addr$FULL_N ;
// value method axi4_slave_m_rvalid
assign axi4_slave_rvalid = m_slave_xactor_f_rd_data$EMPTY_N ;
// value method axi4_slave_m_rid
assign axi4_slave_rid = m_slave_xactor_f_rd_data$D_OUT[82:67] ;
// value method axi4_slave_m_rdata
assign axi4_slave_rdata = m_slave_xactor_f_rd_data$D_OUT[66:3] ;
// value method axi4_slave_m_rresp
assign axi4_slave_rresp = m_slave_xactor_f_rd_data$D_OUT[2:1] ;
// value method axi4_slave_m_rlast
assign axi4_slave_rlast = m_slave_xactor_f_rd_data$D_OUT[0] ;
// action method axi4_slave_m_rready
assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ;
// action method v_sources_0_m_interrupt_req
assign CAN_FIRE_v_sources_0_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_0_m_interrupt_req = 1'd1 ;
// action method v_sources_1_m_interrupt_req
assign CAN_FIRE_v_sources_1_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_1_m_interrupt_req = 1'd1 ;
// action method v_sources_2_m_interrupt_req
assign CAN_FIRE_v_sources_2_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_2_m_interrupt_req = 1'd1 ;
// action method v_sources_3_m_interrupt_req
assign CAN_FIRE_v_sources_3_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_3_m_interrupt_req = 1'd1 ;
// action method v_sources_4_m_interrupt_req
assign CAN_FIRE_v_sources_4_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_4_m_interrupt_req = 1'd1 ;
// action method v_sources_5_m_interrupt_req
assign CAN_FIRE_v_sources_5_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_5_m_interrupt_req = 1'd1 ;
// action method v_sources_6_m_interrupt_req
assign CAN_FIRE_v_sources_6_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_6_m_interrupt_req = 1'd1 ;
// action method v_sources_7_m_interrupt_req
assign CAN_FIRE_v_sources_7_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_7_m_interrupt_req = 1'd1 ;
// action method v_sources_8_m_interrupt_req
assign CAN_FIRE_v_sources_8_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_8_m_interrupt_req = 1'd1 ;
// action method v_sources_9_m_interrupt_req
assign CAN_FIRE_v_sources_9_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_9_m_interrupt_req = 1'd1 ;
// action method v_sources_10_m_interrupt_req
assign CAN_FIRE_v_sources_10_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_10_m_interrupt_req = 1'd1 ;
// action method v_sources_11_m_interrupt_req
assign CAN_FIRE_v_sources_11_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_11_m_interrupt_req = 1'd1 ;
// action method v_sources_12_m_interrupt_req
assign CAN_FIRE_v_sources_12_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_12_m_interrupt_req = 1'd1 ;
// action method v_sources_13_m_interrupt_req
assign CAN_FIRE_v_sources_13_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_13_m_interrupt_req = 1'd1 ;
// action method v_sources_14_m_interrupt_req
assign CAN_FIRE_v_sources_14_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_14_m_interrupt_req = 1'd1 ;
// action method v_sources_15_m_interrupt_req
assign CAN_FIRE_v_sources_15_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_v_sources_15_m_interrupt_req = 1'd1 ;
// value method v_targets_0_m_eip
assign v_targets_0_m_eip = a__h81740 > m_vrg_target_threshold_0 ;
// value method v_targets_1_m_eip
assign v_targets_1_m_eip = a__h83894 > m_vrg_target_threshold_1 ;
// submodule m_f_reset_reqs
FIFO20 #(.guarded(1'd1)) m_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(m_f_reset_reqs$ENQ),
.DEQ(m_f_reset_reqs$DEQ),
.CLR(m_f_reset_reqs$CLR),
.FULL_N(m_f_reset_reqs$FULL_N),
.EMPTY_N(m_f_reset_reqs$EMPTY_N));
// submodule m_f_reset_rsps
FIFO20 #(.guarded(1'd1)) m_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(m_f_reset_rsps$ENQ),
.DEQ(m_f_reset_rsps$DEQ),
.CLR(m_f_reset_rsps$CLR),
.FULL_N(m_f_reset_rsps$FULL_N),
.EMPTY_N(m_f_reset_rsps$EMPTY_N));
// submodule m_slave_xactor_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) m_slave_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(m_slave_xactor_f_rd_addr$D_IN),
.ENQ(m_slave_xactor_f_rd_addr$ENQ),
.DEQ(m_slave_xactor_f_rd_addr$DEQ),
.CLR(m_slave_xactor_f_rd_addr$CLR),
.D_OUT(m_slave_xactor_f_rd_addr$D_OUT),
.FULL_N(m_slave_xactor_f_rd_addr$FULL_N),
.EMPTY_N(m_slave_xactor_f_rd_addr$EMPTY_N));
// submodule m_slave_xactor_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(1'd1)) m_slave_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(m_slave_xactor_f_rd_data$D_IN),
.ENQ(m_slave_xactor_f_rd_data$ENQ),
.DEQ(m_slave_xactor_f_rd_data$DEQ),
.CLR(m_slave_xactor_f_rd_data$CLR),
.D_OUT(m_slave_xactor_f_rd_data$D_OUT),
.FULL_N(m_slave_xactor_f_rd_data$FULL_N),
.EMPTY_N(m_slave_xactor_f_rd_data$EMPTY_N));
// submodule m_slave_xactor_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) m_slave_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(m_slave_xactor_f_wr_addr$D_IN),
.ENQ(m_slave_xactor_f_wr_addr$ENQ),
.DEQ(m_slave_xactor_f_wr_addr$DEQ),
.CLR(m_slave_xactor_f_wr_addr$CLR),
.D_OUT(m_slave_xactor_f_wr_addr$D_OUT),
.FULL_N(m_slave_xactor_f_wr_addr$FULL_N),
.EMPTY_N(m_slave_xactor_f_wr_addr$EMPTY_N));
// submodule m_slave_xactor_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) m_slave_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(m_slave_xactor_f_wr_data$D_IN),
.ENQ(m_slave_xactor_f_wr_data$ENQ),
.DEQ(m_slave_xactor_f_wr_data$DEQ),
.CLR(m_slave_xactor_f_wr_data$CLR),
.D_OUT(m_slave_xactor_f_wr_data$D_OUT),
.FULL_N(m_slave_xactor_f_wr_data$FULL_N),
.EMPTY_N(m_slave_xactor_f_wr_data$EMPTY_N));
// submodule m_slave_xactor_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(1'd1)) m_slave_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(m_slave_xactor_f_wr_resp$D_IN),
.ENQ(m_slave_xactor_f_wr_resp$ENQ),
.DEQ(m_slave_xactor_f_wr_resp$DEQ),
.CLR(m_slave_xactor_f_wr_resp$CLR),
.D_OUT(m_slave_xactor_f_wr_resp$D_OUT),
.FULL_N(m_slave_xactor_f_wr_resp$FULL_N),
.EMPTY_N(m_slave_xactor_f_wr_resp$EMPTY_N));
// rule RL_m_rl_reset
assign CAN_FIRE_RL_m_rl_reset =
m_f_reset_reqs$EMPTY_N && m_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_m_rl_reset = CAN_FIRE_RL_m_rl_reset ;
// rule RL_m_rl_process_rd_req
assign CAN_FIRE_RL_m_rl_process_rd_req =
m_slave_xactor_f_rd_addr$EMPTY_N &&
m_slave_xactor_f_rd_data$FULL_N &&
!m_f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_m_rl_process_rd_req = CAN_FIRE_RL_m_rl_process_rd_req ;
// rule RL_m_rl_process_wr_req
assign CAN_FIRE_RL_m_rl_process_wr_req =
m_slave_xactor_f_wr_addr$EMPTY_N &&
m_slave_xactor_f_wr_data$EMPTY_N &&
m_slave_xactor_f_wr_resp$FULL_N &&
!m_f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_m_rl_process_wr_req = CAN_FIRE_RL_m_rl_process_wr_req ;
// inputs to muxes for submodule ports
assign MUX_m_vrg_source_busy_0$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd0 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_0$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd0 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_1$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd1 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_1$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd1 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_10$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd10 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_10$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd10 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_11$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd11 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_11$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd11 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_12$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd12 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_12$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd12 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_13$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd13 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_13$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd13 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_14$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd14 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_14$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd14 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_15$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd15 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_15$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd15 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_16$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd16 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_16$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd16 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_2$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd2 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_2$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd2 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_3$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd3 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_3$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd3 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_4$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd4 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_4$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd4 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_5$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd5 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_5$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd5 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_6$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd6 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_6$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd6 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_7$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd7 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_7$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd7 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_8$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd8 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_8$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd8 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_busy_9$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd9 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ;
assign MUX_m_vrg_source_busy_9$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd9 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ;
assign MUX_m_vrg_source_prio_0$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
addr_offset__h27245[11:2] == 10'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d826 ;
assign MUX_m_vrg_source_prio_1$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d837 ;
assign MUX_m_vrg_source_prio_10$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d855 ;
assign MUX_m_vrg_source_prio_11$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d857 ;
assign MUX_m_vrg_source_prio_12$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d859 ;
assign MUX_m_vrg_source_prio_13$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d861 ;
assign MUX_m_vrg_source_prio_14$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d863 ;
assign MUX_m_vrg_source_prio_15$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d865 ;
assign MUX_m_vrg_source_prio_16$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d867 ;
assign MUX_m_vrg_source_prio_2$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d839 ;
assign MUX_m_vrg_source_prio_3$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d841 ;
assign MUX_m_vrg_source_prio_4$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d843 ;
assign MUX_m_vrg_source_prio_5$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d845 ;
assign MUX_m_vrg_source_prio_6$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d847 ;
assign MUX_m_vrg_source_prio_7$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d849 ;
assign MUX_m_vrg_source_prio_8$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d851 ;
assign MUX_m_vrg_source_prio_9$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d853 ;
assign MUX_m_vrg_target_threshold_0$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2860 ;
assign MUX_m_vrg_target_threshold_1$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2862 ;
assign MUX_m_vvrg_ie_0_0$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ;
assign MUX_m_vvrg_ie_0_1$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 ;
assign MUX_m_vvrg_ie_0_10$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 ;
assign MUX_m_vvrg_ie_0_11$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 ;
assign MUX_m_vvrg_ie_0_12$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 ;
assign MUX_m_vvrg_ie_0_13$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 ;
assign MUX_m_vvrg_ie_0_14$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 ;
assign MUX_m_vvrg_ie_0_15$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 ;
assign MUX_m_vvrg_ie_0_16$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 ;
assign MUX_m_vvrg_ie_0_2$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 ;
assign MUX_m_vvrg_ie_0_3$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 ;
assign MUX_m_vvrg_ie_0_4$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 ;
assign MUX_m_vvrg_ie_0_5$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 ;
assign MUX_m_vvrg_ie_0_6$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 ;
assign MUX_m_vvrg_ie_0_7$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 ;
assign MUX_m_vvrg_ie_0_8$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 ;
assign MUX_m_vvrg_ie_0_9$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 ;
assign MUX_m_vvrg_ie_1_0$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 ;
assign MUX_m_vvrg_ie_1_1$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 ;
assign MUX_m_vvrg_ie_1_10$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 ;
assign MUX_m_vvrg_ie_1_11$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 ;
assign MUX_m_vvrg_ie_1_12$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 ;
assign MUX_m_vvrg_ie_1_13$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 ;
assign MUX_m_vvrg_ie_1_14$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 ;
assign MUX_m_vvrg_ie_1_15$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 ;
assign MUX_m_vvrg_ie_1_16$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 ;
assign MUX_m_vvrg_ie_1_2$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 ;
assign MUX_m_vvrg_ie_1_3$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 ;
assign MUX_m_vvrg_ie_1_4$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 ;
assign MUX_m_vvrg_ie_1_5$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 ;
assign MUX_m_vvrg_ie_1_6$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 ;
assign MUX_m_vvrg_ie_1_7$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 ;
assign MUX_m_vvrg_ie_1_8$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 ;
assign MUX_m_vvrg_ie_1_9$write_1__SEL_1 =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ;
assign MUX_m_vvrg_ie_0_0$write_1__VAL_1 =
(source_id_base__h28620 == 10'd0 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2040 ;
assign MUX_m_vvrg_ie_0_1$write_1__VAL_1 =
(source_id_base__h28620 == 10'd1 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2038 ;
assign MUX_m_vvrg_ie_0_10$write_1__VAL_1 =
(source_id_base__h28620 == 10'd10 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2020 ;
assign MUX_m_vvrg_ie_0_11$write_1__VAL_1 =
(source_id_base__h28620 == 10'd11 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2018 ;
assign MUX_m_vvrg_ie_0_12$write_1__VAL_1 =
(source_id_base__h28620 == 10'd12 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2016 ;
assign MUX_m_vvrg_ie_0_13$write_1__VAL_1 =
(source_id_base__h28620 == 10'd13 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2014 ;
assign MUX_m_vvrg_ie_0_14$write_1__VAL_1 =
(source_id_base__h28620 == 10'd14 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2012 ;
assign MUX_m_vvrg_ie_0_15$write_1__VAL_1 =
(source_id_base__h28620 == 10'd15 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2010 ;
assign MUX_m_vvrg_ie_0_16$write_1__VAL_1 =
(source_id_base__h28620 == 10'd16 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2008 ;
assign MUX_m_vvrg_ie_0_2$write_1__VAL_1 =
(source_id_base__h28620 == 10'd2 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2036 ;
assign MUX_m_vvrg_ie_0_3$write_1__VAL_1 =
(source_id_base__h28620 == 10'd3 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2034 ;
assign MUX_m_vvrg_ie_0_4$write_1__VAL_1 =
(source_id_base__h28620 == 10'd4 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2032 ;
assign MUX_m_vvrg_ie_0_5$write_1__VAL_1 =
(source_id_base__h28620 == 10'd5 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2030 ;
assign MUX_m_vvrg_ie_0_6$write_1__VAL_1 =
(source_id_base__h28620 == 10'd6 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2028 ;
assign MUX_m_vvrg_ie_0_7$write_1__VAL_1 =
(source_id_base__h28620 == 10'd7 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2026 ;
assign MUX_m_vvrg_ie_0_8$write_1__VAL_1 =
(source_id_base__h28620 == 10'd8 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2024 ;
assign MUX_m_vvrg_ie_0_9$write_1__VAL_1 =
(source_id_base__h28620 == 10'd9 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895) ?
wdata32__h27246[0] :
_dfoo2022 ;
assign MUX_m_vvrg_ie_1_0$write_1__VAL_1 =
(source_id_base__h28620 == 10'd0 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo2006 ;
assign MUX_m_vvrg_ie_1_1$write_1__VAL_1 =
(source_id_base__h28620 == 10'd1 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo2004 ;
assign MUX_m_vvrg_ie_1_10$write_1__VAL_1 =
(source_id_base__h28620 == 10'd10 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1986 ;
assign MUX_m_vvrg_ie_1_11$write_1__VAL_1 =
(source_id_base__h28620 == 10'd11 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1984 ;
assign MUX_m_vvrg_ie_1_12$write_1__VAL_1 =
(source_id_base__h28620 == 10'd12 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1982 ;
assign MUX_m_vvrg_ie_1_13$write_1__VAL_1 =
(source_id_base__h28620 == 10'd13 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1980 ;
assign MUX_m_vvrg_ie_1_14$write_1__VAL_1 =
(source_id_base__h28620 == 10'd14 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1978 ;
assign MUX_m_vvrg_ie_1_15$write_1__VAL_1 =
(source_id_base__h28620 == 10'd15 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1976 ;
assign MUX_m_vvrg_ie_1_16$write_1__VAL_1 =
(source_id_base__h28620 == 10'd16 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1974 ;
assign MUX_m_vvrg_ie_1_2$write_1__VAL_1 =
(source_id_base__h28620 == 10'd2 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo2002 ;
assign MUX_m_vvrg_ie_1_3$write_1__VAL_1 =
(source_id_base__h28620 == 10'd3 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo2000 ;
assign MUX_m_vvrg_ie_1_4$write_1__VAL_1 =
(source_id_base__h28620 == 10'd4 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1998 ;
assign MUX_m_vvrg_ie_1_5$write_1__VAL_1 =
(source_id_base__h28620 == 10'd5 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1996 ;
assign MUX_m_vvrg_ie_1_6$write_1__VAL_1 =
(source_id_base__h28620 == 10'd6 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1994 ;
assign MUX_m_vvrg_ie_1_7$write_1__VAL_1 =
(source_id_base__h28620 == 10'd7 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1992 ;
assign MUX_m_vvrg_ie_1_8$write_1__VAL_1 =
(source_id_base__h28620 == 10'd8 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1990 ;
assign MUX_m_vvrg_ie_1_9$write_1__VAL_1 =
(source_id_base__h28620 == 10'd9 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931) ?
wdata32__h27246[0] :
_dfoo1988 ;
// register m_cfg_verbosity
assign m_cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign m_cfg_verbosity$EN = EN_set_verbosity ;
// register m_rg_addr_base
assign m_rg_addr_base$D_IN = set_addr_map_addr_base ;
assign m_rg_addr_base$EN = EN_set_addr_map ;
// register m_rg_addr_lim
assign m_rg_addr_lim$D_IN = set_addr_map_addr_lim ;
assign m_rg_addr_lim$EN = EN_set_addr_map ;
// register m_vrg_source_busy_0
always@(MUX_m_vrg_source_busy_0$write_1__SEL_1 or
MUX_m_vrg_source_busy_0$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_0$write_1__SEL_1: m_vrg_source_busy_0$D_IN = 1'd0;
MUX_m_vrg_source_busy_0$write_1__SEL_2: m_vrg_source_busy_0$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_0$D_IN = 1'd0;
default: m_vrg_source_busy_0$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_0$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd0 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd0 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_1
always@(MUX_m_vrg_source_busy_1$write_1__SEL_1 or
MUX_m_vrg_source_busy_1$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_1$write_1__SEL_1: m_vrg_source_busy_1$D_IN = 1'd0;
MUX_m_vrg_source_busy_1$write_1__SEL_2: m_vrg_source_busy_1$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_1$D_IN = 1'd0;
default: m_vrg_source_busy_1$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_1$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd1 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd1 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_10
always@(MUX_m_vrg_source_busy_10$write_1__SEL_1 or
MUX_m_vrg_source_busy_10$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_10$write_1__SEL_1: m_vrg_source_busy_10$D_IN = 1'd0;
MUX_m_vrg_source_busy_10$write_1__SEL_2: m_vrg_source_busy_10$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_10$D_IN = 1'd0;
default: m_vrg_source_busy_10$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_10$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd10 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd10 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_11
always@(MUX_m_vrg_source_busy_11$write_1__SEL_1 or
MUX_m_vrg_source_busy_11$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_11$write_1__SEL_1: m_vrg_source_busy_11$D_IN = 1'd0;
MUX_m_vrg_source_busy_11$write_1__SEL_2: m_vrg_source_busy_11$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_11$D_IN = 1'd0;
default: m_vrg_source_busy_11$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_11$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd11 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd11 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_12
always@(MUX_m_vrg_source_busy_12$write_1__SEL_1 or
MUX_m_vrg_source_busy_12$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_12$write_1__SEL_1: m_vrg_source_busy_12$D_IN = 1'd0;
MUX_m_vrg_source_busy_12$write_1__SEL_2: m_vrg_source_busy_12$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_12$D_IN = 1'd0;
default: m_vrg_source_busy_12$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_12$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd12 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd12 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_13
always@(MUX_m_vrg_source_busy_13$write_1__SEL_1 or
MUX_m_vrg_source_busy_13$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_13$write_1__SEL_1: m_vrg_source_busy_13$D_IN = 1'd0;
MUX_m_vrg_source_busy_13$write_1__SEL_2: m_vrg_source_busy_13$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_13$D_IN = 1'd0;
default: m_vrg_source_busy_13$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_13$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd13 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd13 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_14
always@(MUX_m_vrg_source_busy_14$write_1__SEL_1 or
MUX_m_vrg_source_busy_14$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_14$write_1__SEL_1: m_vrg_source_busy_14$D_IN = 1'd0;
MUX_m_vrg_source_busy_14$write_1__SEL_2: m_vrg_source_busy_14$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_14$D_IN = 1'd0;
default: m_vrg_source_busy_14$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_14$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd14 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd14 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_15
always@(MUX_m_vrg_source_busy_15$write_1__SEL_1 or
MUX_m_vrg_source_busy_15$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_15$write_1__SEL_1: m_vrg_source_busy_15$D_IN = 1'd0;
MUX_m_vrg_source_busy_15$write_1__SEL_2: m_vrg_source_busy_15$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_15$D_IN = 1'd0;
default: m_vrg_source_busy_15$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_15$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd15 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd15 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_16
always@(MUX_m_vrg_source_busy_16$write_1__SEL_1 or
MUX_m_vrg_source_busy_16$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_16$write_1__SEL_1: m_vrg_source_busy_16$D_IN = 1'd0;
MUX_m_vrg_source_busy_16$write_1__SEL_2: m_vrg_source_busy_16$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_16$D_IN = 1'd0;
default: m_vrg_source_busy_16$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_16$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd16 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd16 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_2
always@(MUX_m_vrg_source_busy_2$write_1__SEL_1 or
MUX_m_vrg_source_busy_2$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_2$write_1__SEL_1: m_vrg_source_busy_2$D_IN = 1'd0;
MUX_m_vrg_source_busy_2$write_1__SEL_2: m_vrg_source_busy_2$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_2$D_IN = 1'd0;
default: m_vrg_source_busy_2$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_2$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd2 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd2 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_3
always@(MUX_m_vrg_source_busy_3$write_1__SEL_1 or
MUX_m_vrg_source_busy_3$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_3$write_1__SEL_1: m_vrg_source_busy_3$D_IN = 1'd0;
MUX_m_vrg_source_busy_3$write_1__SEL_2: m_vrg_source_busy_3$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_3$D_IN = 1'd0;
default: m_vrg_source_busy_3$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_3$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd3 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd3 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_4
always@(MUX_m_vrg_source_busy_4$write_1__SEL_1 or
MUX_m_vrg_source_busy_4$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_4$write_1__SEL_1: m_vrg_source_busy_4$D_IN = 1'd0;
MUX_m_vrg_source_busy_4$write_1__SEL_2: m_vrg_source_busy_4$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_4$D_IN = 1'd0;
default: m_vrg_source_busy_4$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_4$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd4 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd4 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_5
always@(MUX_m_vrg_source_busy_5$write_1__SEL_1 or
MUX_m_vrg_source_busy_5$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_5$write_1__SEL_1: m_vrg_source_busy_5$D_IN = 1'd0;
MUX_m_vrg_source_busy_5$write_1__SEL_2: m_vrg_source_busy_5$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_5$D_IN = 1'd0;
default: m_vrg_source_busy_5$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_5$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd5 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd5 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_6
always@(MUX_m_vrg_source_busy_6$write_1__SEL_1 or
MUX_m_vrg_source_busy_6$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_6$write_1__SEL_1: m_vrg_source_busy_6$D_IN = 1'd0;
MUX_m_vrg_source_busy_6$write_1__SEL_2: m_vrg_source_busy_6$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_6$D_IN = 1'd0;
default: m_vrg_source_busy_6$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_6$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd6 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd6 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_7
always@(MUX_m_vrg_source_busy_7$write_1__SEL_1 or
MUX_m_vrg_source_busy_7$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_7$write_1__SEL_1: m_vrg_source_busy_7$D_IN = 1'd0;
MUX_m_vrg_source_busy_7$write_1__SEL_2: m_vrg_source_busy_7$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_7$D_IN = 1'd0;
default: m_vrg_source_busy_7$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_7$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd7 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd7 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_8
always@(MUX_m_vrg_source_busy_8$write_1__SEL_1 or
MUX_m_vrg_source_busy_8$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_8$write_1__SEL_1: m_vrg_source_busy_8$D_IN = 1'd0;
MUX_m_vrg_source_busy_8$write_1__SEL_2: m_vrg_source_busy_8$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_8$D_IN = 1'd0;
default: m_vrg_source_busy_8$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_8$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd8 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd8 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_busy_9
always@(MUX_m_vrg_source_busy_9$write_1__SEL_1 or
MUX_m_vrg_source_busy_9$write_1__SEL_2 or WILL_FIRE_RL_m_rl_reset)
case (1'b1)
MUX_m_vrg_source_busy_9$write_1__SEL_1: m_vrg_source_busy_9$D_IN = 1'd0;
MUX_m_vrg_source_busy_9$write_1__SEL_2: m_vrg_source_busy_9$D_IN = 1'd1;
WILL_FIRE_RL_m_rl_reset: m_vrg_source_busy_9$D_IN = 1'd0;
default: m_vrg_source_busy_9$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign m_vrg_source_busy_9$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd9 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_process_wr_req &&
wdata32__h27246[9:0] == 10'd9 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_0
assign m_vrg_source_ip_0$D_IN = 1'd0 ;
assign m_vrg_source_ip_0$EN =
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd0 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_1
assign m_vrg_source_ip_1$D_IN =
!MUX_m_vrg_source_busy_1$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_0_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_1$EN =
!m_vrg_source_busy_1 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd1 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_10
assign m_vrg_source_ip_10$D_IN =
!MUX_m_vrg_source_busy_10$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_9_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_10$EN =
!m_vrg_source_busy_10 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd10 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_11
assign m_vrg_source_ip_11$D_IN =
!MUX_m_vrg_source_busy_11$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_10_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_11$EN =
!m_vrg_source_busy_11 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd11 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_12
assign m_vrg_source_ip_12$D_IN =
!MUX_m_vrg_source_busy_12$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_11_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_12$EN =
!m_vrg_source_busy_12 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd12 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_13
assign m_vrg_source_ip_13$D_IN =
!MUX_m_vrg_source_busy_13$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_12_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_13$EN =
!m_vrg_source_busy_13 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd13 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_14
assign m_vrg_source_ip_14$D_IN =
!MUX_m_vrg_source_busy_14$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_13_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_14$EN =
!m_vrg_source_busy_14 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd14 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_15
assign m_vrg_source_ip_15$D_IN =
!MUX_m_vrg_source_busy_15$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_14_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_15$EN =
!m_vrg_source_busy_15 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd15 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_16
assign m_vrg_source_ip_16$D_IN =
!MUX_m_vrg_source_busy_16$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_15_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_16$EN =
!m_vrg_source_busy_16 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd16 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_2
assign m_vrg_source_ip_2$D_IN =
!MUX_m_vrg_source_busy_2$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_1_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_2$EN =
!m_vrg_source_busy_2 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd2 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_3
assign m_vrg_source_ip_3$D_IN =
!MUX_m_vrg_source_busy_3$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_2_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_3$EN =
!m_vrg_source_busy_3 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd3 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_4
assign m_vrg_source_ip_4$D_IN =
!MUX_m_vrg_source_busy_4$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_3_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_4$EN =
!m_vrg_source_busy_4 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd4 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_5
assign m_vrg_source_ip_5$D_IN =
!MUX_m_vrg_source_busy_5$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_4_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_5$EN =
!m_vrg_source_busy_5 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd5 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_6
assign m_vrg_source_ip_6$D_IN =
!MUX_m_vrg_source_busy_6$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_5_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_6$EN =
!m_vrg_source_busy_6 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd6 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_7
assign m_vrg_source_ip_7$D_IN =
!MUX_m_vrg_source_busy_7$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_6_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_7$EN =
!m_vrg_source_busy_7 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd7 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_8
assign m_vrg_source_ip_8$D_IN =
!MUX_m_vrg_source_busy_8$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_7_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_8$EN =
!m_vrg_source_busy_8 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd8 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_ip_9
assign m_vrg_source_ip_9$D_IN =
!MUX_m_vrg_source_busy_9$write_1__SEL_2 &&
!WILL_FIRE_RL_m_rl_reset &&
v_sources_8_m_interrupt_req_set_not_clear ;
assign m_vrg_source_ip_9$EN =
!m_vrg_source_busy_9 ||
WILL_FIRE_RL_m_rl_process_rd_req && max_id__h24210 == 5'd9 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_0
assign m_vrg_source_prio_0$D_IN =
MUX_m_vrg_source_prio_0$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_0$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
addr_offset__h27245[11:2] == 10'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d826 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_1
assign m_vrg_source_prio_1$D_IN =
MUX_m_vrg_source_prio_1$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_1$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d837 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_10
assign m_vrg_source_prio_10$D_IN =
MUX_m_vrg_source_prio_10$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_10$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d855 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_11
assign m_vrg_source_prio_11$D_IN =
MUX_m_vrg_source_prio_11$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_11$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d857 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_12
assign m_vrg_source_prio_12$D_IN =
MUX_m_vrg_source_prio_12$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_12$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d859 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_13
assign m_vrg_source_prio_13$D_IN =
MUX_m_vrg_source_prio_13$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_13$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d861 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_14
assign m_vrg_source_prio_14$D_IN =
MUX_m_vrg_source_prio_14$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_14$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d863 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_15
assign m_vrg_source_prio_15$D_IN =
MUX_m_vrg_source_prio_15$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_15$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d865 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_16
assign m_vrg_source_prio_16$D_IN =
MUX_m_vrg_source_prio_16$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_16$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d867 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_2
assign m_vrg_source_prio_2$D_IN =
MUX_m_vrg_source_prio_2$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_2$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d839 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_3
assign m_vrg_source_prio_3$D_IN =
MUX_m_vrg_source_prio_3$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_3$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d841 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_4
assign m_vrg_source_prio_4$D_IN =
MUX_m_vrg_source_prio_4$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_4$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d843 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_5
assign m_vrg_source_prio_5$D_IN =
MUX_m_vrg_source_prio_5$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_5$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d845 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_6
assign m_vrg_source_prio_6$D_IN =
MUX_m_vrg_source_prio_6$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_6$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d847 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_7
assign m_vrg_source_prio_7$D_IN =
MUX_m_vrg_source_prio_7$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_7$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d849 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_8
assign m_vrg_source_prio_8$D_IN =
MUX_m_vrg_source_prio_8$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_8$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d851 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_source_prio_9
assign m_vrg_source_prio_9$D_IN =
MUX_m_vrg_source_prio_9$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd0 ;
assign m_vrg_source_prio_9$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d853 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_target_threshold_0
assign m_vrg_target_threshold_0$D_IN =
MUX_m_vrg_target_threshold_0$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd7 ;
assign m_vrg_target_threshold_0$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2860 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vrg_target_threshold_1
assign m_vrg_target_threshold_1$D_IN =
MUX_m_vrg_target_threshold_1$write_1__SEL_1 ?
wdata32__h27246[2:0] :
3'd7 ;
assign m_vrg_target_threshold_1$EN =
WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2862 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_0
assign m_vvrg_ie_0_0$D_IN =
MUX_m_vvrg_ie_0_0$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_0$write_1__VAL_1 ;
assign m_vvrg_ie_0_0$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2107 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_1
assign m_vvrg_ie_0_1$D_IN =
MUX_m_vvrg_ie_0_1$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_1$write_1__VAL_1 ;
assign m_vvrg_ie_0_1$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2105 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_10
assign m_vvrg_ie_0_10$D_IN =
MUX_m_vvrg_ie_0_10$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_10$write_1__VAL_1 ;
assign m_vvrg_ie_0_10$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2087 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_11
assign m_vvrg_ie_0_11$D_IN =
MUX_m_vvrg_ie_0_11$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_11$write_1__VAL_1 ;
assign m_vvrg_ie_0_11$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2085 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_12
assign m_vvrg_ie_0_12$D_IN =
MUX_m_vvrg_ie_0_12$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_12$write_1__VAL_1 ;
assign m_vvrg_ie_0_12$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2083 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_13
assign m_vvrg_ie_0_13$D_IN =
MUX_m_vvrg_ie_0_13$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_13$write_1__VAL_1 ;
assign m_vvrg_ie_0_13$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2081 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_14
assign m_vvrg_ie_0_14$D_IN =
MUX_m_vvrg_ie_0_14$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_14$write_1__VAL_1 ;
assign m_vvrg_ie_0_14$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2079 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_15
assign m_vvrg_ie_0_15$D_IN =
MUX_m_vvrg_ie_0_15$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_15$write_1__VAL_1 ;
assign m_vvrg_ie_0_15$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2077 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_16
assign m_vvrg_ie_0_16$D_IN =
MUX_m_vvrg_ie_0_16$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_16$write_1__VAL_1 ;
assign m_vvrg_ie_0_16$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2075 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_2
assign m_vvrg_ie_0_2$D_IN =
MUX_m_vvrg_ie_0_2$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_2$write_1__VAL_1 ;
assign m_vvrg_ie_0_2$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2103 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_3
assign m_vvrg_ie_0_3$D_IN =
MUX_m_vvrg_ie_0_3$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_3$write_1__VAL_1 ;
assign m_vvrg_ie_0_3$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2101 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_4
assign m_vvrg_ie_0_4$D_IN =
MUX_m_vvrg_ie_0_4$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_4$write_1__VAL_1 ;
assign m_vvrg_ie_0_4$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2099 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_5
assign m_vvrg_ie_0_5$D_IN =
MUX_m_vvrg_ie_0_5$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_5$write_1__VAL_1 ;
assign m_vvrg_ie_0_5$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2097 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_6
assign m_vvrg_ie_0_6$D_IN =
MUX_m_vvrg_ie_0_6$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_6$write_1__VAL_1 ;
assign m_vvrg_ie_0_6$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2095 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_7
assign m_vvrg_ie_0_7$D_IN =
MUX_m_vvrg_ie_0_7$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_7$write_1__VAL_1 ;
assign m_vvrg_ie_0_7$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2093 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_8
assign m_vvrg_ie_0_8$D_IN =
MUX_m_vvrg_ie_0_8$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_8$write_1__VAL_1 ;
assign m_vvrg_ie_0_8$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2091 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_0_9
assign m_vvrg_ie_0_9$D_IN =
MUX_m_vvrg_ie_0_9$write_1__SEL_1 &&
MUX_m_vvrg_ie_0_9$write_1__VAL_1 ;
assign m_vvrg_ie_0_9$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2089 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_0
assign m_vvrg_ie_1_0$D_IN =
MUX_m_vvrg_ie_1_0$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_0$write_1__VAL_1 ;
assign m_vvrg_ie_1_0$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2073 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_1
assign m_vvrg_ie_1_1$D_IN =
MUX_m_vvrg_ie_1_1$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_1$write_1__VAL_1 ;
assign m_vvrg_ie_1_1$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2071 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_10
assign m_vvrg_ie_1_10$D_IN =
MUX_m_vvrg_ie_1_10$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_10$write_1__VAL_1 ;
assign m_vvrg_ie_1_10$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2053 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_11
assign m_vvrg_ie_1_11$D_IN =
MUX_m_vvrg_ie_1_11$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_11$write_1__VAL_1 ;
assign m_vvrg_ie_1_11$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2051 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_12
assign m_vvrg_ie_1_12$D_IN =
MUX_m_vvrg_ie_1_12$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_12$write_1__VAL_1 ;
assign m_vvrg_ie_1_12$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2049 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_13
assign m_vvrg_ie_1_13$D_IN =
MUX_m_vvrg_ie_1_13$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_13$write_1__VAL_1 ;
assign m_vvrg_ie_1_13$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2047 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_14
assign m_vvrg_ie_1_14$D_IN =
MUX_m_vvrg_ie_1_14$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_14$write_1__VAL_1 ;
assign m_vvrg_ie_1_14$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2045 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_15
assign m_vvrg_ie_1_15$D_IN =
MUX_m_vvrg_ie_1_15$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_15$write_1__VAL_1 ;
assign m_vvrg_ie_1_15$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2043 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_16
assign m_vvrg_ie_1_16$D_IN =
MUX_m_vvrg_ie_1_16$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_16$write_1__VAL_1 ;
assign m_vvrg_ie_1_16$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2041 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_2
assign m_vvrg_ie_1_2$D_IN =
MUX_m_vvrg_ie_1_2$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_2$write_1__VAL_1 ;
assign m_vvrg_ie_1_2$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2069 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_3
assign m_vvrg_ie_1_3$D_IN =
MUX_m_vvrg_ie_1_3$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_3$write_1__VAL_1 ;
assign m_vvrg_ie_1_3$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2067 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_4
assign m_vvrg_ie_1_4$D_IN =
MUX_m_vvrg_ie_1_4$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_4$write_1__VAL_1 ;
assign m_vvrg_ie_1_4$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2065 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_5
assign m_vvrg_ie_1_5$D_IN =
MUX_m_vvrg_ie_1_5$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_5$write_1__VAL_1 ;
assign m_vvrg_ie_1_5$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2063 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_6
assign m_vvrg_ie_1_6$D_IN =
MUX_m_vvrg_ie_1_6$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_6$write_1__VAL_1 ;
assign m_vvrg_ie_1_6$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2061 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_7
assign m_vvrg_ie_1_7$D_IN =
MUX_m_vvrg_ie_1_7$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_7$write_1__VAL_1 ;
assign m_vvrg_ie_1_7$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2059 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_8
assign m_vvrg_ie_1_8$D_IN =
MUX_m_vvrg_ie_1_8$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_8$write_1__VAL_1 ;
assign m_vvrg_ie_1_8$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2057 ||
WILL_FIRE_RL_m_rl_reset ;
// register m_vvrg_ie_1_9
assign m_vvrg_ie_1_9$D_IN =
MUX_m_vvrg_ie_1_9$write_1__SEL_1 &&
MUX_m_vvrg_ie_1_9$write_1__VAL_1 ;
assign m_vvrg_ie_1_9$EN =
WILL_FIRE_RL_m_rl_process_wr_req && _dfoo2055 ||
WILL_FIRE_RL_m_rl_reset ;
// submodule m_f_reset_reqs
assign m_f_reset_reqs$ENQ = EN_server_reset_request_put ;
assign m_f_reset_reqs$DEQ = CAN_FIRE_RL_m_rl_reset ;
assign m_f_reset_reqs$CLR = 1'b0 ;
// submodule m_f_reset_rsps
assign m_f_reset_rsps$ENQ = CAN_FIRE_RL_m_rl_reset ;
assign m_f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign m_f_reset_rsps$CLR = 1'b0 ;
// submodule m_slave_xactor_f_rd_addr
assign m_slave_xactor_f_rd_addr$D_IN =
{ axi4_slave_arid,
axi4_slave_araddr,
axi4_slave_arlen,
axi4_slave_arsize,
axi4_slave_arburst,
axi4_slave_arlock,
axi4_slave_arcache,
axi4_slave_arprot,
axi4_slave_arqos,
axi4_slave_arregion } ;
assign m_slave_xactor_f_rd_addr$ENQ =
axi4_slave_arvalid && m_slave_xactor_f_rd_addr$FULL_N ;
assign m_slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_m_rl_process_rd_req ;
assign m_slave_xactor_f_rd_addr$CLR = CAN_FIRE_RL_m_rl_reset ;
// submodule m_slave_xactor_f_rd_data
assign m_slave_xactor_f_rd_data$D_IN =
{ m_slave_xactor_f_rd_addr$D_OUT[108:93],
x__h26677,
rresp__h26521,
1'd1 } ;
assign m_slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_m_rl_process_rd_req ;
assign m_slave_xactor_f_rd_data$DEQ =
axi4_slave_rready && m_slave_xactor_f_rd_data$EMPTY_N ;
assign m_slave_xactor_f_rd_data$CLR = CAN_FIRE_RL_m_rl_reset ;
// submodule m_slave_xactor_f_wr_addr
assign m_slave_xactor_f_wr_addr$D_IN =
{ axi4_slave_awid,
axi4_slave_awaddr,
axi4_slave_awlen,
axi4_slave_awsize,
axi4_slave_awburst,
axi4_slave_awlock,
axi4_slave_awcache,
axi4_slave_awprot,
axi4_slave_awqos,
axi4_slave_awregion } ;
assign m_slave_xactor_f_wr_addr$ENQ =
axi4_slave_awvalid && m_slave_xactor_f_wr_addr$FULL_N ;
assign m_slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_m_rl_process_wr_req ;
assign m_slave_xactor_f_wr_addr$CLR = CAN_FIRE_RL_m_rl_reset ;
// submodule m_slave_xactor_f_wr_data
assign m_slave_xactor_f_wr_data$D_IN =
{ axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ;
assign m_slave_xactor_f_wr_data$ENQ =
axi4_slave_wvalid && m_slave_xactor_f_wr_data$FULL_N ;
assign m_slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_m_rl_process_wr_req ;
assign m_slave_xactor_f_wr_data$CLR = CAN_FIRE_RL_m_rl_reset ;
// submodule m_slave_xactor_f_wr_resp
assign m_slave_xactor_f_wr_resp$D_IN =
{ m_slave_xactor_f_wr_addr$D_OUT[108:93], v__h27250 } ;
assign m_slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_m_rl_process_wr_req ;
assign m_slave_xactor_f_wr_resp$DEQ =
axi4_slave_bready && m_slave_xactor_f_wr_resp$EMPTY_N ;
assign m_slave_xactor_f_wr_resp$CLR = CAN_FIRE_RL_m_rl_reset ;
// remaining internal signals
assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d748 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 ?
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ||
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 :
x__h23928 != 32'h00200000 && x__h23928 != 32'h00200004 ||
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ;
assign IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ?
addr_offset__h13465[11:2] == 10'd0 ||
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 :
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 ?
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 :
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d748) ;
assign IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2874 =
wdata32__h27246[9:0] <= 10'd17 ;
assign IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2950 =
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 ?
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 ||
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 :
x__h76716 != 32'h00200000 && x__h76716 != 32'h00200004 ||
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 ;
assign IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952 =
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 ?
addr_offset__h27245[11:2] == 10'd0 ||
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 :
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 ?
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 :
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2950) ;
assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3037 =
m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3036 ?
m_vrg_source_prio_10 :
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3032 ;
assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3131 =
m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3130 ?
m_vrg_source_prio_10 :
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3126 ;
assign IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 =
m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ?
m_vrg_source_prio_10 :
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 ;
assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3042 =
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3041 ?
m_vrg_source_prio_11 :
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3037 ;
assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3078 =
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3041 ?
5'd11 :
(m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3036 ?
5'd10 :
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3076) ;
assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3136 =
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3135 ?
m_vrg_source_prio_11 :
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3131 ;
assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3172 =
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3135 ?
5'd11 :
(m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3130 ?
5'd10 :
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3170) ;
assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 =
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ?
m_vrg_source_prio_11 :
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 ;
assign IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667 =
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ?
5'd11 :
(m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ?
5'd10 :
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665) ;
assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3047 =
m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3046 ?
m_vrg_source_prio_12 :
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3042 ;
assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3141 =
m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3140 ?
m_vrg_source_prio_12 :
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3136 ;
assign IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 =
m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ?
m_vrg_source_prio_12 :
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 ;
assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3052 =
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3051 ?
m_vrg_source_prio_13 :
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3047 ;
assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3080 =
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3051 ?
5'd13 :
(m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3046 ?
5'd12 :
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3078) ;
assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3146 =
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3145 ?
m_vrg_source_prio_13 :
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3141 ;
assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3174 =
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3145 ?
5'd13 :
(m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3140 ?
5'd12 :
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3172) ;
assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 =
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ?
m_vrg_source_prio_13 :
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 ;
assign IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669 =
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ?
5'd13 :
(m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ?
5'd12 :
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d667) ;
assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3057 =
m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3056 ?
m_vrg_source_prio_14 :
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3052 ;
assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3151 =
m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3150 ?
m_vrg_source_prio_14 :
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3146 ;
assign IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 =
m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ?
m_vrg_source_prio_14 :
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 ;
assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3062 =
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3061 ?
m_vrg_source_prio_15 :
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3057 ;
assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3082 =
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3061 ?
5'd15 :
(m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3056 ?
5'd14 :
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3080) ;
assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3156 =
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3155 ?
m_vrg_source_prio_15 :
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3151 ;
assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3176 =
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3155 ?
5'd15 :
(m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3150 ?
5'd14 :
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3174) ;
assign IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 =
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ?
5'd15 :
(m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ?
5'd14 :
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d669) ;
assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d2992 =
(m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 &&
m_vvrg_ie_0_1) ?
m_vrg_source_prio_1 :
3'd0 ;
assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3086 =
(m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 &&
m_vvrg_ie_1_1) ?
m_vrg_source_prio_1 :
3'd0 ;
assign IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 =
m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ?
m_vrg_source_prio_1 :
3'd0 ;
assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d2997 =
m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d2996 ?
m_vrg_source_prio_2 :
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d2992 ;
assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3091 =
m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3090 ?
m_vrg_source_prio_2 :
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3086 ;
assign IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 =
m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ?
m_vrg_source_prio_2 :
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 ;
assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3002 =
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3001 ?
m_vrg_source_prio_3 :
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d2997 ;
assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3070 =
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3001 ?
5'd3 :
(m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d2996 ?
5'd2 :
((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 &&
m_vvrg_ie_0_1) ?
5'd1 :
5'd0)) ;
assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3096 =
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3095 ?
m_vrg_source_prio_3 :
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3091 ;
assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3164 =
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3095 ?
5'd3 :
(m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3090 ?
5'd2 :
((m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 &&
m_vvrg_ie_1_1) ?
5'd1 :
5'd0)) ;
assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 =
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ?
m_vrg_source_prio_3 :
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 ;
assign IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659 =
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ?
5'd3 :
(m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ?
5'd2 :
(m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ?
5'd1 :
5'd0)) ;
assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3007 =
m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3006 ?
m_vrg_source_prio_4 :
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3002 ;
assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3101 =
m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3100 ?
m_vrg_source_prio_4 :
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3096 ;
assign IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 =
m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ?
m_vrg_source_prio_4 :
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 ;
assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3012 =
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3011 ?
m_vrg_source_prio_5 :
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3007 ;
assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3072 =
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3011 ?
5'd5 :
(m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3006 ?
5'd4 :
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3070) ;
assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3106 =
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3105 ?
m_vrg_source_prio_5 :
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3101 ;
assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3166 =
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3105 ?
5'd5 :
(m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3100 ?
5'd4 :
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3164) ;
assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 =
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ?
m_vrg_source_prio_5 :
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 ;
assign IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661 =
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ?
5'd5 :
(m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ?
5'd4 :
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d659) ;
assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3017 =
m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3016 ?
m_vrg_source_prio_6 :
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3012 ;
assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3111 =
m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3110 ?
m_vrg_source_prio_6 :
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3106 ;
assign IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 =
m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ?
m_vrg_source_prio_6 :
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 ;
assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3022 =
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3021 ?
m_vrg_source_prio_7 :
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3017 ;
assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3074 =
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3021 ?
5'd7 :
(m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3016 ?
5'd6 :
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3072) ;
assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3116 =
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3115 ?
m_vrg_source_prio_7 :
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3111 ;
assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3168 =
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3115 ?
5'd7 :
(m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3110 ?
5'd6 :
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3166) ;
assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 =
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ?
m_vrg_source_prio_7 :
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 ;
assign IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663 =
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ?
5'd7 :
(m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ?
5'd6 :
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d661) ;
assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3027 =
m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3026 ?
m_vrg_source_prio_8 :
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3022 ;
assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3121 =
m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3120 ?
m_vrg_source_prio_8 :
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3116 ;
assign IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 =
m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ?
m_vrg_source_prio_8 :
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 ;
assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3032 =
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3031 ?
m_vrg_source_prio_9 :
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3027 ;
assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3076 =
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3031 ?
5'd9 :
(m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3026 ?
5'd8 :
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3074) ;
assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3126 =
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3125 ?
m_vrg_source_prio_9 :
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3121 ;
assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3170 =
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3125 ?
5'd9 :
(m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3120 ?
5'd8 :
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3168) ;
assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 =
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ?
m_vrg_source_prio_9 :
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 ;
assign IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d665 =
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ?
5'd9 :
(m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ?
5'd8 :
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d663) ;
assign NOT_m_cfg_verbosity_read_ULE_1_5___d16 = m_cfg_verbosity > 4'd1 ;
assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248 =
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538 =
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 &&
x__h23928 == 32'h00200000 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d695 =
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 &&
x__h23928 == 32'h00200004 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 &&
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d689 ;
assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d733 =
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 &&
x__h23928 == 32'h00200004 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74 =
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h31729 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h33225 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h34721 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h36217 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h37713 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h39209 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h40705 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h42201 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h43697 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h45193 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h46689 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h48185 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h49681 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h51177 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h52673 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h54169 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h55665 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h57161 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h58657 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h60153 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h61649 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h63145 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h64641 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h66137 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h67633 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h69129 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h70625 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h72121 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h73617 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h75113 <= 10'd16 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2844 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2857 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
x__h76716 == 32'h00200000 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2868 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
x__h76716 == 32'h00200000 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2884 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
x__h76716 == 32'h00200004 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 &&
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2874 &&
SEL_ARR_SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_ETC___d2878 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2923 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
x__h76716 == 32'h00200004 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 &&
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2874 &&
SEL_ARR_SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_ETC___d2878 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2935 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
x__h76716 == 32'h00200004 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 &&
(!IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2874 ||
!SEL_ARR_SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_ETC___d2878) &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d826 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
addr_offset__h27245[11:2] != 10'd0 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d880 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_cfg_verbosity != 4'd0 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d892 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 ;
assign NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 =
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 &&
source_id__h30233 <= 10'd16 ;
assign NOT_m_vrg_source_busy_10_983_284_AND_NOT_m_cfg_ETC___d3288 =
!m_vrg_source_busy_10 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_10 != v_sources_9_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_11_984_292_AND_NOT_m_cfg_ETC___d3296 =
!m_vrg_source_busy_11 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_11 !=
v_sources_10_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_12_985_300_AND_NOT_m_cfg_ETC___d3304 =
!m_vrg_source_busy_12 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_12 !=
v_sources_11_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_13_986_308_AND_NOT_m_cfg_ETC___d3312 =
!m_vrg_source_busy_13 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_13 !=
v_sources_12_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_14_987_316_AND_NOT_m_cfg_ETC___d3320 =
!m_vrg_source_busy_14 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_14 !=
v_sources_13_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_15_988_324_AND_NOT_m_cfg_ETC___d3328 =
!m_vrg_source_busy_15 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_15 !=
v_sources_14_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_16_989_332_AND_NOT_m_cfg_ETC___d3336 =
!m_vrg_source_busy_16 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_16 !=
v_sources_15_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_1_974_213_AND_NOT_m_cfg__ETC___d3217 =
!m_vrg_source_busy_1 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_1 != v_sources_0_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_2_975_220_AND_NOT_m_cfg__ETC___d3224 =
!m_vrg_source_busy_2 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_2 != v_sources_1_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_3_976_228_AND_NOT_m_cfg__ETC___d3232 =
!m_vrg_source_busy_3 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_3 != v_sources_2_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_4_977_236_AND_NOT_m_cfg__ETC___d3240 =
!m_vrg_source_busy_4 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_4 != v_sources_3_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_5_978_244_AND_NOT_m_cfg__ETC___d3248 =
!m_vrg_source_busy_5 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_5 != v_sources_4_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_6_979_252_AND_NOT_m_cfg__ETC___d3256 =
!m_vrg_source_busy_6 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_6 != v_sources_5_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_7_980_260_AND_NOT_m_cfg__ETC___d3264 =
!m_vrg_source_busy_7 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_7 != v_sources_6_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_8_981_268_AND_NOT_m_cfg__ETC___d3272 =
!m_vrg_source_busy_8 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_8 != v_sources_7_m_interrupt_req_set_not_clear ;
assign NOT_m_vrg_source_busy_9_982_276_AND_NOT_m_cfg__ETC___d3280 =
!m_vrg_source_busy_9 && m_cfg_verbosity != 4'd0 &&
m_vrg_source_ip_9 != v_sources_8_m_interrupt_req_set_not_clear ;
assign _dfoo1 =
source_id__h73617 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo10 =
(source_id__h73617 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo100 =
(source_id__h72121 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo32 ;
assign _dfoo1000 =
(source_id__h52673 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo932 ;
assign _dfoo1001 =
source_id__h52673 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo865 ;
assign _dfoo1002 =
(source_id__h52673 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo934 ;
assign _dfoo1003 =
source_id__h52673 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo867 ;
assign _dfoo1004 =
(source_id__h52673 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo936 ;
assign _dfoo1005 =
source_id__h52673 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo869 ;
assign _dfoo1006 =
(source_id__h52673 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo938 ;
assign _dfoo1007 =
source_id__h52673 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo871 ;
assign _dfoo1008 =
(source_id__h52673 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo940 ;
assign _dfoo1009 =
source_id__h52673 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo873 ;
assign _dfoo1010 =
(source_id__h52673 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo942 ;
assign _dfoo1011 =
source_id__h52673 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo875 ;
assign _dfoo1012 =
(source_id__h52673 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo944 ;
assign _dfoo1013 =
source_id__h52673 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo877 ;
assign _dfoo1014 =
(source_id__h52673 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo946 ;
assign _dfoo1015 =
source_id__h52673 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo879 ;
assign _dfoo1016 =
(source_id__h52673 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo948 ;
assign _dfoo1017 =
source_id__h52673 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo881 ;
assign _dfoo1018 =
(source_id__h52673 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo950 ;
assign _dfoo1019 =
source_id__h52673 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo883 ;
assign _dfoo102 =
(source_id__h72121 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo34 ;
assign _dfoo1020 =
(source_id__h52673 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo952 ;
assign _dfoo1022 =
(source_id__h51177 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo954 ;
assign _dfoo1024 =
(source_id__h51177 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo956 ;
assign _dfoo1026 =
(source_id__h51177 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo958 ;
assign _dfoo1028 =
(source_id__h51177 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo960 ;
assign _dfoo1030 =
(source_id__h51177 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo962 ;
assign _dfoo1032 =
(source_id__h51177 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo964 ;
assign _dfoo1034 =
(source_id__h51177 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo966 ;
assign _dfoo1036 =
(source_id__h51177 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo968 ;
assign _dfoo1038 =
(source_id__h51177 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo970 ;
assign _dfoo104 =
(source_id__h72121 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo36 ;
assign _dfoo1040 =
(source_id__h51177 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo972 ;
assign _dfoo1042 =
(source_id__h51177 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo974 ;
assign _dfoo1044 =
(source_id__h51177 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo976 ;
assign _dfoo1046 =
(source_id__h51177 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo978 ;
assign _dfoo1048 =
(source_id__h51177 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo980 ;
assign _dfoo1050 =
(source_id__h51177 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo982 ;
assign _dfoo1052 =
(source_id__h51177 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo984 ;
assign _dfoo1054 =
(source_id__h51177 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo986 ;
assign _dfoo1056 =
(source_id__h51177 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo988 ;
assign _dfoo1058 =
(source_id__h51177 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo990 ;
assign _dfoo106 =
(source_id__h72121 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo38 ;
assign _dfoo1060 =
(source_id__h51177 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo992 ;
assign _dfoo1062 =
(source_id__h51177 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo994 ;
assign _dfoo1064 =
(source_id__h51177 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo996 ;
assign _dfoo1066 =
(source_id__h51177 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo998 ;
assign _dfoo1068 =
(source_id__h51177 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1000 ;
assign _dfoo1070 =
(source_id__h51177 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1002 ;
assign _dfoo1072 =
(source_id__h51177 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1004 ;
assign _dfoo1074 =
(source_id__h51177 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1006 ;
assign _dfoo1076 =
(source_id__h51177 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1008 ;
assign _dfoo1078 =
(source_id__h51177 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1010 ;
assign _dfoo108 =
(source_id__h72121 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo40 ;
assign _dfoo1080 =
(source_id__h51177 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1012 ;
assign _dfoo1082 =
(source_id__h51177 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1014 ;
assign _dfoo1084 =
(source_id__h51177 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1016 ;
assign _dfoo1086 =
(source_id__h51177 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1018 ;
assign _dfoo1088 =
(source_id__h51177 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810) ?
wdata32__h27246[15] :
_dfoo1020 ;
assign _dfoo1089 =
source_id__h49681 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo953 ;
assign _dfoo1090 =
(source_id__h49681 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1022 ;
assign _dfoo1091 =
source_id__h49681 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo955 ;
assign _dfoo1092 =
(source_id__h49681 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1024 ;
assign _dfoo1093 =
source_id__h49681 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo957 ;
assign _dfoo1094 =
(source_id__h49681 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1026 ;
assign _dfoo1095 =
source_id__h49681 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo959 ;
assign _dfoo1096 =
(source_id__h49681 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1028 ;
assign _dfoo1097 =
source_id__h49681 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo961 ;
assign _dfoo1098 =
(source_id__h49681 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1030 ;
assign _dfoo1099 =
source_id__h49681 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo963 ;
assign _dfoo11 =
source_id__h73617 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo110 =
(source_id__h72121 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo42 ;
assign _dfoo1100 =
(source_id__h49681 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1032 ;
assign _dfoo1101 =
source_id__h49681 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo965 ;
assign _dfoo1102 =
(source_id__h49681 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1034 ;
assign _dfoo1103 =
source_id__h49681 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo967 ;
assign _dfoo1104 =
(source_id__h49681 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1036 ;
assign _dfoo1105 =
source_id__h49681 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo969 ;
assign _dfoo1106 =
(source_id__h49681 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1038 ;
assign _dfoo1107 =
source_id__h49681 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo971 ;
assign _dfoo1108 =
(source_id__h49681 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1040 ;
assign _dfoo1109 =
source_id__h49681 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo973 ;
assign _dfoo1110 =
(source_id__h49681 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1042 ;
assign _dfoo1111 =
source_id__h49681 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo975 ;
assign _dfoo1112 =
(source_id__h49681 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1044 ;
assign _dfoo1113 =
source_id__h49681 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo977 ;
assign _dfoo1114 =
(source_id__h49681 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1046 ;
assign _dfoo1115 =
source_id__h49681 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo979 ;
assign _dfoo1116 =
(source_id__h49681 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1048 ;
assign _dfoo1117 =
source_id__h49681 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo981 ;
assign _dfoo1118 =
(source_id__h49681 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1050 ;
assign _dfoo1119 =
source_id__h49681 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo983 ;
assign _dfoo112 =
(source_id__h72121 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo44 ;
assign _dfoo1120 =
(source_id__h49681 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1052 ;
assign _dfoo1121 =
source_id__h49681 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo985 ;
assign _dfoo1122 =
(source_id__h49681 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1054 ;
assign _dfoo1123 =
source_id__h49681 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo987 ;
assign _dfoo1124 =
(source_id__h49681 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1056 ;
assign _dfoo1125 =
source_id__h49681 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo989 ;
assign _dfoo1126 =
(source_id__h49681 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1058 ;
assign _dfoo1127 =
source_id__h49681 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo991 ;
assign _dfoo1128 =
(source_id__h49681 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1060 ;
assign _dfoo1129 =
source_id__h49681 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo993 ;
assign _dfoo1130 =
(source_id__h49681 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1062 ;
assign _dfoo1131 =
source_id__h49681 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo995 ;
assign _dfoo1132 =
(source_id__h49681 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1064 ;
assign _dfoo1133 =
source_id__h49681 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo997 ;
assign _dfoo1134 =
(source_id__h49681 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1066 ;
assign _dfoo1135 =
source_id__h49681 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo999 ;
assign _dfoo1136 =
(source_id__h49681 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1068 ;
assign _dfoo1137 =
source_id__h49681 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1001 ;
assign _dfoo1138 =
(source_id__h49681 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1070 ;
assign _dfoo1139 =
source_id__h49681 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1003 ;
assign _dfoo114 =
(source_id__h72121 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo46 ;
assign _dfoo1140 =
(source_id__h49681 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1072 ;
assign _dfoo1141 =
source_id__h49681 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1005 ;
assign _dfoo1142 =
(source_id__h49681 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1074 ;
assign _dfoo1143 =
source_id__h49681 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1007 ;
assign _dfoo1144 =
(source_id__h49681 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1076 ;
assign _dfoo1145 =
source_id__h49681 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1009 ;
assign _dfoo1146 =
(source_id__h49681 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1078 ;
assign _dfoo1147 =
source_id__h49681 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1011 ;
assign _dfoo1148 =
(source_id__h49681 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1080 ;
assign _dfoo1149 =
source_id__h49681 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1013 ;
assign _dfoo1150 =
(source_id__h49681 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1082 ;
assign _dfoo1151 =
source_id__h49681 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1015 ;
assign _dfoo1152 =
(source_id__h49681 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1084 ;
assign _dfoo1153 =
source_id__h49681 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1017 ;
assign _dfoo1154 =
(source_id__h49681 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1086 ;
assign _dfoo1155 =
source_id__h49681 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749 ||
source_id__h51177 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1810 ||
_dfoo1019 ;
assign _dfoo1156 =
(source_id__h49681 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1749) ?
wdata32__h27246[14] :
_dfoo1088 ;
assign _dfoo1158 =
(source_id__h48185 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1090 ;
assign _dfoo116 =
(source_id__h72121 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo48 ;
assign _dfoo1160 =
(source_id__h48185 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1092 ;
assign _dfoo1162 =
(source_id__h48185 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1094 ;
assign _dfoo1164 =
(source_id__h48185 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1096 ;
assign _dfoo1166 =
(source_id__h48185 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1098 ;
assign _dfoo1168 =
(source_id__h48185 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1100 ;
assign _dfoo1170 =
(source_id__h48185 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1102 ;
assign _dfoo1172 =
(source_id__h48185 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1104 ;
assign _dfoo1174 =
(source_id__h48185 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1106 ;
assign _dfoo1176 =
(source_id__h48185 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1108 ;
assign _dfoo1178 =
(source_id__h48185 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1110 ;
assign _dfoo118 =
(source_id__h72121 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo50 ;
assign _dfoo1180 =
(source_id__h48185 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1112 ;
assign _dfoo1182 =
(source_id__h48185 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1114 ;
assign _dfoo1184 =
(source_id__h48185 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1116 ;
assign _dfoo1186 =
(source_id__h48185 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1118 ;
assign _dfoo1188 =
(source_id__h48185 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1120 ;
assign _dfoo1190 =
(source_id__h48185 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1122 ;
assign _dfoo1192 =
(source_id__h48185 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1124 ;
assign _dfoo1194 =
(source_id__h48185 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1126 ;
assign _dfoo1196 =
(source_id__h48185 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1128 ;
assign _dfoo1198 =
(source_id__h48185 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1130 ;
assign _dfoo12 =
(source_id__h73617 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo120 =
(source_id__h72121 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo52 ;
assign _dfoo1200 =
(source_id__h48185 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1132 ;
assign _dfoo1202 =
(source_id__h48185 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1134 ;
assign _dfoo1204 =
(source_id__h48185 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1136 ;
assign _dfoo1206 =
(source_id__h48185 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1138 ;
assign _dfoo1208 =
(source_id__h48185 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1140 ;
assign _dfoo1210 =
(source_id__h48185 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1142 ;
assign _dfoo1212 =
(source_id__h48185 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1144 ;
assign _dfoo1214 =
(source_id__h48185 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1146 ;
assign _dfoo1216 =
(source_id__h48185 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1148 ;
assign _dfoo1218 =
(source_id__h48185 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1150 ;
assign _dfoo122 =
(source_id__h72121 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo54 ;
assign _dfoo1220 =
(source_id__h48185 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1152 ;
assign _dfoo1222 =
(source_id__h48185 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1154 ;
assign _dfoo1224 =
(source_id__h48185 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688) ?
wdata32__h27246[13] :
_dfoo1156 ;
assign _dfoo1225 =
source_id__h46689 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1089 ;
assign _dfoo1226 =
(source_id__h46689 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1158 ;
assign _dfoo1227 =
source_id__h46689 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1091 ;
assign _dfoo1228 =
(source_id__h46689 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1160 ;
assign _dfoo1229 =
source_id__h46689 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1093 ;
assign _dfoo1230 =
(source_id__h46689 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1162 ;
assign _dfoo1231 =
source_id__h46689 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1095 ;
assign _dfoo1232 =
(source_id__h46689 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1164 ;
assign _dfoo1233 =
source_id__h46689 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1097 ;
assign _dfoo1234 =
(source_id__h46689 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1166 ;
assign _dfoo1235 =
source_id__h46689 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1099 ;
assign _dfoo1236 =
(source_id__h46689 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1168 ;
assign _dfoo1237 =
source_id__h46689 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1101 ;
assign _dfoo1238 =
(source_id__h46689 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1170 ;
assign _dfoo1239 =
source_id__h46689 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1103 ;
assign _dfoo124 =
(source_id__h72121 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo56 ;
assign _dfoo1240 =
(source_id__h46689 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1172 ;
assign _dfoo1241 =
source_id__h46689 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1105 ;
assign _dfoo1242 =
(source_id__h46689 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1174 ;
assign _dfoo1243 =
source_id__h46689 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1107 ;
assign _dfoo1244 =
(source_id__h46689 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1176 ;
assign _dfoo1245 =
source_id__h46689 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1109 ;
assign _dfoo1246 =
(source_id__h46689 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1178 ;
assign _dfoo1247 =
source_id__h46689 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1111 ;
assign _dfoo1248 =
(source_id__h46689 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1180 ;
assign _dfoo1249 =
source_id__h46689 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1113 ;
assign _dfoo1250 =
(source_id__h46689 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1182 ;
assign _dfoo1251 =
source_id__h46689 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1115 ;
assign _dfoo1252 =
(source_id__h46689 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1184 ;
assign _dfoo1253 =
source_id__h46689 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1117 ;
assign _dfoo1254 =
(source_id__h46689 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1186 ;
assign _dfoo1255 =
source_id__h46689 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1119 ;
assign _dfoo1256 =
(source_id__h46689 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1188 ;
assign _dfoo1257 =
source_id__h46689 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1121 ;
assign _dfoo1258 =
(source_id__h46689 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1190 ;
assign _dfoo1259 =
source_id__h46689 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1123 ;
assign _dfoo126 =
(source_id__h72121 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo58 ;
assign _dfoo1260 =
(source_id__h46689 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1192 ;
assign _dfoo1261 =
source_id__h46689 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1125 ;
assign _dfoo1262 =
(source_id__h46689 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1194 ;
assign _dfoo1263 =
source_id__h46689 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1127 ;
assign _dfoo1264 =
(source_id__h46689 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1196 ;
assign _dfoo1265 =
source_id__h46689 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1129 ;
assign _dfoo1266 =
(source_id__h46689 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1198 ;
assign _dfoo1267 =
source_id__h46689 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1131 ;
assign _dfoo1268 =
(source_id__h46689 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1200 ;
assign _dfoo1269 =
source_id__h46689 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1133 ;
assign _dfoo1270 =
(source_id__h46689 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1202 ;
assign _dfoo1271 =
source_id__h46689 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1135 ;
assign _dfoo1272 =
(source_id__h46689 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1204 ;
assign _dfoo1273 =
source_id__h46689 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1137 ;
assign _dfoo1274 =
(source_id__h46689 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1206 ;
assign _dfoo1275 =
source_id__h46689 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1139 ;
assign _dfoo1276 =
(source_id__h46689 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1208 ;
assign _dfoo1277 =
source_id__h46689 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1141 ;
assign _dfoo1278 =
(source_id__h46689 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1210 ;
assign _dfoo1279 =
source_id__h46689 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1143 ;
assign _dfoo128 =
(source_id__h72121 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo60 ;
assign _dfoo1280 =
(source_id__h46689 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1212 ;
assign _dfoo1281 =
source_id__h46689 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1145 ;
assign _dfoo1282 =
(source_id__h46689 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1214 ;
assign _dfoo1283 =
source_id__h46689 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1147 ;
assign _dfoo1284 =
(source_id__h46689 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1216 ;
assign _dfoo1285 =
source_id__h46689 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1149 ;
assign _dfoo1286 =
(source_id__h46689 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1218 ;
assign _dfoo1287 =
source_id__h46689 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1151 ;
assign _dfoo1288 =
(source_id__h46689 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1220 ;
assign _dfoo1289 =
source_id__h46689 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1153 ;
assign _dfoo1290 =
(source_id__h46689 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1222 ;
assign _dfoo1291 =
source_id__h46689 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627 ||
source_id__h48185 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1688 ||
_dfoo1155 ;
assign _dfoo1292 =
(source_id__h46689 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1627) ?
wdata32__h27246[12] :
_dfoo1224 ;
assign _dfoo1294 =
(source_id__h45193 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1226 ;
assign _dfoo1296 =
(source_id__h45193 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1228 ;
assign _dfoo1298 =
(source_id__h45193 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1230 ;
assign _dfoo13 =
source_id__h73617 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo130 =
(source_id__h72121 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo62 ;
assign _dfoo1300 =
(source_id__h45193 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1232 ;
assign _dfoo1302 =
(source_id__h45193 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1234 ;
assign _dfoo1304 =
(source_id__h45193 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1236 ;
assign _dfoo1306 =
(source_id__h45193 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1238 ;
assign _dfoo1308 =
(source_id__h45193 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1240 ;
assign _dfoo1310 =
(source_id__h45193 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1242 ;
assign _dfoo1312 =
(source_id__h45193 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1244 ;
assign _dfoo1314 =
(source_id__h45193 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1246 ;
assign _dfoo1316 =
(source_id__h45193 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1248 ;
assign _dfoo1318 =
(source_id__h45193 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1250 ;
assign _dfoo132 =
(source_id__h72121 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo64 ;
assign _dfoo1320 =
(source_id__h45193 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1252 ;
assign _dfoo1322 =
(source_id__h45193 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1254 ;
assign _dfoo1324 =
(source_id__h45193 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1256 ;
assign _dfoo1326 =
(source_id__h45193 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1258 ;
assign _dfoo1328 =
(source_id__h45193 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1260 ;
assign _dfoo1330 =
(source_id__h45193 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1262 ;
assign _dfoo1332 =
(source_id__h45193 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1264 ;
assign _dfoo1334 =
(source_id__h45193 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1266 ;
assign _dfoo1336 =
(source_id__h45193 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1268 ;
assign _dfoo1338 =
(source_id__h45193 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1270 ;
assign _dfoo134 =
(source_id__h72121 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo66 ;
assign _dfoo1340 =
(source_id__h45193 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1272 ;
assign _dfoo1342 =
(source_id__h45193 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1274 ;
assign _dfoo1344 =
(source_id__h45193 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1276 ;
assign _dfoo1346 =
(source_id__h45193 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1278 ;
assign _dfoo1348 =
(source_id__h45193 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1280 ;
assign _dfoo1350 =
(source_id__h45193 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1282 ;
assign _dfoo1352 =
(source_id__h45193 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1284 ;
assign _dfoo1354 =
(source_id__h45193 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1286 ;
assign _dfoo1356 =
(source_id__h45193 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1288 ;
assign _dfoo1358 =
(source_id__h45193 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1290 ;
assign _dfoo136 =
(source_id__h72121 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo68 ;
assign _dfoo1360 =
(source_id__h45193 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566) ?
wdata32__h27246[11] :
_dfoo1292 ;
assign _dfoo1361 =
source_id__h43697 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1225 ;
assign _dfoo1362 =
(source_id__h43697 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1294 ;
assign _dfoo1363 =
source_id__h43697 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1227 ;
assign _dfoo1364 =
(source_id__h43697 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1296 ;
assign _dfoo1365 =
source_id__h43697 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1229 ;
assign _dfoo1366 =
(source_id__h43697 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1298 ;
assign _dfoo1367 =
source_id__h43697 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1231 ;
assign _dfoo1368 =
(source_id__h43697 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1300 ;
assign _dfoo1369 =
source_id__h43697 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1233 ;
assign _dfoo137 =
source_id__h70625 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo1 ;
assign _dfoo1370 =
(source_id__h43697 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1302 ;
assign _dfoo1371 =
source_id__h43697 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1235 ;
assign _dfoo1372 =
(source_id__h43697 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1304 ;
assign _dfoo1373 =
source_id__h43697 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1237 ;
assign _dfoo1374 =
(source_id__h43697 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1306 ;
assign _dfoo1375 =
source_id__h43697 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1239 ;
assign _dfoo1376 =
(source_id__h43697 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1308 ;
assign _dfoo1377 =
source_id__h43697 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1241 ;
assign _dfoo1378 =
(source_id__h43697 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1310 ;
assign _dfoo1379 =
source_id__h43697 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1243 ;
assign _dfoo138 =
(source_id__h70625 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo70 ;
assign _dfoo1380 =
(source_id__h43697 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1312 ;
assign _dfoo1381 =
source_id__h43697 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1245 ;
assign _dfoo1382 =
(source_id__h43697 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1314 ;
assign _dfoo1383 =
source_id__h43697 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1247 ;
assign _dfoo1384 =
(source_id__h43697 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1316 ;
assign _dfoo1385 =
source_id__h43697 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1249 ;
assign _dfoo1386 =
(source_id__h43697 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1318 ;
assign _dfoo1387 =
source_id__h43697 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1251 ;
assign _dfoo1388 =
(source_id__h43697 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1320 ;
assign _dfoo1389 =
source_id__h43697 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1253 ;
assign _dfoo139 =
source_id__h70625 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo3 ;
assign _dfoo1390 =
(source_id__h43697 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1322 ;
assign _dfoo1391 =
source_id__h43697 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1255 ;
assign _dfoo1392 =
(source_id__h43697 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1324 ;
assign _dfoo1393 =
source_id__h43697 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1257 ;
assign _dfoo1394 =
(source_id__h43697 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1326 ;
assign _dfoo1395 =
source_id__h43697 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1259 ;
assign _dfoo1396 =
(source_id__h43697 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1328 ;
assign _dfoo1397 =
source_id__h43697 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1261 ;
assign _dfoo1398 =
(source_id__h43697 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1330 ;
assign _dfoo1399 =
source_id__h43697 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1263 ;
assign _dfoo14 =
(source_id__h73617 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo140 =
(source_id__h70625 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo72 ;
assign _dfoo1400 =
(source_id__h43697 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1332 ;
assign _dfoo1401 =
source_id__h43697 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1265 ;
assign _dfoo1402 =
(source_id__h43697 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1334 ;
assign _dfoo1403 =
source_id__h43697 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1267 ;
assign _dfoo1404 =
(source_id__h43697 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1336 ;
assign _dfoo1405 =
source_id__h43697 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1269 ;
assign _dfoo1406 =
(source_id__h43697 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1338 ;
assign _dfoo1407 =
source_id__h43697 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1271 ;
assign _dfoo1408 =
(source_id__h43697 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1340 ;
assign _dfoo1409 =
source_id__h43697 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1273 ;
assign _dfoo141 =
source_id__h70625 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo5 ;
assign _dfoo1410 =
(source_id__h43697 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1342 ;
assign _dfoo1411 =
source_id__h43697 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1275 ;
assign _dfoo1412 =
(source_id__h43697 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1344 ;
assign _dfoo1413 =
source_id__h43697 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1277 ;
assign _dfoo1414 =
(source_id__h43697 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1346 ;
assign _dfoo1415 =
source_id__h43697 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1279 ;
assign _dfoo1416 =
(source_id__h43697 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1348 ;
assign _dfoo1417 =
source_id__h43697 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1281 ;
assign _dfoo1418 =
(source_id__h43697 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1350 ;
assign _dfoo1419 =
source_id__h43697 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1283 ;
assign _dfoo142 =
(source_id__h70625 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo74 ;
assign _dfoo1420 =
(source_id__h43697 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1352 ;
assign _dfoo1421 =
source_id__h43697 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1285 ;
assign _dfoo1422 =
(source_id__h43697 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1354 ;
assign _dfoo1423 =
source_id__h43697 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1287 ;
assign _dfoo1424 =
(source_id__h43697 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1356 ;
assign _dfoo1425 =
source_id__h43697 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1289 ;
assign _dfoo1426 =
(source_id__h43697 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1358 ;
assign _dfoo1427 =
source_id__h43697 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505 ||
source_id__h45193 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1566 ||
_dfoo1291 ;
assign _dfoo1428 =
(source_id__h43697 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1505) ?
wdata32__h27246[10] :
_dfoo1360 ;
assign _dfoo143 =
source_id__h70625 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo7 ;
assign _dfoo1430 =
(source_id__h42201 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1362 ;
assign _dfoo1432 =
(source_id__h42201 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1364 ;
assign _dfoo1434 =
(source_id__h42201 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1366 ;
assign _dfoo1436 =
(source_id__h42201 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1368 ;
assign _dfoo1438 =
(source_id__h42201 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1370 ;
assign _dfoo144 =
(source_id__h70625 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo76 ;
assign _dfoo1440 =
(source_id__h42201 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1372 ;
assign _dfoo1442 =
(source_id__h42201 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1374 ;
assign _dfoo1444 =
(source_id__h42201 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1376 ;
assign _dfoo1446 =
(source_id__h42201 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1378 ;
assign _dfoo1448 =
(source_id__h42201 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1380 ;
assign _dfoo145 =
source_id__h70625 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo9 ;
assign _dfoo1450 =
(source_id__h42201 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1382 ;
assign _dfoo1452 =
(source_id__h42201 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1384 ;
assign _dfoo1454 =
(source_id__h42201 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1386 ;
assign _dfoo1456 =
(source_id__h42201 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1388 ;
assign _dfoo1458 =
(source_id__h42201 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1390 ;
assign _dfoo146 =
(source_id__h70625 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo78 ;
assign _dfoo1460 =
(source_id__h42201 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1392 ;
assign _dfoo1462 =
(source_id__h42201 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1394 ;
assign _dfoo1464 =
(source_id__h42201 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1396 ;
assign _dfoo1466 =
(source_id__h42201 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1398 ;
assign _dfoo1468 =
(source_id__h42201 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1400 ;
assign _dfoo147 =
source_id__h70625 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo11 ;
assign _dfoo1470 =
(source_id__h42201 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1402 ;
assign _dfoo1472 =
(source_id__h42201 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1404 ;
assign _dfoo1474 =
(source_id__h42201 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1406 ;
assign _dfoo1476 =
(source_id__h42201 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1408 ;
assign _dfoo1478 =
(source_id__h42201 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1410 ;
assign _dfoo148 =
(source_id__h70625 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo80 ;
assign _dfoo1480 =
(source_id__h42201 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1412 ;
assign _dfoo1482 =
(source_id__h42201 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1414 ;
assign _dfoo1484 =
(source_id__h42201 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1416 ;
assign _dfoo1486 =
(source_id__h42201 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1418 ;
assign _dfoo1488 =
(source_id__h42201 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1420 ;
assign _dfoo149 =
source_id__h70625 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo13 ;
assign _dfoo1490 =
(source_id__h42201 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1422 ;
assign _dfoo1492 =
(source_id__h42201 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1424 ;
assign _dfoo1494 =
(source_id__h42201 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1426 ;
assign _dfoo1496 =
(source_id__h42201 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444) ?
wdata32__h27246[9] :
_dfoo1428 ;
assign _dfoo1497 =
source_id__h40705 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1361 ;
assign _dfoo1498 =
(source_id__h40705 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1430 ;
assign _dfoo1499 =
source_id__h40705 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1363 ;
assign _dfoo15 =
source_id__h73617 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo150 =
(source_id__h70625 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo82 ;
assign _dfoo1500 =
(source_id__h40705 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1432 ;
assign _dfoo1501 =
source_id__h40705 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1365 ;
assign _dfoo1502 =
(source_id__h40705 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1434 ;
assign _dfoo1503 =
source_id__h40705 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1367 ;
assign _dfoo1504 =
(source_id__h40705 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1436 ;
assign _dfoo1505 =
source_id__h40705 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1369 ;
assign _dfoo1506 =
(source_id__h40705 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1438 ;
assign _dfoo1507 =
source_id__h40705 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1371 ;
assign _dfoo1508 =
(source_id__h40705 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1440 ;
assign _dfoo1509 =
source_id__h40705 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1373 ;
assign _dfoo151 =
source_id__h70625 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo15 ;
assign _dfoo1510 =
(source_id__h40705 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1442 ;
assign _dfoo1511 =
source_id__h40705 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1375 ;
assign _dfoo1512 =
(source_id__h40705 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1444 ;
assign _dfoo1513 =
source_id__h40705 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1377 ;
assign _dfoo1514 =
(source_id__h40705 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1446 ;
assign _dfoo1515 =
source_id__h40705 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1379 ;
assign _dfoo1516 =
(source_id__h40705 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1448 ;
assign _dfoo1517 =
source_id__h40705 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1381 ;
assign _dfoo1518 =
(source_id__h40705 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1450 ;
assign _dfoo1519 =
source_id__h40705 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1383 ;
assign _dfoo152 =
(source_id__h70625 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo84 ;
assign _dfoo1520 =
(source_id__h40705 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1452 ;
assign _dfoo1521 =
source_id__h40705 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1385 ;
assign _dfoo1522 =
(source_id__h40705 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1454 ;
assign _dfoo1523 =
source_id__h40705 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1387 ;
assign _dfoo1524 =
(source_id__h40705 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1456 ;
assign _dfoo1525 =
source_id__h40705 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1389 ;
assign _dfoo1526 =
(source_id__h40705 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1458 ;
assign _dfoo1527 =
source_id__h40705 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1391 ;
assign _dfoo1528 =
(source_id__h40705 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1460 ;
assign _dfoo1529 =
source_id__h40705 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1393 ;
assign _dfoo153 =
source_id__h70625 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo17 ;
assign _dfoo1530 =
(source_id__h40705 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1462 ;
assign _dfoo1531 =
source_id__h40705 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1395 ;
assign _dfoo1532 =
(source_id__h40705 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1464 ;
assign _dfoo1533 =
source_id__h40705 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1397 ;
assign _dfoo1534 =
(source_id__h40705 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1466 ;
assign _dfoo1535 =
source_id__h40705 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1399 ;
assign _dfoo1536 =
(source_id__h40705 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1468 ;
assign _dfoo1537 =
source_id__h40705 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1401 ;
assign _dfoo1538 =
(source_id__h40705 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1470 ;
assign _dfoo1539 =
source_id__h40705 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1403 ;
assign _dfoo154 =
(source_id__h70625 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo86 ;
assign _dfoo1540 =
(source_id__h40705 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1472 ;
assign _dfoo1541 =
source_id__h40705 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1405 ;
assign _dfoo1542 =
(source_id__h40705 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1474 ;
assign _dfoo1543 =
source_id__h40705 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1407 ;
assign _dfoo1544 =
(source_id__h40705 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1476 ;
assign _dfoo1545 =
source_id__h40705 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1409 ;
assign _dfoo1546 =
(source_id__h40705 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1478 ;
assign _dfoo1547 =
source_id__h40705 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1411 ;
assign _dfoo1548 =
(source_id__h40705 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1480 ;
assign _dfoo1549 =
source_id__h40705 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1413 ;
assign _dfoo155 =
source_id__h70625 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo19 ;
assign _dfoo1550 =
(source_id__h40705 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1482 ;
assign _dfoo1551 =
source_id__h40705 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1415 ;
assign _dfoo1552 =
(source_id__h40705 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1484 ;
assign _dfoo1553 =
source_id__h40705 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1417 ;
assign _dfoo1554 =
(source_id__h40705 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1486 ;
assign _dfoo1555 =
source_id__h40705 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1419 ;
assign _dfoo1556 =
(source_id__h40705 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1488 ;
assign _dfoo1557 =
source_id__h40705 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1421 ;
assign _dfoo1558 =
(source_id__h40705 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1490 ;
assign _dfoo1559 =
source_id__h40705 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1423 ;
assign _dfoo156 =
(source_id__h70625 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo88 ;
assign _dfoo1560 =
(source_id__h40705 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1492 ;
assign _dfoo1561 =
source_id__h40705 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1425 ;
assign _dfoo1562 =
(source_id__h40705 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1494 ;
assign _dfoo1563 =
source_id__h40705 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383 ||
source_id__h42201 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1444 ||
_dfoo1427 ;
assign _dfoo1564 =
(source_id__h40705 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1383) ?
wdata32__h27246[8] :
_dfoo1496 ;
assign _dfoo1566 =
(source_id__h39209 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1498 ;
assign _dfoo1568 =
(source_id__h39209 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1500 ;
assign _dfoo157 =
source_id__h70625 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo21 ;
assign _dfoo1570 =
(source_id__h39209 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1502 ;
assign _dfoo1572 =
(source_id__h39209 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1504 ;
assign _dfoo1574 =
(source_id__h39209 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1506 ;
assign _dfoo1576 =
(source_id__h39209 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1508 ;
assign _dfoo1578 =
(source_id__h39209 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1510 ;
assign _dfoo158 =
(source_id__h70625 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo90 ;
assign _dfoo1580 =
(source_id__h39209 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1512 ;
assign _dfoo1582 =
(source_id__h39209 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1514 ;
assign _dfoo1584 =
(source_id__h39209 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1516 ;
assign _dfoo1586 =
(source_id__h39209 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1518 ;
assign _dfoo1588 =
(source_id__h39209 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1520 ;
assign _dfoo159 =
source_id__h70625 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo23 ;
assign _dfoo1590 =
(source_id__h39209 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1522 ;
assign _dfoo1592 =
(source_id__h39209 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1524 ;
assign _dfoo1594 =
(source_id__h39209 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1526 ;
assign _dfoo1596 =
(source_id__h39209 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1528 ;
assign _dfoo1598 =
(source_id__h39209 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1530 ;
assign _dfoo16 =
(source_id__h73617 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo160 =
(source_id__h70625 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo92 ;
assign _dfoo1600 =
(source_id__h39209 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1532 ;
assign _dfoo1602 =
(source_id__h39209 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1534 ;
assign _dfoo1604 =
(source_id__h39209 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1536 ;
assign _dfoo1606 =
(source_id__h39209 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1538 ;
assign _dfoo1608 =
(source_id__h39209 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1540 ;
assign _dfoo161 =
source_id__h70625 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo25 ;
assign _dfoo1610 =
(source_id__h39209 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1542 ;
assign _dfoo1612 =
(source_id__h39209 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1544 ;
assign _dfoo1614 =
(source_id__h39209 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1546 ;
assign _dfoo1616 =
(source_id__h39209 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1548 ;
assign _dfoo1618 =
(source_id__h39209 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1550 ;
assign _dfoo162 =
(source_id__h70625 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo94 ;
assign _dfoo1620 =
(source_id__h39209 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1552 ;
assign _dfoo1622 =
(source_id__h39209 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1554 ;
assign _dfoo1624 =
(source_id__h39209 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1556 ;
assign _dfoo1626 =
(source_id__h39209 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1558 ;
assign _dfoo1628 =
(source_id__h39209 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1560 ;
assign _dfoo163 =
source_id__h70625 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo27 ;
assign _dfoo1630 =
(source_id__h39209 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1562 ;
assign _dfoo1632 =
(source_id__h39209 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322) ?
wdata32__h27246[7] :
_dfoo1564 ;
assign _dfoo1633 =
source_id__h37713 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1497 ;
assign _dfoo1634 =
(source_id__h37713 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1566 ;
assign _dfoo1635 =
source_id__h37713 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1499 ;
assign _dfoo1636 =
(source_id__h37713 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1568 ;
assign _dfoo1637 =
source_id__h37713 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1501 ;
assign _dfoo1638 =
(source_id__h37713 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1570 ;
assign _dfoo1639 =
source_id__h37713 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1503 ;
assign _dfoo164 =
(source_id__h70625 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo96 ;
assign _dfoo1640 =
(source_id__h37713 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1572 ;
assign _dfoo1641 =
source_id__h37713 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1505 ;
assign _dfoo1642 =
(source_id__h37713 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1574 ;
assign _dfoo1643 =
source_id__h37713 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1507 ;
assign _dfoo1644 =
(source_id__h37713 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1576 ;
assign _dfoo1645 =
source_id__h37713 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1509 ;
assign _dfoo1646 =
(source_id__h37713 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1578 ;
assign _dfoo1647 =
source_id__h37713 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1511 ;
assign _dfoo1648 =
(source_id__h37713 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1580 ;
assign _dfoo1649 =
source_id__h37713 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1513 ;
assign _dfoo165 =
source_id__h70625 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo29 ;
assign _dfoo1650 =
(source_id__h37713 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1582 ;
assign _dfoo1651 =
source_id__h37713 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1515 ;
assign _dfoo1652 =
(source_id__h37713 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1584 ;
assign _dfoo1653 =
source_id__h37713 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1517 ;
assign _dfoo1654 =
(source_id__h37713 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1586 ;
assign _dfoo1655 =
source_id__h37713 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1519 ;
assign _dfoo1656 =
(source_id__h37713 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1588 ;
assign _dfoo1657 =
source_id__h37713 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1521 ;
assign _dfoo1658 =
(source_id__h37713 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1590 ;
assign _dfoo1659 =
source_id__h37713 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1523 ;
assign _dfoo166 =
(source_id__h70625 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo98 ;
assign _dfoo1660 =
(source_id__h37713 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1592 ;
assign _dfoo1661 =
source_id__h37713 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1525 ;
assign _dfoo1662 =
(source_id__h37713 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1594 ;
assign _dfoo1663 =
source_id__h37713 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1527 ;
assign _dfoo1664 =
(source_id__h37713 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1596 ;
assign _dfoo1665 =
source_id__h37713 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1529 ;
assign _dfoo1666 =
(source_id__h37713 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1598 ;
assign _dfoo1667 =
source_id__h37713 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1531 ;
assign _dfoo1668 =
(source_id__h37713 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1600 ;
assign _dfoo1669 =
source_id__h37713 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1533 ;
assign _dfoo167 =
source_id__h70625 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo31 ;
assign _dfoo1670 =
(source_id__h37713 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1602 ;
assign _dfoo1671 =
source_id__h37713 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1535 ;
assign _dfoo1672 =
(source_id__h37713 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1604 ;
assign _dfoo1673 =
source_id__h37713 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1537 ;
assign _dfoo1674 =
(source_id__h37713 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1606 ;
assign _dfoo1675 =
source_id__h37713 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1539 ;
assign _dfoo1676 =
(source_id__h37713 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1608 ;
assign _dfoo1677 =
source_id__h37713 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1541 ;
assign _dfoo1678 =
(source_id__h37713 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1610 ;
assign _dfoo1679 =
source_id__h37713 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1543 ;
assign _dfoo168 =
(source_id__h70625 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo100 ;
assign _dfoo1680 =
(source_id__h37713 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1612 ;
assign _dfoo1681 =
source_id__h37713 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1545 ;
assign _dfoo1682 =
(source_id__h37713 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1614 ;
assign _dfoo1683 =
source_id__h37713 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1547 ;
assign _dfoo1684 =
(source_id__h37713 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1616 ;
assign _dfoo1685 =
source_id__h37713 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1549 ;
assign _dfoo1686 =
(source_id__h37713 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1618 ;
assign _dfoo1687 =
source_id__h37713 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1551 ;
assign _dfoo1688 =
(source_id__h37713 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1620 ;
assign _dfoo1689 =
source_id__h37713 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1553 ;
assign _dfoo169 =
source_id__h70625 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo33 ;
assign _dfoo1690 =
(source_id__h37713 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1622 ;
assign _dfoo1691 =
source_id__h37713 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1555 ;
assign _dfoo1692 =
(source_id__h37713 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1624 ;
assign _dfoo1693 =
source_id__h37713 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1557 ;
assign _dfoo1694 =
(source_id__h37713 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1626 ;
assign _dfoo1695 =
source_id__h37713 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1559 ;
assign _dfoo1696 =
(source_id__h37713 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1628 ;
assign _dfoo1697 =
source_id__h37713 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1561 ;
assign _dfoo1698 =
(source_id__h37713 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1630 ;
assign _dfoo1699 =
source_id__h37713 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261 ||
source_id__h39209 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1322 ||
_dfoo1563 ;
assign _dfoo17 =
source_id__h73617 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo170 =
(source_id__h70625 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo102 ;
assign _dfoo1700 =
(source_id__h37713 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1261) ?
wdata32__h27246[6] :
_dfoo1632 ;
assign _dfoo1702 =
(source_id__h36217 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1634 ;
assign _dfoo1704 =
(source_id__h36217 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1636 ;
assign _dfoo1706 =
(source_id__h36217 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1638 ;
assign _dfoo1708 =
(source_id__h36217 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1640 ;
assign _dfoo171 =
source_id__h70625 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo35 ;
assign _dfoo1710 =
(source_id__h36217 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1642 ;
assign _dfoo1712 =
(source_id__h36217 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1644 ;
assign _dfoo1714 =
(source_id__h36217 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1646 ;
assign _dfoo1716 =
(source_id__h36217 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1648 ;
assign _dfoo1718 =
(source_id__h36217 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1650 ;
assign _dfoo172 =
(source_id__h70625 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo104 ;
assign _dfoo1720 =
(source_id__h36217 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1652 ;
assign _dfoo1722 =
(source_id__h36217 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1654 ;
assign _dfoo1724 =
(source_id__h36217 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1656 ;
assign _dfoo1726 =
(source_id__h36217 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1658 ;
assign _dfoo1728 =
(source_id__h36217 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1660 ;
assign _dfoo173 =
source_id__h70625 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo37 ;
assign _dfoo1730 =
(source_id__h36217 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1662 ;
assign _dfoo1732 =
(source_id__h36217 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1664 ;
assign _dfoo1734 =
(source_id__h36217 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1666 ;
assign _dfoo1736 =
(source_id__h36217 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1668 ;
assign _dfoo1738 =
(source_id__h36217 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1670 ;
assign _dfoo174 =
(source_id__h70625 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo106 ;
assign _dfoo1740 =
(source_id__h36217 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1672 ;
assign _dfoo1742 =
(source_id__h36217 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1674 ;
assign _dfoo1744 =
(source_id__h36217 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1676 ;
assign _dfoo1746 =
(source_id__h36217 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1678 ;
assign _dfoo1748 =
(source_id__h36217 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1680 ;
assign _dfoo175 =
source_id__h70625 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo39 ;
assign _dfoo1750 =
(source_id__h36217 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1682 ;
assign _dfoo1752 =
(source_id__h36217 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1684 ;
assign _dfoo1754 =
(source_id__h36217 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1686 ;
assign _dfoo1756 =
(source_id__h36217 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1688 ;
assign _dfoo1758 =
(source_id__h36217 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1690 ;
assign _dfoo176 =
(source_id__h70625 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo108 ;
assign _dfoo1760 =
(source_id__h36217 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1692 ;
assign _dfoo1762 =
(source_id__h36217 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1694 ;
assign _dfoo1764 =
(source_id__h36217 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1696 ;
assign _dfoo1766 =
(source_id__h36217 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1698 ;
assign _dfoo1768 =
(source_id__h36217 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200) ?
wdata32__h27246[5] :
_dfoo1700 ;
assign _dfoo1769 =
source_id__h34721 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1633 ;
assign _dfoo177 =
source_id__h70625 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo41 ;
assign _dfoo1770 =
(source_id__h34721 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1702 ;
assign _dfoo1771 =
source_id__h34721 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1635 ;
assign _dfoo1772 =
(source_id__h34721 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1704 ;
assign _dfoo1773 =
source_id__h34721 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1637 ;
assign _dfoo1774 =
(source_id__h34721 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1706 ;
assign _dfoo1775 =
source_id__h34721 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1639 ;
assign _dfoo1776 =
(source_id__h34721 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1708 ;
assign _dfoo1777 =
source_id__h34721 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1641 ;
assign _dfoo1778 =
(source_id__h34721 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1710 ;
assign _dfoo1779 =
source_id__h34721 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1643 ;
assign _dfoo178 =
(source_id__h70625 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo110 ;
assign _dfoo1780 =
(source_id__h34721 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1712 ;
assign _dfoo1781 =
source_id__h34721 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1645 ;
assign _dfoo1782 =
(source_id__h34721 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1714 ;
assign _dfoo1783 =
source_id__h34721 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1647 ;
assign _dfoo1784 =
(source_id__h34721 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1716 ;
assign _dfoo1785 =
source_id__h34721 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1649 ;
assign _dfoo1786 =
(source_id__h34721 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1718 ;
assign _dfoo1787 =
source_id__h34721 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1651 ;
assign _dfoo1788 =
(source_id__h34721 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1720 ;
assign _dfoo1789 =
source_id__h34721 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1653 ;
assign _dfoo179 =
source_id__h70625 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo43 ;
assign _dfoo1790 =
(source_id__h34721 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1722 ;
assign _dfoo1791 =
source_id__h34721 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1655 ;
assign _dfoo1792 =
(source_id__h34721 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1724 ;
assign _dfoo1793 =
source_id__h34721 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1657 ;
assign _dfoo1794 =
(source_id__h34721 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1726 ;
assign _dfoo1795 =
source_id__h34721 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1659 ;
assign _dfoo1796 =
(source_id__h34721 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1728 ;
assign _dfoo1797 =
source_id__h34721 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1661 ;
assign _dfoo1798 =
(source_id__h34721 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1730 ;
assign _dfoo1799 =
source_id__h34721 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1663 ;
assign _dfoo18 =
(source_id__h73617 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo180 =
(source_id__h70625 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo112 ;
assign _dfoo1800 =
(source_id__h34721 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1732 ;
assign _dfoo1801 =
source_id__h34721 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1665 ;
assign _dfoo1802 =
(source_id__h34721 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1734 ;
assign _dfoo1803 =
source_id__h34721 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1667 ;
assign _dfoo1804 =
(source_id__h34721 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1736 ;
assign _dfoo1805 =
source_id__h34721 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1669 ;
assign _dfoo1806 =
(source_id__h34721 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1738 ;
assign _dfoo1807 =
source_id__h34721 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1671 ;
assign _dfoo1808 =
(source_id__h34721 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1740 ;
assign _dfoo1809 =
source_id__h34721 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1673 ;
assign _dfoo181 =
source_id__h70625 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo45 ;
assign _dfoo1810 =
(source_id__h34721 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1742 ;
assign _dfoo1811 =
source_id__h34721 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1675 ;
assign _dfoo1812 =
(source_id__h34721 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1744 ;
assign _dfoo1813 =
source_id__h34721 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1677 ;
assign _dfoo1814 =
(source_id__h34721 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1746 ;
assign _dfoo1815 =
source_id__h34721 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1679 ;
assign _dfoo1816 =
(source_id__h34721 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1748 ;
assign _dfoo1817 =
source_id__h34721 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1681 ;
assign _dfoo1818 =
(source_id__h34721 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1750 ;
assign _dfoo1819 =
source_id__h34721 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1683 ;
assign _dfoo182 =
(source_id__h70625 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo114 ;
assign _dfoo1820 =
(source_id__h34721 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1752 ;
assign _dfoo1821 =
source_id__h34721 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1685 ;
assign _dfoo1822 =
(source_id__h34721 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1754 ;
assign _dfoo1823 =
source_id__h34721 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1687 ;
assign _dfoo1824 =
(source_id__h34721 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1756 ;
assign _dfoo1825 =
source_id__h34721 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1689 ;
assign _dfoo1826 =
(source_id__h34721 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1758 ;
assign _dfoo1827 =
source_id__h34721 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1691 ;
assign _dfoo1828 =
(source_id__h34721 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1760 ;
assign _dfoo1829 =
source_id__h34721 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1693 ;
assign _dfoo183 =
source_id__h70625 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo47 ;
assign _dfoo1830 =
(source_id__h34721 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1762 ;
assign _dfoo1831 =
source_id__h34721 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1695 ;
assign _dfoo1832 =
(source_id__h34721 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1764 ;
assign _dfoo1833 =
source_id__h34721 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1697 ;
assign _dfoo1834 =
(source_id__h34721 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1766 ;
assign _dfoo1835 =
source_id__h34721 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139 ||
source_id__h36217 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1200 ||
_dfoo1699 ;
assign _dfoo1836 =
(source_id__h34721 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1139) ?
wdata32__h27246[4] :
_dfoo1768 ;
assign _dfoo1838 =
(source_id__h33225 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1770 ;
assign _dfoo184 =
(source_id__h70625 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo116 ;
assign _dfoo1840 =
(source_id__h33225 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1772 ;
assign _dfoo1842 =
(source_id__h33225 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1774 ;
assign _dfoo1844 =
(source_id__h33225 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1776 ;
assign _dfoo1846 =
(source_id__h33225 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1778 ;
assign _dfoo1848 =
(source_id__h33225 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1780 ;
assign _dfoo185 =
source_id__h70625 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo49 ;
assign _dfoo1850 =
(source_id__h33225 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1782 ;
assign _dfoo1852 =
(source_id__h33225 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1784 ;
assign _dfoo1854 =
(source_id__h33225 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1786 ;
assign _dfoo1856 =
(source_id__h33225 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1788 ;
assign _dfoo1858 =
(source_id__h33225 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1790 ;
assign _dfoo186 =
(source_id__h70625 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo118 ;
assign _dfoo1860 =
(source_id__h33225 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1792 ;
assign _dfoo1862 =
(source_id__h33225 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1794 ;
assign _dfoo1864 =
(source_id__h33225 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1796 ;
assign _dfoo1866 =
(source_id__h33225 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1798 ;
assign _dfoo1868 =
(source_id__h33225 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1800 ;
assign _dfoo187 =
source_id__h70625 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo51 ;
assign _dfoo1870 =
(source_id__h33225 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1802 ;
assign _dfoo1872 =
(source_id__h33225 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1804 ;
assign _dfoo1874 =
(source_id__h33225 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1806 ;
assign _dfoo1876 =
(source_id__h33225 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1808 ;
assign _dfoo1878 =
(source_id__h33225 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1810 ;
assign _dfoo188 =
(source_id__h70625 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo120 ;
assign _dfoo1880 =
(source_id__h33225 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1812 ;
assign _dfoo1882 =
(source_id__h33225 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1814 ;
assign _dfoo1884 =
(source_id__h33225 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1816 ;
assign _dfoo1886 =
(source_id__h33225 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1818 ;
assign _dfoo1888 =
(source_id__h33225 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1820 ;
assign _dfoo189 =
source_id__h70625 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo53 ;
assign _dfoo1890 =
(source_id__h33225 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1822 ;
assign _dfoo1892 =
(source_id__h33225 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1824 ;
assign _dfoo1894 =
(source_id__h33225 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1826 ;
assign _dfoo1896 =
(source_id__h33225 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1828 ;
assign _dfoo1898 =
(source_id__h33225 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1830 ;
assign _dfoo19 =
source_id__h73617 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo190 =
(source_id__h70625 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo122 ;
assign _dfoo1900 =
(source_id__h33225 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1832 ;
assign _dfoo1902 =
(source_id__h33225 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1834 ;
assign _dfoo1904 =
(source_id__h33225 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078) ?
wdata32__h27246[3] :
_dfoo1836 ;
assign _dfoo1905 =
source_id__h31729 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1769 ;
assign _dfoo1906 =
(source_id__h31729 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1838 ;
assign _dfoo1907 =
source_id__h31729 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1771 ;
assign _dfoo1908 =
(source_id__h31729 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1840 ;
assign _dfoo1909 =
source_id__h31729 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1773 ;
assign _dfoo191 =
source_id__h70625 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo55 ;
assign _dfoo1910 =
(source_id__h31729 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1842 ;
assign _dfoo1911 =
source_id__h31729 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1775 ;
assign _dfoo1912 =
(source_id__h31729 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1844 ;
assign _dfoo1913 =
source_id__h31729 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1777 ;
assign _dfoo1914 =
(source_id__h31729 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1846 ;
assign _dfoo1915 =
source_id__h31729 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1779 ;
assign _dfoo1916 =
(source_id__h31729 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1848 ;
assign _dfoo1917 =
source_id__h31729 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1781 ;
assign _dfoo1918 =
(source_id__h31729 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1850 ;
assign _dfoo1919 =
source_id__h31729 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1783 ;
assign _dfoo192 =
(source_id__h70625 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo124 ;
assign _dfoo1920 =
(source_id__h31729 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1852 ;
assign _dfoo1921 =
source_id__h31729 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1785 ;
assign _dfoo1922 =
(source_id__h31729 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1854 ;
assign _dfoo1923 =
source_id__h31729 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1787 ;
assign _dfoo1924 =
(source_id__h31729 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1856 ;
assign _dfoo1925 =
source_id__h31729 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1789 ;
assign _dfoo1926 =
(source_id__h31729 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1858 ;
assign _dfoo1927 =
source_id__h31729 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1791 ;
assign _dfoo1928 =
(source_id__h31729 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1860 ;
assign _dfoo1929 =
source_id__h31729 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1793 ;
assign _dfoo193 =
source_id__h70625 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo57 ;
assign _dfoo1930 =
(source_id__h31729 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1862 ;
assign _dfoo1931 =
source_id__h31729 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1795 ;
assign _dfoo1932 =
(source_id__h31729 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1864 ;
assign _dfoo1933 =
source_id__h31729 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1797 ;
assign _dfoo1934 =
(source_id__h31729 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1866 ;
assign _dfoo1935 =
source_id__h31729 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1799 ;
assign _dfoo1936 =
(source_id__h31729 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1868 ;
assign _dfoo1937 =
source_id__h31729 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1801 ;
assign _dfoo1938 =
(source_id__h31729 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1870 ;
assign _dfoo1939 =
source_id__h31729 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1803 ;
assign _dfoo194 =
(source_id__h70625 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo126 ;
assign _dfoo1940 =
(source_id__h31729 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1872 ;
assign _dfoo1941 =
source_id__h31729 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1805 ;
assign _dfoo1942 =
(source_id__h31729 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1874 ;
assign _dfoo1943 =
source_id__h31729 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1807 ;
assign _dfoo1944 =
(source_id__h31729 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1876 ;
assign _dfoo1945 =
source_id__h31729 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1809 ;
assign _dfoo1946 =
(source_id__h31729 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1878 ;
assign _dfoo1947 =
source_id__h31729 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1811 ;
assign _dfoo1948 =
(source_id__h31729 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1880 ;
assign _dfoo1949 =
source_id__h31729 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1813 ;
assign _dfoo195 =
source_id__h70625 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo59 ;
assign _dfoo1950 =
(source_id__h31729 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1882 ;
assign _dfoo1951 =
source_id__h31729 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1815 ;
assign _dfoo1952 =
(source_id__h31729 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1884 ;
assign _dfoo1953 =
source_id__h31729 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1817 ;
assign _dfoo1954 =
(source_id__h31729 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1886 ;
assign _dfoo1955 =
source_id__h31729 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1819 ;
assign _dfoo1956 =
(source_id__h31729 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1888 ;
assign _dfoo1957 =
source_id__h31729 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1821 ;
assign _dfoo1958 =
(source_id__h31729 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1890 ;
assign _dfoo1959 =
source_id__h31729 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1823 ;
assign _dfoo196 =
(source_id__h70625 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo128 ;
assign _dfoo1960 =
(source_id__h31729 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1892 ;
assign _dfoo1961 =
source_id__h31729 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1825 ;
assign _dfoo1962 =
(source_id__h31729 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1894 ;
assign _dfoo1963 =
source_id__h31729 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1827 ;
assign _dfoo1964 =
(source_id__h31729 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1896 ;
assign _dfoo1965 =
source_id__h31729 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1829 ;
assign _dfoo1966 =
(source_id__h31729 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1898 ;
assign _dfoo1967 =
source_id__h31729 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1831 ;
assign _dfoo1968 =
(source_id__h31729 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1900 ;
assign _dfoo1969 =
source_id__h31729 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1833 ;
assign _dfoo197 =
source_id__h70625 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo61 ;
assign _dfoo1970 =
(source_id__h31729 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1902 ;
assign _dfoo1971 =
source_id__h31729 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017 ||
source_id__h33225 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1078 ||
_dfoo1835 ;
assign _dfoo1972 =
(source_id__h31729 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1017) ?
wdata32__h27246[2] :
_dfoo1904 ;
assign _dfoo1974 =
(source_id__h30233 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1906 ;
assign _dfoo1976 =
(source_id__h30233 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1908 ;
assign _dfoo1978 =
(source_id__h30233 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1910 ;
assign _dfoo198 =
(source_id__h70625 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo130 ;
assign _dfoo1980 =
(source_id__h30233 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1912 ;
assign _dfoo1982 =
(source_id__h30233 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1914 ;
assign _dfoo1984 =
(source_id__h30233 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1916 ;
assign _dfoo1986 =
(source_id__h30233 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1918 ;
assign _dfoo1988 =
(source_id__h30233 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1920 ;
assign _dfoo199 =
source_id__h70625 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo63 ;
assign _dfoo1990 =
(source_id__h30233 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1922 ;
assign _dfoo1992 =
(source_id__h30233 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1924 ;
assign _dfoo1994 =
(source_id__h30233 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1926 ;
assign _dfoo1996 =
(source_id__h30233 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1928 ;
assign _dfoo1998 =
(source_id__h30233 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1930 ;
assign _dfoo2 =
(source_id__h73617 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo20 =
(source_id__h73617 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo200 =
(source_id__h70625 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo132 ;
assign _dfoo2000 =
(source_id__h30233 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1932 ;
assign _dfoo2002 =
(source_id__h30233 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1934 ;
assign _dfoo2004 =
(source_id__h30233 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1936 ;
assign _dfoo2006 =
(source_id__h30233 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1938 ;
assign _dfoo2008 =
(source_id__h30233 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1940 ;
assign _dfoo201 =
source_id__h70625 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo65 ;
assign _dfoo2010 =
(source_id__h30233 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1942 ;
assign _dfoo2012 =
(source_id__h30233 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1944 ;
assign _dfoo2014 =
(source_id__h30233 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1946 ;
assign _dfoo2016 =
(source_id__h30233 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1948 ;
assign _dfoo2018 =
(source_id__h30233 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1950 ;
assign _dfoo202 =
(source_id__h70625 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo134 ;
assign _dfoo2020 =
(source_id__h30233 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1952 ;
assign _dfoo2022 =
(source_id__h30233 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1954 ;
assign _dfoo2024 =
(source_id__h30233 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1956 ;
assign _dfoo2026 =
(source_id__h30233 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1958 ;
assign _dfoo2028 =
(source_id__h30233 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1960 ;
assign _dfoo203 =
source_id__h70625 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603 ||
source_id__h72121 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664 ||
_dfoo67 ;
assign _dfoo2030 =
(source_id__h30233 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1962 ;
assign _dfoo2032 =
(source_id__h30233 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1964 ;
assign _dfoo2034 =
(source_id__h30233 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1966 ;
assign _dfoo2036 =
(source_id__h30233 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1968 ;
assign _dfoo2038 =
(source_id__h30233 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1970 ;
assign _dfoo204 =
(source_id__h70625 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2603) ?
wdata32__h27246[28] :
_dfoo136 ;
assign _dfoo2040 =
(source_id__h30233 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956) ?
wdata32__h27246[1] :
_dfoo1972 ;
assign _dfoo2041 =
source_id_base__h28620 == 10'd16 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1905 ;
assign _dfoo2043 =
source_id_base__h28620 == 10'd15 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1907 ;
assign _dfoo2045 =
source_id_base__h28620 == 10'd14 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1909 ;
assign _dfoo2047 =
source_id_base__h28620 == 10'd13 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1911 ;
assign _dfoo2049 =
source_id_base__h28620 == 10'd12 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1913 ;
assign _dfoo2051 =
source_id_base__h28620 == 10'd11 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1915 ;
assign _dfoo2053 =
source_id_base__h28620 == 10'd10 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1917 ;
assign _dfoo2055 =
source_id_base__h28620 == 10'd9 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1919 ;
assign _dfoo2057 =
source_id_base__h28620 == 10'd8 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1921 ;
assign _dfoo2059 =
source_id_base__h28620 == 10'd7 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1923 ;
assign _dfoo206 =
(source_id__h69129 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo138 ;
assign _dfoo2061 =
source_id_base__h28620 == 10'd6 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1925 ;
assign _dfoo2063 =
source_id_base__h28620 == 10'd5 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1927 ;
assign _dfoo2065 =
source_id_base__h28620 == 10'd4 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1929 ;
assign _dfoo2067 =
source_id_base__h28620 == 10'd3 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1931 ;
assign _dfoo2069 =
source_id_base__h28620 == 10'd2 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1933 ;
assign _dfoo2071 =
source_id_base__h28620 == 10'd1 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1935 ;
assign _dfoo2073 =
source_id_base__h28620 == 10'd0 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 ||
source_id__h30233 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1937 ;
assign _dfoo2075 =
source_id_base__h28620 == 10'd16 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1939 ;
assign _dfoo2077 =
source_id_base__h28620 == 10'd15 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1941 ;
assign _dfoo2079 =
source_id_base__h28620 == 10'd14 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1943 ;
assign _dfoo208 =
(source_id__h69129 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo140 ;
assign _dfoo2081 =
source_id_base__h28620 == 10'd13 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1945 ;
assign _dfoo2083 =
source_id_base__h28620 == 10'd12 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1947 ;
assign _dfoo2085 =
source_id_base__h28620 == 10'd11 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1949 ;
assign _dfoo2087 =
source_id_base__h28620 == 10'd10 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1951 ;
assign _dfoo2089 =
source_id_base__h28620 == 10'd9 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1953 ;
assign _dfoo2091 =
source_id_base__h28620 == 10'd8 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1955 ;
assign _dfoo2093 =
source_id_base__h28620 == 10'd7 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1957 ;
assign _dfoo2095 =
source_id_base__h28620 == 10'd6 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1959 ;
assign _dfoo2097 =
source_id_base__h28620 == 10'd5 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1961 ;
assign _dfoo2099 =
source_id_base__h28620 == 10'd4 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1963 ;
assign _dfoo21 =
source_id__h73617 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo210 =
(source_id__h69129 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo142 ;
assign _dfoo2101 =
source_id_base__h28620 == 10'd3 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1965 ;
assign _dfoo2103 =
source_id_base__h28620 == 10'd2 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1967 ;
assign _dfoo2105 =
source_id_base__h28620 == 10'd1 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1969 ;
assign _dfoo2107 =
source_id_base__h28620 == 10'd0 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 ||
source_id__h30233 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d956 ||
_dfoo1971 ;
assign _dfoo212 =
(source_id__h69129 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo144 ;
assign _dfoo214 =
(source_id__h69129 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo146 ;
assign _dfoo216 =
(source_id__h69129 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo148 ;
assign _dfoo218 =
(source_id__h69129 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo150 ;
assign _dfoo22 =
(source_id__h73617 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo220 =
(source_id__h69129 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo152 ;
assign _dfoo222 =
(source_id__h69129 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo154 ;
assign _dfoo224 =
(source_id__h69129 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo156 ;
assign _dfoo226 =
(source_id__h69129 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo158 ;
assign _dfoo228 =
(source_id__h69129 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo160 ;
assign _dfoo23 =
source_id__h73617 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo230 =
(source_id__h69129 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo162 ;
assign _dfoo232 =
(source_id__h69129 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo164 ;
assign _dfoo234 =
(source_id__h69129 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo166 ;
assign _dfoo236 =
(source_id__h69129 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo168 ;
assign _dfoo238 =
(source_id__h69129 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo170 ;
assign _dfoo24 =
(source_id__h73617 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo240 =
(source_id__h69129 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo172 ;
assign _dfoo242 =
(source_id__h69129 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo174 ;
assign _dfoo244 =
(source_id__h69129 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo176 ;
assign _dfoo246 =
(source_id__h69129 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo178 ;
assign _dfoo248 =
(source_id__h69129 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo180 ;
assign _dfoo25 =
source_id__h73617 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo250 =
(source_id__h69129 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo182 ;
assign _dfoo252 =
(source_id__h69129 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo184 ;
assign _dfoo254 =
(source_id__h69129 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo186 ;
assign _dfoo256 =
(source_id__h69129 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo188 ;
assign _dfoo258 =
(source_id__h69129 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo190 ;
assign _dfoo26 =
(source_id__h73617 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo260 =
(source_id__h69129 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo192 ;
assign _dfoo262 =
(source_id__h69129 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo194 ;
assign _dfoo264 =
(source_id__h69129 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo196 ;
assign _dfoo266 =
(source_id__h69129 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo198 ;
assign _dfoo268 =
(source_id__h69129 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo200 ;
assign _dfoo27 =
source_id__h73617 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo270 =
(source_id__h69129 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo202 ;
assign _dfoo272 =
(source_id__h69129 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542) ?
wdata32__h27246[27] :
_dfoo204 ;
assign _dfoo273 =
source_id__h67633 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo137 ;
assign _dfoo274 =
(source_id__h67633 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo206 ;
assign _dfoo275 =
source_id__h67633 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo139 ;
assign _dfoo276 =
(source_id__h67633 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo208 ;
assign _dfoo277 =
source_id__h67633 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo141 ;
assign _dfoo278 =
(source_id__h67633 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo210 ;
assign _dfoo279 =
source_id__h67633 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo143 ;
assign _dfoo28 =
(source_id__h73617 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo280 =
(source_id__h67633 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo212 ;
assign _dfoo281 =
source_id__h67633 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo145 ;
assign _dfoo282 =
(source_id__h67633 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo214 ;
assign _dfoo283 =
source_id__h67633 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo147 ;
assign _dfoo284 =
(source_id__h67633 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo216 ;
assign _dfoo285 =
source_id__h67633 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo149 ;
assign _dfoo286 =
(source_id__h67633 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo218 ;
assign _dfoo287 =
source_id__h67633 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo151 ;
assign _dfoo288 =
(source_id__h67633 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo220 ;
assign _dfoo289 =
source_id__h67633 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo153 ;
assign _dfoo29 =
source_id__h73617 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo290 =
(source_id__h67633 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo222 ;
assign _dfoo291 =
source_id__h67633 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo155 ;
assign _dfoo292 =
(source_id__h67633 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo224 ;
assign _dfoo293 =
source_id__h67633 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo157 ;
assign _dfoo294 =
(source_id__h67633 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo226 ;
assign _dfoo295 =
source_id__h67633 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo159 ;
assign _dfoo296 =
(source_id__h67633 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo228 ;
assign _dfoo297 =
source_id__h67633 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo161 ;
assign _dfoo298 =
(source_id__h67633 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo230 ;
assign _dfoo299 =
source_id__h67633 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo163 ;
assign _dfoo3 =
source_id__h73617 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo30 =
(source_id__h73617 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo300 =
(source_id__h67633 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo232 ;
assign _dfoo301 =
source_id__h67633 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo165 ;
assign _dfoo302 =
(source_id__h67633 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo234 ;
assign _dfoo303 =
source_id__h67633 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo167 ;
assign _dfoo304 =
(source_id__h67633 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo236 ;
assign _dfoo305 =
source_id__h67633 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo169 ;
assign _dfoo306 =
(source_id__h67633 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo238 ;
assign _dfoo307 =
source_id__h67633 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo171 ;
assign _dfoo308 =
(source_id__h67633 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo240 ;
assign _dfoo309 =
source_id__h67633 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo173 ;
assign _dfoo31 =
source_id__h73617 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo310 =
(source_id__h67633 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo242 ;
assign _dfoo311 =
source_id__h67633 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo175 ;
assign _dfoo312 =
(source_id__h67633 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo244 ;
assign _dfoo313 =
source_id__h67633 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo177 ;
assign _dfoo314 =
(source_id__h67633 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo246 ;
assign _dfoo315 =
source_id__h67633 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo179 ;
assign _dfoo316 =
(source_id__h67633 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo248 ;
assign _dfoo317 =
source_id__h67633 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo181 ;
assign _dfoo318 =
(source_id__h67633 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo250 ;
assign _dfoo319 =
source_id__h67633 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo183 ;
assign _dfoo32 =
(source_id__h73617 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo320 =
(source_id__h67633 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo252 ;
assign _dfoo321 =
source_id__h67633 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo185 ;
assign _dfoo322 =
(source_id__h67633 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo254 ;
assign _dfoo323 =
source_id__h67633 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo187 ;
assign _dfoo324 =
(source_id__h67633 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo256 ;
assign _dfoo325 =
source_id__h67633 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo189 ;
assign _dfoo326 =
(source_id__h67633 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo258 ;
assign _dfoo327 =
source_id__h67633 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo191 ;
assign _dfoo328 =
(source_id__h67633 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo260 ;
assign _dfoo329 =
source_id__h67633 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo193 ;
assign _dfoo33 =
source_id__h73617 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo330 =
(source_id__h67633 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo262 ;
assign _dfoo331 =
source_id__h67633 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo195 ;
assign _dfoo332 =
(source_id__h67633 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo264 ;
assign _dfoo333 =
source_id__h67633 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo197 ;
assign _dfoo334 =
(source_id__h67633 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo266 ;
assign _dfoo335 =
source_id__h67633 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo199 ;
assign _dfoo336 =
(source_id__h67633 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo268 ;
assign _dfoo337 =
source_id__h67633 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo201 ;
assign _dfoo338 =
(source_id__h67633 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo270 ;
assign _dfoo339 =
source_id__h67633 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481 ||
source_id__h69129 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2542 ||
_dfoo203 ;
assign _dfoo34 =
(source_id__h73617 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo340 =
(source_id__h67633 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2481) ?
wdata32__h27246[26] :
_dfoo272 ;
assign _dfoo342 =
(source_id__h66137 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo274 ;
assign _dfoo344 =
(source_id__h66137 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo276 ;
assign _dfoo346 =
(source_id__h66137 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo278 ;
assign _dfoo348 =
(source_id__h66137 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo280 ;
assign _dfoo35 =
source_id__h73617 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo350 =
(source_id__h66137 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo282 ;
assign _dfoo352 =
(source_id__h66137 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo284 ;
assign _dfoo354 =
(source_id__h66137 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo286 ;
assign _dfoo356 =
(source_id__h66137 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo288 ;
assign _dfoo358 =
(source_id__h66137 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo290 ;
assign _dfoo36 =
(source_id__h73617 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo360 =
(source_id__h66137 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo292 ;
assign _dfoo362 =
(source_id__h66137 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo294 ;
assign _dfoo364 =
(source_id__h66137 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo296 ;
assign _dfoo366 =
(source_id__h66137 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo298 ;
assign _dfoo368 =
(source_id__h66137 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo300 ;
assign _dfoo37 =
source_id__h73617 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo370 =
(source_id__h66137 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo302 ;
assign _dfoo372 =
(source_id__h66137 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo304 ;
assign _dfoo374 =
(source_id__h66137 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo306 ;
assign _dfoo376 =
(source_id__h66137 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo308 ;
assign _dfoo378 =
(source_id__h66137 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo310 ;
assign _dfoo38 =
(source_id__h73617 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo380 =
(source_id__h66137 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo312 ;
assign _dfoo382 =
(source_id__h66137 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo314 ;
assign _dfoo384 =
(source_id__h66137 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo316 ;
assign _dfoo386 =
(source_id__h66137 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo318 ;
assign _dfoo388 =
(source_id__h66137 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo320 ;
assign _dfoo39 =
source_id__h73617 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo390 =
(source_id__h66137 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo322 ;
assign _dfoo392 =
(source_id__h66137 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo324 ;
assign _dfoo394 =
(source_id__h66137 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo326 ;
assign _dfoo396 =
(source_id__h66137 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo328 ;
assign _dfoo398 =
(source_id__h66137 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo330 ;
assign _dfoo4 =
(source_id__h73617 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo40 =
(source_id__h73617 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo400 =
(source_id__h66137 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo332 ;
assign _dfoo402 =
(source_id__h66137 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo334 ;
assign _dfoo404 =
(source_id__h66137 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo336 ;
assign _dfoo406 =
(source_id__h66137 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo338 ;
assign _dfoo408 =
(source_id__h66137 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420) ?
wdata32__h27246[25] :
_dfoo340 ;
assign _dfoo409 =
source_id__h64641 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo273 ;
assign _dfoo41 =
source_id__h73617 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo410 =
(source_id__h64641 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo342 ;
assign _dfoo411 =
source_id__h64641 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo275 ;
assign _dfoo412 =
(source_id__h64641 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo344 ;
assign _dfoo413 =
source_id__h64641 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo277 ;
assign _dfoo414 =
(source_id__h64641 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo346 ;
assign _dfoo415 =
source_id__h64641 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo279 ;
assign _dfoo416 =
(source_id__h64641 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo348 ;
assign _dfoo417 =
source_id__h64641 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo281 ;
assign _dfoo418 =
(source_id__h64641 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo350 ;
assign _dfoo419 =
source_id__h64641 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo283 ;
assign _dfoo42 =
(source_id__h73617 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo420 =
(source_id__h64641 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo352 ;
assign _dfoo421 =
source_id__h64641 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo285 ;
assign _dfoo422 =
(source_id__h64641 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo354 ;
assign _dfoo423 =
source_id__h64641 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo287 ;
assign _dfoo424 =
(source_id__h64641 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo356 ;
assign _dfoo425 =
source_id__h64641 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo289 ;
assign _dfoo426 =
(source_id__h64641 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo358 ;
assign _dfoo427 =
source_id__h64641 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo291 ;
assign _dfoo428 =
(source_id__h64641 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo360 ;
assign _dfoo429 =
source_id__h64641 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo293 ;
assign _dfoo43 =
source_id__h73617 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo430 =
(source_id__h64641 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo362 ;
assign _dfoo431 =
source_id__h64641 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo295 ;
assign _dfoo432 =
(source_id__h64641 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo364 ;
assign _dfoo433 =
source_id__h64641 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo297 ;
assign _dfoo434 =
(source_id__h64641 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo366 ;
assign _dfoo435 =
source_id__h64641 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo299 ;
assign _dfoo436 =
(source_id__h64641 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo368 ;
assign _dfoo437 =
source_id__h64641 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo301 ;
assign _dfoo438 =
(source_id__h64641 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo370 ;
assign _dfoo439 =
source_id__h64641 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo303 ;
assign _dfoo44 =
(source_id__h73617 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo440 =
(source_id__h64641 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo372 ;
assign _dfoo441 =
source_id__h64641 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo305 ;
assign _dfoo442 =
(source_id__h64641 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo374 ;
assign _dfoo443 =
source_id__h64641 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo307 ;
assign _dfoo444 =
(source_id__h64641 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo376 ;
assign _dfoo445 =
source_id__h64641 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo309 ;
assign _dfoo446 =
(source_id__h64641 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo378 ;
assign _dfoo447 =
source_id__h64641 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo311 ;
assign _dfoo448 =
(source_id__h64641 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo380 ;
assign _dfoo449 =
source_id__h64641 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo313 ;
assign _dfoo45 =
source_id__h73617 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo450 =
(source_id__h64641 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo382 ;
assign _dfoo451 =
source_id__h64641 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo315 ;
assign _dfoo452 =
(source_id__h64641 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo384 ;
assign _dfoo453 =
source_id__h64641 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo317 ;
assign _dfoo454 =
(source_id__h64641 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo386 ;
assign _dfoo455 =
source_id__h64641 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo319 ;
assign _dfoo456 =
(source_id__h64641 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo388 ;
assign _dfoo457 =
source_id__h64641 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo321 ;
assign _dfoo458 =
(source_id__h64641 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo390 ;
assign _dfoo459 =
source_id__h64641 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo323 ;
assign _dfoo46 =
(source_id__h73617 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo460 =
(source_id__h64641 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo392 ;
assign _dfoo461 =
source_id__h64641 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo325 ;
assign _dfoo462 =
(source_id__h64641 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo394 ;
assign _dfoo463 =
source_id__h64641 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo327 ;
assign _dfoo464 =
(source_id__h64641 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo396 ;
assign _dfoo465 =
source_id__h64641 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo329 ;
assign _dfoo466 =
(source_id__h64641 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo398 ;
assign _dfoo467 =
source_id__h64641 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo331 ;
assign _dfoo468 =
(source_id__h64641 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo400 ;
assign _dfoo469 =
source_id__h64641 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo333 ;
assign _dfoo47 =
source_id__h73617 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo470 =
(source_id__h64641 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo402 ;
assign _dfoo471 =
source_id__h64641 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo335 ;
assign _dfoo472 =
(source_id__h64641 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo404 ;
assign _dfoo473 =
source_id__h64641 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo337 ;
assign _dfoo474 =
(source_id__h64641 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo406 ;
assign _dfoo475 =
source_id__h64641 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359 ||
source_id__h66137 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2420 ||
_dfoo339 ;
assign _dfoo476 =
(source_id__h64641 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2359) ?
wdata32__h27246[24] :
_dfoo408 ;
assign _dfoo478 =
(source_id__h63145 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo410 ;
assign _dfoo48 =
(source_id__h73617 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo480 =
(source_id__h63145 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo412 ;
assign _dfoo482 =
(source_id__h63145 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo414 ;
assign _dfoo484 =
(source_id__h63145 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo416 ;
assign _dfoo486 =
(source_id__h63145 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo418 ;
assign _dfoo488 =
(source_id__h63145 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo420 ;
assign _dfoo49 =
source_id__h73617 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo490 =
(source_id__h63145 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo422 ;
assign _dfoo492 =
(source_id__h63145 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo424 ;
assign _dfoo494 =
(source_id__h63145 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo426 ;
assign _dfoo496 =
(source_id__h63145 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo428 ;
assign _dfoo498 =
(source_id__h63145 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo430 ;
assign _dfoo5 =
source_id__h73617 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo50 =
(source_id__h73617 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo500 =
(source_id__h63145 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo432 ;
assign _dfoo502 =
(source_id__h63145 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo434 ;
assign _dfoo504 =
(source_id__h63145 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo436 ;
assign _dfoo506 =
(source_id__h63145 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo438 ;
assign _dfoo508 =
(source_id__h63145 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo440 ;
assign _dfoo51 =
source_id__h73617 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo510 =
(source_id__h63145 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo442 ;
assign _dfoo512 =
(source_id__h63145 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo444 ;
assign _dfoo514 =
(source_id__h63145 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo446 ;
assign _dfoo516 =
(source_id__h63145 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo448 ;
assign _dfoo518 =
(source_id__h63145 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo450 ;
assign _dfoo52 =
(source_id__h73617 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo520 =
(source_id__h63145 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo452 ;
assign _dfoo522 =
(source_id__h63145 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo454 ;
assign _dfoo524 =
(source_id__h63145 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo456 ;
assign _dfoo526 =
(source_id__h63145 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo458 ;
assign _dfoo528 =
(source_id__h63145 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo460 ;
assign _dfoo53 =
source_id__h73617 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo530 =
(source_id__h63145 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo462 ;
assign _dfoo532 =
(source_id__h63145 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo464 ;
assign _dfoo534 =
(source_id__h63145 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo466 ;
assign _dfoo536 =
(source_id__h63145 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo468 ;
assign _dfoo538 =
(source_id__h63145 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo470 ;
assign _dfoo54 =
(source_id__h73617 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo540 =
(source_id__h63145 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo472 ;
assign _dfoo542 =
(source_id__h63145 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo474 ;
assign _dfoo544 =
(source_id__h63145 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298) ?
wdata32__h27246[23] :
_dfoo476 ;
assign _dfoo545 =
source_id__h61649 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo409 ;
assign _dfoo546 =
(source_id__h61649 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo478 ;
assign _dfoo547 =
source_id__h61649 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo411 ;
assign _dfoo548 =
(source_id__h61649 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo480 ;
assign _dfoo549 =
source_id__h61649 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo413 ;
assign _dfoo55 =
source_id__h73617 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo550 =
(source_id__h61649 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo482 ;
assign _dfoo551 =
source_id__h61649 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo415 ;
assign _dfoo552 =
(source_id__h61649 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo484 ;
assign _dfoo553 =
source_id__h61649 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo417 ;
assign _dfoo554 =
(source_id__h61649 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo486 ;
assign _dfoo555 =
source_id__h61649 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo419 ;
assign _dfoo556 =
(source_id__h61649 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo488 ;
assign _dfoo557 =
source_id__h61649 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo421 ;
assign _dfoo558 =
(source_id__h61649 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo490 ;
assign _dfoo559 =
source_id__h61649 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo423 ;
assign _dfoo56 =
(source_id__h73617 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo560 =
(source_id__h61649 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo492 ;
assign _dfoo561 =
source_id__h61649 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo425 ;
assign _dfoo562 =
(source_id__h61649 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo494 ;
assign _dfoo563 =
source_id__h61649 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo427 ;
assign _dfoo564 =
(source_id__h61649 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo496 ;
assign _dfoo565 =
source_id__h61649 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo429 ;
assign _dfoo566 =
(source_id__h61649 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo498 ;
assign _dfoo567 =
source_id__h61649 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo431 ;
assign _dfoo568 =
(source_id__h61649 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo500 ;
assign _dfoo569 =
source_id__h61649 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo433 ;
assign _dfoo57 =
source_id__h73617 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo570 =
(source_id__h61649 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo502 ;
assign _dfoo571 =
source_id__h61649 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo435 ;
assign _dfoo572 =
(source_id__h61649 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo504 ;
assign _dfoo573 =
source_id__h61649 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo437 ;
assign _dfoo574 =
(source_id__h61649 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo506 ;
assign _dfoo575 =
source_id__h61649 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo439 ;
assign _dfoo576 =
(source_id__h61649 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo508 ;
assign _dfoo577 =
source_id__h61649 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo441 ;
assign _dfoo578 =
(source_id__h61649 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo510 ;
assign _dfoo579 =
source_id__h61649 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo443 ;
assign _dfoo58 =
(source_id__h73617 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo580 =
(source_id__h61649 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo512 ;
assign _dfoo581 =
source_id__h61649 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo445 ;
assign _dfoo582 =
(source_id__h61649 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo514 ;
assign _dfoo583 =
source_id__h61649 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo447 ;
assign _dfoo584 =
(source_id__h61649 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo516 ;
assign _dfoo585 =
source_id__h61649 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo449 ;
assign _dfoo586 =
(source_id__h61649 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo518 ;
assign _dfoo587 =
source_id__h61649 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo451 ;
assign _dfoo588 =
(source_id__h61649 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo520 ;
assign _dfoo589 =
source_id__h61649 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo453 ;
assign _dfoo59 =
source_id__h73617 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo590 =
(source_id__h61649 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo522 ;
assign _dfoo591 =
source_id__h61649 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo455 ;
assign _dfoo592 =
(source_id__h61649 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo524 ;
assign _dfoo593 =
source_id__h61649 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo457 ;
assign _dfoo594 =
(source_id__h61649 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo526 ;
assign _dfoo595 =
source_id__h61649 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo459 ;
assign _dfoo596 =
(source_id__h61649 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo528 ;
assign _dfoo597 =
source_id__h61649 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo461 ;
assign _dfoo598 =
(source_id__h61649 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo530 ;
assign _dfoo599 =
source_id__h61649 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo463 ;
assign _dfoo6 =
(source_id__h73617 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo60 =
(source_id__h73617 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo600 =
(source_id__h61649 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo532 ;
assign _dfoo601 =
source_id__h61649 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo465 ;
assign _dfoo602 =
(source_id__h61649 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo534 ;
assign _dfoo603 =
source_id__h61649 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo467 ;
assign _dfoo604 =
(source_id__h61649 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo536 ;
assign _dfoo605 =
source_id__h61649 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo469 ;
assign _dfoo606 =
(source_id__h61649 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo538 ;
assign _dfoo607 =
source_id__h61649 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo471 ;
assign _dfoo608 =
(source_id__h61649 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo540 ;
assign _dfoo609 =
source_id__h61649 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo473 ;
assign _dfoo61 =
source_id__h73617 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo610 =
(source_id__h61649 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo542 ;
assign _dfoo611 =
source_id__h61649 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237 ||
source_id__h63145 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2298 ||
_dfoo475 ;
assign _dfoo612 =
(source_id__h61649 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2237) ?
wdata32__h27246[22] :
_dfoo544 ;
assign _dfoo614 =
(source_id__h60153 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo546 ;
assign _dfoo616 =
(source_id__h60153 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo548 ;
assign _dfoo618 =
(source_id__h60153 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo550 ;
assign _dfoo62 =
(source_id__h73617 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo620 =
(source_id__h60153 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo552 ;
assign _dfoo622 =
(source_id__h60153 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo554 ;
assign _dfoo624 =
(source_id__h60153 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo556 ;
assign _dfoo626 =
(source_id__h60153 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo558 ;
assign _dfoo628 =
(source_id__h60153 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo560 ;
assign _dfoo63 =
source_id__h73617 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo630 =
(source_id__h60153 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo562 ;
assign _dfoo632 =
(source_id__h60153 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo564 ;
assign _dfoo634 =
(source_id__h60153 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo566 ;
assign _dfoo636 =
(source_id__h60153 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo568 ;
assign _dfoo638 =
(source_id__h60153 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo570 ;
assign _dfoo64 =
(source_id__h73617 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo640 =
(source_id__h60153 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo572 ;
assign _dfoo642 =
(source_id__h60153 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo574 ;
assign _dfoo644 =
(source_id__h60153 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo576 ;
assign _dfoo646 =
(source_id__h60153 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo578 ;
assign _dfoo648 =
(source_id__h60153 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo580 ;
assign _dfoo65 =
source_id__h73617 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo650 =
(source_id__h60153 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo582 ;
assign _dfoo652 =
(source_id__h60153 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo584 ;
assign _dfoo654 =
(source_id__h60153 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo586 ;
assign _dfoo656 =
(source_id__h60153 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo588 ;
assign _dfoo658 =
(source_id__h60153 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo590 ;
assign _dfoo66 =
(source_id__h73617 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo660 =
(source_id__h60153 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo592 ;
assign _dfoo662 =
(source_id__h60153 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo594 ;
assign _dfoo664 =
(source_id__h60153 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo596 ;
assign _dfoo666 =
(source_id__h60153 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo598 ;
assign _dfoo668 =
(source_id__h60153 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo600 ;
assign _dfoo67 =
source_id__h73617 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo670 =
(source_id__h60153 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo602 ;
assign _dfoo672 =
(source_id__h60153 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo604 ;
assign _dfoo674 =
(source_id__h60153 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo606 ;
assign _dfoo676 =
(source_id__h60153 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo608 ;
assign _dfoo678 =
(source_id__h60153 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo610 ;
assign _dfoo68 =
(source_id__h73617 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo680 =
(source_id__h60153 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176) ?
wdata32__h27246[21] :
_dfoo612 ;
assign _dfoo681 =
source_id__h58657 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo545 ;
assign _dfoo682 =
(source_id__h58657 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo614 ;
assign _dfoo683 =
source_id__h58657 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo547 ;
assign _dfoo684 =
(source_id__h58657 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo616 ;
assign _dfoo685 =
source_id__h58657 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo549 ;
assign _dfoo686 =
(source_id__h58657 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo618 ;
assign _dfoo687 =
source_id__h58657 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo551 ;
assign _dfoo688 =
(source_id__h58657 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo620 ;
assign _dfoo689 =
source_id__h58657 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo553 ;
assign _dfoo690 =
(source_id__h58657 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo622 ;
assign _dfoo691 =
source_id__h58657 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo555 ;
assign _dfoo692 =
(source_id__h58657 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo624 ;
assign _dfoo693 =
source_id__h58657 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo557 ;
assign _dfoo694 =
(source_id__h58657 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo626 ;
assign _dfoo695 =
source_id__h58657 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo559 ;
assign _dfoo696 =
(source_id__h58657 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo628 ;
assign _dfoo697 =
source_id__h58657 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo561 ;
assign _dfoo698 =
(source_id__h58657 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo630 ;
assign _dfoo699 =
source_id__h58657 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo563 ;
assign _dfoo7 =
source_id__h73617 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo70 =
(source_id__h72121 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo2 ;
assign _dfoo700 =
(source_id__h58657 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo632 ;
assign _dfoo701 =
source_id__h58657 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo565 ;
assign _dfoo702 =
(source_id__h58657 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo634 ;
assign _dfoo703 =
source_id__h58657 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo567 ;
assign _dfoo704 =
(source_id__h58657 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo636 ;
assign _dfoo705 =
source_id__h58657 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo569 ;
assign _dfoo706 =
(source_id__h58657 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo638 ;
assign _dfoo707 =
source_id__h58657 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo571 ;
assign _dfoo708 =
(source_id__h58657 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo640 ;
assign _dfoo709 =
source_id__h58657 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo573 ;
assign _dfoo710 =
(source_id__h58657 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo642 ;
assign _dfoo711 =
source_id__h58657 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo575 ;
assign _dfoo712 =
(source_id__h58657 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo644 ;
assign _dfoo713 =
source_id__h58657 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo577 ;
assign _dfoo714 =
(source_id__h58657 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo646 ;
assign _dfoo715 =
source_id__h58657 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo579 ;
assign _dfoo716 =
(source_id__h58657 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo648 ;
assign _dfoo717 =
source_id__h58657 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo581 ;
assign _dfoo718 =
(source_id__h58657 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo650 ;
assign _dfoo719 =
source_id__h58657 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo583 ;
assign _dfoo72 =
(source_id__h72121 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo4 ;
assign _dfoo720 =
(source_id__h58657 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo652 ;
assign _dfoo721 =
source_id__h58657 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo585 ;
assign _dfoo722 =
(source_id__h58657 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo654 ;
assign _dfoo723 =
source_id__h58657 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo587 ;
assign _dfoo724 =
(source_id__h58657 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo656 ;
assign _dfoo725 =
source_id__h58657 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo589 ;
assign _dfoo726 =
(source_id__h58657 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo658 ;
assign _dfoo727 =
source_id__h58657 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo591 ;
assign _dfoo728 =
(source_id__h58657 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo660 ;
assign _dfoo729 =
source_id__h58657 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo593 ;
assign _dfoo730 =
(source_id__h58657 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo662 ;
assign _dfoo731 =
source_id__h58657 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo595 ;
assign _dfoo732 =
(source_id__h58657 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo664 ;
assign _dfoo733 =
source_id__h58657 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo597 ;
assign _dfoo734 =
(source_id__h58657 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo666 ;
assign _dfoo735 =
source_id__h58657 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo599 ;
assign _dfoo736 =
(source_id__h58657 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo668 ;
assign _dfoo737 =
source_id__h58657 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo601 ;
assign _dfoo738 =
(source_id__h58657 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo670 ;
assign _dfoo739 =
source_id__h58657 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo603 ;
assign _dfoo74 =
(source_id__h72121 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo6 ;
assign _dfoo740 =
(source_id__h58657 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo672 ;
assign _dfoo741 =
source_id__h58657 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo605 ;
assign _dfoo742 =
(source_id__h58657 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo674 ;
assign _dfoo743 =
source_id__h58657 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo607 ;
assign _dfoo744 =
(source_id__h58657 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo676 ;
assign _dfoo745 =
source_id__h58657 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo609 ;
assign _dfoo746 =
(source_id__h58657 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo678 ;
assign _dfoo747 =
source_id__h58657 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115 ||
source_id__h60153 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2176 ||
_dfoo611 ;
assign _dfoo748 =
(source_id__h58657 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2115) ?
wdata32__h27246[20] :
_dfoo680 ;
assign _dfoo750 =
(source_id__h57161 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo682 ;
assign _dfoo752 =
(source_id__h57161 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo684 ;
assign _dfoo754 =
(source_id__h57161 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo686 ;
assign _dfoo756 =
(source_id__h57161 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo688 ;
assign _dfoo758 =
(source_id__h57161 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo690 ;
assign _dfoo76 =
(source_id__h72121 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo8 ;
assign _dfoo760 =
(source_id__h57161 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo692 ;
assign _dfoo762 =
(source_id__h57161 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo694 ;
assign _dfoo764 =
(source_id__h57161 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo696 ;
assign _dfoo766 =
(source_id__h57161 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo698 ;
assign _dfoo768 =
(source_id__h57161 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo700 ;
assign _dfoo770 =
(source_id__h57161 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo702 ;
assign _dfoo772 =
(source_id__h57161 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo704 ;
assign _dfoo774 =
(source_id__h57161 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo706 ;
assign _dfoo776 =
(source_id__h57161 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo708 ;
assign _dfoo778 =
(source_id__h57161 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo710 ;
assign _dfoo78 =
(source_id__h72121 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo10 ;
assign _dfoo780 =
(source_id__h57161 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo712 ;
assign _dfoo782 =
(source_id__h57161 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo714 ;
assign _dfoo784 =
(source_id__h57161 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo716 ;
assign _dfoo786 =
(source_id__h57161 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo718 ;
assign _dfoo788 =
(source_id__h57161 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo720 ;
assign _dfoo790 =
(source_id__h57161 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo722 ;
assign _dfoo792 =
(source_id__h57161 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo724 ;
assign _dfoo794 =
(source_id__h57161 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo726 ;
assign _dfoo796 =
(source_id__h57161 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo728 ;
assign _dfoo798 =
(source_id__h57161 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo730 ;
assign _dfoo8 =
(source_id__h73617 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725) ?
wdata32__h27246[30] :
wdata32__h27246[31] ;
assign _dfoo80 =
(source_id__h72121 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo12 ;
assign _dfoo800 =
(source_id__h57161 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo732 ;
assign _dfoo802 =
(source_id__h57161 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo734 ;
assign _dfoo804 =
(source_id__h57161 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo736 ;
assign _dfoo806 =
(source_id__h57161 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo738 ;
assign _dfoo808 =
(source_id__h57161 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo740 ;
assign _dfoo810 =
(source_id__h57161 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo742 ;
assign _dfoo812 =
(source_id__h57161 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo744 ;
assign _dfoo814 =
(source_id__h57161 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo746 ;
assign _dfoo816 =
(source_id__h57161 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054) ?
wdata32__h27246[19] :
_dfoo748 ;
assign _dfoo817 =
source_id__h55665 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo681 ;
assign _dfoo818 =
(source_id__h55665 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo750 ;
assign _dfoo819 =
source_id__h55665 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo683 ;
assign _dfoo82 =
(source_id__h72121 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo14 ;
assign _dfoo820 =
(source_id__h55665 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo752 ;
assign _dfoo821 =
source_id__h55665 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo685 ;
assign _dfoo822 =
(source_id__h55665 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo754 ;
assign _dfoo823 =
source_id__h55665 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo687 ;
assign _dfoo824 =
(source_id__h55665 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo756 ;
assign _dfoo825 =
source_id__h55665 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo689 ;
assign _dfoo826 =
(source_id__h55665 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo758 ;
assign _dfoo827 =
source_id__h55665 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo691 ;
assign _dfoo828 =
(source_id__h55665 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo760 ;
assign _dfoo829 =
source_id__h55665 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo693 ;
assign _dfoo830 =
(source_id__h55665 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo762 ;
assign _dfoo831 =
source_id__h55665 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo695 ;
assign _dfoo832 =
(source_id__h55665 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo764 ;
assign _dfoo833 =
source_id__h55665 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo697 ;
assign _dfoo834 =
(source_id__h55665 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo766 ;
assign _dfoo835 =
source_id__h55665 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo699 ;
assign _dfoo836 =
(source_id__h55665 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo768 ;
assign _dfoo837 =
source_id__h55665 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo701 ;
assign _dfoo838 =
(source_id__h55665 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo770 ;
assign _dfoo839 =
source_id__h55665 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo703 ;
assign _dfoo84 =
(source_id__h72121 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo16 ;
assign _dfoo840 =
(source_id__h55665 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo772 ;
assign _dfoo841 =
source_id__h55665 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo705 ;
assign _dfoo842 =
(source_id__h55665 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo774 ;
assign _dfoo843 =
source_id__h55665 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo707 ;
assign _dfoo844 =
(source_id__h55665 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo776 ;
assign _dfoo845 =
source_id__h55665 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo709 ;
assign _dfoo846 =
(source_id__h55665 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo778 ;
assign _dfoo847 =
source_id__h55665 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo711 ;
assign _dfoo848 =
(source_id__h55665 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo780 ;
assign _dfoo849 =
source_id__h55665 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo713 ;
assign _dfoo850 =
(source_id__h55665 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo782 ;
assign _dfoo851 =
source_id__h55665 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo715 ;
assign _dfoo852 =
(source_id__h55665 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo784 ;
assign _dfoo853 =
source_id__h55665 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo717 ;
assign _dfoo854 =
(source_id__h55665 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo786 ;
assign _dfoo855 =
source_id__h55665 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo719 ;
assign _dfoo856 =
(source_id__h55665 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo788 ;
assign _dfoo857 =
source_id__h55665 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo721 ;
assign _dfoo858 =
(source_id__h55665 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo790 ;
assign _dfoo859 =
source_id__h55665 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo723 ;
assign _dfoo86 =
(source_id__h72121 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo18 ;
assign _dfoo860 =
(source_id__h55665 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo792 ;
assign _dfoo861 =
source_id__h55665 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo725 ;
assign _dfoo862 =
(source_id__h55665 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo794 ;
assign _dfoo863 =
source_id__h55665 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo727 ;
assign _dfoo864 =
(source_id__h55665 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo796 ;
assign _dfoo865 =
source_id__h55665 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo729 ;
assign _dfoo866 =
(source_id__h55665 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo798 ;
assign _dfoo867 =
source_id__h55665 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo731 ;
assign _dfoo868 =
(source_id__h55665 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo800 ;
assign _dfoo869 =
source_id__h55665 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo733 ;
assign _dfoo870 =
(source_id__h55665 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo802 ;
assign _dfoo871 =
source_id__h55665 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo735 ;
assign _dfoo872 =
(source_id__h55665 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo804 ;
assign _dfoo873 =
source_id__h55665 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo737 ;
assign _dfoo874 =
(source_id__h55665 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo806 ;
assign _dfoo875 =
source_id__h55665 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo739 ;
assign _dfoo876 =
(source_id__h55665 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo808 ;
assign _dfoo877 =
source_id__h55665 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo741 ;
assign _dfoo878 =
(source_id__h55665 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo810 ;
assign _dfoo879 =
source_id__h55665 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo743 ;
assign _dfoo88 =
(source_id__h72121 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo20 ;
assign _dfoo880 =
(source_id__h55665 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo812 ;
assign _dfoo881 =
source_id__h55665 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo745 ;
assign _dfoo882 =
(source_id__h55665 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo814 ;
assign _dfoo883 =
source_id__h55665 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993 ||
source_id__h57161 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2054 ||
_dfoo747 ;
assign _dfoo884 =
(source_id__h55665 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1993) ?
wdata32__h27246[18] :
_dfoo816 ;
assign _dfoo886 =
(source_id__h54169 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo818 ;
assign _dfoo888 =
(source_id__h54169 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo820 ;
assign _dfoo890 =
(source_id__h54169 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo822 ;
assign _dfoo892 =
(source_id__h54169 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo824 ;
assign _dfoo894 =
(source_id__h54169 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo826 ;
assign _dfoo896 =
(source_id__h54169 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo828 ;
assign _dfoo898 =
(source_id__h54169 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo830 ;
assign _dfoo9 =
source_id__h73617 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2725 ||
source_id__h75113 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2786 ;
assign _dfoo90 =
(source_id__h72121 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo22 ;
assign _dfoo900 =
(source_id__h54169 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo832 ;
assign _dfoo902 =
(source_id__h54169 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo834 ;
assign _dfoo904 =
(source_id__h54169 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo836 ;
assign _dfoo906 =
(source_id__h54169 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo838 ;
assign _dfoo908 =
(source_id__h54169 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo840 ;
assign _dfoo910 =
(source_id__h54169 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo842 ;
assign _dfoo912 =
(source_id__h54169 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo844 ;
assign _dfoo914 =
(source_id__h54169 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo846 ;
assign _dfoo916 =
(source_id__h54169 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo848 ;
assign _dfoo918 =
(source_id__h54169 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo850 ;
assign _dfoo92 =
(source_id__h72121 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo24 ;
assign _dfoo920 =
(source_id__h54169 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo852 ;
assign _dfoo922 =
(source_id__h54169 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo854 ;
assign _dfoo924 =
(source_id__h54169 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo856 ;
assign _dfoo926 =
(source_id__h54169 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo858 ;
assign _dfoo928 =
(source_id__h54169 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo860 ;
assign _dfoo930 =
(source_id__h54169 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo862 ;
assign _dfoo932 =
(source_id__h54169 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo864 ;
assign _dfoo934 =
(source_id__h54169 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo866 ;
assign _dfoo936 =
(source_id__h54169 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo868 ;
assign _dfoo938 =
(source_id__h54169 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo870 ;
assign _dfoo94 =
(source_id__h72121 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo26 ;
assign _dfoo940 =
(source_id__h54169 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo872 ;
assign _dfoo942 =
(source_id__h54169 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo874 ;
assign _dfoo944 =
(source_id__h54169 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo876 ;
assign _dfoo946 =
(source_id__h54169 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo878 ;
assign _dfoo948 =
(source_id__h54169 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo880 ;
assign _dfoo950 =
(source_id__h54169 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo882 ;
assign _dfoo952 =
(source_id__h54169 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932) ?
wdata32__h27246[17] :
_dfoo884 ;
assign _dfoo953 =
source_id__h52673 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo817 ;
assign _dfoo954 =
(source_id__h52673 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo886 ;
assign _dfoo955 =
source_id__h52673 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo819 ;
assign _dfoo956 =
(source_id__h52673 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo888 ;
assign _dfoo957 =
source_id__h52673 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo821 ;
assign _dfoo958 =
(source_id__h52673 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo890 ;
assign _dfoo959 =
source_id__h52673 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo823 ;
assign _dfoo96 =
(source_id__h72121 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo28 ;
assign _dfoo960 =
(source_id__h52673 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo892 ;
assign _dfoo961 =
source_id__h52673 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo825 ;
assign _dfoo962 =
(source_id__h52673 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo894 ;
assign _dfoo963 =
source_id__h52673 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo827 ;
assign _dfoo964 =
(source_id__h52673 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo896 ;
assign _dfoo965 =
source_id__h52673 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo829 ;
assign _dfoo966 =
(source_id__h52673 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo898 ;
assign _dfoo967 =
source_id__h52673 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo831 ;
assign _dfoo968 =
(source_id__h52673 == 10'd9 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo900 ;
assign _dfoo969 =
source_id__h52673 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo833 ;
assign _dfoo970 =
(source_id__h52673 == 10'd8 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo902 ;
assign _dfoo971 =
source_id__h52673 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo835 ;
assign _dfoo972 =
(source_id__h52673 == 10'd7 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo904 ;
assign _dfoo973 =
source_id__h52673 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo837 ;
assign _dfoo974 =
(source_id__h52673 == 10'd6 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo906 ;
assign _dfoo975 =
source_id__h52673 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo839 ;
assign _dfoo976 =
(source_id__h52673 == 10'd5 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo908 ;
assign _dfoo977 =
source_id__h52673 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo841 ;
assign _dfoo978 =
(source_id__h52673 == 10'd4 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo910 ;
assign _dfoo979 =
source_id__h52673 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo843 ;
assign _dfoo98 =
(source_id__h72121 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2664) ?
wdata32__h27246[29] :
_dfoo30 ;
assign _dfoo980 =
(source_id__h52673 == 10'd3 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo912 ;
assign _dfoo981 =
source_id__h52673 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo845 ;
assign _dfoo982 =
(source_id__h52673 == 10'd2 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo914 ;
assign _dfoo983 =
source_id__h52673 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo847 ;
assign _dfoo984 =
(source_id__h52673 == 10'd1 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo916 ;
assign _dfoo985 =
source_id__h52673 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo849 ;
assign _dfoo986 =
(source_id__h52673 == 10'd0 &&
addr_offset__h27245[11:7] == 5'd1 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo918 ;
assign _dfoo987 =
source_id__h52673 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo851 ;
assign _dfoo988 =
(source_id__h52673 == 10'd16 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo920 ;
assign _dfoo989 =
source_id__h52673 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo853 ;
assign _dfoo990 =
(source_id__h52673 == 10'd15 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo922 ;
assign _dfoo991 =
source_id__h52673 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo855 ;
assign _dfoo992 =
(source_id__h52673 == 10'd14 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo924 ;
assign _dfoo993 =
source_id__h52673 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo857 ;
assign _dfoo994 =
(source_id__h52673 == 10'd13 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo926 ;
assign _dfoo995 =
source_id__h52673 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo859 ;
assign _dfoo996 =
(source_id__h52673 == 10'd12 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo928 ;
assign _dfoo997 =
source_id__h52673 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo861 ;
assign _dfoo998 =
(source_id__h52673 == 10'd11 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871) ?
wdata32__h27246[16] :
_dfoo930 ;
assign _dfoo999 =
source_id__h52673 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1871 ||
source_id__h54169 == 10'd10 &&
addr_offset__h27245[11:7] == 5'd0 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d1932 ||
_dfoo863 ;
assign a__h81740 =
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3066 ?
m_vrg_source_prio_16 :
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3062 ;
assign a__h83894 =
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3160 ?
m_vrg_source_prio_16 :
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3156 ;
assign addr_offset__h13465 =
m_slave_xactor_f_rd_addr$D_OUT[92:29] - m_rg_addr_base ;
assign addr_offset__h27245 =
m_slave_xactor_f_wr_addr$D_OUT[92:29] - m_rg_addr_base ;
assign b__h81741 =
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3066 ?
5'd16 :
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3082 ;
assign b__h83895 =
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3160 ?
5'd16 :
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3176 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240 =
addr_offset__h13465 < 64'h0000000000003000 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242 =
addr_offset__h13465[11:7] <= 5'd1 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 =
m_slave_xactor_f_rd_addr$D_OUT[92:29] < m_rg_addr_base ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 =
addr_offset__h13465 < 64'h0000000000001000 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 =
addr_offset__h13465[11:2] <= 10'd16 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
addr_offset__h13465[11:2] != 10'd0 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40 &&
m_cfg_verbosity != 4'd0 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 =
addr_offset__h13465[16:12] <= 5'd1 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 =
addr_offset__h13465 < 64'h0000000000002000 ;
assign m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 =
source_id_base__h13893 <= 10'd16 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 =
addr_offset__h27245[16:12] <= 5'd1 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2860 =
addr_offset__h27245[16:12] == 5'd0 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2857 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2862 =
addr_offset__h27245[16:12] == 5'd1 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2857 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 =
m_slave_xactor_f_wr_addr$D_OUT[92:29] < m_rg_addr_base ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 =
addr_offset__h27245 < 64'h0000000000001000 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 =
addr_offset__h27245[11:2] <= 10'd16 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d837 =
addr_offset__h27245[11:2] == 10'd1 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d839 =
addr_offset__h27245[11:2] == 10'd2 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d841 =
addr_offset__h27245[11:2] == 10'd3 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d843 =
addr_offset__h27245[11:2] == 10'd4 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d845 =
addr_offset__h27245[11:2] == 10'd5 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d847 =
addr_offset__h27245[11:2] == 10'd6 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d849 =
addr_offset__h27245[11:2] == 10'd7 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d851 =
addr_offset__h27245[11:2] == 10'd8 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d853 =
addr_offset__h27245[11:2] == 10'd9 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d855 =
addr_offset__h27245[11:2] == 10'd10 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d857 =
addr_offset__h27245[11:2] == 10'd11 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d859 =
addr_offset__h27245[11:2] == 10'd12 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d861 =
addr_offset__h27245[11:2] == 10'd13 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d863 =
addr_offset__h27245[11:2] == 10'd14 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d865 =
addr_offset__h27245[11:2] == 10'd15 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d867 =
addr_offset__h27245[11:2] == 10'd16 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d869 =
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
addr_offset__h27245[11:2] != 10'd0 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823 &&
m_cfg_verbosity != 4'd0 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 =
addr_offset__h27245 < 64'h0000000000002000 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 =
source_id_base__h28620 <= 10'd16 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888 =
addr_offset__h27245 < 64'h0000000000003000 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889 =
addr_offset__h27245[11:7] <= 5'd1 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d895 =
addr_offset__h27245[11:7] == 5'd0 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d892 ;
assign m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d931 =
addr_offset__h27245[11:7] == 5'd1 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d892 ;
assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3036 =
m_vrg_source_ip_10 &&
m_vrg_source_prio_10 >
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3032 &&
m_vvrg_ie_0_10 ;
assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d3130 =
m_vrg_source_ip_10 &&
m_vrg_source_prio_10 >
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d3126 &&
m_vvrg_ie_1_10 ;
assign m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 =
m_vrg_source_ip_10 &&
m_vrg_source_prio_10 >
IF_m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_sou_ETC___d608 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 ;
assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3041 =
m_vrg_source_ip_11 &&
m_vrg_source_prio_11 >
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3037 &&
m_vvrg_ie_0_11 ;
assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d3135 =
m_vrg_source_ip_11 &&
m_vrg_source_prio_11 >
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d3131 &&
m_vvrg_ie_1_11 ;
assign m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 =
m_vrg_source_ip_11 &&
m_vrg_source_prio_11 >
IF_m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_so_ETC___d615 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 ;
assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3046 =
m_vrg_source_ip_12 &&
m_vrg_source_prio_12 >
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3042 &&
m_vvrg_ie_0_12 ;
assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d3140 =
m_vrg_source_ip_12 &&
m_vrg_source_prio_12 >
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d3136 &&
m_vvrg_ie_1_12 ;
assign m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 =
m_vrg_source_ip_12 &&
m_vrg_source_prio_12 >
IF_m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_so_ETC___d622 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 ;
assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3051 =
m_vrg_source_ip_13 &&
m_vrg_source_prio_13 >
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3047 &&
m_vvrg_ie_0_13 ;
assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d3145 =
m_vrg_source_ip_13 &&
m_vrg_source_prio_13 >
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d3141 &&
m_vvrg_ie_1_13 ;
assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 =
m_vrg_source_ip_13 &&
m_vrg_source_prio_13 >
IF_m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_so_ETC___d629 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 ;
assign m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d686 =
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d635 ||
m_vrg_source_ip_12_read__2_AND_NOT_m_vrg_sourc_ETC___d628 ||
m_vrg_source_ip_11_read__1_AND_NOT_m_vrg_sourc_ETC___d621 ||
m_vrg_source_ip_10_read__0_AND_NOT_m_vrg_sourc_ETC___d614 ||
m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 ||
m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 ||
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d680 ;
assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3056 =
m_vrg_source_ip_14 &&
m_vrg_source_prio_14 >
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3052 &&
m_vvrg_ie_0_14 ;
assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d3150 =
m_vrg_source_ip_14 &&
m_vrg_source_prio_14 >
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d3146 &&
m_vvrg_ie_1_14 ;
assign m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 =
m_vrg_source_ip_14 &&
m_vrg_source_prio_14 >
IF_m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_so_ETC___d636 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 ;
assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3061 =
m_vrg_source_ip_15 &&
m_vrg_source_prio_15 >
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3057 &&
m_vvrg_ie_0_15 ;
assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d3155 =
m_vrg_source_ip_15 &&
m_vrg_source_prio_15 >
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d3151 &&
m_vvrg_ie_1_15 ;
assign m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 =
m_vrg_source_ip_15 &&
m_vrg_source_prio_15 >
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 ;
assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3066 =
m_vrg_source_ip_16 &&
m_vrg_source_prio_16 >
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3062 &&
m_vvrg_ie_0_16 ;
assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d3160 =
m_vrg_source_ip_16 &&
m_vrg_source_prio_16 >
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d3156 &&
m_vvrg_ie_1_16 ;
assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 =
m_vrg_source_ip_16 &&
!m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 ;
assign m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d689 =
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 ||
m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ||
m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_sourc_ETC___d642 ||
m_vrg_source_ip_13_read__3_AND_NOT_m_vrg_sourc_ETC___d686 ;
assign m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 =
m_vrg_source_ip_1 && m_vrg_source_prio_1 != 3'd0 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 ;
assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d2996 =
m_vrg_source_ip_2 &&
m_vrg_source_prio_2 >
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d2992 &&
m_vvrg_ie_0_2 ;
assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d3090 =
m_vrg_source_ip_2 &&
m_vrg_source_prio_2 >
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d3086 &&
m_vvrg_ie_1_2 ;
assign m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 =
m_vrg_source_ip_2 &&
m_vrg_source_prio_2 >
IF_m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_sou_ETC___d552 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 ;
assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3001 =
m_vrg_source_ip_3 &&
m_vrg_source_prio_3 >
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d2997 &&
m_vvrg_ie_0_3 ;
assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d3095 =
m_vrg_source_ip_3 &&
m_vrg_source_prio_3 >
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d3091 &&
m_vvrg_ie_1_3 ;
assign m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 =
m_vrg_source_ip_3 &&
m_vrg_source_prio_3 >
IF_m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_sou_ETC___d559 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 ;
assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3006 =
m_vrg_source_ip_4 &&
m_vrg_source_prio_4 >
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3002 &&
m_vvrg_ie_0_4 ;
assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d3100 =
m_vrg_source_ip_4 &&
m_vrg_source_prio_4 >
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d3096 &&
m_vvrg_ie_1_4 ;
assign m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 =
m_vrg_source_ip_4 &&
m_vrg_source_prio_4 >
IF_m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_sou_ETC___d566 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 ;
assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3011 =
m_vrg_source_ip_5 &&
m_vrg_source_prio_5 >
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3007 &&
m_vvrg_ie_0_5 ;
assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d3105 =
m_vrg_source_ip_5 &&
m_vrg_source_prio_5 >
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d3101 &&
m_vvrg_ie_1_5 ;
assign m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 =
m_vrg_source_ip_5 &&
m_vrg_source_prio_5 >
IF_m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_sou_ETC___d573 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 ;
assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3016 =
m_vrg_source_ip_6 &&
m_vrg_source_prio_6 >
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3012 &&
m_vvrg_ie_0_6 ;
assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d3110 =
m_vrg_source_ip_6 &&
m_vrg_source_prio_6 >
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d3106 &&
m_vvrg_ie_1_6 ;
assign m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 =
m_vrg_source_ip_6 &&
m_vrg_source_prio_6 >
IF_m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_sou_ETC___d580 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 ;
assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3021 =
m_vrg_source_ip_7 &&
m_vrg_source_prio_7 >
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3017 &&
m_vvrg_ie_0_7 ;
assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d3115 =
m_vrg_source_ip_7 &&
m_vrg_source_prio_7 >
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d3111 &&
m_vvrg_ie_1_7 ;
assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 =
m_vrg_source_ip_7 &&
m_vrg_source_prio_7 >
IF_m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_sou_ETC___d587 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 ;
assign m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d680 =
m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_source_ETC___d593 ||
m_vrg_source_ip_6_read__6_AND_NOT_m_vrg_source_ETC___d586 ||
m_vrg_source_ip_5_read__5_AND_NOT_m_vrg_source_ETC___d579 ||
m_vrg_source_ip_4_read__4_AND_NOT_m_vrg_source_ETC___d572 ||
m_vrg_source_ip_3_read__3_AND_NOT_m_vrg_source_ETC___d565 ||
m_vrg_source_ip_2_read__2_AND_NOT_m_vrg_source_ETC___d558 ||
m_vrg_source_ip_1_read__1_AND_NOT_m_vrg_source_ETC___d551 ;
assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3026 =
m_vrg_source_ip_8 &&
m_vrg_source_prio_8 >
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3022 &&
m_vvrg_ie_0_8 ;
assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d3120 =
m_vrg_source_ip_8 &&
m_vrg_source_prio_8 >
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d3116 &&
m_vvrg_ie_1_8 ;
assign m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_source_ETC___d600 =
m_vrg_source_ip_8 &&
m_vrg_source_prio_8 >
IF_m_vrg_source_ip_7_read__7_AND_NOT_m_vrg_sou_ETC___d594 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 ;
assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3031 =
m_vrg_source_ip_9 &&
m_vrg_source_prio_9 >
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3027 &&
m_vvrg_ie_0_9 ;
assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d3125 =
m_vrg_source_ip_9 &&
m_vrg_source_prio_9 >
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d3121 &&
m_vvrg_ie_1_9 ;
assign m_vrg_source_ip_9_read__9_AND_NOT_m_vrg_source_ETC___d607 =
m_vrg_source_ip_9 &&
m_vrg_source_prio_9 >
IF_m_vrg_source_ip_8_read__8_AND_NOT_m_vrg_sou_ETC___d601 &&
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 ;
assign m_vrg_source_prio_16_3_ULE_IF_m_vrg_source_ip__ETC___d651 =
m_vrg_source_prio_16 <=
(m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_sourc_ETC___d649 ?
m_vrg_source_prio_15 :
IF_m_vrg_source_ip_14_read__4_AND_NOT_m_vrg_so_ETC___d643) ;
assign max_id__h24210 =
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d656 ?
5'd16 :
IF_m_vrg_source_ip_15_read__5_AND_NOT_m_vrg_so_ETC___d671 ;
assign rdata___1__h26714 = { rdata__h26520[31:0], 32'h0 } ;
assign rdata__h26520 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ?
64'd0 :
y_avValue_fst__h26512 ;
assign rresp__h26521 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ?
2'b11 :
y_avValue_snd__h26513 ;
assign source_id__h15937 = { addr_offset__h13465[4:0], 5'd31 } ;
assign source_id__h16044 = { addr_offset__h13465[4:0], 5'd30 } ;
assign source_id__h16117 = { addr_offset__h13465[4:0], 5'd29 } ;
assign source_id__h16190 = { addr_offset__h13465[4:0], 5'd28 } ;
assign source_id__h16263 = { addr_offset__h13465[4:0], 5'd27 } ;
assign source_id__h16336 = { addr_offset__h13465[4:0], 5'd26 } ;
assign source_id__h16409 = { addr_offset__h13465[4:0], 5'd25 } ;
assign source_id__h16482 = { addr_offset__h13465[4:0], 5'd24 } ;
assign source_id__h16555 = { addr_offset__h13465[4:0], 5'd23 } ;
assign source_id__h16628 = { addr_offset__h13465[4:0], 5'd22 } ;
assign source_id__h16701 = { addr_offset__h13465[4:0], 5'd21 } ;
assign source_id__h16774 = { addr_offset__h13465[4:0], 5'd20 } ;
assign source_id__h16847 = { addr_offset__h13465[4:0], 5'd19 } ;
assign source_id__h16920 = { addr_offset__h13465[4:0], 5'd18 } ;
assign source_id__h16993 = { addr_offset__h13465[4:0], 5'd17 } ;
assign source_id__h17066 = { addr_offset__h13465[4:0], 5'd16 } ;
assign source_id__h17139 = { addr_offset__h13465[4:0], 5'd15 } ;
assign source_id__h17212 = { addr_offset__h13465[4:0], 5'd14 } ;
assign source_id__h17285 = { addr_offset__h13465[4:0], 5'd13 } ;
assign source_id__h17358 = { addr_offset__h13465[4:0], 5'd12 } ;
assign source_id__h17431 = { addr_offset__h13465[4:0], 5'd11 } ;
assign source_id__h17504 = { addr_offset__h13465[4:0], 5'd10 } ;
assign source_id__h17577 = { addr_offset__h13465[4:0], 5'd9 } ;
assign source_id__h17650 = { addr_offset__h13465[4:0], 5'd8 } ;
assign source_id__h17723 = { addr_offset__h13465[4:0], 5'd7 } ;
assign source_id__h17796 = { addr_offset__h13465[4:0], 5'd6 } ;
assign source_id__h17869 = { addr_offset__h13465[4:0], 5'd5 } ;
assign source_id__h17942 = { addr_offset__h13465[4:0], 5'd4 } ;
assign source_id__h18015 = { addr_offset__h13465[4:0], 5'd3 } ;
assign source_id__h18088 = { addr_offset__h13465[4:0], 5'd2 } ;
assign source_id__h18161 = { addr_offset__h13465[4:0], 5'd1 } ;
assign source_id__h20405 = 10'd31 + source_id_base__h13893 ;
assign source_id__h20581 = 10'd30 + source_id_base__h13893 ;
assign source_id__h20689 = 10'd29 + source_id_base__h13893 ;
assign source_id__h20797 = 10'd28 + source_id_base__h13893 ;
assign source_id__h20905 = 10'd27 + source_id_base__h13893 ;
assign source_id__h21013 = 10'd26 + source_id_base__h13893 ;
assign source_id__h21121 = 10'd25 + source_id_base__h13893 ;
assign source_id__h21229 = 10'd24 + source_id_base__h13893 ;
assign source_id__h21337 = 10'd23 + source_id_base__h13893 ;
assign source_id__h21445 = 10'd22 + source_id_base__h13893 ;
assign source_id__h21553 = 10'd21 + source_id_base__h13893 ;
assign source_id__h21661 = 10'd20 + source_id_base__h13893 ;
assign source_id__h21769 = 10'd19 + source_id_base__h13893 ;
assign source_id__h21877 = 10'd18 + source_id_base__h13893 ;
assign source_id__h21985 = 10'd17 + source_id_base__h13893 ;
assign source_id__h22093 = 10'd16 + source_id_base__h13893 ;
assign source_id__h22201 = 10'd15 + source_id_base__h13893 ;
assign source_id__h22309 = 10'd14 + source_id_base__h13893 ;
assign source_id__h22417 = 10'd13 + source_id_base__h13893 ;
assign source_id__h22525 = 10'd12 + source_id_base__h13893 ;
assign source_id__h22633 = 10'd11 + source_id_base__h13893 ;
assign source_id__h22741 = 10'd10 + source_id_base__h13893 ;
assign source_id__h22849 = 10'd9 + source_id_base__h13893 ;
assign source_id__h22957 = 10'd8 + source_id_base__h13893 ;
assign source_id__h23065 = 10'd7 + source_id_base__h13893 ;
assign source_id__h23173 = 10'd6 + source_id_base__h13893 ;
assign source_id__h23281 = 10'd5 + source_id_base__h13893 ;
assign source_id__h23389 = 10'd4 + source_id_base__h13893 ;
assign source_id__h23497 = 10'd3 + source_id_base__h13893 ;
assign source_id__h23605 = 10'd2 + source_id_base__h13893 ;
assign source_id__h23713 = 10'd1 + source_id_base__h13893 ;
assign source_id__h30233 = { addr_offset__h27245[4:0], 5'd1 } ;
assign source_id__h31729 = { addr_offset__h27245[4:0], 5'd2 } ;
assign source_id__h33225 = { addr_offset__h27245[4:0], 5'd3 } ;
assign source_id__h34721 = { addr_offset__h27245[4:0], 5'd4 } ;
assign source_id__h36217 = { addr_offset__h27245[4:0], 5'd5 } ;
assign source_id__h37713 = { addr_offset__h27245[4:0], 5'd6 } ;
assign source_id__h39209 = { addr_offset__h27245[4:0], 5'd7 } ;
assign source_id__h40705 = { addr_offset__h27245[4:0], 5'd8 } ;
assign source_id__h42201 = { addr_offset__h27245[4:0], 5'd9 } ;
assign source_id__h43697 = { addr_offset__h27245[4:0], 5'd10 } ;
assign source_id__h45193 = { addr_offset__h27245[4:0], 5'd11 } ;
assign source_id__h46689 = { addr_offset__h27245[4:0], 5'd12 } ;
assign source_id__h48185 = { addr_offset__h27245[4:0], 5'd13 } ;
assign source_id__h49681 = { addr_offset__h27245[4:0], 5'd14 } ;
assign source_id__h51177 = { addr_offset__h27245[4:0], 5'd15 } ;
assign source_id__h52673 = { addr_offset__h27245[4:0], 5'd16 } ;
assign source_id__h54169 = { addr_offset__h27245[4:0], 5'd17 } ;
assign source_id__h55665 = { addr_offset__h27245[4:0], 5'd18 } ;
assign source_id__h57161 = { addr_offset__h27245[4:0], 5'd19 } ;
assign source_id__h58657 = { addr_offset__h27245[4:0], 5'd20 } ;
assign source_id__h60153 = { addr_offset__h27245[4:0], 5'd21 } ;
assign source_id__h61649 = { addr_offset__h27245[4:0], 5'd22 } ;
assign source_id__h63145 = { addr_offset__h27245[4:0], 5'd23 } ;
assign source_id__h64641 = { addr_offset__h27245[4:0], 5'd24 } ;
assign source_id__h66137 = { addr_offset__h27245[4:0], 5'd25 } ;
assign source_id__h67633 = { addr_offset__h27245[4:0], 5'd26 } ;
assign source_id__h69129 = { addr_offset__h27245[4:0], 5'd27 } ;
assign source_id__h70625 = { addr_offset__h27245[4:0], 5'd28 } ;
assign source_id__h72121 = { addr_offset__h27245[4:0], 5'd29 } ;
assign source_id__h73617 = { addr_offset__h27245[4:0], 5'd30 } ;
assign source_id__h75113 = { addr_offset__h27245[4:0], 5'd31 } ;
assign source_id_base__h13893 = { addr_offset__h13465[4:0], 5'h0 } ;
assign source_id_base__h28620 = { addr_offset__h27245[4:0], 5'h0 } ;
assign v__h13689 = { 61'd0, x__h13769 } ;
assign v__h13934 = { 32'd0, v_ip__h13937 } ;
assign v__h18403 = { 32'd0, v_ie__h18406 } ;
assign v__h24016 = { 61'd0, x__h24096 } ;
assign v__h24251 =
m_vrg_source_ip_16_read__6_AND_NOT_m_vrg_sourc_ETC___d689 ?
v__h25556 :
64'd0 ;
assign v__h25556 = { 59'd0, max_id__h24210 } ;
assign v__h27250 =
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ?
2'b11 :
v__h27435 ;
assign v__h27435 =
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 ?
v__h27448 :
v__h28425 ;
assign v__h27448 =
(addr_offset__h27245[11:2] != 10'd0 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d823) ?
2'b0 :
2'b10 ;
assign v__h28425 =
(!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874) ?
v__h28444 :
v__h28597 ;
assign v__h28444 =
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 ?
2'b0 :
2'b10 ;
assign v__h28597 =
(!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d874 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d888) ?
v__h28616 :
v__h76713 ;
assign v__h28616 =
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d877 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d889) ?
2'b0 :
2'b10 ;
assign v__h76750 =
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d2854 ?
2'b0 :
2'b10 ;
assign v_ie__h18406 =
{ source_id__h20405 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1,
source_id__h20581 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2,
source_id__h20689 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3,
source_id__h20797 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4,
source_id__h20905 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5,
source_id__h21013 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6,
source_id__h21121 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7,
source_id__h21229 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8,
source_id__h21337 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9,
source_id__h21445 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10,
source_id__h21553 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11,
source_id__h21661 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12,
source_id__h21769 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13,
source_id__h21877 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14,
source_id__h21985 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15,
source_id__h22093 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16,
source_id__h22201 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17,
source_id__h22309 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18,
source_id__h22417 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19,
source_id__h22525 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20,
source_id__h22633 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21,
source_id__h22741 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22,
source_id__h22849 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23,
source_id__h22957 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24,
source_id__h23065 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25,
source_id__h23173 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26,
source_id__h23281 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27,
source_id__h23389 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28,
source_id__h23497 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29,
source_id__h23605 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30,
source_id__h23713 <= 10'd16 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 &&
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 } ;
assign v_ip__h13937 =
{ source_id__h15937 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98,
source_id__h16044 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102,
source_id__h16117 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107,
source_id__h16190 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111,
source_id__h16263 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116,
source_id__h16336 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120,
source_id__h16409 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125,
source_id__h16482 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129,
source_id__h16555 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134,
source_id__h16628 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138,
source_id__h16701 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143,
source_id__h16774 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147,
source_id__h16847 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152,
source_id__h16920 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156,
source_id__h16993 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161,
source_id__h17066 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165,
source_id__h17139 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170,
source_id__h17212 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174,
source_id__h17285 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179,
source_id__h17358 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183,
source_id__h17431 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188,
source_id__h17504 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192,
source_id__h17577 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197,
source_id__h17650 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201,
source_id__h17723 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206,
source_id__h17796 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210,
source_id__h17869 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215,
source_id__h17942 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219,
source_id__h18015 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224,
source_id__h18088 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228,
source_id__h18161 <= 10'd16 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233,
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 &&
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 } ;
assign wdata32__h27246 =
(addr_offset__h27245[2:0] == 3'd4) ?
m_slave_xactor_f_wr_data$D_OUT[72:41] :
m_slave_xactor_f_wr_data$D_OUT[40:9] ;
assign x__h23928 =
{ addr_offset__h13465[31:16], 4'd0, addr_offset__h13465[11:0] } ;
assign x__h26677 =
(addr_offset__h13465[2:0] == 3'd4) ?
rdata___1__h26714 :
rdata__h26520 ;
assign x__h76716 =
{ addr_offset__h27245[31:16], 4'd0, addr_offset__h27245[11:0] } ;
assign y_avValue_fst__h26433 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ?
v__h24251 :
64'd0 ;
assign y_avValue_fst__h26445 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ?
v__h24016 :
64'd0 ;
assign y_avValue_fst__h26461 =
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ?
v__h18403 :
64'd0 ;
assign y_avValue_fst__h26477 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ?
v__h13934 :
64'd0 ;
assign y_avValue_fst__h26482 =
(!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ?
y_avValue_fst__h26461 :
y_avValue_fst__h26466 ;
assign y_avValue_fst__h26493 =
(addr_offset__h13465[11:2] != 10'd0 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ?
v__h13689 :
64'd0 ;
assign y_avValue_fst__h26498 =
(!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ?
y_avValue_fst__h26477 :
y_avValue_fst__h26482 ;
assign y_avValue_fst__h26512 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ?
y_avValue_fst__h26493 :
y_avValue_fst__h26498 ;
assign y_avValue_snd__h26446 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d532 ?
2'b0 :
2'b10 ;
assign y_avValue_snd__h26462 =
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d242) ?
2'b0 :
2'b10 ;
assign y_avValue_snd__h26478 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d71 ?
2'b0 :
2'b10 ;
assign y_avValue_snd__h26483 =
(!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d240) ?
y_avValue_snd__h26462 :
y_avValue_snd__h26467 ;
assign y_avValue_snd__h26494 =
(addr_offset__h13465[11:2] != 10'd0 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d40) ?
2'b0 :
2'b10 ;
assign y_avValue_snd__h26499 =
(!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d68) ?
y_avValue_snd__h26478 :
y_avValue_snd__h26483 ;
assign y_avValue_snd__h26513 =
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d36 ?
y_avValue_snd__h26494 :
y_avValue_snd__h26499 ;
always@(addr_offset__h13465 or
m_vrg_source_prio_0 or
m_vrg_source_prio_1 or
m_vrg_source_prio_2 or
m_vrg_source_prio_3 or
m_vrg_source_prio_4 or
m_vrg_source_prio_5 or
m_vrg_source_prio_6 or
m_vrg_source_prio_7 or
m_vrg_source_prio_8 or
m_vrg_source_prio_9 or
m_vrg_source_prio_10 or
m_vrg_source_prio_11 or
m_vrg_source_prio_12 or
m_vrg_source_prio_13 or
m_vrg_source_prio_14 or
m_vrg_source_prio_15 or m_vrg_source_prio_16)
begin
case (addr_offset__h13465[11:2])
10'd0: x__h13769 = m_vrg_source_prio_0;
10'd1: x__h13769 = m_vrg_source_prio_1;
10'd2: x__h13769 = m_vrg_source_prio_2;
10'd3: x__h13769 = m_vrg_source_prio_3;
10'd4: x__h13769 = m_vrg_source_prio_4;
10'd5: x__h13769 = m_vrg_source_prio_5;
10'd6: x__h13769 = m_vrg_source_prio_6;
10'd7: x__h13769 = m_vrg_source_prio_7;
10'd8: x__h13769 = m_vrg_source_prio_8;
10'd9: x__h13769 = m_vrg_source_prio_9;
10'd10: x__h13769 = m_vrg_source_prio_10;
10'd11: x__h13769 = m_vrg_source_prio_11;
10'd12: x__h13769 = m_vrg_source_prio_12;
10'd13: x__h13769 = m_vrg_source_prio_13;
10'd14: x__h13769 = m_vrg_source_prio_14;
10'd15: x__h13769 = m_vrg_source_prio_15;
10'd16: x__h13769 = m_vrg_source_prio_16;
default: x__h13769 = 3'b010 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
m_vrg_target_threshold_0 or m_vrg_target_threshold_1)
begin
case (addr_offset__h13465[16:12])
5'd0: x__h24096 = m_vrg_target_threshold_0;
5'd1: x__h24096 = m_vrg_target_threshold_1;
default: x__h24096 = 3'b010 /* unspecified value */ ;
endcase
end
always@(source_id_base__h13893 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id_base__h13893)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d235 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20581 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h20581)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20405 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h20405)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20405 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h20405)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20581 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h20581)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h15937 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h15937)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d98 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20689 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h20689)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20689 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h20689)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20797 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h20797)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16044 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16044)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d102 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20797 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h20797)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20905 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h20905)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h20905 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h20905)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21013 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21013)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21013 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21013)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16117 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16117)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d107 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16190 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16190)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d111 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21121 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21121)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21121 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21121)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21229 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21229)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16263 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16263)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d116 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21229 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21229)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16336 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16336)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d120 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21337 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21337)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21337 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21337)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21445 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21445)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16409 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16409)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d125 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21445 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21445)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16482 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16482)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d129 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21553 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21553)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21553 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21553)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21661 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21661)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16555 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16555)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d134 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21661 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21661)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16628 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16628)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d138 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21769 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21769)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21769 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21769)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21877 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21877)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16701 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16701)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d143 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21877 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21877)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17358 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17358)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d183 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16774 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16774)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d147 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21985 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h21985)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h21985 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h21985)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22093 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22093)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16847 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16847)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d152 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22093 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22093)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16920 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16920)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d156 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22201 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22201)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22201 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22201)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22309 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22309)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h16993 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h16993)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d161 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22309 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22309)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17066 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17066)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d165 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22417 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22417)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22417 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22417)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22525 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22525)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17139 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17139)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d170 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22525 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22525)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17212 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17212)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d174 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22633 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22633)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22633 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22633)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22741 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22741)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17285 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17285)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d179 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22741 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22741)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22849 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22849)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22849 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22849)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22957 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h22957)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17431 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17431)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d188 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h22957 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h22957)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17504 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17504)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d192 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23065 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h23065)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23065 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h23065)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23173 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h23173)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17577 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17577)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d197 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23173 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h23173)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17650 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17650)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d201 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23281 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h23281)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23281 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h23281)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23389 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h23389)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17723 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17723)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d206 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23389 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h23389)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17796 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17796)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d210 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23497 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h23497)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23497 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h23497)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23605 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h23605)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17869 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17869)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d215 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23605 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h23605)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h17942 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h17942)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d219 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23713 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id__h23713)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h23713 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id__h23713)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id_base__h13893 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (source_id_base__h13893)
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h18015 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h18015)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d224 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id_base__h13893 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (source_id_base__h13893)
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d271;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d290;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q1 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d296;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d297;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q2 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d304;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d305;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q3 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d311;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d312;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q4 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d319;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d320;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q5 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d326;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d327;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q6 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d334;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d335;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q7 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d341;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d342;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q8 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d349;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d350;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q9 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d356;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d357;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q10 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d364;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d365;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q11 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d371;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d372;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q12 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d379;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d380;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q13 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d386;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d387;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q14 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d394;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d395;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q15 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d401;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d402;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q16 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d409;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d410;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q17 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d416;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d417;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q18 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d424;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d425;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q19 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d431;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d432;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q20 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d439;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d440;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q21 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d446;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d447;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q22 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d454;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d455;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q23 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d461;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d462;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q24 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d469;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d470;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q25 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d476;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d477;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q26 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d484;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d485;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q27 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d491;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d492;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q28 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d499;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d500;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q29 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d506;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d507;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q30 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d514;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d515;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q31 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520)
begin
case (addr_offset__h13465[11:7])
5'd0:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d519;
5'd1:
CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d520;
default: CASE_addr_offset3465_BITS_11_TO_7_0_SEL_ARR_m__ETC__q32 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h18088 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h18088)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d228 =
1'b0 /* unspecified value */ ;
endcase
end
always@(source_id__h18161 or
m_vrg_source_ip_0 or
m_vrg_source_ip_1 or
m_vrg_source_ip_2 or
m_vrg_source_ip_3 or
m_vrg_source_ip_4 or
m_vrg_source_ip_5 or
m_vrg_source_ip_6 or
m_vrg_source_ip_7 or
m_vrg_source_ip_8 or
m_vrg_source_ip_9 or
m_vrg_source_ip_10 or
m_vrg_source_ip_11 or
m_vrg_source_ip_12 or
m_vrg_source_ip_13 or
m_vrg_source_ip_14 or m_vrg_source_ip_15 or m_vrg_source_ip_16)
begin
case (source_id__h18161)
10'd0:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_0;
10'd1:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_1;
10'd2:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_2;
10'd3:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_3;
10'd4:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_4;
10'd5:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_5;
10'd6:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_6;
10'd7:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_7;
10'd8:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_8;
10'd9:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_9;
10'd10:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_10;
10'd11:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_11;
10'd12:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_12;
10'd13:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_13;
10'd14:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_14;
10'd15:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_15;
10'd16:
SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
m_vrg_source_ip_16;
default: SEL_ARR_m_vrg_source_ip_0_read__0_m_vrg_source_ETC___d233 =
1'b0 /* unspecified value */ ;
endcase
end
always@(x__h23928 or y_avValue_snd__h26446)
begin
case (x__h23928)
32'h00200000, 32'h00200004:
y_avValue_snd__h26467 = y_avValue_snd__h26446;
default: y_avValue_snd__h26467 = 2'b10;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_1 or m_vvrg_ie_1_1)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 =
m_vvrg_ie_0_1;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 =
m_vvrg_ie_1_1;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q33 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_2 or m_vvrg_ie_1_2)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 =
m_vvrg_ie_0_2;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 =
m_vvrg_ie_1_2;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q34 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_3 or m_vvrg_ie_1_3)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 =
m_vvrg_ie_0_3;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 =
m_vvrg_ie_1_3;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q35 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_4 or m_vvrg_ie_1_4)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 =
m_vvrg_ie_0_4;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 =
m_vvrg_ie_1_4;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q36 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_5 or m_vvrg_ie_1_5)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 =
m_vvrg_ie_0_5;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 =
m_vvrg_ie_1_5;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q37 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_6 or m_vvrg_ie_1_6)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 =
m_vvrg_ie_0_6;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 =
m_vvrg_ie_1_6;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q38 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_7 or m_vvrg_ie_1_7)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 =
m_vvrg_ie_0_7;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 =
m_vvrg_ie_1_7;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q39 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_8 or m_vvrg_ie_1_8)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 =
m_vvrg_ie_0_8;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 =
m_vvrg_ie_1_8;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q40 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_9 or m_vvrg_ie_1_9)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 =
m_vvrg_ie_0_9;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 =
m_vvrg_ie_1_9;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q41 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_10 or m_vvrg_ie_1_10)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 =
m_vvrg_ie_0_10;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 =
m_vvrg_ie_1_10;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q42 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_11 or m_vvrg_ie_1_11)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 =
m_vvrg_ie_0_11;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 =
m_vvrg_ie_1_11;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q43 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_12 or m_vvrg_ie_1_12)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 =
m_vvrg_ie_0_12;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 =
m_vvrg_ie_1_12;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q44 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_13 or m_vvrg_ie_1_13)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 =
m_vvrg_ie_0_13;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 =
m_vvrg_ie_1_13;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q45 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_14 or m_vvrg_ie_1_14)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 =
m_vvrg_ie_0_14;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 =
m_vvrg_ie_1_14;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q46 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_15 or m_vvrg_ie_1_15)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 =
m_vvrg_ie_0_15;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 =
m_vvrg_ie_1_15;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q47 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h13465 or m_vvrg_ie_0_16 or m_vvrg_ie_1_16)
begin
case (addr_offset__h13465[16:12])
5'd0:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 =
m_vvrg_ie_0_16;
5'd1:
CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 =
m_vvrg_ie_1_16;
default: CASE_addr_offset3465_BITS_16_TO_12_0_m_vvrg_ie_ETC__q48 =
1'b0 /* unspecified value */ ;
endcase
end
always@(x__h23928 or y_avValue_fst__h26445 or y_avValue_fst__h26433)
begin
case (x__h23928)
32'h00200000: y_avValue_fst__h26466 = y_avValue_fst__h26445;
32'h00200004: y_avValue_fst__h26466 = y_avValue_fst__h26433;
default: y_avValue_fst__h26466 = 64'd0;
endcase
end
always@(x__h76716 or v__h76750)
begin
case (x__h76716)
32'h00200000, 32'h00200004: v__h76713 = v__h76750;
default: v__h76713 = 2'b10;
endcase
end
always@(wdata32__h27246 or
m_vvrg_ie_0_0 or
m_vvrg_ie_0_1 or
m_vvrg_ie_0_2 or
m_vvrg_ie_0_3 or
m_vvrg_ie_0_4 or
m_vvrg_ie_0_5 or
m_vvrg_ie_0_6 or
m_vvrg_ie_0_7 or
m_vvrg_ie_0_8 or
m_vvrg_ie_0_9 or
m_vvrg_ie_0_10 or
m_vvrg_ie_0_11 or
m_vvrg_ie_0_12 or
m_vvrg_ie_0_13 or
m_vvrg_ie_0_14 or m_vvrg_ie_0_15 or m_vvrg_ie_0_16)
begin
case (wdata32__h27246[9:0])
10'd0:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_0;
10'd1:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_1;
10'd2:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_2;
10'd3:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_3;
10'd4:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_4;
10'd5:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_5;
10'd6:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_6;
10'd7:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_7;
10'd8:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_8;
10'd9:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_9;
10'd10:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_10;
10'd11:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_11;
10'd12:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_12;
10'd13:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_13;
10'd14:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_14;
10'd15:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_15;
10'd16:
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
m_vvrg_ie_0_16;
default: SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 =
1'b0 /* unspecified value */ ;
endcase
end
always@(wdata32__h27246 or
m_vvrg_ie_1_0 or
m_vvrg_ie_1_1 or
m_vvrg_ie_1_2 or
m_vvrg_ie_1_3 or
m_vvrg_ie_1_4 or
m_vvrg_ie_1_5 or
m_vvrg_ie_1_6 or
m_vvrg_ie_1_7 or
m_vvrg_ie_1_8 or
m_vvrg_ie_1_9 or
m_vvrg_ie_1_10 or
m_vvrg_ie_1_11 or
m_vvrg_ie_1_12 or
m_vvrg_ie_1_13 or
m_vvrg_ie_1_14 or m_vvrg_ie_1_15 or m_vvrg_ie_1_16)
begin
case (wdata32__h27246[9:0])
10'd0:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_0;
10'd1:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_1;
10'd2:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_2;
10'd3:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_3;
10'd4:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_4;
10'd5:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_5;
10'd6:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_6;
10'd7:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_7;
10'd8:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_8;
10'd9:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_9;
10'd10:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_10;
10'd11:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_11;
10'd12:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_12;
10'd13:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_13;
10'd14:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_14;
10'd15:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_15;
10'd16:
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
m_vvrg_ie_1_16;
default: SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876 =
1'b0 /* unspecified value */ ;
endcase
end
always@(addr_offset__h27245 or
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875 or
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876)
begin
case (addr_offset__h27245[16:12])
5'd0:
SEL_ARR_SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_ETC___d2878 =
SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_54_m_vv_ETC___d2875;
5'd1:
SEL_ARR_SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_ETC___d2878 =
SEL_ARR_m_vvrg_ie_1_0_72_m_vvrg_ie_1_1_73_m_vv_ETC___d2876;
default: SEL_ARR_SEL_ARR_m_vvrg_ie_0_0_53_m_vvrg_ie_0_1_ETC___d2878 =
1'b0 /* unspecified value */ ;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY 3'd0;
m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY 3'd7;
m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY 3'd7;
m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY 1'd0;
m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (m_cfg_verbosity$EN)
m_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY m_cfg_verbosity$D_IN;
if (m_vrg_source_busy_0$EN)
m_vrg_source_busy_0 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_0$D_IN;
if (m_vrg_source_busy_1$EN)
m_vrg_source_busy_1 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_1$D_IN;
if (m_vrg_source_busy_10$EN)
m_vrg_source_busy_10 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_10$D_IN;
if (m_vrg_source_busy_11$EN)
m_vrg_source_busy_11 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_11$D_IN;
if (m_vrg_source_busy_12$EN)
m_vrg_source_busy_12 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_12$D_IN;
if (m_vrg_source_busy_13$EN)
m_vrg_source_busy_13 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_13$D_IN;
if (m_vrg_source_busy_14$EN)
m_vrg_source_busy_14 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_14$D_IN;
if (m_vrg_source_busy_15$EN)
m_vrg_source_busy_15 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_15$D_IN;
if (m_vrg_source_busy_16$EN)
m_vrg_source_busy_16 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_16$D_IN;
if (m_vrg_source_busy_2$EN)
m_vrg_source_busy_2 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_2$D_IN;
if (m_vrg_source_busy_3$EN)
m_vrg_source_busy_3 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_3$D_IN;
if (m_vrg_source_busy_4$EN)
m_vrg_source_busy_4 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_4$D_IN;
if (m_vrg_source_busy_5$EN)
m_vrg_source_busy_5 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_5$D_IN;
if (m_vrg_source_busy_6$EN)
m_vrg_source_busy_6 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_6$D_IN;
if (m_vrg_source_busy_7$EN)
m_vrg_source_busy_7 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_7$D_IN;
if (m_vrg_source_busy_8$EN)
m_vrg_source_busy_8 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_8$D_IN;
if (m_vrg_source_busy_9$EN)
m_vrg_source_busy_9 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_busy_9$D_IN;
if (m_vrg_source_ip_0$EN)
m_vrg_source_ip_0 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_0$D_IN;
if (m_vrg_source_ip_1$EN)
m_vrg_source_ip_1 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_1$D_IN;
if (m_vrg_source_ip_10$EN)
m_vrg_source_ip_10 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_10$D_IN;
if (m_vrg_source_ip_11$EN)
m_vrg_source_ip_11 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_11$D_IN;
if (m_vrg_source_ip_12$EN)
m_vrg_source_ip_12 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_12$D_IN;
if (m_vrg_source_ip_13$EN)
m_vrg_source_ip_13 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_13$D_IN;
if (m_vrg_source_ip_14$EN)
m_vrg_source_ip_14 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_14$D_IN;
if (m_vrg_source_ip_15$EN)
m_vrg_source_ip_15 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_15$D_IN;
if (m_vrg_source_ip_16$EN)
m_vrg_source_ip_16 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_16$D_IN;
if (m_vrg_source_ip_2$EN)
m_vrg_source_ip_2 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_2$D_IN;
if (m_vrg_source_ip_3$EN)
m_vrg_source_ip_3 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_3$D_IN;
if (m_vrg_source_ip_4$EN)
m_vrg_source_ip_4 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_4$D_IN;
if (m_vrg_source_ip_5$EN)
m_vrg_source_ip_5 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_5$D_IN;
if (m_vrg_source_ip_6$EN)
m_vrg_source_ip_6 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_6$D_IN;
if (m_vrg_source_ip_7$EN)
m_vrg_source_ip_7 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_7$D_IN;
if (m_vrg_source_ip_8$EN)
m_vrg_source_ip_8 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_8$D_IN;
if (m_vrg_source_ip_9$EN)
m_vrg_source_ip_9 <= `BSV_ASSIGNMENT_DELAY m_vrg_source_ip_9$D_IN;
if (m_vrg_source_prio_0$EN)
m_vrg_source_prio_0 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_0$D_IN;
if (m_vrg_source_prio_1$EN)
m_vrg_source_prio_1 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_1$D_IN;
if (m_vrg_source_prio_10$EN)
m_vrg_source_prio_10 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_10$D_IN;
if (m_vrg_source_prio_11$EN)
m_vrg_source_prio_11 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_11$D_IN;
if (m_vrg_source_prio_12$EN)
m_vrg_source_prio_12 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_12$D_IN;
if (m_vrg_source_prio_13$EN)
m_vrg_source_prio_13 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_13$D_IN;
if (m_vrg_source_prio_14$EN)
m_vrg_source_prio_14 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_14$D_IN;
if (m_vrg_source_prio_15$EN)
m_vrg_source_prio_15 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_15$D_IN;
if (m_vrg_source_prio_16$EN)
m_vrg_source_prio_16 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_16$D_IN;
if (m_vrg_source_prio_2$EN)
m_vrg_source_prio_2 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_2$D_IN;
if (m_vrg_source_prio_3$EN)
m_vrg_source_prio_3 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_3$D_IN;
if (m_vrg_source_prio_4$EN)
m_vrg_source_prio_4 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_4$D_IN;
if (m_vrg_source_prio_5$EN)
m_vrg_source_prio_5 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_5$D_IN;
if (m_vrg_source_prio_6$EN)
m_vrg_source_prio_6 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_6$D_IN;
if (m_vrg_source_prio_7$EN)
m_vrg_source_prio_7 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_7$D_IN;
if (m_vrg_source_prio_8$EN)
m_vrg_source_prio_8 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_8$D_IN;
if (m_vrg_source_prio_9$EN)
m_vrg_source_prio_9 <= `BSV_ASSIGNMENT_DELAY
m_vrg_source_prio_9$D_IN;
if (m_vrg_target_threshold_0$EN)
m_vrg_target_threshold_0 <= `BSV_ASSIGNMENT_DELAY
m_vrg_target_threshold_0$D_IN;
if (m_vrg_target_threshold_1$EN)
m_vrg_target_threshold_1 <= `BSV_ASSIGNMENT_DELAY
m_vrg_target_threshold_1$D_IN;
if (m_vvrg_ie_0_0$EN)
m_vvrg_ie_0_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_0$D_IN;
if (m_vvrg_ie_0_1$EN)
m_vvrg_ie_0_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_1$D_IN;
if (m_vvrg_ie_0_10$EN)
m_vvrg_ie_0_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_10$D_IN;
if (m_vvrg_ie_0_11$EN)
m_vvrg_ie_0_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_11$D_IN;
if (m_vvrg_ie_0_12$EN)
m_vvrg_ie_0_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_12$D_IN;
if (m_vvrg_ie_0_13$EN)
m_vvrg_ie_0_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_13$D_IN;
if (m_vvrg_ie_0_14$EN)
m_vvrg_ie_0_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_14$D_IN;
if (m_vvrg_ie_0_15$EN)
m_vvrg_ie_0_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_15$D_IN;
if (m_vvrg_ie_0_16$EN)
m_vvrg_ie_0_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_16$D_IN;
if (m_vvrg_ie_0_2$EN)
m_vvrg_ie_0_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_2$D_IN;
if (m_vvrg_ie_0_3$EN)
m_vvrg_ie_0_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_3$D_IN;
if (m_vvrg_ie_0_4$EN)
m_vvrg_ie_0_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_4$D_IN;
if (m_vvrg_ie_0_5$EN)
m_vvrg_ie_0_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_5$D_IN;
if (m_vvrg_ie_0_6$EN)
m_vvrg_ie_0_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_6$D_IN;
if (m_vvrg_ie_0_7$EN)
m_vvrg_ie_0_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_7$D_IN;
if (m_vvrg_ie_0_8$EN)
m_vvrg_ie_0_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_8$D_IN;
if (m_vvrg_ie_0_9$EN)
m_vvrg_ie_0_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_0_9$D_IN;
if (m_vvrg_ie_1_0$EN)
m_vvrg_ie_1_0 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_0$D_IN;
if (m_vvrg_ie_1_1$EN)
m_vvrg_ie_1_1 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_1$D_IN;
if (m_vvrg_ie_1_10$EN)
m_vvrg_ie_1_10 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_10$D_IN;
if (m_vvrg_ie_1_11$EN)
m_vvrg_ie_1_11 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_11$D_IN;
if (m_vvrg_ie_1_12$EN)
m_vvrg_ie_1_12 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_12$D_IN;
if (m_vvrg_ie_1_13$EN)
m_vvrg_ie_1_13 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_13$D_IN;
if (m_vvrg_ie_1_14$EN)
m_vvrg_ie_1_14 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_14$D_IN;
if (m_vvrg_ie_1_15$EN)
m_vvrg_ie_1_15 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_15$D_IN;
if (m_vvrg_ie_1_16$EN)
m_vvrg_ie_1_16 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_16$D_IN;
if (m_vvrg_ie_1_2$EN)
m_vvrg_ie_1_2 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_2$D_IN;
if (m_vvrg_ie_1_3$EN)
m_vvrg_ie_1_3 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_3$D_IN;
if (m_vvrg_ie_1_4$EN)
m_vvrg_ie_1_4 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_4$D_IN;
if (m_vvrg_ie_1_5$EN)
m_vvrg_ie_1_5 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_5$D_IN;
if (m_vvrg_ie_1_6$EN)
m_vvrg_ie_1_6 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_6$D_IN;
if (m_vvrg_ie_1_7$EN)
m_vvrg_ie_1_7 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_7$D_IN;
if (m_vvrg_ie_1_8$EN)
m_vvrg_ie_1_8 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_8$D_IN;
if (m_vvrg_ie_1_9$EN)
m_vvrg_ie_1_9 <= `BSV_ASSIGNMENT_DELAY m_vvrg_ie_1_9$D_IN;
end
if (m_rg_addr_base$EN)
m_rg_addr_base <= `BSV_ASSIGNMENT_DELAY m_rg_addr_base$D_IN;
if (m_rg_addr_lim$EN)
m_rg_addr_lim <= `BSV_ASSIGNMENT_DELAY m_rg_addr_lim$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
m_cfg_verbosity = 4'hA;
m_rg_addr_base = 64'hAAAAAAAAAAAAAAAA;
m_rg_addr_lim = 64'hAAAAAAAAAAAAAAAA;
m_vrg_source_busy_0 = 1'h0;
m_vrg_source_busy_1 = 1'h0;
m_vrg_source_busy_10 = 1'h0;
m_vrg_source_busy_11 = 1'h0;
m_vrg_source_busy_12 = 1'h0;
m_vrg_source_busy_13 = 1'h0;
m_vrg_source_busy_14 = 1'h0;
m_vrg_source_busy_15 = 1'h0;
m_vrg_source_busy_16 = 1'h0;
m_vrg_source_busy_2 = 1'h0;
m_vrg_source_busy_3 = 1'h0;
m_vrg_source_busy_4 = 1'h0;
m_vrg_source_busy_5 = 1'h0;
m_vrg_source_busy_6 = 1'h0;
m_vrg_source_busy_7 = 1'h0;
m_vrg_source_busy_8 = 1'h0;
m_vrg_source_busy_9 = 1'h0;
m_vrg_source_ip_0 = 1'h0;
m_vrg_source_ip_1 = 1'h0;
m_vrg_source_ip_10 = 1'h0;
m_vrg_source_ip_11 = 1'h0;
m_vrg_source_ip_12 = 1'h0;
m_vrg_source_ip_13 = 1'h0;
m_vrg_source_ip_14 = 1'h0;
m_vrg_source_ip_15 = 1'h0;
m_vrg_source_ip_16 = 1'h0;
m_vrg_source_ip_2 = 1'h0;
m_vrg_source_ip_3 = 1'h0;
m_vrg_source_ip_4 = 1'h0;
m_vrg_source_ip_5 = 1'h0;
m_vrg_source_ip_6 = 1'h0;
m_vrg_source_ip_7 = 1'h0;
m_vrg_source_ip_8 = 1'h0;
m_vrg_source_ip_9 = 1'h0;
m_vrg_source_prio_0 = 3'h2;
m_vrg_source_prio_1 = 3'h2;
m_vrg_source_prio_10 = 3'h2;
m_vrg_source_prio_11 = 3'h2;
m_vrg_source_prio_12 = 3'h2;
m_vrg_source_prio_13 = 3'h2;
m_vrg_source_prio_14 = 3'h2;
m_vrg_source_prio_15 = 3'h2;
m_vrg_source_prio_16 = 3'h2;
m_vrg_source_prio_2 = 3'h2;
m_vrg_source_prio_3 = 3'h2;
m_vrg_source_prio_4 = 3'h2;
m_vrg_source_prio_5 = 3'h2;
m_vrg_source_prio_6 = 3'h2;
m_vrg_source_prio_7 = 3'h2;
m_vrg_source_prio_8 = 3'h2;
m_vrg_source_prio_9 = 3'h2;
m_vrg_target_threshold_0 = 3'h2;
m_vrg_target_threshold_1 = 3'h2;
m_vvrg_ie_0_0 = 1'h0;
m_vvrg_ie_0_1 = 1'h0;
m_vvrg_ie_0_10 = 1'h0;
m_vvrg_ie_0_11 = 1'h0;
m_vvrg_ie_0_12 = 1'h0;
m_vvrg_ie_0_13 = 1'h0;
m_vvrg_ie_0_14 = 1'h0;
m_vvrg_ie_0_15 = 1'h0;
m_vvrg_ie_0_16 = 1'h0;
m_vvrg_ie_0_2 = 1'h0;
m_vvrg_ie_0_3 = 1'h0;
m_vvrg_ie_0_4 = 1'h0;
m_vvrg_ie_0_5 = 1'h0;
m_vvrg_ie_0_6 = 1'h0;
m_vvrg_ie_0_7 = 1'h0;
m_vvrg_ie_0_8 = 1'h0;
m_vvrg_ie_0_9 = 1'h0;
m_vvrg_ie_1_0 = 1'h0;
m_vvrg_ie_1_1 = 1'h0;
m_vvrg_ie_1_10 = 1'h0;
m_vvrg_ie_1_11 = 1'h0;
m_vvrg_ie_1_12 = 1'h0;
m_vvrg_ie_1_13 = 1'h0;
m_vvrg_ie_1_14 = 1'h0;
m_vvrg_ie_1_15 = 1'h0;
m_vvrg_ie_1_16 = 1'h0;
m_vvrg_ie_1_2 = 1'h0;
m_vvrg_ie_1_3 = 1'h0;
m_vvrg_ie_1_4 = 1'h0;
m_vvrg_ie_1_5 = 1'h0;
m_vvrg_ie_1_6 = 1'h0;
m_vvrg_ie_1_7 = 1'h0;
m_vvrg_ie_1_8 = 1'h0;
m_vvrg_ie_1_9 = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $display("----------------");
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write("Src IPs :");
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_1);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_2);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_3);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_4);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_5);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_6);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_8);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_9);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_10);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_11);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_12);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_13);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_14);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_15);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_ip_16);
if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write("Src Prios:");
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_1);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_2);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_3);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_4);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_5);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_6);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_8);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_9);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_10);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_11);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_12);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_13);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_14);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_15);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_prio_16);
if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write("Src busy :");
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_1);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_2);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_3);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_4);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_5);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_6);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_8);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_9);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_10);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_11);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_12);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_13);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_14);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_15);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vrg_source_busy_16);
if (RST_N != `BSV_RESET_VALUE) if (EN_show_PLIC_state) $display("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_1);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_2);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_3);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_4);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_5);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_6);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_8);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_9);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_10);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_11);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_12);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_13);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_14);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_15);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_0_16);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state)
$display(" MaxPri %0d, Thresh %0d, MaxId %0d",
a__h81740,
m_vrg_target_threshold_0,
b__h81741);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write("T %0d IEs :", $signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_1);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_2);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_3);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_4);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_5);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_6);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_8);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_9);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_10);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_11);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_12);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_13);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_14);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_15);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state) $write(" %0d", m_vvrg_ie_1_16);
if (RST_N != `BSV_RESET_VALUE)
if (EN_show_PLIC_state)
$display(" MaxPri %0d, Thresh %0d, MaxId %0d",
a__h83894,
m_vrg_target_threshold_1,
b__h83895);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_1_974_213_AND_NOT_m_cfg__ETC___d3217)
begin
v__h86246 = $stime;
#0;
end
v__h86240 = v__h86246 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_1_974_213_AND_NOT_m_cfg__ETC___d3217)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h86240,
$signed(32'd1),
v_sources_0_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_2_975_220_AND_NOT_m_cfg__ETC___d3224)
begin
v__h86441 = $stime;
#0;
end
v__h86435 = v__h86441 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_2_975_220_AND_NOT_m_cfg__ETC___d3224)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h86435,
$signed(32'd2),
v_sources_1_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_3_976_228_AND_NOT_m_cfg__ETC___d3232)
begin
v__h86636 = $stime;
#0;
end
v__h86630 = v__h86636 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_3_976_228_AND_NOT_m_cfg__ETC___d3232)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h86630,
$signed(32'd3),
v_sources_2_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_4_977_236_AND_NOT_m_cfg__ETC___d3240)
begin
v__h86831 = $stime;
#0;
end
v__h86825 = v__h86831 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_4_977_236_AND_NOT_m_cfg__ETC___d3240)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h86825,
$signed(32'd4),
v_sources_3_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_5_978_244_AND_NOT_m_cfg__ETC___d3248)
begin
v__h87026 = $stime;
#0;
end
v__h87020 = v__h87026 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_5_978_244_AND_NOT_m_cfg__ETC___d3248)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h87020,
$signed(32'd5),
v_sources_4_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_6_979_252_AND_NOT_m_cfg__ETC___d3256)
begin
v__h87221 = $stime;
#0;
end
v__h87215 = v__h87221 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_6_979_252_AND_NOT_m_cfg__ETC___d3256)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h87215,
$signed(32'd6),
v_sources_5_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_7_980_260_AND_NOT_m_cfg__ETC___d3264)
begin
v__h87416 = $stime;
#0;
end
v__h87410 = v__h87416 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_7_980_260_AND_NOT_m_cfg__ETC___d3264)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h87410,
$signed(32'd7),
v_sources_6_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_8_981_268_AND_NOT_m_cfg__ETC___d3272)
begin
v__h87611 = $stime;
#0;
end
v__h87605 = v__h87611 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_8_981_268_AND_NOT_m_cfg__ETC___d3272)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h87605,
$signed(32'd8),
v_sources_7_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_9_982_276_AND_NOT_m_cfg__ETC___d3280)
begin
v__h87806 = $stime;
#0;
end
v__h87800 = v__h87806 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_9_982_276_AND_NOT_m_cfg__ETC___d3280)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h87800,
$signed(32'd9),
v_sources_8_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_10_983_284_AND_NOT_m_cfg_ETC___d3288)
begin
v__h88001 = $stime;
#0;
end
v__h87995 = v__h88001 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_10_983_284_AND_NOT_m_cfg_ETC___d3288)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h87995,
$signed(32'd10),
v_sources_9_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_11_984_292_AND_NOT_m_cfg_ETC___d3296)
begin
v__h88196 = $stime;
#0;
end
v__h88190 = v__h88196 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_11_984_292_AND_NOT_m_cfg_ETC___d3296)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h88190,
$signed(32'd11),
v_sources_10_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_12_985_300_AND_NOT_m_cfg_ETC___d3304)
begin
v__h88391 = $stime;
#0;
end
v__h88385 = v__h88391 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_12_985_300_AND_NOT_m_cfg_ETC___d3304)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h88385,
$signed(32'd12),
v_sources_11_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_13_986_308_AND_NOT_m_cfg_ETC___d3312)
begin
v__h88586 = $stime;
#0;
end
v__h88580 = v__h88586 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_13_986_308_AND_NOT_m_cfg_ETC___d3312)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h88580,
$signed(32'd13),
v_sources_12_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_14_987_316_AND_NOT_m_cfg_ETC___d3320)
begin
v__h88781 = $stime;
#0;
end
v__h88775 = v__h88781 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_14_987_316_AND_NOT_m_cfg_ETC___d3320)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h88775,
$signed(32'd14),
v_sources_13_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_15_988_324_AND_NOT_m_cfg_ETC___d3328)
begin
v__h88976 = $stime;
#0;
end
v__h88970 = v__h88976 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_15_988_324_AND_NOT_m_cfg_ETC___d3328)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h88970,
$signed(32'd15),
v_sources_14_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_16_989_332_AND_NOT_m_cfg_ETC___d3336)
begin
v__h89171 = $stime;
#0;
end
v__h89165 = v__h89171 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_m_vrg_source_busy_16_989_332_AND_NOT_m_cfg_ETC___d3336)
$display("%0d: %m.m_interrupt_req: changing vrg_source_ip [%0d] to %0d",
v__h89165,
$signed(32'd16),
v_sources_15_m_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0)
begin
v__h5962 = $stime;
#0;
end
v__h5956 = v__h5962 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_reset && m_cfg_verbosity != 4'd0)
$display("%0d: PLIC.rl_reset", v__h5956);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
begin
v__h13331 = $stime;
#0;
end
v__h13325 = v__h13331 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$display("%0d: PLIC.rl_process_rd_req:", v__h13325);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
begin
v__h13514 = $stime;
#0;
end
v__h13508 = v__h13514 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr",
v__h13508);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43)
begin
v__h13730 = $stime;
#0;
end
v__h13724 = v__h13730 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d43)
$display("%0d: PLIC.rl_process_rd_req: reading Source Priority: source %0d = 0x%0h",
v__h13724,
addr_offset__h13465[11:2],
v__h13689);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74)
begin
v__h13976 = $stime;
#0;
end
v__h13970 = v__h13976 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
!m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d74)
$display("%0d: PLIC.rl_process_rd_req: reading Intr Pending 32 bits from source %0d = 0x%0h",
v__h13970,
source_id_base__h13893,
v__h13934);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248)
begin
v__h18445 = $stime;
#0;
end
v__h18439 = v__h18445 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d248)
$display("%0d: PLIC.rl_process_rd_req: reading Intr Enable 32 bits from source %0d = 0x%0h",
v__h18439,
source_id_base__h13893,
v__h18403);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538)
begin
v__h24057 = $stime;
#0;
end
v__h24051 = v__h24057 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d538)
$display("%0d: PLIC.rl_process_rd_req: reading Threshold for target %0d = 0x%0h",
v__h24051,
addr_offset__h13465[16:12],
v__h24016);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d733)
begin
v__h26355 = $stime;
#0;
end
v__h26349 = v__h26355 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_slave_xactor_f_rd_addr_first__9_BITS_92__ETC___d733)
$display("%0d: PLIC.rl_process_rd_req: reading Claim for target %0d = 0x%0h",
v__h26349,
addr_offset__h13465[16:12],
v__h24251);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
begin
v__h26568 = $stime;
#0;
end
v__h26562 = v__h26568 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$display("%0d: ERROR: PLIC.rl_process_rd_req: unrecognized addr",
v__h26562);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
(m_slave_xactor_f_rd_addr_first__9_BITS_92_TO_2_ETC___d31 ||
IF_m_slave_xactor_f_rd_addr_first__9_BITS_92_T_ETC___d750))
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
begin
v__h26773 = $stime;
#0;
end
v__h26767 = v__h26773 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$display("%0d: PLIC.rl_process_rd_req", v__h26767);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", x__h26677);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", rresp__h26521);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_rd_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
begin
v__h27053 = $stime;
#0;
end
v__h27047 = v__h27053 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$display("%0d: PLIC.rl_process_wr_req", v__h27047);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16 &&
m_slave_xactor_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16 &&
!m_slave_xactor_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
begin
v__h27284 = $stime;
#0;
end
v__h27278 = v__h27284 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr",
v__h27278);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d869)
begin
v__h28359 = $stime;
#0;
end
v__h28353 = v__h28359 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d869)
$display("%0d: PLIC.rl_process_wr_req: writing Source Priority: source %0d = 0x%0h",
v__h28353,
addr_offset__h27245[11:2],
wdata32__h27246);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d880)
begin
v__h28531 = $stime;
#0;
end
v__h28525 = v__h28531 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d880)
$display("%0d: PLIC.rl_process_wr_req: Ignoring write to Read-only Intr Pending 32 bits from source %0d",
v__h28525,
source_id_base__h28620);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2844)
begin
v__h76647 = $stime;
#0;
end
v__h76641 = v__h76647 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2844)
$display("%0d: PLIC.rl_process_wr_req: writing Intr Enable 32 bits for target %0d from source %0d = 0x%0h",
v__h76641,
addr_offset__h27245[11:7],
source_id_base__h28620,
wdata32__h27246);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2868)
begin
v__h76947 = $stime;
#0;
end
v__h76941 = v__h76947 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2868)
$display("%0d: PLIC.rl_process_wr_req: writing threshold for target %0d = 0x%0h",
v__h76941,
addr_offset__h27245[16:12],
wdata32__h27246);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2923)
begin
v__h77579 = $stime;
#0;
end
v__h77573 = v__h77579 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2923)
$display("%0d: PLIC.rl_process_wr_req: writing completion for target %0d for source 0x%0h",
v__h77573,
addr_offset__h27245[16:12],
wdata32__h27246[9:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2935)
begin
v__h77673 = $stime;
#0;
end
v__h77667 = v__h77673 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 &&
!m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d821 &&
NOT_m_slave_xactor_f_wr_addr_first__94_BITS_92_ETC___d2935)
$display("%0d: PLIC.rl_process_wr_req: ignoring completion for target %0d for source 0x%0h",
v__h77667,
addr_offset__h27245[16:12],
wdata32__h27246[9:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
begin
v__h77844 = $stime;
#0;
end
v__h77838 = v__h77844 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$display("%0d: ERROR: PLIC.rl_process_wr_req: unrecognized addr",
v__h77838);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952) &&
m_slave_xactor_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952) &&
!m_slave_xactor_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
(m_slave_xactor_f_wr_addr_first__94_BITS_92_TO__ETC___d812 ||
IF_m_slave_xactor_f_wr_addr_first__94_BITS_92__ETC___d2952))
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
begin
v__h78064 = $stime;
#0;
end
v__h78058 = v__h78064 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$display("%0d: PLIC.AXI4.rl_process_wr_req", v__h78058);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16 &&
m_slave_xactor_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16 &&
!m_slave_xactor_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", m_slave_xactor_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", v__h27250);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_process_wr_req &&
NOT_m_cfg_verbosity_read_ULE_1_5___d16)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0)
begin
v__h85245 = $stime;
#0;
end
v__h85239 = v__h85245 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0)
$display("%0d: WARNING: PLIC.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned",
v__h85239,
set_addr_map_addr_base);
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0)
begin
v__h85351 = $stime;
#0;
end
v__h85345 = v__h85351 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0)
$display("%0d: WARNING: PLIC.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned",
v__h85345,
set_addr_map_addr_lim);
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && m_cfg_verbosity != 4'd0)
begin
v__h85478 = $stime;
#0;
end
v__h85472 = v__h85478 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && m_cfg_verbosity != 4'd0)
$display("%0d: PLIC.set_addr_map: base 0x%0h limit 0x%0h",
v__h85472,
set_addr_map_addr_base,
set_addr_map_addr_lim);
end
// synopsys translate_on
endmodule // mkPLIC_16_2_7
|
`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH UST
// Engineer: Wojciech Gredel, Hubert Górowski
//
// Create Date:
// Design Name:
// Module Name: Player
// Project Name: DOS_Mario
// Target Devices: Basys3
// Tool versions: Vivado 2016.1
// Description:
// This module displays player
//
// Dependencies:
//
// Revision:
// Revision 0.01 - Module created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Player
#( parameter
SMALL = 40,
BIG = 80
)
(
input wire [9:0] xpos,
input wire [8:0] ypos,
input wire direction,
input wire size,
input wire fire,
input wire [9:0] hcount_in,
input wire hsync_in,
input wire [9:0] vcount_in,
input wire vsync_in,
input wire blnk_in,
input wire rst,
input wire clk,
input wire [23:0] rgb_in,
input wire [23:0] rom_data,
output reg [10:0] rom_addr,
output reg [9:0] hcount_out,
output reg hsync_out,
output reg [9:0] vcount_out,
output reg vsync_out,
output reg [23:0] rgb_out,
output reg blnk_out
);
localparam ALFA_COLOR = 24'hA3_49_A4;
localparam YRES = 480;
localparam PLAYER_WIDTH = 40;
reg [5:0] player_height;
reg [5:0] player_height_nxt;
reg [23:0] rgb_nxt;
reg [10:0] rom_addr_nxt;
always @(posedge clk or posedge rst) begin
if(rst)
rom_addr <= #1 0;
else
rom_addr <= #1 rom_addr_nxt;
end
always @(posedge clk or posedge rst) begin
if(rst) begin
rgb_out <= #1 0;
hcount_out <= #1 0;
hsync_out <= #1 0;
vcount_out <= #1 0;
vsync_out <= #1 0;
blnk_out <= #1 0;
end
else begin
rgb_out <= #1 rgb_nxt;
hcount_out <= #1 hcount_in;
hsync_out <= #1 hsync_in;
vcount_out <= #1 vcount_in;
vsync_out <= #1 vsync_in;
blnk_out <= #1 blnk_in;
end
end
always @* begin
if(size)
player_height_nxt = BIG;
else
player_height_nxt = SMALL;
end
always@(posedge clk or posedge rst) begin
if(rst) begin
player_height = SMALL;
end
else begin
player_height = player_height_nxt;
end
end
always @* begin
if(direction) begin
rom_addr_nxt = PLAYER_WIDTH*(vcount_in -(YRES - ypos - player_height)) + (PLAYER_WIDTH - 1 - (hcount_in - xpos + 1));
end
else begin
rom_addr_nxt = PLAYER_WIDTH*(vcount_in -(YRES - ypos - player_height)) + ((hcount_in - xpos + 1));
end
end
always @*
begin
if(((YRES - 1 - vcount_in) < (ypos + player_height)) && ((YRES - 1 - vcount_in) >= ypos) && (hcount_in < (xpos+PLAYER_WIDTH) ) && ((xpos) <= hcount_in)) begin
if(rom_data == ALFA_COLOR)
rgb_nxt = rgb_in;
else
rgb_nxt = rom_data;
end
else begin
rgb_nxt = rgb_in;
end
end
endmodule
|
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This bursting read master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post full length bursts until
the length register reaches a value less than a full burst. A single final
burst is then posted and when all the reads return the done bit will be asserted.
To use this master you must simply drive the control signals into this block,
and also read the data from the exposed read FIFO. To read from the exposed FIFO
use the 'user_read_buffer' signal to pop data from the FIFO 'user_buffer_data'.
The signal 'user_data_available' is asserted whenever data is available from the
exposed FIFO.
Update by FabienM <[email protected]>
- adding scfifo verilog model description
*/
`timescale 1 ps / 1 ps
// altera message_off 10230
`define FIFODEPTH_LOG2_DEF 5
/* altera scfifo model rewritten */
module scfifo (
input aclr,
input clock,
input [31:0] data,
output empty,
output [31:0] q,
input rdreq,
output [`FIFODEPTH_LOG2_DEF-1:0] usedw,
input wrreq);
localparam lpm_width = 32;
localparam lpm_numwords = 32; // FIFODEPTH
localparam lpm_showahead = "ON";
localparam use_eab = "ON";
localparam add_ram_output_register = "OFF";
localparam underflow_checking = "OFF";
localparam overflow_checking = "OFF";
assign q = buf_out;
assign empty = buf_empty;
assign usedw = fifo_counter;
reg[lpm_width-1:0] buf_out;
reg buf_empty, buf_full;
reg[lpm_numwords :0] fifo_counter;
// pointer to read and write addresses
reg[`FIFODEPTH_LOG2_DEF-1:0] rd_ptr, wr_ptr;
reg[lpm_width:0] buf_mem[lpm_numwords-1 : 0];
always @(fifo_counter)
begin
buf_empty = (fifo_counter==0);
buf_full = (fifo_counter==lpm_numwords);
end
always @(posedge clock or posedge aclr)
begin
if(aclr)
fifo_counter <= 0;
else if( (!buf_full && wrreq) && ( !buf_empty && rdreq ) )
fifo_counter <= fifo_counter;
else if( !buf_full && wrreq )
fifo_counter <= fifo_counter + 1;
else if( !buf_empty && rdreq )
fifo_counter <= fifo_counter - 1;
else
fifo_counter <= fifo_counter;
end
always @( posedge clock or posedge aclr)
begin
if( aclr )
buf_out <= 0;
else
begin
if( rdreq && !buf_empty )
buf_out <= buf_mem[rd_ptr];
else
buf_out <= buf_out;
end
end
always @(posedge clock)
begin
if( wrreq && !buf_full )
buf_mem[ wr_ptr ] <= data;
else
buf_mem[ wr_ptr ] <= buf_mem[ wr_ptr ];
end
always@(posedge clock or posedge aclr)
begin
if( aclr )
begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else
begin
if( !buf_full && wrreq ) wr_ptr <= wr_ptr + 1;
else wr_ptr <= wr_ptr;
if( !buf_empty && rdreq ) rd_ptr <= rd_ptr + 1;
else rd_ptr <= rd_ptr;
end
end
endmodule
module burst_read_master (
clk,
reset,
// control inputs and outputs
control_fixed_location, // When set the master address will not increment
control_read_base, // Word aligned byte address
control_read_length, // Number of bytes to transfer
control_go,
control_done,
control_early_done,
// user logic inputs and outputs
user_read_buffer,
user_buffer_data,
user_data_available,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_burstcount,
master_waitrequest);
parameter MAXBURSTCOUNT = 16; // in word
parameter BURSTCOUNTWIDTH = 5;
parameter DATAWIDTH = 32;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = `FIFODEPTH_LOG2_DEF;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
output wire control_done;
// don't use this unless you know what you are doing,
// it's going to fire when the last read is posted,
// not when the last data returns!
output wire control_early_done;
// user logic inputs and outputs
input user_read_buffer;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
// internal control signals
reg control_fixed_location_d1;
wire fifo_empty;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
reg [FIFODEPTH_LOG2-1:0] reads_pending;
wire increment_address;
wire [BURSTCOUNTWIDTH-1:0] burst_count;
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire first_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire final_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
reg burst_begin;
wire too_many_reads_pending;
wire [FIFODEPTH_LOG2-1:0] fifo_used;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
// always performing word size accesses,
// increment by the burst count presented
address <= address + (burst_count * BYTEENABLEWIDTH);
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
// always performing word size accesses,
// decrement by the burst count presented
length <= length - (burst_count * BYTEENABLEWIDTH);
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
// all ones, always performing word size accesses
assign master_byteenable = -1;
assign master_burstcount = burst_count;
// need to make sure that the reads have returned before firing the done bit
assign control_done = (length == 0) & (reads_pending == 0);
// advanced feature, you should use 'control_done' if you need all
// the reads to return first
assign control_early_done = (length == 0);
assign master_read = (too_many_reads_pending == 0) & (length != 0);
assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
assign first_short_burst_enable = (burst_boundary_word_address != 0);
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
// if the burst boundary isn't a multiple of 2 then must post a burst of
// 1 to get to a multiple of 2 for the next burst
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 :
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
assign final_short_burst_count = (length / BYTEENABLEWIDTH);
// this will get the transfer back on a burst boundary,
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count :
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address =
(too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
// make sure there are fewer reads posted than room in the FIFO
assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFODEPTH - MAXBURSTCOUNT - 4);
// tracking FIFO
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
reads_pending <= 0;
end
else
begin
if(increment_address == 1)
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending + burst_count;
end
else
begin
// a burst read was posted, but a word returned
reads_pending <= reads_pending + burst_count - 1;
end
end
else
begin
if(master_readdatavalid == 0)
begin
// burst read was not posted and no read returned
reads_pending <= reads_pending;
end
else
begin
// burst read was not posted but a word returned
reads_pending <= reads_pending - 1;
end
end
end
end
// read data feeding user logic
assign user_data_available = !fifo_empty;
scfifo the_master_to_user_fifo (
.aclr (reset),
.clock (clk),
.data (master_readdata),
.empty (fifo_empty),
.q (user_buffer_data),
.rdreq (user_read_buffer),
.usedw (fifo_used),
.wrreq (master_readdatavalid)
);
defparam the_master_to_user_fifo.lpm_width = DATAWIDTH;
defparam the_master_to_user_fifo.lpm_numwords = FIFODEPTH;
defparam the_master_to_user_fifo.lpm_showahead = "ON";
defparam the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_master_to_user_fifo.add_ram_output_register = "OFF";
defparam the_master_to_user_fifo.underflow_checking = "OFF";
defparam the_master_to_user_fifo.overflow_checking = "OFF";
initial begin
$dumpfile("waveform.vcd");
$dumpvars(0, burst_read_master);
end
endmodule
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4.1 (lin64) Build 1149489 Thu Feb 19 16:01:47 MST 2015
//Date : Fri Sep 4 18:33:50 2015
//Host : HomeMegaUbuntu running 64-bit Ubuntu 15.04
//Command : generate_target elink_testbench_wrapper.bd
//Design : elink_testbench_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module elink_testbench_wrapper
(aclk,
aresetn,
csysreq,
done0,
done1,
done2,
error0,
error1,
error2,
reset,
rx_cclk_n,
rx_cclk_p,
start);
input aclk;
input aresetn;
input csysreq;
output done0;
output done1;
output done2;
output error0;
output error1;
output error2;
input reset;
output rx_cclk_n;
output rx_cclk_p;
input start;
wire aclk;
wire aresetn;
wire csysreq;
wire done0;
wire done1;
wire done2;
wire error0;
wire error1;
wire error2;
wire reset;
wire rx_cclk_n;
wire rx_cclk_p;
wire start;
elink_testbench elink_testbench_i
(.aclk(aclk),
.aresetn(aresetn),
.csysreq(csysreq),
.done0(done0),
.done1(done1),
.done2(done2),
.error0(error0),
.error1(error1),
.error2(error2),
.reset(reset),
.rx_cclk_n(rx_cclk_n),
.rx_cclk_p(rx_cclk_p),
.start(start));
endmodule
|
//-----------------------------------------------------------------
// RISC-V Core
// V1.0.1
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014-2019, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
module riscv_multiplier
(
// Inputs
input clk_i
,input rst_i
,input opcode_valid_i
,input inst_mul
,input inst_mulh
,input inst_mulhsu
,input inst_mulhu
,input [ 31:0] opcode_ra_operand_i
,input [ 31:0] opcode_rb_operand_i
,input hold_i
// Outputs
,output [ 31:0] writeback_value_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
//`include "riscv_defs.v"
localparam MULT_STAGES = 2; // 2 or 3
//-------------------------------------------------------------
// Registers / Wires
//-------------------------------------------------------------
reg [31:0] result_e2_q;
reg [31:0] result_e3_q;
reg [32:0] operand_a_e1_q;
reg [32:0] operand_b_e1_q;
reg mulhi_sel_e1_q;
//-------------------------------------------------------------
// Multiplier
//-------------------------------------------------------------
wire [64:0] mult_result_w;
reg [32:0] operand_b_r;
reg [32:0] operand_a_r;
reg [31:0] result_r;
wire mult_inst_w = (inst_mul) ||
(inst_mulh) ||
(inst_mulhsu) ||
(inst_mulhu);
always @ *
begin
if (inst_mulhsu)
operand_a_r = {opcode_ra_operand_i[31], opcode_ra_operand_i[31:0]};
else if (inst_mulh)
operand_a_r = {opcode_ra_operand_i[31], opcode_ra_operand_i[31:0]};
else // MULHU || MUL
operand_a_r = {1'b0, opcode_ra_operand_i[31:0]};
end
always @ *
begin
if (inst_mulhsu)
operand_b_r = {1'b0, opcode_rb_operand_i[31:0]};
else if (inst_mulh)
operand_b_r = {opcode_rb_operand_i[31], opcode_rb_operand_i[31:0]};
else // MULHU || MUL
operand_b_r = {1'b0, opcode_rb_operand_i[31:0]};
end
// Pipeline flops for multiplier
always @(posedge clk_i)
if (rst_i)
begin
operand_a_e1_q <= 33'b0;
operand_b_e1_q <= 33'b0;
mulhi_sel_e1_q <= 1'b0;
end
else if (hold_i)
;
else if (opcode_valid_i && mult_inst_w)
begin
operand_a_e1_q <= operand_a_r;
operand_b_e1_q <= operand_b_r;
mulhi_sel_e1_q <= ~(inst_mul);
end
else
begin
operand_a_e1_q <= 33'b0;
operand_b_e1_q <= 33'b0;
mulhi_sel_e1_q <= 1'b0;
end
assign mult_result_w = {{ 32 {operand_a_e1_q[32]}}, operand_a_e1_q}*{{ 32 {operand_b_e1_q[32]}}, operand_b_e1_q};
always @ *
begin
result_r = mulhi_sel_e1_q ? mult_result_w[63:32] : mult_result_w[31:0];
end
always @(posedge clk_i)
if (rst_i)
result_e2_q <= 32'b0;
else if (~hold_i)
result_e2_q <= result_r;
always @(posedge clk_i)
if (rst_i)
result_e3_q <= 32'b0;
else if (~hold_i)
result_e3_q <= result_e2_q;
assign writeback_value_o = (MULT_STAGES == 3) ? result_e3_q : result_e2_q;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__SDFSTP_FUNCTIONAL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_ps/sky130_fd_sc_hdll__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_hdll__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSTP_FUNCTIONAL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Feb 08 00:47:16 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_clk_wiz_0_0 -prefix
// system_clk_wiz_0_0_ system_clk_wiz_0_0_sim_netlist.v
// Design : system_clk_wiz_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module system_clk_wiz_0_0
(clk_out1,
resetn,
locked,
clk_in1);
output clk_out1;
input resetn;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
wire resetn;
system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked),
.resetn(resetn));
endmodule
module system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
(clk_out1,
resetn,
locked,
clk_in1);
output clk_out1;
input resetn;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_system_clk_wiz_0_0;
wire clk_out1;
wire clk_out1_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfbout_system_clk_wiz_0_0;
wire locked;
wire reset_high;
wire resetn;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_system_clk_wiz_0_0),
.O(clkfbout_buf_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_system_clk_wiz_0_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(9.125000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(36.500000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_system_clk_wiz_0_0),
.CLKFBOUT(clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_system_clk_wiz_0_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_system_clk_wiz_0_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset_high));
LUT1 #(
.INIT(2'h1))
mmcm_adv_inst_i_1
(.I0(resetn),
.O(reset_high));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
`include "asserts.vh"
module queue_tb();
reg [11:0] story_to;
reg clk_i, reset_i;
reg [7:0] dat_i;
reg push_i, pop_i, oe_i;
wire [7:0] dat_o;
wire full_o, empty_o;
wire [2:0] rp_to;
wire [2:0] wp_to;
wire [3:0] room_to;
queue #(
.DEPTH_BITS(3), // 8-deep queue
.DATA_BITS(8) // 8-bit data path for input and output
) q (
.clk_i(clk_i),
.reset_i(reset_i),
.dat_i(dat_i),
.push_i(push_i),
.dat_o(dat_o),
.pop_i(pop_i),
.oe_i(oe_i),
.full_o(full_o),
.empty_o(empty_o),
.rp_to(rp_to),
.wp_to(wp_to),
.room_to(room_to)
);
always begin
#20 clk_i <= ~clk_i;
end
task story;
input [11:0] expected;
begin
story_to = expected;
end
endtask
`DEFASSERT(rp,2,to)
`DEFASSERT(wp,2,to)
`DEFASSERT(room,3,to)
`DEFASSERT0(empty,o)
`DEFASSERT0(full,o)
`DEFASSERT(dat,7,o)
task tick;
begin
wait(clk_i); wait(~clk_i);
end
endtask
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
{clk_i, reset_i, dat_i, push_i, pop_i, oe_i} <= 0;
story(0);
wait(~clk_i);
reset_i <= 1;
tick;
assert_rp(0);
assert_wp(0);
assert_room(8);
assert_dat(0);
assert_empty(1);
assert_full(0);
story(2);
reset_i <= 0;
push_i <= 1;
dat_i <= 8'hFF;
tick;
assert_room(7);
assert_wp(1);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(6);
assert_wp(2);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(5);
assert_wp(3);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(4);
assert_wp(4);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(3);
assert_wp(5);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(2);
assert_wp(6);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(1);
assert_wp(7);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(0);
tick;
assert_room(0);
assert_wp(0);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(1);
tick;
assert_room(0);
assert_wp(0);
assert_rp(0);
assert_dat(0);
assert_empty(0);
assert_full(1);
// Popping the queue should advance the read pointer.
story(3);
push_i <= 0;
pop_i <= 1; // Does NOT drive data outputs.
oe_i <= 1; // THIS does.
tick;
assert_room(1);
assert_wp(0);
assert_rp(1);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(2);
assert_wp(0);
assert_rp(2);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(3);
assert_wp(0);
assert_rp(3);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(4);
assert_wp(0);
assert_rp(4);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(5);
assert_wp(0);
assert_rp(5);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(6);
assert_wp(0);
assert_rp(6);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(7);
assert_wp(0);
assert_rp(7);
assert_dat(255);
assert_empty(0);
assert_full(0);
tick;
assert_room(8);
assert_wp(0);
assert_rp(0);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(0);
assert_rp(0);
assert_dat(255);
assert_empty(1);
assert_full(0);
// The FIFO must support concurrent reads and writes.
// Testing strategy is simple:
// First, we write all $AA bytes to the queue's storage.
// From our previous tests, we know the data bus must be $FF.
story(4);
dat_i <= 8'hAA;
push_i <= 1;
pop_i <= 1; // Does NOT drive data outputs.
oe_i <= 1; // THIS does.
tick;
assert_room(8);
assert_wp(1);
assert_rp(1);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(2);
assert_rp(2);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(3);
assert_rp(3);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(4);
assert_rp(4);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(5);
assert_rp(5);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(6);
assert_rp(6);
assert_dat(255);
assert_empty(1);
assert_full(0);
tick;
assert_room(8);
assert_wp(7);
assert_rp(7);
assert_dat(255);
assert_empty(1);
assert_full(0);
// (after writing the 8th item to the queue,
// we should wrap around, and see the first
// of the overwrites.)
tick;
assert_room(8);
assert_wp(0);
assert_rp(0);
assert_dat(8'hAA);
assert_empty(1);
assert_full(0);
$display("@I Done.");
$stop;
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:58:52 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_8 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_11 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_12 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_14 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_17 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module CORDIC_Arch3_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
overflow_flag, underflow_flag, zero_flag, busy, data_output );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
input clk, rst, beg_fsm_cordic, ack_cordic, operation;
output ready_cordic, overflow_flag, underflow_flag, zero_flag, busy;
wire enab_d_ff4_Zn, enab_d_ff_RB1, enab_RB3, enab_d_ff5_data_out,
d_ff1_operation_out, d_ff1_shift_region_flag_out_0_, d_ff3_sign_out,
enab_d_ff4_Yn, enab_d_ff4_Xn, fmtted_Result_31_, ITER_CONT_net3570591,
ITER_CONT_N5, ITER_CONT_N4, ITER_CONT_N3,
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_SGF,
inst_FPU_PIPELINED_FPADDSUB_N60, inst_FPU_PIPELINED_FPADDSUB_N59,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB__19_net_,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2,
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2,
inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2,
inst_FPU_PIPELINED_FPADDSUB__6_net_,
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_INIT,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_INIT,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_INIT,
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5,
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6,
inst_FPU_PIPELINED_FPADDSUB_enable_Pipeline_input,
d_ff5_data_out_net3570357, reg_Z0_net3570357,
reg_val_muxZ_2stage_net3570357, reg_shift_y_net3570357,
d_ff4_Xn_net3570357, d_ff4_Yn_net3570357, d_ff4_Zn_net3570357,
inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3570555,
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465,
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393,
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447,
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429,
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393,
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447,
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447,
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447,
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429,
inst_FPU_PIPELINED_FPADDSUB_array_comparators_GTComparator_N0,
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0, n529,
n539, n540, n541, n542, n543, n544, n545, n546, n547, n548, n549,
n550, n551, n553, n554, n555, n556, n557, n558, n559, n561, n562,
n563, n564, n565, n567, n569, n570, n571, n577, n585, n586, n587,
n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598,
n599, n600, n601, n602, n603, n604, n605, n607, n608, n609, n611,
n612, n614, n615, n616, n617, n618, n619, n620, n621, n623, n625,
n626, DP_OP_33J164_122_2179_n18, DP_OP_33J164_122_2179_n17,
DP_OP_33J164_122_2179_n16, DP_OP_33J164_122_2179_n15,
DP_OP_33J164_122_2179_n14, DP_OP_33J164_122_2179_n8,
DP_OP_33J164_122_2179_n7, DP_OP_33J164_122_2179_n6,
DP_OP_33J164_122_2179_n5, DP_OP_33J164_122_2179_n4,
DP_OP_33J164_122_2179_n3, DP_OP_33J164_122_2179_n2,
DP_OP_33J164_122_2179_n1, intadd_402_CI, intadd_402_n3, intadd_402_n2,
intadd_402_n1, intadd_403_CI, intadd_403_n3, intadd_403_n2,
intadd_403_n1, intadd_404_CI, intadd_404_SUM_2_, intadd_404_SUM_1_,
intadd_404_SUM_0_, intadd_404_n3, intadd_404_n2, intadd_404_n1, n629,
n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640,
n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662,
n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684,
n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695,
n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706,
n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717,
n718, n719, n720, n721, n722, n723, n724, n725, n726, n727, n728,
n729, n730, n731, n732, n733, n734, n735, n736, n737, n738, n739,
n740, n741, n742, n743, n744, n745, n746, n747, n748, n749, n750,
n751, n752, n753, n754, n755, n756, n757, n758, n759, n760, n761,
n762, n763, n764, n765, n766, n767, n768, n769, n770, n771, n772,
n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783,
n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794,
n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805,
n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816,
n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827,
n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838,
n839, n840, n841, n842, n843, n844, n845, n846, n847, n848, n849,
n850, n851, n852, n853, n854, n855, n856, n857, n858, n859, n860,
n861, n862, n863, n864, n865, n866, n867, n868, n869, n870, n871,
n872, n873, n874, n875, n876, n877, n878, n879, n880, n881, n882,
n883, n884, n885, n886, n887, n888, n889, n890, n891, n892, n893,
n894, n895, n896, n897, n898, n899, n900, n901, n902, n903, n904,
n905, n906, n907, n908, n909, n910, n911, n912, n913, n914, n915,
n916, n917, n918, n919, n920, n921, n922, n923, n924, n925, n926,
n927, n928, n929, n930, n931, n932, n933, n934, n935, n936, n937,
n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, n948,
n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, n959,
n960, n961, n962, n963, n964, n965, n966, n967, n968, n969, n970,
n971, n972, n973, n974, n975, n976, n977, n978, n979, n980, n981,
n982, n983, n984, n985, n986, n987, n988, n989, n990, n991, n992,
n993, n994, n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003,
n1004, n1005, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144,
n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154,
n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164,
n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174,
n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484,
n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494,
n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554,
n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564,
n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574,
n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584,
n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593;
wire [3:0] cont_iter_out;
wire [1:0] cont_var_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] first_mux_X;
wire [31:0] d_ff_Yn;
wire [31:0] first_mux_Y;
wire [31:0] d_ff_Zn;
wire [31:0] first_mux_Z;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [7:0] sh_exp_x;
wire [7:0] sh_exp_y;
wire [25:4] data_out_LUT;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [31:5] result_add_subt;
wire [30:0] mux_sal;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
wire [31:0] inst_FPU_PIPELINED_FPADDSUB_formatted_number_W;
wire [24:1] inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF;
wire [24:2] inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SFG;
wire [7:0] inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW;
wire [25:0] inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR;
wire [7:0] inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW;
wire [48:0] inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR;
wire [25:0] inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR;
wire [4:3] inst_FPU_PIPELINED_FPADDSUB_shft_value_mux_o_EWR;
wire [4:0] inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR;
wire [4:0] inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW;
wire [4:0] inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW;
wire [27:0] inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW;
wire [27:0] inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW;
wire [31:0] inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW;
wire [3:0] inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7;
wire [2:0] inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(n1548), .ENCLK(ITER_CONT_net3570591), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 d_ff5_data_out_clk_gate_Q_reg ( .CLK(
clk), .EN(enab_d_ff5_data_out), .ENCLK(d_ff5_data_out_net3570357),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_17 reg_Z0_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff_RB1), .ENCLK(reg_Z0_net3570357), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_14 reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
reg_val_muxZ_2stage_net3570357), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_12 reg_shift_y_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_RB3), .ENCLK(reg_shift_y_net3570357), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_11 d_ff4_Xn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Xn), .ENCLK(d_ff4_Xn_net3570357), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 d_ff4_Yn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Yn), .ENCLK(d_ff4_Yn_net3570357), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_8 d_ff4_Zn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Zn), .ENCLK(d_ff4_Zn_net3570357), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n626), .ENCLK(
inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3570555), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]),
.ENCLK(inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_2 inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]),
.ENCLK(inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB__19_net_), .ENCLK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]),
.ENCLK(inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_3 inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB_enable_Pipeline_input),
.ENCLK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_4 inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6),
.ENCLK(inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5),
.ENCLK(inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .TE(
1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB__6_net_), .ENCLK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .TE(1'b0) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n1575), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n1570), .Q(
inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(data_in[31]), .CK(reg_Z0_net3570357), .RN(
n1574), .Q(d_ff1_Z[31]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(data_in[30]), .CK(reg_Z0_net3570357), .RN(
n1573), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(data_in[29]), .CK(reg_Z0_net3570357), .RN(
n1569), .Q(d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(data_in[28]), .CK(reg_Z0_net3570357), .RN(
n1574), .Q(d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(data_in[27]), .CK(reg_Z0_net3570357), .RN(
n1571), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(data_in[26]), .CK(reg_Z0_net3570357), .RN(
n1566), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(data_in[25]), .CK(reg_Z0_net3570357), .RN(
n1566), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(data_in[24]), .CK(reg_Z0_net3570357), .RN(
n1568), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(data_in[23]), .CK(reg_Z0_net3570357), .RN(
n1570), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(data_in[22]), .CK(reg_Z0_net3570357), .RN(
n1574), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(data_in[21]), .CK(reg_Z0_net3570357), .RN(
n1568), .Q(d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(data_in[20]), .CK(reg_Z0_net3570357), .RN(
n1570), .Q(d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(data_in[19]), .CK(reg_Z0_net3570357), .RN(
n1569), .Q(d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(data_in[18]), .CK(reg_Z0_net3570357), .RN(
n1566), .Q(d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(data_in[17]), .CK(reg_Z0_net3570357), .RN(
n1571), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(data_in[16]), .CK(reg_Z0_net3570357), .RN(
n1570), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(data_in[15]), .CK(reg_Z0_net3570357), .RN(
n1566), .Q(d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(data_in[14]), .CK(reg_Z0_net3570357), .RN(
n1568), .Q(d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(data_in[13]), .CK(reg_Z0_net3570357), .RN(
n1566), .Q(d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(data_in[12]), .CK(reg_Z0_net3570357), .RN(
n1569), .Q(d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(data_in[11]), .CK(reg_Z0_net3570357), .RN(
n1574), .Q(d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(data_in[10]), .CK(reg_Z0_net3570357), .RN(
n1565), .Q(d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(data_in[9]), .CK(reg_Z0_net3570357), .RN(n1575), .Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(data_in[8]), .CK(reg_Z0_net3570357), .RN(n1572), .Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(data_in[7]), .CK(reg_Z0_net3570357), .RN(n1567), .Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(data_in[6]), .CK(reg_Z0_net3570357), .RN(n1564), .Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(data_in[5]), .CK(reg_Z0_net3570357), .RN(n1565), .Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(data_in[4]), .CK(reg_Z0_net3570357), .RN(n1575), .Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(data_in[3]), .CK(reg_Z0_net3570357), .RN(n1572), .Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(data_in[2]), .CK(reg_Z0_net3570357), .RN(n1567), .Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(data_in[1]), .CK(reg_Z0_net3570357), .RN(n1564), .Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(data_in[0]), .CK(reg_Z0_net3570357), .RN(n1565), .Q(d_ff1_Z[0]) );
DFFRXLTS reg_region_flag_Q_reg_0_ ( .D(shift_region_flag[0]), .CK(
reg_Z0_net3570357), .RN(n1571), .Q(d_ff1_shift_region_flag_out_0_),
.QN(n699) );
DFFRXLTS reg_region_flag_Q_reg_1_ ( .D(shift_region_flag[1]), .CK(
reg_Z0_net3570357), .RN(n1573), .QN(n631) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(sh_exp_y[7]), .CK(reg_shift_y_net3570357), .RN(n1570), .Q(d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(sh_exp_y[6]), .CK(reg_shift_y_net3570357), .RN(n1568), .Q(d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(sh_exp_y[5]), .CK(reg_shift_y_net3570357), .RN(n1573), .Q(d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(sh_exp_y[4]), .CK(reg_shift_y_net3570357), .RN(n1569), .Q(d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(sh_exp_y[3]), .CK(reg_shift_y_net3570357), .RN(n1570), .Q(d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(sh_exp_y[2]), .CK(reg_shift_y_net3570357), .RN(n1571), .Q(d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(sh_exp_y[1]), .CK(reg_shift_y_net3570357), .RN(n1566), .Q(d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(sh_exp_y[0]), .CK(reg_shift_y_net3570357), .RN(n1573), .Q(d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(sh_exp_x[7]), .CK(reg_shift_y_net3570357), .RN(n1568), .Q(d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(sh_exp_x[6]), .CK(reg_shift_y_net3570357), .RN(n1566), .Q(d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(sh_exp_x[5]), .CK(reg_shift_y_net3570357), .RN(n1569), .Q(d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(sh_exp_x[4]), .CK(reg_shift_y_net3570357), .RN(n1566), .Q(d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(sh_exp_x[3]), .CK(reg_shift_y_net3570357), .RN(n1571), .Q(d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(sh_exp_x[2]), .CK(reg_shift_y_net3570357), .RN(n1574), .Q(d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(sh_exp_x[1]), .CK(reg_shift_y_net3570357), .RN(n1566), .Q(d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(sh_exp_x[0]), .CK(reg_shift_y_net3570357), .RN(n1568), .Q(d_ff3_sh_x_out[23]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n551), .CK(reg_shift_y_net3570357), .RN(
n1574), .Q(d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(data_out_LUT[25]), .CK(
reg_shift_y_net3570357), .RN(n1569), .Q(d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n542), .CK(reg_shift_y_net3570357), .RN(
n1573), .Q(d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n543), .CK(reg_shift_y_net3570357), .RN(
n1571), .Q(d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n544), .CK(reg_shift_y_net3570357), .RN(
n1570), .Q(d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n559), .CK(reg_shift_y_net3570357), .RN(
n1574), .Q(d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n557), .CK(reg_shift_y_net3570357), .RN(
n1568), .Q(d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n545), .CK(reg_shift_y_net3570357), .RN(
n1573), .Q(d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n554), .CK(reg_shift_y_net3570357), .RN(
n1569), .Q(d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n548), .CK(reg_shift_y_net3570357), .RN(
n1573), .Q(d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n555), .CK(reg_shift_y_net3570357), .RN(n1571), .Q(d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n1384), .CK(reg_shift_y_net3570357), .RN(
n1573), .Q(d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n553), .CK(reg_shift_y_net3570357), .RN(n1570), .Q(d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n549), .CK(reg_shift_y_net3570357), .RN(n1568), .Q(d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n547), .CK(reg_shift_y_net3570357), .RN(n1570), .Q(d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(data_out_LUT[4]), .CK(reg_shift_y_net3570357),
.RN(n1569), .Q(d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n558), .CK(reg_shift_y_net3570357), .RN(n1566), .Q(d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n550), .CK(reg_shift_y_net3570357), .RN(n1571), .Q(d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n556), .CK(reg_shift_y_net3570357), .RN(n1570), .Q(d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n546), .CK(reg_shift_y_net3570357), .RN(n1571), .Q(d_ff3_LUT_out[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n1593),
.CK(inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3570555), .RN(
n1541), .Q(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6), .CK(
inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3570555), .RN(n1518),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(busy),
.CK(inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3570555), .RN(
n1517), .Q(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3570555), .RN(n1545),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1517),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1522),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1540),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1517),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1516),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1533),
.QN(n649) );
DFFRXLTS d_ff4_Xn_Q_reg_23_ ( .D(n675), .CK(d_ff4_Xn_net3570357), .RN(n1566),
.Q(d_ff_Xn[23]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(first_mux_X[23]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1574), .Q(d_ff2_X[23]), .QN(n698) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(n675), .CK(d_ff4_Yn_net3570357), .RN(n1570),
.Q(d_ff_Yn[23]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_23_ ( .D(first_mux_Y[23]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1574), .Q(d_ff2_Y[23]), .QN(n700) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n675), .CK(d_ff4_Zn_net3570357), .RN(n1569),
.Q(d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(first_mux_Z[23]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1573), .Q(d_ff2_Z[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1529),
.QN(n648) );
DFFRXLTS d_ff4_Xn_Q_reg_24_ ( .D(n674), .CK(d_ff4_Xn_net3570357), .RN(n1571),
.Q(d_ff_Xn[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(n674), .CK(d_ff4_Yn_net3570357), .RN(n1574),
.Q(d_ff_Yn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n674), .CK(d_ff4_Zn_net3570357), .RN(n1567),
.Q(d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(first_mux_Z[24]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1564), .Q(d_ff2_Z[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1520),
.QN(n647) );
DFFRXLTS d_ff4_Xn_Q_reg_25_ ( .D(n673), .CK(d_ff4_Xn_net3570357), .RN(n1565),
.Q(d_ff_Xn[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(n673), .CK(d_ff4_Yn_net3570357), .RN(n1575),
.Q(d_ff_Yn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n673), .CK(d_ff4_Zn_net3570357), .RN(n1572),
.Q(d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(first_mux_Z[25]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1567), .Q(d_ff2_Z[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[26]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1530),
.QN(n646) );
DFFRXLTS d_ff4_Xn_Q_reg_26_ ( .D(n672), .CK(d_ff4_Xn_net3570357), .RN(n1564),
.Q(d_ff_Xn[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(n672), .CK(d_ff4_Yn_net3570357), .RN(n1570),
.Q(d_ff_Yn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n672), .CK(d_ff4_Zn_net3570357), .RN(n1573),
.Q(d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(first_mux_Z[26]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1568), .Q(d_ff2_Z[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[27]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1537),
.QN(n645) );
DFFRXLTS d_ff4_Xn_Q_reg_27_ ( .D(n671), .CK(d_ff4_Xn_net3570357), .RN(n1573),
.Q(d_ff_Xn[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(n671), .CK(d_ff4_Yn_net3570357), .RN(n1574),
.Q(d_ff_Yn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n671), .CK(d_ff4_Zn_net3570357), .RN(n1569),
.Q(d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(first_mux_Z[27]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1572), .Q(d_ff2_Z[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[28]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1541),
.QN(n644) );
DFFRXLTS d_ff4_Xn_Q_reg_28_ ( .D(n670), .CK(d_ff4_Xn_net3570357), .RN(n1567),
.Q(d_ff_Xn[28]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(n670), .CK(d_ff4_Yn_net3570357), .RN(n1564),
.Q(d_ff_Yn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n670), .CK(d_ff4_Zn_net3570357), .RN(n1565),
.Q(d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(first_mux_Z[28]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1575), .Q(d_ff2_Z[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[29]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1516),
.QN(n643) );
DFFRXLTS d_ff4_Xn_Q_reg_29_ ( .D(n669), .CK(d_ff4_Xn_net3570357), .RN(n1572),
.Q(d_ff_Xn[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(n669), .CK(d_ff4_Yn_net3570357), .RN(n1567),
.Q(d_ff_Yn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n669), .CK(d_ff4_Zn_net3570357), .RN(n1564),
.Q(d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(first_mux_Z[29]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n853), .Q(d_ff2_Z[29]) );
DFFRXLTS d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Xn_net3570357), .RN(n1565), .Q(d_ff_Xn[30]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(first_mux_X[30]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1575), .Q(d_ff2_X[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Yn_net3570357), .RN(n853), .Q(d_ff_Yn[30]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_30_ ( .D(first_mux_Y[30]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1572), .Q(d_ff2_Y[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Zn_net3570357), .RN(n1567), .Q(d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(first_mux_Z[30]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1564), .Q(d_ff2_Z[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(
n589), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1516), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .QN(n691) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1514), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1519), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1532), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[26]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1523), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[27]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1524), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1520), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23]), .QN(n692) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[27]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1519), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[28]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1520), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[29]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1530), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[30]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1538), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1539),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1545),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1517),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1514),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1535),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1520),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1515),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1516),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1533),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1543), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1543),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1543), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1524),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1543), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1543),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1543), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1520),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1544), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1543),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1543), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1544),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1515), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1544),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1515), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1528),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1544), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1515),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1544), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1526),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1515), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1544),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1515), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1532),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1545), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1515),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1544), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1532),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1517), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1516),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1532), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRXLTS d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Xn_net3570357), .RN(n1565), .Q(d_ff_Xn[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(first_mux_X[22]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1575), .Q(d_ff2_X[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(d_ff2_X[22]), .CK(reg_shift_y_net3570357), .RN(n1563), .Q(d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Yn_net3570357), .RN(n1552), .Q(d_ff_Yn[22]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_22_ ( .D(first_mux_Y[22]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1555), .Q(d_ff2_Y[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(d_ff2_Y[22]), .CK(reg_shift_y_net3570357), .RN(n1553), .Q(d_ff3_sh_y_out[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Zn_net3570357), .RN(n1560), .Q(d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(first_mux_Z[22]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1563), .Q(d_ff2_Z[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1530), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1538),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Xn_net3570357), .RN(n1552), .Q(d_ff_Xn[15]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_15_ ( .D(first_mux_X[15]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1555), .Q(d_ff2_X[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(d_ff2_X[15]), .CK(reg_shift_y_net3570357), .RN(n1553), .Q(d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Yn_net3570357), .RN(n1560), .Q(d_ff_Yn[15]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_15_ ( .D(first_mux_Y[15]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1563), .Q(d_ff2_Y[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(d_ff2_Y[15]), .CK(reg_shift_y_net3570357), .RN(n1558), .Q(d_ff3_sh_y_out[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Zn_net3570357), .RN(n1556), .Q(d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(first_mux_Z[15]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1562), .Q(d_ff2_Z[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1534), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1532),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Xn_net3570357), .RN(n1558), .Q(d_ff_Xn[18]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_18_ ( .D(first_mux_X[18]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1558), .Q(d_ff2_X[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(d_ff2_X[18]), .CK(reg_shift_y_net3570357), .RN(n1559), .Q(d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Yn_net3570357), .RN(n1561), .Q(d_ff_Yn[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(first_mux_Y[18]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1557), .Q(d_ff2_Y[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(d_ff2_Y[18]), .CK(reg_shift_y_net3570357), .RN(n1556), .Q(d_ff3_sh_y_out[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Zn_net3570357), .RN(n1558), .Q(d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(first_mux_Z[18]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1557), .Q(d_ff2_Z[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1533), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1519),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1539),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]) );
DFFRXLTS d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Xn_net3570357), .RN(n1559), .Q(d_ff_Xn[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_21_ ( .D(first_mux_X[21]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1559), .Q(d_ff2_X[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(d_ff2_X[21]), .CK(reg_shift_y_net3570357), .RN(n1562), .Q(d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Yn_net3570357), .RN(n1556), .Q(d_ff_Yn[21]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_21_ ( .D(first_mux_Y[21]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1557), .Q(d_ff2_Y[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(d_ff2_Y[21]), .CK(reg_shift_y_net3570357), .RN(n1554), .Q(d_ff3_sh_y_out[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Zn_net3570357), .RN(n1554), .Q(d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(first_mux_Z[21]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1559), .Q(d_ff2_Z[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1538), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1537),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Xn_net3570357), .RN(n1559), .Q(d_ff_Xn[19]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_19_ ( .D(first_mux_X[19]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1558), .Q(d_ff2_X[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(d_ff2_X[19]), .CK(reg_shift_y_net3570357), .RN(n1555), .Q(d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Yn_net3570357), .RN(n1553), .Q(d_ff_Yn[19]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(first_mux_Y[19]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1560), .Q(d_ff2_Y[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(d_ff2_Y[19]), .CK(reg_shift_y_net3570357), .RN(n1563), .Q(d_ff3_sh_y_out[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Zn_net3570357), .RN(n1552), .Q(d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(first_mux_Z[19]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1555), .Q(d_ff2_Z[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1522), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1528),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1521),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1518),
.QN(n642) );
DFFRXLTS d_ff4_Xn_Q_reg_20_ ( .D(n668), .CK(d_ff4_Xn_net3570357), .RN(n1553),
.Q(d_ff_Xn[20]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_20_ ( .D(first_mux_X[20]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1560), .Q(d_ff2_X[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(d_ff2_X[20]), .CK(reg_shift_y_net3570357), .RN(n1563), .Q(d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n668), .CK(d_ff4_Yn_net3570357), .RN(n1552),
.Q(d_ff_Yn[20]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_20_ ( .D(first_mux_Y[20]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1555), .Q(d_ff2_Y[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(d_ff2_Y[20]), .CK(reg_shift_y_net3570357), .RN(n1562), .Q(d_ff3_sh_y_out[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n668), .CK(d_ff4_Zn_net3570357), .RN(n1562),
.Q(d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(first_mux_Z[20]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1559), .Q(d_ff2_Z[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1514), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1523),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Xn_net3570357), .RN(n1561), .Q(d_ff_Xn[17]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_17_ ( .D(first_mux_X[17]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1554), .Q(d_ff2_X[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(d_ff2_X[17]), .CK(reg_shift_y_net3570357), .RN(n1556), .Q(d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Yn_net3570357), .RN(n1562), .Q(d_ff_Yn[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(first_mux_Y[17]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1558), .Q(d_ff2_Y[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(d_ff2_Y[17]), .CK(reg_shift_y_net3570357), .RN(n1558), .Q(d_ff3_sh_y_out[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Zn_net3570357), .RN(n1559), .Q(d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(first_mux_Z[17]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1557), .Q(d_ff2_Z[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1533), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1514),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1535),
.QN(n641) );
DFFRXLTS d_ff4_Xn_Q_reg_4_ ( .D(n667), .CK(d_ff4_Xn_net3570357), .RN(n1556),
.Q(d_ff_Xn[4]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(first_mux_X[4]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1558), .Q(d_ff2_X[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(d_ff2_X[4]), .CK(reg_shift_y_net3570357),
.RN(n1557), .Q(d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n667), .CK(d_ff4_Yn_net3570357), .RN(n1562),
.Q(d_ff_Yn[4]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_4_ ( .D(first_mux_Y[4]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1559), .Q(d_ff2_Y[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(d_ff2_Y[4]), .CK(reg_shift_y_net3570357),
.RN(n1561), .Q(d_ff3_sh_y_out[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n667), .CK(d_ff4_Zn_net3570357), .RN(n1554),
.Q(d_ff_Zn[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(first_mux_Z[4]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1556), .Q(d_ff2_Z[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1524), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1536),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1540),
.QN(n640) );
DFFRXLTS d_ff4_Xn_Q_reg_6_ ( .D(n666), .CK(d_ff4_Xn_net3570357), .RN(n1557),
.Q(d_ff_Xn[6]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(first_mux_X[6]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1554), .Q(d_ff2_X[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(d_ff2_X[6]), .CK(reg_shift_y_net3570357),
.RN(n1559), .Q(d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n666), .CK(d_ff4_Yn_net3570357), .RN(n1561),
.Q(d_ff_Yn[6]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(first_mux_Y[6]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1558), .Q(d_ff2_Y[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(d_ff2_Y[6]), .CK(reg_shift_y_net3570357),
.RN(n1556), .Q(d_ff3_sh_y_out[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n666), .CK(d_ff4_Zn_net3570357), .RN(n1554),
.Q(d_ff_Zn[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(first_mux_Z[6]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1562), .Q(d_ff2_Z[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1518), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1525),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Xn_net3570357), .RN(n1554), .Q(d_ff_Xn[13]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_13_ ( .D(first_mux_X[13]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1559), .Q(d_ff2_X[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(d_ff2_X[13]), .CK(reg_shift_y_net3570357), .RN(n1561), .Q(d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Yn_net3570357), .RN(n1558), .Q(d_ff_Yn[13]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_13_ ( .D(first_mux_Y[13]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1556), .Q(d_ff2_Y[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(d_ff2_Y[13]), .CK(reg_shift_y_net3570357), .RN(n1557), .Q(d_ff3_sh_y_out[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Zn_net3570357), .RN(n1554), .Q(d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(first_mux_Z[13]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1554), .Q(d_ff2_Z[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1525), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1525),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Xn_net3570357), .RN(n1559), .Q(d_ff_Xn[16]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_16_ ( .D(first_mux_X[16]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1561), .Q(d_ff2_X[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(d_ff2_X[16]), .CK(reg_shift_y_net3570357), .RN(n1562), .Q(d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Yn_net3570357), .RN(n1557), .Q(d_ff_Yn[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_16_ ( .D(first_mux_Y[16]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1554), .Q(d_ff2_Y[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(d_ff2_Y[16]), .CK(reg_shift_y_net3570357), .RN(n1562), .Q(d_ff3_sh_y_out[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Zn_net3570357), .RN(n1562), .Q(d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(first_mux_Z[16]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1563), .Q(d_ff2_Z[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n892), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n854), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n858),
.QN(n639) );
DFFRXLTS d_ff4_Xn_Q_reg_8_ ( .D(n665), .CK(d_ff4_Xn_net3570357), .RN(n1552),
.Q(d_ff_Xn[8]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(first_mux_X[8]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1555), .Q(d_ff2_X[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(d_ff2_X[8]), .CK(reg_shift_y_net3570357),
.RN(n1553), .Q(d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n665), .CK(d_ff4_Yn_net3570357), .RN(n857),
.Q(d_ff_Yn[8]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(first_mux_Y[8]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1560), .Q(d_ff2_Y[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(d_ff2_Y[8]), .CK(reg_shift_y_net3570357),
.RN(n1563), .Q(d_ff3_sh_y_out[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n665), .CK(d_ff4_Zn_net3570357), .RN(n1552),
.Q(d_ff_Zn[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(first_mux_Z[8]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1555), .Q(d_ff2_Z[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n855), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1514),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Xn_net3570357), .RN(n1553), .Q(d_ff_Xn[11]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_11_ ( .D(first_mux_X[11]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n857), .Q(d_ff2_X[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(d_ff2_X[11]), .CK(reg_shift_y_net3570357), .RN(n1558), .Q(d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Yn_net3570357), .RN(n1558), .Q(d_ff_Yn[11]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_11_ ( .D(first_mux_Y[11]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1559), .Q(d_ff2_Y[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(d_ff2_Y[11]), .CK(reg_shift_y_net3570357), .RN(n1561), .Q(d_ff3_sh_y_out[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Zn_net3570357), .RN(n1557), .Q(d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(first_mux_Z[11]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1558), .Q(d_ff2_Z[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1514), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1544),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Xn_net3570357), .RN(n1562), .Q(d_ff_Xn[14]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_14_ ( .D(first_mux_X[14]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1557), .Q(d_ff2_X[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(d_ff2_X[14]), .CK(reg_shift_y_net3570357), .RN(n1557), .Q(d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Yn_net3570357), .RN(n1559), .Q(d_ff_Yn[14]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_14_ ( .D(first_mux_Y[14]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1561), .Q(d_ff2_Y[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(d_ff2_Y[14]), .CK(reg_shift_y_net3570357), .RN(n1552), .Q(d_ff3_sh_y_out[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Zn_net3570357), .RN(n1555), .Q(d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(first_mux_Z[14]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1553), .Q(d_ff2_Z[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1534), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1545),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n858),
.QN(n638) );
DFFRXLTS d_ff4_Xn_Q_reg_10_ ( .D(n664), .CK(d_ff4_Xn_net3570357), .RN(n857),
.Q(d_ff_Xn[10]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_10_ ( .D(first_mux_X[10]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1560), .Q(d_ff2_X[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(d_ff2_X[10]), .CK(reg_shift_y_net3570357), .RN(n1563), .Q(d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n664), .CK(d_ff4_Yn_net3570357), .RN(n1552),
.Q(d_ff_Yn[10]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_10_ ( .D(first_mux_Y[10]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1555), .Q(d_ff2_Y[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(d_ff2_Y[10]), .CK(reg_shift_y_net3570357), .RN(n1553), .Q(d_ff3_sh_y_out[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n664), .CK(d_ff4_Zn_net3570357), .RN(n857),
.Q(d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(first_mux_Z[10]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1563), .Q(d_ff2_Z[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n855), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1524),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n855),
.QN(n637) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(n663), .CK(d_ff4_Xn_net3570357), .RN(n1552),
.Q(d_ff_Xn[12]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_12_ ( .D(first_mux_X[12]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1555), .Q(d_ff2_X[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(d_ff2_X[12]), .CK(reg_shift_y_net3570357), .RN(n1553), .Q(d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n663), .CK(d_ff4_Yn_net3570357), .RN(n857),
.Q(d_ff_Yn[12]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_12_ ( .D(first_mux_Y[12]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1560), .Q(d_ff2_Y[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(d_ff2_Y[12]), .CK(reg_shift_y_net3570357), .RN(n1563), .Q(d_ff3_sh_y_out[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n663), .CK(d_ff4_Zn_net3570357), .RN(n1552),
.Q(d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(first_mux_Z[12]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1555), .Q(d_ff2_Z[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_INIT), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n858), .Q(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n855), .Q(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n854), .Q(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1536), .Q(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1520),
.Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1527), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Xn_net3570357), .RN(n1553), .Q(d_ff_Xn[31]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(first_mux_X[31]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n857), .Q(d_ff2_X[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(d_ff2_X[31]), .CK(reg_shift_y_net3570357), .RN(n1551), .Q(d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Yn_net3570357), .RN(n853), .Q(d_ff_Yn[31]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_31_ ( .D(first_mux_Y[31]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1557), .Q(d_ff2_Y[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(d_ff2_Y[31]), .CK(reg_shift_y_net3570357), .RN(n1554), .Q(d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Zn_net3570357), .RN(n1556), .Q(d_ff_Zn[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(first_mux_Z[31]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1558), .Q(d_ff2_Z[31]) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(d_ff2_Z[31]), .CK(reg_shift_y_net3570357),
.RN(n1557), .Q(d_ff3_sign_out) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_INIT), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n855), .Q(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n892), .Q(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n854), .Q(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1519), .Q(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1542), .Q(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1524), .Q(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1542), .Q(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1543), .Q(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1516),
.QN(n636) );
DFFRXLTS d_ff4_Xn_Q_reg_0_ ( .D(n662), .CK(d_ff4_Xn_net3570357), .RN(n1554),
.Q(d_ff_Xn[0]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_0_ ( .D(first_mux_X[0]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1556), .Q(d_ff2_X[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(d_ff2_X[0]), .CK(reg_shift_y_net3570357),
.RN(n1550), .Q(d_ff3_sh_x_out[0]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n662), .CK(d_ff4_Yn_net3570357), .RN(n1569),
.Q(d_ff_Yn[0]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(first_mux_Y[0]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1568), .Q(d_ff2_Y[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(d_ff2_Y[0]), .CK(reg_shift_y_net3570357),
.RN(n1571), .Q(d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n662), .CK(d_ff4_Zn_net3570357), .RN(n1550),
.Q(d_ff_Zn[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(first_mux_Z[0]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1569), .Q(d_ff2_Z[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1530), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1518),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1538), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1523),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1529),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1531),
.QN(n635) );
DFFRXLTS d_ff4_Xn_Q_reg_1_ ( .D(n661), .CK(d_ff4_Xn_net3570357), .RN(n1571),
.Q(d_ff_Xn[1]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_1_ ( .D(first_mux_X[1]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1559), .Q(d_ff2_X[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(d_ff2_X[1]), .CK(reg_shift_y_net3570357),
.RN(n1550), .Q(d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n661), .CK(d_ff4_Yn_net3570357), .RN(n1569),
.Q(d_ff_Yn[1]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_1_ ( .D(first_mux_Y[1]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1570), .Q(d_ff2_Y[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(d_ff2_Y[1]), .CK(reg_shift_y_net3570357),
.RN(n1566), .Q(d_ff3_sh_y_out[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n661), .CK(d_ff4_Zn_net3570357), .RN(n1576),
.Q(d_ff_Zn[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(first_mux_Z[1]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1551), .Q(d_ff2_Z[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1515), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1522),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1521), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1533),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1519),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1523),
.QN(n634) );
DFFRXLTS d_ff4_Xn_Q_reg_2_ ( .D(n660), .CK(d_ff4_Xn_net3570357), .RN(n1549),
.Q(d_ff_Xn[2]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_2_ ( .D(first_mux_X[2]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1576), .Q(d_ff2_X[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(d_ff2_X[2]), .CK(reg_shift_y_net3570357),
.RN(n1551), .Q(d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n660), .CK(d_ff4_Yn_net3570357), .RN(n1549),
.Q(d_ff_Yn[2]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_2_ ( .D(first_mux_Y[2]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1576), .Q(d_ff2_Y[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(d_ff2_Y[2]), .CK(reg_shift_y_net3570357),
.RN(n1551), .Q(d_ff3_sh_y_out[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n660), .CK(d_ff4_Zn_net3570357), .RN(n1549),
.Q(d_ff_Zn[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(first_mux_Z[2]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1576), .Q(d_ff2_Z[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1529), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1545),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1544), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1521),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1518),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1514),
.QN(n633) );
DFFRXLTS d_ff4_Xn_Q_reg_3_ ( .D(n659), .CK(d_ff4_Xn_net3570357), .RN(n1551),
.Q(d_ff_Xn[3]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_3_ ( .D(first_mux_X[3]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1550), .Q(d_ff2_X[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(d_ff2_X[3]), .CK(reg_shift_y_net3570357),
.RN(n1550), .Q(d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n659), .CK(d_ff4_Yn_net3570357), .RN(n1550),
.Q(d_ff_Yn[3]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_3_ ( .D(first_mux_Y[3]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1550), .Q(d_ff2_Y[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(d_ff2_Y[3]), .CK(reg_shift_y_net3570357),
.RN(n1550), .Q(d_ff3_sh_y_out[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n659), .CK(d_ff4_Zn_net3570357), .RN(n1550),
.Q(d_ff_Zn[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(first_mux_Z[3]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1550), .Q(d_ff2_Z[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1535), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1526),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1532), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1530),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1528),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Xn_net3570357), .RN(n1550), .Q(d_ff_Xn[5]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(first_mux_X[5]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1550), .Q(d_ff2_X[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(d_ff2_X[5]), .CK(reg_shift_y_net3570357),
.RN(n1550), .Q(d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Yn_net3570357), .RN(n1550), .Q(d_ff_Yn[5]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_5_ ( .D(first_mux_Y[5]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1551), .Q(d_ff2_Y[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(d_ff2_Y[5]), .CK(reg_shift_y_net3570357),
.RN(n856), .Q(d_ff3_sh_y_out[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Zn_net3570357), .RN(n529), .Q(d_ff_Zn[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(first_mux_Z[5]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n529), .Q(d_ff2_Z[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1538), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1514),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1524), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1538),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1524),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Xn_net3570357), .RN(n529), .Q(d_ff_Xn[7]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(first_mux_X[7]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n529), .Q(d_ff2_X[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(d_ff2_X[7]), .CK(reg_shift_y_net3570357),
.RN(n529), .Q(d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Yn_net3570357), .RN(n856), .Q(d_ff_Yn[7]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_7_ ( .D(first_mux_Y[7]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n529), .Q(d_ff2_Y[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(d_ff2_Y[7]), .CK(reg_shift_y_net3570357),
.RN(n1549), .Q(d_ff3_sh_y_out[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Zn_net3570357), .RN(n1576), .Q(d_ff_Zn[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(first_mux_Z[7]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1551), .Q(d_ff2_Z[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1524), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1541),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1522), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1536),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1540),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1538),
.QN(n632) );
DFFRXLTS d_ff4_Xn_Q_reg_9_ ( .D(n658), .CK(d_ff4_Xn_net3570357), .RN(n1549),
.Q(d_ff_Xn[9]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(first_mux_X[9]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1576), .Q(d_ff2_X[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(d_ff2_X[9]), .CK(reg_shift_y_net3570357),
.RN(n1551), .Q(d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n658), .CK(d_ff4_Yn_net3570357), .RN(n1549),
.Q(d_ff_Yn[9]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_9_ ( .D(first_mux_Y[9]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1576), .Q(d_ff2_Y[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(d_ff2_Y[9]), .CK(reg_shift_y_net3570357),
.RN(n1551), .Q(d_ff3_sh_y_out[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n658), .CK(d_ff4_Zn_net3570357), .RN(n1549),
.Q(d_ff_Zn[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(first_mux_Z[9]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1576), .Q(d_ff2_Z[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1536), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1534),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1522), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1524),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1529),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_INIT), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1536), .Q(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1518),
.Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1519),
.Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1519), .Q(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1531),
.Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1537), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1536), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1541),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1528), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1529),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1535),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1521), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1536),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1539),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1537), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1529),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1535),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1534), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1528),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1536),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1531), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1522),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1535),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1529), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1539),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1521),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1536), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1526),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1524),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1541), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1518),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1536),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1531), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1528),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1535),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1541), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1540),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1526),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1531), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1539),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1534),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1541), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1531),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1526),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1539), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1534),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1541),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1540), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1534),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1541),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1526), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1531),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1539),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1534),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1516), .Q(
inst_FPU_PIPELINED_FPADDSUB_N60) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1542),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1542),
.QN(n694) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1542), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3570447), .RN(n1542),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3570447), .RN(n1542),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFSX2TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n853), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
CMPR32X2TS DP_OP_33J164_122_2179_U9 ( .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]), .B(n1391), .C(
DP_OP_33J164_122_2179_n18), .CO(DP_OP_33J164_122_2179_n8), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_33J164_122_2179_U8 ( .A(DP_OP_33J164_122_2179_n17), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]), .C(
DP_OP_33J164_122_2179_n8), .CO(DP_OP_33J164_122_2179_n7), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_33J164_122_2179_U7 ( .A(DP_OP_33J164_122_2179_n16), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]), .C(
DP_OP_33J164_122_2179_n7), .CO(DP_OP_33J164_122_2179_n6), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_33J164_122_2179_U6 ( .A(DP_OP_33J164_122_2179_n15), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]), .C(
DP_OP_33J164_122_2179_n6), .CO(DP_OP_33J164_122_2179_n5), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS intadd_404_U4 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[24]),
.B(n1498), .C(intadd_404_CI), .CO(intadd_404_n3), .S(intadd_404_SUM_0_) );
CMPR32X2TS intadd_404_U3 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25]),
.B(n1497), .C(intadd_404_n3), .CO(intadd_404_n2), .S(intadd_404_SUM_1_) );
CMPR32X2TS intadd_404_U2 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[26]),
.B(n1511), .C(intadd_404_n2), .CO(intadd_404_n1), .S(intadd_404_SUM_2_) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(reg_shift_y_net3570357), .RN(
n1551), .Q(d_ff3_LUT_out[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_N59), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1517),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n1512) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n593), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1514),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .QN(n1508) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(
n619), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1520), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .QN(n1507) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n594), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1535),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .QN(n1504) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(
n604), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1517), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .QN(n1503) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(
n618), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1524), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .QN(n1502) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(
n611), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1532), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .QN(n1501) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n601), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1522),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .QN(n1499) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(
n605), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1536), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .QN(n1496) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(
n620), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1514), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .QN(n1495) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n602), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1534),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .QN(n1494) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(
n615), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1541), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .QN(n1493) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n595), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1528),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .QN(n1491) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(
n614), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1526), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .QN(n1490) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(
n617), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1537), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .QN(n1488) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(
n603), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n858), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .QN(n1487) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n597), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1536),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .QN(n1486) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(
n609), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1525), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .QN(n1485) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n599), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1518),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .QN(n1484) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_Ready_reg_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1520), .QN(n1481) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ (
.D(n1593), .CK(clk), .RN(n1529), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(
n1476) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(
n591), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1534), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .QN(n1472) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(
n590), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1530), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .QN(n1471) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1541), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .QN(n1469) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(
n587), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1520), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .QN(n1467) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(
n586), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1519), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .QN(n1460) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n569), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n855),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .QN(n1457) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n562), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1516),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .QN(n1456) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1526), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .QN(n1454) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1540), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .QN(n1453) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(
n623), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1544), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .QN(n1451) );
DFFRX1TS VAR_CONT_temp_reg_0_ ( .D(n540), .CK(clk), .RN(n853), .Q(
cont_var_out[0]), .QN(n1448) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1541), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .QN(n1447) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1524), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .QN(n1445) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n1570), .Q(
inst_CORDIC_FSM_v3_state_reg[2]), .QN(n1444) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1535), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .QN(n1436) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1527),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n1434) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n858),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n1432) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1521), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .QN(n1431) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1521),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n1430) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1541), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .QN(n1428) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1537), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .QN(n1426) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1538), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .QN(n1425) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1540), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .QN(n1424) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1530), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .QN(n1422) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1539), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .QN(n1421) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(
n607), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1517), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .QN(n1419) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(
n612), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1521), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .QN(n1418) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1531), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .QN(n1415) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1534), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .QN(n1413) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(
n585), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1533), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .QN(n1412) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n563), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1544),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .QN(n1411) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n561), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1518),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .QN(n1410) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(
n588), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1516), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .QN(n1409) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n570), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1536),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .QN(n1405) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n564), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1532),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .QN(n1400) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1540), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .QN(n1397) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n1571), .Q(
inst_CORDIC_FSM_v3_state_reg[1]), .QN(n1396) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1534), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .QN(n1394) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1521), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .QN(n1392) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1537), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .QN(n1390) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1538), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .QN(n1389) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1537), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .QN(n1387) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1538), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .QN(n1386) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(mux_sal[23]), .CK(
d_ff5_data_out_net3570357), .RN(n1569), .Q(data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(mux_sal[24]), .CK(
d_ff5_data_out_net3570357), .RN(n1572), .Q(data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(mux_sal[25]), .CK(
d_ff5_data_out_net3570357), .RN(n853), .Q(data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(mux_sal[26]), .CK(
d_ff5_data_out_net3570357), .RN(n1566), .Q(data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(mux_sal[27]), .CK(
d_ff5_data_out_net3570357), .RN(n1570), .Q(data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(mux_sal[28]), .CK(
d_ff5_data_out_net3570357), .RN(n1575), .Q(data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(mux_sal[29]), .CK(
d_ff5_data_out_net3570357), .RN(n1567), .Q(data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(mux_sal[30]), .CK(
d_ff5_data_out_net3570357), .RN(n1572), .Q(data_output[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1542),
.Q(underflow_flag) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_GTComparator_N0), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1542),
.Q(overflow_flag) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(mux_sal[22]), .CK(
d_ff5_data_out_net3570357), .RN(n1560), .Q(data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(mux_sal[15]), .CK(
d_ff5_data_out_net3570357), .RN(n1561), .Q(data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(mux_sal[18]), .CK(
d_ff5_data_out_net3570357), .RN(n1559), .Q(data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(mux_sal[21]), .CK(
d_ff5_data_out_net3570357), .RN(n1557), .Q(data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(mux_sal[19]), .CK(
d_ff5_data_out_net3570357), .RN(n1552), .Q(data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(mux_sal[20]), .CK(
d_ff5_data_out_net3570357), .RN(n1554), .Q(data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(mux_sal[17]), .CK(
d_ff5_data_out_net3570357), .RN(n1556), .Q(data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(mux_sal[4]), .CK(
d_ff5_data_out_net3570357), .RN(n1561), .Q(data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(mux_sal[6]), .CK(
d_ff5_data_out_net3570357), .RN(n1557), .Q(data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(mux_sal[13]), .CK(
d_ff5_data_out_net3570357), .RN(n1554), .Q(data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(mux_sal[16]), .CK(
d_ff5_data_out_net3570357), .RN(n1554), .Q(data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(mux_sal[8]), .CK(
d_ff5_data_out_net3570357), .RN(n1560), .Q(data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(mux_sal[11]), .CK(
d_ff5_data_out_net3570357), .RN(n1558), .Q(data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(mux_sal[14]), .CK(
d_ff5_data_out_net3570357), .RN(n1563), .Q(data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(mux_sal[10]), .CK(
d_ff5_data_out_net3570357), .RN(n1560), .Q(data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(mux_sal[12]), .CK(
d_ff5_data_out_net3570357), .RN(n1560), .Q(data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(fmtted_Result_31_), .CK(
d_ff5_data_out_net3570357), .RN(n857), .Q(data_output[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(mux_sal[0]), .CK(
d_ff5_data_out_net3570357), .RN(n1549), .Q(data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(mux_sal[1]), .CK(
d_ff5_data_out_net3570357), .RN(n1561), .Q(data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(mux_sal[2]), .CK(
d_ff5_data_out_net3570357), .RN(n1549), .Q(data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(mux_sal[3]), .CK(
d_ff5_data_out_net3570357), .RN(n1550), .Q(data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(mux_sal[5]), .CK(
d_ff5_data_out_net3570357), .RN(n1576), .Q(data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(mux_sal[7]), .CK(
d_ff5_data_out_net3570357), .RN(n1549), .Q(data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(mux_sal[9]), .CK(
d_ff5_data_out_net3570357), .RN(n1549), .Q(data_output[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1526),
.Q(zero_flag) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5), .CK(
inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3570555), .RN(n1530),
.Q(busy) );
CMPR32X2TS DP_OP_33J164_122_2179_U5 ( .A(DP_OP_33J164_122_2179_n14), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]), .C(
DP_OP_33J164_122_2179_n5), .CO(DP_OP_33J164_122_2179_n4), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_33J164_122_2179_U4 ( .A(n1391), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]), .C(
DP_OP_33J164_122_2179_n4), .CO(DP_OP_33J164_122_2179_n3), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_33J164_122_2179_U3 ( .A(n1391), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]), .C(
DP_OP_33J164_122_2179_n3), .CO(DP_OP_33J164_122_2179_n2), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_33J164_122_2179_U2 ( .A(n1391), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]), .C(
DP_OP_33J164_122_2179_n2), .CO(DP_OP_33J164_122_2179_n1), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1518), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]) );
DFFSXLTS R_0 ( .D(n1513), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(n854), .Q(n1577) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(
n1590), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(
n1540), .Q(n1404) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(
n1591), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(
n1519), .Q(n1403) );
DFFRX2TS ITER_CONT_temp_reg_0_ ( .D(n1393), .CK(ITER_CONT_net3570591), .RN(
n1572), .Q(cont_iter_out[0]), .QN(n1393) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3570465), .RN(n1543), .Q(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .QN(n1391) );
DFFRX2TS ITER_CONT_temp_reg_2_ ( .D(ITER_CONT_N4), .CK(ITER_CONT_net3570591),
.RN(n1564), .Q(cont_iter_out[2]), .QN(n1384) );
DFFRX2TS ITER_CONT_temp_reg_3_ ( .D(ITER_CONT_N5), .CK(ITER_CONT_net3570591),
.RN(n1567), .Q(cont_iter_out[3]), .QN(n1385) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n600), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1534),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .QN(n1482) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n858),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n1479) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(
n616), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1530), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .QN(n1416) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(
n608), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1514), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .QN(n1506) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n567), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1518),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .QN(n1462) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n565), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1541),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .QN(n1461) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(
n571), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n854), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .QN(n1458) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(
n577), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1537), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .QN(n1475) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n598), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1530),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .QN(n1483) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n596), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1516),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]), .QN(n1505) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1543),
.QN(n1547) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(
n1578), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(
n1528), .Q(n1468), .QN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(
n1579), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(
n1535), .Q(n1408), .QN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(
n1580), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(
n1538), .Q(n1402), .QN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(
n1581), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(
n1523), .Q(n1407), .QN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(
n1582), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(
n1518), .Q(n1466), .QN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(
n1583), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(
n1534), .Q(n1406), .QN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(
n1584), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(
n1533), .Q(n1459), .QN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(
n1585), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(
n1514), .Q(n1401), .QN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(
n1586), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(
n1541), .Q(n1465), .QN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(
n1587), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(
n1525), .Q(n1452), .QN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(
n1588), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(n854), .Q(n1464), .QN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(
n1589), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(
n1516), .Q(n1463), .QN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(
n1383), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(
n1525), .Q(n1489), .QN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(
n842), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(n1514), .Q(n1399), .QN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(
n840), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(n1514), .Q(n1492), .QN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(
n838), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .SN(n1523), .Q(n1500), .QN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1382),
.CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .SN(n1521),
.Q(n1427), .QN(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1381), .CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .SN(n1532), .Q(
n1478), .QN(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1380), .CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .SN(n1522), .Q(
n1470), .QN(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1379),
.CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .SN(n1528),
.Q(n1388), .QN(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1378),
.CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .SN(n1523),
.Q(n1423), .QN(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1377),
.CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .SN(n1545),
.Q(n1420), .QN(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1376), .CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .SN(n1544), .Q(
n1443), .QN(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1375), .CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .SN(n1533), .Q(
n1398), .QN(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1374), .CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .SN(n1525), .Q(
n1437), .QN(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1373), .CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .SN(n1524), .Q(
n1429), .QN(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1372), .CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .SN(n1540), .Q(
n1433), .QN(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1371), .CK(inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .SN(n1515),
.Q(n1446), .QN(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n696), .CK(inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .SN(n1533), .Q(
n1455), .QN(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1370), .CK(inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .SN(n1531),
.Q(n1439), .QN(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n695),
.CK(inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .SN(
n1517), .Q(n1435), .QN(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n697),
.CK(inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .SN(n1529), .Q(n1477), .QN(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n690),
.CK(inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .SN(n1518), .Q(n1417), .QN(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1369), .CK(inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .SN(n1522),
.Q(n1440), .QN(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1368),
.CK(inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .SN(n1544), .Q(n1474), .QN(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1367), .CK(inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .SN(n1544),
.Q(n1442), .QN(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1366), .CK(inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .SN(n1537),
.Q(n1395), .QN(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]) );
DFFSX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n689),
.CK(inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .SN(
n1540), .Q(n1441), .QN(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1521),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1522),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1523),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1519), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1519),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1514),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1524),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(
n621), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1516), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1526), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n855), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1536), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1524), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1527), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1525), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1535), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1519), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1544), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1531),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ (
.D(n541), .CK(clk), .RN(n1533), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1518), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_shft_value_mux_o_EWR[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1539),
.Q(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS VAR_CONT_temp_reg_1_ ( .D(n539), .CK(clk), .RN(n1565), .Q(
cont_var_out[1]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n892),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1533),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1539),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1540),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1538),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1523),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n854),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(first_mux_X[27]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1571), .Q(d_ff2_X[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(first_mux_Y[27]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1566), .Q(d_ff2_Y[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1523),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1529),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1536),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n892),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n657), .CK(inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1528), .Q(
inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(first_mux_X[29]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1575), .Q(d_ff2_X[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(first_mux_Y[29]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1565), .Q(d_ff2_Y[29]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n1567), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(operation), .CK(reg_Z0_net3570357),
.RN(n853), .Q(d_ff1_operation_out) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3570555), .RN(n1531),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3570555), .RN(n1538),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n1592) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[30]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1532),
.Q(result_add_subt[30]) );
DFFRX4TS ITER_CONT_temp_reg_1_ ( .D(ITER_CONT_N3), .CK(ITER_CONT_net3570591),
.RN(n1575), .Q(cont_iter_out[1]), .QN(n1438) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(first_mux_X[24]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1568), .Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(first_mux_X[26]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1569), .Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(first_mux_X[25]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1564), .Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(first_mux_Y[26]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1566), .Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(first_mux_Y[25]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1567), .Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(first_mux_Y[24]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1572), .Q(d_ff2_Y[24]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(
n592), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3570393), .RN(n1528), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n892),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n855),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n854),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1539),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1525),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1527),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1526),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1517),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]) );
DFFRX4TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_shft_value_mux_o_EWR[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1516),
.Q(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n1449) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_SGF), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3570429), .RN(n1517),
.Q(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n1572), .Q(
inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1542), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .QN(n693) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3570447), .RN(n1542), .Q(
inst_FPU_PIPELINED_FPADDSUB_N59) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ (
.D(n625), .CK(clk), .RN(n1516), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1522),
.Q(result_add_subt[22]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1532),
.Q(result_add_subt[15]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1515),
.Q(result_add_subt[18]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1522),
.Q(result_add_subt[21]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1518),
.Q(result_add_subt[19]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1533),
.Q(result_add_subt[17]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1525),
.Q(result_add_subt[13]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1525),
.Q(result_add_subt[16]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1520),
.Q(result_add_subt[11]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1515),
.Q(result_add_subt[14]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[31]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1527),
.Q(result_add_subt[31]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1529),
.Q(result_add_subt[5]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3570393), .RN(n1519),
.Q(result_add_subt[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1523),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1537),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1525),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1519),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_28_ ( .D(first_mux_Y[28]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n1565), .Q(d_ff2_Y[28]), .QN(
n1510) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(first_mux_X[28]), .CK(
reg_val_muxZ_2stage_net3570357), .RN(n853), .Q(d_ff2_X[28]), .QN(n1509) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[26]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1534), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]), .QN(n1511) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1538), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25]), .QN(n1497) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3570447), .RN(n1516), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]), .QN(n1498) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1538),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .QN(n1480) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1528),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .QN(n1473) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429), .RN(n1520),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .QN(n1414) );
DFFRXLTS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n1564), .Q(
inst_CORDIC_FSM_v3_state_reg[6]), .QN(n1450) );
DFFRX4TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(
n1546), .CK(inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3570429),
.RN(n1523), .Q(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .QN(n629)
);
CMPR32X2TS intadd_403_U4 ( .A(d_ff2_Y[24]), .B(n1438), .C(intadd_403_CI),
.CO(intadd_403_n3), .S(sh_exp_y[1]) );
CMPR32X2TS intadd_402_U4 ( .A(n1438), .B(d_ff2_X[24]), .C(intadd_402_CI),
.CO(intadd_402_n3), .S(sh_exp_x[1]) );
CMPR32X2TS intadd_402_U3 ( .A(d_ff2_X[25]), .B(n1384), .C(intadd_402_n3),
.CO(intadd_402_n2), .S(sh_exp_x[2]) );
CMPR32X2TS intadd_403_U3 ( .A(d_ff2_Y[25]), .B(n1384), .C(intadd_403_n3),
.CO(intadd_403_n2), .S(sh_exp_y[2]) );
CMPR32X2TS intadd_403_U2 ( .A(d_ff2_Y[26]), .B(n1385), .C(intadd_403_n2),
.CO(intadd_403_n1), .S(sh_exp_y[3]) );
CMPR32X2TS intadd_402_U2 ( .A(d_ff2_X[26]), .B(n1385), .C(intadd_402_n2),
.CO(intadd_402_n1), .S(sh_exp_x[3]) );
AOI222X1TS U982 ( .A0(n938), .A1(d_ff2_X[30]), .B0(n1332), .B1(d_ff2_Y[30]),
.C0(n1342), .C1(d_ff2_Z[30]), .Y(n917) );
AOI222X4TS U983 ( .A0(n1052), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]), .B0(n1312), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .C1(n656), .Y(n1096)
);
AOI211X2TS U984 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .A1(
n781), .B0(n832), .C0(n831), .Y(n972) );
AOI211X2TS U985 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .A1(
n781), .B0(n832), .C0(n803), .Y(n884) );
AOI222X4TS U986 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .B1(n757), .C0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .C1(n757), .Y(n1251) );
AOI222X4TS U987 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .B1(n773), .C0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .C1(n773), .Y(n1019) );
NAND2X1TS U988 ( .A(n1122), .B(n726), .Y(n1124) );
NOR2X1TS U989 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .B(
n724), .Y(n726) );
NOR2XLTS U990 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .B(
n1124), .Y(n717) );
NOR2XLTS U991 ( .A(n652), .B(n810), .Y(n811) );
AOI222X2TS U992 ( .A0(n1311), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n657), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n1312), .Y(
n1085) );
AOI31XLTS U993 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .A1(
n735), .A2(n1435), .B0(n1116), .Y(n740) );
AOI222X2TS U994 ( .A0(n1052), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]), .B0(n1546), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .C1(n656), .Y(n1068)
);
OAI21XLTS U995 ( .A0(n1108), .A1(n678), .B0(n1057), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]) );
OAI21XLTS U996 ( .A0(n1103), .A1(n677), .B0(n1072), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]) );
OAI21XLTS U997 ( .A0(n1091), .A1(n655), .B0(n1044), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]) );
OAI211XLTS U998 ( .A0(n1079), .A1(n687), .B0(n1083), .C0(n1033), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]) );
OAI21XLTS U999 ( .A0(n1079), .A1(n677), .B0(n1054), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]) );
XOR2X1TS U1000 ( .A(n1276), .B(n1275), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[24]) );
XOR2X1TS U1001 ( .A(n1270), .B(n1269), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[23]) );
OAI21X1TS U1002 ( .A0(n1097), .A1(n655), .B0(n1051), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]) );
OAI21X1TS U1003 ( .A0(n1114), .A1(n678), .B0(n1113), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]) );
OAI21X1TS U1004 ( .A0(n1097), .A1(n678), .B0(n1078), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]) );
OAI21X1TS U1005 ( .A0(n1085), .A1(n677), .B0(n1074), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]) );
OAI21X1TS U1006 ( .A0(n1096), .A1(n678), .B0(n1059), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]) );
OAI21X1TS U1007 ( .A0(n1085), .A1(n655), .B0(n1047), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]) );
OAI21X1TS U1008 ( .A0(n1038), .A1(n651), .B0(n1037), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]) );
OAI21X1TS U1009 ( .A0(n1101), .A1(n678), .B0(n1100), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]) );
OAI21X1TS U1010 ( .A0(n708), .A1(n706), .B0(n707), .Y(n705) );
OAI21X1TS U1011 ( .A0(n1089), .A1(n677), .B0(n1088), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]) );
OAI21X1TS U1012 ( .A0(n1083), .A1(n678), .B0(n1082), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]) );
OAI21X1TS U1013 ( .A0(n1084), .A1(n677), .B0(n1065), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]) );
AOI222X4TS U1014 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B1(n1273), .C0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .C1(n1273), .Y(
n1137) );
OAI21X1TS U1015 ( .A0(n1090), .A1(n678), .B0(n1061), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]) );
OAI21X1TS U1016 ( .A0(n1095), .A1(n678), .B0(n1094), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]) );
OAI21X1TS U1017 ( .A0(n1091), .A1(n678), .B0(n1070), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]) );
OAI21X1TS U1018 ( .A0(n1102), .A1(n677), .B0(n1063), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]) );
OAI21X1TS U1019 ( .A0(n1103), .A1(n655), .B0(n1041), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]) );
OAI21X1TS U1020 ( .A0(n1107), .A1(n677), .B0(n1106), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]) );
OAI21X1TS U1021 ( .A0(n1068), .A1(n678), .B0(n1067), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]) );
XOR2X1TS U1022 ( .A(n1265), .B(n1264), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[21]) );
AOI222X4TS U1023 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B1(n703), .C0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .C1(n703), .Y(n1266) );
OAI21X1TS U1024 ( .A0(n715), .A1(n713), .B0(n714), .Y(n712) );
XOR2X1TS U1025 ( .A(n1260), .B(n1259), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[19]) );
OAI21X1TS U1026 ( .A0(n750), .A1(n748), .B0(n749), .Y(n747) );
AOI222X4TS U1027 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B1(n710), .C0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .C1(n710), .Y(n1261) );
AND2X2TS U1028 ( .A(n1031), .B(n742), .Y(n743) );
AND2X2TS U1029 ( .A(n1031), .B(n1032), .Y(n741) );
OAI21X1TS U1030 ( .A0(n1030), .A1(n1028), .B0(n1029), .Y(n1027) );
AOI222X4TS U1031 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B1(n745), .C0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .C1(n745), .Y(n1256) );
AOI222X4TS U1032 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B1(n1025), .C0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .C1(n1025), .Y(n752) );
OAI21X1TS U1033 ( .A0(n762), .A1(n760), .B0(n761), .Y(n759) );
NOR2X6TS U1034 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_GTComparator_N0), .Y(
n864) );
AND3X2TS U1035 ( .A(n851), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n850), .Y(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_GTComparator_N0) );
NAND2BX1TS U1036 ( .AN(n772), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n1123) );
AOI31X1TS U1037 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]),
.A1(n734), .A2(n1446), .B0(n733), .Y(n728) );
AOI222X4TS U1038 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B1(n991), .C0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .C1(n991), .Y(n997)
);
BUFX4TS U1039 ( .A(n1309), .Y(n685) );
AOI222X4TS U1040 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .B1(n980), .C0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .C1(n980), .Y(n986)
);
NAND3BX1TS U1041 ( .AN(n1222), .B(n1220), .C(n1219), .Y(n1240) );
NAND2BX1TS U1042 ( .AN(n1124), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n1119) );
AOI31X1TS U1043 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]),
.A1(n735), .A2(n725), .B0(n1116), .Y(n729) );
CLKAND2X2TS U1044 ( .A(n841), .B(n1325), .Y(n842) );
AOI222X4TS U1045 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B1(n952), .C0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .C1(n952), .Y(n965)
);
AOI221X4TS U1046 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]),
.A1(n1546), .B0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]),
.B1(n1035), .C0(n1052), .Y(n1038) );
INVX3TS U1047 ( .A(n1301), .Y(n1300) );
CLKAND2X2TS U1048 ( .A(n839), .B(n1333), .Y(n840) );
CLKAND2X2TS U1049 ( .A(n837), .B(n1333), .Y(n838) );
INVX3TS U1050 ( .A(n1278), .Y(n1308) );
CLKBUFX3TS U1051 ( .A(n780), .Y(n684) );
NOR2X4TS U1052 ( .A(n653), .B(n810), .Y(n801) );
NAND2X4TS U1053 ( .A(n653), .B(n1449), .Y(n807) );
NAND3X1TS U1054 ( .A(n1319), .B(n861), .C(n1481), .Y(n1359) );
NAND3X1TS U1055 ( .A(n1548), .B(n1348), .C(n1322), .Y(n1293) );
OAI211X1TS U1056 ( .A0(n1180), .A1(n1237), .B0(n1179), .C0(n1178), .Y(n1186)
);
OAI211XLTS U1057 ( .A0(n1505), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .B0(n1191), .C0(n1190), .Y(n1194) );
OAI21X1TS U1058 ( .A0(d_ff1_operation_out), .A1(n676), .B0(n1279), .Y(n1277)
);
NAND2X4TS U1059 ( .A(n652), .B(n1449), .Y(n796) );
INVX1TS U1060 ( .A(n727), .Y(n735) );
OAI211XLTS U1061 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .A1(n1499), .B0(n1203), .C0(n1206), .Y(n1217) );
NAND3X1TS U1062 ( .A(n1507), .B(n1177), .C(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .Y(n1179) );
NOR2X1TS U1063 ( .A(n1236), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]),
.Y(n1176) );
INVX3TS U1064 ( .A(n1272), .Y(n1247) );
INVX1TS U1065 ( .A(n764), .Y(n766) );
INVX1TS U1066 ( .A(n1115), .Y(n1117) );
OAI211X2TS U1067 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .A1(
n1496), .B0(n1213), .C0(n1199), .Y(n1215) );
OAI21X1TS U1068 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]),
.A1(n737), .B0(n1441), .Y(n738) );
CLKINVX3TS U1069 ( .A(n797), .Y(n798) );
OAI211X2TS U1070 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .A1(
n1492), .B0(n1233), .C0(n1218), .Y(n1227) );
OR2X4TS U1071 ( .A(cont_iter_out[2]), .B(n1244), .Y(n1301) );
NOR2X4TS U1072 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]),
.B(n829), .Y(n780) );
NAND2BX1TS U1073 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .Y(n1218) );
NAND2BX1TS U1074 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .Y(n1234) );
INVX3TS U1075 ( .A(n1316), .Y(n1339) );
NOR2X6TS U1076 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n781) );
NAND2BX1TS U1077 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .Y(n1177) );
NAND2BX1TS U1078 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .Y(n1178) );
NAND2BX1TS U1079 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .Y(n1224) );
NOR3X1TS U1080 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n1115) );
NOR3X1TS U1081 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n767) );
NOR3X1TS U1082 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n1122) );
INVX3TS U1083 ( .A(n1547), .Y(n686) );
NAND2BXLTS U1084 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .Y(n1190) );
AOI2BB2XLTS U1085 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .B1(
n1505), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .A1N(n1192),
.Y(n1193) );
OAI21XLTS U1086 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .A1(n1505),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .Y(n1192) );
NAND2BXLTS U1087 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .Y(n1205) );
NAND3XLTS U1088 ( .A(n1499), .B(n1203), .C(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .Y(n1204) );
NOR2XLTS U1089 ( .A(n1201), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]),
.Y(n1202) );
OAI21XLTS U1090 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .A1(n1489), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .Y(n1200) );
NAND2BXLTS U1091 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .Y(n1203) );
NAND2BXLTS U1092 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .Y(n1199) );
OAI21XLTS U1093 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .A1(n1416), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .Y(n1229) );
NAND3BXLTS U1094 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(n1444), .C(n1396), .Y(n909) );
NAND2X1TS U1095 ( .A(n767), .B(n764), .Y(n727) );
BUFX4TS U1096 ( .A(n1592), .Y(n1052) );
OAI22X1TS U1097 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]),
.A1(n1436), .B0(n760), .B1(n758), .Y(n1252) );
OAI22X1TS U1098 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(
n1426), .B0(n983), .B1(n981), .Y(n987) );
AOI22X1TS U1099 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .A1(n1420),
.B0(n893), .B1(n894), .Y(n902) );
CLKAND2X2TS U1100 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .B(
n1422), .Y(n904) );
AOI22X1TS U1101 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .A1(n1388),
.B0(n967), .B1(n966), .Y(n981) );
CLKAND2X2TS U1102 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .B(
n1426), .Y(n983) );
OAI22X1TS U1103 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]),
.A1(n1447), .B0(n748), .B1(n746), .Y(n1257) );
AOI22X1TS U1104 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .A1(n1427),
.B0(n988), .B1(n987), .Y(n992) );
CLKAND2X2TS U1105 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]),
.B(n1428), .Y(n994) );
AOI211X1TS U1106 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .A1(
n684), .B0(n792), .C0(n791), .Y(n887) );
OAI21XLTS U1107 ( .A0(n1473), .A1(n797), .B0(n790), .Y(n791) );
AO22XLTS U1108 ( .A0(n682), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .B0(n680), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .Y(n793) );
OAI21XLTS U1109 ( .A0(n797), .A1(n1477), .B0(n785), .Y(n786) );
AOI211X1TS U1110 ( .A0(n684), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .B0(n792), .C0(n789),
.Y(n890) );
OAI21XLTS U1111 ( .A0(n797), .A1(n1474), .B0(n788), .Y(n789) );
AO22XLTS U1112 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .A1(
n682), .B0(n680), .B1(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]),
.Y(n787) );
OAI22X1TS U1113 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]),
.A1(n1454), .B0(n713), .B1(n711), .Y(n1262) );
AOI22X1TS U1114 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .A1(n1437),
.B0(n1253), .B1(n1252), .Y(n1026) );
CLKAND2X2TS U1115 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]),
.B(n1445), .Y(n1028) );
OAI22X1TS U1116 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]),
.A1(n1431), .B0(n776), .B1(n774), .Y(n1020) );
OAI22X1TS U1117 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]),
.A1(n1428), .B0(n994), .B1(n992), .Y(n998) );
AOI22X1TS U1118 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .A1(n1470),
.B0(n1263), .B1(n1262), .Y(n704) );
AOI22X1TS U1119 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .A1(n1398),
.B0(n1258), .B1(n1257), .Y(n711) );
CLKAND2X2TS U1120 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]),
.B(n1454), .Y(n713) );
AOI22X1TS U1121 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .A1(n1443),
.B0(n754), .B1(n753), .Y(n746) );
CLKAND2X2TS U1122 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]),
.B(n1447), .Y(n748) );
AOI22X1TS U1123 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .A1(n1433),
.B0(n1021), .B1(n1020), .Y(n758) );
CLKAND2X2TS U1124 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]),
.B(n1436), .Y(n760) );
AOI22X1TS U1125 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .A1(n1429),
.B0(n999), .B1(n998), .Y(n774) );
CLKAND2X2TS U1126 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]),
.B(n1431), .Y(n776) );
OAI22X1TS U1127 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(
n1422), .B0(n904), .B1(n902), .Y(n911) );
AOI22X1TS U1128 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .A1(n1423),
.B0(n912), .B1(n911), .Y(n953) );
CLKAND2X2TS U1129 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .B(
n1424), .Y(n955) );
NAND2X1TS U1130 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n1246) );
NAND2BXLTS U1131 ( .AN(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]),
.B(n1395), .Y(n721) );
INVX2TS U1132 ( .A(n718), .Y(n719) );
AOI222X4TS U1133 ( .A0(n1052), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]), .B0(n1546), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .C1(n657), .Y(n1079)
);
OR2X1TS U1134 ( .A(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n1134) );
NAND3BXLTS U1135 ( .AN(inst_CORDIC_FSM_v3_state_reg[0]), .B(
inst_CORDIC_FSM_v3_state_reg[3]), .C(n959), .Y(n958) );
OAI211XLTS U1136 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n1476), .B0(n1355), .C0(n1136), .Y(n626) );
CLKAND2X2TS U1137 ( .A(n688), .B(n891), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[7]) );
CLKAND2X2TS U1138 ( .A(n688), .B(n1296), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[5]) );
AOI2BB1XLTS U1139 ( .A0N(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .A1N(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_GTComparator_N0), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[31]) );
CLKAND2X2TS U1140 ( .A(n864), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[16]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[14]) );
CLKAND2X2TS U1141 ( .A(n864), .B(n876), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[11]) );
CLKAND2X2TS U1142 ( .A(n688), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[18]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[16]) );
CLKAND2X2TS U1143 ( .A(n864), .B(n878), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[13]) );
CLKAND2X2TS U1144 ( .A(n688), .B(n1297), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[17]) );
CLKAND2X2TS U1145 ( .A(n688), .B(n1298), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[19]) );
CLKAND2X2TS U1146 ( .A(n864), .B(n865), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[21]) );
CLKAND2X2TS U1147 ( .A(n688), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[20]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[18]) );
CLKAND2X2TS U1148 ( .A(n864), .B(n877), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[15]) );
CLKAND2X2TS U1149 ( .A(n864), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[24]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[22]) );
AO22XLTS U1150 ( .A0(n1312), .A1(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[4]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]), .B1(n1311), .Y(
inst_FPU_PIPELINED_FPADDSUB_shft_value_mux_o_EWR[4]) );
XOR2XLTS U1151 ( .A(n1255), .B(n1254), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[15]) );
OAI21XLTS U1152 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]),
.A1(n1394), .B0(n1253), .Y(n1254) );
XOR2XLTS U1153 ( .A(n990), .B(n989), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[9]) );
OAI21XLTS U1154 ( .A0(n985), .A1(n983), .B0(n984), .Y(n982) );
XOR2XLTS U1155 ( .A(n969), .B(n968), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[7]) );
AO22XLTS U1156 ( .A0(n1546), .A1(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[3]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]), .B1(n1311), .Y(
inst_FPU_PIPELINED_FPADDSUB_shft_value_mux_o_EWR[3]) );
AO22XLTS U1157 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(
n1476), .B1(n1354), .Y(n1356) );
OAI21XLTS U1158 ( .A0(n996), .A1(n994), .B0(n995), .Y(n993) );
OAI21XLTS U1159 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]),
.A1(n1413), .B0(n1263), .Y(n1264) );
OAI21XLTS U1160 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]),
.A1(n1415), .B0(n1268), .Y(n1269) );
XOR2XLTS U1161 ( .A(n1023), .B(n1022), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[13]) );
XOR2XLTS U1162 ( .A(n1001), .B(n1000), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[11]) );
OAI32X1TS U1163 ( .A0(n1272), .A1(n1271), .A2(n701), .B0(n1137), .B1(n1247),
.Y(n702) );
INVX2TS U1164 ( .A(n709), .Y(n1366) );
INVX2TS U1165 ( .A(n716), .Y(n1367) );
INVX2TS U1166 ( .A(n744), .Y(n1368) );
INVX2TS U1167 ( .A(n751), .Y(n1369) );
OAI21XLTS U1168 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]),
.A1(n1397), .B0(n754), .Y(n755) );
INVX2TS U1169 ( .A(n763), .Y(n1370) );
INVX2TS U1170 ( .A(n779), .Y(n1371) );
OAI21XLTS U1171 ( .A0(n778), .A1(n776), .B0(n777), .Y(n775) );
INVX2TS U1172 ( .A(n875), .Y(n1373) );
INVX2TS U1173 ( .A(n878), .Y(n1374) );
INVX2TS U1174 ( .A(n1297), .Y(n1375) );
INVX2TS U1175 ( .A(n877), .Y(n1376) );
INVX2TS U1176 ( .A(n871), .Y(n1377) );
INVX2TS U1177 ( .A(n1295), .Y(n1378) );
INVX2TS U1178 ( .A(n1296), .Y(n1379) );
INVX2TS U1179 ( .A(n1298), .Y(n1380) );
INVX2TS U1180 ( .A(n865), .Y(n1381) );
INVX2TS U1181 ( .A(n891), .Y(n1382) );
AO22XLTS U1182 ( .A0(n1307), .A1(d_ff_Yn[0]), .B0(n1310), .B1(d_ff_Xn[0]),
.Y(mux_sal[0]) );
AO22XLTS U1183 ( .A0(n685), .A1(d_ff_Yn[20]), .B0(n1310), .B1(d_ff_Xn[20]),
.Y(mux_sal[20]) );
AO22XLTS U1184 ( .A0(n685), .A1(d_ff_Yn[19]), .B0(n1310), .B1(d_ff_Xn[19]),
.Y(mux_sal[19]) );
AO22XLTS U1185 ( .A0(n685), .A1(d_ff_Yn[21]), .B0(n1310), .B1(d_ff_Xn[21]),
.Y(mux_sal[21]) );
AO22XLTS U1186 ( .A0(n685), .A1(d_ff_Yn[22]), .B0(n1310), .B1(d_ff_Xn[22]),
.Y(mux_sal[22]) );
AO22XLTS U1187 ( .A0(n1309), .A1(d_ff_Yn[30]), .B0(n1310), .B1(d_ff_Xn[30]),
.Y(mux_sal[30]) );
AO22XLTS U1188 ( .A0(n1309), .A1(d_ff_Yn[29]), .B0(n1310), .B1(d_ff_Xn[29]),
.Y(mux_sal[29]) );
AO22XLTS U1189 ( .A0(n685), .A1(d_ff_Yn[28]), .B0(n1310), .B1(d_ff_Xn[28]),
.Y(mux_sal[28]) );
AO22XLTS U1190 ( .A0(n1307), .A1(d_ff_Yn[27]), .B0(n1310), .B1(d_ff_Xn[27]),
.Y(mux_sal[27]) );
AO22XLTS U1191 ( .A0(n685), .A1(d_ff_Yn[26]), .B0(n1310), .B1(d_ff_Xn[26]),
.Y(mux_sal[26]) );
AO22XLTS U1192 ( .A0(n685), .A1(d_ff_Yn[25]), .B0(n1310), .B1(d_ff_Xn[25]),
.Y(mux_sal[25]) );
AO22XLTS U1193 ( .A0(n685), .A1(d_ff_Yn[24]), .B0(n1310), .B1(d_ff_Xn[24]),
.Y(mux_sal[24]) );
AO22XLTS U1194 ( .A0(n685), .A1(d_ff_Yn[23]), .B0(n1310), .B1(d_ff_Xn[23]),
.Y(mux_sal[23]) );
AOI222X1TS U1195 ( .A0(n938), .A1(d_ff2_X[27]), .B0(n1332), .B1(d_ff2_Y[27]),
.C0(n1342), .C1(d_ff2_Z[27]), .Y(n921) );
AOI222X1TS U1196 ( .A0(n938), .A1(d_ff2_X[24]), .B0(n1332), .B1(d_ff2_Y[24]),
.C0(n1342), .C1(d_ff2_Z[24]), .Y(n919) );
OAI21XLTS U1197 ( .A0(n957), .A1(n955), .B0(n956), .Y(n954) );
AOI222X1TS U1198 ( .A0(n938), .A1(d_ff2_X[25]), .B0(n1332), .B1(d_ff2_Y[25]),
.C0(n1342), .C1(d_ff2_Z[25]), .Y(n926) );
AOI222X1TS U1199 ( .A0(n938), .A1(d_ff2_X[26]), .B0(n1332), .B1(d_ff2_Y[26]),
.C0(n1342), .C1(d_ff2_Z[26]), .Y(n927) );
AOI222X1TS U1200 ( .A0(n938), .A1(d_ff2_X[29]), .B0(n1332), .B1(d_ff2_Y[29]),
.C0(n1342), .C1(d_ff2_Z[29]), .Y(n918) );
AOI222X1TS U1201 ( .A0(n1138), .A1(d_ff3_sh_y_out[25]), .B0(n1337), .B1(
d_ff3_sh_x_out[25]), .C0(n1347), .C1(d_ff3_LUT_out[25]), .Y(n929) );
AOI222X1TS U1202 ( .A0(n1138), .A1(d_ff3_sh_y_out[26]), .B0(n1337), .B1(
d_ff3_sh_x_out[26]), .C0(n950), .C1(d_ff3_LUT_out[26]), .Y(n928) );
OAI21XLTS U1203 ( .A0(n807), .A1(n976), .B0(n975), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[1]) );
AO22XLTS U1204 ( .A0(n1302), .A1(d_ff1_Z[9]), .B0(n1305), .B1(d_ff_Zn[9]),
.Y(first_mux_Z[9]) );
CLKAND2X2TS U1205 ( .A(n864), .B(n875), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[9]) );
AO22XLTS U1206 ( .A0(n1302), .A1(d_ff1_Z[7]), .B0(n1305), .B1(d_ff_Zn[7]),
.Y(first_mux_Z[7]) );
AO22XLTS U1207 ( .A0(n1302), .A1(d_ff1_Z[5]), .B0(n1305), .B1(d_ff_Zn[5]),
.Y(first_mux_Z[5]) );
AO22XLTS U1208 ( .A0(n1302), .A1(d_ff1_Z[3]), .B0(n1301), .B1(d_ff_Zn[3]),
.Y(first_mux_Z[3]) );
CLKAND2X2TS U1209 ( .A(n688), .B(n1295), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[3]) );
AO22XLTS U1210 ( .A0(n1300), .A1(d_ff1_Z[2]), .B0(n1301), .B1(d_ff_Zn[2]),
.Y(first_mux_Z[2]) );
CLKAND2X2TS U1211 ( .A(n688), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[4]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[2]) );
AO22XLTS U1212 ( .A0(n1302), .A1(d_ff1_Z[1]), .B0(n1303), .B1(d_ff_Zn[1]),
.Y(first_mux_Z[1]) );
CLKAND2X2TS U1213 ( .A(n864), .B(n871), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[1]) );
CLKAND2X2TS U1214 ( .A(n864), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[2]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[0]) );
AOI211X1TS U1215 ( .A0(n1118), .A1(n1117), .B0(n1116), .C0(n1127), .Y(n1120)
);
AO22XLTS U1216 ( .A0(n1302), .A1(d_ff1_Z[12]), .B0(n1305), .B1(d_ff_Zn[12]),
.Y(first_mux_Z[12]) );
CLKAND2X2TS U1217 ( .A(n864), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[14]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[12]) );
AO22XLTS U1218 ( .A0(n1302), .A1(d_ff1_Z[10]), .B0(n1305), .B1(d_ff_Zn[10]),
.Y(first_mux_Z[10]) );
CLKAND2X2TS U1219 ( .A(n864), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[12]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[10]) );
AO22XLTS U1220 ( .A0(n1302), .A1(d_ff1_Z[14]), .B0(n1305), .B1(d_ff_Zn[14]),
.Y(first_mux_Z[14]) );
AO22XLTS U1221 ( .A0(n1302), .A1(d_ff1_Z[11]), .B0(n1305), .B1(d_ff_Zn[11]),
.Y(first_mux_Z[11]) );
AO22XLTS U1222 ( .A0(n1302), .A1(d_ff1_Z[8]), .B0(n1305), .B1(d_ff_Zn[8]),
.Y(first_mux_Z[8]) );
CLKAND2X2TS U1223 ( .A(n864), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[10]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[8]) );
AO22XLTS U1224 ( .A0(n1302), .A1(d_ff1_Z[13]), .B0(n1305), .B1(d_ff_Zn[13]),
.Y(first_mux_Z[13]) );
AO22XLTS U1225 ( .A0(n1302), .A1(d_ff1_Z[6]), .B0(n1305), .B1(d_ff_Zn[6]),
.Y(first_mux_Z[6]) );
CLKAND2X2TS U1226 ( .A(n864), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[8]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[6]) );
AO22XLTS U1227 ( .A0(n1302), .A1(d_ff1_Z[4]), .B0(n1305), .B1(d_ff_Zn[4]),
.Y(first_mux_Z[4]) );
CLKAND2X2TS U1228 ( .A(n688), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[6]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[4]) );
CLKAND2X2TS U1229 ( .A(n864), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[22]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[20]) );
OR2X1TS U1230 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[28]) );
OR2X1TS U1231 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[27]) );
OR2X1TS U1232 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[26]) );
OR2X1TS U1233 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[25]) );
OR2X1TS U1234 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[24]) );
OR2X1TS U1235 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[23]) );
XOR2XLTS U1236 ( .A(d_ff2_X[30]), .B(n1363), .Y(sh_exp_x[7]) );
XOR2XLTS U1237 ( .A(d_ff2_Y[30]), .B(n1360), .Y(sh_exp_y[7]) );
INVX2TS U1238 ( .A(n653), .Y(n1014) );
OR2X1TS U1239 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .B(
n830), .Y(n630) );
BUFX3TS U1240 ( .A(n892), .Y(n1527) );
BUFX4TS U1241 ( .A(n892), .Y(n855) );
NOR2X6TS U1242 ( .A(rst), .B(n1548), .Y(n892) );
BUFX3TS U1243 ( .A(n529), .Y(n856) );
INVX2TS U1244 ( .A(n1077), .Y(n650) );
INVX2TS U1245 ( .A(n1077), .Y(n651) );
INVX2TS U1246 ( .A(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .Y(n652) );
INVX2TS U1247 ( .A(n652), .Y(n653) );
INVX2TS U1248 ( .A(n743), .Y(n654) );
INVX4TS U1249 ( .A(n743), .Y(n655) );
INVX4TS U1250 ( .A(n1288), .Y(n1291) );
INVX4TS U1251 ( .A(n1285), .Y(n1287) );
INVX4TS U1252 ( .A(n1283), .Y(n1292) );
CLKINVX3TS U1253 ( .A(n1049), .Y(n656) );
INVX3TS U1254 ( .A(n1049), .Y(n657) );
OAI221X1TS U1255 ( .A0(n1400), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]), .B0(n1467), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .C0(n1150), .Y(
n1153) );
OAI221X1TS U1256 ( .A0(n1407), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B0(n1472), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .C0(n1164), .Y(n1171) );
OAI21X1TS U1257 ( .A0(n830), .A1(n1473), .B0(n818), .Y(n819) );
AOI221X1TS U1258 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .A1(
n1451), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .B1(n1399),
.C0(n1183), .Y(n1185) );
INVX1TS U1259 ( .A(n1317), .Y(n1320) );
NAND3X2TS U1260 ( .A(n1385), .B(n1393), .C(n1438), .Y(n1244) );
NOR2X2TS U1261 ( .A(n1481), .B(n1316), .Y(enab_d_ff4_Zn) );
OR2X1TS U1262 ( .A(n832), .B(n792), .Y(n794) );
NOR2X2TS U1263 ( .A(n818), .B(n1455), .Y(n832) );
BUFX3TS U1264 ( .A(n529), .Y(n857) );
BUFX4TS U1265 ( .A(n857), .Y(n1554) );
BUFX4TS U1266 ( .A(n857), .Y(n1557) );
BUFX4TS U1267 ( .A(n857), .Y(n1558) );
BUFX4TS U1268 ( .A(n1553), .Y(n1559) );
BUFX4TS U1269 ( .A(n854), .Y(n1544) );
BUFX3TS U1270 ( .A(n856), .Y(n853) );
BUFX4TS U1271 ( .A(n855), .Y(n1541) );
BUFX4TS U1272 ( .A(n1565), .Y(n1570) );
BUFX4TS U1273 ( .A(n1575), .Y(n1571) );
BUFX4TS U1274 ( .A(n1565), .Y(n1566) );
BUFX4TS U1275 ( .A(n1564), .Y(n1569) );
OAI21XLTS U1276 ( .A0(n979), .A1(n796), .B0(n973), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[25]) );
OAI211X1TS U1277 ( .A0(n1449), .A1(n979), .B0(n835), .C0(n834), .Y(n885) );
AOI21X2TS U1278 ( .A0(n781), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]), .B0(n833), .Y(n979)
);
BUFX4TS U1279 ( .A(n856), .Y(n1565) );
BUFX4TS U1280 ( .A(n855), .Y(n1514) );
BUFX4TS U1281 ( .A(n1519), .Y(n1516) );
BUFX4TS U1282 ( .A(n1530), .Y(n1519) );
BUFX4TS U1283 ( .A(n1527), .Y(n1518) );
OAI211X1TS U1284 ( .A0(n1449), .A1(n874), .B0(n800), .C0(n799), .Y(n1009) );
AOI21X2TS U1285 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .A1(
n781), .B0(n833), .Y(n874) );
OAI211X1TS U1286 ( .A0(n1449), .A1(n881), .B0(n821), .C0(n820), .Y(n1005) );
AOI21X2TS U1287 ( .A0(n781), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .B0(n833), .Y(n881)
);
BUFX4TS U1288 ( .A(n855), .Y(n1524) );
BUFX4TS U1289 ( .A(n1527), .Y(n1538) );
BUFX4TS U1290 ( .A(n855), .Y(n1534) );
BUFX4TS U1291 ( .A(n892), .Y(n1536) );
AOI21X2TS U1292 ( .A0(n781), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .B0(n833), .Y(n976)
);
AOI21X2TS U1293 ( .A0(n781), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .B0(n814), .Y(n1016)
);
AOI21X2TS U1294 ( .A0(n781), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .B0(n813), .Y(n1004)
);
NOR2X4TS U1295 ( .A(n1384), .B(n1385), .Y(n1348) );
AOI222X2TS U1296 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]),
.A1(n1421), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .B1(
n1248), .C0(n1421), .C1(n1248), .Y(n893) );
OR2X1TS U1297 ( .A(inst_FPU_PIPELINED_FPADDSUB_N60), .B(
inst_FPU_PIPELINED_FPADDSUB_N59), .Y(n1248) );
NOR2BX2TS U1298 ( .AN(n1319), .B(n1317), .Y(n1354) );
NAND4X2TS U1299 ( .A(n859), .B(n1396), .C(n1444), .D(
inst_CORDIC_FSM_v3_state_reg[4]), .Y(n1319) );
INVX2TS U1300 ( .A(n632), .Y(n658) );
INVX2TS U1301 ( .A(n633), .Y(n659) );
INVX2TS U1302 ( .A(n634), .Y(n660) );
INVX2TS U1303 ( .A(n635), .Y(n661) );
INVX2TS U1304 ( .A(n636), .Y(n662) );
INVX2TS U1305 ( .A(n637), .Y(n663) );
INVX2TS U1306 ( .A(n638), .Y(n664) );
INVX2TS U1307 ( .A(n639), .Y(n665) );
INVX2TS U1308 ( .A(n640), .Y(n666) );
INVX2TS U1309 ( .A(n641), .Y(n667) );
INVX2TS U1310 ( .A(n642), .Y(n668) );
INVX2TS U1311 ( .A(n643), .Y(n669) );
INVX2TS U1312 ( .A(n644), .Y(n670) );
INVX2TS U1313 ( .A(n645), .Y(n671) );
INVX2TS U1314 ( .A(n646), .Y(n672) );
INVX2TS U1315 ( .A(n647), .Y(n673) );
INVX2TS U1316 ( .A(n648), .Y(n674) );
INVX2TS U1317 ( .A(n649), .Y(n675) );
NAND2BX1TS U1318 ( .AN(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(
n1136) );
NAND2X1TS U1319 ( .A(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
n1476), .Y(n1355) );
AOI222X1TS U1320 ( .A0(n938), .A1(d_ff3_sh_y_out[0]), .B0(n1332), .B1(
d_ff3_sh_x_out[0]), .C0(n1342), .C1(d_ff3_LUT_out[0]), .Y(n922) );
AOI222X1TS U1321 ( .A0(n938), .A1(d_ff3_sh_y_out[1]), .B0(n1332), .B1(
d_ff3_sh_x_out[1]), .C0(n1342), .C1(d_ff3_LUT_out[1]), .Y(n920) );
BUFX4TS U1322 ( .A(n1336), .Y(n1342) );
OAI21XLTS U1323 ( .A0(n807), .A1(n979), .B0(n978), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[0]) );
BUFX4TS U1324 ( .A(n1052), .Y(n1311) );
INVX2TS U1325 ( .A(n631), .Y(n676) );
OAI21XLTS U1326 ( .A0(ack_cordic), .A1(n1294), .B0(n1293), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
INVX2TS U1327 ( .A(n741), .Y(n677) );
INVX4TS U1328 ( .A(n741), .Y(n678) );
AOI222X1TS U1329 ( .A0(n938), .A1(d_ff2_X[28]), .B0(n1332), .B1(d_ff2_Y[28]),
.C0(n1342), .C1(d_ff2_Z[28]), .Y(n937) );
BUFX4TS U1330 ( .A(n1339), .Y(n1332) );
BUFX4TS U1331 ( .A(n1336), .Y(n950) );
BUFX4TS U1332 ( .A(n1336), .Y(n1347) );
OAI21X2TS U1333 ( .A0(n1035), .A1(n1432), .B0(n1034), .Y(n1111) );
BUFX4TS U1334 ( .A(n1282), .Y(n1290) );
BUFX4TS U1335 ( .A(n1339), .Y(n1323) );
BUFX4TS U1336 ( .A(n1339), .Y(n1344) );
INVX2TS U1337 ( .A(n782), .Y(n679) );
INVX2TS U1338 ( .A(n679), .Y(n680) );
INVX2TS U1339 ( .A(n679), .Y(n681) );
INVX2TS U1340 ( .A(n630), .Y(n682) );
INVX2TS U1341 ( .A(n630), .Y(n683) );
AOI222X1TS U1342 ( .A0(n1138), .A1(d_ff3_sh_y_out[23]), .B0(n1337), .B1(
d_ff3_sh_x_out[23]), .C0(n950), .C1(d_ff3_LUT_out[23]), .Y(n940) );
AOI222X1TS U1343 ( .A0(n1138), .A1(d_ff3_sh_y_out[12]), .B0(n1337), .B1(
d_ff3_sh_x_out[12]), .C0(n950), .C1(d_ff3_LUT_out[12]), .Y(n930) );
AOI222X1TS U1344 ( .A0(n1138), .A1(d_ff3_sh_y_out[21]), .B0(n1337), .B1(
d_ff3_sh_x_out[21]), .C0(n1347), .C1(d_ff3_LUT_out[21]), .Y(n931) );
INVX3TS U1345 ( .A(n852), .Y(n1138) );
INVX3TS U1346 ( .A(n852), .Y(n1340) );
OR2X2TS U1347 ( .A(n1448), .B(cont_var_out[1]), .Y(n852) );
OAI2BB1X1TS U1348 ( .A0N(n1312), .A1N(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(n1045), .Y(
n1087) );
NOR2X1TS U1349 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n1125) );
NOR4X1TS U1350 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .D(n1121), .Y(n736)
);
INVX2TS U1351 ( .A(n1112), .Y(n687) );
NOR2X4TS U1352 ( .A(n1031), .B(n742), .Y(n1112) );
BUFX3TS U1353 ( .A(n687), .Y(n1075) );
OAI221X1TS U1354 ( .A0(n1409), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B0(n1466), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .C0(n1158), .Y(n1161) );
OAI221X1TS U1355 ( .A0(n1458), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .B0(n1411), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .C0(n1142), .Y(n1145) );
OAI221X1TS U1356 ( .A0(n1459), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .B0(n1475), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .C0(n1166), .Y(n1169) );
OAI221X1TS U1357 ( .A0(n1404), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .B0(n1465), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .C0(n1148), .Y(
n1155) );
NOR2X4TS U1358 ( .A(n1393), .B(n1438), .Y(n1322) );
NOR2X2TS U1359 ( .A(n1439), .B(n724), .Y(n1116) );
BUFX4TS U1360 ( .A(n1551), .Y(n1550) );
BUFX3TS U1361 ( .A(n853), .Y(n1576) );
NOR3X2TS U1362 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(n1444), .C(n960),
.Y(inst_CORDIC_FSM_v3_state_next[3]) );
NOR3X6TS U1363 ( .A(n851), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n846), .Y(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0) );
XNOR2X2TS U1364 ( .A(DP_OP_33J164_122_2179_n1), .B(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n851) );
OAI21X2TS U1365 ( .A0(n1430), .A1(n1049), .B0(n1048), .Y(n1099) );
OAI21X2TS U1366 ( .A0(n1440), .A1(n1049), .B0(n1042), .Y(n1093) );
OAI21X2TS U1367 ( .A0(n1439), .A1(n1049), .B0(n1039), .Y(n1105) );
NAND2X2TS U1368 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM), .Y(n1049) );
OAI32X4TS U1369 ( .A0(n699), .A1(d_ff1_operation_out), .A2(n676), .B0(
d_ff1_shift_region_flag_out_0_), .B1(n1279), .Y(n1280) );
NOR3BX2TS U1370 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(n915), .Y(ready_cordic) );
AOI21X2TS U1371 ( .A0(cont_iter_out[2]), .A1(n1385), .B0(n862), .Y(n964) );
NOR2X4TS U1372 ( .A(n1032), .B(n1031), .Y(n1077) );
INVX4TS U1373 ( .A(n1288), .Y(n1286) );
BUFX4TS U1374 ( .A(n1282), .Y(n1288) );
BUFX3TS U1375 ( .A(n892), .Y(n854) );
BUFX3TS U1376 ( .A(n864), .Y(n688) );
AOI21X2TS U1377 ( .A0(n781), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .B0(n795), .Y(n1011)
);
AOI21X2TS U1378 ( .A0(n781), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .B0(n819), .Y(n1008)
);
INVX4TS U1379 ( .A(n1308), .Y(n1307) );
OAI211XLTS U1380 ( .A0(n1358), .A1(n852), .B0(n1316), .C0(n848), .Y(n539) );
NAND3X2TS U1381 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .C(n1449),
.Y(n797) );
NAND2X2TS U1382 ( .A(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n818) );
OAI22X2TS U1383 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(
n1424), .B0(n955), .B1(n953), .Y(n966) );
OAI22X2TS U1384 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]),
.A1(n1445), .B0(n1028), .B1(n1026), .Y(n753) );
AOI222X4TS U1385 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .B1(n901), .C0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .C1(n901), .Y(n910)
);
OAI221X4TS U1386 ( .A0(n691), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .B0(n1462), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .C0(n1156), .Y(
n1163) );
OAI32X1TS U1387 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]),
.A1(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(n1442),
.B0(n1395), .B1(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(
n737) );
NOR2XLTS U1388 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n723) );
NOR2XLTS U1389 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n725) );
NOR4X2TS U1390 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n764) );
NOR2XLTS U1391 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n765) );
XNOR2X1TS U1392 ( .A(n694), .B(n702), .Y(n689) );
OA22X1TS U1393 ( .A0(n1055), .A1(n678), .B0(n1038), .B1(n655), .Y(n690) );
INVX2TS U1394 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .Y(n1182) );
XNOR2X1TS U1395 ( .A(n756), .B(n755), .Y(n695) );
AOI22X1TS U1396 ( .A0(n1312), .A1(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[2]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]), .B1(n1592), .Y(
n696) );
OA21XLTS U1397 ( .A0(n1038), .A1(n678), .B0(n1049), .Y(n697) );
OAI21XLTS U1398 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1(n1504),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .Y(n1189) );
OAI21XLTS U1399 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .A1(n1506), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .Y(n1209) );
NOR2XLTS U1400 ( .A(n1222), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]),
.Y(n1223) );
OAI21XLTS U1401 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .A1(n1490), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .Y(n1221) );
OAI21XLTS U1402 ( .A0(n797), .A1(n1417), .B0(n783), .Y(n784) );
NAND2X1TS U1403 ( .A(n1128), .B(n1430), .Y(n772) );
OAI21XLTS U1404 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]),
.A1(n1453), .B0(n1258), .Y(n1259) );
NOR2XLTS U1405 ( .A(n852), .B(n1481), .Y(enab_d_ff4_Yn) );
INVX2TS U1406 ( .A(n876), .Y(n1372) );
OR2X1TS U1407 ( .A(d_ff_Xn[28]), .B(n963), .Y(first_mux_X[28]) );
NOR2XLTS U1408 ( .A(n907), .B(n551), .Y(ITER_CONT_N5) );
OAI21XLTS U1409 ( .A0(beg_fsm_cordic), .A1(n1315), .B0(n962), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
OR2X1TS U1410 ( .A(d_ff_Xn[5]), .B(n1300), .Y(first_mux_X[5]) );
OR2X1TS U1411 ( .A(d_ff_Xn[14]), .B(n1300), .Y(first_mux_X[14]) );
OR2X1TS U1412 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[29]) );
OR2X1TS U1413 ( .A(d_ff_Xn[25]), .B(n963), .Y(first_mux_X[25]) );
CLKBUFX2TS U1414 ( .A(n1547), .Y(n1272) );
NOR2X1TS U1415 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .B(
n693), .Y(n1271) );
NAND2X1TS U1416 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]), .B(
n1415), .Y(n1268) );
CLKAND2X2TS U1417 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]),
.B(n1469), .Y(n706) );
NAND2X1TS U1418 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]), .B(
n1413), .Y(n1263) );
NAND2X1TS U1419 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]), .B(
n1453), .Y(n1258) );
NAND2X1TS U1420 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]), .B(
n1397), .Y(n754) );
NAND2X1TS U1421 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]), .B(
n1394), .Y(n1253) );
NAND2X1TS U1422 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]), .B(
n1392), .Y(n1021) );
NAND2X1TS U1423 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]), .B(
n1390), .Y(n999) );
NAND2X1TS U1424 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .B(
n1389), .Y(n988) );
NAND2X1TS U1425 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .B(
n1425), .Y(n967) );
NAND2X1TS U1426 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .B(
n1387), .Y(n912) );
NAND2X1TS U1427 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .B(
n1386), .Y(n894) );
OAI22X1TS U1428 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]),
.A1(n1469), .B0(n706), .B1(n704), .Y(n1267) );
AOI22X1TS U1429 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .A1(n1478),
.B0(n1268), .B1(n1267), .Y(n1274) );
AOI21X1TS U1430 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]),
.A1(n693), .B0(n1274), .Y(n701) );
AOI222X4TS U1431 ( .A0(n1386), .A1(n1246), .B0(n1386), .B1(n1420), .C0(n1246), .C1(n1420), .Y(n901) );
AOI222X4TS U1432 ( .A0(n910), .A1(n1387), .B0(n910), .B1(n1423), .C0(n1387),
.C1(n1423), .Y(n952) );
AOI222X4TS U1433 ( .A0(n965), .A1(n1425), .B0(n965), .B1(n1388), .C0(n1425),
.C1(n1388), .Y(n980) );
AOI222X4TS U1434 ( .A0(n986), .A1(n1389), .B0(n986), .B1(n1427), .C0(n1389),
.C1(n1427), .Y(n991) );
AOI222X4TS U1435 ( .A0(n997), .A1(n1390), .B0(n997), .B1(n1429), .C0(n1390),
.C1(n1429), .Y(n773) );
AOI222X4TS U1436 ( .A0(n1019), .A1(n1392), .B0(n1019), .B1(n1433), .C0(n1392), .C1(n1433), .Y(n757) );
AOI222X4TS U1437 ( .A0(n1251), .A1(n1394), .B0(n1251), .B1(n1437), .C0(n1394), .C1(n1437), .Y(n1025) );
AOI222X4TS U1438 ( .A0(n752), .A1(n1397), .B0(n752), .B1(n1443), .C0(n1397),
.C1(n1443), .Y(n745) );
AOI222X4TS U1439 ( .A0(n1256), .A1(n1453), .B0(n1256), .B1(n1398), .C0(n1453), .C1(n1398), .Y(n710) );
AOI222X4TS U1440 ( .A0(n1261), .A1(n1413), .B0(n1261), .B1(n1470), .C0(n1413), .C1(n1470), .Y(n703) );
AOI222X4TS U1441 ( .A0(n1266), .A1(n1415), .B0(n1266), .B1(n1478), .C0(n1415), .C1(n1478), .Y(n1273) );
NOR2X1TS U1442 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .B(
n1469), .Y(n708) );
AOI22X1TS U1443 ( .A0(n686), .A1(n704), .B0(n703), .B1(n1272), .Y(n707) );
OAI31X1TS U1444 ( .A0(n708), .A1(n707), .A2(n706), .B0(n705), .Y(n709) );
NOR2X1TS U1445 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .B(
n1454), .Y(n715) );
BUFX3TS U1446 ( .A(n1547), .Y(n1024) );
AOI22X1TS U1447 ( .A0(n686), .A1(n711), .B0(n710), .B1(n1024), .Y(n714) );
OAI31X1TS U1448 ( .A0(n715), .A1(n714), .A2(n713), .B0(n712), .Y(n716) );
OR2X2TS U1449 ( .A(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM), .B(n1311),
.Y(n1035) );
INVX4TS U1450 ( .A(n1035), .Y(n1546) );
NOR2X1TS U1451 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .B(
n727), .Y(n1118) );
NAND2X1TS U1452 ( .A(n1118), .B(n1115), .Y(n724) );
NAND2X1TS U1453 ( .A(n1125), .B(n717), .Y(n718) );
NOR2X2TS U1454 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .B(
n718), .Y(n1128) );
NOR3X2TS U1455 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .C(n772), .Y(n769)
);
OA21XLTS U1456 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .B0(n769), .Y(n720)
);
OAI31X1TS U1457 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(
n720), .A2(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n719),
.Y(n1130) );
NOR2X1TS U1458 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n722) );
AOI32X1TS U1459 ( .A0(n723), .A1(n722), .A2(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(n721), .B1(n722), .Y(n730) );
INVX2TS U1460 ( .A(n726), .Y(n1121) );
NOR2X1TS U1461 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
n1121), .Y(n734) );
OAI21X1TS U1462 ( .A0(n727), .A1(n1440), .B0(n1119), .Y(n733) );
NAND4X1TS U1463 ( .A(n1130), .B(n730), .C(n729), .D(n728), .Y(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[1]) );
AOI21X1TS U1464 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(
n1434), .B0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n731)
);
NAND2X1TS U1465 ( .A(n769), .B(n1432), .Y(n1131) );
OAI22X1TS U1466 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(
n1123), .B0(n731), .B1(n1131), .Y(n732) );
AOI211X1TS U1467 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]),
.A1(n734), .B0(n733), .C0(n732), .Y(n771) );
AOI22X1TS U1468 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .A1(
n736), .B0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n1128), .Y(n739) );
NAND4X1TS U1469 ( .A(n771), .B(n740), .C(n739), .D(n738), .Y(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[0]) );
AOI22X2TS U1470 ( .A0(n1546), .A1(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[1]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]), .B1(n1052), .Y(
n1031) );
OAI22X2TS U1471 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]),
.A1(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[0]), .B0(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[0]), .B1(n1035), .Y(n1032)
);
INVX2TS U1472 ( .A(n1032), .Y(n742) );
INVX4TS U1473 ( .A(n1035), .Y(n1312) );
AOI222X4TS U1474 ( .A0(n1311), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .B1(n657), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .C1(n1312), .Y(n1109) );
AOI222X4TS U1475 ( .A0(n1311), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .B1(n657), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .C1(n1312), .Y(n1055) );
OAI222X1TS U1476 ( .A0(n687), .A1(n1038), .B0(n678), .B1(n1109), .C0(n655),
.C1(n1055), .Y(n744) );
NOR2X1TS U1477 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .B(
n1447), .Y(n750) );
AOI22X1TS U1478 ( .A0(n686), .A1(n746), .B0(n745), .B1(n1547), .Y(n749) );
OAI31X1TS U1479 ( .A0(n750), .A1(n749), .A2(n748), .B0(n747), .Y(n751) );
AOI22X1TS U1480 ( .A0(n686), .A1(n753), .B0(n752), .B1(n1547), .Y(n756) );
NOR2X1TS U1481 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .B(
n1436), .Y(n762) );
AOI22X1TS U1482 ( .A0(n686), .A1(n758), .B0(n757), .B1(n1024), .Y(n761) );
OAI31X1TS U1483 ( .A0(n762), .A1(n761), .A2(n760), .B0(n759), .Y(n763) );
OAI22X1TS U1484 ( .A0(n767), .A1(n766), .B0(n765), .B1(n1121), .Y(n768) );
AOI21X1TS U1485 ( .A0(n769), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n768), .Y(n770)
);
OAI211X1TS U1486 ( .A0(n772), .A1(n1479), .B0(n771), .C0(n770), .Y(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[2]) );
NOR2X1TS U1487 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .B(
n1431), .Y(n778) );
AOI22X1TS U1488 ( .A0(n686), .A1(n774), .B0(n773), .B1(n1024), .Y(n777) );
OAI31X1TS U1489 ( .A0(n778), .A1(n777), .A2(n776), .B0(n775), .Y(n779) );
NAND2X1TS U1490 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.B(n1455), .Y(n829) );
NAND2X1TS U1491 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]),
.B(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .Y(n810) );
INVX2TS U1492 ( .A(n810), .Y(n792) );
NAND2BX2TS U1493 ( .AN(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n830) );
NOR2BX1TS U1494 ( .AN(n781), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n782) );
AOI22X1TS U1495 ( .A0(n682), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .B0(n680), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .Y(n783) );
AOI211X1TS U1496 ( .A0(n684), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .B0(n792), .C0(n784),
.Y(n866) );
AOI22X1TS U1497 ( .A0(n682), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .B0(n680), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .Y(n785) );
AOI211X1TS U1498 ( .A0(n684), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .B0(n792), .C0(n786),
.Y(n867) );
AOI22X1TS U1499 ( .A0(n653), .A1(n866), .B0(n867), .B1(n1014), .Y(n876) );
AOI211X1TS U1500 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .A1(
n684), .B0(n794), .C0(n787), .Y(n889) );
AOI22X1TS U1501 ( .A0(n683), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .B0(n681), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .Y(n788) );
AOI22X1TS U1502 ( .A0(n653), .A1(n889), .B0(n890), .B1(n652), .Y(n875) );
AOI22X1TS U1503 ( .A0(n683), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .B0(n681), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .Y(n790) );
AOI211X1TS U1504 ( .A0(n684), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .B0(n794), .C0(n793),
.Y(n888) );
AOI22X1TS U1505 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(n887), .B0(n888), .B1(n1014), .Y(n878) );
OAI21X1TS U1506 ( .A0(n830), .A1(n1474), .B0(n818), .Y(n795) );
NOR2BX2TS U1507 ( .AN(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .B(n781),
.Y(n833) );
AOI22X1TS U1508 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .A1(
n798), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .B1(n684),
.Y(n800) );
AOI22X1TS U1509 ( .A0(n683), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]), .B1(n681), .Y(n799)
);
AOI21X1TS U1510 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n1009), .B0(n801), .Y(n802) );
OAI21X1TS U1511 ( .A0(n1011), .A1(n796), .B0(n802), .Y(n1297) );
OAI22X1TS U1512 ( .A0(n830), .A1(n1414), .B0(n829), .B1(n1477), .Y(n803) );
AOI22X1TS U1513 ( .A0(n798), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .B0(n780), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .Y(n805) );
AOI22X1TS U1514 ( .A0(n682), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .B0(n681), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .Y(n804) );
OAI211X1TS U1515 ( .A0(n1449), .A1(n976), .B0(n805), .C0(n804), .Y(n882) );
AOI21X1TS U1516 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(n882), .B0(n801), .Y(n806) );
OAI21X1TS U1517 ( .A0(n884), .A1(n796), .B0(n806), .Y(n877) );
AOI22X1TS U1518 ( .A0(n798), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .B0(n780), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .Y(n809) );
AOI22X1TS U1519 ( .A0(n682), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]), .B0(n680), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]), .Y(n808) );
OAI211X1TS U1520 ( .A0(n1011), .A1(n1449), .B0(n809), .C0(n808), .Y(n872) );
BUFX3TS U1521 ( .A(n811), .Y(n1012) );
AOI21X1TS U1522 ( .A0(n1014), .A1(n872), .B0(n1012), .Y(n812) );
OAI21X1TS U1523 ( .A0(n807), .A1(n874), .B0(n812), .Y(n871) );
OAI21X1TS U1524 ( .A0(n830), .A1(n1417), .B0(n818), .Y(n813) );
OAI21X1TS U1525 ( .A0(n830), .A1(n1477), .B0(n818), .Y(n814) );
AOI22X1TS U1526 ( .A0(n798), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .B0(n780), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .Y(n816) );
AOI22X1TS U1527 ( .A0(n682), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .B0(n681), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]), .Y(n815) );
OAI211X1TS U1528 ( .A0(n1016), .A1(n1449), .B0(n816), .C0(n815), .Y(n1002)
);
AOI21X1TS U1529 ( .A0(n1014), .A1(n1002), .B0(n1012), .Y(n817) );
OAI21X1TS U1530 ( .A0(n1004), .A1(n807), .B0(n817), .Y(n1295) );
AOI22X1TS U1531 ( .A0(n798), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .B0(n684), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .Y(n821) );
AOI22X1TS U1532 ( .A0(n683), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .B0(n681), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]), .Y(n820) );
AOI21X1TS U1533 ( .A0(n629), .A1(n1005), .B0(n1012), .Y(n822) );
OAI21X1TS U1534 ( .A0(n1008), .A1(n807), .B0(n822), .Y(n1296) );
AOI22X1TS U1535 ( .A0(n798), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .B0(n780), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .Y(n824) );
AOI22X1TS U1536 ( .A0(n683), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .B0(n680), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]), .Y(n823) );
OAI211X1TS U1537 ( .A0(n1004), .A1(n1449), .B0(n824), .C0(n823), .Y(n1013)
);
AOI21X1TS U1538 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n1013), .B0(n801), .Y(n825) );
OAI21X1TS U1539 ( .A0(n1016), .A1(n796), .B0(n825), .Y(n1298) );
AOI22X1TS U1540 ( .A0(n798), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .B0(n780), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .Y(n827) );
AOI22X1TS U1541 ( .A0(n683), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]), .B0(n680), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .Y(n826) );
OAI211X1TS U1542 ( .A0(n1008), .A1(n1449), .B0(n827), .C0(n826), .Y(n879) );
AOI21X1TS U1543 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(n879), .B0(n801), .Y(n828) );
OAI21X1TS U1544 ( .A0(n881), .A1(n796), .B0(n828), .Y(n865) );
OAI22X1TS U1545 ( .A0(n830), .A1(n1480), .B0(n829), .B1(n1417), .Y(n831) );
AOI22X1TS U1546 ( .A0(n683), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .B0(n780), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .Y(n835) );
AOI22X1TS U1547 ( .A0(n681), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .B0(n798), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .Y(n834) );
AOI21X1TS U1548 ( .A0(n629), .A1(n885), .B0(n1012), .Y(n836) );
OAI21X1TS U1549 ( .A0(n972), .A1(n807), .B0(n836), .Y(n891) );
NAND2X1TS U1550 ( .A(cont_var_out[1]), .B(n1448), .Y(n1316) );
AOI22X1TS U1551 ( .A0(n1340), .A1(d_ff3_sh_y_out[17]), .B0(n1344), .B1(
d_ff3_sh_x_out[17]), .Y(n837) );
NAND2X1TS U1552 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .Y(n1318) );
INVX2TS U1553 ( .A(n1318), .Y(n1336) );
NAND2X1TS U1554 ( .A(n1331), .B(d_ff3_LUT_out[15]), .Y(n1333) );
AOI22X1TS U1555 ( .A0(n1340), .A1(d_ff3_sh_y_out[20]), .B0(n1323), .B1(
d_ff3_sh_x_out[20]), .Y(n839) );
AOI22X1TS U1556 ( .A0(n1340), .A1(d_ff3_sh_y_out[29]), .B0(n1344), .B1(
d_ff3_sh_x_out[29]), .Y(n841) );
NAND2X1TS U1557 ( .A(n1331), .B(d_ff3_LUT_out[27]), .Y(n1325) );
INVX4TS U1558 ( .A(n852), .Y(n1345) );
AOI22X1TS U1559 ( .A0(n1345), .A1(d_ff3_sh_y_out[13]), .B0(n1344), .B1(
d_ff3_sh_x_out[13]), .Y(n843) );
OAI2BB1X1TS U1560 ( .A0N(n1347), .A1N(d_ff3_LUT_out[13]), .B0(n843), .Y(n844) );
INVX2TS U1561 ( .A(n844), .Y(n1383) );
OR4X2TS U1562 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]), .D(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n845) );
OR4X2TS U1563 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(n845), .Y(n846)
);
NOR2X1TS U1564 ( .A(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[7]), .Y(n847) );
NAND2X1TS U1565 ( .A(n847), .B(n1450), .Y(n908) );
NOR3X1TS U1566 ( .A(inst_CORDIC_FSM_v3_state_reg[3]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(n908), .Y(n859) );
NOR3X1TS U1567 ( .A(inst_CORDIC_FSM_v3_state_reg[3]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(n909), .Y(n863) );
NAND3X1TS U1568 ( .A(n863), .B(inst_CORDIC_FSM_v3_state_reg[6]), .C(n847),
.Y(n861) );
INVX2TS U1569 ( .A(n1359), .Y(n1358) );
NAND2X1TS U1570 ( .A(n1358), .B(cont_var_out[1]), .Y(n848) );
AND4X1TS U1571 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]), .D(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n849) );
AND4X1TS U1572 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(n849), .Y(n850)
);
INVX2TS U1573 ( .A(n1348), .Y(n559) );
NAND2X1TS U1574 ( .A(n1384), .B(cont_iter_out[3]), .Y(n898) );
INVX2TS U1575 ( .A(n898), .Y(n862) );
NAND2X1TS U1576 ( .A(n559), .B(cont_iter_out[0]), .Y(n1353) );
INVX2TS U1577 ( .A(n1353), .Y(n1352) );
NOR2X1TS U1578 ( .A(n862), .B(n1352), .Y(n1349) );
OAI211X1TS U1579 ( .A0(cont_iter_out[3]), .A1(n1393), .B0(n1384), .C0(n1438),
.Y(n1351) );
OAI21XLTS U1580 ( .A0(n1349), .A1(n1438), .B0(n1351), .Y(n548) );
NAND2X1TS U1581 ( .A(n1322), .B(n1384), .Y(n897) );
OAI31X1TS U1582 ( .A0(cont_iter_out[3]), .A1(cont_iter_out[1]), .A2(n1384),
.B0(n897), .Y(n550) );
OAI31X4TS U1583 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[3]), .A2(n1393),
.B0(n559), .Y(n1350) );
OAI21XLTS U1584 ( .A0(n1348), .A1(n1438), .B0(n1350), .Y(n553) );
OAI21XLTS U1585 ( .A0(n1438), .A1(n1350), .B0(n898), .Y(n554) );
INVX2TS U1586 ( .A(rst), .Y(n529) );
BUFX3TS U1587 ( .A(n856), .Y(n1572) );
BUFX3TS U1588 ( .A(n1565), .Y(n1573) );
INVX2TS U1589 ( .A(n861), .Y(n1548) );
BUFX3TS U1590 ( .A(n854), .Y(n1515) );
BUFX3TS U1591 ( .A(n1565), .Y(n1568) );
BUFX3TS U1592 ( .A(n856), .Y(n1560) );
BUFX3TS U1593 ( .A(n1553), .Y(n1561) );
BUFX3TS U1594 ( .A(n856), .Y(n1567) );
BUFX3TS U1595 ( .A(n857), .Y(n1562) );
BUFX3TS U1596 ( .A(n853), .Y(n1563) );
BUFX3TS U1597 ( .A(n1531), .Y(n1542) );
CLKBUFX2TS U1598 ( .A(n892), .Y(n858) );
CLKBUFX2TS U1599 ( .A(n1521), .Y(n1545) );
BUFX3TS U1600 ( .A(n856), .Y(n1564) );
BUFX3TS U1601 ( .A(n1529), .Y(n1517) );
BUFX3TS U1602 ( .A(n1565), .Y(n1574) );
BUFX3TS U1603 ( .A(n1527), .Y(n1521) );
BUFX3TS U1604 ( .A(n855), .Y(n1523) );
BUFX3TS U1605 ( .A(n855), .Y(n1520) );
BUFX3TS U1606 ( .A(n892), .Y(n1540) );
BUFX3TS U1607 ( .A(n1527), .Y(n1529) );
BUFX3TS U1608 ( .A(n1527), .Y(n1522) );
BUFX3TS U1609 ( .A(n892), .Y(n1526) );
BUFX3TS U1610 ( .A(n854), .Y(n1530) );
BUFX3TS U1611 ( .A(n856), .Y(n1551) );
BUFX3TS U1612 ( .A(n1515), .Y(n1532) );
BUFX3TS U1613 ( .A(n1535), .Y(n1543) );
BUFX3TS U1614 ( .A(n856), .Y(n1552) );
BUFX3TS U1615 ( .A(n892), .Y(n1539) );
BUFX3TS U1616 ( .A(n1527), .Y(n1537) );
BUFX3TS U1617 ( .A(n853), .Y(n1555) );
BUFX3TS U1618 ( .A(n1576), .Y(n1553) );
BUFX3TS U1619 ( .A(n855), .Y(n1533) );
BUFX3TS U1620 ( .A(n857), .Y(n1556) );
BUFX3TS U1621 ( .A(n1532), .Y(n1531) );
BUFX3TS U1622 ( .A(n1527), .Y(n1528) );
BUFX3TS U1623 ( .A(n853), .Y(n1549) );
BUFX3TS U1624 ( .A(n856), .Y(n1575) );
BUFX3TS U1625 ( .A(n854), .Y(n1535) );
NAND2X1TS U1626 ( .A(cont_iter_out[2]), .B(n1322), .Y(n1321) );
NOR2X1TS U1627 ( .A(n1385), .B(n1321), .Y(n907) );
NAND2BX1TS U1628 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(n859), .Y(n960)
);
OR3X1TS U1629 ( .A(n960), .B(n1396), .C(inst_CORDIC_FSM_v3_state_reg[2]),
.Y(n860) );
OAI21XLTS U1630 ( .A0(n907), .A1(n861), .B0(n860), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
BUFX3TS U1631 ( .A(n1339), .Y(n1337) );
AO22XLTS U1632 ( .A0(n1138), .A1(d_ff3_sh_y_out[30]), .B0(n1337), .B1(
d_ff3_sh_x_out[30]), .Y(n623) );
NAND2X1TS U1633 ( .A(n964), .B(n1353), .Y(n545) );
NAND2X1TS U1634 ( .A(n863), .B(n1450), .Y(n915) );
AOI22X1TS U1635 ( .A0(n653), .A1(n867), .B0(n866), .B1(n652), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[12]) );
AOI22X1TS U1636 ( .A0(n683), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]), .B0(n681), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .Y(n869) );
AOI22X1TS U1637 ( .A0(n798), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .B0(n780), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .Y(n868) );
OAI211X1TS U1638 ( .A0(n884), .A1(n1449), .B0(n869), .C0(n868), .Y(n974) );
AOI21X1TS U1639 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(n974), .B0(n801), .Y(n870) );
OAI21X1TS U1640 ( .A0(n976), .A1(n796), .B0(n870), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[24]) );
AOI21X1TS U1641 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(n872), .B0(n801), .Y(n873) );
OAI21X1TS U1642 ( .A0(n874), .A1(n796), .B0(n873), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[22]) );
AOI21X1TS U1643 ( .A0(n1014), .A1(n879), .B0(n1012), .Y(n880) );
OAI21X1TS U1644 ( .A0(n881), .A1(n807), .B0(n880), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[2]) );
AOI21X1TS U1645 ( .A0(n1014), .A1(n882), .B0(n1012), .Y(n883) );
OAI21X1TS U1646 ( .A0(n884), .A1(n807), .B0(n883), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[8]) );
AOI21X1TS U1647 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(n885), .B0(n801), .Y(n886) );
OAI21X1TS U1648 ( .A0(n972), .A1(n796), .B0(n886), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[16]) );
AOI22X1TS U1649 ( .A0(n653), .A1(n888), .B0(n887), .B1(n652), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[10]) );
AOI22X1TS U1650 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(n890), .B0(n889), .B1(n652), .Y(inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[14])
);
BUFX3TS U1651 ( .A(n1517), .Y(n1525) );
NAND2X1TS U1652 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]), .B(n692),
.Y(n900) );
OAI21XLTS U1653 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]), .A1(
n692), .B0(n900), .Y(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[0]) );
NAND2X1TS U1654 ( .A(n700), .B(cont_iter_out[0]), .Y(intadd_403_CI) );
OAI21XLTS U1655 ( .A0(cont_iter_out[0]), .A1(n700), .B0(intadd_403_CI), .Y(
sh_exp_y[0]) );
NAND2X1TS U1656 ( .A(n698), .B(cont_iter_out[0]), .Y(intadd_402_CI) );
OAI21XLTS U1657 ( .A0(cont_iter_out[0]), .A1(n698), .B0(intadd_402_CI), .Y(
sh_exp_x[0]) );
INVX2TS U1658 ( .A(intadd_404_SUM_0_), .Y(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[1]) );
NOR2X1TS U1659 ( .A(cont_iter_out[0]), .B(cont_iter_out[1]), .Y(n899) );
NOR2XLTS U1660 ( .A(n1322), .B(n899), .Y(ITER_CONT_N3) );
OAI21XLTS U1661 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n1355), .B0(n1136), .Y(n625) );
INVX2TS U1662 ( .A(intadd_404_SUM_1_), .Y(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[2]) );
AOI22X1TS U1663 ( .A0(n1247), .A1(n893), .B0(n1246), .B1(n1272), .Y(n896) );
OAI21XLTS U1664 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(
n1386), .B0(n894), .Y(n895) );
XOR2XLTS U1665 ( .A(n896), .B(n895), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[3]) );
OAI21XLTS U1666 ( .A0(n1348), .A1(cont_iter_out[1]), .B0(n964), .Y(n558) );
OAI211XLTS U1667 ( .A0(n899), .A1(n898), .B0(n897), .C0(n1244), .Y(n549) );
INVX2TS U1668 ( .A(intadd_404_SUM_2_), .Y(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[3]) );
INVX2TS U1669 ( .A(n900), .Y(intadd_404_CI) );
NOR2X1TS U1670 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .B(
n1422), .Y(n906) );
AOI22X1TS U1671 ( .A0(n1247), .A1(n902), .B0(n901), .B1(n1024), .Y(n905) );
OAI21XLTS U1672 ( .A0(n906), .A1(n904), .B0(n905), .Y(n903) );
OAI31X1TS U1673 ( .A0(n906), .A1(n905), .A2(n904), .B0(n903), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[4]) );
NOR2X1TS U1674 ( .A(d_ff2_Y[27]), .B(intadd_403_n1), .Y(n1362) );
OR3X1TS U1675 ( .A(d_ff2_Y[28]), .B(d_ff2_Y[27]), .C(intadd_403_n1), .Y(
n1361) );
OAI21XLTS U1676 ( .A0(n1362), .A1(n1510), .B0(n1361), .Y(sh_exp_y[5]) );
NOR2X1TS U1677 ( .A(d_ff2_X[27]), .B(intadd_402_n1), .Y(n1365) );
OR3X1TS U1678 ( .A(d_ff2_X[28]), .B(d_ff2_X[27]), .C(intadd_402_n1), .Y(
n1364) );
OAI21XLTS U1679 ( .A0(n1365), .A1(n1509), .B0(n1364), .Y(sh_exp_x[5]) );
CLKAND2X2TS U1680 ( .A(n1321), .B(n1385), .Y(n551) );
NOR2X1TS U1681 ( .A(n909), .B(n908), .Y(n959) );
OAI21XLTS U1682 ( .A0(n1319), .A1(n1331), .B0(n958), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
AOI22X1TS U1683 ( .A0(n1247), .A1(n911), .B0(n910), .B1(n1024), .Y(n914) );
OAI21XLTS U1684 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(
n1387), .B0(n912), .Y(n913) );
XOR2XLTS U1685 ( .A(n914), .B(n913), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[5]) );
OAI21XLTS U1686 ( .A0(cont_iter_out[0]), .A1(n559), .B0(n1353), .Y(n543) );
INVX2TS U1687 ( .A(n1136), .Y(n1357) );
NOR3BX1TS U1688 ( .AN(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[7]), .C(n915), .Y(n1317) );
INVX2TS U1689 ( .A(n1355), .Y(n916) );
AOI211XLTS U1690 ( .A0(n1357), .A1(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(
n1354), .C0(n916), .Y(
inst_FPU_PIPELINED_FPADDSUB_enable_Pipeline_input) );
INVX4TS U1691 ( .A(n852), .Y(n938) );
INVX2TS U1692 ( .A(n917), .Y(n591) );
INVX2TS U1693 ( .A(n918), .Y(n590) );
INVX2TS U1694 ( .A(n919), .Y(n585) );
INVX2TS U1695 ( .A(n920), .Y(n594) );
INVX2TS U1696 ( .A(n921), .Y(n588) );
INVX2TS U1697 ( .A(n922), .Y(n593) );
AOI222X1TS U1698 ( .A0(n938), .A1(d_ff3_sh_y_out[4]), .B0(n1332), .B1(
d_ff3_sh_x_out[4]), .C0(n1331), .C1(d_ff3_LUT_out[4]), .Y(n923) );
INVX2TS U1699 ( .A(n923), .Y(n597) );
AOI222X1TS U1700 ( .A0(n938), .A1(d_ff2_X[0]), .B0(n1332), .B1(d_ff2_Y[0]),
.C0(n1342), .C1(d_ff2_Z[0]), .Y(n924) );
INVX2TS U1701 ( .A(n924), .Y(n561) );
AOI222X1TS U1702 ( .A0(n938), .A1(d_ff3_sh_y_out[2]), .B0(n1332), .B1(
d_ff3_sh_x_out[2]), .C0(n1342), .C1(d_ff3_LUT_out[2]), .Y(n925) );
INVX2TS U1703 ( .A(n925), .Y(n595) );
INVX2TS U1704 ( .A(n926), .Y(n586) );
INVX2TS U1705 ( .A(n927), .Y(n587) );
INVX2TS U1706 ( .A(n928), .Y(n619) );
INVX2TS U1707 ( .A(n929), .Y(n618) );
INVX2TS U1708 ( .A(n930), .Y(n605) );
INVX2TS U1709 ( .A(n931), .Y(n614) );
AOI222X1TS U1710 ( .A0(n1138), .A1(d_ff3_sh_y_out[9]), .B0(n1337), .B1(
d_ff3_sh_x_out[9]), .C0(n1331), .C1(d_ff3_LUT_out[9]), .Y(n932) );
INVX2TS U1711 ( .A(n932), .Y(n602) );
AOI222X1TS U1712 ( .A0(n1138), .A1(d_ff3_sh_y_out[24]), .B0(n1337), .B1(
d_ff3_sh_x_out[24]), .C0(n1331), .C1(d_ff3_LUT_out[24]), .Y(n933) );
INVX2TS U1713 ( .A(n933), .Y(n617) );
AOI222X1TS U1714 ( .A0(n1138), .A1(d_ff3_sh_y_out[8]), .B0(n1337), .B1(
d_ff3_sh_x_out[8]), .C0(n1331), .C1(d_ff3_LUT_out[8]), .Y(n934) );
INVX2TS U1715 ( .A(n934), .Y(n601) );
AOI222X1TS U1716 ( .A0(n1138), .A1(d_ff3_sh_y_out[10]), .B0(n1337), .B1(
d_ff3_sh_x_out[10]), .C0(n1331), .C1(d_ff3_LUT_out[10]), .Y(n935) );
INVX2TS U1717 ( .A(n935), .Y(n603) );
AOI222X1TS U1718 ( .A0(n1138), .A1(d_ff3_sh_y_out[6]), .B0(n1337), .B1(
d_ff3_sh_x_out[6]), .C0(n950), .C1(d_ff3_LUT_out[6]), .Y(n936) );
INVX2TS U1719 ( .A(n936), .Y(n599) );
INVX2TS U1720 ( .A(n937), .Y(n589) );
AOI222X1TS U1721 ( .A0(n938), .A1(d_ff2_X[31]), .B0(n1332), .B1(d_ff2_Y[31]),
.C0(n1342), .C1(d_ff2_Z[31]), .Y(n939) );
INVX2TS U1722 ( .A(n939), .Y(n592) );
INVX2TS U1723 ( .A(n940), .Y(n616) );
INVX2TS U1724 ( .A(ready_cordic), .Y(n1294) );
OAI21XLTS U1725 ( .A0(cont_iter_out[1]), .A1(n1350), .B0(n964), .Y(n556) );
INVX4TS U1726 ( .A(n852), .Y(n946) );
BUFX3TS U1727 ( .A(n1336), .Y(n1331) );
AOI222X1TS U1728 ( .A0(n946), .A1(d_ff2_X[22]), .B0(n1323), .B1(d_ff2_Y[22]),
.C0(n950), .C1(d_ff2_Z[22]), .Y(n1579) );
AOI222X1TS U1729 ( .A0(n946), .A1(d_ff2_X[20]), .B0(n1323), .B1(d_ff2_Y[20]),
.C0(n1347), .C1(d_ff2_Z[20]), .Y(n1581) );
AOI222X1TS U1730 ( .A0(n946), .A1(d_ff2_X[21]), .B0(n1344), .B1(d_ff2_Y[21]),
.C0(n950), .C1(d_ff2_Z[21]), .Y(n1580) );
AOI222X1TS U1731 ( .A0(n946), .A1(d_ff2_X[11]), .B0(n1344), .B1(d_ff2_Y[11]),
.C0(n1347), .C1(d_ff2_Z[11]), .Y(n1589) );
AOI222X1TS U1732 ( .A0(n946), .A1(d_ff2_X[23]), .B0(n1323), .B1(d_ff2_Y[23]),
.C0(n1342), .C1(d_ff2_Z[23]), .Y(n1578) );
AOI222X1TS U1733 ( .A0(n946), .A1(d_ff2_X[17]), .B0(n1323), .B1(d_ff2_Y[17]),
.C0(n950), .C1(d_ff2_Z[17]), .Y(n1584) );
AOI222X1TS U1734 ( .A0(n946), .A1(d_ff2_X[15]), .B0(n1344), .B1(d_ff2_Y[15]),
.C0(n950), .C1(d_ff2_Z[15]), .Y(n1585) );
AOI222X1TS U1735 ( .A0(n946), .A1(d_ff2_X[13]), .B0(n1344), .B1(d_ff2_Y[13]),
.C0(n1347), .C1(d_ff2_Z[13]), .Y(n1587) );
AOI222X1TS U1736 ( .A0(n946), .A1(d_ff2_X[14]), .B0(n1323), .B1(d_ff2_Y[14]),
.C0(n950), .C1(d_ff2_Z[14]), .Y(n1586) );
AOI222X1TS U1737 ( .A0(n946), .A1(d_ff2_X[12]), .B0(n1323), .B1(d_ff2_Y[12]),
.C0(n950), .C1(d_ff2_Z[12]), .Y(n1588) );
AOI222X1TS U1738 ( .A0(n946), .A1(d_ff2_X[18]), .B0(n1344), .B1(d_ff2_Y[18]),
.C0(n1347), .C1(d_ff2_Z[18]), .Y(n1583) );
AOI222X1TS U1739 ( .A0(n946), .A1(d_ff2_X[19]), .B0(n1344), .B1(d_ff2_Y[19]),
.C0(n950), .C1(d_ff2_Z[19]), .Y(n1582) );
AOI222X1TS U1740 ( .A0(n1345), .A1(d_ff2_X[8]), .B0(n1323), .B1(d_ff2_Y[8]),
.C0(n1347), .C1(d_ff2_Z[8]), .Y(n941) );
INVX2TS U1741 ( .A(n941), .Y(n569) );
AOI222X1TS U1742 ( .A0(n1345), .A1(d_ff2_X[1]), .B0(n1344), .B1(d_ff2_Y[1]),
.C0(n950), .C1(d_ff2_Z[1]), .Y(n942) );
INVX2TS U1743 ( .A(n942), .Y(n562) );
AOI222X1TS U1744 ( .A0(n1345), .A1(d_ff2_X[2]), .B0(n1323), .B1(d_ff2_Y[2]),
.C0(n1347), .C1(d_ff2_Z[2]), .Y(n943) );
INVX2TS U1745 ( .A(n943), .Y(n563) );
AOI222X1TS U1746 ( .A0(n1345), .A1(d_ff2_X[9]), .B0(n1344), .B1(d_ff2_Y[9]),
.C0(n950), .C1(d_ff2_Z[9]), .Y(n944) );
INVX2TS U1747 ( .A(n944), .Y(n570) );
AOI222X1TS U1748 ( .A0(n1345), .A1(d_ff2_X[3]), .B0(n1323), .B1(d_ff2_Y[3]),
.C0(n1347), .C1(d_ff2_Z[3]), .Y(n945) );
INVX2TS U1749 ( .A(n945), .Y(n564) );
AOI222X1TS U1750 ( .A0(n946), .A1(d_ff2_X[16]), .B0(n1344), .B1(d_ff2_Y[16]),
.C0(n1331), .C1(d_ff2_Z[16]), .Y(n947) );
INVX2TS U1751 ( .A(n947), .Y(n577) );
AOI222X1TS U1752 ( .A0(n1345), .A1(d_ff2_X[6]), .B0(n1323), .B1(d_ff2_Y[6]),
.C0(n1331), .C1(d_ff2_Z[6]), .Y(n948) );
INVX2TS U1753 ( .A(n948), .Y(n567) );
AOI222X1TS U1754 ( .A0(n1345), .A1(d_ff2_X[4]), .B0(n1323), .B1(d_ff2_Y[4]),
.C0(n1331), .C1(d_ff2_Z[4]), .Y(n949) );
INVX2TS U1755 ( .A(n949), .Y(n565) );
AOI222X1TS U1756 ( .A0(n1345), .A1(d_ff2_X[7]), .B0(n1344), .B1(d_ff2_Y[7]),
.C0(n950), .C1(d_ff2_Z[7]), .Y(n1590) );
AOI222X1TS U1757 ( .A0(n1345), .A1(d_ff2_X[5]), .B0(n1323), .B1(d_ff2_Y[5]),
.C0(n1347), .C1(d_ff2_Z[5]), .Y(n1591) );
AOI222X1TS U1758 ( .A0(n1345), .A1(d_ff2_X[10]), .B0(n1344), .B1(d_ff2_Y[10]), .C0(n1331), .C1(d_ff2_Z[10]), .Y(n951) );
INVX2TS U1759 ( .A(n951), .Y(n571) );
NOR2X1TS U1760 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .B(
n1424), .Y(n957) );
AOI22X1TS U1761 ( .A0(n1247), .A1(n953), .B0(n952), .B1(n1024), .Y(n956) );
OAI31X1TS U1762 ( .A0(n957), .A1(n956), .A2(n955), .B0(n954), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[6]) );
INVX2TS U1763 ( .A(n958), .Y(enab_RB3) );
NAND3BX1TS U1764 ( .AN(inst_CORDIC_FSM_v3_state_reg[3]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(n959), .Y(n1315) );
OAI31X1TS U1765 ( .A0(inst_CORDIC_FSM_v3_state_reg[2]), .A1(n1396), .A2(n960), .B0(n1315), .Y(enab_d_ff_RB1) );
NOR4X1TS U1766 ( .A(inst_CORDIC_FSM_v3_state_next[3]), .B(n1548), .C(
enab_RB3), .D(enab_d_ff_RB1), .Y(n961) );
AOI32X1TS U1767 ( .A0(n1354), .A1(n1294), .A2(n961), .B0(ready_cordic), .B1(
ack_cordic), .Y(n962) );
BUFX3TS U1768 ( .A(n1301), .Y(n1303) );
OR2X1TS U1769 ( .A(d_ff_Xn[19]), .B(n1300), .Y(first_mux_X[19]) );
OR2X1TS U1770 ( .A(d_ff_Xn[3]), .B(n1300), .Y(first_mux_X[3]) );
OR2X1TS U1771 ( .A(d_ff_Xn[20]), .B(n1300), .Y(first_mux_X[20]) );
OR2X1TS U1772 ( .A(d_ff_Xn[2]), .B(n1300), .Y(first_mux_X[2]) );
OR2X1TS U1773 ( .A(d_ff_Xn[17]), .B(n1300), .Y(first_mux_X[17]) );
OR2X1TS U1774 ( .A(d_ff_Xn[1]), .B(n1300), .Y(first_mux_X[1]) );
OR2X1TS U1775 ( .A(d_ff_Xn[16]), .B(n1300), .Y(first_mux_X[16]) );
OR2X1TS U1776 ( .A(d_ff_Xn[12]), .B(n1300), .Y(first_mux_X[12]) );
OR2X1TS U1777 ( .A(d_ff_Xn[10]), .B(n1300), .Y(first_mux_X[10]) );
OR2X1TS U1778 ( .A(d_ff_Xn[6]), .B(n1300), .Y(first_mux_X[6]) );
INVX2TS U1779 ( .A(n1301), .Y(n963) );
OR2X1TS U1780 ( .A(d_ff_Xn[13]), .B(n963), .Y(first_mux_X[13]) );
OR2X1TS U1781 ( .A(d_ff_Xn[24]), .B(n963), .Y(first_mux_X[24]) );
OR2X1TS U1782 ( .A(d_ff_Xn[29]), .B(n963), .Y(first_mux_X[29]) );
OR2X1TS U1783 ( .A(d_ff_Xn[7]), .B(n963), .Y(first_mux_X[7]) );
OR2X1TS U1784 ( .A(d_ff_Xn[27]), .B(n963), .Y(first_mux_X[27]) );
OR2X1TS U1785 ( .A(d_ff_Xn[26]), .B(n963), .Y(first_mux_X[26]) );
OAI21X1TS U1786 ( .A0(n1348), .A1(n1438), .B0(n964), .Y(n557) );
OR2X1TS U1787 ( .A(n557), .B(n1352), .Y(n544) );
AOI22X1TS U1788 ( .A0(n1247), .A1(n966), .B0(n965), .B1(n1024), .Y(n969) );
OAI21XLTS U1789 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(
n1425), .B0(n967), .Y(n968) );
AOI22X1TS U1790 ( .A0(n683), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]), .B0(n684), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .Y(n971) );
AOI22X1TS U1791 ( .A0(n681), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .B0(n798), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .Y(n970) );
OAI211X1TS U1792 ( .A0(n972), .A1(n1449), .B0(n971), .C0(n970), .Y(n977) );
AOI21X1TS U1793 ( .A0(n653), .A1(n977), .B0(n801), .Y(n973) );
AOI21X1TS U1794 ( .A0(n652), .A1(n974), .B0(n1012), .Y(n975) );
AOI21X1TS U1795 ( .A0(n652), .A1(n977), .B0(n1012), .Y(n978) );
NOR2X1TS U1796 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .B(
n1426), .Y(n985) );
AOI22X1TS U1797 ( .A0(n1247), .A1(n981), .B0(n980), .B1(n1024), .Y(n984) );
OAI31X1TS U1798 ( .A0(n985), .A1(n984), .A2(n983), .B0(n982), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[8]) );
AOI22X1TS U1799 ( .A0(n1247), .A1(n987), .B0(n986), .B1(n1024), .Y(n990) );
OAI21XLTS U1800 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(
n1389), .B0(n988), .Y(n989) );
NOR2X1TS U1801 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .B(
n1428), .Y(n996) );
AOI22X1TS U1802 ( .A0(n1247), .A1(n992), .B0(n991), .B1(n1024), .Y(n995) );
OAI31X1TS U1803 ( .A0(n996), .A1(n995), .A2(n994), .B0(n993), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[10]) );
AOI22X1TS U1804 ( .A0(n1247), .A1(n998), .B0(n997), .B1(n1024), .Y(n1001) );
OAI21XLTS U1805 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]),
.A1(n1390), .B0(n999), .Y(n1000) );
AOI21X1TS U1806 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n1002), .B0(n801), .Y(n1003) );
OAI21X1TS U1807 ( .A0(n1004), .A1(n796), .B0(n1003), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[20]) );
AOI21X1TS U1808 ( .A0(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .A1(
n1005), .B0(n801), .Y(n1007) );
OAI21X1TS U1809 ( .A0(n1008), .A1(n796), .B0(n1007), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[18]) );
AOI21X1TS U1810 ( .A0(n1014), .A1(n1009), .B0(n1012), .Y(n1010) );
OAI21X1TS U1811 ( .A0(n1011), .A1(n807), .B0(n1010), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[6]) );
AOI21X1TS U1812 ( .A0(n1014), .A1(n1013), .B0(n1012), .Y(n1015) );
OAI21X1TS U1813 ( .A0(n1016), .A1(n807), .B0(n1015), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[4]) );
NOR2BX1TS U1814 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1017) );
XOR2X1TS U1815 ( .A(n1391), .B(n1017), .Y(DP_OP_33J164_122_2179_n15) );
NOR2BX1TS U1816 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1018) );
XOR2X1TS U1817 ( .A(n1391), .B(n1018), .Y(DP_OP_33J164_122_2179_n14) );
AOI22X1TS U1818 ( .A0(n686), .A1(n1020), .B0(n1019), .B1(n1024), .Y(n1023)
);
OAI21XLTS U1819 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]),
.A1(n1392), .B0(n1021), .Y(n1022) );
NOR2X1TS U1820 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .B(
n1445), .Y(n1030) );
AOI22X1TS U1821 ( .A0(n686), .A1(n1026), .B0(n1025), .B1(n1024), .Y(n1029)
);
OAI31X1TS U1822 ( .A0(n1030), .A1(n1029), .A2(n1028), .B0(n1027), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[16]) );
AOI22X1TS U1823 ( .A0(n1546), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n657), .Y(n1083)
);
INVX2TS U1824 ( .A(n1068), .Y(n1081) );
AOI22X1TS U1825 ( .A0(n1546), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n1077), .B1(
n1081), .Y(n1033) );
AOI22X1TS U1826 ( .A0(n656), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n1052), .Y(
n1034) );
OAI22X1TS U1827 ( .A0(n1055), .A1(n1075), .B0(n1109), .B1(n655), .Y(n1036)
);
AOI21X1TS U1828 ( .A0(n741), .A1(n1111), .B0(n1036), .Y(n1037) );
AOI222X4TS U1829 ( .A0(n1311), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(n1546), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(n656), .Y(n1103) );
AOI22X1TS U1830 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]),
.A1(n1546), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12]),
.B1(n1052), .Y(n1039) );
AOI222X4TS U1831 ( .A0(n1311), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]), .B0(n1546), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(n656), .Y(n1090) );
AOI222X4TS U1832 ( .A0(n1311), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]), .B0(n1546), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n656), .Y(n1095) );
OAI22X1TS U1833 ( .A0(n1090), .A1(n650), .B0(n1095), .B1(n1075), .Y(n1040)
);
AOI21X1TS U1834 ( .A0(n741), .A1(n1105), .B0(n1040), .Y(n1041) );
AOI222X4TS U1835 ( .A0(n1311), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .B1(n657), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .C1(n1312), .Y(n1091) );
AOI22X1TS U1836 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(
n1546), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(
n1052), .Y(n1042) );
AOI222X4TS U1837 ( .A0(n1311), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .B1(n657), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .C1(n1312), .Y(n1108) );
AOI222X4TS U1838 ( .A0(n1311), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B1(n657), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .C1(n1312), .Y(n1114) );
OAI22X1TS U1839 ( .A0(n1108), .A1(n651), .B0(n1114), .B1(n1075), .Y(n1043)
);
AOI21X1TS U1840 ( .A0(n741), .A1(n1093), .B0(n1043), .Y(n1044) );
AOI22X1TS U1841 ( .A0(n656), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n1052), .Y(n1045) );
AOI222X4TS U1842 ( .A0(n1311), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(n1312), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n656), .Y(n1102) );
AOI222X4TS U1843 ( .A0(n1311), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n657), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n1312), .Y(
n1107) );
OAI22X1TS U1844 ( .A0(n1102), .A1(n651), .B0(n1107), .B1(n1075), .Y(n1046)
);
AOI21X1TS U1845 ( .A0(n741), .A1(n1087), .B0(n1046), .Y(n1047) );
AOI222X4TS U1846 ( .A0(n1052), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]), .B0(n1546), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .C1(n656), .Y(n1097)
);
AOI22X1TS U1847 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]),
.A1(n1546), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(
n1052), .Y(n1048) );
AOI222X4TS U1848 ( .A0(n1052), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n657), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n1312), .Y(
n1084) );
AOI222X4TS U1849 ( .A0(n1311), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n657), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(n1312), .Y(
n1089) );
OAI22X1TS U1850 ( .A0(n1084), .A1(n650), .B0(n1089), .B1(n1075), .Y(n1050)
);
AOI21X1TS U1851 ( .A0(n741), .A1(n1099), .B0(n1050), .Y(n1051) );
AOI222X4TS U1852 ( .A0(n1052), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]), .B0(n1312), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .C1(n656), .Y(n1101)
);
OAI22X1TS U1853 ( .A0(n1096), .A1(n651), .B0(n1101), .B1(n1075), .Y(n1053)
);
AOI21X1TS U1854 ( .A0(n743), .A1(n1081), .B0(n1053), .Y(n1054) );
OAI22X1TS U1855 ( .A0(n1055), .A1(n651), .B0(n1109), .B1(n1075), .Y(n1056)
);
AOI21X1TS U1856 ( .A0(n743), .A1(n1111), .B0(n1056), .Y(n1057) );
OAI22X1TS U1857 ( .A0(n1089), .A1(n650), .B0(n1097), .B1(n1075), .Y(n1058)
);
AOI21X1TS U1858 ( .A0(n743), .A1(n1099), .B0(n1058), .Y(n1059) );
OAI22X1TS U1859 ( .A0(n1114), .A1(n651), .B0(n1091), .B1(n1075), .Y(n1060)
);
AOI21X1TS U1860 ( .A0(n743), .A1(n1093), .B0(n1060), .Y(n1061) );
OAI22X1TS U1861 ( .A0(n1095), .A1(n650), .B0(n1103), .B1(n1075), .Y(n1062)
);
AOI21X1TS U1862 ( .A0(n743), .A1(n1105), .B0(n1062), .Y(n1063) );
OAI22X1TS U1863 ( .A0(n1107), .A1(n650), .B0(n1085), .B1(n1075), .Y(n1064)
);
AOI21X1TS U1864 ( .A0(n743), .A1(n1087), .B0(n1064), .Y(n1065) );
OAI22X1TS U1865 ( .A0(n1096), .A1(n1075), .B0(n1101), .B1(n655), .Y(n1066)
);
AOI21X1TS U1866 ( .A0(n1077), .A1(n1099), .B0(n1066), .Y(n1067) );
OAI22X1TS U1867 ( .A0(n1108), .A1(n687), .B0(n1114), .B1(n655), .Y(n1069) );
AOI21X1TS U1868 ( .A0(n1077), .A1(n1111), .B0(n1069), .Y(n1070) );
OAI22X1TS U1869 ( .A0(n1090), .A1(n687), .B0(n1095), .B1(n654), .Y(n1071) );
AOI21X1TS U1870 ( .A0(n1077), .A1(n1093), .B0(n1071), .Y(n1072) );
OAI22X1TS U1871 ( .A0(n1102), .A1(n687), .B0(n1107), .B1(n654), .Y(n1073) );
AOI21X1TS U1872 ( .A0(n1077), .A1(n1105), .B0(n1073), .Y(n1074) );
OAI22X1TS U1873 ( .A0(n1084), .A1(n687), .B0(n1089), .B1(n654), .Y(n1076) );
AOI21X1TS U1874 ( .A0(n1077), .A1(n1087), .B0(n1076), .Y(n1078) );
OAI22X1TS U1875 ( .A0(n1101), .A1(n651), .B0(n1079), .B1(n655), .Y(n1080) );
AOI21X1TS U1876 ( .A0(n1112), .A1(n1081), .B0(n1080), .Y(n1082) );
OAI22X1TS U1877 ( .A0(n1085), .A1(n650), .B0(n1084), .B1(n654), .Y(n1086) );
AOI21X1TS U1878 ( .A0(n1112), .A1(n1087), .B0(n1086), .Y(n1088) );
OAI22X1TS U1879 ( .A0(n1091), .A1(n651), .B0(n1090), .B1(n655), .Y(n1092) );
AOI21X1TS U1880 ( .A0(n1112), .A1(n1093), .B0(n1092), .Y(n1094) );
OAI22X1TS U1881 ( .A0(n1097), .A1(n650), .B0(n1096), .B1(n654), .Y(n1098) );
AOI21X1TS U1882 ( .A0(n1112), .A1(n1099), .B0(n1098), .Y(n1100) );
OAI22X1TS U1883 ( .A0(n1103), .A1(n650), .B0(n1102), .B1(n654), .Y(n1104) );
AOI21X1TS U1884 ( .A0(n1112), .A1(n1105), .B0(n1104), .Y(n1106) );
OAI22X1TS U1885 ( .A0(n1109), .A1(n651), .B0(n1108), .B1(n655), .Y(n1110) );
AOI21X1TS U1886 ( .A0(n1112), .A1(n1111), .B0(n1110), .Y(n1113) );
NOR3X1TS U1887 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .B(
n1131), .C(n1434), .Y(n1127) );
OAI211X1TS U1888 ( .A0(n1122), .A1(n1121), .B0(n1120), .C0(n1119), .Y(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[3]) );
OAI31X1TS U1889 ( .A0(n1125), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .A2(n1124), .B0(
n1123), .Y(n1126) );
AOI211X1TS U1890 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]),
.A1(n1128), .B0(n1127), .C0(n1126), .Y(n1129) );
OAI211X1TS U1891 ( .A0(n1512), .A1(n1131), .B0(n1130), .C0(n1129), .Y(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[4]) );
NOR3XLTS U1892 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .C(n1481), .Y(
enab_d_ff4_Xn) );
NOR2BX1TS U1893 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1132) );
XOR2X1TS U1894 ( .A(n1391), .B(n1132), .Y(DP_OP_33J164_122_2179_n16) );
NOR2BX1TS U1895 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1133) );
XOR2X1TS U1896 ( .A(n1391), .B(n1133), .Y(DP_OP_33J164_122_2179_n17) );
XOR2X1TS U1897 ( .A(n1391), .B(n1134), .Y(DP_OP_33J164_122_2179_n18) );
NOR2BX1TS U1898 ( .AN(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_GTComparator_N0), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[30]) );
XOR2XLTS U1899 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27]), .Y(n1135) );
XOR2XLTS U1900 ( .A(intadd_404_n1), .B(n1135), .Y(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[4]) );
AOI22X1TS U1901 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(
n1136), .B1(n1476), .Y(n1593) );
AOI21X1TS U1902 ( .A0(n1137), .A1(n694), .B0(n1247), .Y(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_SGF) );
NOR2BX1TS U1903 ( .AN(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(
inst_FPU_PIPELINED_FPADDSUB__19_net_) );
AO22XLTS U1904 ( .A0(n1138), .A1(d_ff3_sh_y_out[31]), .B0(n1337), .B1(
d_ff3_sh_x_out[31]), .Y(n1140) );
XOR2XLTS U1905 ( .A(d_ff3_sign_out), .B(cont_var_out[0]), .Y(n1139) );
XNOR2X1TS U1906 ( .A(n1140), .B(n1139), .Y(n1513) );
XNOR2X1TS U1907 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .B(n1577),
.Y(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_INIT) );
AOI22X1TS U1908 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .B0(n1416), .B1(n1468),
.Y(n1147) );
AOI22X1TS U1909 ( .A0(n1401), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .B0(n1452), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .Y(n1141) );
OAI221XLTS U1910 ( .A0(n1401), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .B0(n1452), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .C0(n1141), .Y(n1146) );
AOI22X1TS U1911 ( .A0(n1458), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .B0(n1411), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .Y(n1142) );
AOI22X1TS U1912 ( .A0(n1405), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]),
.B0(n1463), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .Y(n1143)
);
OAI221XLTS U1913 ( .A0(n1405), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .B0(n1463), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .C0(n1143), .Y(
n1144) );
NOR4X1TS U1914 ( .A(n1147), .B(n1146), .C(n1145), .D(n1144), .Y(n1175) );
AOI22X1TS U1915 ( .A0(n1404), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]),
.B0(n1465), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .Y(n1148)
);
AOI22X1TS U1916 ( .A0(n1403), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]),
.B0(n1461), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .Y(n1149)
);
OAI221XLTS U1917 ( .A0(n1403), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .B0(n1461), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .C0(n1149), .Y(
n1154) );
AOI22X1TS U1918 ( .A0(n1400), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]),
.B0(n1467), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .Y(n1150)
);
AOI22X1TS U1919 ( .A0(n1456), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]),
.B0(n1410), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .Y(n1151)
);
OAI221XLTS U1920 ( .A0(n1456), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .B0(n1410), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .C0(n1151), .Y(
n1152) );
NOR4X1TS U1921 ( .A(n1155), .B(n1154), .C(n1153), .D(n1152), .Y(n1174) );
AOI22X1TS U1922 ( .A0(n691), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]),
.B0(n1462), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .Y(n1156)
);
AOI22X1TS U1923 ( .A0(n1406), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .B0(n1471), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .Y(n1157) );
OAI221XLTS U1924 ( .A0(n1406), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .B0(n1471), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .C0(n1157), .Y(n1162) );
AOI22X1TS U1925 ( .A0(n1409), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B0(n1466), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .Y(n1158) );
AOI22X1TS U1926 ( .A0(n1460), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .B0(n1412), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .Y(n1159) );
OAI221XLTS U1927 ( .A0(n1460), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .B0(n1412), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .C0(n1159), .Y(n1160) );
NOR4X1TS U1928 ( .A(n1163), .B(n1162), .C(n1161), .D(n1160), .Y(n1173) );
AOI22X1TS U1929 ( .A0(n1407), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B0(n1472), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .Y(n1164) );
AOI22X1TS U1930 ( .A0(n1457), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]),
.B0(n1402), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .Y(n1165)
);
OAI221XLTS U1931 ( .A0(n1457), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .B0(n1402), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .C0(n1165), .Y(
n1170) );
AOI22X1TS U1932 ( .A0(n1459), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .B0(n1475), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .Y(n1166) );
AOI22X1TS U1933 ( .A0(n1408), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .B0(n1464), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .Y(n1167) );
OAI221XLTS U1934 ( .A0(n1408), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .B0(n1464), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .C0(n1167), .Y(n1168) );
NOR4X1TS U1935 ( .A(n1171), .B(n1170), .C(n1169), .D(n1168), .Y(n1172) );
NAND4XLTS U1936 ( .A(n1175), .B(n1174), .C(n1173), .D(n1172), .Y(n1242) );
NOR2BX1TS U1937 ( .AN(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_INIT), .B(n1242),
.Y(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_INIT) );
NOR2X1TS U1938 ( .A(n1502), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]),
.Y(n1236) );
AOI22X1TS U1939 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .A1(n1502), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B1(n1176), .Y(n1180) );
OAI21X1TS U1940 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .A1(n1507), .B0(n1177), .Y(n1237) );
NOR2X1TS U1941 ( .A(n1451), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]),
.Y(n1184) );
NOR2X1TS U1942 ( .A(n1399), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]),
.Y(n1181) );
AOI211X1TS U1943 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .A1(
n1182), .B0(n1184), .C0(n1181), .Y(n1235) );
NOR3X1TS U1944 ( .A(n1182), .B(n1181), .C(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .Y(n1183) );
AOI2BB2X1TS U1945 ( .B0(n1186), .B1(n1235), .A0N(n1185), .A1N(n1184), .Y(
n1241) );
NOR2X1TS U1946 ( .A(n1500), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]),
.Y(n1222) );
NOR2X1TS U1947 ( .A(n1503), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]),
.Y(n1201) );
AOI21X1TS U1948 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .A1(n1458), .B0(n1201), .Y(n1206) );
OAI2BB1X1TS U1949 ( .A0N(n1403), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .Y(n1187) );
OAI22X1TS U1950 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .A1(n1187),
.B0(n1403), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .Y(n1198)
);
OAI2BB1X1TS U1951 ( .A0N(n1404), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .Y(n1188) );
OAI22X1TS U1952 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .A1(n1188),
.B0(n1404), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .Y(n1197)
);
OAI2BB2XLTS U1953 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .B1(
n1189), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1N(n1504),
.Y(n1191) );
AOI222X1TS U1954 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .A1(n1461), .B0(n1194), .B1(n1193), .C0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .C1(
n1403), .Y(n1196) );
AOI22X1TS U1955 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .A1(n1404),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .B1(n1462), .Y(n1195)
);
OAI32X1TS U1956 ( .A0(n1198), .A1(n1197), .A2(n1196), .B0(n1195), .B1(n1197),
.Y(n1216) );
OA22X1TS U1957 ( .A0(n1419), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]),
.B0(n1506), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .Y(n1213)
);
OAI2BB2XLTS U1958 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .B1(
n1200), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .A1N(n1489),
.Y(n1212) );
AOI22X1TS U1959 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .A1(n1503), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .B1(n1202), .Y(n1208) );
AOI21X1TS U1960 ( .A0(n1205), .A1(n1204), .B0(n1215), .Y(n1207) );
OAI2BB2XLTS U1961 ( .B0(n1208), .B1(n1215), .A0N(n1207), .A1N(n1206), .Y(
n1211) );
OAI2BB2XLTS U1962 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .B1(
n1209), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .A1N(n1506),
.Y(n1210) );
AOI211X1TS U1963 ( .A0(n1213), .A1(n1212), .B0(n1211), .C0(n1210), .Y(n1214)
);
OAI31X1TS U1964 ( .A0(n1217), .A1(n1216), .A2(n1215), .B0(n1214), .Y(n1220)
);
OA22X1TS U1965 ( .A0(n1493), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]),
.B0(n1416), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .Y(n1233)
);
OAI21X1TS U1966 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .A1(n1501), .B0(n1224), .Y(n1228) );
AOI211X1TS U1967 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .A1(
n1475), .B0(n1227), .C0(n1228), .Y(n1219) );
OAI2BB2XLTS U1968 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B1(
n1221), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .A1N(n1490),
.Y(n1232) );
AOI22X1TS U1969 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .A1(n1500), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .B1(n1223), .Y(n1226) );
AOI32X1TS U1970 ( .A0(n1501), .A1(n1224), .A2(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .B1(n1418), .Y(n1225) );
OAI32X1TS U1971 ( .A0(n1228), .A1(n1227), .A2(n1226), .B0(n1225), .B1(n1227),
.Y(n1231) );
OAI2BB2XLTS U1972 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .B1(
n1229), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .A1N(n1416),
.Y(n1230) );
AOI211X1TS U1973 ( .A0(n1233), .A1(n1232), .B0(n1231), .C0(n1230), .Y(n1239)
);
NAND4BBX1TS U1974 ( .AN(n1237), .BN(n1236), .C(n1235), .D(n1234), .Y(n1238)
);
AOI32X1TS U1975 ( .A0(n1241), .A1(n1240), .A2(n1239), .B0(n1238), .B1(n1241),
.Y(n1282) );
AOI21X1TS U1976 ( .A0(n1242), .A1(n1291), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .Y(n1243) );
AOI21X1TS U1977 ( .A0(n1577), .A1(n1292), .B0(n1243), .Y(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_INIT) );
AOI32X1TS U1978 ( .A0(cont_iter_out[3]), .A1(n1244), .A2(n1438), .B0(
cont_iter_out[2]), .B1(n1244), .Y(data_out_LUT[4]) );
OAI22X1TS U1979 ( .A0(cont_iter_out[3]), .A1(n1321), .B0(cont_iter_out[2]),
.B1(n1322), .Y(data_out_LUT[25]) );
NAND2X1TS U1980 ( .A(inst_FPU_PIPELINED_FPADDSUB_N59), .B(n1247), .Y(n1245)
);
XNOR2X1TS U1981 ( .A(n1245), .B(inst_FPU_PIPELINED_FPADDSUB_N60), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[1]) );
OAI21XLTS U1982 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .B0(n1246), .Y(n1250) );
NAND2X1TS U1983 ( .A(n1248), .B(n1247), .Y(n1249) );
XOR2XLTS U1984 ( .A(n1250), .B(n1249), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[2]) );
AOI22X1TS U1985 ( .A0(n686), .A1(n1252), .B0(n1251), .B1(n1547), .Y(n1255)
);
AOI22X1TS U1986 ( .A0(n686), .A1(n1257), .B0(n1256), .B1(n1272), .Y(n1260)
);
AOI22X1TS U1987 ( .A0(n686), .A1(n1262), .B0(n1261), .B1(n1547), .Y(n1265)
);
AOI22X1TS U1988 ( .A0(n686), .A1(n1267), .B0(n1266), .B1(n1547), .Y(n1270)
);
AOI21X1TS U1989 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]),
.A1(n693), .B0(n1271), .Y(n1276) );
AOI22X1TS U1990 ( .A0(n686), .A1(n1274), .B0(n1273), .B1(n1272), .Y(n1275)
);
NAND2X1TS U1991 ( .A(d_ff1_operation_out), .B(n676), .Y(n1279) );
XOR2X1TS U1992 ( .A(n699), .B(n1277), .Y(n1278) );
BUFX3TS U1993 ( .A(n1308), .Y(n1306) );
AOI22X1TS U1994 ( .A0(n1307), .A1(d_ff_Yn[31]), .B0(d_ff_Xn[31]), .B1(n1306),
.Y(n1281) );
XNOR2X1TS U1995 ( .A(n1281), .B(n1280), .Y(fmtted_Result_31_) );
BUFX3TS U1996 ( .A(n1288), .Y(n1284) );
BUFX3TS U1997 ( .A(n1284), .Y(n1283) );
AOI22X1TS U1998 ( .A0(n1283), .A1(n1508), .B0(n1410), .B1(n1287), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[0]) );
AOI22X1TS U1999 ( .A0(n1283), .A1(n1504), .B0(n1456), .B1(n1292), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[1]) );
AOI22X1TS U2000 ( .A0(n1283), .A1(n1491), .B0(n1411), .B1(n1287), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[2]) );
AOI22X1TS U2001 ( .A0(n1283), .A1(n1505), .B0(n1400), .B1(n1292), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[3]) );
AOI22X1TS U2002 ( .A0(n1283), .A1(n1486), .B0(n1461), .B1(n1287), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[4]) );
AOI22X1TS U2003 ( .A0(n1283), .A1(n1483), .B0(n1403), .B1(n1291), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[5]) );
AOI22X1TS U2004 ( .A0(n1283), .A1(n1484), .B0(n1462), .B1(n1287), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[6]) );
AOI22X1TS U2005 ( .A0(n1283), .A1(n1482), .B0(n1404), .B1(n1287), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[7]) );
AOI22X1TS U2006 ( .A0(n1283), .A1(n1499), .B0(n1457), .B1(n1292), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[8]) );
AOI22X1TS U2007 ( .A0(n1283), .A1(n1494), .B0(n1405), .B1(n1292), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[9]) );
AOI22X1TS U2008 ( .A0(n1284), .A1(n1487), .B0(n1458), .B1(n1287), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[10]) );
AOI22X1TS U2009 ( .A0(n1284), .A1(n1503), .B0(n1463), .B1(n1292), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[11]) );
AOI22X1TS U2010 ( .A0(n1284), .A1(n1496), .B0(n1464), .B1(n1287), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[12]) );
AOI22X1TS U2011 ( .A0(n1284), .A1(n1489), .B0(n1452), .B1(n1292), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[13]) );
AOI22X1TS U2012 ( .A0(n1284), .A1(n1419), .B0(n1465), .B1(n1287), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[14]) );
AOI22X1TS U2013 ( .A0(n1284), .A1(n1506), .B0(n1401), .B1(n1292), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[15]) );
AOI22X1TS U2014 ( .A0(n1284), .A1(n1485), .B0(n1475), .B1(n1292), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[16]) );
AOI22X1TS U2015 ( .A0(n1284), .A1(n1500), .B0(n1459), .B1(n1287), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[17]) );
AOI22X1TS U2016 ( .A0(n1284), .A1(n1501), .B0(n1406), .B1(n1292), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[18]) );
AOI22X1TS U2017 ( .A0(n1284), .A1(n1418), .B0(n1466), .B1(n1287), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[19]) );
AOI22X1TS U2018 ( .A0(n1288), .A1(n1492), .B0(n1407), .B1(n1292), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[20]) );
AOI22X1TS U2019 ( .A0(n1288), .A1(n1490), .B0(n1402), .B1(n1287), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[21]) );
AOI22X1TS U2020 ( .A0(n1288), .A1(n1493), .B0(n1408), .B1(n1291), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[22]) );
AOI22X1TS U2021 ( .A0(n1288), .A1(n1416), .B0(n1468), .B1(n1291), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[23]) );
AOI22X1TS U2022 ( .A0(n1288), .A1(n1488), .B0(n1412), .B1(n1287), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[24]) );
AOI22X1TS U2023 ( .A0(n1288), .A1(n1502), .B0(n1460), .B1(n1291), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[25]) );
AOI22X1TS U2024 ( .A0(n1288), .A1(n1507), .B0(n1467), .B1(n1291), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[26]) );
AOI22X1TS U2025 ( .A0(n1288), .A1(n1495), .B0(n1409), .B1(n1292), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[27]) );
AOI22X1TS U2026 ( .A0(n1288), .A1(n1410), .B0(n1508), .B1(n1291), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[0]) );
AOI22X1TS U2027 ( .A0(n1288), .A1(n1456), .B0(n1504), .B1(n1291), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[1]) );
BUFX3TS U2028 ( .A(n1284), .Y(n1285) );
AOI22X1TS U2029 ( .A0(n1285), .A1(n1411), .B0(n1491), .B1(n1292), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[2]) );
AOI22X1TS U2030 ( .A0(n1285), .A1(n1400), .B0(n1505), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[3]) );
AOI22X1TS U2031 ( .A0(n1285), .A1(n1461), .B0(n1486), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[4]) );
AOI22X1TS U2032 ( .A0(n1285), .A1(n1403), .B0(n1483), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[5]) );
AOI22X1TS U2033 ( .A0(n1285), .A1(n1462), .B0(n1484), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[6]) );
AOI22X1TS U2034 ( .A0(n1285), .A1(n1404), .B0(n1482), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[7]) );
AOI22X1TS U2035 ( .A0(n1285), .A1(n1457), .B0(n1499), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[8]) );
AOI22X1TS U2036 ( .A0(n1285), .A1(n1405), .B0(n1494), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[9]) );
AOI22X1TS U2037 ( .A0(n1285), .A1(n1458), .B0(n1487), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[10]) );
AOI22X1TS U2038 ( .A0(n1285), .A1(n1463), .B0(n1503), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[11]) );
AOI22X1TS U2039 ( .A0(n1290), .A1(n1464), .B0(n1496), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[12]) );
AOI22X1TS U2040 ( .A0(n1290), .A1(n1452), .B0(n1489), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[13]) );
AOI22X1TS U2041 ( .A0(n1290), .A1(n1465), .B0(n1419), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[14]) );
INVX2TS U2042 ( .A(n1288), .Y(n1289) );
AOI22X1TS U2043 ( .A0(n1290), .A1(n1401), .B0(n1506), .B1(n1289), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[15]) );
AOI22X1TS U2044 ( .A0(n1290), .A1(n1475), .B0(n1485), .B1(n1289), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[16]) );
AOI22X1TS U2045 ( .A0(n1290), .A1(n1459), .B0(n1500), .B1(n1291), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[17]) );
AOI22X1TS U2046 ( .A0(n1290), .A1(n1406), .B0(n1501), .B1(n1289), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[18]) );
AOI22X1TS U2047 ( .A0(n1290), .A1(n1466), .B0(n1418), .B1(n1289), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[19]) );
AOI22X1TS U2048 ( .A0(n1290), .A1(n1407), .B0(n1492), .B1(n1289), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[20]) );
AOI22X1TS U2049 ( .A0(n1290), .A1(n1402), .B0(n1490), .B1(n1289), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[21]) );
AOI22X1TS U2050 ( .A0(n1290), .A1(n1408), .B0(n1493), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[22]) );
AOI22X1TS U2051 ( .A0(n1288), .A1(n1468), .B0(n1416), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[23]) );
AOI22X1TS U2052 ( .A0(n1290), .A1(n1412), .B0(n1488), .B1(n1289), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[24]) );
AOI22X1TS U2053 ( .A0(n1290), .A1(n1460), .B0(n1502), .B1(n1289), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[25]) );
AOI22X1TS U2054 ( .A0(n1290), .A1(n1467), .B0(n1507), .B1(n1289), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[26]) );
AOI22X1TS U2055 ( .A0(n1290), .A1(n1409), .B0(n1495), .B1(n1286), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[27]) );
OAI2BB2XLTS U2056 ( .B0(n1291), .B1(n1182), .A0N(n1291), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[28]) );
OAI2BB2XLTS U2057 ( .B0(n1291), .B1(n1471), .A0N(n1291), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[29]) );
OAI2BB2XLTS U2058 ( .B0(n1291), .B1(n1472), .A0N(n1291), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[30]) );
NAND2X1TS U2059 ( .A(n1294), .B(n1293), .Y(enab_d_ff5_data_out) );
INVX4TS U2060 ( .A(n1301), .Y(n1302) );
NOR2BX1TS U2061 ( .AN(d_ff_Yn[0]), .B(n1302), .Y(first_mux_Y[0]) );
NOR2BX1TS U2062 ( .AN(d_ff_Yn[1]), .B(n1302), .Y(first_mux_Y[1]) );
INVX4TS U2063 ( .A(n1301), .Y(n1314) );
NOR2BX1TS U2064 ( .AN(d_ff_Yn[2]), .B(n1314), .Y(first_mux_Y[2]) );
INVX4TS U2065 ( .A(n1301), .Y(n1304) );
NOR2BX1TS U2066 ( .AN(d_ff_Yn[3]), .B(n1304), .Y(first_mux_Y[3]) );
NOR2BX1TS U2067 ( .AN(d_ff_Yn[4]), .B(n1314), .Y(first_mux_Y[4]) );
NOR2BX1TS U2068 ( .AN(d_ff_Yn[5]), .B(n1304), .Y(first_mux_Y[5]) );
INVX4TS U2069 ( .A(n1301), .Y(n1313) );
NOR2BX1TS U2070 ( .AN(d_ff_Yn[6]), .B(n1313), .Y(first_mux_Y[6]) );
NOR2BX1TS U2071 ( .AN(d_ff_Yn[7]), .B(n1313), .Y(first_mux_Y[7]) );
NOR2BX1TS U2072 ( .AN(d_ff_Yn[8]), .B(n1313), .Y(first_mux_Y[8]) );
INVX4TS U2073 ( .A(n1301), .Y(n1299) );
NOR2BX1TS U2074 ( .AN(d_ff_Yn[9]), .B(n1299), .Y(first_mux_Y[9]) );
NOR2BX1TS U2075 ( .AN(d_ff_Yn[10]), .B(n1299), .Y(first_mux_Y[10]) );
NOR2BX1TS U2076 ( .AN(d_ff_Yn[11]), .B(n1299), .Y(first_mux_Y[11]) );
NOR2BX1TS U2077 ( .AN(d_ff_Yn[12]), .B(n1299), .Y(first_mux_Y[12]) );
NOR2BX1TS U2078 ( .AN(d_ff_Yn[13]), .B(n1299), .Y(first_mux_Y[13]) );
NOR2BX1TS U2079 ( .AN(d_ff_Yn[14]), .B(n1299), .Y(first_mux_Y[14]) );
NOR2BX1TS U2080 ( .AN(d_ff_Yn[15]), .B(n1299), .Y(first_mux_Y[15]) );
NOR2BX1TS U2081 ( .AN(d_ff_Yn[16]), .B(n1299), .Y(first_mux_Y[16]) );
NOR2BX1TS U2082 ( .AN(d_ff_Yn[17]), .B(n1299), .Y(first_mux_Y[17]) );
NOR2BX1TS U2083 ( .AN(d_ff_Yn[18]), .B(n1299), .Y(first_mux_Y[18]) );
NOR2BX1TS U2084 ( .AN(d_ff_Yn[19]), .B(n1299), .Y(first_mux_Y[19]) );
NOR2BX1TS U2085 ( .AN(d_ff_Yn[20]), .B(n1299), .Y(first_mux_Y[20]) );
NOR2BX1TS U2086 ( .AN(d_ff_Yn[21]), .B(n1299), .Y(first_mux_Y[21]) );
NOR2BX1TS U2087 ( .AN(d_ff_Yn[22]), .B(n1299), .Y(first_mux_Y[22]) );
NOR2BX1TS U2088 ( .AN(d_ff_Yn[23]), .B(n1299), .Y(first_mux_Y[23]) );
NOR2BX1TS U2089 ( .AN(d_ff_Yn[24]), .B(n1313), .Y(first_mux_Y[24]) );
NOR2BX1TS U2090 ( .AN(d_ff_Yn[25]), .B(n1313), .Y(first_mux_Y[25]) );
NOR2BX1TS U2091 ( .AN(d_ff_Yn[26]), .B(n1313), .Y(first_mux_Y[26]) );
NOR2BX1TS U2092 ( .AN(d_ff_Yn[27]), .B(n1313), .Y(first_mux_Y[27]) );
NOR2BX1TS U2093 ( .AN(d_ff_Yn[28]), .B(n1313), .Y(first_mux_Y[28]) );
NOR2BX1TS U2094 ( .AN(d_ff_Yn[29]), .B(n1313), .Y(first_mux_Y[29]) );
NOR2BX1TS U2095 ( .AN(d_ff_Yn[30]), .B(n1313), .Y(first_mux_Y[30]) );
NOR2BX1TS U2096 ( .AN(d_ff_Yn[31]), .B(n1313), .Y(first_mux_Y[31]) );
AO22XLTS U2097 ( .A0(n1314), .A1(d_ff1_Z[0]), .B0(n1301), .B1(d_ff_Zn[0]),
.Y(first_mux_Z[0]) );
BUFX3TS U2098 ( .A(n1301), .Y(n1305) );
AO22XLTS U2099 ( .A0(n1304), .A1(d_ff1_Z[15]), .B0(n1305), .B1(d_ff_Zn[15]),
.Y(first_mux_Z[15]) );
AO22XLTS U2100 ( .A0(n1304), .A1(d_ff1_Z[16]), .B0(n1305), .B1(d_ff_Zn[16]),
.Y(first_mux_Z[16]) );
AO22XLTS U2101 ( .A0(n1304), .A1(d_ff1_Z[17]), .B0(n1303), .B1(d_ff_Zn[17]),
.Y(first_mux_Z[17]) );
AO22XLTS U2102 ( .A0(n1304), .A1(d_ff1_Z[18]), .B0(n1303), .B1(d_ff_Zn[18]),
.Y(first_mux_Z[18]) );
AO22XLTS U2103 ( .A0(n1304), .A1(d_ff1_Z[19]), .B0(n1303), .B1(d_ff_Zn[19]),
.Y(first_mux_Z[19]) );
AO22XLTS U2104 ( .A0(n1304), .A1(d_ff1_Z[20]), .B0(n1303), .B1(d_ff_Zn[20]),
.Y(first_mux_Z[20]) );
AO22XLTS U2105 ( .A0(n1304), .A1(d_ff1_Z[21]), .B0(n1303), .B1(d_ff_Zn[21]),
.Y(first_mux_Z[21]) );
AO22XLTS U2106 ( .A0(n1304), .A1(d_ff1_Z[22]), .B0(n1303), .B1(d_ff_Zn[22]),
.Y(first_mux_Z[22]) );
AO22XLTS U2107 ( .A0(n1304), .A1(d_ff1_Z[23]), .B0(n1303), .B1(d_ff_Zn[23]),
.Y(first_mux_Z[23]) );
AO22XLTS U2108 ( .A0(n1304), .A1(d_ff1_Z[24]), .B0(n1303), .B1(d_ff_Zn[24]),
.Y(first_mux_Z[24]) );
AO22XLTS U2109 ( .A0(n1304), .A1(d_ff1_Z[25]), .B0(n1303), .B1(d_ff_Zn[25]),
.Y(first_mux_Z[25]) );
AO22XLTS U2110 ( .A0(n1304), .A1(d_ff1_Z[26]), .B0(n1303), .B1(d_ff_Zn[26]),
.Y(first_mux_Z[26]) );
AO22XLTS U2111 ( .A0(n1304), .A1(d_ff1_Z[27]), .B0(n1303), .B1(d_ff_Zn[27]),
.Y(first_mux_Z[27]) );
AO22XLTS U2112 ( .A0(n1314), .A1(d_ff1_Z[28]), .B0(n1301), .B1(d_ff_Zn[28]),
.Y(first_mux_Z[28]) );
AO22XLTS U2113 ( .A0(n1314), .A1(d_ff1_Z[29]), .B0(n1303), .B1(d_ff_Zn[29]),
.Y(first_mux_Z[29]) );
AO22XLTS U2114 ( .A0(n1314), .A1(d_ff1_Z[30]), .B0(n1303), .B1(d_ff_Zn[30]),
.Y(first_mux_Z[30]) );
AO22XLTS U2115 ( .A0(n1314), .A1(d_ff1_Z[31]), .B0(n1305), .B1(d_ff_Zn[31]),
.Y(first_mux_Z[31]) );
BUFX3TS U2116 ( .A(n1306), .Y(n1310) );
AO22XLTS U2117 ( .A0(n1307), .A1(d_ff_Yn[1]), .B0(n1306), .B1(d_ff_Xn[1]),
.Y(mux_sal[1]) );
AO22XLTS U2118 ( .A0(n1307), .A1(d_ff_Yn[2]), .B0(n1306), .B1(d_ff_Xn[2]),
.Y(mux_sal[2]) );
AO22XLTS U2119 ( .A0(n1307), .A1(d_ff_Yn[3]), .B0(n1306), .B1(d_ff_Xn[3]),
.Y(mux_sal[3]) );
AO22XLTS U2120 ( .A0(n1307), .A1(d_ff_Yn[4]), .B0(n1306), .B1(d_ff_Xn[4]),
.Y(mux_sal[4]) );
AO22XLTS U2121 ( .A0(n1307), .A1(d_ff_Yn[5]), .B0(n1306), .B1(d_ff_Xn[5]),
.Y(mux_sal[5]) );
AO22XLTS U2122 ( .A0(n1307), .A1(d_ff_Yn[6]), .B0(n1306), .B1(d_ff_Xn[6]),
.Y(mux_sal[6]) );
AO22XLTS U2123 ( .A0(n1307), .A1(d_ff_Yn[7]), .B0(n1306), .B1(d_ff_Xn[7]),
.Y(mux_sal[7]) );
AO22XLTS U2124 ( .A0(n1307), .A1(d_ff_Yn[8]), .B0(n1306), .B1(d_ff_Xn[8]),
.Y(mux_sal[8]) );
AO22XLTS U2125 ( .A0(n1307), .A1(d_ff_Yn[9]), .B0(n1306), .B1(d_ff_Xn[9]),
.Y(mux_sal[9]) );
AO22XLTS U2126 ( .A0(n1307), .A1(d_ff_Yn[10]), .B0(n1306), .B1(d_ff_Xn[10]),
.Y(mux_sal[10]) );
AO22XLTS U2127 ( .A0(n1307), .A1(d_ff_Yn[11]), .B0(n1308), .B1(d_ff_Xn[11]),
.Y(mux_sal[11]) );
AO22XLTS U2128 ( .A0(n1307), .A1(d_ff_Yn[12]), .B0(n1308), .B1(d_ff_Xn[12]),
.Y(mux_sal[12]) );
INVX2TS U2129 ( .A(n1308), .Y(n1309) );
AO22XLTS U2130 ( .A0(n685), .A1(d_ff_Yn[13]), .B0(n1308), .B1(d_ff_Xn[13]),
.Y(mux_sal[13]) );
AO22XLTS U2131 ( .A0(n685), .A1(d_ff_Yn[14]), .B0(n1308), .B1(d_ff_Xn[14]),
.Y(mux_sal[14]) );
AO22XLTS U2132 ( .A0(n685), .A1(d_ff_Yn[15]), .B0(n1308), .B1(d_ff_Xn[15]),
.Y(mux_sal[15]) );
AO22XLTS U2133 ( .A0(n685), .A1(d_ff_Yn[16]), .B0(n1308), .B1(d_ff_Xn[16]),
.Y(mux_sal[16]) );
AO22XLTS U2134 ( .A0(n685), .A1(d_ff_Yn[17]), .B0(n1308), .B1(d_ff_Xn[17]),
.Y(mux_sal[17]) );
AO22XLTS U2135 ( .A0(n685), .A1(d_ff_Yn[18]), .B0(n1306), .B1(d_ff_Xn[18]),
.Y(mux_sal[18]) );
NOR2BX1TS U2136 ( .AN(d_ff_Xn[0]), .B(n1314), .Y(first_mux_X[0]) );
NOR2BX1TS U2137 ( .AN(d_ff_Xn[4]), .B(n1314), .Y(first_mux_X[4]) );
NOR2BX1TS U2138 ( .AN(d_ff_Xn[8]), .B(n1314), .Y(first_mux_X[8]) );
NOR2BX1TS U2139 ( .AN(d_ff_Xn[9]), .B(n1314), .Y(first_mux_X[9]) );
NOR2BX1TS U2140 ( .AN(d_ff_Xn[11]), .B(n1314), .Y(first_mux_X[11]) );
NOR2BX1TS U2141 ( .AN(d_ff_Xn[15]), .B(n1314), .Y(first_mux_X[15]) );
NOR2BX1TS U2142 ( .AN(d_ff_Xn[18]), .B(n1314), .Y(first_mux_X[18]) );
NOR2BX1TS U2143 ( .AN(d_ff_Xn[21]), .B(n1313), .Y(first_mux_X[21]) );
NOR2BX1TS U2144 ( .AN(d_ff_Xn[22]), .B(n1313), .Y(first_mux_X[22]) );
NOR2BX1TS U2145 ( .AN(d_ff_Xn[23]), .B(n1313), .Y(first_mux_X[23]) );
NOR2BX1TS U2146 ( .AN(d_ff_Xn[30]), .B(n1313), .Y(first_mux_X[30]) );
NOR2BX1TS U2147 ( .AN(d_ff_Xn[31]), .B(n1314), .Y(first_mux_X[31]) );
NOR2BX1TS U2148 ( .AN(beg_fsm_cordic), .B(n1315), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U2149 ( .A0(enab_d_ff4_Zn), .A1(n1320), .B0(n1319), .B1(n1318),
.Y(inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U2150 ( .AN(enab_d_ff4_Zn), .B(n1320), .Y(
inst_CORDIC_FSM_v3_state_next[6]) );
OA21XLTS U2152 ( .A0(cont_iter_out[2]), .A1(n1322), .B0(n1321), .Y(
ITER_CONT_N4) );
AOI22X1TS U2153 ( .A0(n1340), .A1(d_ff3_sh_y_out[28]), .B0(n1323), .B1(
d_ff3_sh_x_out[28]), .Y(n1324) );
NAND2X1TS U2154 ( .A(n1324), .B(n1325), .Y(n621) );
AOI22X1TS U2155 ( .A0(n1340), .A1(d_ff3_sh_y_out[27]), .B0(n1332), .B1(
d_ff3_sh_x_out[27]), .Y(n1326) );
NAND2X1TS U2156 ( .A(n1326), .B(n1325), .Y(n620) );
AOI22X1TS U2157 ( .A0(n1340), .A1(d_ff3_sh_y_out[22]), .B0(n1339), .B1(
d_ff3_sh_x_out[22]), .Y(n1327) );
OAI2BB1X1TS U2158 ( .A0N(n1347), .A1N(d_ff3_LUT_out[19]), .B0(n1327), .Y(
n615) );
AOI22X1TS U2159 ( .A0(n1340), .A1(d_ff3_sh_y_out[19]), .B0(n1339), .B1(
d_ff3_sh_x_out[19]), .Y(n1328) );
OAI2BB1X1TS U2160 ( .A0N(n1336), .A1N(d_ff3_LUT_out[19]), .B0(n1328), .Y(
n612) );
AOI22X1TS U2161 ( .A0(n1340), .A1(d_ff3_sh_y_out[18]), .B0(n1339), .B1(
d_ff3_sh_x_out[18]), .Y(n1329) );
OAI2BB1X1TS U2162 ( .A0N(n1342), .A1N(d_ff3_LUT_out[13]), .B0(n1329), .Y(
n611) );
AOI22X1TS U2163 ( .A0(n1340), .A1(d_ff3_sh_y_out[16]), .B0(n1339), .B1(
d_ff3_sh_x_out[16]), .Y(n1330) );
OAI2BB1X1TS U2164 ( .A0N(n950), .A1N(d_ff3_LUT_out[3]), .B0(n1330), .Y(n609)
);
AOI22X1TS U2165 ( .A0(n1340), .A1(d_ff3_sh_y_out[15]), .B0(n1332), .B1(
d_ff3_sh_x_out[15]), .Y(n1334) );
NAND2X1TS U2166 ( .A(n1334), .B(n1333), .Y(n608) );
AOI22X1TS U2167 ( .A0(n1340), .A1(d_ff3_sh_y_out[14]), .B0(n1339), .B1(
d_ff3_sh_x_out[14]), .Y(n1335) );
OAI2BB1X1TS U2168 ( .A0N(n1336), .A1N(d_ff3_LUT_out[5]), .B0(n1335), .Y(n607) );
AOI22X1TS U2169 ( .A0(n1340), .A1(d_ff3_sh_y_out[11]), .B0(n1337), .B1(
d_ff3_sh_x_out[11]), .Y(n1338) );
OAI2BB1X1TS U2170 ( .A0N(n1347), .A1N(d_ff3_LUT_out[7]), .B0(n1338), .Y(n604) );
AOI22X1TS U2171 ( .A0(n1340), .A1(d_ff3_sh_y_out[7]), .B0(n1339), .B1(
d_ff3_sh_x_out[7]), .Y(n1341) );
OAI2BB1X1TS U2172 ( .A0N(n1342), .A1N(d_ff3_LUT_out[7]), .B0(n1341), .Y(n600) );
AOI22X1TS U2173 ( .A0(n1345), .A1(d_ff3_sh_y_out[5]), .B0(n1344), .B1(
d_ff3_sh_x_out[5]), .Y(n1343) );
OAI2BB1X1TS U2174 ( .A0N(n1347), .A1N(d_ff3_LUT_out[5]), .B0(n1343), .Y(n598) );
AOI22X1TS U2175 ( .A0(n1345), .A1(d_ff3_sh_y_out[3]), .B0(n1323), .B1(
d_ff3_sh_x_out[3]), .Y(n1346) );
OAI2BB1X1TS U2176 ( .A0N(n1347), .A1N(d_ff3_LUT_out[3]), .B0(n1346), .Y(n596) );
AOI22X1TS U2177 ( .A0(cont_iter_out[1]), .A1(n1350), .B0(n1348), .B1(n1438),
.Y(n555) );
AOI22X1TS U2178 ( .A0(cont_iter_out[1]), .A1(n1350), .B0(n1349), .B1(n1438),
.Y(n547) );
OAI2BB1X1TS U2179 ( .A0N(cont_iter_out[1]), .A1N(n545), .B0(n1351), .Y(n546)
);
AOI22X1TS U2180 ( .A0(cont_iter_out[1]), .A1(n1353), .B0(n1352), .B1(n1438),
.Y(n542) );
OAI22X1TS U2181 ( .A0(n1357), .A1(n1356), .B0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B1(
n1355), .Y(n541) );
AOI22X1TS U2182 ( .A0(cont_var_out[0]), .A1(n1359), .B0(n1358), .B1(n1448),
.Y(n540) );
NAND2BXLTS U2183 ( .AN(busy), .B(n1592), .Y(
inst_FPU_PIPELINED_FPADDSUB__6_net_) );
NOR2XLTS U2185 ( .A(d_ff2_Y[29]), .B(n1361), .Y(n1360) );
XNOR2X1TS U2186 ( .A(d_ff2_Y[29]), .B(n1361), .Y(sh_exp_y[6]) );
AO21XLTS U2187 ( .A0(intadd_403_n1), .A1(d_ff2_Y[27]), .B0(n1362), .Y(
sh_exp_y[4]) );
NOR2XLTS U2188 ( .A(d_ff2_X[29]), .B(n1364), .Y(n1363) );
XNOR2X1TS U2189 ( .A(d_ff2_X[29]), .B(n1364), .Y(sh_exp_x[6]) );
AO21XLTS U2190 ( .A0(intadd_402_n1), .A1(d_ff2_X[27]), .B0(n1365), .Y(
sh_exp_x[4]) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
|
module jt10_test(
input rst, // rst should be at least 6 clk&cen cycles long
input clk, // CPU clock
input cen, // optional clock enable, if not needed leave as 1'b1
input [7:0] din,
input [1:0] addr,
input cs_n,
input wr_n,
output [7:0] dout,
output irq_n,
// ADPCM pins
output [19:0] adpcma_addr, // real hardware has 10 pins multiplexed through RMPX pin
output [3:0] adpcma_bank,
output adpcma_roe_n, // ADPCM-A ROM output enable
input [7:0] adpcma_data, // Data from RAM
output [23:0] adpcmb_addr, // real hardware has 12 pins multiplexed through PMPX pin
output adpcmb_roe_n, // ADPCM-B ROM output enable
// combined output
output signed [15:0] snd_right,
output signed [15:0] snd_left,
output snd_sample
);
wire [7:0] psg_A;
wire [7:0] psg_B;
wire [7:0] psg_C;
wire signed [15:0] fm_snd;
wire [9:0] psg_snd;
jt10 uut (
.rst (rst ),
.clk (clk ),
.cen (cen ),
.din (din ),
.addr (addr ),
.cs_n (cs_n ),
.wr_n (wr_n ),
.dout (dout ),
.irq_n (irq_n ),
.adpcma_addr (adpcma_addr ),
.adpcma_bank (adpcma_bank ),
.adpcma_roe_n(adpcma_roe_n),
.adpcma_data (adpcma_data ),
.adpcmb_addr (adpcmb_addr ),
.adpcmb_roe_n(adpcmb_roe_n),
.psg_A (psg_A ),
.psg_B (psg_B ),
.psg_C (psg_C ),
.fm_snd (fm_snd ),
.psg_snd (psg_snd ),
.snd_right (snd_right ),
.snd_left (snd_left ),
.snd_sample (snd_sample )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0P_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__INPUTISO0P_PP_BLACKBOX_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso0p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0P_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__SDFRTN_PP_BLACKBOX_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTN_PP_BLACKBOX_V
|
module dc_video_reconfig(
input clock,
input [7:0] data_in,
output DCVideoConfig dcVideoConfig,
output forceVGAMode
);
`ifdef std
`include "config/std/dc_config.v"
`elsif hq2x
`include "config/hq2x/dc_config.v"
`endif
`include "config/dc_config.v"
reg [7:0] data_in_reg = 0;
reg forceVGAMode_reg;
DCVideoConfig dcVideoConfig_reg;
initial begin
dcVideoConfig_reg <= DC_VIDEO_CONFIG_1080P;
end
assign dcVideoConfig = dcVideoConfig_reg;
assign forceVGAMode = forceVGAMode_reg;
always @(posedge clock) begin
data_in_reg <= data_in;
if (data_in_reg != data_in) begin
forceVGAMode_reg <= data_in[7];
case (data_in[6:0])
// RECONF
7'h00: dcVideoConfig_reg <= DC_VIDEO_CONFIG_1080P;
7'h01: dcVideoConfig_reg <= DC_VIDEO_CONFIG_960P;
7'h02: dcVideoConfig_reg <= DC_VIDEO_CONFIG_480P;
7'h03: dcVideoConfig_reg <= DC_VIDEO_CONFIG_VGA;
7'h04: dcVideoConfig_reg <= DC_VIDEO_CONFIG_288P;
7'h05: dcVideoConfig_reg <= DC_VIDEO_CONFIG_288P;
7'h06: dcVideoConfig_reg <= DC_VIDEO_CONFIG_288P;
7'h07: dcVideoConfig_reg <= DC_VIDEO_CONFIG_288P;
7'h08: dcVideoConfig_reg <= DC_VIDEO_CONFIG_576P;
7'h09: dcVideoConfig_reg <= DC_VIDEO_CONFIG_576P;
7'h0A: dcVideoConfig_reg <= DC_VIDEO_CONFIG_576P;
7'h0B: dcVideoConfig_reg <= DC_VIDEO_CONFIG_576P;
7'h10: dcVideoConfig_reg <= DC_VIDEO_CONFIG_240P_1080P;
7'h11: dcVideoConfig_reg <= DC_VIDEO_CONFIG_240P_960P;
7'h12: dcVideoConfig_reg <= DC_VIDEO_CONFIG_240P_480P;
7'h13: dcVideoConfig_reg <= DC_VIDEO_CONFIG_240P_VGA;
7'h20: dcVideoConfig_reg <= DC_VIDEO_CONFIG_480I;
7'h21: dcVideoConfig_reg <= DC_VIDEO_CONFIG_480I;
7'h22: dcVideoConfig_reg <= DC_VIDEO_CONFIG_480I;
7'h23: dcVideoConfig_reg <= DC_VIDEO_CONFIG_480I;
7'h40: dcVideoConfig_reg <= DC_VIDEO_CONFIG_576I;
7'h41: dcVideoConfig_reg <= DC_VIDEO_CONFIG_576I;
7'h42: dcVideoConfig_reg <= DC_VIDEO_CONFIG_576I;
7'h43: dcVideoConfig_reg <= DC_VIDEO_CONFIG_576I;
endcase
end
end
endmodule
|
module EX_MEM (
input clk,
input rst,
input is_hold,
input[`RegAddrWidth-1:0] target_EX,
input[`RegDataWidth-1:0] data_out_EX,
input we_hi_EX,
input we_lo_EX,
input[`RegDataWidth-1:0] hi_EX,
input[`RegDataWidth-1:0] lo_EX,
input[`RegAddrWidth-1:0] raddr_2_EX,
input[`RegDataWidth-1:0] rdata_2_EX,
input WriteReg_EX,
input MemOrAlu_EX,
input WriteMem_EX,
input ReadMem_EX,
input[`OpcodeWidth-1:0] opcode_EX,
output[`RegAddrWidth-1:0] target_MEM,
output[`RegDataWidth-1:0] data_from_ALU_MEM,
output we_hi_MEM,
output we_lo_MEM,
output[`RegDataWidth-1:0] hi_MEM,
output[`RegDataWidth-1:0] lo_MEM,
output[`RegDataWidth-1:0] rdata_2_MEM,
output[`RegAddrWidth-1:0] raddr_2_MEM,
output WriteReg_MEM,
output MemOrAlu_MEM,
output WriteMem_MEM,
output ReadMem_MEM,
output[`OpcodeWidth-1:0] opcode_MEM
);
dffe #(.data_width(`RegAddrWidth)) target_holder(clk, rst, is_hold, target_EX, target_MEM);
dffe #(.data_width(`RegDataWidth)) data_holder(clk, rst, is_hold, data_out_EX, data_from_ALU_MEM);
dffe we_hi_holder(clk, rst, is_hold, we_hi_EX, we_hi_MEM);
dffe we_lo_holder(clk, rst, is_hold, we_lo_EX, we_lo_MEM);
dffe #(.data_width(`RegDataWidth)) hi_holder(clk, rst, is_hold, hi_EX, hi_MEM);
dffe #(.data_width(`RegDataWidth)) lo_holder(clk, rst, is_hold, lo_EX, lo_MEM);
dffe #(.data_width(`RegAddrWidth)) raddr_2_holder(clk, rst, is_hold, raddr_2_EX, raddr_2_MEM);
dffe #(.data_width(`RegDataWidth)) rdata_2_holder(clk, rst, is_hold, rdata_2_EX, rdata_2_MEM);
dffe WriteReg_holder(clk, rst, is_hold, WriteReg_EX, WriteReg_MEM);
dffe MemOrAlu_holder(clk, rst, is_hold, MemOrAlu_EX, MemOrAlu_MEM);
dffe WriteMem_holder(clk, rst, is_hold, WriteMem_EX, WriteMem_MEM);
dffe ReadMem_holder(clk, rst, is_hold, ReadMem_EX, ReadMem_MEM);
dffe #(.data_width(`OpcodeWidth)) opcode_holder(clk, rst, is_hold, opcode_EX, opcode_MEM);
endmodule
|
`default_nettype none
`include "setup.v"
module measure_mid (
// System
input pcie_clk,
input sys_rst,
// Management
input [6:0] rx_bar_hit,
input [7:0] bus_num,
input [4:0] dev_num,
input [2:0] func_num,
// Receive
input rx_st,
input rx_end,
input [15:0] rx_data,
input rx_malf,
// Transmit
output tx_req,
input tx_rdy,
output tx_st,
output tx_end,
output [15:0] tx_data,
input [8:0] tx_ca_ph,
input [12:0] tx_ca_pd,
input [8:0] tx_ca_nph,
input [12:0] tx_ca_npd,
input [8:0] tx_ca_cplh,
input [12:0] tx_ca_cpld,
input tx_ca_p_recheck,
input tx_ca_cpl_recheck,
// Receive credits
output [7:0] pd_num,
output ph_cr,
output pd_cr,
output nph_cr,
output npd_cr,
// Ethernet PHY#1
input phy1_125M_clk,
output phy1_tx_en,
output [7:0] phy1_tx_data,
input phy1_rx_clk,
input phy1_rx_dv,
input phy1_rx_er,
input [7:0] phy1_rx_data,
// Ethernet PHY#2
input phy2_125M_clk,
output phy2_tx_en,
output [7:0] phy2_tx_data,
input phy2_rx_clk,
input phy2_rx_dv,
input phy2_rx_er,
input [7:0] phy2_rx_data,
// LED and Switches
input [7:0] dipsw,
output [7:0] led,
output [13:0] segled,
input btn
);
// Slave bus
wire [6:0] slv_bar_i;
wire slv_ce_i;
wire slv_we_i;
wire [19:1] slv_adr_i;
wire [15:0] slv_dat_i;
wire [1:0] slv_sel_i;
wire [15:0] slv_dat_o, slv_dat1_o, slv_dat2_o;
reg [15:0] slv_dat0_o;
pcie_tlp inst_pcie_tlp (
// System
.pcie_clk(pcie_clk),
.sys_rst(sys_rst),
// Management
.rx_bar_hit(rx_bar_hit),
.bus_num(bus_num),
.dev_num(dev_num),
.func_num(func_num),
// Receive
.rx_st(rx_st),
.rx_end(rx_end),
.rx_data(rx_data),
.rx_malf(rx_malf),
// Transmit
.tx_req(tx_req),
.tx_rdy(tx_rdy),
.tx_st(tx_st),
.tx_end(tx_end),
.tx_data(tx_data),
.tx_ca_ph(tx_ca_ph),
.tx_ca_pd(tx_ca_pd),
.tx_ca_nph(tx_ca_nph),
.tx_ca_npd(tx_ca_npd),
.tx_ca_cplh(tx_ca_cplh),
.tx_ca_cpld(tx_ca_cpld),
.tx_ca_p_recheck(tx_ca_p_recheck),
.tx_ca_cpl_recheck(tx_ca_cpl_recheck),
//Receive credits
.pd_num(pd_num),
.ph_cr(ph_cr),
.pd_cr(pd_cr),
.nph_cr(nph_cr),
.npd_cr(npd_cr),
// Master FIFO
.mst_rd_en(),
.mst_empty(),
.mst_dout(),
.mst_wr_en(),
.mst_full(),
.mst_din(),
// Slave BUS
.slv_bar_i(slv_bar_i),
.slv_ce_i(slv_ce_i),
.slv_we_i(slv_we_i),
.slv_adr_i(slv_adr_i),
.slv_dat_i(slv_dat_i),
.slv_sel_i(slv_sel_i),
.slv_dat_o(slv_dat_o),
// Slave FIFO
.slv_rd_en(),
.slv_empty(),
.slv_dout(),
.slv_wr_en(),
.slv_full(),
.slv_din(),
// LED and Switches
.dipsw(dipsw),
.led(),
.segled(),
.btn(btn)
);
//-----------------------------------
// PCI user registers
//-----------------------------------
reg tx0_enable;
reg tx0_ipv6;
reg tx0_fullroute;
reg tx0_req_arp;
reg [15:0] tx0_frame_len;
reg [31:0] tx0_inter_frame_gap;
reg [31:0] tx0_ipv4_srcip;
reg [47:0] tx0_src_mac;
reg [31:0] tx0_ipv4_gwip;
reg [127:0] tx0_ipv6_srcip;
reg [127:0] tx0_ipv6_dstip;
wire [47:0] tx0_dst_mac;
reg [31:0] tx0_ipv4_dstip;
wire [31:0] tx0_pps;
wire [31:0] tx0_throughput;
wire [31:0] tx0_ipv4_ip;
wire [31:0] rx1_pps;
wire [31:0] rx1_throughput;
wire [23:0] rx1_latency;
wire [31:0] rx1_ipv4_ip;
wire [31:0] global_counter;
wire [31:0] count_2976_latency;
reg [13:0] segledr;
always @(posedge pcie_clk) begin
if (sys_rst == 1'b1) begin
slv_dat0_o <= 16'h0;
// PCI User Registers
tx0_enable <= 1'b1;
tx0_ipv6 <= 1'b0;
tx0_fullroute <= 1'b0;
tx0_req_arp <= 1'b0;
case (dipsw[7:5])
3'h0: tx0_frame_len <= 16'd64;
3'h1: tx0_frame_len <= 16'd128;
3'h2: tx0_frame_len <= 16'd256;
3'h3: tx0_frame_len <= 16'd512;
3'h4: tx0_frame_len <= 16'd768;
3'h5: tx0_frame_len <= 16'd1024;
3'h6: tx0_frame_len <= 16'd1280;
3'h7: tx0_frame_len <= 16'd1518;
endcase
tx0_inter_frame_gap <= 32'd11 + (32'h1 << dipsw[4:0]);
tx0_src_mac <= 48'h003776_000100;
tx0_ipv4_gwip <= {8'd10,8'd0,8'd20,8'd1};
tx0_ipv4_srcip <= {8'd10,8'd0,8'd20,8'd105};
tx0_ipv4_dstip <= {8'd10,8'd0,8'd21,8'd105};
tx0_ipv6_srcip <= 128'h3776_0000_0000_0020_0000_0000_0000_0105;
tx0_ipv6_dstip <= 128'h3776_0000_0000_0021_0000_0000_0000_0105;
end else begin
if (slv_bar_i[0] & slv_ce_i) begin
case (slv_adr_i[7:1])
7'h00: begin // tx enable bit
if (slv_we_i) begin
if (slv_sel_i[1])
{tx0_enable, tx0_ipv6, tx0_fullroute} <= {slv_dat_i[15:14], slv_dat_i[8]};
end else
slv_dat0_o <= {tx0_enable, tx0_ipv6, 5'b0, tx0_fullroute, 8'h00};
end
7'h03: begin // tx0 frame length
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_frame_len[ 7:0] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_frame_len[15:8] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_frame_len[15:8];
end
7'h04: begin // tx0 inter frame gap
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_inter_frame_gap[23:16] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_inter_frame_gap[31:24] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_inter_frame_gap[31:16];
end
7'h05: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_inter_frame_gap[ 7:0] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_inter_frame_gap[15:8] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_inter_frame_gap[15:0];
end
7'h08: begin // tx0 ipv4_srcip
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv4_srcip[23:16] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv4_srcip[31:24] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv4_srcip[31:16];
end
7'h09: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv4_srcip[ 7:0] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv4_srcip[15:8] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv4_srcip[15: 0];
end
7'h0b: begin // tx0 src_mac 47-32bit
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_src_mac[39:32] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_src_mac[47:40] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_src_mac[47:32];
end
7'h0c: begin // tx0 src_mac 31-16bit
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_src_mac[23:16] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_src_mac[31:24] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_src_mac[31:16];
end
7'h0d: begin // tx0 src_mac 15- 0bit
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_src_mac[ 7: 0] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_src_mac[15: 8] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_src_mac[15: 0];
end
7'h10: begin // tx0 ipv4_gwip
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv4_gwip[23:16] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv4_gwip[31:24] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv4_gwip[31:16];
end
7'h11: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv4_gwip[ 7:0] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv4_gwip[15:8] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv4_gwip[15: 0];
end
7'h13: begin // tx0 dst_mac 47-32bit
slv_dat0_o <= tx0_dst_mac[47:32];
end
7'h14: begin // tx0 dst_mac 31-16bit
slv_dat0_o <= tx0_dst_mac[31:16];
end
7'h15: begin // tx0 dst_mac 15- 0bit
slv_dat0_o <= tx0_dst_mac[15: 0];
end
7'h16: begin // tx0 ipv4_dstip
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv4_dstip[23:16] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv4_dstip[31:24] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv4_dstip[31:16];
end
7'h17: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv4_dstip[ 7: 0] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv4_dstip[15: 8] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv4_dstip[15: 0];
end
7'h20: begin // tx0 pps
slv_dat0_o <= tx0_pps[31:16];
end
7'h21: begin
slv_dat0_o <= tx0_pps[15: 0];
end
7'h22: begin // tx0 throughput
slv_dat0_o <= tx0_throughput[31:16];
end
7'h23: begin
slv_dat0_o <= tx0_throughput[15: 0];
end
7'h26: begin // tx0 ipv4_ip
slv_dat0_o <= tx0_ipv4_ip[31:16];
end
7'h27: begin
slv_dat0_o <= tx0_ipv4_ip[15: 0];
end
7'h28: begin // rx1 pps
slv_dat0_o <= rx1_pps[31:16];
end
7'h29: begin
slv_dat0_o <= rx1_pps[15: 0];
end
7'h2a: begin // rx1 throughput
slv_dat0_o <= rx1_throughput[31:16];
end
7'h2b: begin
slv_dat0_o <= rx1_throughput[15: 0];
end
7'h2c: begin // rx1 latency
slv_dat0_o <= {8'h0, rx1_latency[23:16]};
end
7'h2d: begin
slv_dat0_o <= rx1_latency[15: 0];
end
7'h2e: begin // rx1 ipv4_ip
slv_dat0_o <= rx1_ipv4_ip[31:16];
end
7'h2f: begin
slv_dat0_o <= rx1_ipv4_ip[15: 0];
end
7'h40: begin // tx0_ipv6_srcip
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_srcip[119:112] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_srcip[127:120] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_srcip[127:112];
end
7'h41: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_srcip[103: 96] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_srcip[111:104] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_srcip[111: 96];
end
7'h42: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_srcip[ 87: 80] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_srcip[ 95: 88] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_srcip[ 95: 80];
end
7'h43: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_srcip[ 71: 64] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_srcip[ 79: 72] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_srcip[ 79: 64];
end
7'h44: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_srcip[ 55: 48] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_srcip[ 63: 56] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_srcip[ 63: 48];
end
7'h45: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_srcip[ 39: 32] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_srcip[ 47: 40] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_srcip[ 47: 32];
end
7'h46: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_srcip[ 23: 16] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_srcip[ 31: 24] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_srcip[ 31: 16];
end
7'h47: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_srcip[ 7: 0] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_srcip[ 15: 8] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_srcip[ 15: 0];
end
7'h48: begin // tx0_ipv6_dstip
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_dstip[119:112] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_dstip[127:120] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_dstip[127:112];
end
7'h49: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_dstip[103: 96] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_dstip[111:104] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_dstip[111: 96];
end
7'h4a: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_dstip[ 87: 80] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_dstip[ 95: 88] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_dstip[ 95: 80];
end
7'h4b: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_dstip[ 71: 64] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_dstip[ 79: 72] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_dstip[ 79: 64];
end
7'h4c: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_dstip[ 55: 48] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_dstip[ 63: 56] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_dstip[ 63: 48];
end
7'h4d: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_dstip[ 39: 32] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_dstip[ 47: 40] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_dstip[ 47: 32];
end
7'h4e: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_dstip[ 23: 16] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_dstip[ 31: 24] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_dstip[ 31: 16];
end
7'h4f: begin
if (slv_we_i) begin
if (slv_sel_i[0])
tx0_ipv6_dstip[ 7: 0] <= slv_dat_i[7:0];
if (slv_sel_i[1])
tx0_ipv6_dstip[ 15: 8] <= slv_dat_i[15:8];
end else
slv_dat0_o <= tx0_ipv6_dstip[ 15: 0];
end
7'h50: begin // global_counter
slv_dat0_o <= global_counter[ 31: 16];
end
7'h51: begin
slv_dat0_o <= global_counter[ 15: 0];
end
7'h52: begin // count_2976_latency
slv_dat0_o <= count_2976_latency[ 31: 16];
end
7'h53: begin
slv_dat0_o <= count_2976_latency[ 15: 0];
end
default: begin
slv_dat0_o <= 16'h00; // slv_adr_i[16:1];
end
endcase
end
end
end
wire [15:0] rom_dat_o;
// BIOS ROM
`ifdef ENABLE_EXPROM
biosrom biosrom_inst (
.Address(slv_adr_i[10:1]),
.OutClock(pcie_clk),
.OutClockEn(slv_ce_i & (slv_bar_i[6])),
.Reset(sys_rst),
.Q({rom_dat_o[7:0],rom_dat_o[15:8]})
);
`endif
measure measure_inst (
.sys_rst(sys_rst),
.sys_clk(pcie_clk),
.pci_clk(pcie_clk),
.gmii_0_tx_clk(phy1_125M_clk),
.gmii_0_txd(phy1_tx_data),
.gmii_0_tx_en(phy1_tx_en),
.gmii_0_rxd(phy1_rx_data),
.gmii_0_rx_dv(phy1_rx_dv),
.gmii_0_rx_clk(phy1_rx_clk),
.gmii_1_tx_clk(phy2_125M_clk),
.gmii_1_txd(phy2_tx_data),
.gmii_1_tx_en(phy2_tx_en),
.gmii_1_rxd(phy2_rx_data),
.gmii_1_rx_dv(phy2_rx_dv),
.gmii_1_rx_clk(phy2_rx_clk),
.tx0_enable(tx0_enable),
.tx0_ipv6(tx0_ipv6),
.tx0_fullroute(tx0_fullroute),
.tx0_req_arp(tx0_req_arp),
.tx0_frame_len(tx0_frame_len),
.tx0_inter_frame_gap(tx0_inter_frame_gap),
.tx0_ipv4_srcip(tx0_ipv4_srcip),
.tx0_src_mac(tx0_src_mac),
.tx0_ipv4_gwip(tx0_ipv4_gwip),
.tx0_ipv6_srcip(tx0_ipv6_srcip),
.tx0_ipv6_dstip(tx0_ipv6_dstip),
.tx0_dst_mac(tx0_dst_mac),
.tx0_ipv4_dstip(tx0_ipv4_dstip),
.tx0_pps(tx0_pps),
.tx0_throughput(tx0_throughput),
.tx0_ipv4_ip(tx0_ipv4_ip),
.rx1_pps(rx1_pps),
.rx1_throughput(rx1_throughput),
.rx1_latency(rx1_latency),
.rx1_ipv4_ip(rx1_ipv4_ip),
.global_counter(global_counter),
.count_2976_latency(count_2976_latency)
);
`ifdef ENABLE_EXPROM
assign slv_dat_o = ( {16{slv_bar_i[0]}} & slv_dat0_o ) | ( {16{slv_bar_i[2]}} & slv_dat1_o ) | ( {16{slv_bar_i[6]}} & rom_dat_o );
`else
assign slv_dat_o = ( {16{slv_bar_i[0]}} & slv_dat0_o ) | ( {16{slv_bar_i[2]}} & slv_dat1_o );
`endif
assign segled = segledr;
endmodule
`default_nettype wire
|
//--------------------------------------------------------------------------------
// meta.v
//
// Copyright (C) 2011 Ian Davis
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details:
// http://www.dangerousprototypes.com/ols
// http://www.gadgetfactory.net/gf/project/butterflylogic
// http://www.mygizmos.org/ols
//
// Inserts META data into spi_transmitter datapath upon command...
//
`timescale 1ns/100ps
module meta_handler(
clock, extReset,
query_metadata, xmit_idle,
// outputs...
writeMeta, meta_data);
input clock;
input extReset;
input query_metadata;
input xmit_idle;
output writeMeta;
output [7:0] meta_data;
reg [5:0] metasel, next_metasel;
reg writeMeta;
`define ADDBYTE(cmd) meta_rom[i]=cmd; i=i+1
`define ADDSHORT(cmd,b0) meta_rom[i]=cmd; meta_rom[i+1]=b0; i=i+2
`define ADDLONG(cmd,b0,b1,b2,b3) meta_rom[i]=cmd; meta_rom[i+1]=b0; meta_rom[i+2]=b1; meta_rom[i+3]=b2; meta_rom[i+4]=b3; i=i+5
// Create meta data ROM...
reg [5:0] METADATA_LEN;
reg [7:0] meta_rom[63:0];
wire [7:0] meta_data = meta_rom[metasel];
initial
begin : meta
integer i;
i=0;
`ADDLONG(8'h01, "O", "p", "e", "n"); // Device name string...
`ADDLONG(" ", "L", "o", "g", "i");
`ADDLONG("c", " ", "S", "n", "i");
`ADDLONG("f", "f", "e", "r", " ");
`ADDLONG("v", "1", ".", "0", "1");
`ADDBYTE(0);
`ADDLONG(8'h02, "3", ".", "0", "7"); // FPGA firmware version string
`ADDBYTE(0);
//`ADDLONG(8'h21,8'h00,8'h60,8'h00,8'h00); // Amount of sample memory (24K)
//`ADDLONG(8'h23,8'h00,8'hC2,8'hEB,8'h0B); // Max sample rate (200Mhz)
`ADDLONG(8'h21,8'h00,8'h00,8'h60,8'h00); // Amount of sample memory (24K)
`ADDLONG(8'h23,8'h0B,8'hEB,8'hC2,8'h00); // Max sample rate (200Mhz)
`ADDSHORT(8'h40,8'h20); // Max # of probes
`ADDSHORT(8'h41,8'h02); // Protocol version
`ADDBYTE(0); // End of data flag
METADATA_LEN = i;
for (i=i; i<64; i=i+1) meta_rom[i]=0; // Padding
end
//
// Control FSM for sending meta data...
//
parameter [1:0] IDLE = 0, METASEND = 1, METAPOLL = 2;
reg [1:0] state, next_state;
initial state = IDLE;
always @(posedge clock or posedge extReset)
begin
if (extReset)
begin
state = IDLE;
metasel = 3'h0;
end
else
begin
state = next_state;
metasel = next_metasel;
end
end
always @*
begin
#1;
next_state = state;
next_metasel = metasel;
writeMeta = 1'b0;
case (state)
IDLE :
begin
next_metasel = 0;
next_state = (query_metadata && xmit_idle) ? METASEND : IDLE;
end
METASEND : // output contents of META data rom - IED
begin
writeMeta = 1'b1;
next_metasel = metasel+1'b1;
next_state = METAPOLL;
end
METAPOLL :
begin
if (xmit_idle)
next_state = (metasel==METADATA_LEN) ? IDLE : METASEND;
end
default : next_state = IDLE;
endcase
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module sparse_mm_mul_31ns_32s_32_3_Mul3S_1(clk, ce, a, b, p);
input clk;
input ce;
input[31 - 1 : 0] a; // synthesis attribute keep a "true"
input[32 - 1 : 0] b; // synthesis attribute keep b "true"
output[32 - 1 : 0] p;
reg [31 - 1 : 0] a_reg0;
reg signed [32 - 1 : 0] b_reg0;
wire signed [32 - 1 : 0] tmp_product;
reg signed [32 - 1 : 0] buff0;
assign p = buff0;
assign tmp_product = $signed({1'b0, a_reg0}) * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module sparse_mm_mul_31ns_32s_32_3(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
sparse_mm_mul_31ns_32s_32_3_Mul3S_1 sparse_mm_mul_31ns_32s_32_3_Mul3S_1_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_clint(
input clock,
input reset,
output io_in_0_a_ready,
input io_in_0_a_valid,
input [2:0] io_in_0_a_bits_opcode,
input [2:0] io_in_0_a_bits_param,
input [2:0] io_in_0_a_bits_size,
input [4:0] io_in_0_a_bits_source,
input [25:0] io_in_0_a_bits_address,
input [3:0] io_in_0_a_bits_mask,
input [31:0] io_in_0_a_bits_data,
input io_in_0_b_ready,
output io_in_0_b_valid,
output [2:0] io_in_0_b_bits_opcode,
output [1:0] io_in_0_b_bits_param,
output [2:0] io_in_0_b_bits_size,
output [4:0] io_in_0_b_bits_source,
output [25:0] io_in_0_b_bits_address,
output [3:0] io_in_0_b_bits_mask,
output [31:0] io_in_0_b_bits_data,
output io_in_0_c_ready,
input io_in_0_c_valid,
input [2:0] io_in_0_c_bits_opcode,
input [2:0] io_in_0_c_bits_param,
input [2:0] io_in_0_c_bits_size,
input [4:0] io_in_0_c_bits_source,
input [25:0] io_in_0_c_bits_address,
input [31:0] io_in_0_c_bits_data,
input io_in_0_c_bits_error,
input io_in_0_d_ready,
output io_in_0_d_valid,
output [2:0] io_in_0_d_bits_opcode,
output [1:0] io_in_0_d_bits_param,
output [2:0] io_in_0_d_bits_size,
output [4:0] io_in_0_d_bits_source,
output io_in_0_d_bits_sink,
output [1:0] io_in_0_d_bits_addr_lo,
output [31:0] io_in_0_d_bits_data,
output io_in_0_d_bits_error,
output io_in_0_e_ready,
input io_in_0_e_valid,
input io_in_0_e_bits_sink,
output io_tiles_0_mtip,
output io_tiles_0_msip,
input io_rtcTick
);
reg [31:0] time_0;
reg [31:0] GEN_62;
reg [31:0] time_1;
reg [31:0] GEN_63;
wire [63:0] T_904;
wire [64:0] T_906;
wire [63:0] T_907;
wire [31:0] T_909;
wire [63:0] GEN_6;
wire [31:0] GEN_7;
reg [31:0] timecmp_0_0;
reg [31:0] GEN_64;
reg [31:0] timecmp_0_1;
reg [31:0] GEN_65;
reg ipi_0;
reg [31:0] GEN_66;
wire [63:0] T_915;
wire T_916;
wire T_940_ready;
wire T_940_valid;
wire T_940_bits_read;
wire [13:0] T_940_bits_index;
wire [31:0] T_940_bits_data;
wire [3:0] T_940_bits_mask;
wire [9:0] T_940_bits_extra;
wire T_957;
wire [23:0] T_958;
wire [1:0] T_959;
wire [6:0] T_960;
wire [9:0] T_961;
wire T_979_ready;
wire T_979_valid;
wire T_979_bits_read;
wire [31:0] T_979_bits_data;
wire [9:0] T_979_bits_extra;
wire T_1015_ready;
wire T_1015_valid;
wire T_1015_bits_read;
wire [13:0] T_1015_bits_index;
wire [31:0] T_1015_bits_data;
wire [3:0] T_1015_bits_mask;
wire [9:0] T_1015_bits_extra;
wire T_1058_0;
wire T_1058_1;
wire T_1058_2;
wire T_1058_3;
wire T_1058_4;
wire T_1063_0;
wire T_1063_1;
wire T_1063_2;
wire T_1063_3;
wire T_1063_4;
wire T_1068_0;
wire T_1068_1;
wire T_1068_2;
wire T_1068_3;
wire T_1068_4;
wire T_1073_0;
wire T_1073_1;
wire T_1073_2;
wire T_1073_3;
wire T_1073_4;
wire T_1078_0;
wire T_1078_1;
wire T_1078_2;
wire T_1078_3;
wire T_1078_4;
wire T_1083_0;
wire T_1083_1;
wire T_1083_2;
wire T_1083_3;
wire T_1083_4;
wire T_1088_0;
wire T_1088_1;
wire T_1088_2;
wire T_1088_3;
wire T_1088_4;
wire T_1093_0;
wire T_1093_1;
wire T_1093_2;
wire T_1093_3;
wire T_1093_4;
wire T_1135;
wire T_1136;
wire T_1137;
wire T_1138;
wire [7:0] T_1142;
wire [7:0] T_1146;
wire [7:0] T_1150;
wire [7:0] T_1154;
wire [15:0] T_1155;
wire [15:0] T_1156;
wire [31:0] T_1157;
wire [31:0] T_1185;
wire T_1187;
wire T_1200;
wire [31:0] GEN_8;
wire [31:0] T_1219;
wire T_1240;
wire [31:0] GEN_9;
wire T_1280;
wire [63:0] GEN_10;
wire T_1320;
wire [31:0] GEN_11;
wire T_1360;
wire [31:0] GEN_12;
wire T_1421_0;
wire T_1421_1;
wire T_1421_2;
wire T_1421_3;
wire T_1421_4;
wire T_1421_5;
wire T_1421_6;
wire T_1421_7;
wire T_1472_0;
wire T_1472_1;
wire T_1472_2;
wire T_1472_3;
wire T_1472_4;
wire T_1472_5;
wire T_1472_6;
wire T_1472_7;
wire T_1523_0;
wire T_1523_1;
wire T_1523_2;
wire T_1523_3;
wire T_1523_4;
wire T_1523_5;
wire T_1523_6;
wire T_1523_7;
wire T_1574_0;
wire T_1574_1;
wire T_1574_2;
wire T_1574_3;
wire T_1574_4;
wire T_1574_5;
wire T_1574_6;
wire T_1574_7;
wire T_1585;
wire T_1586;
wire T_1597;
wire [1:0] T_1599;
wire [2:0] T_1600;
wire GEN_0;
wire GEN_13;
wire GEN_14;
wire GEN_15;
wire GEN_16;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_1;
wire GEN_20;
wire GEN_21;
wire GEN_22;
wire GEN_23;
wire GEN_24;
wire GEN_25;
wire GEN_26;
wire T_1619;
wire GEN_2;
wire GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_31;
wire GEN_32;
wire GEN_33;
wire GEN_3;
wire GEN_34;
wire GEN_35;
wire GEN_36;
wire GEN_37;
wire GEN_38;
wire GEN_39;
wire GEN_40;
wire T_1622;
wire T_1623;
wire T_1624;
wire T_1625;
wire T_1626;
wire [7:0] T_1628;
wire T_1647;
wire T_1648;
wire T_1649;
wire T_1650;
wire T_1653;
wire T_1654;
wire T_1656;
wire T_1657;
wire T_1658;
wire T_1660;
wire T_1664;
wire T_1666;
wire T_1689;
wire T_1690;
wire T_1696;
wire T_1700;
wire T_1706;
wire T_1709;
wire T_1710;
wire T_1716;
wire T_1720;
wire T_1726;
wire T_1729;
wire T_1730;
wire T_1736;
wire T_1740;
wire T_1746;
wire T_1749;
wire T_1750;
wire T_1756;
wire T_1760;
wire T_1766;
wire T_1838_0;
wire T_1838_1;
wire T_1838_2;
wire T_1838_3;
wire T_1838_4;
wire T_1838_5;
wire T_1838_6;
wire T_1838_7;
wire [31:0] T_1861_0;
wire [31:0] T_1861_1;
wire [31:0] T_1861_2;
wire [31:0] T_1861_3;
wire [31:0] T_1861_4;
wire [31:0] T_1861_5;
wire [31:0] T_1861_6;
wire [31:0] T_1861_7;
wire GEN_4;
wire GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire GEN_45;
wire GEN_46;
wire GEN_47;
wire [31:0] GEN_5;
wire [31:0] GEN_48;
wire [31:0] GEN_49;
wire [31:0] GEN_50;
wire [31:0] GEN_51;
wire [31:0] GEN_52;
wire [31:0] GEN_53;
wire [31:0] GEN_54;
wire [31:0] T_1874;
wire [1:0] T_1875;
wire [4:0] T_1877;
wire [2:0] T_1878;
wire [2:0] T_1889_opcode;
wire [1:0] T_1889_param;
wire [2:0] T_1889_size;
wire [4:0] T_1889_source;
wire T_1889_sink;
wire [1:0] T_1889_addr_lo;
wire [31:0] T_1889_data;
wire T_1889_error;
wire [2:0] GEN_55 = 3'b0;
reg [31:0] GEN_67;
wire [1:0] GEN_56 = 2'b0;
reg [31:0] GEN_68;
wire [2:0] GEN_57 = 3'b0;
reg [31:0] GEN_69;
wire [4:0] GEN_58 = 5'b0;
reg [31:0] GEN_70;
wire [25:0] GEN_59 = 26'b0;
reg [31:0] GEN_71;
wire [3:0] GEN_60 = 4'b0;
reg [31:0] GEN_72;
wire [31:0] GEN_61 = 32'b0;
reg [31:0] GEN_73;
assign io_in_0_a_ready = T_940_ready;
assign io_in_0_b_valid = 1'h0;
assign io_in_0_b_bits_opcode = GEN_55;
assign io_in_0_b_bits_param = GEN_56;
assign io_in_0_b_bits_size = GEN_57;
assign io_in_0_b_bits_source = GEN_58;
assign io_in_0_b_bits_address = GEN_59;
assign io_in_0_b_bits_mask = GEN_60;
assign io_in_0_b_bits_data = GEN_61;
assign io_in_0_c_ready = 1'h1;
assign io_in_0_d_valid = T_979_valid;
assign io_in_0_d_bits_opcode = {{2'd0}, T_979_bits_read};
assign io_in_0_d_bits_param = T_1889_param;
assign io_in_0_d_bits_size = T_1889_size;
assign io_in_0_d_bits_source = T_1889_source;
assign io_in_0_d_bits_sink = T_1889_sink;
assign io_in_0_d_bits_addr_lo = T_1889_addr_lo;
assign io_in_0_d_bits_data = T_979_bits_data;
assign io_in_0_d_bits_error = T_1889_error;
assign io_in_0_e_ready = 1'h1;
assign io_tiles_0_mtip = T_916;
assign io_tiles_0_msip = ipi_0;
assign T_904 = {time_1,time_0};
assign T_906 = T_904 + 64'h1;
assign T_907 = T_906[63:0];
assign T_909 = T_907[63:32];
assign GEN_6 = io_rtcTick ? T_907 : {{32'd0}, time_0};
assign GEN_7 = io_rtcTick ? T_909 : time_1;
assign T_915 = {timecmp_0_1,timecmp_0_0};
assign T_916 = T_904 >= T_915;
assign T_940_ready = T_1623;
assign T_940_valid = io_in_0_a_valid;
assign T_940_bits_read = T_957;
assign T_940_bits_index = T_958[13:0];
assign T_940_bits_data = io_in_0_a_bits_data;
assign T_940_bits_mask = io_in_0_a_bits_mask;
assign T_940_bits_extra = T_961;
assign T_957 = io_in_0_a_bits_opcode == 3'h4;
assign T_958 = io_in_0_a_bits_address[25:2];
assign T_959 = io_in_0_a_bits_address[1:0];
assign T_960 = {T_959,io_in_0_a_bits_source};
assign T_961 = {T_960,io_in_0_a_bits_size};
assign T_979_ready = io_in_0_d_ready;
assign T_979_valid = T_1626;
assign T_979_bits_read = T_1015_bits_read;
assign T_979_bits_data = T_1874;
assign T_979_bits_extra = T_1015_bits_extra;
assign T_1015_ready = T_1625;
assign T_1015_valid = T_1624;
assign T_1015_bits_read = T_940_bits_read;
assign T_1015_bits_index = T_940_bits_index;
assign T_1015_bits_data = T_940_bits_data;
assign T_1015_bits_mask = T_940_bits_mask;
assign T_1015_bits_extra = T_940_bits_extra;
assign T_1058_0 = T_1650;
assign T_1058_1 = T_1750;
assign T_1058_2 = T_1690;
assign T_1058_3 = T_1710;
assign T_1058_4 = T_1730;
assign T_1063_0 = T_1656;
assign T_1063_1 = T_1756;
assign T_1063_2 = T_1696;
assign T_1063_3 = T_1716;
assign T_1063_4 = T_1736;
assign T_1068_0 = 1'h1;
assign T_1068_1 = 1'h1;
assign T_1068_2 = 1'h1;
assign T_1068_3 = 1'h1;
assign T_1068_4 = 1'h1;
assign T_1073_0 = 1'h1;
assign T_1073_1 = 1'h1;
assign T_1073_2 = 1'h1;
assign T_1073_3 = 1'h1;
assign T_1073_4 = 1'h1;
assign T_1078_0 = 1'h1;
assign T_1078_1 = 1'h1;
assign T_1078_2 = 1'h1;
assign T_1078_3 = 1'h1;
assign T_1078_4 = 1'h1;
assign T_1083_0 = 1'h1;
assign T_1083_1 = 1'h1;
assign T_1083_2 = 1'h1;
assign T_1083_3 = 1'h1;
assign T_1083_4 = 1'h1;
assign T_1088_0 = T_1660;
assign T_1088_1 = T_1760;
assign T_1088_2 = T_1700;
assign T_1088_3 = T_1720;
assign T_1088_4 = T_1740;
assign T_1093_0 = T_1666;
assign T_1093_1 = T_1766;
assign T_1093_2 = T_1706;
assign T_1093_3 = T_1726;
assign T_1093_4 = T_1746;
assign T_1135 = T_1015_bits_mask[0];
assign T_1136 = T_1015_bits_mask[1];
assign T_1137 = T_1015_bits_mask[2];
assign T_1138 = T_1015_bits_mask[3];
assign T_1142 = T_1135 ? 8'hff : 8'h0;
assign T_1146 = T_1136 ? 8'hff : 8'h0;
assign T_1150 = T_1137 ? 8'hff : 8'h0;
assign T_1154 = T_1138 ? 8'hff : 8'h0;
assign T_1155 = {T_1146,T_1142};
assign T_1156 = {T_1154,T_1150};
assign T_1157 = {T_1156,T_1155};
assign T_1185 = ~ T_1157;
assign T_1187 = T_1185 == 32'h0;
assign T_1200 = T_1093_0 & T_1187;
assign GEN_8 = T_1200 ? T_1015_bits_data : {{31'd0}, ipi_0};
assign T_1219 = {{31'd0}, ipi_0};
assign T_1240 = T_1093_1 & T_1187;
assign GEN_9 = T_1240 ? T_1015_bits_data : timecmp_0_1;
assign T_1280 = T_1093_2 & T_1187;
assign GEN_10 = T_1280 ? {{32'd0}, T_1015_bits_data} : GEN_6;
assign T_1320 = T_1093_3 & T_1187;
assign GEN_11 = T_1320 ? T_1015_bits_data : GEN_7;
assign T_1360 = T_1093_4 & T_1187;
assign GEN_12 = T_1360 ? T_1015_bits_data : timecmp_0_0;
assign T_1421_0 = T_1068_0;
assign T_1421_1 = 1'h1;
assign T_1421_2 = T_1068_2;
assign T_1421_3 = T_1068_3;
assign T_1421_4 = T_1068_4;
assign T_1421_5 = T_1068_1;
assign T_1421_6 = 1'h1;
assign T_1421_7 = 1'h1;
assign T_1472_0 = T_1073_0;
assign T_1472_1 = 1'h1;
assign T_1472_2 = T_1073_2;
assign T_1472_3 = T_1073_3;
assign T_1472_4 = T_1073_4;
assign T_1472_5 = T_1073_1;
assign T_1472_6 = 1'h1;
assign T_1472_7 = 1'h1;
assign T_1523_0 = T_1078_0;
assign T_1523_1 = 1'h1;
assign T_1523_2 = T_1078_2;
assign T_1523_3 = T_1078_3;
assign T_1523_4 = T_1078_4;
assign T_1523_5 = T_1078_1;
assign T_1523_6 = 1'h1;
assign T_1523_7 = 1'h1;
assign T_1574_0 = T_1083_0;
assign T_1574_1 = 1'h1;
assign T_1574_2 = T_1083_2;
assign T_1574_3 = T_1083_3;
assign T_1574_4 = T_1083_4;
assign T_1574_5 = T_1083_1;
assign T_1574_6 = 1'h1;
assign T_1574_7 = 1'h1;
assign T_1585 = T_1015_bits_index[0];
assign T_1586 = T_1015_bits_index[1];
assign T_1597 = T_1015_bits_index[12];
assign T_1599 = {T_1597,T_1586};
assign T_1600 = {T_1599,T_1585};
assign GEN_0 = GEN_19;
assign GEN_13 = 3'h1 == T_1600 ? T_1421_1 : T_1421_0;
assign GEN_14 = 3'h2 == T_1600 ? T_1421_2 : GEN_13;
assign GEN_15 = 3'h3 == T_1600 ? T_1421_3 : GEN_14;
assign GEN_16 = 3'h4 == T_1600 ? T_1421_4 : GEN_15;
assign GEN_17 = 3'h5 == T_1600 ? T_1421_5 : GEN_16;
assign GEN_18 = 3'h6 == T_1600 ? T_1421_6 : GEN_17;
assign GEN_19 = 3'h7 == T_1600 ? T_1421_7 : GEN_18;
assign GEN_1 = GEN_26;
assign GEN_20 = 3'h1 == T_1600 ? T_1472_1 : T_1472_0;
assign GEN_21 = 3'h2 == T_1600 ? T_1472_2 : GEN_20;
assign GEN_22 = 3'h3 == T_1600 ? T_1472_3 : GEN_21;
assign GEN_23 = 3'h4 == T_1600 ? T_1472_4 : GEN_22;
assign GEN_24 = 3'h5 == T_1600 ? T_1472_5 : GEN_23;
assign GEN_25 = 3'h6 == T_1600 ? T_1472_6 : GEN_24;
assign GEN_26 = 3'h7 == T_1600 ? T_1472_7 : GEN_25;
assign T_1619 = T_1015_bits_read ? GEN_0 : GEN_1;
assign GEN_2 = GEN_33;
assign GEN_27 = 3'h1 == T_1600 ? T_1523_1 : T_1523_0;
assign GEN_28 = 3'h2 == T_1600 ? T_1523_2 : GEN_27;
assign GEN_29 = 3'h3 == T_1600 ? T_1523_3 : GEN_28;
assign GEN_30 = 3'h4 == T_1600 ? T_1523_4 : GEN_29;
assign GEN_31 = 3'h5 == T_1600 ? T_1523_5 : GEN_30;
assign GEN_32 = 3'h6 == T_1600 ? T_1523_6 : GEN_31;
assign GEN_33 = 3'h7 == T_1600 ? T_1523_7 : GEN_32;
assign GEN_3 = GEN_40;
assign GEN_34 = 3'h1 == T_1600 ? T_1574_1 : T_1574_0;
assign GEN_35 = 3'h2 == T_1600 ? T_1574_2 : GEN_34;
assign GEN_36 = 3'h3 == T_1600 ? T_1574_3 : GEN_35;
assign GEN_37 = 3'h4 == T_1600 ? T_1574_4 : GEN_36;
assign GEN_38 = 3'h5 == T_1600 ? T_1574_5 : GEN_37;
assign GEN_39 = 3'h6 == T_1600 ? T_1574_6 : GEN_38;
assign GEN_40 = 3'h7 == T_1600 ? T_1574_7 : GEN_39;
assign T_1622 = T_1015_bits_read ? GEN_2 : GEN_3;
assign T_1623 = T_1015_ready & T_1619;
assign T_1624 = T_940_valid & T_1619;
assign T_1625 = T_979_ready & T_1622;
assign T_1626 = T_1015_valid & T_1622;
assign T_1628 = 8'h1 << T_1600;
assign T_1647 = T_940_valid & T_1015_ready;
assign T_1648 = T_1647 & T_1015_bits_read;
assign T_1649 = T_1628[0];
assign T_1650 = T_1648 & T_1649;
assign T_1653 = T_1015_bits_read == 1'h0;
assign T_1654 = T_1647 & T_1653;
assign T_1656 = T_1654 & T_1649;
assign T_1657 = T_1015_valid & T_979_ready;
assign T_1658 = T_1657 & T_1015_bits_read;
assign T_1660 = T_1658 & T_1649;
assign T_1664 = T_1657 & T_1653;
assign T_1666 = T_1664 & T_1649;
assign T_1689 = T_1628[2];
assign T_1690 = T_1648 & T_1689;
assign T_1696 = T_1654 & T_1689;
assign T_1700 = T_1658 & T_1689;
assign T_1706 = T_1664 & T_1689;
assign T_1709 = T_1628[3];
assign T_1710 = T_1648 & T_1709;
assign T_1716 = T_1654 & T_1709;
assign T_1720 = T_1658 & T_1709;
assign T_1726 = T_1664 & T_1709;
assign T_1729 = T_1628[4];
assign T_1730 = T_1648 & T_1729;
assign T_1736 = T_1654 & T_1729;
assign T_1740 = T_1658 & T_1729;
assign T_1746 = T_1664 & T_1729;
assign T_1749 = T_1628[5];
assign T_1750 = T_1648 & T_1749;
assign T_1756 = T_1654 & T_1749;
assign T_1760 = T_1658 & T_1749;
assign T_1766 = T_1664 & T_1749;
assign T_1838_0 = 1'h1;
assign T_1838_1 = 1'h1;
assign T_1838_2 = 1'h1;
assign T_1838_3 = 1'h1;
assign T_1838_4 = 1'h1;
assign T_1838_5 = 1'h1;
assign T_1838_6 = 1'h1;
assign T_1838_7 = 1'h1;
assign T_1861_0 = T_1219;
assign T_1861_1 = 32'h0;
assign T_1861_2 = time_0;
assign T_1861_3 = time_1;
assign T_1861_4 = timecmp_0_0;
assign T_1861_5 = timecmp_0_1;
assign T_1861_6 = 32'h0;
assign T_1861_7 = 32'h0;
assign GEN_4 = GEN_47;
assign GEN_41 = 3'h1 == T_1600 ? T_1838_1 : T_1838_0;
assign GEN_42 = 3'h2 == T_1600 ? T_1838_2 : GEN_41;
assign GEN_43 = 3'h3 == T_1600 ? T_1838_3 : GEN_42;
assign GEN_44 = 3'h4 == T_1600 ? T_1838_4 : GEN_43;
assign GEN_45 = 3'h5 == T_1600 ? T_1838_5 : GEN_44;
assign GEN_46 = 3'h6 == T_1600 ? T_1838_6 : GEN_45;
assign GEN_47 = 3'h7 == T_1600 ? T_1838_7 : GEN_46;
assign GEN_5 = GEN_54;
assign GEN_48 = 3'h1 == T_1600 ? T_1861_1 : T_1861_0;
assign GEN_49 = 3'h2 == T_1600 ? T_1861_2 : GEN_48;
assign GEN_50 = 3'h3 == T_1600 ? T_1861_3 : GEN_49;
assign GEN_51 = 3'h4 == T_1600 ? T_1861_4 : GEN_50;
assign GEN_52 = 3'h5 == T_1600 ? T_1861_5 : GEN_51;
assign GEN_53 = 3'h6 == T_1600 ? T_1861_6 : GEN_52;
assign GEN_54 = 3'h7 == T_1600 ? T_1861_7 : GEN_53;
assign T_1874 = GEN_4 ? GEN_5 : 32'h0;
assign T_1875 = T_979_bits_extra[9:8];
assign T_1877 = T_979_bits_extra[7:3];
assign T_1878 = T_979_bits_extra[2:0];
assign T_1889_opcode = 3'h0;
assign T_1889_param = 2'h0;
assign T_1889_size = T_1878;
assign T_1889_source = T_1877;
assign T_1889_sink = 1'h0;
assign T_1889_addr_lo = T_1875;
assign T_1889_data = 32'h0;
assign T_1889_error = 1'h0;
always @(posedge clock or posedge reset) begin
if (reset) begin
time_0 <= 32'h0;
end else begin
time_0 <= GEN_10[31:0];
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
time_1 <= 32'h0;
end else begin
if (T_1320) begin
time_1 <= T_1015_bits_data;
end else begin
if (io_rtcTick) begin
time_1 <= T_909;
end
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
timecmp_0_0 <= 32'hFFFF_FFFF;
end
else if (T_1360) begin
timecmp_0_0 <= T_1015_bits_data;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
timecmp_0_1 <= 32'hFFFF_FFFF;
end
else if (T_1240) begin
timecmp_0_1 <= T_1015_bits_data;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
ipi_0 <= 1'h0;
end else begin
ipi_0 <= GEN_8[0];
end
end
endmodule
|
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ([email protected])
//
// Brief Description:
// PLL for generating system and TX sample clocks (uses Altera PLL primitive).
//
//------------------------------------------------------------------------------
`ifndef _ZL_SYS_PLL_V_
`define _ZL_SYS_PLL_V_
module zl_sys_pll
(
input clk_ref,
input rst_n,
//
output clk_sys,
output clk_sample,
//
output lock
);
wire [4:0] pll_out;
assign clk_sys = pll_out[0];
assign clk_sample = pll_out[1];
altpll #
(
.bandwidth_type("AUTO"),
.clk0_divide_by(1),
.clk0_duty_cycle(50),
.clk0_multiply_by(1),
.clk0_phase_shift("0"),
.clk1_divide_by(25),
.clk1_duty_cycle(50),
.clk1_multiply_by(2),
.clk1_phase_shift("0"),
.compensate_clock("CLK0"),
.inclk0_input_frequency(20000),
.intended_device_family("Cyclone IV E"),
.lpm_type("altpll"),
.operation_mode("NORMAL"),
.pll_type("AUTO"),
.port_activeclock("PORT_UNUSED"),
.port_areset("PORT_USED"),
.port_clkbad0("PORT_UNUSED"),
.port_clkbad1("PORT_UNUSED"),
.port_clkloss("PORT_UNUSED"),
.port_clkswitch("PORT_UNUSED"),
.port_configupdate("PORT_UNUSED"),
.port_fbin("PORT_UNUSED"),
.port_inclk0("PORT_USED"),
.port_inclk1("PORT_UNUSED"),
.port_locked("PORT_USED"),
.port_pfdena("PORT_UNUSED"),
.port_phasecounterselect("PORT_UNUSED"),
.port_phasedone("PORT_UNUSED"),
.port_phasestep("PORT_UNUSED"),
.port_phaseupdown("PORT_UNUSED"),
.port_pllena("PORT_UNUSED"),
.port_scanaclr("PORT_UNUSED"),
.port_scanclk("PORT_UNUSED"),
.port_scanclkena("PORT_UNUSED"),
.port_scandata("PORT_UNUSED"),
.port_scandataout("PORT_UNUSED"),
.port_scandone("PORT_UNUSED"),
.port_scanread("PORT_UNUSED"),
.port_scanwrite("PORT_UNUSED"),
.port_clk0("PORT_USED"),
.port_clk1("PORT_USED"),
.port_clk2("PORT_UNUSED"),
.port_clk3("PORT_UNUSED"),
.port_clk4("PORT_UNUSED"),
.port_clk5("PORT_UNUSED"),
.port_clkena0("PORT_UNUSED"),
.port_clkena1("PORT_UNUSED"),
.port_clkena2("PORT_UNUSED"),
.port_clkena3("PORT_UNUSED"),
.port_clkena4("PORT_UNUSED"),
.port_clkena5("PORT_UNUSED"),
.port_extclk0("PORT_UNUSED"),
.port_extclk1("PORT_UNUSED"),
.port_extclk2("PORT_UNUSED"),
.port_extclk3("PORT_UNUSED"),
.self_reset_on_loss_lock("OFF"),
.width_clock(5)
)
zl_sys_pll_inst
(
.areset (~rst_n),
.inclk ({1'b0, clk_ref}),
.clk (pll_out),
.locked (lock),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ()
);
endmodule // zl_sys_pll
`endif // _ZL_SYS_PLL_V_
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBN_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__SDFBBN_PP_BLACKBOX_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBN_PP_BLACKBOX_V
|
module TOP(CLK, RST, IN, IN2, reg1, OUT);
input CLK, RST, IN, IN2;
reg reg1,reg2,reg3;
output reg1,OUT;
wire in1;
always @(posedge CLK or negedge RST) begin
if(RST) begin
reg1 <= 1'b0;
end else begin
reg1 <= IN;
end
end
always @(posedge CLK or negedge RST) begin
if(RST) begin
reg2 <= 1'b0;
end else begin
reg2 <= func1(reg1);
end
end
SUB sub(CLK,RST,in1,OUT);
SUB2 ccc(CLK,RST,in1);
function func1;
input bit;
if(bit)
func1 = !bit;
else
func1 = bit;
endfunction
endmodule
module SUB(CLK,RST,IN, OUT);
input CLK, RST, IN;
output OUT;
reg reg1;
wire OUT = reg1;
always @(posedge CLK or negedge RST) begin
if(RST) begin
reg1 <= 1'b0;
end else begin
reg1 <= 1'b1;
end
end
endmodule
module SUB2(CLK,RST,IN);
input CLK, RST, IN;
reg reg1;
always @(posedge CLK or negedge RST) begin
if(RST) begin
reg1 <= 1'b0;
end else if(IN) begin
reg1 <= 1'b0;
end else begin
reg1 <= 1'b1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXTP_SYMBOL_V
`define SKY130_FD_SC_LS__SEDFXTP_SYMBOL_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sedfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input DE ,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXTP_SYMBOL_V
|
// file: Clock48MHZ_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock48MHZ_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.000*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [4:1] COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [4:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (10.000*1*31.750*1000/15.250);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (10.000*1*8*1000/15.250);
time prev_rise2;
real period3;
real ref_period3;
localparam ref_period3_clkin1 = (10.000*1*15*1000/15.250);
time prev_rise3;
real period4;
real ref_period4;
localparam ref_period4_clkin1 = (10.000*1*103*1000/15.250);
time prev_rise4;
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
if ((period1 -ref_period1_clkin1) <= 100 && (period1 -ref_period1_clkin1) >= -100) begin
$display("Freq of CLK_OUT[1] ( in MHz ) : %0f\n", 1000000/period1);
end else
$display("ERROR: Freq of CLK_OUT[1] is not correct");
if ((period2 -ref_period2_clkin1) <= 100 && (period2 -ref_period2_clkin1) >= -100) begin
$display("Freq of CLK_OUT[2] ( in MHz ) : %0f\n", 1000000/period2);
end else
$display("ERROR: Freq of CLK_OUT[2] is not correct");
if ((period3 -ref_period3_clkin1) <= 100 && (period3 -ref_period3_clkin1) >= -100) begin
$display("Freq of CLK_OUT[3] ( in MHz ) : %0f\n", 1000000/period3);
end else
$display("ERROR: Freq of CLK_OUT[3] is not correct");
if ((period4 -ref_period4_clkin1) <= 100 && (period4 -ref_period4_clkin1) >= -100) begin
$display("Freq of CLK_OUT[4] ( in MHz ) : %0f\n", 1000000/period4);
end else
$display("ERROR: Freq of CLK_OUT[4] is not correct");
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock48MHZ_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
initial
prev_rise1 = 0;
always @(posedge CLK_OUT[1])
begin
if (prev_rise1 != 0)
period1 = $time - prev_rise1;
prev_rise1 = $time;
end
initial
prev_rise2 = 0;
always @(posedge CLK_OUT[2])
begin
if (prev_rise2 != 0)
period2 = $time - prev_rise2;
prev_rise2 = $time;
end
initial
prev_rise3 = 0;
always @(posedge CLK_OUT[3])
begin
if (prev_rise3 != 0)
period3 = $time - prev_rise3;
prev_rise3 = $time;
end
initial
prev_rise4 = 0;
always @(posedge CLK_OUT[4])
begin
if (prev_rise4 != 0)
period4 = $time - prev_rise4;
prev_rise4 = $time;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCIN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__FAHCIN_FUNCTIONAL_PP_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCIN_FUNCTIONAL_PP_V
|
//======================================================================
//
// sha256_k_constants.v
// --------------------
// The table K with constants in the SHA-256 hash function.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module sha256_k_constants(
input wire [5 : 0] round,
output wire [31 : 0] K
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_K;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign K = tmp_K;
//----------------------------------------------------------------
// round_mux
//----------------------------------------------------------------
always @*
begin : round_mux
case(round)
00: tmp_K = 32'h428a2f98;
01: tmp_K = 32'h71374491;
02: tmp_K = 32'hb5c0fbcf;
03: tmp_K = 32'he9b5dba5;
04: tmp_K = 32'h3956c25b;
05: tmp_K = 32'h59f111f1;
06: tmp_K = 32'h923f82a4;
07: tmp_K = 32'hab1c5ed5;
08: tmp_K = 32'hd807aa98;
09: tmp_K = 32'h12835b01;
10: tmp_K = 32'h243185be;
11: tmp_K = 32'h550c7dc3;
12: tmp_K = 32'h72be5d74;
13: tmp_K = 32'h80deb1fe;
14: tmp_K = 32'h9bdc06a7;
15: tmp_K = 32'hc19bf174;
16: tmp_K = 32'he49b69c1;
17: tmp_K = 32'hefbe4786;
18: tmp_K = 32'h0fc19dc6;
19: tmp_K = 32'h240ca1cc;
20: tmp_K = 32'h2de92c6f;
21: tmp_K = 32'h4a7484aa;
22: tmp_K = 32'h5cb0a9dc;
23: tmp_K = 32'h76f988da;
24: tmp_K = 32'h983e5152;
25: tmp_K = 32'ha831c66d;
26: tmp_K = 32'hb00327c8;
27: tmp_K = 32'hbf597fc7;
28: tmp_K = 32'hc6e00bf3;
29: tmp_K = 32'hd5a79147;
30: tmp_K = 32'h06ca6351;
31: tmp_K = 32'h14292967;
32: tmp_K = 32'h27b70a85;
33: tmp_K = 32'h2e1b2138;
34: tmp_K = 32'h4d2c6dfc;
35: tmp_K = 32'h53380d13;
36: tmp_K = 32'h650a7354;
37: tmp_K = 32'h766a0abb;
38: tmp_K = 32'h81c2c92e;
39: tmp_K = 32'h92722c85;
40: tmp_K = 32'ha2bfe8a1;
41: tmp_K = 32'ha81a664b;
42: tmp_K = 32'hc24b8b70;
43: tmp_K = 32'hc76c51a3;
44: tmp_K = 32'hd192e819;
45: tmp_K = 32'hd6990624;
46: tmp_K = 32'hf40e3585;
47: tmp_K = 32'h106aa070;
48: tmp_K = 32'h19a4c116;
49: tmp_K = 32'h1e376c08;
50: tmp_K = 32'h2748774c;
51: tmp_K = 32'h34b0bcb5;
52: tmp_K = 32'h391c0cb3;
53: tmp_K = 32'h4ed8aa4a;
54: tmp_K = 32'h5b9cca4f;
55: tmp_K = 32'h682e6ff3;
56: tmp_K = 32'h748f82ee;
57: tmp_K = 32'h78a5636f;
58: tmp_K = 32'h84c87814;
59: tmp_K = 32'h8cc70208;
60: tmp_K = 32'h90befffa;
61: tmp_K = 32'ha4506ceb;
62: tmp_K = 32'hbef9a3f7;
63: tmp_K = 32'hc67178f2;
endcase // case (round)
end // block: round_mux
endmodule // sha256_k_constants
//======================================================================
// sha256_k_constants.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S2S_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DLYMETAL6S2S_PP_SYMBOL_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlymetal6s2s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S2S_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211O_1_V
`define SKY130_FD_SC_HDLL__A211O_1_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a211o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a211o_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a211o_1 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211O_1_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_adrgen #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [10:0] dx_c,
input [10:0] dy_c,
input [16:0] tx_c,
input [16:0] ty_c,
input [fml_depth-1-1:0] dst_fbuf, /* in 16-bit words */
input [10:0] dst_hres,
input [fml_depth-1-1:0] tex_fbuf, /* in 16-bit words */
input [10:0] tex_hres,
output pipe_stb_o,
input pipe_ack_i,
output [fml_depth-1-1:0] dadr, /* in 16-bit words */
output [fml_depth-1-1:0] tadra,
output [fml_depth-1-1:0] tadrb,
output [fml_depth-1-1:0] tadrc,
output [fml_depth-1-1:0] tadrd,
output [5:0] x_frac,
output [5:0] y_frac
);
/* Arithmetic pipeline. Enable signal is shared to ease usage of hard macros. */
wire pipe_en;
reg valid_1;
reg [fml_depth-1-1:0] dadr_1;
reg [fml_depth-1-1:0] tadra_1;
reg [5:0] x_frac_1;
reg [5:0] y_frac_1;
reg valid_2;
reg [fml_depth-1-1:0] dadr_2;
reg [fml_depth-1-1:0] tadra_2;
reg [5:0] x_frac_2;
reg [5:0] y_frac_2;
reg valid_3;
reg [fml_depth-1-1:0] dadr_3;
reg [fml_depth-1-1:0] tadra_3;
reg [fml_depth-1-1:0] tadrb_3;
reg [fml_depth-1-1:0] tadrc_3;
reg [fml_depth-1-1:0] tadrd_3;
reg [5:0] x_frac_3;
reg [5:0] y_frac_3;
always @(posedge sys_clk) begin
if(sys_rst) begin
valid_1 <= 1'b0;
valid_2 <= 1'b0;
valid_3 <= 1'b0;
end else if(pipe_en) begin
valid_1 <= pipe_stb_i;
dadr_1 <= dst_fbuf + dst_hres*dy_c + dx_c;
tadra_1 <= tex_fbuf + tex_hres*ty_c[16:6] + tx_c[16:6];
x_frac_1 <= tx_c[5:0];
y_frac_1 <= ty_c[5:0];
valid_2 <= valid_1;
dadr_2 <= dadr_1;
tadra_2 <= tadra_1;
x_frac_2 <= x_frac_1;
y_frac_2 <= y_frac_1;
valid_3 <= valid_2;
dadr_3 <= dadr_2;
tadra_3 <= tadra_2;
tadrb_3 <= tadra_2 + 1'd1;
tadrc_3 <= tadra_2 + tex_hres;
tadrd_3 <= tadra_2 + tex_hres + 1'd1;
x_frac_3 <= x_frac_2;
y_frac_3 <= y_frac_2;
end
end
/* Glue logic */
assign pipe_stb_o = valid_3;
assign dadr = dadr_3;
assign tadra = tadra_3;
assign tadrb = tadrb_3;
assign tadrc = tadrc_3;
assign tadrd = tadrd_3;
assign x_frac = x_frac_3;
assign y_frac = y_frac_3;
assign pipe_en = ~valid_3 | pipe_ack_i;
assign pipe_ack_o = ~valid_3 | pipe_ack_i;
assign busy = valid_1 | valid_2 | valid_3;
endmodule
|
//----------------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//----------------------------------------------------------------------------
// Filename : db_lcu_ram.v
// Author : chewein
// Created : 2014-04-18
// Description : memory of luma pixels:192 x 16 x 8 bits
//----------------------------------------------------------------------------
module db_lcu_ram(
clka ,
cena_i ,
rena_i ,
wena_i ,
addra_i ,
dataa_o ,
dataa_i ,
clkb ,
cenb_i ,
renb_i ,
wenb_i ,
addrb_i ,
datab_o ,
datab_i
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter DATA_WIDTH = 128 ;
parameter ADDR_WIDTH = 8 ;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
// A port
input clka ; // clock input
input cena_i ; // chip enable, low active
input rena_i ; // data output enable, low active
input wena_i ; // write enable, low active
input [ADDR_WIDTH-1:0] addra_i; // address input
input [DATA_WIDTH-1:0] dataa_i; // data input
output [DATA_WIDTH-1:0] dataa_o; // data output
// B Port
input clkb ; // clock input
input cenb_i ; // chip enable, low active
input renb_i ; // data output enable, low active
input wenb_i ; // write enable, low active
input [ADDR_WIDTH-1:0] addrb_i; // address input
input [DATA_WIDTH-1:0] datab_i; // data input
output [DATA_WIDTH-1:0] datab_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [DATA_WIDTH-1:0] mem_array[(1<<ADDR_WIDTH)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [DATA_WIDTH-1:0] dataa_r;
reg [DATA_WIDTH-1:0] datab_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// -- A Port --//
always @(posedge clka) begin
if(!cena_i && !wena_i)
mem_array[addra_i] <= dataa_i;
end
always @(posedge clka) begin
if (!cena_i && wena_i)
dataa_r <= mem_array[addra_i];
else
dataa_r <= 'bx;
end
assign dataa_o = rena_i ? 'bz : dataa_r;
// -- B Port --//
always @(posedge clkb) begin
if(!cenb_i && !wenb_i)
mem_array[addrb_i] <= datab_i;
end
always @(posedge clkb) begin
if (!cenb_i && wenb_i)
datab_r <= mem_array[addrb_i];
else
datab_r <= 'bx;
end
assign datab_o = renb_i ? 'bz : datab_r;
endmodule
|
module color_component_driver
(
input clk,
input reset_n,
input test_panel_select_n,
input shift,
input load_led_vals,
input load_brightness,
input [7:0] pwm_time,
input [127:0] component_values,
output serial_data_out
);
wire [7:0] brightness;
wire [15:0] brightness_extended;
wire [15:0] out;
wire [15:0] led_vals_out;
assign brightness = 8'hff; //TODO: Replace with host-defined brightness
assign brightness_extended = {8'h00, brightness};
// Odd & even columns are switched on the cube panels
piso_shift_register #(.WIDTH(16)) sr
(.clk(clk), .reset_n(reset_n),
.par_in_a({out[1], out[0], out[3], out[2],
out[5], out[4], out[7], out[6],
out[9], out[8], out[11], out[10],
out[13], out[12], out[15], out[14]}),
.par_in_b(brightness_extended),
.load_a(load_led_vals), .load_b(load_brightness),
.shift(shift), .ser_out(serial_data_out));
genvar i;
generate
for (i=0; i<16; i=i+1)
begin : comparator
assign out[i] = pwm_time < component_values[8*i+7:8*i];
end
endgenerate
endmodule // color_component_driver
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FA_SYMBOL_V
`define SKY130_FD_SC_LP__FA_SYMBOL_V
/**
* fa: Full adder.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fa (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FA_SYMBOL_V
|
//This is the playfield engine.
//It takes the raw bitplane data and generates a
//single or dual playfield
//it also generated the nplayfield valid data signals which are needed
//by the main video priority logic in Denise
module denise_playfields
(
input aga,
input [8:1] bpldata, //raw bitplane data in
input dblpf, //double playfield select
input [2:0] pf2of, // playfield 2 offset into color table
input [6:0] bplcon2, //bplcon2 (playfields priority)
output reg [2:1] nplayfield, //playfield 1,2 valid data
output reg [7:0] plfdata //playfield data out
);
//local signals
wire pf2pri; //playfield 2 priority over playfield 1
wire [2:0] pf2p; //playfield 2 priority code
reg [7:0] pf2of_val; // playfield 2 offset value
assign pf2pri = bplcon2[6];
assign pf2p = bplcon2[5:3];
always @ (*) begin
case(pf2of)
3'd0 : pf2of_val = 8'd0;
3'd1 : pf2of_val = 8'd2;
3'd2 : pf2of_val = 8'd4;
3'd3 : pf2of_val = 8'd8;
3'd4 : pf2of_val = 8'd16;
3'd5 : pf2of_val = 8'd32;
3'd6 : pf2of_val = 8'd64;
3'd7 : pf2of_val = 8'd128;
endcase
end
//generate playfield 1,2 data valid signals
always @(*)
begin
if (dblpf) //dual playfield
begin
if (bpldata[7] || bpldata[5] || bpldata[3] || bpldata[1]) //detect data valid for playfield 1
nplayfield[1] = 1;
else
nplayfield[1] = 0;
if (bpldata[8] || bpldata[6] || bpldata[4] || bpldata[2]) //detect data valid for playfield 2
nplayfield[2] = 1;
else
nplayfield[2] = 0;
end
else //single playfield is always playfield 2
begin
nplayfield[1] = 0;
if (bpldata[8:1]!=8'b000000)
nplayfield[2] = 1;
else
nplayfield[2] = 0;
end
end
//playfield 1 and 2 priority logic
always @(*)
begin
if (dblpf) //dual playfield
begin
if (pf2pri) //playfield 2 (2,4,6) has priority
begin
if (nplayfield[2])
if (aga)
plfdata[7:0] = {4'b0000,bpldata[8],bpldata[6],bpldata[4],bpldata[2]} + pf2of_val;
else
plfdata[7:0] = {4'b0000,1'b1,bpldata[6],bpldata[4],bpldata[2]};
else if (nplayfield[1])
plfdata[7:0] = {4'b0000,bpldata[7],bpldata[5],bpldata[3],bpldata[1]};
else //both planes transparant, select background color
plfdata[7:0] = 8'b00000000;
end
else //playfield 1 (1,3,5) has priority
begin
if (nplayfield[1])
plfdata[7:0] = {4'b0000,bpldata[7],bpldata[5],bpldata[3],bpldata[1]};
else if (nplayfield[2])
if (aga)
plfdata[7:0] = {4'b0000,bpldata[8],bpldata[6],bpldata[4],bpldata[2]} + pf2of_val;
else
plfdata[7:0] = {4'b0000,1'b1,bpldata[6],bpldata[4],bpldata[2]};
else //both planes transparent, select background color
plfdata[7:0] = 8'b00000000;
end
end
else //normal single playfield (playfield 2 only)
//OCS/ECS undocumented feature when bpu=5 and pf2pri>5 (Swiv score display)
if ((pf2p>5) && bpldata[5] && !aga)
plfdata[7:0] = {8'b00010000};
else
plfdata[7:0] = bpldata[8:1];
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: cmd_prbs_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This moduel use LFSR to generate random address, isntructions
// or burst_length.
//Reference:
//Revision History: 1.1 Added condition to zero out the LSB address bits according to
// DWIDTH and FAMILY. 7/9/2009
//
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_cmd_prbs_gen_axi #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter ADDR_WIDTH = 29,
parameter DWIDTH = 32,
parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS"
parameter PRBS_WIDTH = 64, // 64,15,20
parameter SEED_WIDTH = 32, // 32,15,4
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter PRBS_EADDR = 32'h00002000,
parameter PRBS_SADDR = 32'h00002000
)
(
input clk_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input clk_en,
input [SEED_WIDTH-1:0] prbs_seed_i,
output[SEED_WIDTH-1:0] prbs_o // generated address
);
wire[ADDR_WIDTH - 1:0] ZEROS;
reg [SEED_WIDTH - 1:0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
assign ZEROS = 'b0;
//
//**************************************************************
//####################################################################################################################
// #
// #
// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} #
// upper 32 bits are loadable #
// #
//
//
// ........................................................................................
// ^ ^ ^ ^ |
// | ____ | ___ ___ | ___ | ___ ___ ___ |
// | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable.
// ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<--
// |___| --- |___| |___| --- |___| --- |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages.
// we need to provide 30 bits addres. SRLC32 has only one bit output.
// address seed will be loaded to upper 32 bits.
//
// parallel load and serial shift out to LFSR during INIT time
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64) begin :gen64_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {31'b0,prbs_seed_i};
end else if(clk_en) begin
lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63];
lfsr_q[63] <= #TCQ lfsr_q[62];
lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61];
lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60];
lfsr_q[60:2] <= #TCQ lfsr_q[59:1];
lfsr_q[1] <= #TCQ lfsr_q[64];
end
end
always @(lfsr_q[32:1]) begin
prbs = lfsr_q[32:1];
end
end
endgenerate
function integer logb2;
input [31:0] in;
integer i;
begin
i = in;
for(logb2=1; i>0; logb2=logb2+1)
i = i >> 1;
end
endfunction
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32) begin :gen32_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {prbs_seed_i};
end else if(clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
integer i;
always @(lfsr_q[32:1]) begin
if (FAMILY == "SPARTAN6" ) begin // for 32 bits
for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = lfsr_q[i+1];
prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}};
end
else begin
for(i = logb2(DWIDTH)-4; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = lfsr_q[i+1];
prbs[logb2(DWIDTH)-5:0] = {logb2(DWIDTH) - 4{1'b0}};
end
end
end endgenerate
//////////////////////////////////////////////////////////////////////////
//####################################################################################################################
// #
// #
// 15 taps: [15,14]: #
// #
// #
//
//
// .............................................................
// ^ ^ . ^
// | ____ | ___ ___ ___ ___ ___ |
// | | | |---|<- | | | | | |...| | | | |
// ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<--
// |___| --- |___| |___| |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
generate
if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN") begin :gen20_taps
always @(posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]};
end else if(clk_en) begin
lfsr_q[20] <= #TCQ lfsr_q[19];
lfsr_q[19] <= #TCQ lfsr_q[18];
lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17];
lfsr_q[17:2] <= #TCQ lfsr_q[16:1];
lfsr_q[1] <= #TCQ lfsr_q[20];
end
end
always @ (lfsr_q) begin
prbs = lfsr_q[32:1];
end
end
endgenerate
assign prbs_o = prbs;
endmodule
|
//`include "uart_tx_buffer.v"
`timescale 1ns/1ns
module uart_tx_buffer_tb();
// Declare inputs as regs and outputs as wires
reg clk, rst;
reg[7:0] data;
reg dataReady;
reg txBusy;
wire txStart;
wire[7:0] txData;
uart_tx_buffer U0(
.clk(clk),
.rst(rst),
.data(data),
.dataReady(dataReady),
.txBusy(txBusy),
.txStart(txStart),
.txData(txData),
.empty(empty),
.full(full)
);
// Initialize all variables
initial begin
$monitor ("clk=%b data=%b dataReady=%b txBusy=%b txStart=%b txData=%b",
clk, data, dataReady, txBusy, txStart, txData);
clk = 1;
rst = 1;
data = 0;
dataReady = 0;
txBusy = 0;
#2
rst = 0;
#2
data = 8'b01000001; // A
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01000010; // B
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01000011; // C
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01000100; // D
dataReady = 1;
txBusy = 1;
#2
dataReady = 0;
#2
data = 8'b01000101; // E
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01000110; // F
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01000111; // G
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01001000; // H
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01001001; // I
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
#2
data = 8'b01001010; // J
dataReady = 1;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#2
dataReady = 0;
txBusy = 0;
#10
$stop; // Terminate simulation
end
always begin
#1 clk = !clk;
end
endmodule
|
// Top Module of CHIPPER Router
`include "globalVariable.v"
module Top (inPortE, inPortW, inPortN, inPortS, inPortLocal, injectReq, clk, reset, inPG, inWU, outPortE, outPortW, outPortN, outPortS, outPortLocal, injectGrant, outPG, outWU);
input [`CHANNEL_SIZE-1:0] inPortE, inPortW, inPortN, inPortS,inPortLocal;
input clk, reset,injectReq;
input [3:0] inPG, inWU;
output reg [`CHANNEL_SIZE-1:0] outPortE, outPortW, outPortN, outPortS,outPortLocal;
output injectGrant;
output [3:0] outPG, outWU;
wire [`COORDINATE_SIZE-1:0] CURRENT_POSITION = {`CURRENT_POSITION_X,`CURRENT_POSITION_Y};
wire [`COORDINATE_SIZE+`PKTID_SIZE-1:0] counterGolden;
wire [`IN_ROUTER_SIZE-1:0] inRouterFlit [3:0];
wire [`IN_ROUTER_SIZE-1:0] inj2PipelineLatch [3:0];
wire [3:0] valid;
wire [3:0] validArrival;
wire [3:0] productiveVector;
wire [3:0] portPGTypeVector;
wire pgEnable;
wire [4*`PORT_STAT_SIZE-1:0] portStatus;
wire [`PORT_STAT_SIZE-1:0] wPortStatus [3:0];
wire [`PG_ROUTER_LOAD_SIZE-1:0] routerLoad;
wire [4*`PG_PORT_LOAD_SIZE-1:0] portLoad; // [S, N, W, E]
wire [`PG_PORT_LOAD_SIZE-1:0] wPortLoad [3:0]; // [S, N, W, E]
genvar i;
goldenCounter goldenCounter (reset, clk, counterGolden);
pgCounter pgCounter(clk, reset, pgEnable);
loadTrack loadTrack(reset, clk, validArrival, productiveVector, pgEnable, portStatus, routerLoad, portLoad);
portPGLevel portPGLevel(reset, pgEnable, routerLoad, portPGTypeVector);
generate
for (i=0;i<4;i=i+1)
begin : generate1
// Split the bus
assign validArrival[i] = inRouterFlit[i][`VALID];
assign productiveVector[i] = inRouterFlit[0][`PROD_VECTOR_EAST+i]&inRouterFlit[1][`PROD_VECTOR_EAST+i]&inRouterFlit[2][`PROD_VECTOR_EAST+i]&inRouterFlit[3][`PROD_VECTOR_EAST+i];
assign wPortLoad[i] = portLoad[i*`PG_PORT_LOAD_SIZE+:`PG_PORT_LOAD_SIZE];
// PG each data channel
fsmPG fsmPG(clk, reset, portPGTypeVector[i], wPortLoad[i], pgEnable, inPG[i], inWU[i], wPortStatus[i], outPG[i], outWU[i]);
// aggregate the bus segment
assign portStatus[i*`PORT_STAT_SIZE+:`PORT_STAT_SIZE] = wPortStatus[i];
end
endgenerate
reg [`CHANNEL_SIZE-1:0] inPort [4:0];
// input latch
always @ (posedge clk or negedge reset) begin
if (~reset) begin
inPort[0] <= 0;
inPort[1] <= 0;
inPort[2] <= 0;
inPort[3] <= 0;
inPort[4] <= 0;
end
else begin
inPort[0] <= inPortE;
inPort[1] <= inPortW;
inPort[2] <= inPortN;
inPort[3] <= inPortS;
inPort[4] <= inPortLocal;
end
end
generate
for (i=0;i<3'd4;i=i+1)
begin : generate2
routerComputation RC (
.flit (inPort[i]),
.CURRENT_POSITION (CURRENT_POSITION),
.counterGolden (counterGolden),
.PORT_INDEX (i[2:0]),
.inRouterFlit (inRouterFlit[i])
);
end
endgenerate
wire [`IN_ROUTER_SIZE-1:0] winningFlit;
ejectTree ejectTree(
.flit0 (inRouterFlit[2]),
.flit1 (inRouterFlit[0]),
.flit2 (inRouterFlit[3]),
.flit3 (inRouterFlit[1]),
.winningFlit (winningFlit)
);
generate
for (i=0;i<4;i=i+1)
begin : generate3
ejectKill ejectKill(
.portIndex (inRouterFlit[i][`PORT_TAG]),
.winnerPort (winningFlit[`PORT_TAG]),
.validIn (inRouterFlit[i][`VALID]),
.winnerValid (winningFlit[`VALID]),
.validOut (valid[i]) // check if there is any racing
);
end
endgenerate
wire [3:0] grant; // inject channel selection
injectArb injectArb(
.valid (valid),
.injectReq (injectReq),
.portStatus (portStatus),
.injectGrant (injectGrant),
.grant (grant)
);
wire [`IN_ROUTER_SIZE-1:0] inRouterFlitLocal;
routerComputation RCLocal (
.flit (inPort[4]),
.CURRENT_POSITION (CURRENT_POSITION),
.counterGolden (counterGolden),
.PORT_INDEX (3'b100),
.inRouterFlit (inRouterFlitLocal)
);
generate
for (i=0;i<4;i=i+1)
begin : generate4
mux2to1InRouter Inject (
.aIn ({valid[i],inRouterFlit[i][`IN_ROUTER_SIZE-2:0]}),
.bIn (inRouterFlitLocal),
.sel (grant[i]),
.dataOut (inj2PipelineLatch[i])
);
end
endgenerate
reg [`IN_ROUTER_SIZE-1:0] pipelineLatch [3:0];
always @ (posedge clk or negedge reset) begin
if (~reset) begin
pipelineLatch[0] <= 0;
pipelineLatch[1] <= 0;
pipelineLatch[2] <= 0;
pipelineLatch[3] <= 0;
outPortLocal <= 0;
end
else begin
pipelineLatch[0] <= inj2PipelineLatch[0];
pipelineLatch[1] <= inj2PipelineLatch[1];
pipelineLatch[2] <= inj2PipelineLatch[2];
pipelineLatch[3] <= inj2PipelineLatch[3];
outPortLocal <= winningFlit;
end
end
wire [`IN_ROUTER_SIZE-1:0] w_outPort [3:0];
permutationNetwork permutationNetwork(
.inFlitE (pipelineLatch[0]),
.inFlitW (pipelineLatch[1]),
.inFlitN (pipelineLatch[2]),
.inFlitS (pipelineLatch[3]),
.portStatus (portStatus),
.outFlitE (w_outPort[0]),
.outFlitW (w_outPort[1]),
.outFlitN (w_outPort[2]),
.outFlitS (w_outPort[3])
);
always @ (posedge clk or negedge reset) begin
if (~reset) begin
outPortE <= 0;
outPortW <= 0;
outPortN <= 0;
outPortS <= 0;
end
else begin
outPortE <= w_outPort[0][`CHANNEL_SIZE-1:0];
outPortW <= w_outPort[1][`CHANNEL_SIZE-1:0];
outPortN <= w_outPort[2][`CHANNEL_SIZE-1:0];
outPortS <= w_outPort[3][`CHANNEL_SIZE-1:0];
end
end
endmodule
|
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_ps2, input_i2c, input_switches, input_eth_rx, input_buttons, input_timer_stb, input_rs232_rx_stb, input_ps2_stb, input_i2c_stb, input_switches_stb, input_eth_rx_stb, input_buttons_stb, input_timer_ack, input_rs232_rx_ack, input_ps2_ack, input_i2c_ack, input_switches_ack, input_eth_rx_ack, input_buttons_ack, output_seven_segment_annode, output_eth_tx, output_rs232_tx, output_leds, output_audio, output_led_g, output_seven_segment_cathode, output_led_b, output_i2c, output_vga, output_led_r, output_seven_segment_annode_stb, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_audio_stb, output_led_g_stb, output_seven_segment_cathode_stb, output_led_b_stb, output_i2c_stb, output_vga_stb, output_led_r_stb, output_seven_segment_annode_ack, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack, output_audio_ack, output_led_g_ack, output_seven_segment_cathode_ack, output_led_b_ack, output_i2c_ack, output_vga_ack, output_led_r_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
input [31:0] input_i2c;
input input_i2c_stb;
output input_i2c_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
output [31:0] output_seven_segment_annode;
output output_seven_segment_annode_stb;
input output_seven_segment_annode_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_audio;
output output_audio_stb;
input output_audio_ack;
output [31:0] output_led_g;
output output_led_g_stb;
input output_led_g_ack;
output [31:0] output_seven_segment_cathode;
output output_seven_segment_cathode_stb;
input output_seven_segment_cathode_ack;
output [31:0] output_led_b;
output output_led_b_stb;
input output_led_b_ack;
output [31:0] output_i2c;
output output_i2c_stb;
input output_i2c_ack;
output [31:0] output_vga;
output output_vga_stb;
input output_vga_ack;
output [31:0] output_led_r;
output output_led_r_stb;
input output_led_r_ack;
wire exception_139931267303256;
wire exception_139931269149616;
wire exception_139931271097088;
wire exception_139931269435904;
wire exception_139931283888464;
wire exception_139931281193296;
wire exception_139931279228296;
wire exception_139931268839760;
wire exception_139931275005104;
wire exception_139931279977360;
wire exception_139931285101240;
wire exception_139931282853112;
wire exception_139931270883088;
wire exception_139931277530680;
wire exception_139931274790312;
wire exception_139931284813728;
wire exception_139931269227152;
wire exception_139931272276880;
main_0 main_0_139931267303256(
.clk(clk),
.rst(rst),
.exception(exception_139931267303256),
.output_leds(output_leds),
.output_leds_stb(output_leds_stb),
.output_leds_ack(output_leds_ack));
main_1 main_1_139931269149616(
.clk(clk),
.rst(rst),
.exception(exception_139931269149616),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_2 main_2_139931271097088(
.clk(clk),
.rst(rst),
.exception(exception_139931271097088),
.input_in(input_rs232_rx),
.input_in_stb(input_rs232_rx_stb),
.input_in_ack(input_rs232_rx_ack));
main_3 main_3_139931269435904(
.clk(clk),
.rst(rst),
.exception(exception_139931269435904),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_4 main_4_139931283888464(
.clk(clk),
.rst(rst),
.exception(exception_139931283888464),
.input_in(input_i2c),
.input_in_stb(input_i2c_stb),
.input_in_ack(input_i2c_ack));
main_5 main_5_139931281193296(
.clk(clk),
.rst(rst),
.exception(exception_139931281193296),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_6 main_6_139931279228296(
.clk(clk),
.rst(rst),
.exception(exception_139931279228296),
.input_in(input_eth_rx),
.input_in_stb(input_eth_rx_stb),
.input_in_ack(input_eth_rx_ack));
main_7 main_7_139931268839760(
.clk(clk),
.rst(rst),
.exception(exception_139931268839760),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_8 main_8_139931275005104(
.clk(clk),
.rst(rst),
.exception(exception_139931275005104),
.output_out(output_seven_segment_annode),
.output_out_stb(output_seven_segment_annode_stb),
.output_out_ack(output_seven_segment_annode_ack));
main_9 main_9_139931279977360(
.clk(clk),
.rst(rst),
.exception(exception_139931279977360),
.output_out(output_eth_tx),
.output_out_stb(output_eth_tx_stb),
.output_out_ack(output_eth_tx_ack));
main_10 main_10_139931285101240(
.clk(clk),
.rst(rst),
.exception(exception_139931285101240),
.output_out(output_rs232_tx),
.output_out_stb(output_rs232_tx_stb),
.output_out_ack(output_rs232_tx_ack));
main_11 main_11_139931282853112(
.clk(clk),
.rst(rst),
.exception(exception_139931282853112),
.output_out(output_audio),
.output_out_stb(output_audio_stb),
.output_out_ack(output_audio_ack));
main_12 main_12_139931270883088(
.clk(clk),
.rst(rst),
.exception(exception_139931270883088),
.output_out(output_led_g),
.output_out_stb(output_led_g_stb),
.output_out_ack(output_led_g_ack));
main_13 main_13_139931277530680(
.clk(clk),
.rst(rst),
.exception(exception_139931277530680),
.output_out(output_seven_segment_cathode),
.output_out_stb(output_seven_segment_cathode_stb),
.output_out_ack(output_seven_segment_cathode_ack));
main_14 main_14_139931274790312(
.clk(clk),
.rst(rst),
.exception(exception_139931274790312),
.output_out(output_led_b),
.output_out_stb(output_led_b_stb),
.output_out_ack(output_led_b_ack));
main_15 main_15_139931284813728(
.clk(clk),
.rst(rst),
.exception(exception_139931284813728),
.output_out(output_i2c),
.output_out_stb(output_i2c_stb),
.output_out_ack(output_i2c_ack));
main_16 main_16_139931269227152(
.clk(clk),
.rst(rst),
.exception(exception_139931269227152),
.output_out(output_vga),
.output_out_stb(output_vga_stb),
.output_out_ack(output_vga_ack));
main_17 main_17_139931272276880(
.clk(clk),
.rst(rst),
.exception(exception_139931272276880),
.output_out(output_led_r),
.output_out_stb(output_led_r_stb),
.output_out_ack(output_led_r_ack));
assign exception = exception_139931267303256 || exception_139931269149616 || exception_139931271097088 || exception_139931269435904 || exception_139931283888464 || exception_139931281193296 || exception_139931279228296 || exception_139931268839760 || exception_139931275005104 || exception_139931279977360 || exception_139931285101240 || exception_139931282853112 || exception_139931270883088 || exception_139931277530680 || exception_139931274790312 || exception_139931284813728 || exception_139931269227152 || exception_139931272276880;
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_mgmt #(
parameter sdram_depth = 26,
parameter sdram_columndepth = 9
) (
input sys_clk,
input sdram_rst,
input [2:0] tim_rp,
input [2:0] tim_rcd,
input [10:0] tim_refi,
input [3:0] tim_rfc,
input stb,
input we,
input [sdram_depth-3-1:0] address, /* in 64-bit words */
output reg ack,
output reg read,
output reg write,
output [3:0] concerned_bank,
input read_safe,
input write_safe,
input [3:0] precharge_safe,
output sdram_cs_n,
output sdram_we_n,
output sdram_cas_n,
output sdram_ras_n,
output [12:0] sdram_adr,
output [1:0] sdram_ba
);
/*
* Address Mapping :
* | ROW ADDRESS | BANK NUMBER | COL ADDRESS | for 32-bit words
* |depth-1 coldepth+2|coldepth+1 coldepth|coldepth-1 0|
* (depth for 32-bit words, which is sdram_depth-2)
*/
parameter rowdepth = sdram_depth-2-1-(sdram_columndepth+2)+1;
wire [sdram_depth-2-1:0] address32 = {address, 1'b0};
wire [sdram_columndepth-1:0] col_address = address32[sdram_columndepth-1:0];
wire [1:0] bank_address = address32[sdram_columndepth+1:sdram_columndepth];
wire [rowdepth-1:0] row_address = address32[sdram_depth-2-1:sdram_columndepth+2];
reg [3:0] bank_address_onehot;
always @(*) begin
case(bank_address)
2'b00: bank_address_onehot <= 4'b0001;
2'b01: bank_address_onehot <= 4'b0010;
2'b10: bank_address_onehot <= 4'b0100;
2'b11: bank_address_onehot <= 4'b1000;
endcase
end
/* Track open rows */
reg [3:0] has_openrow;
reg [rowdepth-1:0] openrows[0:3];
reg [3:0] track_close;
reg [3:0] track_open;
always @(posedge sys_clk) begin
if(sdram_rst) begin
has_openrow = 4'h0;
end else begin
has_openrow = (has_openrow | track_open) & ~track_close;
if(track_open[0]) openrows[0] <= row_address;
if(track_open[1]) openrows[1] <= row_address;
if(track_open[2]) openrows[2] <= row_address;
if(track_open[3]) openrows[3] <= row_address;
end
end
/* Bank precharge safety */
assign concerned_bank = bank_address_onehot;
wire current_precharge_safe =
(precharge_safe[0] | ~bank_address_onehot[0])
&(precharge_safe[1] | ~bank_address_onehot[1])
&(precharge_safe[2] | ~bank_address_onehot[2])
&(precharge_safe[3] | ~bank_address_onehot[3]);
/* Check for page hits */
wire bank_open = has_openrow[bank_address];
wire page_hit = bank_open & (openrows[bank_address] == row_address);
/* Address drivers */
reg sdram_adr_loadrow;
reg sdram_adr_loadcol;
reg sdram_adr_loadA10;
assign sdram_adr =
({13{sdram_adr_loadrow}} & row_address)
|({13{sdram_adr_loadcol}} & col_address)
|({13{sdram_adr_loadA10}} & 13'd1024);
assign sdram_ba = bank_address;
/* Command drivers */
reg sdram_cs;
reg sdram_we;
reg sdram_cas;
reg sdram_ras;
assign sdram_cs_n = ~sdram_cs;
assign sdram_we_n = ~sdram_we;
assign sdram_cas_n = ~sdram_cas;
assign sdram_ras_n = ~sdram_ras;
/* Timing counters */
/* The number of clocks we must wait following a PRECHARGE command (usually tRP). */
reg [2:0] precharge_counter;
reg reload_precharge_counter;
wire precharge_done = (precharge_counter == 3'd0);
always @(posedge sys_clk) begin
if(reload_precharge_counter)
precharge_counter <= tim_rp;
else if(~precharge_done)
precharge_counter <= precharge_counter - 3'd1;
end
/* The number of clocks we must wait following an ACTIVATE command (usually tRCD). */
reg [2:0] activate_counter;
reg reload_activate_counter;
wire activate_done = (activate_counter == 3'd0);
always @(posedge sys_clk) begin
if(reload_activate_counter)
activate_counter <= tim_rcd;
else if(~activate_done)
activate_counter <= activate_counter - 3'd1;
end
/* The number of clocks we have left before we must refresh one row in the SDRAM array (usually tREFI). */
reg [10:0] refresh_counter;
reg reload_refresh_counter;
wire must_refresh = refresh_counter == 11'd0;
always @(posedge sys_clk) begin
if(sdram_rst)
refresh_counter <= 11'd0;
else begin
if(reload_refresh_counter)
refresh_counter <= tim_refi;
else if(~must_refresh)
refresh_counter <= refresh_counter - 11'd1;
end
end
/* The number of clocks we must wait following an AUTO REFRESH command (usually tRFC). */
reg [3:0] autorefresh_counter;
reg reload_autorefresh_counter;
wire autorefresh_done = (autorefresh_counter == 4'd0);
always @(posedge sys_clk) begin
if(reload_autorefresh_counter)
autorefresh_counter <= tim_rfc;
else if(~autorefresh_done)
autorefresh_counter <= autorefresh_counter - 4'd1;
end
/* FSM that pushes commands into the SDRAM */
reg [3:0] state;
reg [3:0] next_state;
parameter IDLE = 4'd0;
parameter ACTIVATE = 4'd1;
parameter READ = 4'd2;
parameter WRITE = 4'd3;
parameter PRECHARGEALL = 4'd4;
parameter AUTOREFRESH = 4'd5;
parameter AUTOREFRESH_WAIT = 4'd6;
always @(posedge sys_clk) begin
if(sdram_rst)
state <= IDLE;
else begin
//$display("state: %d -> %d", state, next_state);
state <= next_state;
end
end
always @(*) begin
next_state = state;
reload_precharge_counter = 1'b0;
reload_activate_counter = 1'b0;
reload_refresh_counter = 1'b0;
reload_autorefresh_counter = 1'b0;
sdram_cs = 1'b0;
sdram_we = 1'b0;
sdram_cas = 1'b0;
sdram_ras = 1'b0;
sdram_adr_loadrow = 1'b0;
sdram_adr_loadcol = 1'b0;
sdram_adr_loadA10 = 1'b0;
track_close = 4'b0000;
track_open = 4'b0000;
read = 1'b0;
write = 1'b0;
ack = 1'b0;
case(state)
IDLE: begin
if(must_refresh)
next_state = PRECHARGEALL;
else begin
if(stb) begin
if(page_hit) begin
if(we) begin
if(write_safe) begin
/* Write */
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b1;
sdram_adr_loadcol = 1'b1;
write = 1'b1;
ack = 1'b1;
end
end else begin
if(read_safe) begin
/* Read */
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b0;
sdram_adr_loadcol = 1'b1;
read = 1'b1;
ack = 1'b1;
end
end
end else begin
if(bank_open) begin
if(current_precharge_safe) begin
/* Precharge Bank */
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b1;
track_close = bank_address_onehot;
reload_precharge_counter = 1'b1;
next_state = ACTIVATE;
end
end else begin
/* Activate */
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b0;
sdram_adr_loadrow = 1'b1;
track_open = bank_address_onehot;
reload_activate_counter = 1'b1;
if(we)
next_state = WRITE;
else
next_state = READ;
end
end
end
end
end
ACTIVATE: begin
if(precharge_done) begin
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b0;
sdram_adr_loadrow = 1'b1;
track_open = bank_address_onehot;
reload_activate_counter = 1'b1;
if(we)
next_state = WRITE;
else
next_state = READ;
end
end
READ: begin
if(activate_done) begin
if(read_safe) begin
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b0;
sdram_adr_loadcol = 1'b1;
read = 1'b1;
ack = 1'b1;
next_state = IDLE;
end
end
end
WRITE: begin
if(activate_done) begin
if(write_safe) begin
sdram_cs = 1'b1;
sdram_ras = 1'b0;
sdram_cas = 1'b1;
sdram_we = 1'b1;
sdram_adr_loadcol = 1'b1;
write = 1'b1;
ack = 1'b1;
next_state = IDLE;
end
end
end
PRECHARGEALL: begin
if(precharge_safe == 4'b1111) begin
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b0;
sdram_we = 1'b1;
sdram_adr_loadA10 = 1'b1;
reload_precharge_counter = 1'b1;
track_close = 4'b1111;
next_state = AUTOREFRESH;
end
end
AUTOREFRESH: begin
if(precharge_done) begin
sdram_cs = 1'b1;
sdram_ras = 1'b1;
sdram_cas = 1'b1;
sdram_we = 1'b0;
reload_refresh_counter = 1'b1;
reload_autorefresh_counter = 1'b1;
next_state = AUTOREFRESH_WAIT;
end
end
AUTOREFRESH_WAIT: begin
if(autorefresh_done)
next_state = IDLE;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBE_P_8_V
`define SKY130_FD_SC_HVL__PROBE_P_8_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog wrapper for probe_p with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__probe_p.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__probe_p_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__probe_p base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__probe_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__probe_p base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBE_P_8_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:30:52 01/30/2011
// Design Name: MiniAlu
// Module Name: D:/Proyecto/RTL/Dev/MiniALU/TestBench.v
// Project Name: MiniALU
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MiniAlu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestBench;
// Inputs
reg Clock;
reg Reset;
// Outputs
wire [7:0] oLed;
// Instantiate the Unit Under Test (UUT)
MiniAlu uut (
.Clock(Clock),
.Reset(Reset),
.oLed(oLed)
);
always
begin
#5 Clock = ! Clock;
end
initial begin
// Initialize Inputs
Clock = 0;
Reset = 0;
// Wait 100 ns for global reset to finish
#100;
Reset = 1;
#50;
Reset = 0;
// Add stimulus here
end
endmodule
|
module EX_MEM_Seg(
input Clk,
input stall,
input flush,
input [31:0] Branch_addr,PC_add,
input [2:0] Condition,
input Branch,
input [2:0]PC_write,
input [3:0]Mem_Byte_Write,Rd_Write_Byte_en,
input MemWBSrc,OverflowEn,
input [31:0] MemData,WBData,
input Less,Zero,Overflow,
input [4:0]Rd,
output reg [31:0] Branch_addr_out,PC_add_out,
output reg [2:0] Condition_out,
output reg Branch_out,
output reg [2:0]PC_write_out,
output reg [3:0]Mem_Byte_Write_out,Rd_Write_Byte_en_out,
output reg MemWBSrc_out,OverflowEn_out,
output reg [31:0] MemData_out,WBData_out,
output reg Less_out,Zero_out,Overflow_out,
output reg [4:0]Rd_out
);
always@(posedge Clk)
begin
if(flush)
begin
OverflowEn_out <= 1'b0;
Branch_addr_out <= 32'b0;
PC_add_out <= 32'b0;
Condition_out <= 3'b0;
Branch_out <= 1'b0;
PC_write_out =3'b0;
Mem_Byte_Write_out <= 4'b0;
Rd_Write_Byte_en_out <= 4'b0;
MemWBSrc_out <= 1'b0;
MemData_out <= 32'h0;
WBData_out <= 32'b0;
Less_out <= 1'b0;
Zero_out <= 1'b0;
Overflow_out <= 1'b0;
Rd_out <= 5'b0;
end
else if(~stall)
begin
OverflowEn_out <= OverflowEn;
Branch_addr_out <= Branch_addr;
PC_add_out <= PC_add;
Condition_out <= Condition;
Branch_out <= Branch;
PC_write_out = PC_write;
Mem_Byte_Write_out <= Mem_Byte_Write;
Rd_Write_Byte_en_out <= Rd_Write_Byte_en;
MemWBSrc_out <= MemWBSrc;
MemData_out <= MemData;
WBData_out <= WBData;
Less_out <= Less;
Zero_out <= Zero;
Overflow_out <= Overflow;
Rd_out <= Rd;
end
end
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// Terasic DE0 Nano SoC (Cyclone V SoC) Development Board
//
module de0_nano_soc
(
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
input [1:0] BUTTON,
input [3:0] SW,
output [7:0] LED,
output UART_TX,
input UART_RX,
output SPDR_TX,
input SPDR_RX
);
wire clk_50 = FPGA_CLK1_50;
wire clk_slow = FPGA_CLK2_50;
wire fpga_reset_n = BUTTON[0]; // NOTE: Debounced on board
wire irom_cs;
wire [23:0] irom_addr;
wire [31:0] irom_data;
irom irom
(
.clk(clk_50),
.addr(irom_addr),
.cs(irom_cs),
.dout(irom_data)
);
wire [31:0] dram_addr;
wire dram_cs;
wire dram_wr;
wire [3:0] dram_mask;
wire [31:0] dram_din;
wire [31:0] dram_dout;
dram dram
(
.clk(clk_50),
.addr(dram_addr),
.cs(dram_cs),
.wr(dram_wr),
.mask(dram_mask),
.din(dram_din),
.dout(dram_dout)
);
wire [68:0] rcn_00;
wire [68:0] rcn_01;
wire [68:0] rcn_02;
wire [68:0] rcn_03;
wire [68:0] rcn_04;
tawas #(.MASTER_ID(0)) tawas
(
.clk(clk_50),
.rst(!fpga_reset_n),
.ics(irom_cs),
.iaddr(irom_addr),
.idata(irom_data),
.dcs(dram_cs),
.dwr(dram_wr),
.daddr(dram_addr),
.dmask(dram_mask),
.dout(dram_din),
.din(dram_dout),
.rcn_in(rcn_00),
.rcn_out(rcn_01)
);
wire [31:0] test_progress;
wire [31:0] test_fail;
wire [31:0] test_pass;
rcn_testregs #(.ADDR_BASE(24'hFFFFF0)) testregs
(
.clk(clk_50),
.rst(!fpga_reset_n),
.test_progress(),
.test_progress(),
.test_pass(),
.rcn_in(rcn_01),
.rcn_out(rcn_02)
);
rcn_ram #(.ADDR_BASE(24'hFE0000)) sram_0
(
.clk(clk_50),
.rst(!fpga_reset_n),
.rcn_in(rcn_02),
.rcn_out(rcn_03)
);
wire uart_tx_req;
wire uart_rx_req;
rcn_uart #(.ADDR_BASE(24'hFFFFB8)) uart
(
.clk(clk_50),
.clk_50(clk_50),
.rst(!fpga_reset_n),
.rcn_in(rcn_03),
.rcn_out(rcn_04),
.tx_req(uart_tx_req),
.rx_req(uart_rx_req),
.uart_tx(UART_TX),
.uart_rx(UART_RX)
);
wire [68:0] rcn_20;
wire [68:0] rcn_21;
wire [68:0] rcn_22;
rcn_bridge_async #(.ID_MASK(6'h3C), .ID_BASE(6'h08),
.ADDR_MASK(24'hF00000), .ADDR_BASE(24'h100000)) bridge
(
.main_clk(clk_50),
.main_rst(!fpga_reset_n),
.sub_clk(clk_slow),
.main_rcn_in(rcn_04),
.main_rcn_out(rcn_00),
.sub_rcn_in(rcn_20),
.sub_rcn_out(rcn_21)
);
wire [31:0] spdr_gpo;
assign LED[7:0] = spdr_gpo[7:0];
rcn_spdr #(.MASTER_ID(9)) spdr
(
.clk(clk_slow),
.clk_50(clk_50),
.rst(!fpga_reset_n),
.rcn_in(rcn_21),
.rcn_out(rcn_22),
.gpi({28'd0, SW[3:0]}),
.gpi_strobe(),
.gpo(spdr_gpo),
.gpo_strobe(),
.uart_tx(SPDR_TX),
.uart_rx(SPDR_RX)
);
rcn_dma #(.ADDR_BASE(24'h1FFFC0), .MASTER_ID(8)) dma
(
.clk(clk_slow),
.rst(!fpga_reset_n),
.rcn_in(rcn_22),
.rcn_out(rcn_20),
.req({uart_rx_req, uart_tx_req, 14'd1}),
.done()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__HA_BLACKBOX_V
`define SKY130_FD_SC_MS__HA_BLACKBOX_V
/**
* ha: Half adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__ha (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__HA_BLACKBOX_V
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_phy_ctl_io.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Thu Aug 24 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module puts the memory control signals like address, bank address,
// row address strobe, column address strobe, write enable and clock enable
// in the IOBs.
//Reference:
//Revision History:
// Rev 1.1 - To fix CR 540201, S attribute is added for CS, CKE and ODT
// module (FDCPE) instances. PK. 01/08/10
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_phy_ctl_io #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_36_1 module. Please refer to
// the mig_36_1 module for actual values.
parameter BANK_WIDTH = 2,
parameter CKE_WIDTH = 1,
parameter COL_WIDTH = 10,
parameter CS_NUM = 1,
parameter TWO_T_TIME_EN = 0,
parameter CS_WIDTH = 1,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 14,
parameter DDR_TYPE = 1
)
(
input clk0,
input clk90,
input rst0,
input rst90,
input [ROW_WIDTH-1:0] ctrl_addr,
input [BANK_WIDTH-1:0] ctrl_ba,
input ctrl_ras_n,
input ctrl_cas_n,
input ctrl_we_n,
input [CS_NUM-1:0] ctrl_cs_n,
input [ROW_WIDTH-1:0] phy_init_addr,
input [BANK_WIDTH-1:0] phy_init_ba,
input phy_init_ras_n,
input phy_init_cas_n,
input phy_init_we_n,
input [CS_NUM-1:0] phy_init_cs_n,
input [CKE_WIDTH-1:0] phy_init_cke,
input phy_init_data_sel,
input [CS_NUM-1:0] odt,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_ras_n,
output ddr_cas_n,
output ddr_we_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH-1:0] ddr_cs_n,
output [ODT_WIDTH-1:0] ddr_odt
);
reg [ROW_WIDTH-1:0] addr_mux;
reg [BANK_WIDTH-1:0] ba_mux;
reg cas_n_mux;
reg [CS_NUM-1:0] cs_n_mux;
reg ras_n_mux;
reg we_n_mux;
//***************************************************************************
// MUX to choose from either PHY or controller for SDRAM control
generate // in 2t timing mode the extra register stage cannot be used.
if(TWO_T_TIME_EN) begin // the control signals are asserted for two cycles
always @(*)begin
if (phy_init_data_sel) begin
addr_mux = ctrl_addr;
ba_mux = ctrl_ba;
cas_n_mux = ctrl_cas_n;
cs_n_mux = ctrl_cs_n;
ras_n_mux = ctrl_ras_n;
we_n_mux = ctrl_we_n;
end else begin
addr_mux = phy_init_addr;
ba_mux = phy_init_ba;
cas_n_mux = phy_init_cas_n;
cs_n_mux = phy_init_cs_n;
ras_n_mux = phy_init_ras_n;
we_n_mux = phy_init_we_n;
end
end
end else begin
always @(posedge clk0)begin // register the signals in non 2t mode
if (phy_init_data_sel) begin
addr_mux <= ctrl_addr;
ba_mux <= ctrl_ba;
cas_n_mux <= ctrl_cas_n;
cs_n_mux <= ctrl_cs_n;
ras_n_mux <= ctrl_ras_n;
we_n_mux <= ctrl_we_n;
end else begin
addr_mux <= phy_init_addr;
ba_mux <= phy_init_ba;
cas_n_mux <= phy_init_cas_n;
cs_n_mux <= phy_init_cs_n;
ras_n_mux <= phy_init_ras_n;
we_n_mux <= phy_init_we_n;
end
end
end
endgenerate
//***************************************************************************
// Output flop instantiation
// NOTE: Make sure all control/address flops are placed in IOBs
//***************************************************************************
// RAS: = 1 at reset
(* IOB = "FORCE" *) FDCPE u_ff_ras_n
(
.Q (ddr_ras_n),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (ras_n_mux),
.PRE (rst0)
) /* synthesis syn_useioff = 1 */;
// CAS: = 1 at reset
(* IOB = "FORCE" *) FDCPE u_ff_cas_n
(
.Q (ddr_cas_n),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (cas_n_mux),
.PRE (rst0)
) /* synthesis syn_useioff = 1 */;
// WE: = 1 at reset
(* IOB = "FORCE" *) FDCPE u_ff_we_n
(
.Q (ddr_we_n),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (we_n_mux),
.PRE (rst0)
) /* synthesis syn_useioff = 1 */;
// CKE: = 0 at reset
genvar cke_i;
generate
for (cke_i = 0; cke_i < CKE_WIDTH; cke_i = cke_i + 1) begin: gen_cke
(* IOB = "FORCE" *) (* S = "TRUE" *) FDCPE u_ff_cke
(
.Q (ddr_cke[cke_i]),
.C (clk0),
.CE (1'b1),
.CLR (rst0),
.D (phy_init_cke[cke_i]),
.PRE (1'b0)
) /* synthesis syn_useioff = 1 */;
end
endgenerate
// chip select: = 1 at reset
// For unbuffered dimms the loading will be high. The chip select
// can be asserted early if the loading is very high. The
// code as is uses clock 0. If needed clock 270 can be used to
// toggle chip select 1/4 clock cycle early. The code has
// the clock 90 input for the early assertion of chip select.
genvar cs_i;
generate
for(cs_i = 0; cs_i < CS_WIDTH; cs_i = cs_i + 1) begin: gen_cs_n
if(TWO_T_TIME_EN) begin
(* IOB = "FORCE" *) (* S = "TRUE" *) FDCPE u_ff_cs_n
(
.Q (ddr_cs_n[cs_i]),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (cs_n_mux[(cs_i*CS_NUM)/CS_WIDTH]),
.PRE (rst0)
) /* synthesis syn_useioff = 1 */;
end else begin // if (TWO_T_TIME_EN)
(* IOB = "FORCE" *) (* S = "TRUE" *) FDCPE u_ff_cs_n
(
.Q (ddr_cs_n[cs_i]),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (cs_n_mux[(cs_i*CS_NUM)/CS_WIDTH]),
.PRE (rst0)
) /* synthesis syn_useioff = 1 */;
end // else: !if(TWO_T_TIME_EN)
end
endgenerate
// address: = X at reset
genvar addr_i;
generate
for (addr_i = 0; addr_i < ROW_WIDTH; addr_i = addr_i + 1) begin: gen_addr
(* IOB = "FORCE" *) FDCPE u_ff_addr
(
.Q (ddr_addr[addr_i]),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (addr_mux[addr_i]),
.PRE (1'b0)
) /* synthesis syn_useioff = 1 */;
end
endgenerate
// bank address = X at reset
genvar ba_i;
generate
for (ba_i = 0; ba_i < BANK_WIDTH; ba_i = ba_i + 1) begin: gen_ba
(* IOB = "FORCE" *) FDCPE u_ff_ba
(
.Q (ddr_ba[ba_i]),
.C (clk0),
.CE (1'b1),
.CLR (1'b0),
.D (ba_mux[ba_i]),
.PRE (1'b0)
) /* synthesis syn_useioff = 1 */;
end
endgenerate
// ODT control = 0 at reset
genvar odt_i;
generate
if (DDR_TYPE > 0) begin: gen_odt_ddr2
for (odt_i = 0; odt_i < ODT_WIDTH; odt_i = odt_i + 1) begin: gen_odt
(* IOB = "FORCE" *) (* S = "TRUE" *) FDCPE u_ff_odt
(
.Q (ddr_odt[odt_i]),
.C (clk0),
.CE (1'b1),
.CLR (rst0),
.D (odt[(odt_i*CS_NUM)/ODT_WIDTH]),
.PRE (1'b0)
) /* synthesis syn_useioff = 1 */;
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_4_V
`define SKY130_FD_SC_HD__NOR4B_4_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A21O_BEHAVIORAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_BEHAVIORAL_PP_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module lpddr2_cntrlr_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe (probe_input),
.source ()
// synopsys translate_off
,
.clr (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
iss_probe_inst.enable_metastability = "NO",
iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH,
iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0,
iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_sstl_bscan.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_sstl_bscan(hiz_l ,odt_enable ,odt_enable_mask ,to_core ,
drv_oe ,rcv_in ,data_out ,bso ,oe ,data_in ,mode_ctrl ,bsi ,
clock_dr ,update_dr ,shift_dr );
output odt_enable ;
output to_core ;
output data_out ;
output bso ;
output oe ;
input hiz_l ;
input odt_enable_mask ;
input drv_oe ;
input rcv_in ;
input data_in ;
input mode_ctrl ;
input bsi ;
input clock_dr ;
input update_dr ;
input shift_dr ;
supply0 vss ;
wire bso_1 ;
wire bso_2 ;
wire bso_3 ;
wire odt_enable_in ;
bw_io_jp_sstl_bscan bscan_input (
.in (rcv_in ),
.update_dr (update_dr ),
.mode_ctl (mode_ctrl ),
.shift_dr (shift_dr ),
.clock_dr (clock_dr ),
.bsr_so (bso_1 ),
.out (to_core ),
.bsr_si (bsi ) );
bw_io_jp_sstl_oebscan bscan_oe (
.bsr_si (bso_3 ),
.update_dr (update_dr ),
.in (drv_oe ),
.bsr_hiz_l (hiz_l ),
.test_mode_oe (vss ),
.mode_ctl (mode_ctrl ),
.shift_dr (shift_dr ),
.clock_dr (clock_dr ),
.out_type (vss ),
.bsr_so (bso ),
.out (oe ) );
bw_u1_nor2_1x odt_nor2 (
.z (odt_enable_in ),
.a (drv_oe ),
.b (odt_enable_mask ) );
bw_io_jp_sstl_bscan bscan_output (
.in (data_in ),
.update_dr (update_dr ),
.mode_ctl (mode_ctrl ),
.shift_dr (shift_dr ),
.clock_dr (clock_dr ),
.bsr_so (bso_3 ),
.out (data_out ),
.bsr_si (bso_2 ) );
bw_io_jp_sstl_oebscan bscan_odt_en (
.bsr_si (bso_1 ),
.update_dr (update_dr ),
.in (odt_enable_in ),
.bsr_hiz_l (hiz_l ),
.test_mode_oe (vss ),
.mode_ctl (mode_ctrl ),
.shift_dr (shift_dr ),
.clock_dr (clock_dr ),
.out_type (vss ),
.bsr_so (bso_2 ),
.out (odt_enable ) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXBP_1_V
`define SKY130_FD_SC_LS__EDFXBP_1_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for edfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__edfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__edfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__edfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__edfxbp_1 (
Q ,
Q_N,
CLK,
D ,
DE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__edfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXBP_1_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's register file inside CPU ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// Instantiation of register file memories ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_rf.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Bugs fixed, coding style changed.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_rf(
// Clock and reset
clk, rst,
// Write i/f
cy_we_i, cy_we_o, supv, wb_freeze, addrw, dataw, we, flushpipe,
// Read i/f
id_freeze, addra, addrb, dataa, datab, rda, rdb,
// Debug
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, du_read
, sp_attack_enable, gpr_written_to, gpr_written_addr, gpr_written_data, sp_exception_comb
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Write i/f
//
input cy_we_i;
output cy_we_o;
input supv;
input wb_freeze;
input [aw-1:0] addrw;
input [dw-1:0] dataw;
input we;
input flushpipe;
//
// Read i/f
//
input id_freeze;
input [aw-1:0] addra;
input [aw-1:0] addrb;
output [dw-1:0] dataa;
output [dw-1:0] datab;
input rda;
input rdb;
//
// SPR access for debugging purposes
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
input du_read;
input [31:0] sp_attack_enable;
output [aw-1:0] gpr_written_addr;
output [dw-1:0] gpr_written_data;
output gpr_written_to;
input sp_exception_comb;
//
// Internal wires and regs
//
wire [dw-1:0] from_rfa;
wire [dw-1:0] from_rfb;
wire [aw-1:0] rf_addra;
wire [aw-1:0] rf_addrw;
wire [dw-1:0] rf_dataw;
wire rf_we;
wire spr_valid;
wire rf_ena;
wire rf_enb;
reg rf_we_allow;
// Logic to restore output on RFA after debug unit has read out via SPR if.
// Problem was that the incorrect output would be on RFA after debug unit
// had read out - this is bad if that output is relied upon by execute
// stage for next instruction. We simply save the last address for rf A and
// and re-read it whenever the SPR select goes low, so we must remember
// the last address and generate a signal for falling edge of SPR cs.
// -- Julius
// Detect falling edge of SPR select
reg spr_du_cs;
wire spr_cs_fe;
// Track RF A's address each time it's enabled
reg [aw-1:0] addra_last;
always @(posedge clk)
if (rf_ena & !(spr_cs_fe | (du_read & spr_cs)))
addra_last <= addra;
always @(posedge clk)
spr_du_cs <= spr_cs & du_read;
assign spr_cs_fe = spr_du_cs & !(spr_cs & du_read);
//
// SPR access is valid when spr_cs is asserted and
// SPR address matches GPR addresses
//
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
//
// SPR data output is always from RF A
//
assign spr_dat_o = from_rfa;
//
// Operand A comes from RF or from saved A register
//
assign dataa = from_rfa;
//
// Operand B comes from RF or from saved B register
//
assign datab = from_rfb;
//
// RF A read address is either from SPRS or normal from CPU control
//
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] :
spr_cs_fe ? addra_last : addra;
//
// RF write address is either from SPRS or normal from CPU control
//
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
assign gpr_written_addr = rf_addrw;
//
// RF write data is either from SPRS or normal from CPU datapath
//
assign rf_dataw = (rf_addrw == 0) ? 32'b0 : (spr_valid & spr_write) ? spr_dat_i : dataw;
assign gpr_written_data = rf_dataw;
//
// RF write enable is either from SPRS or normal from CPU control
//
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE)
rf_we_allow <= 1'b1;
else if (~wb_freeze)
rf_we_allow <= ~flushpipe;
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
assign gpr_written_to = rf_we;
assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
//
// CS RF A asserted when instruction reads operand A and ID stage
// is not stalled
//
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe;
//
// CS RF B asserted when instruction reads operand B and ID stage
// is not stalled
//
assign rf_enb = rdb & ~id_freeze;
`ifdef OR1200_RFRAM_TWOPORT
//
// Instantiation of register file two-port RAM A
//
or1200_tpram_32x32 rf_a(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_ena),
.we_a(1'b0),
.oe_a(1'b1),
.addr_a(rf_addra),
.di_a(32'h0000_0000),
.do_a(from_rfa),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we & ~sp_exception_comb),
.we_b(rf_we & ~sp_exception_comb),
.oe_b(1'b0),
.addr_b(rf_addrw),
.di_b(rf_dataw),
.do_b()
);
//
// Instantiation of register file two-port RAM B
//
or1200_tpram_32x32 rf_b(
// Port A
.clk_a(clk),
.rst_a(rst),
.ce_a(rf_enb),
.we_a(1'b0),
.oe_a(1'b1),
.addr_a(addrb),
.di_a(32'h0000_0000),
.do_a(from_rfb),
// Port B
.clk_b(clk),
.rst_b(rst),
.ce_b(rf_we & ~sp_exception_comb),
.we_b(rf_we & ~sp_exception_comb),
.oe_b(1'b0),
.addr_b(rf_addrw),
.di_b(rf_dataw),
.do_b()
);
`else
`ifdef OR1200_RFRAM_DUALPORT
//
// Instantiation of register file two-port RAM A
//
or1200_dpram #
(
.aw(5),
.dw(32)
)
rf_a
(
// Port A
.clk_a(clk),
.ce_a(rf_ena),
.addr_a(rf_addra),
.do_a(from_rfa),
// Port B
.clk_b(clk),
.ce_b(rf_we & ~sp_exception_comb),
.we_b(rf_we & ~sp_exception_comb),
.addr_b(rf_addrw),
.di_b(rf_dataw)
);
//
// Instantiation of register file two-port RAM B
//
or1200_dpram #
(
.aw(5),
.dw(32)
)
rf_b
(
// Port A
.clk_a(clk),
.ce_a(rf_enb),
.addr_a(addrb),
.do_a(from_rfb),
// Port B
.clk_b(clk),
.ce_b(rf_we & ~sp_exception_comb),
.we_b(rf_we & ~sp_exception_comb),
.addr_b(rf_addrw),
.di_b(rf_dataw)
);
`else
`ifdef OR1200_RFRAM_GENERIC
//
// Instantiation of generic (flip-flop based) register file
//
or1200_rfram_generic rf_a(
// Clock and reset
.clk(clk),
.rst(rst),
// Port A
.ce_a(rf_ena),
.addr_a(rf_addra),
.do_a(from_rfa),
// Port B
.ce_b(rf_enb),
.addr_b(addrb),
.do_b(from_rfb),
// Port W
.ce_w(rf_we & ~sp_exception_comb),
.we_w(rf_we & ~sp_exception_comb),
.addr_w(rf_addrw),
.di_w(rf_dataw)
);
`else
//
// RFRAM type not specified
//
initial begin
$display("Define RFRAM type.");
$finish;
end
`endif
`endif
`endif
endmodule
|
`include "trellis.vh"
module tx_multiplexer
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_NUM_CHNL = 12,
parameter C_TAG_WIDTH = 5,
parameter C_VENDOR = "ALTERA",
parameter C_DEPTH_PACKETS = 10
)
(
input CLK,
input RST_IN,
input [C_NUM_CHNL-1:0] WR_REQ, // Write request
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] WR_ADDR, // Write address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] WR_LEN, // Write data length
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
output [C_NUM_CHNL-1:0] WR_DATA_REN, // Write data read enable
output [C_NUM_CHNL-1:0] WR_ACK, // Write request has been accepted
output [C_NUM_CHNL-1:0] WR_SENT, // Write Reuqest has been sent to the core
input [C_NUM_CHNL-1:0] RD_REQ, // Read request
input [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL, // Read request channel for scatter gather lists
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] RD_ADDR, // Read request address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] RD_LEN, // Read request length
output [C_NUM_CHNL-1:0] RD_ACK, // Read request has been accepted
output [5:0] INT_TAG, // Internal tag to exchange with external
output INT_TAG_VALID, // High to signal tag exchange
input [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
input EXT_TAG_VALID, // High to signal external tag is valid
output TX_ENG_RD_REQ_SENT, // Read completion request issued
input RXBUF_SPACE_AVAIL,
// Interface: TXR Engine
output TXR_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
output TXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
output TXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
input TXR_DATA_READY,
output TXR_META_VALID,
output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
output [`SIG_TAG_W-1:0] TXR_META_TAG,
output [`SIG_TC_W-1:0] TXR_META_TC,
output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
output TXR_META_EP,
input TXR_META_READY,
input TXR_SENT);
`include "functions.vh"
wire [C_NUM_CHNL-1:0] wAckRdData;
reg [C_NUM_CHNL-1:0] rAckWrData; // Registered fifo input (only write acks)
reg [C_NUM_CHNL-1:0] rAckRdData; // Registered fifo output (only write acks)
reg rAckWrEn,_rAckWrEn; // Fifo write enable (RD or WR_ACK)
reg rAckRdEn; // Fifo read enable (TXR_SENT)
always @(*) begin
_rAckWrEn = (WR_ACK != 0) | (RD_ACK != 0);
end
always @(posedge CLK) begin
rAckWrData <= WR_ACK;
rAckWrEn <= _rAckWrEn;
end
always @(posedge CLK) begin
rAckRdEn <= TXR_SENT;
if(rAckRdEn) begin
rAckRdData <= wAckRdData;
end else begin
rAckRdData <= 0;
end
end
assign WR_SENT = rAckRdData;
fifo
#(// Parameters
.C_WIDTH (C_NUM_CHNL),
.C_DEPTH (C_DEPTH_PACKETS*3), // This is an extremely conservative estimate...
.C_DELAY (0)
/*AUTOINSTPARAM*/)
req_ack_fifo
(// Outputs
.WR_READY (),
.RD_DATA (wAckRdData),
.RD_VALID (),
// Inputs
.WR_DATA (rAckWrData),
.WR_VALID (rAckWrEn),
.RD_READY (rAckRdEn),
.RST (RST_IN),
/*AUTOINST*/
// Inputs
.CLK (CLK));
generate
if(C_PCI_DATA_WIDTH == 32) begin
tx_multiplexer_32
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_TAG_WIDTH (C_TAG_WIDTH),
.C_VENDOR (C_VENDOR))
tx_mux
(/*AUTOINST*/
// Outputs
.WR_DATA_REN (WR_DATA_REN[C_NUM_CHNL-1:0]),
.WR_ACK (WR_ACK[C_NUM_CHNL-1:0]),
.RD_ACK (RD_ACK[C_NUM_CHNL-1:0]),
.INT_TAG (INT_TAG[5:0]),
.INT_TAG_VALID (INT_TAG_VALID),
.TX_ENG_RD_REQ_SENT (TX_ENG_RD_REQ_SENT),
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_REQ (WR_REQ[C_NUM_CHNL-1:0]),
.WR_ADDR (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.WR_LEN (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.WR_DATA (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.RD_REQ (RD_REQ[C_NUM_CHNL-1:0]),
.RD_SG_CHNL (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
.RD_ADDR (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.RD_LEN (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.EXT_TAG (EXT_TAG[C_TAG_WIDTH-1:0]),
.EXT_TAG_VALID (EXT_TAG_VALID),
.RXBUF_SPACE_AVAIL (RXBUF_SPACE_AVAIL),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY));
end else if(C_PCI_DATA_WIDTH == 64) begin
tx_multiplexer_64
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_TAG_WIDTH (C_TAG_WIDTH),
.C_VENDOR (C_VENDOR))
tx_mux
(/*AUTOINST*/
// Outputs
.WR_DATA_REN (WR_DATA_REN[C_NUM_CHNL-1:0]),
.WR_ACK (WR_ACK[C_NUM_CHNL-1:0]),
.RD_ACK (RD_ACK[C_NUM_CHNL-1:0]),
.INT_TAG (INT_TAG[5:0]),
.INT_TAG_VALID (INT_TAG_VALID),
.TX_ENG_RD_REQ_SENT (TX_ENG_RD_REQ_SENT),
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_REQ (WR_REQ[C_NUM_CHNL-1:0]),
.WR_ADDR (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.WR_LEN (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.WR_DATA (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.RD_REQ (RD_REQ[C_NUM_CHNL-1:0]),
.RD_SG_CHNL (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
.RD_ADDR (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.RD_LEN (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.EXT_TAG (EXT_TAG[C_TAG_WIDTH-1:0]),
.EXT_TAG_VALID (EXT_TAG_VALID),
.RXBUF_SPACE_AVAIL (RXBUF_SPACE_AVAIL),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY));
end else if(C_PCI_DATA_WIDTH == 128) begin
tx_multiplexer_128
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_TAG_WIDTH (C_TAG_WIDTH),
.C_VENDOR (C_VENDOR))
tx_mux_128_inst
(/*AUTOINST*/
// Outputs
.WR_DATA_REN (WR_DATA_REN[C_NUM_CHNL-1:0]),
.WR_ACK (WR_ACK[C_NUM_CHNL-1:0]),
.RD_ACK (RD_ACK[C_NUM_CHNL-1:0]),
.INT_TAG (INT_TAG[5:0]),
.INT_TAG_VALID (INT_TAG_VALID),
.TX_ENG_RD_REQ_SENT (TX_ENG_RD_REQ_SENT),
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_REQ (WR_REQ[C_NUM_CHNL-1:0]),
.WR_ADDR (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.WR_LEN (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.WR_DATA (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.RD_REQ (RD_REQ[C_NUM_CHNL-1:0]),
.RD_SG_CHNL (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
.RD_ADDR (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.RD_LEN (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.EXT_TAG (EXT_TAG[C_TAG_WIDTH-1:0]),
.EXT_TAG_VALID (EXT_TAG_VALID),
.RXBUF_SPACE_AVAIL (RXBUF_SPACE_AVAIL),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY));
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "registers/" "../common/")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311OI_LP_V
`define SKY130_FD_SC_LP__A311OI_LP_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311oi_lp (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311oi_lp (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311OI_LP_V
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
reg probepresent /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
probepresent <= 1'b0;
resetrequest <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
probepresent <= jdo[19] ? 1
: jdo[18] ? 0
: probepresent;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset)
begin
jtag_break <= probepresent;
resetlatch <= 1;
end
else if (~debugack & debugreq & probepresent)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_b,
byteena_a,
clock0,
clock1,
clocken0,
clocken1,
data_a,
data_b,
wren_a,
wren_b,
// outputs:
q_a,
q_b
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q_a;
output [ 31: 0] q_b;
input [ 7: 0] address_a;
input [ 7: 0] address_b;
input [ 3: 0] byteena_a;
input clock0;
input clock1;
input clocken0;
input clocken1;
input [ 31: 0] data_a;
input [ 31: 0] data_b;
input wren_a;
input wren_b;
wire [ 31: 0] q_a;
wire [ 31: 0] q_b;
altsyncram the_altsyncram
(
.address_a (address_a),
.address_b (address_b),
.byteena_a (byteena_a),
.clock0 (clock0),
.clock1 (clock1),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (data_a),
.data_b (data_b),
.q_a (q_a),
.q_b (q_b),
.wren_a (wren_a),
.wren_b (wren_b)
);
defparam the_altsyncram.address_aclr_a = "NONE",
the_altsyncram.address_aclr_b = "NONE",
the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.indata_aclr_a = "NONE",
the_altsyncram.indata_aclr_b = "NONE",
the_altsyncram.init_file = lpm_file,
the_altsyncram.intended_device_family = "STRATIXIV",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.numwords_a = 256,
the_altsyncram.numwords_b = 256,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_aclr_a = "NONE",
the_altsyncram.outdata_aclr_b = "NONE",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8,
the_altsyncram.widthad_b = 8,
the_altsyncram.wrcontrol_aclr_a = "NONE",
the_altsyncram.wrcontrol_aclr_b = "NONE";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_ocimem (
// inputs:
address,
begintransfer,
byteenable,
chipselect,
clk,
debugaccess,
jdo,
jrst_n,
resetrequest,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
oci_ram_readdata
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] oci_ram_readdata;
input [ 8: 0] address;
input begintransfer;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input resetrequest;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonRd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonRd1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonWr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon;
wire [ 31: 0] cfgdout;
wire [ 31: 0] oci_ram_readdata;
wire [ 31: 0] sramdout;
assign avalon = begintransfer & ~resetrequest;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
MonWr <= 1'b0;
MonRd <= 1'b0;
MonRd1 <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonAReg[10 : 2]+1;
MonRd <= 1'b1;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
MonRd <= 1'b1;
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonAReg[10 : 2]+1;
MonDReg <= jdo[34 : 3];
MonWr <= 1'b1;
end
else
begin
if (~avalon)
begin
MonWr <= 0;
MonRd <= 0;
end
if (MonRd1)
MonDReg <= MonAReg[10] ? cfgdout : sramdout;
end
MonRd1 <= MonRd;
end
end
//altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component, which is an nios_tdp_ram
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component_module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component
(
.address_a (address[7 : 0]),
.address_b (MonAReg[9 : 2]),
.byteena_a (byteenable),
.clock0 (clk),
.clock1 (clk),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_a (writedata),
.data_b (MonDReg[31 : 0]),
.q_a (oci_ram_readdata),
.q_b (sramdout),
.wren_a (chipselect & write & debugaccess &
~address[8]
),
.wren_b (MonWr)
);
//synthesis translate_off
`ifdef NO_PLI
defparam altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component.lpm_file = "altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_ociram_default_contents.dat";
`else
defparam altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component.lpm_file = "altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_ociram_default_contents.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_ociram_lpm_dram_bdp_component.lpm_file = "altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_ociram_default_contents.mif";
//synthesis read_comments_as_HDL off
assign cfgdout = (MonAReg[4 : 2] == 3'd0)? 32'h00010020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001311 :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000000 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h00010000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_avalon_reg (
// inputs:
address,
chipselect,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input chipselect;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = chipselect & write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000000000000;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000000000);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
reset_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 14: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 16: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 18: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 18: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 18: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
trc_enb,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
dct_buffer,
dct_count,
itm,
trc_ctrl,
trc_on
)
;
output [ 29: 0] dct_buffer;
output [ 3: 0] dct_count;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input trc_enb;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire advanced_exception;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] excaddr;
wire instr_retired;
wire is_cond_dct;
wire is_dct;
wire is_exception;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
wire sync_pending;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
wire synced;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign advanced_exception = 1'b0;
assign is_exception = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign excaddr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_pending = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_pending;
assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign synced = pending_frametype != 4'b1010;
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= ~trc_enb &
take_action_tracectrl & jdo[4];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exctype <= 1'b0;
pending_excaddr <= 0;
end
else if (trc_clear || (!0 && !0))
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exctype <= 1'b0;
pending_excaddr <= 0;
end
else if (instr_retired | advanced_exception)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception)
begin
pending_frametype <= 4'b0010;
pending_excaddr <= excaddr;
if (is_fast_tlb_miss_exception)
pending_exctype <= 1'b1;
else
pending_exctype <= 1'b0;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) & (
~record_itrace |
is_idct |
is_exception |
record_dct_outcome_in_sync
))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~advanced_exception)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & synced & (pending_frametype == 4'b0010))
itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype};
else if (record_itrace & (pending_frametype != 4'b0000))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
end
else if (record_itrace & synced & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= 4'b0000;
end
end
else
itm <= 4'b0000;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
if (0)
trc_ctrl_reg[7 : 5] <= jdo[12 : 10];
if (0 & 0)
trc_ctrl_reg[8] <= jdo[13];
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 18: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_trc_ctrl_td_mode, which is an e_instance
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_td_mode altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else if (0)
begin
if (cpu_d_write & ~cpu_d_wait & record_store_addr)
atm <= {4'b0101, cpu_d_address_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_addr)
atm <= {4'b0100, cpu_d_address_0_padded};
else
atm <= {4'b0000, cpu_d_address_0_padded};
if (cpu_d_write & ~cpu_d_wait & record_store_data)
dtm <= {4'b0111, cpu_d_writedata_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_data)
dtm <= {4'b0110, cpu_d_readdata_0_padded};
else
dtm <= {4'b0000, cpu_d_readdata_0_padded};
end
else
begin
atm <= 0;
dtm <= 0;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
)
;
output [ 1: 0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_tm_count;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_tm_count = 0;
end // 3'b000
3'b001: begin
compute_tm_count = 1;
end // 3'b001
3'b010: begin
compute_tm_count = 1;
end // 3'b010
3'b011: begin
compute_tm_count = 2;
end // 3'b011
3'b100: begin
compute_tm_count = 1;
end // 3'b100
3'b101: begin
compute_tm_count = 2;
end // 3'b101
3'b110: begin
compute_tm_count = 2;
end // 3'b110
3'b111: begin
compute_tm_count = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
)
;
output [ 3: 0] fifowp_inc;
input free2;
input free3;
input [ 1: 0] tm_count;
reg [ 3: 0] fifowp_inc;
always @(free2 or free3 or tm_count)
begin
if (free3 & (tm_count == 3))
fifowp_inc = 3;
else if (free2 & (tm_count >= 2))
fifowp_inc = 2;
else if (tm_count >= 1)
fifowp_inc = 1;
else
fifowp_inc = 0;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
)
;
output [ 4: 0] fifocount_inc;
input empty;
input free2;
input free3;
input [ 1: 0] tm_count;
reg [ 4: 0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)
begin
if (empty)
fifocount_inc = tm_count[1 : 0];
else if (free3 & (tm_count == 3))
fifocount_inc = 2;
else if (free2 & (tm_count >= 2))
fifocount_inc = 1;
else if (tm_count >= 1)
fifocount_inc = 0;
else
fifocount_inc = {5{1'b1}};
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dct_buffer,
dct_count,
dtm,
itm,
jrst_n,
reset_n,
test_ending,
test_has_ended,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input test_ending;
input test_has_ended;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_tm_count_tm_count;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
wire [ 35: 0] fifo_read_mux;
reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifocount_inc_fifocount;
wire [ 35: 0] fifohead;
reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifowp1;
wire [ 3: 0] fifowp2;
wire [ 3: 0] fifowp_inc_fifowp;
wire free2;
wire free3;
wire itm_valid;
reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] ovr_pending_atm;
wire [ 35: 0] ovr_pending_dtm;
wire [ 1: 0] tm_count;
wire tm_count_ge1;
wire tm_count_ge2;
wire tm_count_ge3;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign free2 = ~fifocount[4];
assign free3 = ~fifocount[4] & ~&fifocount[3 : 0];
assign empty = ~|fifocount;
assign fifowp1 = fifowp + 1;
assign fifowp2 = fifowp + 2;
//altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_compute_tm_count_tm_count, which is an e_instance
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_compute_tm_count altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_compute_tm_count_tm_count
(
.atm_valid (atm_valid),
.compute_tm_count (compute_tm_count_tm_count),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign tm_count = compute_tm_count_tm_count;
//altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_fifowp_inc_fifowp, which is an e_instance
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_fifowp_inc altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_fifowp_inc_fifowp
(
.fifowp_inc (fifowp_inc_fifowp),
.free2 (free2),
.free3 (free3),
.tm_count (tm_count)
);
//altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_fifocount_inc_fifocount, which is an e_instance
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_fifocount_inc altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_fifocount_inc_fifocount
(
.empty (empty),
.fifocount_inc (fifocount_inc_fifocount),
.free2 (free2),
.free3 (free3),
.tm_count (tm_count)
);
//the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_oci_test_bench, which is an e_instance
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_oci_test_bench the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_oci_test_bench
(
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.test_ending (test_ending),
.test_has_ended (test_has_ended)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fiforp <= 0;
fifowp <= 0;
fifocount <= 0;
ovf_pending <= 1;
end
else
begin
fifowp <= fifowp + fifowp_inc_fifowp;
fifocount <= fifocount + fifocount_inc_fifocount;
if (~empty)
fiforp <= fiforp + 1;
if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count)))
ovf_pending <= 1;
else if (atm_valid | dtm_valid)
ovf_pending <= 0;
end
end
assign fifohead = fifo_read_mux;
assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm;
assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm :
(((fifowp == 4'd0) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm :
(((fifowp == 4'd1) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm :
(((fifowp == 4'd2) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm :
(((fifowp == 4'd3) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm :
(((fifowp == 4'd4) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm :
(((fifowp == 4'd5) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm :
(((fifowp == 4'd6) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm :
(((fifowp == 4'd7) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm :
(((fifowp == 4'd8) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm :
(((fifowp == 4'd9) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm :
(((fifowp == 4'd10) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm :
(((fifowp == 4'd11) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm :
(((fifowp == 4'd12) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm :
(((fifowp == 4'd13) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm :
(((fifowp == 4'd14) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm :
(((fifowp == 4'd15) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign tm_count_ge1 = |tm_count;
assign tm_count_ge2 = tm_count[1];
assign tm_count_ge3 = &tm_count;
assign ovr_pending_atm = {ovf_pending, atm[34 : 0]};
assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]};
assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 :
(fiforp == 4'd1)? fifo_1 :
(fiforp == 4'd2)? fifo_2 :
(fiforp == 4'd3)? fifo_3 :
(fiforp == 4'd4)? fifo_4 :
(fiforp == 4'd5)? fifo_5 :
(fiforp == 4'd6)? fifo_6 :
(fiforp == 4'd7)? fifo_7 :
(fiforp == 4'd8)? fifo_8 :
(fiforp == 4'd9)? fifo_9 :
(fiforp == 4'd10)? fifo_10 :
(fiforp == 4'd11)? fifo_11 :
(fiforp == 4'd12)? fifo_12 :
(fiforp == 4'd13)? fifo_13 :
(fiforp == 4'd14)? fifo_14 :
fifo_15;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
)
;
output tr_clk;
output [ 17: 0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [ 35: 0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 17: 0] tr_data;
reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
assign phase = x1^x2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
x1 <= 0;
else
x1 <= ~x1;
end
always @(posedge clkx2 or negedge jrst_n)
begin
if (jrst_n == 0)
begin
x2 <= 0;
tr_clk_reg <= 0;
tr_data_reg <= 0;
end
else
begin
x2 <= x1;
tr_clk_reg <= ~phase;
tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18];
end
end
assign tr_clk = 0 ? tr_clk_reg : 0;
assign tr_data = 0 ? tr_data_reg : 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_traceram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_b,
clock0,
clock1,
clocken0,
clocken1,
data_a,
data_b,
wren_a,
wren_b,
// outputs:
q_a,
q_b
)
;
parameter lpm_file = "UNUSED";
output [ 35: 0] q_a;
output [ 35: 0] q_b;
input [ 6: 0] address_a;
input [ 6: 0] address_b;
input clock0;
input clock1;
input clocken0;
input clocken1;
input [ 35: 0] data_a;
input [ 35: 0] data_b;
input wren_a;
input wren_b;
wire [ 35: 0] q_a;
wire [ 35: 0] q_b;
altsyncram the_altsyncram
(
.address_a (address_a),
.address_b (address_b),
.clock0 (clock0),
.clock1 (clock1),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (data_a),
.data_b (data_b),
.q_a (q_a),
.q_b (q_b),
.wren_a (wren_a),
.wren_b (wren_b)
);
defparam the_altsyncram.address_aclr_a = "NONE",
the_altsyncram.address_aclr_b = "NONE",
the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.indata_aclr_a = "NONE",
the_altsyncram.indata_aclr_b = "NONE",
the_altsyncram.init_file = lpm_file,
the_altsyncram.intended_device_family = "STRATIXIV",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.numwords_a = 128,
the_altsyncram.numwords_b = 128,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_aclr_a = "NONE",
the_altsyncram.outdata_aclr_b = "NONE",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
the_altsyncram.width_a = 36,
the_altsyncram.width_b = 36,
the_altsyncram.widthad_a = 7,
the_altsyncram.widthad_b = 7,
the_altsyncram.wrcontrol_aclr_a = "NONE",
the_altsyncram.wrcontrol_aclr_b = "NONE";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output trc_enb;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_tracectrl;
input take_action_tracemem_a;
input take_action_tracemem_b;
input take_no_action_tracemem_a;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire trc_enb;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 35: 0] trc_jtag_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire [ 35: 0] unused_bdpram_port_q_a;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (!0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (take_action_tracectrl &&
(jdo[4] | jdo[3]))
begin
if (jdo[4])
trc_im_addr <= 0;
if (jdo[3])
trc_wrap <= 0;
end
else if (trc_enb & trc_on_chip & tw_valid)
begin
trc_im_addr <= trc_im_addr+1;
if (&trc_im_addr)
trc_wrap <= 1;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trc_jtag_addr <= 0;
else if (take_action_tracemem_a ||
take_no_action_tracemem_a ||
take_action_tracemem_b)
trc_jtag_addr <= take_action_tracemem_a ?
jdo[35 : 19] :
trc_jtag_addr + 1;
end
assign trc_enb = trc_ctrl[0];
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = (0) ?
trc_jtag_data : 0;
assign tracemem_tw = trc_wrap;
assign tracemem_on = trc_enb;
//altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_traceram_lpm_dram_bdp_component, which is an nios_tdp_ram
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_traceram_lpm_dram_bdp_component_module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_traceram_lpm_dram_bdp_component
(
.address_a (trc_im_addr),
.address_b (trc_jtag_addr),
.clock0 (clk),
.clock1 (clk),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_a (trc_im_data),
.data_b (jdo[36 : 1]),
.q_a (unused_bdpram_port_q_a),
.q_b (trc_jtag_data),
.wren_a (tw_valid & trc_enb),
.wren_b (take_action_tracemem_b)
);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_performance_monitors
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address,
av_ld_data_aligned_filtered,
begintransfer,
byteenable,
chipselect,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess,
hbreak_enabled,
reset,
reset_n,
test_ending,
test_has_ended,
write,
writedata,
// outputs:
jtag_debug_module_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest
)
;
output jtag_debug_module_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 14: 0] F_pc;
input [ 8: 0] address;
input [ 31: 0] av_ld_data_aligned_filtered;
input begintransfer;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input [ 18: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess;
input hbreak_enabled;
input reset;
input reset_n;
input test_ending;
input test_has_ended;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] MonDReg;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
wire clkx2;
wire [ 18: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire [ 29: 0] dct_buffer;
wire [ 3: 0] dct_count;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire jtag_debug_module_debugaccess_to_roms;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_ram_readdata;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire tr_clk;
wire [ 17: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire trc_enb;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_debug the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_ocimem the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.begintransfer (begintransfer),
.byteenable (byteenable),
.chipselect (chipselect),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.oci_ram_readdata (oci_ram_readdata),
.resetrequest (resetrequest),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.write (write),
.writedata (writedata)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_avalon_reg the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_avalon_reg
(
.address (address),
.chipselect (chipselect),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_break the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_xbrk the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_dbrk the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_itrace the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_dtrace the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_fifo the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.trc_on (trc_on),
.tw (tw)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_pib the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_pib
(
.clk (clk),
.clkx2 (clkx2),
.jrst_n (jrst_n),
.tr_clk (tr_clk),
.tr_data (tr_data),
.tw (tw)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_im the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci_im
(
.clk (clk),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign readdata = address[8] ? oci_reg_readdata : oci_ram_readdata;
assign jtag_debug_module_debugaccess_to_roms = debugack;
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_clk |
tr_data |
trigout |
debugack;
assign debugreq = 0;
assign clkx2 = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst (
// inputs:
clk,
d_irq,
d_readdata,
d_waitrequest,
i_readdata,
i_waitrequest,
jtag_debug_module_address,
jtag_debug_module_begintransfer,
jtag_debug_module_byteenable,
jtag_debug_module_debugaccess,
jtag_debug_module_select,
jtag_debug_module_write,
jtag_debug_module_writedata,
reset_n,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
i_address,
i_read,
jtag_debug_module_debugaccess_to_roms,
jtag_debug_module_readdata,
jtag_debug_module_resetrequest,
no_ci_readra
)
;
output [ 18: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output [ 16: 0] i_address;
output i_read;
output jtag_debug_module_debugaccess_to_roms;
output [ 31: 0] jtag_debug_module_readdata;
output jtag_debug_module_resetrequest;
output no_ci_readra;
input clk;
input [ 31: 0] d_irq;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 8: 0] jtag_debug_module_address;
input jtag_debug_module_begintransfer;
input [ 3: 0] jtag_debug_module_byteenable;
input jtag_debug_module_debugaccess;
input jtag_debug_module_select;
input jtag_debug_module_write;
input [ 31: 0] jtag_debug_module_writedata;
input reset_n;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_logic;
wire D_ctrl_rdctl_inst;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_st;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 2: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 4: 0] D_iw_shift_imm5;
wire [ 4: 0] D_iw_trap_break_imm5;
wire [ 14: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 55: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 18: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
reg E_valid;
wire [ 55: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 2: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire [ 4: 0] F_av_iw_shift_imm5;
wire [ 4: 0] F_av_iw_trap_break_imm5;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 2: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire [ 4: 0] F_iw_shift_imm5;
wire [ 4: 0] F_iw_trap_break_imm5;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_opx;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_rsv02;
wire F_op_rsv09;
wire F_op_rsv10;
wire F_op_rsv17;
wire F_op_rsv18;
wire F_op_rsv25;
wire F_op_rsv26;
wire F_op_rsv33;
wire F_op_rsv34;
wire F_op_rsv41;
wire F_op_rsv42;
wire F_op_rsv49;
wire F_op_rsv57;
wire F_op_rsv61;
wire F_op_rsv62;
wire F_op_rsv63;
wire F_op_rsvx00;
wire F_op_rsvx10;
wire F_op_rsvx15;
wire F_op_rsvx17;
wire F_op_rsvx21;
wire F_op_rsvx25;
wire F_op_rsvx33;
wire F_op_rsvx34;
wire F_op_rsvx35;
wire F_op_rsvx42;
wire F_op_rsvx43;
wire F_op_rsvx44;
wire F_op_rsvx47;
wire F_op_rsvx50;
wire F_op_rsvx51;
wire F_op_rsvx55;
wire F_op_rsvx56;
wire F_op_rsvx60;
wire F_op_rsvx63;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 14: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 14: 0] F_pc_no_crst_nxt;
wire [ 14: 0] F_pc_nxt;
wire [ 14: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 16: 0] F_pcb;
wire [ 16: 0] F_pcb_nxt;
wire [ 16: 0] F_pcb_plus_four;
wire F_valid;
wire [ 55: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_rdctl_inst;
wire R_ctrl_rdctl_inst_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_st;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
reg R_valid;
wire [ 55: 0] R_vinst;
reg R_wr_dst_reg;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 18: 0] W_mem_baddr;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 55: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 18: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
wire d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 16: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire jtag_debug_module_clk;
wire jtag_debug_module_debugaccess_to_roms;
wire [ 31: 0] jtag_debug_module_readdata;
wire jtag_debug_module_reset;
wire jtag_debug_module_resetrequest;
wire no_ci_readra;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_ending;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench, which is an e_instance
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_alu_result (E_alu_result),
.E_mem_byte_en (E_mem_byte_en),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_exception (R_ctrl_exception),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_bstatus_reg (W_bstatus_reg),
.W_cmp_result (W_cmp_result),
.W_estatus_reg (W_estatus_reg),
.W_ienable_reg (W_ienable_reg),
.W_ipending_reg (W_ipending_reg),
.W_mem_baddr (W_mem_baddr),
.W_rf_wr_data (W_rf_wr_data),
.W_status_reg (W_status_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.d_write_nxt (d_write_nxt),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_shift_imm5 = F_av_iw[10 : 6];
assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[8 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_shift_imm5 = F_iw[10 : 6];
assign F_iw_trap_break_imm5 = F_iw[10 : 6];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[8 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_shift_imm5 = D_iw[10 : 6];
assign D_iw_trap_break_imm5 = D_iw[10 : 6];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[8 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_rsv02 = F_iw_op == 2;
assign F_op_rsv09 = F_iw_op == 9;
assign F_op_rsv10 = F_iw_op == 10;
assign F_op_rsv17 = F_iw_op == 17;
assign F_op_rsv18 = F_iw_op == 18;
assign F_op_rsv25 = F_iw_op == 25;
assign F_op_rsv26 = F_iw_op == 26;
assign F_op_rsv33 = F_iw_op == 33;
assign F_op_rsv34 = F_iw_op == 34;
assign F_op_rsv41 = F_iw_op == 41;
assign F_op_rsv42 = F_iw_op == 42;
assign F_op_rsv49 = F_iw_op == 49;
assign F_op_rsv57 = F_iw_op == 57;
assign F_op_rsv61 = F_iw_op == 61;
assign F_op_rsv62 = F_iw_op == 62;
assign F_op_rsv63 = F_iw_op == 63;
assign F_op_eret = F_op_opx & (F_iw_opx == 1);
assign F_op_roli = F_op_opx & (F_iw_opx == 2);
assign F_op_rol = F_op_opx & (F_iw_opx == 3);
assign F_op_flushp = F_op_opx & (F_iw_opx == 4);
assign F_op_ret = F_op_opx & (F_iw_opx == 5);
assign F_op_nor = F_op_opx & (F_iw_opx == 6);
assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7);
assign F_op_cmpge = F_op_opx & (F_iw_opx == 8);
assign F_op_bret = F_op_opx & (F_iw_opx == 9);
assign F_op_ror = F_op_opx & (F_iw_opx == 11);
assign F_op_flushi = F_op_opx & (F_iw_opx == 12);
assign F_op_jmp = F_op_opx & (F_iw_opx == 13);
assign F_op_and = F_op_opx & (F_iw_opx == 14);
assign F_op_cmplt = F_op_opx & (F_iw_opx == 16);
assign F_op_slli = F_op_opx & (F_iw_opx == 18);
assign F_op_sll = F_op_opx & (F_iw_opx == 19);
assign F_op_wrprs = F_op_opx & (F_iw_opx == 20);
assign F_op_or = F_op_opx & (F_iw_opx == 22);
assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23);
assign F_op_cmpne = F_op_opx & (F_iw_opx == 24);
assign F_op_srli = F_op_opx & (F_iw_opx == 26);
assign F_op_srl = F_op_opx & (F_iw_opx == 27);
assign F_op_nextpc = F_op_opx & (F_iw_opx == 28);
assign F_op_callr = F_op_opx & (F_iw_opx == 29);
assign F_op_xor = F_op_opx & (F_iw_opx == 30);
assign F_op_mulxss = F_op_opx & (F_iw_opx == 31);
assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32);
assign F_op_divu = F_op_opx & (F_iw_opx == 36);
assign F_op_div = F_op_opx & (F_iw_opx == 37);
assign F_op_rdctl = F_op_opx & (F_iw_opx == 38);
assign F_op_mul = F_op_opx & (F_iw_opx == 39);
assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40);
assign F_op_initi = F_op_opx & (F_iw_opx == 41);
assign F_op_trap = F_op_opx & (F_iw_opx == 45);
assign F_op_wrctl = F_op_opx & (F_iw_opx == 46);
assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48);
assign F_op_add = F_op_opx & (F_iw_opx == 49);
assign F_op_break = F_op_opx & (F_iw_opx == 52);
assign F_op_hbreak = F_op_opx & (F_iw_opx == 53);
assign F_op_sync = F_op_opx & (F_iw_opx == 54);
assign F_op_sub = F_op_opx & (F_iw_opx == 57);
assign F_op_srai = F_op_opx & (F_iw_opx == 58);
assign F_op_sra = F_op_opx & (F_iw_opx == 59);
assign F_op_intr = F_op_opx & (F_iw_opx == 61);
assign F_op_crst = F_op_opx & (F_iw_opx == 62);
assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0);
assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10);
assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15);
assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17);
assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21);
assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25);
assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33);
assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34);
assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35);
assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42);
assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43);
assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44);
assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47);
assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50);
assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51);
assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55);
assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56);
assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60);
assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63);
assign F_op_opx = F_iw_op == 58;
assign F_op_custom = F_iw_op == 50;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign no_ci_readra = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000000000;
assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 16392 :
(F_pc_sel_nxt == 2'b01)? 8 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[16 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 16384;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw;
assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_jmp_direct_target_waddr = D_iw[31 : 6];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_register_bank_a, which is an nios_sdp_ram
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_register_bank_a_module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a),
.rdaddress (D_iw_a),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_register_bank_a.lpm_file = "altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_rf_ram_a.dat";
`else
defparam altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_register_bank_a.lpm_file = "altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_rf_ram_a.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_register_bank_a.lpm_file = "altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_rf_ram_a.mif";
//synthesis read_comments_as_HDL off
//altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_register_bank_b, which is an nios_sdp_ram
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_register_bank_b_module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b),
.rdaddress (D_iw_b),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_register_bank_b.lpm_file = "altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_rf_ram_b.dat";
`else
defparam altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_register_bank_b.lpm_file = "altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_rf_ram_b.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_register_bank_b.lpm_file = "altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_rf_ram_b.mif";
//synthesis read_comments_as_HDL off
assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid <= 0;
else
E_valid <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall;
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[18 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg :
(D_iw_control_regnum == 3'd1)? W_estatus_reg :
(D_iw_control_regnum == 3'd2)? W_bstatus_reg :
(D_iw_control_regnum == 3'd3)? W_ienable_reg :
(D_iw_control_regnum == 3'd4)? W_ipending_reg :
0;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_stb_data = R_rf_b[7 : 0];
assign R_sth_data = R_rf_b[15 : 0];
assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_mem16)? {R_sth_data, R_sth_data} :
R_rf_b;
assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :
d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rdctl_inst ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br & W_cmp_result;
assign W_mem_baddr = W_alu_result[18 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000000000;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000000000;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address (jtag_debug_module_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.begintransfer (jtag_debug_module_begintransfer),
.byteenable (jtag_debug_module_byteenable),
.chipselect (jtag_debug_module_select),
.clk (jtag_debug_module_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debugaccess (jtag_debug_module_debugaccess),
.hbreak_enabled (hbreak_enabled),
.jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.readdata (jtag_debug_module_readdata),
.reset (jtag_debug_module_reset),
.reset_n (reset_n),
.resetrequest (jtag_debug_module_resetrequest),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.write (jtag_debug_module_write),
.writedata (jtag_debug_module_writedata)
);
//jtag_debug_module, which is an e_avalon_slave
assign jtag_debug_module_clk = clk;
assign jtag_debug_module_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = D_op_crst|D_op_rsvx63;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|
D_op_jmpi|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_rsvx50|
D_op_sll|
D_op_rsvx51|
D_op_roli|
D_op_rsvx34|
D_op_rol|
D_op_rsvx35|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_br_uncond = D_op_br|D_op_rsv02;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_rsvx25|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_rsvx00|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq|
D_op_rsvx56;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st = D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_rdctl_inst = D_op_rdctl;
assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rdctl_inst <= 0;
else if (R_en)
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42|
D_op_beq|
D_op_rsv34|
D_op_bne|
D_op_rsv62|
D_op_br|
D_op_rsv02;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {7{8'h2d}};
assign D_vinst = D_valid ? D_inst : {7{8'h2d}};
assign R_vinst = R_valid ? D_inst : {7{8'h2d}};
assign E_vinst = E_valid ? D_inst : {7{8'h2d}};
assign W_vinst = W_valid ? D_inst : {7{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
// place this file in testBench folder
`timescale 1ns/100ps
`define DEBUG 1
`include "../define.v"
`include "../regfile.v"
`include "../pipeline_CPU.v"
`include "../hilo_reg.v"
`include "../BranchControl.v"
`include "../HazardControl.v"
`include "../ForwardControl.v"
`include "../IF.v"
`include "../IF_ID.v"
`include "../ID.v"
`include "../ID_EX.v"
`include "../EX.v"
`include "../ALU.v"
`include "../decoder.v"
`include "../EX_MEM.v"
`include "../MEM.v"
`include "../RM_ctrl.v"
`include "../WM_ctrl.v"
`include "../MEM_WB.v"
`include "../utilities/dffe.v"
`include "../utilities/mux2x1.v"
`include "../utilities/mux4x1.v"
`include "rom.v"
`include "memory.v"
module SOPC;
reg clk;
reg rst;
wire[`RegDataWidth-1:0] data_from_mem;
wire[`MemAddrWidth-1:0] mem_addr;
wire[3:0] mem_byte_slct;
wire[`RegDataWidth-1:0] data_to_write_mem;
wire mem_we;
wire mem_re;
wire[`InstDataWidth-1:0] inst_from_rom;
wire[`InstAddrWidth-1:0] rom_addr;
wire rom_ce;
supply1 vcc;
supply0 gnd;
pipeline_CPU CPU(
.clk(clk),
.rst(rst),
.data_from_mem(data_from_mem),
.mem_addr(mem_addr),
.mem_byte_slct(mem_byte_slct),
.data_to_write_mem(data_to_write_mem),
.mem_we(mem_we),
.mem_re(mem_re),
.inst_from_rom(inst_from_rom),
.rom_addr(rom_addr),
.rom_ce(rom_ce)
);
rom #(.InstMemNum(32)) ROM(
.rst(gnd),
.ce(rom_ce),
.addr(rom_addr),
.inst(inst_from_rom)
);
memory RAM(
.rst(rst),
.ce(mem_re),
.data_i(data_to_write_mem),
.addr_i(mem_addr),
.we(mem_we),
.byte_slct(mem_byte_slct),
.data_o(data_from_mem)
);
initial begin
clk = 1;
forever #1 clk = ~clk;
end
initial begin
$dumpfile("test_info/logic/logic.vcd");
$dumpvars;
$readmemh("test_info/logic/logic.data", ROM.rom_data, 0, 13);
rst = `RstEnable;
#3 rst = ~`RstEnable;
#70 $finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211OI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A211OI_PP_SYMBOL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a211oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211OI_PP_SYMBOL_V
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* SGMII autonegotiation state machine
*/
module sgmii_autoneg
(
input rst,
input tbi_rx_clk,
input [7:0] rx_byte,
input rx_is_k,
input rx_disp_err,
output sgmii_autoneg_start,
output sgmii_autoneg_ack,
output sgmii_autoneg_idle,
output sgmii_autoneg_done,
output [15:0] sgmii_config
);
parameter LINK_TIMER = 16'd40000;
//
// RX Autonegotiation state machine
//
reg [5:0] rx_state;
wire [5:0] rx_state_next = (rx_state + 6'd1);
reg rx_state_start;
reg rx_state_ack;
reg rx_state_idle;
reg rx_state_complete;
reg [15:0] rx_cfg_cnt;
reg [15:0] rx_cfg1;
reg [15:0] rx_cfg2;
reg [15:0] rx_cfg;
wire rx_error = rx_disp_err || (rx_is_k && (rx_byte == 8'd0));
assign sgmii_autoneg_start = rx_state_start;
assign sgmii_autoneg_ack = rx_state_ack;
assign sgmii_autoneg_idle = rx_state_idle;
assign sgmii_autoneg_done = rx_state_complete;
assign sgmii_config = rx_cfg;
always @ (posedge tbi_rx_clk or posedge rst)
if (rst)
begin
rx_state <= 6'd0;
rx_state_start <= 1'b0;
rx_state_ack <= 1'b0;
rx_state_idle <= 1'b0;
rx_state_complete <= 1'b0;
rx_cfg_cnt <= 16'd0;
rx_cfg1 <= 16'd0;
rx_cfg2 <= 16'd0;
rx_cfg <= 16'd0;
end
else
case (rx_state)
6'd0:
begin
rx_state <= 6'd1;
rx_state_start <= 1'b0;
rx_state_ack <= 1'b0;
rx_state_idle <= 1'b0;
rx_state_complete <= 1'b0;
rx_cfg_cnt <= 16'd0;
rx_cfg1 <= 16'd0;
rx_cfg2 <= 16'd0;
rx_cfg <= 16'd0;
end
// Search for first CFG1/2
6'd1: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd1;
6'd2: rx_state <= (!rx_is_k && (rx_byte == 8'hB5)) ? rx_state_next : 6'd1;
6'd3: rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
6'd4: rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
6'd5: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd6: rx_state <= (!rx_is_k && (rx_byte == 8'h42)) ? rx_state_next : 6'd0;
6'd7: rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
6'd8: rx_state <= (rx_is_k) ? 6'd0 : 6'd11;
// Continue to count LINK_TIMER x CFG1/2
6'd11: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd12: rx_state <= (!rx_is_k && (rx_byte == 8'hB5)) ? rx_state_next : 6'd0;
6'd13:
begin
rx_state_start <= 1'b1;
rx_cfg_cnt <= rx_cfg_cnt + 16'd1;
rx_cfg1[7:0] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd14:
begin
rx_cfg1[15:8] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd15: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd16: rx_state <= (!rx_is_k && (rx_byte == 8'h42)) ? rx_state_next : 6'd0;
6'd17:
begin
rx_cfg2[7:0] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd18:
begin
rx_cfg2[15:8] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 :
(rx_cfg_cnt == LINK_TIMER) ? 6'd21 : 6'd11;
end
// Wait for non-zero CFG
6'd21: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd22: rx_state <= (!rx_is_k && (rx_byte == 8'hB5)) ? rx_state_next : 6'd0;
6'd23:
begin
rx_cfg_cnt <= 16'd0;
rx_cfg1[7:0] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd24:
begin
rx_cfg1[15:8] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd25: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd26: rx_state <= (!rx_is_k && (rx_byte == 8'h42)) ? rx_state_next : 6'd0;
6'd27:
begin
rx_cfg2[7:0] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd28:
begin
rx_cfg2[15:8] <= rx_byte;
rx_cfg <= rx_cfg2;
rx_state <= (rx_is_k) ? 6'd0 : (rx_cfg1[0] && rx_cfg2[0] && rx_cfg[0]) ? 6'd31 : 6'd21;
end
// Wait for ACK
6'd31: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd32: rx_state <= (!rx_is_k && (rx_byte == 8'hB5)) ? rx_state_next : 6'd0;
6'd33:
begin
rx_state_ack <= 1'b1;
rx_cfg1[7:0] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd34:
begin
rx_cfg1[15:8] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd35: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd36: rx_state <= (!rx_is_k && (rx_byte == 8'h42)) ? rx_state_next : 6'd0;
6'd37:
begin
rx_cfg2[7:0] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd38:
begin
rx_cfg2[15:8] <= rx_byte;
rx_cfg <= rx_cfg2;
rx_state <= (rx_is_k) ? 6'd0 :
(rx_cfg1[14] && rx_cfg1[0] && rx_cfg2[14] && rx_cfg2[0] && rx_cfg[14] && rx_cfg[0]) ? 6'd41 : 6'd31;
end
// Continue to count LINK_TIMER more x CFG1/2, must match previous non-zero value
6'd41: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd42: rx_state <= (rx_is_k) ? 6'd0 : (rx_byte == 8'hB5) ? rx_state_next :
((rx_byte == 8'hC5) || (rx_byte == 8'h50)) ? 6'd51 : 6'd0;
6'd43:
begin
rx_cfg_cnt <= rx_cfg_cnt + 16'd1;
rx_cfg1[7:0] <= rx_byte;
rx_state <= (rx_is_k || (rx_cfg1 != rx_cfg2) || (rx_cfg1 != rx_cfg)) ? 6'd0 : rx_state_next;
end
6'd44:
begin
rx_cfg1[15:8] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd45: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd46: rx_state <= (!rx_is_k && (rx_byte == 8'h42)) ? rx_state_next : 6'd0;
6'd47:
begin
rx_cfg2[7:0] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd48:
begin
rx_cfg2[15:8] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 :
(rx_cfg_cnt == LINK_TIMER) ? 6'd51 : 6'd41;
end
// Wait for 2 x IDLE
6'd51:
begin
rx_state_idle <= 1'b1;
rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd51;
end
6'd52: rx_state <= (!rx_is_k && (rx_byte == 8'hB5)) ? 6'd59 :
(!rx_is_k && ((rx_byte == 8'h50) || (rx_byte == 8'hC5))) ? rx_state_next : 6'd51;
6'd53: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd51;
6'd54: rx_state <= (!rx_is_k && ((rx_byte == 8'h50) || (rx_byte == 8'hC5))) ? rx_state_next : 6'd51;
6'd55: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd51;
6'd56: rx_state <= (!rx_is_k && ((rx_byte == 8'h50) || (rx_byte == 8'hC5))) ? rx_state_next : 6'd51;
6'd57: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd51;
6'd58: rx_state <= (!rx_is_k && ((rx_byte == 8'h50) || (rx_byte == 8'hC5))) ? 6'd61 : 6'd51;
// Error condition if CFG changed
6'd59: rx_state <= (!rx_is_k && (rx_byte != rx_cfg[7:0])) ? 6'd0 : 6'd60;
6'd60: rx_state <= (!rx_is_k && (rx_byte != rx_cfg[15:8])) ? 6'd0 : 6'd51;
// Done receiving CFG - restart on error or seeing another CFG sequence
6'd61:
begin
rx_state_complete <= 1'b1;
rx_state <= rx_state_next;
end
6'd62:
rx_state <= (rx_error) ? 6'd0 :
(rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : rx_state;
6'd63:
rx_state <= (rx_error) ? 6'd0 :
(!rx_is_k && ((rx_byte == 8'hB5) || (rx_byte == 8'h42))) ? 6'd0 : 6'd62;
default: rx_state <= 6'd0;
endcase
endmodule
|
`timescale 1ns/1ns
/******************************************************************************
*
******************************************************************************/
module simulation_top ();
/**
* Signal definitions to connect the DUT.
*/
wire sclk, mosi, miso;
reg spi_select;
reg sys_clk, rst_n;
reg [31:0] q_AXI_araddr; // read address address (data)
reg [2:0] q_AXI_arprot; // ???
wire w_AXI_arready; // read address ready
reg q_AXI_arvalid; // read address valid
reg [31:0] q_AXI_awaddr; // write address address (channel data)
reg [2:0] q_AXI_awprot; // write address ??
wire w_AXI_awready; // write address ready
reg q_AXI_awvalid; // write address valid
reg q_AXI_bready; // (write) response ready
wire [1:0] w_AXI_bresp; // write response
wire w_AXI_bvalid; // write response valid
wire [31:0] w_AXI_rdata; // read data
reg q_AXI_rready; // read ready
wire [1:0] w_AXI_rresp; // read response
wire w_AXI_rvalid; // read valid
reg [31:0] q_AXI_wdata; // write data
wire w_AXI_wready; // write ready
reg [3:0] q_AXI_wstrb; // ??
reg q_AXI_wvalid; // write valid
//IRQ to AXI master
wire IRQ;
/**
* Instantiate the DUT.
*/
axi2spi_bridge axi_spi_DUT(
//CLK
.FCLK_CLK0(sys_clk),
//RST
.RST_N(rst_n),
//AXI INTERFACE
.AXI_araddr(q_AXI_araddr), // read address address (data)
.AXI_arprot(q_AXI_arprot), // ???
.AXI_arready(w_AXI_arready), // read address ready
.AXI_arvalid(q_AXI_arvalid), // read address valid
.AXI_awaddr(q_AXI_awaddr), // write address address (channel data)
.AXI_awprot(q_AXI_awprot), // write address ??
.AXI_awready(w_AXI_awready), // write address ready
.AXI_awvalid(q_AXI_awvalid), // write address valid
.AXI_bready(q_AXI_bready), // (write) response ready
.AXI_bresp(w_AXI_bresp), // write response
.AXI_bvalid(w_AXI_bvalid), // write response valid
.AXI_rdata(w_AXI_rdata), // read data
.AXI_rready(q_AXI_rready), // read ready
.AXI_rresp(w_AXI_rresp), // read response
.AXI_rvalid(w_AXI_rvalid), // read valid
.AXI_wdata(q_AXI_wdata), // write data
.AXI_wready(w_AXI_wready), // write ready
.AXI_wstrb(q_AXI_wstrb), // ??
.AXI_wvalid(q_AXI_wvalid), // write valid
//IRQ to AXI master
.IRQ(w_IRQ),
//SPI interface
.i_miso(miso),
.o_mosi(mosi),
.o_sclk(sclk)
);
/**
* Macros for eeprom:
*/
M95XXX_Macro_mux M95XXX_Macro_mux_inst ();
/**
* Instantiate the SPI eeprom behaviorall.
*/
M95XXX eeprom_model_inst(
.C(sclk),
.D(mosi),
.Q(miso),
.S(spi_select),
.W(1'b1),
.HOLD(1'b1),
.VCC(1'b1),
.VSS(1'b0)
);
/******************************************************************************
* GENERATE STIMULUS
******************************************************************************/
// AXI is a 32 bits width bus. We must multiply addresses by 4.
`define ADDR_CONTROL_REG 32'h0*4
`define ADDR_STATUS_REG 32'h1*4
`define ADDR_DATA_REG 32'h2*4
// enum integer{ADDR_READ, ADDR_WRITE, WRITE_DATA, READ_DATA, RESPONSE} AXI_CHANNEL;
/**
* Set all register initial state to 0;
*/
initial begin
spi_select = 0;
sys_clk = 0;
rst_n = 0;
q_AXI_araddr = 0; // read address address (data)
q_AXI_arprot = 0; // ???
q_AXI_arvalid = 0; // read address valid
q_AXI_awaddr = 0; // write address address (channel data)
q_AXI_awprot = 0; // write address ??
q_AXI_awvalid = 0; // write address valid
q_AXI_bready = 0; // (write) response ready
q_AXI_rready = 0; // read ready
q_AXI_wdata = 0; // write data
q_AXI_wstrb = 0; // ??
q_AXI_wvalid = 0; // write valid
end
initial $timeformat(-9, 0, " ns", 8);
/**
* Generate system clock for the AXI BUS
*/
always #5 begin
sys_clk <= ~ sys_clk;
end
/**
* Reset sequence: assert reset and release it.
*/
task reset_sequence;
begin
rst_n = 0;
spi_select = 1;
#20
rst_n = 1;
#20 begin end
end
endtask
/**
* axi_read_data() task read 32 bits of data from the AXI2SPI bridge.
*/
task axi_read_data;
input [31:0] target_address;
begin
fork
begin
$display("axi_read_data:: ADDR_WRITE. q_AXI_araddr, target_address %h , w_AXI_arready, q_AXI_arvalid ", target_address);
@(posedge sys_clk)
q_AXI_araddr <= target_address;
q_AXI_arvalid <= 1'b1;
if(w_AXI_arready !== 1'b1) begin: wait_for_ready_ADW
forever @(posedge sys_clk) begin
if(w_AXI_arready == 1'b1)
disable wait_for_ready_ADW;
end
end
q_AXI_arvalid <= 1'b0;
end
begin
// $display("axi_read_data:: WRITE_DATA. qq_AXI_wdata, data_to_write %h , w_AXI_wready, q_AXI_wvalid ", data_to_write);
// @(posedge sys_clk)
// q_AXI_wdata <= data_to_write;
// q_AXI_wvalid <= 1'b1;
// if(w_AXI_wready !== 1'b1) begin: wait_for_ready_WD
// forever @(posedge sys_clk) begin
// if(w_AXI_wready == 1'b1)
// disable wait_for_ready_WD;
// end
// end
// q_AXI_wvalid <= 1'b0;
end
join;
$display("END ");
end
endtask
/**
* axi_write_data() task writes 32 bits of data to the AXI2SPI bridge.
*/
task axi_write_data;
input [31:0] data_to_write;
input [31:0] target_address;
begin
fork
begin
$display("axi_write_data:: ADDR_WRITE. q_AXI_awaddr, target_address %h , w_AXI_awready, q_AXI_awvalid ", target_address);
@(posedge sys_clk)
q_AXI_awaddr <= target_address;
q_AXI_awvalid <= 1'b1;
if(w_AXI_awready !== 1'b1) begin: wait_for_ready_ADW
forever @(posedge sys_clk) begin
if(w_AXI_awready == 1'b1)
disable wait_for_ready_ADW;
end
end
q_AXI_awvalid <= 1'b0;
end
begin
$display("axi_write_data:: WRITE_DATA. qq_AXI_wdata, data_to_write %h , w_AXI_wready, q_AXI_wvalid ", data_to_write);
@(posedge sys_clk)
q_AXI_wdata <= data_to_write;
q_AXI_wvalid <= 1'b1;
if(w_AXI_wready !== 1'b1) begin: wait_for_ready_WD
forever @(posedge sys_clk) begin
if(w_AXI_wready == 1'b1)
disable wait_for_ready_WD;
end
end
q_AXI_wvalid <= 1'b0;
end
join;
$display("END ");
end
endtask
/**
*
task _axi_channel_write_;
input [31:0] data_to_write;
input integer channel_id;
begin
case (channel_id)
ADDR_READ: begin
$display("_axi_channel_write_:: ADDR_READ. q_AXI_araddr, data_to_write: %h w_AXI_arready q_AXI_arvalid ", data_to_write);
@(posedge sys_clk)
q_AXI_araddr <= data_to_write;
q_AXI_arvalid <= 1'b1;
if(w_AXI_arready !== 1'b1) begin
forever @(posedge sys_clk) begin: wait_for_ready
if(w_AXI_arready == 1'b1)
disable wait_for_ready;
end
end
q_AXI_arvalid <= 1'b0;
// _axi_channel_write2_(q_AXI_araddr, data_to_write, w_AXI_arready, q_AXI_arvalid);
end
ADDR_WRITE: begin
$display("_axi_channel_write_:: ADDR_WRITE. q_AXI_awaddr, data_to_write %h , w_AXI_awready, q_AXI_awvalid ", data_to_write);
@(posedge sys_clk)
q_AXI_awaddr <= data_to_write;
q_AXI_awvalid <= 1'b1;
if(w_AXI_awready !== 1'b1) begin
forever @(posedge sys_clk) begin: wait_for_ready_ADW
if(w_AXI_awready == 1'b1)
disable wait_for_ready_ADW;
end
end
q_AXI_awvalid <= 1'b0;
// _axi_channel_write2_(q_AXI_awaddr, data_to_write, w_AXI_awready, q_AXI_awvalid);
end
WRITE_DATA: begin
$display("_axi_channel_write_:: WRITE_DATA. qq_AXI_wdata, data_to_write %h , w_AXI_wready, q_AXI_wvalid ", data_to_write);
@(posedge sys_clk)
q_AXI_wdata <= data_to_write;
q_AXI_wvalid <= 1'b1;
if(w_AXI_wready !== 1'b1) begin
forever @(posedge sys_clk) begin: wait_for_ready_WD
if(w_AXI_wready == 1'b1)
disable wait_for_ready_WD;
end
end
q_AXI_wvalid <= 1'b0;
//_axi_channel_write2_(q_AXI_wdata, data_to_write, w_AXI_wready, q_AXI_wvalid);
end
READ_DATA: begin
$display("ERROR: read write");
end
RESPONSE: begin
$display("ERROR: response write");
end
endcase
end
endtask
*/
/**
*
*/
task _axi_channel_write2_;
output [31:0] channel_data; // read address address (data)
input [31:0] data_to_write;
input channel_ready; // read address ready
output channel_valid; // read address valid
begin
@(posedge sys_clk)
channel_data <= data_to_write;
$display("%t _axi_channel_write2_:: ENTER data_to_write: %h", $time, data_to_write);
$display("_axi_channel_write2_:: ENTER channel_data: %h", channel_data);
channel_valid <= 1'b1;
if(channel_ready !== 1'b1) begin
forever @(posedge sys_clk) begin: wait_for_ready
if(channel_ready == 1'b1)
disable wait_for_ready;
end
end
channel_valid <= 1'b0;
#0ns
$display("_axi_channel_write2_:: LEAVE");
end
endtask
/**
* Monitor the axi
*/
task axi_monitor_read;
begin
$display("axi_monitor_read:: ENTER");
fork
forever @ (w_AXI_rvalid) begin
q_AXI_rready <= w_AXI_rvalid;
end
forever @ (posedge sys_clk) begin: wait_for_valid
if(w_AXI_rvalid == 1'b1) begin
$display("Data got from AXI read: %h ", w_AXI_rdata);
end
end
join;
$display("axi_monitor_read:: LEAVE");
end
endtask
task eeprom_write_enable;
begin
$display("eeprom_write_enable:: ENTER");
#500ns
spi_select <= '0;
#500ns
// Write command of EEPROM
axi_write_data(
.target_address(`ADDR_DATA_REG),
.data_to_write(8'h06) // Write
);
#3us
spi_select <= '1;
#10us
$display("eeprom_write_enable:: LEAVE");
end
endtask
/**
* write_eeprom
*/
task write_eeprom;
input [7:0] eeprom_address;
input [7:0] eeprom_datas[];
input integer number_of_datas;
begin
$display("write_eeprom:: ENTER");
eeprom_write_enable();
spi_select <= '0;
#500ns
// Write command of EEPROM
axi_write_data(
.target_address(`ADDR_DATA_REG),
.data_to_write(8'h02) // Write
);
// wait(w_IRQ == 1);
#3us
// Write address of EEPROM
axi_write_data(
.target_address(`ADDR_DATA_REG),
.data_to_write(eeprom_address) //
);
for (int i = 0; i< number_of_datas; i++) begin
#3us
// data of eeprom
axi_write_data(
.target_address(`ADDR_DATA_REG),
.data_to_write(eeprom_datas[i]) //
);
end
#3us
spi_select <= '1;
$display("write_eeprom :: Wait for eeprom write time...");
#10us
$display("write_eeprom:: LEAVE");
end
endtask
/**
* read_eeprom
*/
task read_eeprom;
input [7:0] eeprom_address;
input integer count_of_bytes;
begin
spi_select <= '0;
#500ns
// send REad command of EEPROM
axi_write_data(
.target_address(`ADDR_DATA_REG),
.data_to_write(8'h03) // read
);
// wait(w_IRQ == 1);
#3us
// send REad address of EEPROM
axi_write_data(
.target_address(`ADDR_DATA_REG),
.data_to_write(eeprom_address) //
);
#3us
for (int i = 0; i< count_of_bytes; i++) begin
// send dummy 0x00 to read data
axi_write_data(
.target_address(`ADDR_DATA_REG),
.data_to_write(0) //
);
#3us
// send dummy 0x00 to read data
axi_read_data(
.target_address(`ADDR_DATA_REG)
);
end
#3us
spi_select <= '1;
#500ns begin end
end
endtask
/**
* init_spi_periperal
*/
task init_spi_periperal;
begin
$display("init_spi_periperal:: ENTER");
axi_write_data(
.target_address(`ADDR_CONTROL_REG),
.data_to_write(8'b1101_0010) // SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0
);
$display("init_spi_periperal:: LEAVE");
end
endtask
/******************************************************************************
*
******************************************************************************/
initial begin
#50ns
reset_sequence();
#50ns
init_spi_periperal();
#50ns
fork
axi_monitor_read();
join_none;
#50ns
write_eeprom(4, {8'haa, 8'hff, 8'h00, 8'h55, 8'hc3, 8'h3c}, 6);
#50ns
read_eeprom(4, 6);
#50ns
begin end
end
endmodule
|
module testbench_8 ();
parameter START_ADDR = 32'h8002_0000; // h80020000
reg clk;
reg [31:0] addr;
reg [31:0] din;
reg enable;
reg rw;
reg [1:0] access_size;
reg test_mode;
reg [31:0] int_addr;
wire [31:0] dout;
wire busy;
mips_memory2 test_memory(.clk(clk),
.addr(addr),
.din(din),
.dout(dout),
.access_size(access_size),
.rw(rw),
.busy(busy),
.enable(enable));
reg [7:0] mem[0:256];
initial
begin
clk = 1'b0;
enable = 1'b0;
addr = 32'h8002_0000;
din = 32'b0000_0000;
rw = 1'b1;
access_size = 2'b10;
test_mode = 0;
int_addr = 0;
$readmemh("SumArray.x", mem);
end
always @(negedge clk)
begin
if ((addr + int_addr) > 32'h8002_00b4 & test_mode == 0)
begin
enable = 0;
if (busy == 0)
begin
enable = 1;
test_mode = 1;
addr = 32'h8002_0000;
rw = 1'b0;
int_addr = 4;
end
end
else
begin
if (test_mode == 0)
begin
enable = 1'b1;
din[31:24] = mem[addr + int_addr - START_ADDR];
din[23:16] = mem[addr + int_addr + 1 - START_ADDR];
din[15:8] = mem[addr + int_addr + 2 - START_ADDR];
din[7:0] = mem[addr + int_addr + 3 - START_ADDR];
int_addr = int_addr + 32'h0000_0004;
if (int_addr == 36)
begin
addr = addr + 32'h0000_0020;
int_addr = 4;
end
end
else
begin
enable = 1'b1;
int_addr = int_addr + 32'h0000_0004;
if (int_addr == 36)
begin
addr = addr + 32'h0000_0020;
int_addr = 4;
end
end
end
end
always
#5 clk = !clk;
endmodule
|
`timescale 1ns / 1ps
// Name: WcaDownConverter_stimulus.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
`include "../wca/hal/WcaHalRegisterDefs.vh" //grab register addresses.
`include "../containers/4ChTxRxRegisterDefs.vh"
module WcaDownConverter_stimulus;
parameter SYSCLK_PERIOD = 10.0; // 100 MHz
parameter DSPCLK_PERIOD = 1000.0/128.0; //128 MHz
parameter LIMECLK_PERIOD = 1000.0/64.0; // 64 MHz
parameter CPUCLK_PERIOD = 1000.0/32.0; // 32 MHz
parameter RESET_START = 5*CPUCLK_PERIOD;
parameter EVENT_MASK = 8'h02; // LSDP0, LSDP1;
parameter LSDP_ENABLE = 8'h20; //Enables LSDP0 and LSDP1.
parameter LSDP_RESET = 8'h02; //Resets LSDP0 and LSDP1.
parameter RF0_CTRL_FLAGS = 8'hF5; //Set the RX IQ to rx and Txd Data.,
parameter RX_SAMP_DELAY = 1; // Six nanoseconds
`define DDC0_CTRL (`WCACOMP_DSP_DDC0 + `DSP_DDUC_CTRL)
/////////////////////////////////////////
// Wires and registers
/////////////////////////////////////////
reg reset, cpuclk, dspclk, limeclk, comp_reset;
reg sysclk;
reg [23:0] iq_in;
wire [31:0] iq_out;
wire dstrobe_out;
// Bidirs
reg [11:0] rbusCtrl;
wire [7:0] rbusData;
//CPU I/O and Processing Signals
reg [7:0] adata; //Address set register
reg [7:0] rdata; //Read bus result register.
reg [7:0] wdata; //write data register.
wire [7:0] dbus; //CPU data bus
reg address, write, read; //address,write, read control lines.
//////////////////////////////////////////////////////////////////////
// WCA HAL Functions
//////////////////////////////////////////////////////////////////////
reg [11:0] rf0_rxd;
reg rf0_rxiqsel;
wire rf0_rxclk, rf0_rxen, rf0_txclk, rf0_txiqsel, rf0_txen;
wire [11:0] rf0_txd;
wire [23:0] rx0_iq;
wire [23:0] tx0_iq;
wire rx0_strobe, tx0_strobe, rx1_strobe, tx1_strobe;
//////////////////////////////////////////////////////////////////////
// Downconverter Test.
//////////////////////////////////////////////////////////////////////
WcaRegBus cpuif (
.clock(sysclk),
.reset(reset),
.address(address),
.write(write),
.read(read),
.dbus(dbus),
.rbusCtrl(rbusCtrl),
.rbusData(rbusData)
);
wire [7:0] ddc0_ctrl;
WcaWriteByteReg #(`DDC0_CTRL) wr_ddc0_ctrl
(.reset(reset),
.out( ddc0_ctrl),
.rbusCtrl(rbusCtrl), .rbusData(rbusData) );
// Instantiate the Unit Under Test (UUT)
WcaDownConverter uut (
.clock(dspclk),
.reset(reset),
.enable(ddc0_ctrl[0]),
.aclr( ddc0_ctrl[1]),
.dstrobe_in(rx0_strobe),
.cfgflags(ddc0_ctrl[5:2]),
.iq_in(rx0_iq),
.iq_out(iq_out),
.dstrobe_out(dstrobe_out),
.rbusCtrl(rbusCtrl),
.rbusData(rbusData)
);
// Lime RF#1 Interface implementation.
WcaLimeIF #( `WCAHAL_RF0_CTRL, `WCAHAL_RF0_RSSI, `WCAHAL_RF0_BIAS)
lime1_if ( .clock_dsp(dspclk), .clock_rx(limeclk), .clock_tx(limeclk), .reset(reset),
.rbusCtrl(rbusCtrl),.rbusData(rbusData),
.rf_rxclk(rf0_rxclk), .rf_rxiqsel(rf0_rxiqsel), .rf_rxen(rf0_rxen), .rf_rxdata(rf0_rxd[11:0]),
.rf_txclk(rf0_txclk), .rf_txiqsel(rf0_txiqsel), .rf_txen(rf0_txen), .rf_txdata(rf0_txd[11:0]),
.rx_strobe( rx0_strobe), .rx_iq(rx0_iq), .tx_strobe( tx0_strobe), .tx_iq( tx0_iq) );
//////////////////////////////////////////////////////////////////////
// Lime signals simulations
//////////////////////////////////////////////////////////////////////
//NOTE limeclk is used to drive these simulation timings,
//since the others are not set up during the reset.
reg [11:0] rx0_count;
always @(posedge rf0_rxclk)
begin
if(reset) rx0_count <= 12'h0;
else if( rf0_rxiqsel) rx0_count <= rx0_count + 12'h1;
end
//Simulate the RF0 iqselection.
always @(posedge rf0_rxclk)
begin
if( reset) #(RX_SAMP_DELAY)
begin
rf0_rxiqsel <= 1'h0;
rf0_rxd <= 12'h0;
end
else if( rf0_rxen) #(RX_SAMP_DELAY)
begin
rf0_rxiqsel <= ~rf0_rxiqsel;
rf0_rxd <= (rf0_rxiqsel) ? 12'h17F : 12'hF81;
end
end
//////////////////////////////////////////////////////////////////////
// Simulation
//////////////////////////////////////////////////////////////////////
initial begin
//Set initial state of clocks lime interface related regisers.
#0
sysclk = 1;
dspclk=1;
limeclk = 1;
rf0_rxiqsel <= 1'h0;
rf0_rxd <= 12'h0;
rx0_count <=12'h0;
end
initial begin
//Set initial state of CPU related registers.
#0
cpuclk = 1;
address = 0;
write = 0;
read = 0;
wdata = 8'hEF;
reset = 1'b0;
comp_reset = 1'b0;
//Reset the part.
#(RESET_START) reset = 1'b1;
#(CPUCLK_PERIOD*3) reset = 1'b0;
//Reset the HdwComponent after the main reset.
#(CPUCLK_PERIOD*10) comp_reset = 1'b1;
#(CPUCLK_PERIOD*3) comp_reset = 1'b0;
//Set the Sampling Control on RF1 to receive RF and transmit DSP.
#(CPUCLK_PERIOD * 4) adata = `WCAHAL_RF0_CTRL;
#(CPUCLK_PERIOD) address = 1'b1;
#(CPUCLK_PERIOD) address= 1'b0;
#(CPUCLK_PERIOD) wdata = RF0_CTRL_FLAGS;
#(CPUCLK_PERIOD) write = 1'b1;
#(CPUCLK_PERIOD) write = 1'b0;
end
//////////////////////////////////////////////////////////////////////
// CPU Addressing Simluator
//////////////////////////////////////////////////////////////////////
//Set up Registers for controlling and databus.
assign dbus = (address) ? adata : (write) ? wdata : 8'bz;
always @(posedge cpuclk)
begin
if( reset)
rdata <= 8'h0;
else if( read)
rdata <= dbus;
end
//////////////////////////////////////////////////////////////////////
// Clocks
//////////////////////////////////////////////////////////////////////
always @(sysclk )
#(SYSCLK_PERIOD / 2.0) sysclk <= !sysclk;
always @(cpuclk )
#(CPUCLK_PERIOD / 2.0) cpuclk <= !cpuclk;
always @(dspclk)
#(DSPCLK_PERIOD / 2.0) dspclk<= !dspclk;
always @( posedge dspclk)
limeclk <= !limeclk;
endmodule
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- Implements store FIFO. Serves as a bridge between the processor core & --
// -- the memory interface. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_wb_adapter #(parameter DEPTH = 32) (
// Clock.
input wire i_clk,
input wire i_reset,
// Processor Wishbone interface. These come from the Wishbone registered
// interface.
input wire I_WB_CYC,
input wire I_WB_STB,
input wire [3:0] I_WB_SEL,
input wire [2:0] I_WB_CTI,
input wire [31:0] I_WB_ADR,
input wire [31:0] I_WB_DAT,
input wire I_WB_WE,
output reg [31:0] O_WB_DAT,
output reg O_WB_ACK,
// Wishbone interface.
output reg o_wb_cyc,
output reg o_wb_stb,
output wire [31:0] o_wb_dat,
output wire [31:0] o_wb_adr,
output wire [3:0] o_wb_sel,
output wire [2:0] o_wb_cti,
output wire o_wb_we,
input wire [31:0] i_wb_dat,
input wire i_wb_ack,
output reg o_wb_stb_nxt,
output reg o_wb_cyc_nxt,
output wire [3:0] o_wb_sel_nxt,
output wire [31:0] o_wb_dat_nxt,
output wire [31:0] o_wb_adr_nxt,
output wire o_wb_we_nxt
);
`include "zap_defines.vh"
`include "zap_localparams.vh"
reg fsm_write_en;
reg [69:0] fsm_write_data;
wire w_eob;
wire w_full;
wire w_eob_nxt;
assign o_wb_cti = {w_eob, 1'd1, w_eob};
wire w_emp;
// {SEL, DATA, ADDR, EOB, WEN} = 4 + 64 + 1 + 1 = 70 bit.
zap_sync_fifo #(.WIDTH(70), .DEPTH(DEPTH), .FWFT(1'd0), .PROVIDE_NXT_DATA(1)) U_STORE_FIFO (
.i_clk (i_clk),
.i_reset (i_reset),
.i_ack ((i_wb_ack && o_wb_stb) || emp_ff),
.i_wr_en (fsm_write_en),
.i_data (fsm_write_data),
.o_data ({o_wb_sel, o_wb_dat, o_wb_adr, w_eob, o_wb_we}),
.o_data_nxt ({o_wb_sel_nxt, o_wb_dat_nxt, o_wb_adr_nxt, w_eob_nxt, o_wb_we_nxt}),
.o_empty (w_emp),
.o_full (w_full),
.o_empty_n (),
.o_full_n (),
.o_full_n_nxt ()
);
reg emp_nxt;
reg emp_ff;
reg [31:0] ctr_nxt, ctr_ff;
reg [31:0] dff, dnxt;
reg ack; // ACK write channel.
reg ack_ff; // Read channel.
localparam IDLE = 0;
localparam PRPR_RD_SINGLE = 1;
localparam PRPR_RD_BURST = 2;
localparam WRITE = 3;
localparam WAIT1 = 5;
localparam WAIT2 = 6;
localparam NUMBER_OF_STATES = 7;
reg [$clog2(NUMBER_OF_STATES)-1:0] state_ff, state_nxt;
// FIFO pipeline register and nxt state logic.
always @ (*)
begin
emp_nxt = emp_ff;
o_wb_stb_nxt = o_wb_stb;
o_wb_cyc_nxt = o_wb_cyc;
if ( i_reset )
begin
emp_nxt = 1'd1;
o_wb_stb_nxt = 1'd0;
o_wb_cyc_nxt = 1'd0;
end
else if ( emp_ff || (i_wb_ack && o_wb_stb) )
begin
emp_nxt = w_emp;
o_wb_stb_nxt = !w_emp;
o_wb_cyc_nxt = !w_emp;
end
end
always @ (posedge i_clk)
begin
emp_ff <= emp_nxt;
o_wb_stb <= o_wb_stb_nxt;
o_wb_cyc <= o_wb_cyc_nxt;
end
// Flip flop clocking block.
always @ (posedge i_clk)
begin
if ( i_reset )
begin
state_ff <= IDLE;
ctr_ff <= 0;
dff <= 0;
end
else
begin
state_ff <= state_nxt;
ctr_ff <= ctr_nxt;
dff <= dnxt;
end
end
// Reads from the Wishbone bus are flopped.
always @ (posedge i_clk)
begin
if ( i_reset )
begin
ack_ff <= 1'd0;
O_WB_DAT <= 0;
end
else if ( !o_wb_we && o_wb_cyc && o_wb_stb && i_wb_ack )
begin
ack_ff <= 1'd1;
O_WB_DAT <= i_wb_dat;
end
else
begin
ack_ff <= 1'd0;
end
end
localparam BURST_LEN = 4;
// OR from flop and mealy FSM output.
always @* O_WB_ACK = ack_ff | ack;
// State machine.
always @*
begin:blk1
reg [31:0] adr;
adr = 0;
state_nxt = state_ff;
ctr_nxt = ctr_ff;
ack = 0;
dnxt = dff;
fsm_write_en = 0;
fsm_write_data = 0;
case(state_ff)
IDLE:
begin
ctr_nxt = 0;
dnxt = 0;
if ( I_WB_STB && I_WB_WE && !o_wb_stb ) // Wishbone write request
begin
// Simply buffer stores into the FIFO.
state_nxt = WRITE;
end
else if ( I_WB_STB && !I_WB_WE && !o_wb_stb ) // Wishbone read request
begin
// Write a set of reads into the FIFO.
if ( I_WB_CTI == CTI_BURST ) // Burst of 4 words. Each word is 4 byte.
begin
state_nxt = PRPR_RD_BURST;
end
else // Single.
begin
state_nxt = PRPR_RD_SINGLE;
end
end
end
PRPR_RD_SINGLE: // Write a single read token into the FIFO.
begin
if ( !w_full )
begin
state_nxt = WAIT1;
fsm_write_en = 1'd1;
fsm_write_data = { I_WB_SEL,
I_WB_DAT,
I_WB_ADR,
I_WB_CTI != CTI_BURST ? 1'd1 : 1'd0,
1'd0};
end
end
PRPR_RD_BURST: // Write burst read requests into the FIFO.
begin
if ( O_WB_ACK )
begin
dnxt = dff + 1'd1;
end
if ( ctr_ff == BURST_LEN * 4 )
begin
ctr_nxt = 0;
state_nxt = WAIT2; // FIFO prep done.
end
else if ( !w_full )
begin
adr = {I_WB_ADR[31:4], 4'd0} + ctr_ff; // Ignore lower 4-bits.
fsm_write_en = 1'd1;
fsm_write_data = { I_WB_SEL,
I_WB_DAT,
adr,
ctr_ff == 12 ? 1'd1 : 1'd0,
1'd0 };
ctr_nxt = ctr_ff + 4;
end
end
WRITE:
begin
// As long as requests exist, write them out to the FIFO.
if ( I_WB_STB && I_WB_WE )
begin
if ( !w_full )
begin
fsm_write_en = 1'd1;
fsm_write_data = {I_WB_SEL, I_WB_DAT, I_WB_ADR, I_WB_CTI != CTI_BURST ? 1'd1 : 1'd0, 1'd1};
ack = 1'd1;
end
end
else // Writes done!
begin
state_nxt = IDLE;
end
end
WAIT1: // Wait for single read to complete.
begin
if ( O_WB_ACK )
begin
state_nxt = IDLE;
end
end
WAIT2: // Wait for burst reads to complete.
begin
if ( O_WB_ACK )
begin
dnxt = dff + 1;
end
if ( dff == BURST_LEN && !o_wb_stb )
begin
state_nxt = IDLE;
end
end
endcase
end
endmodule
`default_nettype wire
// ----------------------------------------------------------------------------
// EOF
// ----------------------------------------------------------------------------
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:11:22 11/09/2016
// Design Name:
// Module Name: background_painter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module background_painter(
input wire [9:0] hpos,
input wire [8:0] vpos,
input wire [11:0] code,
// input wire [32:0] num_a,
// input wire [32:0] num_b,
input wire [32:0] resultado,
input wire [4:0] res_out_code,
output reg [2:0] res_in_row,
output reg [3:0] num_salida,
output reg [3:0] out_row,
output reg [1:0] row,
output reg [2:0] column,
output reg [7:0] rgb
);
parameter [7:0]white = 8'b11111111;
parameter [7:0]gray = 8'b10010010;
parameter [7:0]blue = 8'b00000011;
parameter [7:0]black = 8'b00000000;
reg [3:0] col;
reg [3:0] exponente;
reg [29:0] tmp;
always @(*)
begin
if (vpos >= 204 && vpos < 228) //fila 0
begin
row = 0;
out_row = {(vpos - 204) / 2}[3:0];
end
else if(vpos >= 248 && vpos < 272) //fila 1
begin
row = 1;
out_row = {(vpos - 248) / 2}[3:0];
end
else if(vpos >= 292 && vpos < 316) //fila 2
begin
row = 2;
out_row = {(vpos - 292) / 2}[3:0];
end
else
begin
row = 3;
out_row = 0;
end
if (hpos >= 220 && hpos < 244) //columna 0
begin
column = 0;
col = {(hpos - 220) / 2}[3:0];
end
else if(hpos >= 264 && hpos < 288) //columna 1
begin
column = 1;
col = {(hpos - 264) / 2}[3:0];
end
else if(hpos >= 308 && hpos < 332) //columna 2
begin
column = 2;
col = {(hpos - 308) / 2}[3:0];
end
else if(hpos >= 352 && hpos < 376) //columna 3
begin
column = 3;
col = {(hpos - 352) / 2}[3:0];
end
else if(hpos >= 396 && hpos < 420) //columna 4
begin
column = 4;
col = {(hpos - 396) / 2}[3:0];
end
else if(hpos >= 440 && hpos < 462) //columna 5
begin
column = 5;
col = {(hpos - 440) / 2}[3:0];
end
else //ninguna fila
begin
column = 6;
col = 0;
end
end
always @(*)
begin
if ((hpos >= 260 && hpos < 420) && (vpos >= 172 && vpos < 184))
begin
res_in_row = {(vpos - 172)/2}[2:0];
exponente = {(9 - ((hpos - 260)/16))}[3:0];
case (exponente)
4'b0000: tmp = 1;
4'b0001: tmp = 10;
4'b0010: tmp = 100;
4'b0011: tmp = 1000;
4'b0100: tmp = 10000;
4'b0101: tmp = 100000;
4'b0110: tmp = 1000000;
4'b0111: tmp = 10000000;
4'b1000: tmp = 100000000;
4'b1001: tmp = 1000000000;
default: tmp = 1;
endcase
/*if(vpos >= 124 && vpos < 136)
begin
num_salida = (num_a[31:0] / tmp) % 10;
if(((hpos - 260)%16 < 10) && res_out_code[((hpos - 260)%16)/2])
rgb = black;
else
rgb = gray;
end
else if(vpos >= 148 && vpos < 160)
begin
num_salida = (num_b[31:0] / tmp) % 10;
if(((hpos - 260)%16 < 10) && res_out_code[((hpos - 260)%16)/2])
rgb = black;
else
rgb = gray;
end
else*/ //if(vpos >= 172 && vpos < 184)
//begin
num_salida = (resultado[31:0] / tmp) % 10;
if(((hpos - 260)%16 < 10) && res_out_code[((hpos - 260)%16)/2])
rgb = black;
else
rgb = gray;
/*end
else
begin
num_salida = 0;
rgb = gray;
end*/
end
else if(hpos >= 250 && hpos < 256)
begin
num_salida = 0;
res_in_row = 0;
if (/*(vpos >= 124 && vpos < 136 && num_a[32])
|| (vpos >= 148 && vpos < 160 && num_b[32])
|| */(vpos >= 176 && vpos < 178 && resultado[32]))
rgb = black;
else
rgb = gray;
end
else if((row < 2 && column < 6) || (row == 2 && column < 5))
begin
res_in_row = 0;
if(code[col])
begin
rgb = white;
end
else
begin
rgb = blue;
end
num_salida = 0;
end
else
begin
num_salida = 0;
res_in_row = 0;
rgb = gray;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PKG_SN_TB_V
`define SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PKG_SN_TB_V
/**
* udp_dlatch$PR_pp$PKG$sN: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dlatch_pr_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg NOTIFIER;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER = 1'b0;
#80 RESET = 1'b0;
#100 SLEEP_B = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 KAPWR = 1'b1;
#200 NOTIFIER = 1'b1;
#220 RESET = 1'b1;
#240 SLEEP_B = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 KAPWR = 1'b0;
#340 NOTIFIER = 1'b0;
#360 RESET = 1'b0;
#380 SLEEP_B = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 SLEEP_B = 1'b1;
#500 RESET = 1'b1;
#520 NOTIFIER = 1'b1;
#540 KAPWR = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 SLEEP_B = 1'bx;
#640 RESET = 1'bx;
#660 NOTIFIER = 1'bx;
#680 KAPWR = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_lp__udp_dlatch$PR_pp$PKG$sN dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PKG_SN_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311A_4_V
`define SKY130_FD_SC_HS__O311A_4_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o311a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o311a_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311A_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1N_BLACKBOX_V
`define SKY130_FD_SC_LP__INPUTISO1N_BLACKBOX_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputiso1n (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1N_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S18KAPWR_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYBUF4S18KAPWR_PP_BLACKBOX_V
/**
* dlybuf4s18kapwr: Delay Buffer 4-stage 0.18um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s18kapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S18KAPWR_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR2_4_V
`define SKY130_FD_SC_HS__XOR2_4_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xor2_4 (
X ,
A ,
B ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xor2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR2_4_V
|
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// mv_read O 64
// mav_write O 64
// mv_sip_read O 64
// mav_sip_write O 64
// CLK I 1 clock
// RST_N I 1 reset
// mav_write_misa I 28
// mav_write_wordxl I 64
// mav_sip_write_misa I 28
// mav_sip_write_wordxl I 64
// m_external_interrupt_req_req I 1 reg
// s_external_interrupt_req_req I 1 reg
// software_interrupt_req_req I 1 reg
// timer_interrupt_req_req I 1 reg
// EN_reset I 1
// EN_mav_write I 1
// EN_mav_sip_write I 1
//
// Combinational paths from inputs to outputs:
// (mav_write_misa, mav_write_wordxl) -> mav_write
// (mav_sip_write_misa, mav_sip_write_wordxl) -> mav_sip_write
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCSR_MIP(CLK,
RST_N,
EN_reset,
mv_read,
mav_write_misa,
mav_write_wordxl,
EN_mav_write,
mav_write,
mv_sip_read,
mav_sip_write_misa,
mav_sip_write_wordxl,
EN_mav_sip_write,
mav_sip_write,
m_external_interrupt_req_req,
s_external_interrupt_req_req,
software_interrupt_req_req,
timer_interrupt_req_req);
input CLK;
input RST_N;
// action method reset
input EN_reset;
// value method mv_read
output [63 : 0] mv_read;
// actionvalue method mav_write
input [27 : 0] mav_write_misa;
input [63 : 0] mav_write_wordxl;
input EN_mav_write;
output [63 : 0] mav_write;
// value method mv_sip_read
output [63 : 0] mv_sip_read;
// actionvalue method mav_sip_write
input [27 : 0] mav_sip_write_misa;
input [63 : 0] mav_sip_write_wordxl;
input EN_mav_sip_write;
output [63 : 0] mav_sip_write;
// action method m_external_interrupt_req
input m_external_interrupt_req_req;
// action method s_external_interrupt_req
input s_external_interrupt_req_req;
// action method software_interrupt_req
input software_interrupt_req_req;
// action method timer_interrupt_req
input timer_interrupt_req_req;
// signals for module outputs
wire [63 : 0] mav_sip_write, mav_write, mv_read, mv_sip_read;
// register rg_meip
reg rg_meip;
wire rg_meip$D_IN, rg_meip$EN;
// register rg_msip
reg rg_msip;
wire rg_msip$D_IN, rg_msip$EN;
// register rg_mtip
reg rg_mtip;
wire rg_mtip$D_IN, rg_mtip$EN;
// register rg_seip
reg rg_seip;
wire rg_seip$D_IN, rg_seip$EN;
// register rg_ssip
reg rg_ssip;
reg rg_ssip$D_IN;
wire rg_ssip$EN;
// register rg_stip
reg rg_stip;
wire rg_stip$D_IN, rg_stip$EN;
// register rg_ueip
reg rg_ueip;
reg rg_ueip$D_IN;
wire rg_ueip$EN;
// register rg_usip
reg rg_usip;
reg rg_usip$D_IN;
wire rg_usip$EN;
// register rg_utip
reg rg_utip;
wire rg_utip$D_IN, rg_utip$EN;
// rule scheduling signals
wire CAN_FIRE_m_external_interrupt_req,
CAN_FIRE_mav_sip_write,
CAN_FIRE_mav_write,
CAN_FIRE_reset,
CAN_FIRE_s_external_interrupt_req,
CAN_FIRE_software_interrupt_req,
CAN_FIRE_timer_interrupt_req,
WILL_FIRE_m_external_interrupt_req,
WILL_FIRE_mav_sip_write,
WILL_FIRE_mav_write,
WILL_FIRE_reset,
WILL_FIRE_s_external_interrupt_req,
WILL_FIRE_software_interrupt_req,
WILL_FIRE_timer_interrupt_req;
// remaining internal signals
wire [11 : 0] new_mip__h528, new_mip__h946;
wire seip__h562,
ssip__h566,
ssip__h986,
stip__h564,
ueip__h563,
ueip__h985,
usip__h567,
usip__h987,
utip__h565;
// action method reset
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// value method mv_read
assign mv_read = { 52'd0, new_mip__h528 } ;
// actionvalue method mav_write
assign mav_write = { 52'd0, new_mip__h946 } ;
assign CAN_FIRE_mav_write = 1'd1 ;
assign WILL_FIRE_mav_write = EN_mav_write ;
// value method mv_sip_read
assign mv_sip_read =
{ 54'd0,
rg_seip,
rg_ueip,
2'b0,
rg_stip,
rg_utip,
2'b0,
rg_ssip,
rg_usip } ;
// actionvalue method mav_sip_write
assign mav_sip_write =
{ 54'd0,
rg_seip,
ueip__h985,
2'b0,
rg_stip,
rg_utip,
2'b0,
ssip__h986,
usip__h987 } ;
assign CAN_FIRE_mav_sip_write = 1'd1 ;
assign WILL_FIRE_mav_sip_write = EN_mav_sip_write ;
// action method m_external_interrupt_req
assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;
// action method s_external_interrupt_req
assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;
// action method software_interrupt_req
assign CAN_FIRE_software_interrupt_req = 1'd1 ;
assign WILL_FIRE_software_interrupt_req = 1'd1 ;
// action method timer_interrupt_req
assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
assign WILL_FIRE_timer_interrupt_req = 1'd1 ;
// register rg_meip
assign rg_meip$D_IN = m_external_interrupt_req_req ;
assign rg_meip$EN = 1'b1 ;
// register rg_msip
assign rg_msip$D_IN = software_interrupt_req_req ;
assign rg_msip$EN = 1'b1 ;
// register rg_mtip
assign rg_mtip$D_IN = timer_interrupt_req_req ;
assign rg_mtip$EN = 1'b1 ;
// register rg_seip
assign rg_seip$D_IN = s_external_interrupt_req_req ;
assign rg_seip$EN = 1'b1 ;
// register rg_ssip
always@(EN_reset or
EN_mav_write or ssip__h566 or EN_mav_sip_write or ssip__h986)
case (1'b1)
EN_reset: rg_ssip$D_IN = 1'd0;
EN_mav_write: rg_ssip$D_IN = ssip__h566;
EN_mav_sip_write: rg_ssip$D_IN = ssip__h986;
default: rg_ssip$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign rg_ssip$EN = EN_mav_write || EN_mav_sip_write || EN_reset ;
// register rg_stip
assign rg_stip$D_IN = !EN_reset && stip__h564 ;
assign rg_stip$EN = EN_mav_write || EN_reset ;
// register rg_ueip
always@(EN_reset or
EN_mav_write or ueip__h563 or EN_mav_sip_write or ueip__h985)
case (1'b1)
EN_reset: rg_ueip$D_IN = 1'd0;
EN_mav_write: rg_ueip$D_IN = ueip__h563;
EN_mav_sip_write: rg_ueip$D_IN = ueip__h985;
default: rg_ueip$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign rg_ueip$EN = EN_mav_write || EN_mav_sip_write || EN_reset ;
// register rg_usip
always@(EN_reset or
EN_mav_write or usip__h567 or EN_mav_sip_write or usip__h987)
case (1'b1)
EN_reset: rg_usip$D_IN = 1'd0;
EN_mav_write: rg_usip$D_IN = usip__h567;
EN_mav_sip_write: rg_usip$D_IN = usip__h987;
default: rg_usip$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign rg_usip$EN = EN_mav_write || EN_mav_sip_write || EN_reset ;
// register rg_utip
assign rg_utip$D_IN = !EN_reset && utip__h565 ;
assign rg_utip$EN = EN_mav_write || EN_reset ;
// remaining internal signals
assign new_mip__h528 =
{ rg_meip,
1'b0,
rg_seip,
rg_ueip,
rg_mtip,
1'b0,
rg_stip,
rg_utip,
rg_msip,
1'b0,
rg_ssip,
rg_usip } ;
assign new_mip__h946 =
{ rg_meip,
1'b0,
seip__h562,
ueip__h563,
rg_mtip,
1'b0,
stip__h564,
utip__h565,
rg_msip,
1'b0,
ssip__h566,
usip__h567 } ;
assign seip__h562 = mav_write_misa[18] && mav_write_wordxl[9] ;
assign ssip__h566 = mav_write_misa[18] && mav_write_wordxl[1] ;
assign ssip__h986 = mav_sip_write_misa[18] && mav_sip_write_wordxl[1] ;
assign stip__h564 = mav_write_misa[18] && mav_write_wordxl[5] ;
assign ueip__h563 = mav_write_misa[13] && mav_write_wordxl[8] ;
assign ueip__h985 = mav_sip_write_misa[13] && mav_sip_write_wordxl[8] ;
assign usip__h567 = mav_write_misa[13] && mav_write_wordxl[0] ;
assign usip__h987 = mav_sip_write_misa[13] && mav_sip_write_wordxl[0] ;
assign utip__h565 = mav_write_misa[13] && mav_write_wordxl[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_meip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_msip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_seip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_ssip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_stip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_ueip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_usip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_utip <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (rg_meip$EN) rg_meip <= `BSV_ASSIGNMENT_DELAY rg_meip$D_IN;
if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN;
if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN;
if (rg_seip$EN) rg_seip <= `BSV_ASSIGNMENT_DELAY rg_seip$D_IN;
if (rg_ssip$EN) rg_ssip <= `BSV_ASSIGNMENT_DELAY rg_ssip$D_IN;
if (rg_stip$EN) rg_stip <= `BSV_ASSIGNMENT_DELAY rg_stip$D_IN;
if (rg_ueip$EN) rg_ueip <= `BSV_ASSIGNMENT_DELAY rg_ueip$D_IN;
if (rg_usip$EN) rg_usip <= `BSV_ASSIGNMENT_DELAY rg_usip$D_IN;
if (rg_utip$EN) rg_utip <= `BSV_ASSIGNMENT_DELAY rg_utip$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_meip = 1'h0;
rg_msip = 1'h0;
rg_mtip = 1'h0;
rg_seip = 1'h0;
rg_ssip = 1'h0;
rg_stip = 1'h0;
rg_ueip = 1'h0;
rg_usip = 1'h0;
rg_utip = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkCSR_MIP
|
//
// bsg_tag_client
//
// simple serial on-chip configuration network
//
//
// 8/30/2016
//
// RESET SEMANTICS
//
// * NORMAL USAGE
//
// 0. wire bsg_tag_i.en high
// 1. assert reset on the send side of the module for at least one cycle (via bsg_tag_i)
// 2. clock the send side for one cycle.
// 3. clock the recv side for several cycles (for values to flush through synchronizers)
// 5. after resets are dropped, optionally start updating values on bsg_tag_s bus.
//
//
// * CLOCK GENERATOR NORMAL
//
// 0. follow steps 0-2 in NORMAL USAGE
// 1. pull bsg_tag_i.en low to disconnect bsg_tag
// 2. assert async_reset on clock gen
// 3. deassert async_reset on clock gen (clock starts)
// 4. after a few cycles
// 5. pull bsg_tag_i.en high to attach bsg_tag
//
// * CLOCK GENERATOR FAILSAFE
//
// 0. wire bsg_tag_i.en low
// 1. assert async_reset on clock gen
// 2. deassert async_reset
// 3. go
//
//
// note: operation of bsg_tag_i.en is only valid if there
// are no attempts to transmit data on bsg_tag at the same time
// otherwise it is a CDC violation.
`include "bsg_defines.v"
module bsg_tag_client
import bsg_tag_pkg::bsg_tag_s;
#(parameter `BSG_INV_PARAM(width_p), harden_p=1)
(
input bsg_tag_s bsg_tag_i
, input recv_clk_i
, output recv_new_r_o // optional; notifies of new value
, output [width_p-1:0] recv_data_r_o
);
localparam debug_level_lp = 1;
logic op_r, op_r_r, param_r;
always_ff @(posedge bsg_tag_i.clk)
begin
op_r <= bsg_tag_i.op;
param_r <= bsg_tag_i.param;
op_r_r <= op_r;
end
wire reset_op = ~op_r & param_r;
wire shift_op = op_r;
wire no_op = ~op_r & ~param_r;
// when this is high, tag_data_r is already transmitting data
// this control has another cycle of latency in this clock domain
// before passing into the next, which is important.
wire send_now = op_r_r & no_op;
logic [width_p-1:0] tag_data_r, recv_data_r, tag_data_n, tag_data_shift;
logic tag_toggle_r;
// shift in new state
if (width_p == 1)
begin : sb
assign tag_data_shift = { param_r };
end
else
begin : mb
assign tag_data_shift = { param_r, tag_data_r[width_p-1:1] };
end
bsg_mux2_gatestack #(.width_p(width_p),.harden_p(harden_p)) tag_data_mux
(.i0 (tag_data_r ) // sel=0
,.i1(tag_data_shift ) // sel=1
,.i2({ width_p {shift_op} }) // sel var
,.o (tag_data_n)
);
bsg_dff #(.width_p(width_p), .harden_p(harden_p)) tag_data_reg
(.clk_i(bsg_tag_i.clk)
,.data_i(tag_data_n)
,.data_o(tag_data_r)
);
// synopsys translate_off
if (debug_level_lp > 1)
always @(negedge bsg_tag_i.clk)
begin
if (reset_op & ~(~bsg_tag_i.op & bsg_tag_i.param))
$display("## bsg_tag_client (send) RESET DEASSERTED (%m)");
if (~reset_op & (~bsg_tag_i.op & bsg_tag_i.param))
$display("## bsg_tag_client (send) RESET ASSERTED (%m)");
if (send_now)
$display("## bsg_tag_client (send) SENDING %b (%m)",tag_data_r);
end
// synopsys translate_on
logic recv_toggle_r, recv_toggle_n;
// cross clock boundary
bsg_launch_sync_sync #(.width_p(1)) blss
(.iclk_i (bsg_tag_i.clk)
,.iclk_reset_i(reset_op)
,.iclk_data_i (tag_toggle_r ^ send_now)
,.iclk_data_o (tag_toggle_r) // this is the flop that is reset
,.oclk_i (recv_clk_i )
,.oclk_data_o(recv_toggle_n)
);
// note: bsg_tag_i.en is wired from off-chip and should be
// only toggled when there is no attempt to transmit data
wire recv_new = (recv_toggle_r ^ recv_toggle_n) & bsg_tag_i.en;
// we had to add recv_new_r_r to pipeline the receive logic
// and the fanout to the recv_data_r register at the maximum
// frequency on the chip (i.e. the clock generator)
logic recv_new_r, recv_new_r_r;
always_ff @(posedge recv_clk_i)
begin
recv_toggle_r <= recv_toggle_n;
recv_new_r <= recv_new;
recv_new_r_r <= recv_new_r;
end
bsg_dff_en #(.width_p(width_p),.harden_p(harden_p)) recv
(.clk_i(recv_clk_i)
,.en_i(recv_new_r)
,.data_i(tag_data_r)
,.data_o(recv_data_r)
);
// the recv_en_i signal has to come after the flop
// so this works even when the clock is not working
assign recv_new_r_o = recv_new_r_r & bsg_tag_i.en;
assign recv_data_r_o = recv_data_r;
endmodule
`BSG_ABSTRACT_MODULE(bsg_tag_client)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O31A_BEHAVIORAL_PP_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_TB_V
`define SKY130_FD_SC_HVL__OR2_TB_V
/**
* or2: 2-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__or2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hvl__or2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_TB_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06:51:17 11/29/2011
// Design Name: np_core
// Module Name: C:/Hari/Study/Masters_thesis/needtosee/altera_netfpga_08_08_11/Danai_proj/xilinx _test_localram/latest_code_nov20/to_send/ngnp_added_monitor/ngnp/src/testbench.v
// Project Name: np_core
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: np_core
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench();
// Inputs
reg out_rdy;
reg [63:0] in_data;
reg [7:0] in_ctrl;
reg in_wr;
reg reg_req_in;
reg reg_ack_in;
reg reg_rd_wr_L_in;
reg [22:0] reg_addr_in;
reg [31:0] reg_data_in;
reg [1:0] reg_src_in;
reg clk;
reg core_sp_clk;
reg reset;
reg packet_drop;
// Outputs
wire [63:0] out_data;
wire [7:0] out_ctrl;
wire out_wr;
wire in_rdy;
wire reg_req_out;
wire reg_ack_out;
wire reg_rd_wr_L_out;
wire [22:0] reg_addr_out;
wire [31:0] reg_data_out;
wire [1:0] reg_src_out;
wire [31:0] ppu_mem_addr;
// Instantiate the Unit Under Test (UUT)
np_core uut (
.out_data(out_data),
.out_ctrl(out_ctrl),
.out_wr(out_wr),
.out_rdy(out_rdy),
.in_data(in_data),
.in_ctrl(in_ctrl),
.in_wr(in_wr),
.in_rdy(in_rdy),
.reg_req_in(reg_req_in),
.reg_ack_in(reg_ack_in),
.reg_rd_wr_L_in(reg_rd_wr_L_in),
.reg_addr_in(reg_addr_in),
.reg_data_in(reg_data_in),
.reg_src_in(reg_src_in),
.reg_req_out(reg_req_out),
.reg_ack_out(reg_ack_out),
.reg_rd_wr_L_out(reg_rd_wr_L_out),
.reg_addr_out(reg_addr_out),
.reg_data_out(reg_data_out),
.reg_src_out(reg_src_out),
.clk(clk),
.core_sp_clk(clk),
.reset(reset),
.ppu_mem_addr(ppu_mem_addr),
.packet_drop(packet_drop)
);
initial begin
// Initialize Inputs
out_rdy = 0;
in_data = 0;
in_ctrl = 0;
in_wr = 0;
reg_req_in = 0;
reg_ack_in = 0;
reg_rd_wr_L_in = 0;
reg_addr_in = 0;
reg_data_in = 0;
reg_src_in = 0;
clk = 0;
core_sp_clk = 0;
reset = 1;
packet_drop = 0;
// Wait 100 ns for global reset to finish
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
@(posedge clk);
@(negedge clk);
// Add stimulus here
reset = 0;
out_rdy = 1;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'hff;
in_data = 64'h0000000e0004006a;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h004e46324302004e;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h4632430208004500;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h005c000040004001;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h1f9b0a0203020a01;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h04020800d0c4b63d;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h000f92d3b04c55da;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h000008090a0b0c0d;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h0e0f101112131415;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h0e0f101112131415;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h161718191a1b1c1d;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h1e1f202122232425;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h262728292a2b2c2d;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h2e2f303132333435;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h00;
in_data = 64'h363738393a3b3c3d;
@(posedge clk);
@(negedge clk);
//@(posedge clk);
//@(negedge clk);
in_wr = 1;
in_ctrl = 8'h02;
in_data = 64'h3e3f3f3f3f3f3f3f;
@(posedge clk);
@(negedge clk);
in_wr = 0;
in_ctrl = 8'h00;
in_data = 64'h0;
end
always begin
#800 clk = ~clk;
end
endmodule
|
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Test bench for basic logic elements.
`timescale 1ns/1ps
module RegLatchTest;
// Inputs
reg en, clk;
reg [3:0] data;
// Outputs
wire [3:0] rout;
wire [3:0] lout;
// Instantiate the Unit Under Test (UUT)
CC_DFlipFlop #(4) register(clk, en, data, rout);
CC_DLatch #(4) latch(en, data, lout);
initial begin
en = 0;
data = 'b0;
clk = 0;
end
always
#1 clk = ~clk;
always
#4 en = ~en;
always
#2 data = data + 1;
endmodule
module RegDelayTest;
// Inputs
reg clk;
reg reset;
reg [3:0] data;
// Outputs
wire [3:0] out1;
wire [3:0] out2;
wire [3:0] out3;
// Test different delays.
CC_Delay #(.WIDTH(4), .DELAY(1)) delay1(clk, reset, data, out1);
CC_Delay #(.WIDTH(4), .DELAY(2)) delay2(clk, reset, data, out2);
CC_Delay #(.WIDTH(4), .DELAY(3)) delay3(clk, reset, data, out3);
initial begin
clk = 0;
reset = 1;
data = 0;
#3 reset = 0;
end
always
#1 clk = ~clk;
always
#2 data = data + 1;
endmodule
module CC_BidirTest;
reg sel_in;
wire [3:0] port, in, out;
CC_Bidir #(4) bidir(sel_in, port, in, out);
reg [3:0] count_in;
reg [3:0] count_out;
initial begin
sel_in = 0;
count_in = 'b0;
count_out = 'b0;
end
always begin
#1
count_in = count_in + 1;
count_out = count_out - 1;
end
assign port = sel_in ? count_in : 'bz;
assign out = count_out;
always
#4 sel_in = ~sel_in;
endmodule
module CC_MuxRegTest;
reg clk;
reg sel;
reg en;
reg [3:0] in_a, in_b;
wire [3:0] out;
CC_MuxReg #(4) muxreg(sel, clk, en, in_a, in_b, out);
initial begin
sel = 0;
en = 0;
clk = 0;
in_a = 'b0;
in_b = 'b0;
end
always
#1 clk = ~clk;
always
#4 en = ~en;
always
#7 sel = ~sel;
always
#6 in_a = in_a + 1;
always
#10 in_b = in_b + 1;
endmodule
module CC_DecoderTest;
parameter WIDTH=4;
// Inputs
reg [WIDTH-1:0] in;
// Outputs
wire [(1 << WIDTH)-1:0] out;
CC_Decoder #(WIDTH) decoder(.in(in), .out(out));
initial
in = 0;
always
#1 in = in + 1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0P_BLACKBOX_V
`define SKY130_FD_SC_LP__INPUTISO0P_BLACKBOX_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputiso0p (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0P_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_PR_TB_V
`define SKY130_FD_SC_LS__UDP_DFF_PR_TB_V
/**
* udp_dff$PR: Positive edge triggered D flip-flop with active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_dff_pr.v"
module top();
// Inputs are registered
reg D;
reg RESET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 D = 1'b1;
#80 RESET = 1'b1;
#100 D = 1'b0;
#120 RESET = 1'b0;
#140 RESET = 1'b1;
#160 D = 1'b1;
#180 RESET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__udp_dff$PR dut (.D(D), .RESET(RESET), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_PR_TB_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_MENU (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg d1_data_in;
reg d2_data_in;
wire data_in;
reg edge_capture;
wire edge_capture_wr_strobe;
wire edge_detect;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture <= 0;
else if (edge_detect)
edge_capture <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in & ~d2_data_in;
endmodule
|
module bsg_rp_clk_gen_atomic_delay_tuner
( input i
, input sel_i
, input we_async_i
, input we_inited_i
, input async_reset_neg_i
, output we_o
, output o
);
wire [ 1:0] sel_r;
wire [13:0] signal;
wire we_o_pre_buf;
wire zero_bit;
wire mux_lo;
wire we_i_sync, we_i_sync_sync, we_i_sync_sync_nand;
// synopsys rp_group (bsg_clk_gen_cde)
// synopsys rp_fill (13 2 LX)
wire n1, n2, n3, n4;
SC7P5T_CKINVX2_SSC14SL I11 ( .CLK(i), .Z(n1) );
SC7P5T_CKINVX2_SSC14SL I12 ( .CLK(n1), .Z(signal[0]) );
SC7P5T_CKINVX8_SSC14SL I12a ( .CLK(n1), .Z( ));
SC7P5T_CKINVX8_SSC14SL I12b ( .CLK(n1), .Z( ));
SC7P5T_CKINVX2_SSC14SL I21 ( .CLK(signal[0]), .Z(n2) );
SC7P5T_CKINVX2_SSC14SL I22 ( .CLK(n2), .Z(signal[1]) );
SC7P5T_CKINVX8_SSC14SL I22a ( .CLK(n2), .Z( ));
SC7P5T_CKINVX8_SSC14SL I22b ( .CLK(n2), .Z( ));
SC7P5T_CKINVX2_SSC14SL I31 ( .CLK(signal[1]), .Z(n3) );
SC7P5T_CKINVX2_SSC14SL I32 ( .CLK(n3), .Z(signal[2]) );
SC7P5T_CKINVX8_SSC14SL I32a ( .CLK(n3), .Z( ));
SC7P5T_CKINVX8_SSC14SL I32b ( .CLK(n3), .Z( ));
SC7P5T_CKINVX2_SSC14SL I41 ( .CLK(signal[2]), .Z(n4) );
SC7P5T_CKINVX2_SSC14SL I42 ( .CLK(n4), .Z(signal[3]) );
SC7P5T_CKINVX8_SSC14SL I42a ( .CLK(n4), .Z( ));
SC7P5T_CKINVX8_SSC14SL I42b ( .CLK(n4), .Z( ));
// synopsys rp_fill (0 1 RX)
SC7P5T_MUXI4X4_SSC14SL M1 ( .D0(signal[3]), .D1(signal[2]), .D2(zero_bit), .D3(signal[0]), .S0(sel_r[0]), .S1(sel_r[1]), .Z(o) );
// synopsys rp_fill (0 0 RX)
// this gate picks input 01 when async reset is low, initializing the oscillator
SC7P5T_TIELOX2_SSC14SL ZB ( .Z(zero_bit) );
SC7P5T_ND2IAX2_SSC14SL NB ( .A(sel_r[0]), .B(async_reset_neg_i), .Z(sel_r[1]) );
SC7P5T_DFFRQX4_SSC14SL sel_r_reg_0 ( .D(mux_lo), .CLK(o), .RESET(async_reset_neg_i), .Q(sel_r[0]) );
// 40nm: non-inverting mux 32.5ps + load S->Z
// 40nm: inverting mux 43ps + load S->ZN
// inputs are reversed because select is inverted
// we_i&we_inited_i=1 -> new value (I0)
// we_i&we_inited-i=0 -> use value in register (I1)
SC7P5T_MUX2X1_SSC14SL MX1 ( .D0(sel_i), .D1(sel_r[0]), .S(we_i_sync_sync_nand), .Z(mux_lo) );
// nand 10ps versus 22ps
SC7P5T_ND2X1_SSC14SL bsg_we_nand ( .A(we_i_sync_sync), .B(we_inited_i), .Z(we_i_sync_sync_nand) );
// synchronizer flops; negative edge triggered
SC7P5T_DFFNQX1_SSC14SL bsg_SYNC_2_r ( .D(we_i_sync) , .CLK(o), .Q(we_i_sync_sync) );
SC7P5T_DFFNQX1_SSC14SL bsg_SYNC_1_r ( .D(we_async_i), .CLK(o), .Q(we_i_sync) );
// drive we signal to next CDT; minimize capacitive load on critical we_i path
SC7P5T_INVX0P5_SSC14SL we_o_pre ( .A(we_i_sync_sync_nand), .Z(we_o_pre_buf) );
SC7P5T_BUFX4_SSC14SL we_o_buf ( .A(we_o_pre_buf) , .Z(we_o) );
// synopsys rp_endgroup (bsg_clk_gen_cde)
endmodule
`BSG_ABSTRACT_MODULE(bsg_rp_clk_gen_atomic_delay_tuner)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_TB_V
`define SKY130_FD_SC_LS__O311A_TB_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o311a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__o311a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3B_4_V
`define SKY130_FD_SC_HD__AND3B_4_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and3b_4 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and3b_4 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3B_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O41A_BEHAVIORAL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o41a (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_BEHAVIORAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__A2BB2OI_BEHAVIORAL_PP_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y , nor0_out, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2OI_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211O_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A211O_FUNCTIONAL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a211o (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, C1, B1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211O_FUNCTIONAL_V
|
// file: ClockDivider.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___108.000______0.000______50.0______221.150____300.991
// CLK_OUT2_____9.000______0.000______50.0______327.887____300.991
// CLK_OUT3____18.000______0.000______50.0______295.409____300.991
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module ClockDivider
(
// Clock in ports
input clk,
// Clock out ports
output clk_vga,
output clk_cpu,
output clk_2cpu
);
ClockDivider_clk_wiz inst
(
// Clock in ports
.clk(clk),
// Clock out ports
.clk_vga(clk_vga),
.clk_cpu(clk_cpu),
.clk_2cpu(clk_2cpu)
);
endmodule
|
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