text
stringlengths 1
2.1M
|
|---|
// EE 471 Lab 1, Beck Pang, Spring 2015
// Main function for calling different counter onto the board
// @require: only call one counter a time
`include "hexOnHex.v"
`include "Implementation/mux2_1.sv"
`include "Implementation/mux4_1.sv"
`include "Implementation/mux8_1.sv"
`include "Implementation/mux32_1.sv"
`include "Implementation/DFlipFlop.sv"
`include "Implementation/registerSingle.sv"
`include "Implementation/register.sv"
`include "Implementation/decoder5_32.sv"
//`include "DE1_SoCPhase1.v"
`include "adder_subtractor.v"
`include "flag.v"
`include "adder16b.v"
`include "adder4b.v"
`include "fullAdder1b.v"
`include "lookAhead4b.v"
`include "addition.v"
`include "subtract.v"
`include "andGate.v"
`include "orGate.v"
`include "xorGate.v"
`include "setLT.v"
`include "shiftll.v"
`include "ALUnit.sv"
`include "SRAM2Kby16.v"
`include "registerFile.sv"
module DE1_SoCPhase1 (CLOCK_50, LEDR, HEX0, HEX1, HEX2, HEX3, SW, KEY);
input CLOCK_50; // connect to system 50 MHz clock
output [9:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3;
input [9:0] SW;
input [3:0] KEY;
reg [31:0] AL, BL, A, B, data;
reg [1:0] count;
reg enter, eHold;
wire clk, run, res, Z, V, C, N;
wire [31:0] dataOut;
wire [3:0]digits;
reg [2:0] oper;
reg [1:0] sel;
initial begin
oper = 0;
sel = 0;
enter = 0;
eHold = 0;
count = 0;
AL = 0;
BL = 0;
A = 0;
B = 0;
data = 0;
end
assign LEDR[3] = Z;
assign LEDR[2] = V;
assign LEDR[1] = C;
assign LEDR[0] = N;
assign clk = CLOCK_50;
//Interpreted by the system as an Enter. When Enter is pressed
// the ALU will read the state of the input switches and respond accordingly
//assign enter = ~KEY[0];
//Directs the ALU to perform the specified operation and display the results.
assign run = ~KEY[1];
// sets the hex digits
assign digits = SW[3:0];
// Specify whether operand A or B is to be entered or the result is to be displayed
// controls the hex
hexOnHex hex0(data[3:0], HEX0);
hexOnHex hex1(data[7:4], HEX1);
hexOnHex hex2(data[11:8], HEX2);
hexOnHex hex3(data[15:12], HEX3);
ALUnit alzheimers (clk,oper, A, B, dataOut,Z,V,C,N);
//ALuBe alzheimers (clk,oper, A, B, dataOut,Z,V,C,N);
always @(posedge clk) begin
// hex display done
case(sel)
0: data <= AL;
1: data <= BL;
default: data <= dataOut;
endcase
if(~KEY[0]) begin
if(eHold) begin
enter <= 0;
//eHold <=0;
end else begin
enter <= 1;
//eHold <= 1;
end
eHold <= 1;
end
else begin
eHold <= 0;
enter <= 0;
end
if(enter) begin
if(sel != SW[9:8]) begin
sel <= SW[9:8];
count <= 0;
end else begin
if(sel == 0)
case(count)
0: AL[3:0] = digits;
1: AL[7:4] = digits;
2: AL[11:8] = digits;
3: AL[15:12] = digits;
endcase
else if(sel == 1)
case(count)
0: BL[3:0] = digits;
1: BL[7:4] = digits;
2: BL[11:8] = digits;
3: BL[15:12] = digits;
endcase
count = count + 1;
end
end
if(run) begin
oper <= SW[6:4];
A <= AL;
B <= BL;
end
end
endmodule
module interfaceTest();
wire clk; // connect to system 50 MHz clock
wire [9:0] LEDR;
wire [9:0] SW;
wire [3:0] KEY;
wire [6:0] HEX0;
wire [6:0] HEX1;
wire [6:0] HEX2;
wire [6:0] HEX3;
DE1_SoCPhase1 dut (clk, LEDR, HEX0, HEX1, HEX2, HEX3, SW, KEY);
phase1Tester test (clk, SW, KEY);
initial begin
$dumpfile("Phase1Test.vcd");
$dumpvars(1, dut);
end
endmodule
module phase1Tester(clk, SW, KEY);
output reg clk;
output reg [9:0] SW;
output reg [3:0] KEY;
reg [2:0] control;
initial begin
control = 0;
SW = 0;
KEY = 15;
end
//controls = SW[6:4];
//inVal = SW[3:0];
//sel = SW[9:8];
//enter = ~KEY[0];
//run = ~KEY[1];
parameter [2:0] NOP = 3'b000, ADD= 3'b001, SUB = 3'b010, AND = 3'b011, OR = 3'b100, XOR = 3'b101, SLT = 3'b110, SLL = 3'b111;
parameter d = 20;
// Set up the clocking
always #(d/2) clk= ~clk;
initial begin
$display("clk \t SW \t KEY ");
#d
clk =0;
end
// Set up the inputs to the design
initial begin
$monitor("%b \t %b \t %b \t %b", clk,SW, KEY, $time);
/*//#(d*3); //SW[9:8] = 0; //KEY[0] =0;
//#d; //KEY[0]= 1;
//#d;
#d; SW[9:8] = 1; SW[3:0] =2;#d; #d; #d; KEY[0] = 0;//set value of B
#d;#d; KEY[0] = 1;
#d;
#d; SW[9:8] = 0; SW[3:0] = 1;#d;#d; KEY[0]= 0; //set value of A
#d#d; KEY[0] = 1;
#d;
// #d; SW[3:0] = 2; KEY[0] = 0;
// #d; KEY[0] = 1;
// #d;
#d; SW[9:8] = 3; KEY[0] = 0;
#d#d; KEY[0] = 1; // display result
#d;*/
#d SW[3:0] = 1; KEY[0] = 0; #d KEY[0] = 1;
#d SW[8] = 1; KEY[0] = 0; #d KEY[0] = 1;
#d SW[3:0] = 2; KEY[0] = 0; #d KEY[0] = 1;
#d SW[9] = 1; KEY[0] = 0; #d KEY[0] = 1;
// operation tests
#d; SW[6:4] = NOP; KEY[1] = 0;
#d; SW[6:4] = ADD;
#d; SW[6:4] = SUB;
#d; SW[6:4] = AND;
#d; SW[6:4] = OR;
#d; SW[6:4] = XOR;
#d; SW[6:4] = SLT;
#d; SW[6:4] = SLL;
#(d*3);
$stop;
$finish;
end
endmodule
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ns / 1ps
// altera message_off 10036
module acl_ic_local_mem_router #(
parameter integer DATA_W = 256,
parameter integer BURSTCOUNT_W = 6,
parameter integer ADDRESS_W = 32,
parameter integer BYTEENA_W = DATA_W / 8,
parameter integer NUM_BANKS = 8
)
(
input logic clock,
input logic resetn,
// Bank select (one-hot)
input logic [NUM_BANKS-1:0] bank_select,
// Master
input logic m_arb_request,
input logic m_arb_enable,
input logic m_arb_read,
input logic m_arb_write,
input logic [DATA_W-1:0] m_arb_writedata,
input logic [BURSTCOUNT_W-1:0] m_arb_burstcount,
input logic [ADDRESS_W-1:0] m_arb_address,
input logic [BYTEENA_W-1:0] m_arb_byteenable,
output logic m_arb_stall,
output logic m_wrp_ack,
output logic m_rrp_datavalid,
output logic [DATA_W-1:0] m_rrp_data,
// To each bank
output logic b_arb_request [NUM_BANKS],
output logic b_arb_enable [NUM_BANKS],
output logic b_arb_read [NUM_BANKS],
output logic b_arb_write [NUM_BANKS],
output logic [DATA_W-1:0] b_arb_writedata [NUM_BANKS],
output logic [BURSTCOUNT_W-1:0] b_arb_burstcount [NUM_BANKS],
output logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] b_arb_address [NUM_BANKS],
output logic [BYTEENA_W-1:0] b_arb_byteenable [NUM_BANKS],
input logic b_arb_stall [NUM_BANKS],
input logic b_wrp_ack [NUM_BANKS],
input logic b_rrp_datavalid [NUM_BANKS],
input logic [DATA_W-1:0] b_rrp_data [NUM_BANKS]
);
integer i;
always_comb
begin
m_arb_stall = 1'b0;
m_wrp_ack = 1'b0;
m_rrp_datavalid = 1'b0;
m_rrp_data = '0;
for( i = 0; i < NUM_BANKS; i = i + 1 )
begin:b
b_arb_request[i] = m_arb_request & bank_select[i];
b_arb_read[i] = m_arb_read & bank_select[i];
b_arb_enable[i] = m_arb_enable;
b_arb_write[i] = m_arb_write & bank_select[i];
b_arb_writedata[i] = m_arb_writedata;
b_arb_burstcount[i] = m_arb_burstcount;
b_arb_address[i] = m_arb_address[ADDRESS_W-$clog2(NUM_BANKS)-1:0];
b_arb_byteenable[i] = m_arb_byteenable;
m_arb_stall |= b_arb_stall[i] & bank_select[i];
m_wrp_ack |= b_wrp_ack[i];
m_rrp_datavalid |= b_rrp_datavalid[i];
m_rrp_data |= (b_rrp_datavalid[i] ? b_rrp_data[i] : '0);
end
end
// Simulation-only assert - should eventually become hardware exception
// Check that only one return path has active data. Colliding rrps
// will lead to incorrect data, and may mean that there is a mismatch in
// arbitration latency.
// synthesis_off
always @(posedge clock)
begin
logic [NUM_BANKS-1:0] b_rrp_datavalid_packed;
for(int bitnum = 0; bitnum < NUM_BANKS; bitnum++ )
begin
b_rrp_datavalid_packed[bitnum] = b_rrp_datavalid[bitnum];
end
#1 assert ($onehot0(b_rrp_datavalid_packed))
else $fatal(0,"Local memory router: rrp collision. Data corrupted");
end
// synthesis_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_1_V
`define SKY130_FD_SC_HS__MUX2I_1_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2i_1 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
sky130_fd_sc_hs__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2i_1 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_PP_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr (
Y ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_Y, not0_out_Y, KAPWR, VGND);
buf buf0 (Y , pwrgood0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S25_1_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S25_1_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog wrapper for clkdlybuf4s25 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkdlybuf4s25.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s25_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkdlybuf4s25 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s25_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkdlybuf4s25 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S25_1_V
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Miguel Angel Rodriguez Jodar
//
// Create Date: 10:30:33 07/23/2015
// Design Name: SAM Coupé clone
// Module Name: asic
// Project Name: SAM Coupé clone
// Target Devices: Spartan 6
// Tool versions: ISE 12.4
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module asic (
input wire clk,
input wire rst_n,
// CPU interface
input wire mreq_n,
input wire iorq_n,
input wire rd_n,
input wire wr_n,
input wire [15:0] cpuaddr,
input wire [7:0] data_from_cpu,
output reg [7:0] data_to_cpu,
output reg data_enable_n,
output reg wait_n,
// RAM/ROM interface
output reg [18:0] vramaddr,
output reg [18:0] cpuramaddr,
input wire [7:0] data_from_ram,
output reg ramwr_n,
output reg romcs_n,
output reg ramcs_n,
output wire asic_is_using_ram,
// audio I/O
input wire ear,
output wire mic,
output wire beep,
// keyboard I/O
input wire [7:0] keyboard,
output wire rdmsel,
// disk I/O
output reg disc1_n,
output reg disc2_n,
// video output
output wire [1:0] r,
output wire [1:0] g,
output wire [1:0] b,
output wire bright,
output reg hsync_pal,
output reg vsync_pal,
output wire int_n
);
parameter HACTIVEREGION = 512,
RBORDER = 64,
HFPORCH = 16,
HSYNC = 64,
HBPORCH = 64,
LBORDER = 48;
parameter HTOTAL = RBORDER +
HFPORCH +
HSYNC +
HBPORCH +
LBORDER +
HACTIVEREGION;
parameter VACTIVEREGION = 192,
BBORDER = 48,
VFPORCH = 4,
VSYNC = 4,
VBPORCH = 16,
TBORDER = 48;
parameter VTOTAL = VACTIVEREGION +
BBORDER +
VFPORCH +
VSYNC +
VBPORCH +
TBORDER;
// Start of vertical sync, horizontal counter (last 4 scanlines)
parameter BEGINVSYNCH = 0;
// Start and end of vertical sync
parameter BEGINVSYNCV = VACTIVEREGION + BBORDER + VFPORCH;
parameter ENDVSYNCV = BEGINVSYNCV + 4;
parameter IOADDR_VMPR = 8'd252,
IOADDR_HMPR = 8'd251,
IOADDR_LMPR = 8'd250,
IOADDR_BORDER = 8'd254,
IOADDR_LINEINT = 8'd249,
IOADDR_STATUS = 8'd249,
IOADDR_BASECLUT = 8'd248,
IOADDR_ATTRIB = 8'd255,
IOADDR_HLPEN = 8'd248;
//////////////////////////////////////////////////////////////////////////
// IO regs
reg [7:0] vmpr = 8'h00; // port 252. bit 7 is not used. R/W
wire [1:0] screen_mode = vmpr[6:5];
wire [4:0] screen_page = vmpr[4:0];
reg [7:0] lmpr = 8'h00; // port 250. R/W
wire [4:0] low_page = lmpr[4:0];
wire rom_in_section_a = ~lmpr[5];
wire rom_in_section_d = lmpr[6];
wire write_protect_section_a = lmpr[7];
reg [7:0] hmpr = 8'h00; // port 251.
wire [4:0] high_page = hmpr[4:0];
wire [1:0] clut_mode_3_hi = hmpr[6:5];
wire external_memory = hmpr[7];
reg [7:0] border = 8'h00; // port 254. Bit 6 not implemented. Write only.
wire [3:0] clut_border = {border[5],border[2:0]};
assign mic = border[3];
assign beep = border[4];
wire screen_off = border[7] & screen_mode[1];
reg [7:0] lineint = 8'hFF; // port 249 write only
reg [7:0] hpen = 8'h00;
reg [7:0] lpen = 8'h00;
reg [6:0] clut[0:15]; // Port xF8h where x=0..F
initial begin
clut[ 0] = 7'b000_0_000;
clut[ 1] = 7'b001_0_001;
clut[ 2] = 7'b010_0_010;
clut[ 3] = 7'b011_0_011;
clut[ 4] = 7'b100_0_100;
clut[ 5] = 7'b101_0_101;
clut[ 6] = 7'b110_0_110;
clut[ 7] = 7'b111_0_111;
clut[ 8] = 7'b000_0_000;
clut[ 9] = 7'b001_1_001;
clut[10] = 7'b010_1_010;
clut[11] = 7'b011_1_011;
clut[12] = 7'b100_1_100;
clut[13] = 7'b101_1_101;
clut[14] = 7'b110_1_110;
clut[15] = 7'b111_1_111;
end
//////////////////////////////////////////////////////////////////////////
// Pixel counter (horizontal) and scan counter (vertical)
reg [9:0] hc = 10'h000;
reg [8:0] vc = 9'h000;
always @(posedge clk) begin
if (hc != (HTOTAL-1)) begin
hc <= hc + 1;
end
else begin
hc <= 10'h000;
if (vc != (VTOTAL-1))
vc <= vc + 1;
else
vc <= 9'h000;
end
end
//////////////////////////////////////////////////////////////////////////
// Syncs and vertical retrace/raster line interrupt generation
reg vint_n;
reg rint_n;
always @* begin
hsync_pal = 1'b1;
vsync_pal = 1'b1;
vint_n = 1'b1;
rint_n = 1'b1;
if (hc >= (RBORDER + HFPORCH) && hc < (RBORDER + HFPORCH + HSYNC)) begin
hsync_pal = 1'b0;
end
if (vc >= BEGINVSYNCV && vc < ENDVSYNCV) begin
vsync_pal = 1'b0;
end
if (vc == BEGINVSYNCV && hc < 10'd256)
vint_n = 1'b0;
if (lineint >= 8'd0 && lineint <= 8'd191)
if ({1'b0, lineint} == vc && hc < 10'd256)
rint_n = 1'b0;
end
assign int_n = vint_n & rint_n;
//////////////////////////////////////////////////////////////////////////
// fetching_pixels = 1 when pixels should be fetched from memory
reg fetching_pixels;
always @* begin
if (vc>=0 && vc<VACTIVEREGION && hc>=10'd256 && hc<HTOTAL)
fetching_pixels = ~screen_off;
else
fetching_pixels = 1'b0;
end
//////////////////////////////////////////////////////////////////////////
// Blanking time
reg blank_time;
always @* begin
blank_time = 1'b0;
if (screen_off == 1'b1)
blank_time = 1'b1;
if (hc >= RBORDER && hc < (RBORDER + HFPORCH + HSYNC + HBPORCH))
blank_time = 1'b1;
if (vc >= (VACTIVEREGION + BBORDER) && vc < (VACTIVEREGION + BBORDER + VFPORCH + VSYNC + VBPORCH))
blank_time = 1'b1;
end
//////////////////////////////////////////////////////////////////////////
// Contention signal (risk of)
reg mem_contention;
reg io_contention;
always @* begin
mem_contention = 1'b0;
io_contention = 1'b0;
if (screen_off == 1'b0 && hc[3:0]<4'd10)
io_contention = 1'b1;
if (screen_off == 1'b1 && (hc[3:0]==4'd0 ||
hc[3:0]==4'd1 ||
hc[3:0]==4'd8 ||
hc[3:0]==4'd9) )
io_contention = 1'b1;
if (fetching_pixels == 1'b1 && hc[3:0]<4'd10) begin
mem_contention = 1'b1;
end
if (fetching_pixels == 1'b0 && (hc[3:0]==4'd0 ||
hc[3:0]==4'd1 ||
hc[3:0]==4'd8 ||
hc[3:0]==4'd9) ) begin
mem_contention = 1'b1;
end
if (screen_mode == 2'b00 && hc[3:0]<4'd10 && (hc<10'd128 || hc>=10'd256)) begin
mem_contention = 1'b1; // extra contention for MODE 1
end
end
assign asic_is_using_ram = mem_contention & fetching_pixels;
//////////////////////////////////////////////////////////////////////////
// WAIT signal with contention applied
always @* begin
wait_n = 1'b1;
if (mreq_n == 1'b0 && cpuaddr<16'h4000 && rom_in_section_a==1'b1)
wait_n = 1'b1;
else if (mreq_n == 1'b0 && cpuaddr>=16'hC000 && rom_in_section_d==1'b1)
wait_n = 1'b1;
else if (mem_contention == 1'b1 && mreq_n == 1'b0)
wait_n = 1'b0;
else if (io_contention == 1'b1 && iorq_n == 1'b0 && (rd_n == 1'b0 || wr_n == 1'b0))
wait_n = 1'b0;
end
//////////////////////////////////////////////////////////////////////////
// VRAM address generation
reg [14:0] screen_offs = 15'h0000;
reg [4:0] screen_column = 5'h00;
always @* begin
if (screen_mode == 2'd0) begin
if (hc[2] == 1'b0)
vramaddr = {screen_page, 1'b0, vc[7:6], vc[2:0], vc[5:3], screen_column};
else
vramaddr = {screen_page, 4'b0110, vc[7:3], screen_column};
end
else if (screen_mode == 2'd1) begin
if (hc[2] == 1'b0)
vramaddr = {screen_page, 1'b0, screen_offs[12:0]};
else
vramaddr = {screen_page, 1'b1, screen_offs[12:0]};
end
else
vramaddr = {screen_page[4:1], screen_offs};
end
//////////////////////////////////////////////////////////////////////////
// FSM for fetching pixels from RAM and shift registers
reg [7:0] vram_byte1, vram_byte2, vram_byte3, vram_byte4;
reg [7:0] sregm12 = 8'h00;
reg [7:0] attrreg = 8'h00;
reg [31:0] sregm3 = 32'h00000000;
reg [31:0] sregm4 = 32'h00000000;
reg [4:0] flash_counter = 5'h00;
reg [1:0] hibits_clut_m3 = 2'b00;
always @(posedge clk) begin
// a good time to reset pixel address counters and advance flash counter for modes 1 and 2
if (vc==(VTOTAL-1) && hc==(HTOTAL-1)) begin
screen_offs <= 15'h0000;
screen_column <= 5'h00;
flash_counter <= flash_counter + 1;
end
if (hc[3:0] == 4'd1 ||
hc[3:0] == 4'd3 ||
hc[3:0] == 4'd5 ||
hc[3:0] == 4'd7)
begin
if (fetching_pixels==1'b1) begin
case (hc[2:0])
3'd1: vram_byte1 <= data_from_ram;
3'd3: vram_byte2 <= data_from_ram;
3'd5: vram_byte3 <= data_from_ram;
3'd7: begin
vram_byte4 <= data_from_ram;
screen_column <= screen_column + 1;
if (screen_mode[1] == 1'b0) // mode 1 and 2
screen_offs <= screen_offs + 1;
end
endcase
if (screen_mode[1] == 1'b1) // mode 3 and 4
screen_offs <= screen_offs + 1;
end
end
if (hc[3:0] == 4'd9) begin
// Transferir buffers al registro de desplazamiento
if (fetching_pixels == 1'b1) begin // showing paper
sregm12 <= vram_byte1;
attrreg <= vram_byte3;
sregm3 <= {vram_byte1, vram_byte2, vram_byte3, vram_byte4};
sregm4 <= {vram_byte1, vram_byte2, vram_byte3, vram_byte4};
hibits_clut_m3 <= clut_mode_3_hi;
end
else begin // showing border
sregm12 <= 8'h00;
attrreg <= {1'b0, clut_border, 3'b000};
sregm3 <= { {16{clut_border[0],clut_border[1]}} };
sregm4 <= { {8{clut_border}} };
hibits_clut_m3 <= clut_border[3:2];
end
end
else begin
sregm3 <= {sregm3[29:0],2'b00};
if (hc[0] == 1'b1) begin
sregm12 <= {sregm12[6:0],1'b0};
sregm4 <= {sregm4[27:0],4'h0};
end
end
end
//////////////////////////////////////////////////////////////////////////
// MUX to select current pixel colour depending upon the current mode
reg [6:0] pixel;
reg [3:0] index;
reg pixel_with_flash;
always @* begin
index = 4'h0;
case (screen_mode)
2'd0,2'd1:
begin
pixel_with_flash = sregm12[7] ^ (attrreg[7] & flash_counter[4]);
if (pixel_with_flash == 1'b1)
index = {attrreg[6],attrreg[2:0]};
else
index = {attrreg[6],attrreg[5:3]};
end
2'd2: index = {hibits_clut_m3, sregm3[30], sregm3[31]};
2'd3: index = sregm4[31:28];
endcase
if (blank_time == 1'b1)
pixel = 7'h00;
else
pixel = clut[index];
end
assign g = {pixel[6], pixel[2]};
assign r = {pixel[5], pixel[1]};
assign b = {pixel[4], pixel[0]};
assign bright = pixel[3];
//////////////////////////////////////////////////////////////////////////
// HPEN and LPEN counters
reg iorq_prev = 1'b1;
reg [7:0] hpen_internal = 8'h00;
always @(posedge clk) begin
if (hc == 10'd255 && vc == 9'd0) begin
hpen_internal <= 8'h00;
end
else if (hc == (HTOTAL-1)) begin
if (hpen_internal != 8'hC0)
hpen_internal <= hpen_internal + 1;
end
end
always @(posedge clk) begin
iorq_prev <= iorq_n;
if (iorq_prev == 1'b1 && iorq_n == 1'b0) begin // falling edge IORQ
lpen <= (hc<10'd256 || vc>=9'd192)? {7'b0000000,index[0]} : (hc[8:1] ^ 8'h80); // fast way to add 128 to hc[8:1]
hpen <= (screen_off == 1'b1)? 8'd192 : hpen_internal;
end
end
//////////////////////////////////////////////////////////////////////////
// CPU memory address and control signal generation
// Enables for ROM and RAM
always @* begin
romcs_n = 1'b1;
ramcs_n = 1'b1;
if (mreq_n == 1'b0 && cpuaddr<16'h4000 && rom_in_section_a==1'b1) begin
romcs_n = 1'b0;
end
else if (mreq_n == 1'b0 && cpuaddr>=16'hC000 && rom_in_section_d==1'b1) begin
romcs_n = 1'b0;
end
else if (mreq_n == 1'b0) begin
if (cpuaddr >= 16'h8000 && external_memory == 1'b1) // disable internal RAM if bit 7 HMPR is set
ramcs_n = 1'b1;
else
ramcs_n = 1'b0;
end
end
// Write signal for RAM
always @* begin
ramwr_n = 1'b1;
case (cpuaddr[15:14])
2'b00:
begin
cpuramaddr = {low_page, cpuaddr[13:0]};
if (write_protect_section_a == 1'b0)
ramwr_n = ramcs_n | wr_n;
end
2'b01:
begin
cpuramaddr = {low_page+5'd1, cpuaddr[13:0]};
ramwr_n = ramcs_n | wr_n;
end
2'b10:
begin
cpuramaddr = {high_page, cpuaddr[13:0]};
ramwr_n = ramcs_n | wr_n;
end
default: // 2'b11
begin
cpuramaddr = {high_page+5'd1, cpuaddr[13:0]};
ramwr_n = ramcs_n | wr_n;
end
endcase
end
//////////////////////////////////////////////////////////////////////////
// IO ports
// Write to IO ports from CPU
always @(posedge clk) begin
if (rst_n == 1'b0) begin
vmpr <= 8'h00;
lmpr <= 8'h00;
hmpr <= 8'h00;
border <= 8'h00;
end
else begin
if (iorq_n == 1'b0 && wr_n == 1'b0 && wait_n == 1'b1) begin
if (cpuaddr[7:0] == IOADDR_BORDER)
border <= data_from_cpu;
else if (cpuaddr[7:0] == IOADDR_VMPR)
vmpr <= data_from_cpu;
else if (cpuaddr[7:0] == IOADDR_HMPR)
hmpr <= data_from_cpu;
else if (cpuaddr[7:0] == IOADDR_LMPR)
lmpr <= data_from_cpu;
else if (cpuaddr[7:0] == IOADDR_LINEINT)
lineint <= data_from_cpu;
else if (cpuaddr[7:0] == IOADDR_BASECLUT)
clut[cpuaddr[11:8]] <= data_from_cpu[6:0];
end
end
end
// Data available for CPU
always @* begin
data_enable_n = 1'b1;
data_to_cpu = 8'hFF;
disc1_n = 1'b1;
disc2_n = 1'b1;
if (iorq_n == 1'b0 && rd_n == 1'b0) begin
data_enable_n = 1'b0;
if (cpuaddr[7:0] == IOADDR_BORDER)
data_to_cpu = {screen_off, ear, 1'b0, keyboard[4:0]};
else if (cpuaddr[7:0] == IOADDR_ATTRIB)
data_to_cpu = vram_byte3;
else if (cpuaddr[7:0] == IOADDR_STATUS)
data_to_cpu = {keyboard[7:5], 1'b1, vint_n, 2'b11, rint_n};
else if (cpuaddr[7:0] == IOADDR_VMPR)
data_to_cpu = vmpr;
else if (cpuaddr[7:0] == IOADDR_HMPR)
data_to_cpu = hmpr;
else if (cpuaddr[7:0] == IOADDR_LMPR)
data_to_cpu = lmpr;
else if (cpuaddr[8:0] == {1'b0, IOADDR_HLPEN} )
data_to_cpu = lpen;
else if (cpuaddr[8:0] == {1'b1, IOADDR_HLPEN} )
data_to_cpu = hpen;
else if (cpuaddr[7:0]>=8'd224 && cpuaddr[7:0]<=8'd231) begin
disc1_n = 1'b0;
data_enable_n = 1'b1;
end
else if (cpuaddr[7:0]>=8'd240 && cpuaddr[7:0]<=8'd247) begin
disc2_n = 1'b0;
data_enable_n = 1'b1;
end
else
data_enable_n = 1'b1;
end
end
assign rdmsel = (cpuaddr[15:8] == 8'hFF)? 1'b0 : 1'b1;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4BB_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NOR4BB_BEHAVIORAL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor4bb (
Y ,
A ,
B ,
C_N,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, nor0_out, C_N, D_N);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4BB_BEHAVIORAL_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Ethernet arbitrated multiplexer
*/
module eth_arb_mux #
(
parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame inputs
*/
input wire [S_COUNT-1:0] s_eth_hdr_valid,
output wire [S_COUNT-1:0] s_eth_hdr_ready,
input wire [S_COUNT*48-1:0] s_eth_dest_mac,
input wire [S_COUNT*48-1:0] s_eth_src_mac,
input wire [S_COUNT*16-1:0] s_eth_type,
input wire [S_COUNT*DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire [S_COUNT-1:0] s_eth_payload_axis_tvalid,
output wire [S_COUNT-1:0] s_eth_payload_axis_tready,
input wire [S_COUNT-1:0] s_eth_payload_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_eth_payload_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_eth_payload_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_eth_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire [ID_WIDTH-1:0] m_eth_payload_axis_tid,
output wire [DEST_WIDTH-1:0] m_eth_payload_axis_tdest,
output wire [USER_WIDTH-1:0] m_eth_payload_axis_tuser
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_eth_hdr_ready_reg = {S_COUNT{1'b0}}, s_eth_hdr_ready_next;
reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
wire [S_COUNT-1:0] request;
wire [S_COUNT-1:0] acknowledge;
wire [S_COUNT-1:0] grant;
wire grant_valid;
wire [CL_S_COUNT-1:0] grant_encoded;
// internal datapath
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
reg m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
assign s_eth_payload_axis_tready = (m_eth_payload_axis_tready_int_reg && grant_valid) << grant_encoded;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_eth_payload_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_eth_payload_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_eth_payload_axis_tvalid[grant_encoded];
wire current_s_tready = s_eth_payload_axis_tready[grant_encoded];
wire current_s_tlast = s_eth_payload_axis_tlast[grant_encoded];
wire [ID_WIDTH-1:0] current_s_tid = s_eth_payload_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_eth_payload_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_eth_payload_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
// arbiter instance
arbiter #(
.PORTS(S_COUNT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
assign request = s_eth_hdr_valid & ~grant;
assign acknowledge = grant & s_eth_payload_axis_tvalid & s_eth_payload_axis_tready & s_eth_payload_axis_tlast;
always @* begin
frame_next = frame_reg;
s_eth_hdr_ready_next = {S_COUNT{1'b0}};
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
if (s_eth_payload_axis_tvalid[grant_encoded] && s_eth_payload_axis_tready[grant_encoded]) begin
// end of frame detection
if (s_eth_payload_axis_tlast[grant_encoded]) begin
frame_next = 1'b0;
end
end
if (!frame_reg && grant_valid && (m_eth_hdr_ready || !m_eth_hdr_valid)) begin
// start of frame
frame_next = 1'b1;
s_eth_hdr_ready_next = grant;
m_eth_hdr_valid_next = 1'b1;
m_eth_dest_mac_next = s_eth_dest_mac[grant_encoded*48 +: 48];
m_eth_src_mac_next = s_eth_src_mac[grant_encoded*48 +: 48];
m_eth_type_next = s_eth_type[grant_encoded*16 +: 16];
end
// pass through selected packet data
m_eth_payload_axis_tdata_int = current_s_tdata;
m_eth_payload_axis_tkeep_int = current_s_tkeep;
m_eth_payload_axis_tvalid_int = current_s_tvalid && m_eth_payload_axis_tready_int_reg && grant_valid;
m_eth_payload_axis_tlast_int = current_s_tlast;
m_eth_payload_axis_tid_int = current_s_tid;
m_eth_payload_axis_tdest_int = current_s_tdest;
m_eth_payload_axis_tuser_int = current_s_tuser;
end
always @(posedge clk) begin
frame_reg <= frame_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
if (rst) begin
frame_reg <= 1'b0;
s_eth_hdr_ready_reg <= {S_COUNT{1'b0}};
m_eth_hdr_valid_reg <= 1'b0;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_eth_payload_axis_temp_to_output;
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? m_eth_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
assign m_eth_payload_axis_tid = ID_ENABLE ? m_eth_payload_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_eth_payload_axis_tdest = DEST_ENABLE ? m_eth_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_eth_payload_axis_tuser = USER_ENABLE ? m_eth_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_eth_payload_axis_tvalid_reg <= 1'b0;
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_eth_payload_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tid_reg <= temp_m_eth_payload_axis_tid_reg;
m_eth_payload_axis_tdest_reg <= temp_m_eth_payload_axis_tdest_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
end
endmodule
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: gsu_umult.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module gsu_umult (
dataa,
datab,
result);
input [7:0] dataa;
input [7:0] datab;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_mult lpm_mult_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 8,
lpm_mult_component.lpm_widthb = 8,
lpm_mult_component.lpm_widthp = 16;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "8"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "16"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "16"
// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_umult_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Palette file.
module Palette(
clk_a, wr_a, rd_a, addr_a, data_in_a, data_out_a, byte_en_a,
clk_b, wr_b, rd_b, addr_b, data_in_b, data_out_b);
parameter NUM_CHANNELS = 3;
localparam BITS_PER_BYTE = 8;
localparam DATA_WIDTH = NUM_CHANNELS * BITS_PER_BYTE;
localparam ADDR_WIDTH = 10;
input clk_a;
input wr_a;
input rd_a;
input [NUM_CHANNELS-1:0] byte_en_a;
input [ADDR_WIDTH-1:0] addr_a;
input [DATA_WIDTH-1:0] data_in_a;
output [DATA_WIDTH-1:0] data_out_a;
input clk_b;
input wr_b;
input rd_b;
input [ADDR_WIDTH-1:0] addr_b;
input [DATA_WIDTH-1:0] data_in_b;
output [DATA_WIDTH-1:0] data_out_b;
genvar i;
generate
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin : RAM
// Instantiate 1Kx8 RAMs in parallel.
palette_ram_1Kx8 ram(.clock_a(clk_a), .clock_b(clk_b),
.address_a(addr_a), .address_b(addr_b),
.wren_a(wr_a), .wren_b(wr_b),
.rden_a(rd_a), .rden_b(rd_b),
.data_a(data_in_a[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.data_b(data_in_b[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.q_a(data_out_a[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.q_b(data_out_b[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.byteena_a(byte_en_a[i]));
end
endgenerate
endmodule
|
(** * Imp: Simple Imperative Programs *)
(** In this chapter, we take a more serious look at how to use Coq to
study other things. Our case study is a _simple imperative
programming language_ called Imp, embodying a tiny core fragment
of conventional mainstream languages such as C and Java. Here is
a familiar mathematical function written in Imp.
Z := X;
Y := 1;
while ~(Z = 0) do
Y := Y * Z;
Z := Z - 1
end
*)
(** We concentrate here on defining the _syntax_ and _semantics_ of
Imp; later chapters in _Programming Language Foundations_
(_Software Foundations_, volume 2) develop a theory of
_program equivalence_ and introduce _Hoare Logic_, a widely
used logic for reasoning about imperative programs. *)
Set Warnings "-notation-overridden,-parsing".
From Coq Require Import Bool.Bool.
From Coq Require Import Init.Nat.
From Coq Require Import Arith.Arith.
From Coq Require Import Arith.EqNat.
From Coq Require Import Lia.
From Coq Require Import Lists.List.
From Coq Require Import Strings.String.
Import ListNotations.
From PLF Require Import Maps.
(* ################################################################# *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ================================================================= *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum (n : nat)
| APlus (a1 a2 : aexp)
| AMinus (a1 a2 : aexp)
| AMult (a1 a2 : aexp).
Inductive bexp : Type :=
| BTrue
| BFalse
| BEq (a1 a2 : aexp)
| BLe (a1 a2 : aexp)
| BNot (b : bexp)
| BAnd (b1 b2 : bexp).
(** In this chapter, we'll mostly elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1 + 2 * 3"] to the AST
APlus (ANum 1) (AMult (ANum 2) (ANum 3)).
The optional chapter [ImpParser] develops a simple lexical
analyzer and parser that can perform this translation. You do
_not_ need to understand that chapter to understand this one, but
if you haven't already taken a course where these techniques are
covered (e.g., a compilers course) you may want to skim it. *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a := nat
| a + a
| a - a
| a * a
b := true
| false
| a = a
| a <= a
| ~ b
| b && b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written with an infix
[+]) while leaving other aspects of lexical analysis and
parsing (like the relative precedence of [+], [-], and
[*], the use of parens to group subexpressions, etc.)
unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition, e.g., for implementing a compiler.
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- Conversely, the BNF version is lighter and easier to read.
Its informality makes it flexible, a big advantage in
situations like discussions at the blackboard, where
conveying general ideas is more important than getting every
detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say
which kind of BNF they're using because there is no need to:
a rough-and-ready informal understanding is all that's
important.
It's good to be comfortable with both sorts of notations: informal
ones for communicating between humans and formal ones for carrying
out implementations and proofs. *)
(* ================================================================= *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => (aeval a1) =? (aeval a2)
| BLe a1 a2 => (aeval a1) <=? (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ================================================================= *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0 + e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n => ANum n
| APlus (ANum 0) e2 => optimize_0plus e2
| APlus e1 e2 => APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 => AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 => AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a. induction a.
- (* ANum *) reflexivity.
- (* APlus *) destruct a1 eqn:Ea1.
+ (* a1 = ANum n *) destruct n eqn:En.
* (* n = 0 *) simpl. apply IHa2.
* (* n <> 0 *) simpl. rewrite IHa2. reflexivity.
+ (* a1 = APlus a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
+ (* a1 = AMinus a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
+ (* a1 = AMult a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
- (* AMinus *)
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
- (* AMult *)
simpl. rewrite IHa1. rewrite IHa2. reflexivity. Qed.
(* ################################################################# *)
(** * Coq Automation *)
(** The amount of repetition in this last proof is a little
annoying. And if either the language of arithmetic expressions or
the optimization being proved sound were significantly more
complex, it would start to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ================================================================= *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ----------------------------------------------------------------- *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (rather than failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* This just does [reflexivity]. *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* Just [reflexivity] would have failed. *)
apply HP. (* We can still finish the proof in some other way. *)
Qed.
(** There is no real reason to use [try] in completely manual
proofs like these, but it is very useful for doing automated
proofs in conjunction with the [;] tactical, which we show
next. *)
(* ----------------------------------------------------------------- *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most common form, the [;] tactical takes two tactics as
arguments. The compound tactic [T;T'] first performs [T] and then
performs [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, 0 <=? n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals, which are discharged identically... *)
- (* n=0 *) simpl. reflexivity.
- (* n=Sn' *) simpl. reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, 0 <=? n = true.
Proof.
intros.
(* [destruct] the current goal *)
destruct n;
(* then [simpl] each resulting subgoal *)
simpl;
(* and do [reflexivity] on each resulting subgoal *)
reflexivity.
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH... *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* ... but the remaining cases -- ANum and APlus --
are different: *)
- (* ANum *) reflexivity.
- (* APlus *)
destruct a1 eqn:Ea1;
(* Again, most cases follow directly by the IH: *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...]
does nothing, is when [e1 = ANum n]. In this
case, we have to destruct [n] (to see whether
the optimization applies) and rewrite with the
induction hypothesis. *)
+ (* a1 = ANum n *) destruct n eqn:En;
simpl; rewrite IHa2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs. For
example, here is an informal proof of the optimization theorem
that matches the structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. Most cases follow directly from the
IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We must
show
aeval (optimize_0plus (APlus a1 a2)) = aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n]. If
[n = 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** However, this proof can still be improved: the first case (for
[a = ANum n]) is very trivial -- even more trivial than the cases
that we said simply followed from the IH -- yet we have chosen to
write it out in full. It would be better and clearer to drop it
and just say, at the top, "Most cases are either immediate or
direct from the IH. The only interesting case is the one for
[APlus]..." We can make the same improvement in our formal proof
too. Here's how it looks: *)
Theorem optimize_0plus_sound'': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
- (* APlus *)
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
+ (* a1 = ANum n *) destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ----------------------------------------------------------------- *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical also has a more general form than the simple
[T;T'] we've seen above. If [T], [T1], ..., [Tn] are tactics,
then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e., [T;T'] is shorthand for:
T; [T' | T' | ... | T']
*)
(* ----------------------------------------------------------------- *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying this
tactic until it fails to make progress. Here is an example showing
that [10] is in a long list using [repeat]. *)
Theorem In10 : In 10 [1;2;3;4;5;6;7;8;9;10].
Proof.
repeat (try (left; reflexivity); right).
Qed.
(** The tactic [repeat T] never fails: if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (i.e., it repeats zero times). *)
Theorem In10' : In 10 [1;2;3;4;5;6;7;8;9;10].
Proof.
repeat simpl.
repeat (left; reflexivity).
repeat (right; try (left; reflexivity)).
Qed.
(** The tactic [repeat T] also does not have any upper bound on the
number of times it applies [T]. If [T] is a tactic that always
succeeds (and makes progress), then repeat [T] will loop forever. *)
Theorem repeat_loop : forall (m n : nat),
m + n = n + m.
Proof.
intros m n.
(* Uncomment the next line to see the infinite loop occur.
In Proof General, [C-c C-c] will break out of the loop. *)
(* repeat rewrite Nat.add_comm. *)
Admitted.
(** While evaluation in Coq's term language, Gallina, is guaranteed to
terminate, tactic evaluation is not! This does not affect Coq's
logical consistency, however, since the job of [repeat] and other
tactics is to guide Coq in constructing proofs; if the
construction process diverges (i.e., it does not terminate), this
simply means that we have failed to construct a proof, not that we
have constructed a wrong one. *)
(** **** Exercise: 3 stars, standard (optimize_0plus_b_sound)
Since the [optimize_0plus] transformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function that performs this transformation on [bexp]s and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (b : bexp) : bexp
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, standard, optional (optimize)
_Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many possible
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct. (You will probably
find it easiest to start small -- add just a single, simple
optimization and its correctness proof -- and build up to
something more interesting incrementially.) *)
(* FILL IN HERE
[] *)
(* ================================================================= *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic
scripts.
- The [Tactic Notation] idiom illustrated below gives a handy way
to define "shorthand tactics" that bundle several tactics into a
single command.
- For more sophisticated programming, Coq offers a built-in
language called [Ltac] with primitives that can examine and
modify the proof state. The details are a bit too complicated
to get into here (and it is generally agreed that [Ltac] is not
the most beautiful part of Coq's design!), but they can be found
in the reference manual and other books on Coq, and there are
many examples of [Ltac] definitions in the Coq standard library
that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but this
is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips
with, and it offers plenty of power for many purposes. Here's an
example. *)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] that takes one
tactic [c] as an argument and is defined to be equivalent to the
tactic [simpl; try c]. Now writing "[simpl_and_try reflexivity.]"
in a proof will be the same as writing "[simpl; try reflexivity.]" *)
(* ================================================================= *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented by William Pugh [Pugh 1991] (in Bib.v).
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and ordering ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or fail, meaning
that the goal is actually false. (If the goal is _not_ of this
form, [omega] will also fail.) *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. lia.
Qed.
Example plus_comm__omega : forall m n,
m + n = n + m.
Proof.
intros. lia.
Qed.
Example plus_assoc__omega : forall m n p,
m + (n + p) = m + n + p.
Proof.
intros. lia.
Qed.
(** (Note the [From Coq Require Import Lia.] at the top of
the file.) *)
(* ================================================================= *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: For a variable [x], find an assumption [x = e] or
[e = x] in the context, replace [x] with [e] throughout the
context and current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x] (where [x] is a variable).
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, solve the goal.
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c].
We'll see examples of all of these as we go along. *)
(* ################################################################# *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoint]s. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum n :
aevalR (ANum n) n
| E_APlus (e1 e2: aexp) (n1 n2: nat) :
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus (e1 e2: aexp) (n1 n2: nat) :
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult (e1 e2: aexp) (n1 n2: nat) :
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
Module HypothesisNames.
(* A small notational aside. We could also write the definition of
[aevalR] as follow, with explicit names for the hypotheses in each
case: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum n :
aevalR (ANum n) n
| E_APlus (e1 e2: aexp) (n1 n2: nat)
(H1 : aevalR e1 n1)
(H2 : aevalR e2 n2) :
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus (e1 e2: aexp) (n1 n2: nat)
(H1 : aevalR e1 n1)
(H2 : aevalR e2 n2) :
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult (e1 e2: aexp) (n1 n2: nat)
(H1 : aevalR e1 n1)
(H2 : aevalR e2 n2) :
aevalR (AMult e1 e2) (n1 * n2).
(** This style gives us more control over the names that Coq chooses
during proofs involving [aevalR], at the cost of making the
definition a little more verbose. *)
End HypothesisNames.
(** It will be convenient to have an infix notation for
[aevalR]. We'll write [e ==> n] to mean that arithmetic expression
[e] evaluates to value [n]. *)
Notation "e '==>' n"
:= (aevalR e n)
(at level 90, left associativity)
: type_scope.
End aevalR_first_try.
(** As we saw in [IndProp] in our case study of regular
expressions, Coq provides a way to use this notation in the
definition of [aevalR] itself. *)
Reserved Notation "e '==>' n" (at level 90, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum (n : nat) :
(ANum n) ==> n
| E_APlus (e1 e2 : aexp) (n1 n2 : nat) :
(e1 ==> n1) -> (e2 ==> n2) -> (APlus e1 e2) ==> (n1 + n2)
| E_AMinus (e1 e2 : aexp) (n1 n2 : nat) :
(e1 ==> n1) -> (e2 ==> n2) -> (AMinus e1 e2) ==> (n1 - n2)
| E_AMult (e1 e2 : aexp) (n1 n2 : nat) :
(e1 ==> n1) -> (e2 ==> n2) -> (AMult e1 e2) ==> (n1 * n2)
where "e '==>' n" := (aevalR e n) : type_scope.
(* ================================================================= *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient to write the rules
for [aevalR] and similar relations in the more readable graphical
form of _inference rules_, where the premises above the line
justify the conclusion below the line (we have already seen them
in the [IndProp] chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 ==> n1
e2 ==> n2
-------------------- (E_APlus)
APlus e1 e2 ==> n1+n2
*)
(** Formally, there is nothing deep about inference rules: they
are just implications. You can read the rule name on the right as
the name of the constructor and read each of the linebreaks
between the premises above the line (as well as the line itself)
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration. In informal prose, this is either elided or else
indicated by saying something like "Let [aevalR] be the smallest
relation closed under the following rules...". *)
(** For example, [==>] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n ==> n
e1 ==> n1
e2 ==> n2
-------------------- (E_APlus)
APlus e1 e2 ==> n1+n2
e1 ==> n1
e2 ==> n2
--------------------- (E_AMinus)
AMinus e1 e2 ==> n1-n2
e1 ==> n1
e2 ==> n2
-------------------- (E_AMult)
AMult e1 e2 ==> n1*n2
*)
(** **** Exercise: 1 star, standard, optional (beval_rules)
Here, again, is the Coq definition of the [beval] function:
Fixpoint beval (e : bexp) : bool :=
match e with
| BTrue => true
| BFalse => false
| BEq a1 a2 => (aeval a1) =? (aeval a2)
| BLe a1 a2 => (aeval a1) <=? (aeval a2)
| BNot b => negb (beval b)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
Write out a corresponding definition of boolean evaluation as a
relation (in inference rule notation). *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_beval_rules : option (nat*string) := None.
(** [] *)
(* ================================================================= *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree: *)
Theorem aeval_iff_aevalR : forall a n,
(a ==> n) <-> aeval a = n.
Proof.
split.
- (* -> *)
intros H.
induction H; simpl.
+ (* E_ANum *)
reflexivity.
+ (* E_APlus *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
+ (* E_AMinus *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
+ (* E_AMult *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
- (* <- *)
generalize dependent n.
induction a;
simpl; intros; subst.
+ (* ANum *)
apply E_ANum.
+ (* APlus *)
apply E_APlus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
+ (* AMinus *)
apply E_AMinus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
+ (* AMult *)
apply E_AMult.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
Qed.
(** We can make the proof quite a bit shorter by making more
use of tacticals. *)
Theorem aeval_iff_aevalR' : forall a n,
(a ==> n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
- (* -> *)
intros H; induction H; subst; reflexivity.
- (* <- *)
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars, standard (bevalR)
Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval]. *)
Reserved Notation "e '==>b' b" (at level 90, left associativity).
Inductive bevalR: bexp -> bool -> Prop :=
(* FILL IN HERE *)
where "e '==>b' b" := (bevalR e b) : type_scope
.
Lemma beval_iff_bevalR : forall b bv,
b ==>b bv <-> beval b = bv.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End AExp.
(* ================================================================= *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste: either way works.
However, there are circumstances where relational definitions of
evaluation work much better than functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations with division: *)
Inductive aexp : Type :=
| ANum (n : nat)
| APlus (a1 a2 : aexp)
| AMinus (a1 a2 : aexp)
| AMult (a1 a2 : aexp)
| ADiv (a1 a2 : aexp). (* <--- NEW *)
(** Extending the definition of [aeval] to handle this new
operation would not be straightforward (what should we return as
the result of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR]
is very easy. *)
Reserved Notation "e '==>' n"
(at level 90, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum (n : nat) :
(ANum n) ==> n
| E_APlus (a1 a2 : aexp) (n1 n2 : nat) :
(a1 ==> n1) -> (a2 ==> n2) -> (APlus a1 a2) ==> (n1 + n2)
| E_AMinus (a1 a2 : aexp) (n1 n2 : nat) :
(a1 ==> n1) -> (a2 ==> n2) -> (AMinus a1 a2) ==> (n1 - n2)
| E_AMult (a1 a2 : aexp) (n1 n2 : nat) :
(a1 ==> n1) -> (a2 ==> n2) -> (AMult a1 a2) ==> (n1 * n2)
| E_ADiv (a1 a2 : aexp) (n1 n2 n3 : nat) : (* <----- NEW *)
(a1 ==> n1) -> (a2 ==> n2) -> (n2 > 0) ->
(mult n2 n3 = n1) -> (ADiv a1 a2) ==> n3
where "a '==>' n" := (aevalR a n) : type_scope.
(** Notice that the evaluation relation has now become _partial_:
There are some inputs for which it simply does not specify an
output. *)
End aevalR_division.
Module aevalR_extended.
(** Or suppose that we want to extend the arithmetic operations
by a nondeterministic number generator [any] that, when evaluated,
may yield any number. Note that this is not the same as making a
_probabilistic_ choice among all possible numbers -- we're not
specifying any particular probability distribution for the
results, just saying what results are _possible_. *)
Reserved Notation "e '==>' n" (at level 90, left associativity).
Inductive aexp : Type :=
| AAny (* <--- NEW *)
| ANum (n : nat)
| APlus (a1 a2 : aexp)
| AMinus (a1 a2 : aexp)
| AMult (a1 a2 : aexp).
(** Again, extending [aeval] would be tricky, since now
evaluation is _not_ a deterministic function from expressions to
numbers, but extending [aevalR] is no problem... *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any (n : nat) :
AAny ==> n (* <--- NEW *)
| E_ANum (n : nat) :
(ANum n) ==> n
| E_APlus (a1 a2 : aexp) (n1 n2 : nat) :
(a1 ==> n1) -> (a2 ==> n2) -> (APlus a1 a2) ==> (n1 + n2)
| E_AMinus (a1 a2 : aexp) (n1 n2 : nat) :
(a1 ==> n1) -> (a2 ==> n2) -> (AMinus a1 a2) ==> (n1 - n2)
| E_AMult (a1 a2 : aexp) (n1 n2 : nat) :
(a1 ==> n1) -> (a2 ==> n2) -> (AMult a1 a2) ==> (n1 * n2)
where "a '==>' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(** At this point you maybe wondering: which style should I use
by default? In the examples we've just seen, relational
definitions turned out to be more useful than functional ones.
For situations like these, where the thing being defined is not
easy to express as a function, or indeed where it is _not_ a
function, there is no real choice. But what about when both
styles are workable?
One point in favor of relational definitions is that they can be
more elegant and easier to understand.
Another is that Coq automatically generates nice inversion and
induction principles from [Inductive] definitions.
On the other hand, functional definitions can often be more
convenient:
- Functions are by definition deterministic and defined on all
arguments; for a relation we have to _prove_ these properties
explicitly if we need them.
- With functions we can also take advantage of Coq's computation
mechanism to simplify expressions during proofs.
Furthermore, functions can be directly "extracted" from Gallina to
executable code in OCaml or Haskell.
Ultimately, the choice often comes down to either the specifics of
a particular situation or simply a question of taste. Indeed, in
large Coq developments it is common to see a definition given in
_both_ functional and relational styles, plus a lemma stating that
the two coincide, allowing further proofs to switch from one point
of view to the other at will. *)
(* ################################################################# *)
(** * Expressions With Variables *)
(** Now we return to defining Imp. The next thing we need to do is to
enrich our arithmetic and boolean expressions with variables. To
keep things simple, we'll assume that all variables are global and
that they only hold numbers. *)
(* ================================================================= *)
(** ** States *)
(** Since we'll want to look variables up to find out their current
values, we'll reuse maps from the [Maps] chapter, and
[string]s will be used to represent variables in Imp.
A _machine state_ (or just _state_) represents the current values
of _all_ variables at some point in the execution of a program. *)
(** For simplicity, we assume that the state is defined for
_all_ variables, even though any given program is only going to
mention a finite number of them. The state captures all of the
information stored in memory. For Imp programs, because each
variable stores a natural number, we can represent the state as a
mapping from strings to [nat], and will use [0] as default value
in the store. For more complex programming languages, the state
might have more structure. *)
Definition state := total_map nat.
(* ================================================================= *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum (n : nat)
| AId (x : string) (* <--- NEW *)
| APlus (a1 a2 : aexp)
| AMinus (a1 a2 : aexp)
| AMult (a1 a2 : aexp).
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition W : string := "W".
Definition X : string := "X".
Definition Y : string := "Y".
Definition Z : string := "Z".
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in the chapters
developed to Imp, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is unchanged (except that it now refers
to the new [aexp]s): *)
Inductive bexp : Type :=
| BTrue
| BFalse
| BEq (a1 a2 : aexp)
| BLe (a1 a2 : aexp)
| BNot (b : bexp)
| BAnd (b1 b2 : bexp).
(* ================================================================= *)
(** ** Notations *)
(** To make Imp programs easier to read and write, we introduce some
notations and implicit coercions. You do not need to understand
exactly what these declarations do. Briefly, though:
- The [Coercion] declaration stipulates that a function (or
constructor) can be implicitly used by the type system to
coerce a value of the input type to a value of the output
type. For instance, the coercion declaration for [AId]
allows us to use plain strings when an [aexp] is expected;
the string will implicitly be wrapped with [AId].
- [Declare Custom Entry com] tells Coq to create a new
"custom grammar" for parsing Imp expressions and
programs. The first notation declaration after this tells Coq
that anything between [<{] and [}>] should be parsed using
the Imp grammar. Again, it is not necessary to understand the
details, but it is important to recognize that we are
defining _new_ interpretations for some familiar operators
like [+], [-], [*], [=], [<=], etc., when they occur between
[<{] and [}>]. *)
Coercion AId : string >-> aexp.
Coercion ANum : nat >-> aexp.
Declare Custom Entry com.
Declare Scope com_scope.
Notation "<{ e }>" := e (at level 0, e custom com at level 99) : com_scope.
Notation "( x )" := x (in custom com, x at level 99) : com_scope.
Notation "x" := x (in custom com at level 0, x constr at level 0) : com_scope.
Notation "f x .. y" := (.. (f x) .. y)
(in custom com at level 0, only parsing,
f constr at level 0, x constr at level 9,
y constr at level 9) : com_scope.
Notation "x + y" := (APlus x y) (in custom com at level 50, left associativity).
Notation "x - y" := (AMinus x y) (in custom com at level 50, left associativity).
Notation "x * y" := (AMult x y) (in custom com at level 40, left associativity).
Notation "'true'" := true (at level 1).
Notation "'true'" := BTrue (in custom com at level 0).
Notation "'false'" := false (at level 1).
Notation "'false'" := BFalse (in custom com at level 0).
Notation "x <= y" := (BLe x y) (in custom com at level 70, no associativity).
Notation "x = y" := (BEq x y) (in custom com at level 70, no associativity).
Notation "x && y" := (BAnd x y) (in custom com at level 80, left associativity).
Notation "'~' b" := (BNot b) (in custom com at level 75, right associativity).
Open Scope com_scope.
(** We can now write [3 + (X * 2)] instead of [APlus 3 (AMult X 2)],
and [true && ~(X <= 4)] instead of [BAnd true (BNot (BLe X 4))]. *)
Definition example_aexp : aexp := <{ 3 + (X * 2) }>.
Definition example_bexp : bexp := <{ true && ~(X <= 4) }>.
(** One downside of these and notation tricks -- coercions in
particular -- is that they can make it a little harder for humans
to calculate the types of expressions. If you ever find yourself
confused, try doing [Set Printing Coercions] to see exactly what
is going on. *)
Print example_bexp.
(* ===> example_bexp = <{(true && ~ (X <= 4))}> *)
Set Printing Coercions.
Print example_bexp.
(* ===> example_bexp = <{(true && ~ (AId X <= ANum 4))}> *)
Unset Printing Coercions.
(* ================================================================= *)
(** ** Evaluation *)
(** The arith and boolean evaluators are extended to handle
variables in the obvious way, taking a state as an extra
argument: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <--- NEW *)
| <{a1 + a2}> => (aeval st a1) + (aeval st a2)
| <{a1 - a2}> => (aeval st a1) - (aeval st a2)
| <{a1 * a2}> => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| <{true}> => true
| <{false}> => false
| <{a1 = a2}> => (aeval st a1) =? (aeval st a2)
| <{a1 <= a2}> => (aeval st a1) <=? (aeval st a2)
| <{~ b1}> => negb (beval st b1)
| <{b1 && b2}> => andb (beval st b1) (beval st b2)
end.
(** We specialize our notation for total maps to the specific case of
states, i.e. using [(_ !-> 0)] as empty state. *)
Definition empty_st := (_ !-> 0).
(** Now we can add a notation for a "singleton state" with just one
variable bound to a value. *)
Notation "x '!->' v" := (t_update empty_st x v) (at level 100).
Example aexp1 :
aeval (X !-> 5) <{ (3 + (X * 2))}>
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (X !-> 5) <{ true && ~(X <= 4)}>
= true.
Proof. reflexivity. Qed.
(* ################################################################# *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (sometimes called _statements_). *)
(* ================================================================= *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar.
c := skip | x := a | c ; c | if b then c else c end
| while b do c end
*)
(** Here is the formal definition of the abstract syntax of
commands: *)
Inductive com : Type :=
| CSkip
| CAss (x : string) (a : aexp)
| CSeq (c1 c2 : com)
| CIf (b : bexp) (c1 c2 : com)
| CWhile (b : bexp) (c : com).
(** As for expressions, we can use a few [Notation] declarations to
make reading and writing Imp programs more convenient. *)
Notation "'skip'" :=
CSkip (in custom com at level 0) : com_scope.
Notation "x := y" :=
(CAss x y)
(in custom com at level 0, x constr at level 0,
y at level 85, no associativity) : com_scope.
Notation "x ; y" :=
(CSeq x y)
(in custom com at level 90, right associativity) : com_scope.
Notation "'if' x 'then' y 'else' z 'end'" :=
(CIf x y z)
(in custom com at level 89, x at level 99,
y at level 99, z at level 99) : com_scope.
Notation "'while' x 'do' y 'end'" :=
(CWhile x y)
(in custom com at level 89, x at level 99, y at level 99) : com_scope.
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
<{ Z := X;
Y := 1;
while ~(Z = 0) do
Y := Y * Z;
Z := Z - 1
end }>.
Print fact_in_coq.
(* ================================================================= *)
(** ** Desugaring notations *)
(** Coq offers a rich set of features to manage the increasing
complexity of the objects we work with, such as coercions
and notations. However, their heavy usage can make for quite
overwhelming syntax. It is often instructive to "turn off"
those features to get a more elementary picture of things,
using the following commands:
- [Unset Printing Notations] (undo with [Set Printing Notations])
- [Set Printing Coercions] (undo with [Unset Printing Coercions])
- [Set Printing All] (undo with [Unset Printing All])
These commands can also be used in the middle of a proof,
to elaborate the current goal and context.
*)
Unset Printing Notations.
Print fact_in_coq.
(* ===>
fact_in_coq =
CSeq (CAss Z X)
(CSeq (CAss Y (S O))
(CWhile (BNot (BEq Z O))
(CSeq (CAss Y (AMult Y Z))
(CAss Z (AMinus Z (S O))))))
: com *)
Set Printing Notations.
Set Printing Coercions.
Print fact_in_coq.
(* ===>
fact_in_coq =
<{ Z := (AId X);
Y := (ANum 1);
while ~ (AId Z) = (ANum 0) do
Y := (AId Y) * (AId Z);
Z := (AId Z) - (ANum 1)
end }>
: com *)
Unset Printing Coercions.
(* ================================================================= *)
(** ** The [Locate] command *)
(* ----------------------------------------------------------------- *)
(** *** Finding notations *)
(** When faced with unknown notation, use [Locate] with a _string_
containing one of its symbols to see its possible interpretations. *)
Locate "&&".
(* ===>
Notation
"x && y" := BAnd x y (default interpretation)
"x && y" := andb x y : bool_scope (default interpretation)
*)
Locate ";".
(* ===>
Notation
"x '|->' v ';' m" := update m x v (default interpretation)
"x ; y" := CSeq x y : com_scope (default interpretation)
"x '!->' v ';' m" := t_update m x v (default interpretation)
"[ x ; y ; .. ; z ]" := cons x (cons y .. (cons z nil) ..) : list_scope
(default interpretation) *)
Locate "while".
(* ===>
Notation
"'while' x 'do' y 'end'" := CWhile x y : com_scope (default interpretation)
"'_' '!->' v" := t_empty v (default interpretation)
*)
(* ----------------------------------------------------------------- *)
(** *** Finding identifiers *)
(** When used with an identifier, the command [Locate] prints
the full path to every value in scope with the same name.
This is useful to troubleshoot problems due to variable
shadowing. *)
Locate aexp.
(* ===>
Inductive LF.Imp.aexp
Inductive LF.Imp.AExp.aexp
(shorter name to refer to it in current context is AExp.aexp)
Inductive LF.Imp.aevalR_division.aexp
(shorter name to refer to it in current context is aevalR_division.aexp)
Inductive LF.Imp.aevalR_extended.aexp
(shorter name to refer to it in current context is aevalR_extended.aexp)
*)
(* ================================================================= *)
(** ** More Examples *)
(** Assignment: *)
Definition plus2 : com :=
<{ X := X + 2 }>.
Definition XtimesYinZ : com :=
<{ Z := X * Y }>.
Definition subtract_slowly_body : com :=
<{ Z := Z - 1 ;
X := X - 1 }>.
(* ----------------------------------------------------------------- *)
(** *** Loops *)
Definition subtract_slowly : com :=
<{ while ~(X = 0) do
subtract_slowly_body
end }>.
Definition subtract_3_from_5_slowly : com :=
<{ X := 3 ;
Z := 5 ;
subtract_slowly }>.
(* ----------------------------------------------------------------- *)
(** *** An infinite loop: *)
Definition loop : com :=
<{ while true do
skip
end }>.
(* ################################################################# *)
(** * Evaluating Commands *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [while] loops don't necessarily terminate makes
defining an evaluation function tricky... *)
(* ================================================================= *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [while] case. *)
(** The following declaration is needed to be able to use the
notations in match patterns. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| <{ skip }> =>
st
| <{ x := a }> =>
(x !-> (aeval st a) ; st)
| <{ c1 ; c2 }> =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| <{ if b then c1 else c2 end}> =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| <{ while b do c end }> =>
st (* bogus *)
end.
(** In a traditional functional programming language like OCaml or
Haskell we could add the [while] case as follows:
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| while b do c end =>
if (beval st b)
then ceval_fun st (c ; while b do c end)
else st
end.
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it _doesn't_ always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming
language but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is
an (invalid!) program showing what would go wrong if Coq
allowed non-terminating recursive functions:
Fixpoint loop_false (n : nat) : False := loop_false n.
That is, propositions like [False] would become provable
([loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs,
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks and workarounds (see chapter [ImpCEvalFun]
if you're curious about what those might be). *)
(* ================================================================= *)
(** ** Evaluation as a Relation *)
(** Here's a better way: define [ceval] as a _relation_ rather than a
_function_ -- i.e., define it in [Prop] instead of [Type], as we
did for [aevalR] above. *)
(** This is an important change. Besides freeing us from awkward
workarounds, it gives us a lot more flexibility in the definition.
For example, if we add nondeterministic features like [any] to the
language, we want the definition of evaluation to be
nondeterministic -- i.e., not only will it not be total, it will
not even be a function! *)
(** We'll use the notation [st =[ c ]=> st'] for the [ceval] relation:
[st =[ c ]=> st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']". *)
(* ----------------------------------------------------------------- *)
(** *** Operational Semantics *)
(** Here is an informal definition of evaluation, presented as inference
rules for readability:
----------------- (E_Skip)
st =[ skip ]=> st
aeval st a = n
------------------------------- (E_Ass)
st =[ x := a ]=> (x !-> n ; st)
st =[ c1 ]=> st'
st' =[ c2 ]=> st''
--------------------- (E_Seq)
st =[ c1;c2 ]=> st''
beval st b = true
st =[ c1 ]=> st'
-------------------------------------- (E_IfTrue)
st =[ if b then c1 else c2 end ]=> st'
beval st b = false
st =[ c2 ]=> st'
-------------------------------------- (E_IfFalse)
st =[ if b then c1 else c2 end ]=> st'
beval st b = false
----------------------------- (E_WhileFalse)
st =[ while b do c end ]=> st
beval st b = true
st =[ c ]=> st'
st' =[ while b do c end ]=> st''
-------------------------------- (E_WhileTrue)
st =[ while b do c end ]=> st''
*)
(** Here is the formal definition. Make sure you understand
how it corresponds to the inference rules. *)
Reserved Notation
"st '=[' c ']=>' st'"
(at level 40, c custom com at level 99,
st constr, st' constr at next level).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
st =[ skip ]=> st
| E_Ass : forall st a n x,
aeval st a = n ->
st =[ x := a ]=> (x !-> n ; st)
| E_Seq : forall c1 c2 st st' st'',
st =[ c1 ]=> st' ->
st' =[ c2 ]=> st'' ->
st =[ c1 ; c2 ]=> st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
st =[ c1 ]=> st' ->
st =[ if b then c1 else c2 end]=> st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
st =[ c2 ]=> st' ->
st =[ if b then c1 else c2 end]=> st'
| E_WhileFalse : forall b st c,
beval st b = false ->
st =[ while b do c end ]=> st
| E_WhileTrue : forall st st' st'' b c,
beval st b = true ->
st =[ c ]=> st' ->
st' =[ while b do c end ]=> st'' ->
st =[ while b do c end ]=> st''
where "st =[ c ]=> st'" := (ceval c st st').
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
empty_st =[
X := 2;
if (X <= 1)
then Y := 3
else Z := 4
end
]=> (Z !-> 4 ; X !-> 2).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (X !-> 2).
- (* assignment command *)
apply E_Ass. reflexivity.
- (* if command *)
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity.
Qed.
(** **** Exercise: 2 stars, standard (ceval_example2) *)
Example ceval_example2:
empty_st =[
X := 0;
Y := 1;
Z := 2
]=> (Z !-> 2 ; Y !-> 1 ; X !-> 0).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Set Printing Implicit.
Check @ceval_example2.
(** **** Exercise: 3 stars, standard, optional (pup_to_n)
Write an Imp program that sums the numbers from [1] to [X]
(inclusive: [1 + 2 + ... + X]) in the variable [Y]. Your program
should update the state as shown in theorem [pup_to_2_ceval],
which you can reverse-engineer to discover the program you should
write. The proof of that theorem will be somewhat lengthy. *)
Definition pup_to_n : com
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem pup_to_2_ceval :
(X !-> 2) =[
pup_to_n
]=> (X !-> 0 ; Y !-> 3 ; X !-> 1 ; Y !-> 2 ; Y !-> 0 ; X !-> 2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it frees us from the artificial
requirement that evaluation should be a total function. But it
also raises a question: Is the second definition of evaluation
really a partial _function_? Or is it possible that, beginning from
the same state [st], we could evaluate some command [c] in
different ways to reach two different output states [st'] and
[st'']?
In fact, this cannot happen: [ceval] _is_ a partial function: *)
Theorem ceval_deterministic: forall c st st1 st2,
st =[ c ]=> st1 ->
st =[ c ]=> st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
induction E1; intros st2 E2; inversion E2; subst.
- (* E_Skip *) reflexivity.
- (* E_Ass *) reflexivity.
- (* E_Seq *)
rewrite (IHE1_1 st'0 H1) in *.
apply IHE1_2. assumption.
- (* E_IfTrue, b evaluates to true *)
apply IHE1. assumption.
- (* E_IfTrue, b evaluates to false (contradiction) *)
rewrite H in H5. discriminate.
- (* E_IfFalse, b evaluates to true (contradiction) *)
rewrite H in H5. discriminate.
- (* E_IfFalse, b evaluates to false *)
apply IHE1. assumption.
- (* E_WhileFalse, b evaluates to false *)
reflexivity.
- (* E_WhileFalse, b evaluates to true (contradiction) *)
rewrite H in H2. discriminate.
- (* E_WhileTrue, b evaluates to false (contradiction) *)
rewrite H in H4. discriminate.
- (* E_WhileTrue, b evaluates to true *)
rewrite (IHE1_1 st'0 H3) in *.
apply IHE1_2. assumption. Qed.
(* ################################################################# *)
(** * Reasoning About Imp Programs *)
(** We'll get deeper into more systematic and powerful techniques for
reasoning about Imp programs in _Programming Language
Foundations_, but we can get some distance just working with the
bare definitions. This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
st =[ plus2 ]=> st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(** Inverting [Heval] essentially forces Coq to expand one step of
the [ceval] computation -- in this case revealing that [st']
must be [st] extended with the new value of [X], since [plus2]
is an assignment. *)
inversion Heval. subst. clear Heval. simpl.
apply t_update_eq. Qed.
(** **** Exercise: 3 stars, standard, optional (XtimesYinZ_spec)
State and prove a specification of [XtimesYinZ]. *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_XtimesYinZ_spec : option (nat*string) := None.
(** [] *)
(** **** Exercise: 3 stars, standard, especially useful (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(st =[ loop ]=> st').
Proof.
intros st st' contra. unfold loop in contra.
remember <{ while true do skip end }> as loopdef
eqn:Heqloopdef.
(** Proceed by induction on the assumed derivation showing that
[loopdef] terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[discriminate]). *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard (no_whiles_eqv)
Consider the following function: *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| <{ skip }> =>
true
| <{ _ := _ }> =>
true
| <{ c1 ; c2 }> =>
andb (no_whiles c1) (no_whiles c2)
| <{ if _ then ct else cf end }> =>
andb (no_whiles ct) (no_whiles cf)
| <{ while _ do _ end }> =>
false
end.
(** This predicate yields [true] just on programs that have no while
loops. Using [Inductive], write a property [no_whilesR] such that
[no_whilesR c] is provable exactly when [c] is a program with no
while loops. Then prove its equivalence with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
(* FILL IN HERE *)
.
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, standard (no_whiles_terminating)
Imp programs that don't involve while loops always terminate.
State and prove a theorem [no_whiles_terminating] that says this.
Use either [no_whiles] or [no_whilesR], as you prefer. *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_no_whiles_terminating : option (nat*string) := None.
(** [] *)
(* ################################################################# *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars, standard (stack_compiler)
Old HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a _stack_. For instance, the expression
(2*3)+(3*(4-2))
would be written as
2 3 * 3 4 2 - * +
and evaluated like this (where we show the program being evaluated
on the right and the contents of the stack on the left):
[ ] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
The goal of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract the first number from the second.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush (n : nat)
| SLoad (x : string)
| SPlus
| SMinus
| SMult.
(** Write a function to evaluate programs in the stack language. It
should take as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and it should return the
stack after executing the program. Test your function on the
examples below.
Note that it is unspecified what to do when encountering an
[SPlus], [SMinus], or [SMult] instruction if the stack contains
fewer than two elements. In a sense, it is immaterial what we do,
since a correct compiler will never emit such a malformed program.
But for sake of later exercises, it would be best to skip the
offending instruction and continue with the next one. *)
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Check s_execute.
Example s_execute1 :
s_execute empty_st []
[SPush 5; SPush 3; SPush 1; SMinus]
= [2; 5].
(* FILL IN HERE *) Admitted.
Example s_execute2 :
s_execute (X !-> 3) [3;4]
[SPush 4; SLoad X; SMult; SPlus]
= [15; 4].
(* FILL IN HERE *) Admitted.
(** Next, write a function that compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** After you've defined [s_compile], prove the following to test
that it works. *)
Example s_compile1 :
s_compile <{ X - (2 * Y) }>
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard (execute_app) *)
(** Execution can be decomposed in the following sense: executing
stack program [p1 ++ p2] is the same as executing [p1], taking
the resulting stack, and executing [p2] from that stack. Prove
that fact. *)
Theorem execute_app : forall st p1 p2 stack,
s_execute st stack (p1 ++ p2) = s_execute st (s_execute st stack p1) p2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard (stack_compiler_correct) *)
(** Now we'll prove the correctness of the compiler implemented in the
previous exercise. Begin by proving the following lemma. If it
becomes difficult, consider whether your implementation of
[s_execute] or [s_compile] could be simplified. *)
Lemma s_compile_correct_aux : forall st e stack,
s_execute st stack (s_compile e) = aeval st e :: stack.
Proof.
(* FILL IN HERE *) Admitted.
(** The main theorem should be a very easy corollary of that lemma. *)
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st [] (s_compile e) = [ aeval st e ].
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (short_circuit)
Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. (N.b. This is only true because expression
evaluation in Imp is rather simple. In a bigger language where
evaluating an expression might diverge, the short-circuiting [BAnd]
would _not_ be equivalent to the original, since it would make more
programs terminate.) *)
(* FILL IN HERE
[] *)
Module BreakImp.
(** **** Exercise: 4 stars, advanced (break_imp)
Imperative languages like C and Java often include a [break] or
similar statement for interrupting the execution of loops. In this
exercise we consider how to add [break] to Imp. First, we need to
enrich the language of commands with an additional case. *)
Inductive com : Type :=
| CSkip
| CBreak (* <--- NEW *)
| CAss (x : string) (a : aexp)
| CSeq (c1 c2 : com)
| CIf (b : bexp) (c1 c2 : com)
| CWhile (b : bexp) (c : com).
Notation "'break'" := CBreak (in custom com at level 0).
Notation "'skip'" :=
CSkip (in custom com at level 0) : com_scope.
Notation "x := y" :=
(CAss x y)
(in custom com at level 0, x constr at level 0,
y at level 85, no associativity) : com_scope.
Notation "x ; y" :=
(CSeq x y)
(in custom com at level 90, right associativity) : com_scope.
Notation "'if' x 'then' y 'else' z 'end'" :=
(CIf x y z)
(in custom com at level 89, x at level 99,
y at level 99, z at level 99) : com_scope.
Notation "'while' x 'do' y 'end'" :=
(CWhile x y)
(in custom com at level 89, x at level 99, y at level 99) : com_scope.
(** Next, we need to define the behavior of [break]. Informally,
whenever [break] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop should terminate. (If there aren't any
enclosing loops, then the whole program simply terminates.) The
final state should be the same as the one in which the [break]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [break]. In those cases, [break] should only
terminate the _innermost_ loop. Thus, after executing the
following...
X := 0;
Y := 1;
while ~(0 = Y) do
while true do
break
end;
X := 1;
Y := Y - 1
end
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [break] statement: *)
Inductive result : Type :=
| SContinue
| SBreak.
Reserved Notation "st '=[' c ']=>' st' '/' s"
(at level 40, c custom com at level 99, st' constr at next level).
(** Intuitively, [st =[ c ]=> st' / s] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that the innermost surrounding loop (or the whole program) should
exit immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[st =[ c ]=> st' / s]" relation is very
similar to the one we gave above for the regular evaluation
relation ([st =[ c ]=> st']) -- we just need to handle the
termination signals appropriately:
- If the command is [skip], then the state doesn't change and
execution of any enclosing loop can continue normally.
- If the command is [break], the state stays unchanged but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [if b then c1 else c2 end], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state is the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal
generated there.
- Finally, for a loop of the form [while b do c end], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [break] only terminates the
innermost loop, [while] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
(* FILL IN HERE *)
Inductive ceval : com -> state -> result -> state -> Prop :=
| E_Skip : forall st,
st =[ CSkip ]=> st / SContinue
(* FILL IN HERE *)
where "st '=[' c ']=>' st' '/' s" := (ceval c st s st').
(** Now prove the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
st =[ break; c ]=> st' / s ->
st = st'.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_continue : forall b c st st' s,
st =[ while b do c end ]=> st' / s ->
s = SContinue.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
st =[ c ]=> st' / SBreak ->
st =[ while b do c end ]=> st' / SContinue.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (while_break_true) *)
Theorem while_break_true : forall b c st st',
st =[ while b do c end ]=> st' / SContinue ->
beval st' b = true ->
exists st'', st'' =[ c ]=> st' / SBreak.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced, optional (ceval_deterministic) *)
Theorem ceval_deterministic: forall (c:com) st st1 st2 s1 s2,
st =[ c ]=> st1 / s1 ->
st =[ c ]=> st2 / s2 ->
st1 = st2 /\ s1 = s2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End BreakImp.
(** **** Exercise: 4 stars, standard, optional (add_for_loop)
Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this
file are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE
[] *)
(* 2020-09-09 21:08 *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3B_PP_SYMBOL_V
`define SKY130_FD_SC_HS__AND3B_PP_SYMBOL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3B_PP_SYMBOL_V
|
//re-order buffer did three things
//In dispatch, unless ROB is full, allocate new ROB entry for incoming instruction at tail, increase the tail
//during the recovery time (when dec_tail|recover is 1), the ROB will not allocate new entry for instructions in dispatch stage
//In complete, if the completed instruction is not a branch. The ROB entry indexed by rob_number will be marked as complete.
//if it is a branch misprediction or jump, stall all things (flush IF/DP) in the first cycle (when stall_recover is high),
//decrease the tail by 1 (since the tail points to next allocated instr, cannot recover from tail entry). Then,
//assert the recover signal, all data(PR_old, PR_new, rd) are ready, during the time recover is high, flush RS entry (ROB# match),
//flush MT, FL, LSQ (all for ROB# match), flush IS/EX(if ROB# match), EX/CMP(ROB# match). If ROB# doesn't match, stall that block.
//after recover becomes low, the changeFlow_out becomes 1 for 1 cycle, thus PC changes to correct PC, changeFlow also flush the IF/DP
//when recover is low, other parts are allowed to go (MT,RS,FL will not allocate since the IF/DP is NOP, however some instructions
//might still in IS/EX or EX/CMP, let them go
module reorder_buffer(
input rst, clk,
input isDispatch, //serve as the write enable of FIFO
input isSW, //
input RegDest, //stored for roll back, if it is 1, MT and FL need to be restored
input [5:0] PR_old_DP, //from map table, the previous PR#
input [5:0] PR_new_DP,
input [4:0] rd_DP, //architectural destinatioMn register
input complete, //from complete stage, if there is intruction completes
input [3:0] rob_number, //from the complete stage, used to set complete bit
input [31:0] jb_addr, //from complete stage
input changeFlow, //asserted if branch-misprediction or jump, from complete, start the state machine
input hazard_stall, //stall because of structure hazard, won't allocate new entry
output [3:0] rob_num_dp, //rob number in dispatch stage
output [5:0] PR_old_RT, //PR_old to be retired
output RegDest_retire, //only if the instruction write register, the PR_old is returned to MT and FL
output retire_reg, //read enable signal of FIFO
output retire_ST,
output [3:0] retire_rob, //for load/store queue, indicate which ROB entry is retired
output full, empty,
output RegDest_out,
output [5:0] PR_old_flush,
output [5:0] PR_new_flush,
output [4:0] rd_flush,
output [3:0] out_rob_num, //for recovery, provide the current ROB number for FL, MT, RS
output reg changeFlow_out, //asserted for one cycle after all recovery works done
output reg [31:0] changeFlow_addr,
output reg recover //recover signal, inform RS, MT, FL, LSQ, IS/EX, EX/CMP to flush(ROB# match) or stall (ROB# not match)
);
reg [18:0] rob [0:15]; //[18]: RegDest, (whether bet PR back to MT and FL) [17]: isSW, [16:12]rd, [11:6] pr_old, [5:0] pr_new
reg [15:0] complete_array;
/////////////////////////////////////////////Synch FIFO structure///////////////////////////////////////////
reg [3:0] head, tail;
reg dec_tail; //for recovery
assign rob_num_dp = tail;
wire read, write;
//no read or write of ROB during recovery
assign write = isDispatch && !full && !recover && !hazard_stall;
assign read = retire_reg && !empty && !recover && !hazard_stall;
//head logic
always @(posedge clk or negedge rst) begin
if (!rst) begin
head <= 4'h0;
end
else if (read) begin
head <= head + 1;
end
end
assign retire_reg = complete_array[head]; //if the head is complete, retire it
assign PR_old_RT = rob[head][11:6]; //the PR returned to free list
assign retire_ST = rob[head][17]; //tell SQ now a load/store is retired
assign RegDest_retire = rob[head][18];
assign retire_rob = head;
//tail logic
always @(posedge clk or negedge rst) begin
if (!rst)
tail <= 4'h0;
else if (dec_tail)
tail <= tail - 1; //when decreasing tail, the ROB will not accept new instructions
else if (write) begin
tail <= tail + 1;
rob[tail] <= {RegDest, isSW, rd_DP, PR_old_DP, PR_new_DP};
end
end
//Synch FIFO counter
reg [4:0] status_cnt;
always @(posedge clk or negedge rst) begin
if (!rst)
status_cnt <= 4'h0;
else if (write && !read) //write but not read
status_cnt <= status_cnt + 1;
else if (read && !write) //read but not write
status_cnt <= status_cnt - 1;
else if (dec_tail)
status_cnt <= status_cnt - 1;
end
assign full = status_cnt[4]; //if counter = 16, the FIFO is full
assign empty = ~(|status_cnt);
///////////////////////////////////////////////////end of synch FIFO///////////////////////////////////////////////////
//////////////////////////////complete part////////////////////////////////////
reg [3:0] branch_rob;
reg store_jb_addr;
genvar i;
generate for (i = 0; i < 16; i = i + 1) begin : complete_part
always @(posedge clk or negedge rst) begin
if (!rst)
complete_array[i] <= 0;
else if (rob_number == i && complete)
complete_array[i] <= 1'b1; //ROB# cannot equal to tail
else if (tail == i && write)
complete_array[i] <= 1'b0; //reset complete bit when allocate a new entry
end
end
endgenerate
//changeFlow address and ROB number for branch/jump
always @(posedge clk or negedge rst) begin
if (!rst) begin
changeFlow_addr <= 0;
branch_rob <= 0;
end
else if (store_jb_addr) begin
changeFlow_addr <= jb_addr;
branch_rob <= rob_number; //store the ROB# of branch when here comes a branch
end
end
//////////////////////////////end of complete part/////////////////////////////////////
assign out_rob_num = tail; //may need to store ROB number in RS, when completing instructions can index the ROB to set
//during recovery, this number is also used for indexing the flush entry
localparam IDLE = 1'b0;
localparam REC = 1'b1;
reg state, nstate;
always @(posedge clk or negedge rst) begin
if (!rst)
state <= IDLE;
else
state <= nstate;
end
wire recover_end = (branch_rob + 1 == tail);
always @(*) begin
nstate = IDLE;
dec_tail = 0;
recover = 0;
store_jb_addr = 0;
changeFlow_out = 0;
case (state)
IDLE: begin
if(complete && changeFlow) begin
nstate = REC;
dec_tail = 1;
recover = 1;
store_jb_addr = 1;
end
else
nstate = IDLE;
end
default: begin //recover
if(recover_end) begin
nstate = IDLE;
changeFlow_out = 1;
end
else begin
nstate = REC;
dec_tail = 1;
recover = 1;
end
end
endcase
end
//[16:12]rd, [11:6] t_old, [5:0] t_new
assign rd_flush = rob[tail-1][16:12];
assign PR_old_flush = rob[tail-1][11:6];
assign PR_new_flush = rob[tail-1][5:0];
assign RegDest_out = rob[tail-1][18];
//out_rob_tail assigned before, since it is used both in recovery and normal dispatch
endmodule
|
/*
* Copyright (c) 2015-2018 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* CPU top level
*/
`include "uparc_cpu_config.vh"
`include "uparc_cpu_common.vh"
`include "uparc_cpu_const.vh"
/* CPU */
module uparc_cpu_top(
clk,
nrst,
/* Interrupt input */
i_intr,
/* I-Port */
o_IAddr,
o_IRdC,
i_IData,
i_IRdy,
i_IErr,
/* D-Port */
o_DAddr,
o_DCmd,
o_DRnW,
o_DBen,
o_DData,
i_DData,
i_DRdy,
i_DErr
);
input wire clk;
input wire nrst;
/* Interrupt input */
input wire i_intr;
/* I-Port */
output wire [`UPARC_ADDR_WIDTH-1:0] o_IAddr;
output wire o_IRdC;
input wire [`UPARC_DATA_WIDTH-1:0] i_IData;
input wire i_IRdy;
input wire i_IErr;
/* D-Port */
output wire [`UPARC_ADDR_WIDTH-1:0] o_DAddr;
output wire o_DCmd;
output wire o_DRnW;
output wire [`UPARC_BEN_WIDTH-1:0] o_DBen;
output wire [`UPARC_DATA_WIDTH-1:0] o_DData;
input wire [`UPARC_DATA_WIDTH-1:0] i_DData;
input wire i_DRdy;
input wire i_DErr;
/************************ INTERNAL INTERCONNECT *******************************/
/* Program counter */
reg [`UPARC_ADDR_WIDTH-1:0] pc_next;
/* pc_p0 is the output from fetch stage */
reg [`UPARC_ADDR_WIDTH-1:0] pc_p1;
reg [`UPARC_ADDR_WIDTH-1:0] pc_p2;
reg [`UPARC_ADDR_WIDTH-1:0] pc_p3;
reg [`UPARC_ADDR_WIDTH-1:0] pc_p4;
/* Register file wires */
wire [`UPARC_REGNO_WIDTH-1:0] rf_rs;
wire [`UPARC_REG_WIDTH-1:0] rf_rs_data;
wire [`UPARC_REGNO_WIDTH-1:0] rf_rt;
wire [`UPARC_REG_WIDTH-1:0] rf_rt_data;
wire [`UPARC_REGNO_WIDTH-1:0] rf_rd;
wire [`UPARC_REG_WIDTH-1:0] rf_rd_data;
/* Instruction fetch unit wires */
wire [`UPARC_ADDR_WIDTH-1:0] ifu_addr;
wire [`UPARC_INSTR_WIDTH-1:0] ifu_instr_dat;
wire ifu_rd_cmd;
wire ifu_busy;
wire ifu_err_align;
wire ifu_err_bus;
/* Load-store unit wires */
wire [`UPARC_ADDR_WIDTH-1:0] lsu_addr;
wire [`UPARC_DATA_WIDTH-1:0] lsu_wdata;
wire [`UPARC_DATA_WIDTH-1:0] lsu_rdata;
wire [1:0] lsu_cmd;
wire lsu_rnw;
wire lsu_busy;
wire lsu_err_align;
wire lsu_err_bus;
/* Control signals */
wire exec_stall;
wire mem_stall;
wire fetch_stall;
wire wait_stall;
wire core_stall = fetch_stall || exec_stall || mem_stall || wait_stall;
wire bus_error_p0;
wire addr_error_p0;
wire base_decode_error_p1;
wire cop0_decode_error_p1;
wire decode_error_p1 = base_decode_error_p1 || cop0_decode_error_p1;
wire overfl_error_p2;
wire addr_error_p2;
wire syscall_trap_p2;
wire break_trap_p2;
wire bus_error_p3;
wire addr_error_p3;
/* Exception handling signals */
wire except_start_p3;
wire except_dly_slt_p3;
wire except_valid_p4;
wire [`UPARC_ADDR_WIDTH-1:0] except_haddr_p4;
wire nullify_fetch;
wire nullify_decode;
wire nullify_execute;
wire nullify_mem;
wire nullify_wb;
/* Coprocessor 0 wires */
wire cop0_op_p1;
wire [`UPARC_REGNO_WIDTH-1:0] cop0_cop_p1;
wire [`UPARC_REGNO_WIDTH-1:0] cop0_reg_no_p1;
wire [`UPARC_REG_WIDTH-1:0] cop0_reg_val_p1;
wire [`UPARC_REGNO_WIDTH-1:0] cop0_rt_no_p1;
wire [`UPARC_ADDR_WIDTH-11:0] cop0_ivtbase; /* IVT base */
wire cop0_ie; /* IE status */
wire cop0_intr_wait; /* Interrupt wait state */
/* Integer multiplication and division unit wires */
wire [`UPARC_REG_WIDTH-1:0] imuldiv_rd_val;
wire imuldiv_rd_valid;
/* Fetch stage output */
wire [`UPARC_INSTR_WIDTH-1:0] instr_p0;
wire [`UPARC_ADDR_WIDTH-1:0] pc_p0;
/* Decode stage output */
wire [`UPARC_REGNO_WIDTH-1:0] rd_no_p1;
wire [`UPARC_REGNO_WIDTH-1:0] rs_no_p1;
wire [`UPARC_REGNO_WIDTH-1:0] rt_no_p1;
wire [`UPARC_DATA_WIDTH-1:0] imm_p1;
wire [`UPARC_ALUOP_WIDTH-1:0] alu_op_p1;
wire [4:0] alu_inpt_p1;
wire alu_ovf_ex_p1;
wire [4:0] jump_p1;
wire jump_link_p1;
wire [`UPARC_IMDOP_WIDTH-1:0] imuldiv_op_p1;
wire [`UPARC_SWTRP_WIDTH-1:0] sw_trap_p1;
wire [`UPARC_LSUOP_WIDTH-1:0] lsu_op_p1;
wire lsu_lns_p1;
wire lsu_ext_p1;
assign rf_rs = rs_no_p1;
assign rf_rt = rt_no_p1;
wire [`UPARC_REG_WIDTH-1:0] rs_val_p1;
wire [`UPARC_REG_WIDTH-1:0] rt_val_p1;
/* Execute stage output */
wire [`UPARC_REGNO_WIDTH-1:0] rd_no_p2;
wire [`UPARC_REG_WIDTH-1:0] alu_result_p2;
wire [`UPARC_ADDR_WIDTH-1:0] jump_addr_p2;
wire jump_valid_p2;
wire [`UPARC_LSUOP_WIDTH-1:0] lsu_op_p2;
wire lsu_lns_p2;
wire lsu_ext_p2;
wire [`UPARC_DATA_WIDTH-1:0] mem_data_p2;
wire pend_mem_load_p2 = |lsu_op_p2 & lsu_lns_p2;
/* Memory access stage output */
wire [`UPARC_REGNO_WIDTH-1:0] rd_no_p3;
wire [`UPARC_REG_WIDTH-1:0] rd_val_p3;
/************************** UNITS INSTANCE ***********************************/
/** Register File **/
uparc_reg_file rf(
.clk(clk),
.nrst(nrst),
.rs(rf_rs),
.rs_data(rf_rs_data),
.rt(rf_rt),
.rt_data(rf_rt_data),
.rd(rf_rd),
.rd_data(rf_rd_data)
);
/** Instruction Fetch Unit **/
uparc_ifu ifu(
.clk(clk),
.nrst(nrst),
.addr(ifu_addr),
.instr_dat(ifu_instr_dat),
.rd_cmd(ifu_rd_cmd),
.busy(ifu_busy),
.err_align(ifu_err_align),
.err_bus(ifu_err_bus),
.o_IAddr(o_IAddr),
.o_IRdC(o_IRdC),
.i_IData(i_IData),
.i_IRdy(i_IRdy),
.i_IErr(i_IErr)
);
/** Load-Store Unit **/
uparc_lsu lsu(
.clk(clk),
.nrst(nrst),
.addr(lsu_addr),
.wdata(lsu_wdata),
.rdata(lsu_rdata),
.cmd(lsu_cmd),
.rnw(lsu_rnw),
.busy(lsu_busy),
.err_align(lsu_err_align),
.err_bus(lsu_err_bus),
.o_DAddr(o_DAddr),
.o_DCmd(o_DCmd),
.o_DRnW(o_DRnW),
.o_DBen(o_DBen),
.o_DData(o_DData),
.i_DData(i_DData),
.i_DRdy(i_DRdy),
.i_DErr(i_DErr)
);
/** Forwarding Unit **/
uparc_fwdu fwdu(
.rs(rs_no_p1),
.rs_data(rf_rs_data),
.rt(rt_no_p1),
.rt_data(rf_rt_data),
.rd_p2(rd_no_p2),
.rd_data_p2(alu_result_p2),
.pend_mem_load_p2(pend_mem_load_p2),
.rd_p3(rd_no_p3),
.rd_data_p3(rd_val_p3),
.rs_data_p1(rs_val_p1),
.rt_data_p1(rt_val_p1)
);
/** Coprocessor 0 **/
uparc_coproc0 coproc0(
.clk(clk),
.nrst(nrst),
/* Control signals */
.i_exec_stall(exec_stall),
.i_mem_stall(mem_stall),
.i_fetch_stall(fetch_stall),
.i_wait_stall(wait_stall),
.o_decode_error(cop0_decode_error_p1),
.i_except_start(except_start_p3),
.i_except_dly_slt(except_dly_slt_p3),
.i_except_raddr(pc_p3),
.i_except_raddr_dly(pc_p4),
.i_nullify_decode(nullify_decode),
.i_nullify_execute(nullify_execute),
.i_nullify_mem(nullify_mem),
.i_nullify_wb(nullify_wb),
/* COP0 signals */
.o_cop0_ivtbase(cop0_ivtbase),
.o_cop0_ie(cop0_ie),
.o_cop0_intr_wait(cop0_intr_wait),
/* Fetched instruction */
.i_instr(instr_p0),
/* Decoded coprocessor instruction */
.o_cop0_op_p1(cop0_op_p1),
.o_cop0_cop_p1(cop0_cop_p1),
.o_cop0_reg_no_p1(cop0_reg_no_p1),
.o_cop0_reg_val_p1(cop0_reg_val_p1),
.o_cop0_rt_no_p1(cop0_rt_no_p1),
/* Execute stage signals */
.i_cop0_alu_result_p2(alu_result_p2)
);
/** Coprocessor 0. Exceptions and Interrupts Unit. **/
uparc_coproc0_eiu coproc0_eiu(
.clk(clk),
.nrst(nrst),
/* External interrupt */
.i_intr(i_intr),
/* CU signals */
.i_exec_stall(exec_stall),
.i_mem_stall(mem_stall),
.i_fetch_stall(fetch_stall),
.o_wait_stall(wait_stall),
.i_jump_valid(jump_valid_p2),
/* COP0 signals */
.i_cop0_ivtbase(cop0_ivtbase),
.i_cop0_ie(cop0_ie),
.i_cop0_intr_wait(cop0_intr_wait),
/* Exception signals */
.o_except_start(except_start_p3),
.o_except_dly_slt(except_dly_slt_p3),
.o_except_valid(except_valid_p4),
.o_except_haddr(except_haddr_p4),
/* Error signals from stages */
.i_bus_error_p0(bus_error_p0),
.i_addr_error_p0(addr_error_p0),
.i_decode_error_p1(decode_error_p1),
.i_overfl_error_p2(overfl_error_p2),
.i_addr_error_p2(addr_error_p2),
.i_syscall_trap_p2(syscall_trap_p2),
.i_break_trap_p2(break_trap_p2),
.i_bus_error_p3(bus_error_p3),
.i_addr_error_p3(addr_error_p3),
/* Result nullify signals */
.o_nullify_fetch(nullify_fetch),
.o_nullify_decode(nullify_decode),
.o_nullify_execute(nullify_execute),
.o_nullify_mem(nullify_mem),
.o_nullify_wb(nullify_wb)
);
/** Integer multiplication and division unit **/
uparc_imuldivu imuldivu(
.clk(clk),
.nrst(nrst),
/* Control signals */
.o_exec_stall(exec_stall),
.i_mem_stall(mem_stall),
.i_fetch_stall(fetch_stall),
.i_wait_stall(wait_stall),
.i_nullify_execute(nullify_execute),
.i_nullify_mem(nullify_mem),
.i_nullify_wb(nullify_wb),
/* Decoded operation */
.i_imuldiv_op(imuldiv_op_p1),
/* Operands */
.i_rs_val(rs_val_p1),
.i_rt_val(rt_val_p1),
/* Result of MFHI and MFLO */
.o_imuldiv_rd_val(imuldiv_rd_val),
.o_imuldiv_rd_valid(imuldiv_rd_valid)
);
/*************************** PIPELINE STAGES **********************************/
/** Fetch stage **/
uparc_fetch fetch(
.clk(clk),
.nrst(nrst),
/* Control signals */
.i_pc(pc_next),
.i_jump_addr(jump_addr_p2),
.i_jump_valid(jump_valid_p2),
.i_except_valid(except_valid_p4),
.i_except_haddr(except_haddr_p4),
.i_exec_stall(exec_stall),
.i_mem_stall(mem_stall),
.o_fetch_stall(fetch_stall),
.i_wait_stall(wait_stall),
.o_bus_error(bus_error_p0),
.o_addr_error(addr_error_p0),
.i_nullify(nullify_fetch),
/* IFU signals */
.o_addr(ifu_addr),
.i_instr_dat(ifu_instr_dat),
.o_rd_cmd(ifu_rd_cmd),
.i_busy(ifu_busy),
.i_err_align(ifu_err_align),
.i_err_bus(ifu_err_bus),
/* Fetched instruction */
.o_instr(instr_p0),
.o_pc(pc_p0)
);
/** Decode stage **/
uparc_decode decode(
.clk(clk),
.nrst(nrst),
/* Control signals */
.i_pc(pc_p0),
.i_exec_stall(exec_stall),
.i_mem_stall(mem_stall),
.i_fetch_stall(fetch_stall),
.i_wait_stall(wait_stall),
.o_decode_error(base_decode_error_p1),
.i_nullify(nullify_decode),
/* Coprocessor 0 */
.i_cop0_cop(cop0_cop_p1),
.i_cop0_reg_no(cop0_reg_no_p1),
.i_cop0_rt_no(cop0_rt_no_p1),
/* Fetched instruction */
.i_instr(instr_p0),
/* Decoded instruction */
.o_rd_no(rd_no_p1),
.o_rs_no(rs_no_p1),
.o_rt_no(rt_no_p1),
.o_imm(imm_p1),
.o_alu_op(alu_op_p1),
.o_alu_inpt(alu_inpt_p1),
.o_alu_ovf_ex(alu_ovf_ex_p1),
.o_jump(jump_p1),
.o_jump_link(jump_link_p1),
.o_imuldiv_op(imuldiv_op_p1),
.o_sw_trap(sw_trap_p1),
.o_lsu_op(lsu_op_p1),
.o_lsu_lns(lsu_lns_p1),
.o_lsu_ext(lsu_ext_p1)
);
/** Execute stage **/
uparc_execute execute(
.clk(clk),
.nrst(nrst),
/* Control signals */
.i_pc_p0(pc_next),
.i_pc_p1(pc_p0),
.i_exec_stall(exec_stall),
.i_mem_stall(mem_stall),
.i_fetch_stall(fetch_stall),
.i_wait_stall(wait_stall),
.o_overfl_error(overfl_error_p2),
.o_addr_error(addr_error_p2),
.o_syscall_trap(syscall_trap_p2),
.o_break_trap(break_trap_p2),
.i_nullify(nullify_execute),
/* Coprocessor 0 */
.i_cop0_op(cop0_op_p1),
.i_cop0_cop(cop0_cop_p1),
.i_cop0_reg_val(cop0_reg_val_p1),
/* Integer multiplication and division unit */
.i_imuldiv_rd_val(imuldiv_rd_val),
.i_imuldiv_rd_valid(imuldiv_rd_valid),
/* Decoded instruction */
.i_rd_no(rd_no_p1),
.i_rs_val(rs_val_p1),
.i_rt_val(rt_val_p1),
.i_imm(imm_p1),
.i_alu_op(alu_op_p1),
.i_alu_inpt(alu_inpt_p1),
.i_alu_ovf_ex(alu_ovf_ex_p1),
.i_jump(jump_p1),
.i_jump_link(jump_link_p1),
.i_sw_trap(sw_trap_p1),
.i_lsu_op(lsu_op_p1),
.i_lsu_lns(lsu_lns_p1),
.i_lsu_ext(lsu_ext_p1),
/* Stage output */
.o_rd_no(rd_no_p2),
.o_alu_result(alu_result_p2),
.o_jump_addr(jump_addr_p2),
.o_jump_valid(jump_valid_p2),
.o_lsu_op(lsu_op_p2),
.o_lsu_lns(lsu_lns_p2),
.o_lsu_ext(lsu_ext_p2),
.o_mem_data(mem_data_p2)
);
/** Memory access stage **/
uparc_memory_access memory_access(
.clk(clk),
.nrst(nrst),
/* Control signals */
.i_exec_stall(exec_stall),
.o_mem_stall(mem_stall),
.i_fetch_stall(fetch_stall),
.i_wait_stall(wait_stall),
.o_bus_error(bus_error_p3),
.o_addr_error(addr_error_p3),
.i_nullify(nullify_mem),
/* LSU interface */
.lsu_addr(lsu_addr),
.lsu_wdata(lsu_wdata),
.lsu_rdata(lsu_rdata),
.lsu_cmd(lsu_cmd),
.lsu_rnw(lsu_rnw),
.lsu_busy(lsu_busy),
.lsu_err_align(lsu_err_align),
.lsu_err_bus(lsu_err_bus),
/* Result of execute stage */
.i_rd_no(rd_no_p2),
.i_alu_result(alu_result_p2),
.i_lsu_op(lsu_op_p2),
.i_lsu_lns(lsu_lns_p2),
.i_lsu_ext(lsu_ext_p2),
.i_mem_data(mem_data_p2),
/* Data for writeback */
.o_rd_no(rd_no_p3),
.o_rd_val(rd_val_p3)
);
/** Writeback stage **/
uparc_writeback writeback(
.clk(clk),
.nrst(nrst),
/* Control signals */
.i_exec_stall(exec_stall),
.i_mem_stall(mem_stall),
.i_fetch_stall(fetch_stall),
.i_wait_stall(wait_stall),
.i_nullify(nullify_wb),
/* Data for writeback */
.i_rd_no(rd_no_p3),
.i_rd_val(rd_val_p3),
.o_rd_no(rf_rd),
.o_rd_val(rf_rd_data)
);
/* Program counter */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
pc_next <= `UPARC_RESET_ADDR;
pc_p1 <= `UPARC_RESET_ADDR + 1*`UPARC_INSTR_SIZE;
pc_p2 <= `UPARC_RESET_ADDR + 2*`UPARC_INSTR_SIZE;
pc_p3 <= `UPARC_RESET_ADDR + 3*`UPARC_INSTR_SIZE;
pc_p4 <= `UPARC_RESET_ADDR + 4*`UPARC_INSTR_SIZE;
end
else if(!core_stall)
begin
pc_next <= ( !except_valid_p4 ?
(!jump_valid_p2 ? pc_next : jump_addr_p2) : except_haddr_p4 ) +
`UPARC_INSTR_SIZE;
pc_p1 <= pc_p0;
pc_p2 <= pc_p1;
pc_p3 <= pc_p2;
pc_p4 <= pc_p3;
end
end
endmodule /* uparc_cpu_top */
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SDFRTP_BEHAVIORAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S2S_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLYMETAL6S2S_PP_SYMBOL_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlymetal6s2s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S2S_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_4_V
`define SKY130_FD_SC_LP__SDFSTP_4_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A41OI_PP_BLACKBOX_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41OI_PP_BLACKBOX_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : sch2hdl
// / / Filename : Top.vf
// /___/ /\ Timestamp : 12/01/2014 17:59:05
// \ \ / \
// \___\/\___\
//
//Command: sch2hdl -intstyle ise -family spartan3e -verilog C:/Users/samue_000/Documents/FPGA/Projects/Stopwatch/sevensegdecoder/Top.vf -w C:/Users/samue_000/Documents/FPGA/Projects/Stopwatch/sevensegdecoder/Top.sch
//Design Name: Top
//Device: spartan3e
//Purpose:
// This verilog netlist is translated from an ECS schematic.It can be
// synthesized and simulated, but it should not be modified.
//
`timescale 1ns / 1ps
module DigitToSeg(in1,
in2,
in3,
in4,
in5,
in6,
in7,
in8,
mclk,
an,
dp,
seg);
input [3:0] in1;
input [3:0] in2;
input [3:0] in3;
input [3:0] in4;
input [3:0] in5;
input [3:0] in6;
input [3:0] in7;
input [3:0] in8;
input mclk;
output [7:0] an;
output [6:0] seg;
output dp;
//wire swt7;
wire XLXN_94;
wire [3:0] XLXN_102;
wire [2:0] XLXN_109;
sevensegdecoder XLXI_6 (.nIn(XLXN_102[3:0]),
.ssOut(seg[6:0]));
mux4_4bus XLXI_45 (.I0(in1[3:0]),
.I1(in2[3:0]),
.I2(in3[3:0]),
.I3(in4[3:0]),
.I4(in5[3:0]),
.I5(in6[3:0]),
.I6(in7[3:0]),
.I7(in8[3:0]),
.Sel(XLXN_109[2:0]),
.Y(XLXN_102[3:0]));
segClkDevider XLXI_47 (.clk(mclk),
.rst(),
.clk_div(XLXN_94));
//GND XLXI_48 (.G(swt7));
counter3bit XLXI_49 (.clk(XLXN_94),
.rst(),
.Q(XLXN_109[2:0]));
decoder_3_8 XLXI_50 (.I(XLXN_109[2:0]),
.dp(dp),
.an(an[7:0]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4BB_TB_V
`define SKY130_FD_SC_HD__OR4BB_TB_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or4bb.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C_N = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C_N = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C_N = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C_N = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hd__or4bb dut (.A(A), .B(B), .C_N(C_N), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4BB_TB_V
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:04:52 EST 2014
//
//
// Ports:
// Name I/O size props
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 256 reg
// wsiM0_MByteEn O 32 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// CLK I 1 clock
// RST_N I 1 reset
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 32
// wsiS0_MByteEn I 4
// wsiS0_MReqInfo I 8
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkWsiAdapter4B32B(CLK,
RST_N,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n);
input CLK;
input RST_N;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [31 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [3 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [255 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [31 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// signals for module outputs
wire [255 : 0] wsiM0_MData;
wire [31 : 0] wsiM0_MByteEn;
wire [11 : 0] wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo;
wire [2 : 0] wsiM0_MCmd;
wire wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy;
// inlined wires
wire [312 : 0] wsiM_reqFifo_x_wire_wget;
wire [95 : 0] wsiM_extStatusW_wget, wsiS_extStatusW_wget;
wire [60 : 0] wsiS_wsiReq_wget;
wire [31 : 0] wsi_Es_mData_w_wget;
wire [11 : 0] wsi_Es_mBurstLength_w_wget;
wire [7 : 0] wsi_Es_mReqInfo_w_wget;
wire [3 : 0] wsi_Es_mByteEn_w_wget;
wire [2 : 0] wsi_Es_mCmd_w_wget;
wire wsiM_operateD_1_wget,
wsiM_operateD_1_whas,
wsiM_peerIsReady_1_wget,
wsiM_peerIsReady_1_whas,
wsiM_reqFifo_dequeueing_whas,
wsiM_reqFifo_enqueueing_whas,
wsiM_reqFifo_x_wire_whas,
wsiM_sThreadBusy_pw_whas,
wsiS_operateD_1_wget,
wsiS_operateD_1_whas,
wsiS_peerIsReady_1_wget,
wsiS_peerIsReady_1_whas,
wsiS_reqFifo_doResetClr_whas,
wsiS_reqFifo_doResetDeq_whas,
wsiS_reqFifo_doResetEnq_whas,
wsiS_reqFifo_r_clr_whas,
wsiS_reqFifo_r_deq_whas,
wsiS_reqFifo_r_enq_whas,
wsiS_sThreadBusy_dw_wget,
wsiS_sThreadBusy_dw_whas,
wsiS_wsiReq_whas,
wsi_Es_mBurstLength_w_whas,
wsi_Es_mBurstPrecise_w_whas,
wsi_Es_mByteEn_w_whas,
wsi_Es_mCmd_w_whas,
wsi_Es_mDataInfo_w_whas,
wsi_Es_mData_w_whas,
wsi_Es_mReqInfo_w_whas,
wsi_Es_mReqLast_w_whas;
// register isFull
reg isFull;
wire isFull_D_IN, isFull_EN;
// register isLast
reg isLast;
wire isLast_D_IN, isLast_EN;
// register pos
reg [2 : 0] pos;
wire [2 : 0] pos_D_IN;
wire pos_EN;
// register stage_0
reg [60 : 0] stage_0;
wire [60 : 0] stage_0_D_IN;
wire stage_0_EN;
// register stage_1
reg [60 : 0] stage_1;
wire [60 : 0] stage_1_D_IN;
wire stage_1_EN;
// register stage_2
reg [60 : 0] stage_2;
wire [60 : 0] stage_2_D_IN;
wire stage_2_EN;
// register stage_3
reg [60 : 0] stage_3;
wire [60 : 0] stage_3_D_IN;
wire stage_3_EN;
// register stage_4
reg [60 : 0] stage_4;
wire [60 : 0] stage_4_D_IN;
wire stage_4_EN;
// register stage_5
reg [60 : 0] stage_5;
wire [60 : 0] stage_5_D_IN;
wire stage_5_EN;
// register stage_6
reg [60 : 0] stage_6;
wire [60 : 0] stage_6_D_IN;
wire stage_6_EN;
// register stage_7
reg [60 : 0] stage_7;
wire [60 : 0] stage_7_D_IN;
wire stage_7_EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind_D_IN;
wire wsiM_burstKind_EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky_D_IN, wsiM_errorSticky_EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount_D_IN;
wire wsiM_iMesgCount_EN;
// register wsiM_isReset_isInReset
reg wsiM_isReset_isInReset;
wire wsiM_isReset_isInReset_D_IN, wsiM_isReset_isInReset_EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD_D_IN, wsiM_operateD_EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount_D_IN;
wire wsiM_pMesgCount_EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady_D_IN, wsiM_peerIsReady_EN;
// register wsiM_reqFifo_cntr_r
reg [1 : 0] wsiM_reqFifo_cntr_r;
wire [1 : 0] wsiM_reqFifo_cntr_r_D_IN;
wire wsiM_reqFifo_cntr_r_EN;
// register wsiM_reqFifo_q_0
reg [312 : 0] wsiM_reqFifo_q_0;
reg [312 : 0] wsiM_reqFifo_q_0_D_IN;
wire wsiM_reqFifo_q_0_EN;
// register wsiM_reqFifo_q_1
reg [312 : 0] wsiM_reqFifo_q_1;
reg [312 : 0] wsiM_reqFifo_q_1_D_IN;
wire wsiM_reqFifo_q_1_EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d_D_IN, wsiM_sThreadBusy_d_EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR_D_IN;
wire wsiM_statusR_EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount_D_IN;
wire wsiM_tBusyCount_EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky_D_IN, wsiM_trafficSticky_EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind_D_IN;
wire wsiS_burstKind_EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky_D_IN, wsiS_errorSticky_EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount_D_IN;
wire wsiS_iMesgCount_EN;
// register wsiS_isReset_isInReset
reg wsiS_isReset_isInReset;
wire wsiS_isReset_isInReset_D_IN, wsiS_isReset_isInReset_EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength_D_IN;
wire wsiS_mesgWordLength_EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD_D_IN, wsiS_operateD_EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount_D_IN;
wire wsiS_pMesgCount_EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady_D_IN, wsiS_peerIsReady_EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg_D_IN;
wire wsiS_reqFifo_countReg_EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid_D_IN, wsiS_reqFifo_levelsValid_EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR_D_IN;
wire wsiS_statusR_EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount_D_IN;
wire wsiS_tBusyCount_EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky_D_IN, wsiS_trafficSticky_EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount_D_IN;
wire wsiS_wordCount_EN;
// ports of submodule wsiS_reqFifo
wire [60 : 0] wsiS_reqFifo_D_IN, wsiS_reqFifo_D_OUT;
wire wsiS_reqFifo_CLR,
wsiS_reqFifo_DEQ,
wsiS_reqFifo_EMPTY_N,
wsiS_reqFifo_ENQ,
wsiS_reqFifo_FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset;
// inputs to muxes for submodule ports
wire [312 : 0] MUX_wsiM_reqFifo_q_0_write_1__VAL_1,
MUX_wsiM_reqFifo_q_0_write_1__VAL_2,
MUX_wsiM_reqFifo_q_1_write_1__VAL_1;
wire [2 : 0] MUX_pos_write_1__VAL_1;
wire [1 : 0] MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1,
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2;
wire MUX_isFull_write_1__VAL_1,
MUX_wsiM_reqFifo_q_0_write_1__SEL_1,
MUX_wsiM_reqFifo_q_0_write_1__SEL_2,
MUX_wsiM_reqFifo_q_1_write_1__SEL_1,
MUX_wsiM_reqFifo_q_1_write_1__SEL_2,
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3;
// remaining internal signals
reg [31 : 0] x_byteEn__h6989;
wire [255 : 0] x_data__h6988;
wire [31 : 0] be__h8502,
be__h8521,
be__h8562,
be__h8618,
be__h8689,
be__h8775,
be__h8876,
be__h8992;
wire [27 : 0] x__h8880;
wire [23 : 0] x__h8779;
wire [19 : 0] x__h8693;
wire [15 : 0] x__h8622;
wire [11 : 0] x__h8566, x_burstLength__h6987;
wire [7 : 0] x__h8525;
wire _dfoo1, _dfoo3;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[312:310] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[309] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[308] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[307:296] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[295:40] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[39:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ;
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd61),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST(RST_N),
.CLK(CLK),
.D_IN(wsiS_reqFifo_D_IN),
.ENQ(wsiS_reqFifo_ENQ),
.DEQ(wsiS_reqFifo_DEQ),
.CLR(wsiS_reqFifo_CLR),
.D_OUT(wsiS_reqFifo_D_OUT),
.FULL_N(wsiS_reqFifo_FULL_N),
.EMPTY_N(wsiS_reqFifo_EMPTY_N));
// rule RL_wsiM_reqFifo_deq
assign WILL_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ;
// rule RL_wsiM_reqFifo_incCtr
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr =
wsiM_reqFifo_enqueueing_whas && wsiM_reqFifo_enqueueing_whas &&
!WILL_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_reqFifo_decCtr
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr =
WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing_whas ;
// rule RL_wsiM_reqFifo_both
assign WILL_FIRE_RL_wsiM_reqFifo_both =
wsiM_reqFifo_enqueueing_whas && WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_enqueueing_whas ;
// rule RL_wsiS_reqFifo_enq
assign WILL_FIRE_RL_wsiS_reqFifo_enq =
wsiS_reqFifo_FULL_N && wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq_wget[60:58] == 3'd1 ;
// rule RL_wsiS_reqFifo_reset
assign WILL_FIRE_RL_wsiS_reqFifo_reset =
WILL_FIRE_RL_wsiS_reqFifo_enq ||
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// inputs to muxes for submodule ports
assign MUX_wsiM_reqFifo_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo3 ;
assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo1 ;
assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ;
assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 =
wsiS_reqFifo_EMPTY_N && !isFull ;
assign MUX_isFull_write_1__VAL_1 = pos == 3'd7 || wsiS_reqFifo_D_OUT[57] ;
assign MUX_pos_write_1__VAL_1 = pos + 3'd1 ;
assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ;
assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 =
(wsiM_reqFifo_cntr_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 =
{ 3'd1,
isLast,
stage_0[56],
x_burstLength__h6987,
x_data__h6988,
x_byteEn__h6989,
stage_0[7:0] } ;
assign MUX_wsiM_reqFifo_q_1_write_1__VAL_1 =
(wsiM_reqFifo_cntr_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 :
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ;
// inlined wires
assign wsiS_wsiReq_wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq_whas = 1'd1 ;
assign wsiS_operateD_1_wget = 1'd1 ;
assign wsiS_operateD_1_whas = 1'd1 ;
assign wsiS_peerIsReady_1_wget = 1'd1 ;
assign wsiS_peerIsReady_1_whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw_wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw_whas =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_2 ;
assign wsiM_reqFifo_x_wire_whas = wsiM_reqFifo_enqueueing_whas ;
assign wsiM_operateD_1_wget = 1'd1 ;
assign wsiM_operateD_1_whas = 1'd1 ;
assign wsiM_peerIsReady_1_wget = 1'd1 ;
assign wsiM_peerIsReady_1_whas = wsiM0_SReset_n ;
assign wsi_Es_mCmd_w_wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w_whas = 1'd1 ;
assign wsi_Es_mBurstLength_w_wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w_whas = 1'd1 ;
assign wsi_Es_mData_w_wget = wsiS0_MData ;
assign wsi_Es_mData_w_whas = 1'd1 ;
assign wsi_Es_mByteEn_w_wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w_whas = 1'd1 ;
assign wsi_Es_mReqInfo_w_wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w_whas = 1'd1 ;
assign wsiS_reqFifo_r_enq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_r_deq_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_r_clr_whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_doResetDeq_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_doResetClr_whas = 1'b0 ;
assign wsiM_reqFifo_enqueueing_whas =
wsiM_reqFifo_cntr_r != 2'd2 && isFull ;
assign wsiM_reqFifo_dequeueing_whas = WILL_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw_whas = wsiM0_SThreadBusy ;
assign wsi_Es_mReqLast_w_whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w_whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w_whas = 1'd1 ;
assign wsiS_extStatusW_wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign wsiM_extStatusW_wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
// register isFull
assign isFull_D_IN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
MUX_isFull_write_1__VAL_1 ;
assign isFull_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ||
wsiM_reqFifo_enqueueing_whas ;
// register isLast
assign isLast_D_IN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
wsiS_reqFifo_D_OUT[57] ;
assign isLast_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ||
wsiM_reqFifo_enqueueing_whas ;
// register pos
assign pos_D_IN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ?
MUX_pos_write_1__VAL_1 :
3'd0 ;
assign pos_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ||
wsiM_reqFifo_enqueueing_whas ;
// register stage_0
assign stage_0_D_IN = wsiS_reqFifo_D_OUT ;
assign stage_0_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 && pos == 3'd0 ;
// register stage_1
assign stage_1_D_IN = wsiS_reqFifo_D_OUT ;
assign stage_1_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 && pos == 3'd1 ;
// register stage_2
assign stage_2_D_IN = wsiS_reqFifo_D_OUT ;
assign stage_2_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 && pos == 3'd2 ;
// register stage_3
assign stage_3_D_IN = wsiS_reqFifo_D_OUT ;
assign stage_3_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 && pos == 3'd3 ;
// register stage_4
assign stage_4_D_IN = wsiS_reqFifo_D_OUT ;
assign stage_4_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 && pos == 3'd4 ;
// register stage_5
assign stage_5_D_IN = wsiS_reqFifo_D_OUT ;
assign stage_5_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 && pos == 3'd5 ;
// register stage_6
assign stage_6_D_IN = wsiS_reqFifo_D_OUT ;
assign stage_6_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 && pos == 3'd6 ;
// register stage_7
assign stage_7_D_IN = wsiS_reqFifo_D_OUT ;
assign stage_7_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 && pos == 3'd7 ;
// register wsiM_burstKind
assign wsiM_burstKind_D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[308] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[312:310] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[309]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky_D_IN = 1'b0 ;
assign wsiM_errorSticky_EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount_D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[312:310] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[309] ;
// register wsiM_isReset_isInReset
assign wsiM_isReset_isInReset_D_IN = 1'd0 ;
assign wsiM_isReset_isInReset_EN = wsiM_isReset_isInReset ;
// register wsiM_operateD
assign wsiM_operateD_D_IN = 1'b1 ;
assign wsiM_operateD_EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount_D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[312:310] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[309] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady_D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady_EN = 1'd1 ;
// register wsiM_reqFifo_cntr_r
assign wsiM_reqFifo_cntr_r_D_IN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ?
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 :
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ;
assign wsiM_reqFifo_cntr_r_EN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr ;
// register wsiM_reqFifo_q_0
always@(MUX_wsiM_reqFifo_q_0_write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_1 or
MUX_wsiM_reqFifo_q_0_write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_0_write_1__SEL_1:
wsiM_reqFifo_q_0_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_1;
MUX_wsiM_reqFifo_q_0_write_1__SEL_2:
wsiM_reqFifo_q_0_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0_D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0_D_IN =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0_EN =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo3 ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr &&
wsiM_reqFifo_cntr_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(MUX_wsiM_reqFifo_q_1_write_1__SEL_1 or
MUX_wsiM_reqFifo_q_1_write_1__VAL_1 or
MUX_wsiM_reqFifo_q_1_write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_1_write_1__SEL_1:
wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_1;
MUX_wsiM_reqFifo_q_1_write_1__SEL_2:
wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1_D_IN =
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
default: wsiM_reqFifo_q_1_D_IN =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1_EN =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo1 ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr &&
wsiM_reqFifo_cntr_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d_D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d_EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR_D_IN =
{ wsiM_isReset_isInReset,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR_EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount_D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount_EN =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky_D_IN = 1'd1 ;
assign wsiM_trafficSticky_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[312:310] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind_D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq_wget[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq_wget[57]) ;
// register wsiS_errorSticky
assign wsiS_errorSticky_D_IN = 1'b0 ;
assign wsiS_errorSticky_EN = 1'b0 ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount_D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq_wget[57] ;
// register wsiS_isReset_isInReset
assign wsiS_isReset_isInReset_D_IN = 1'd0 ;
assign wsiS_isReset_isInReset_EN = wsiS_isReset_isInReset ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength_D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq_wget[57] ;
// register wsiS_operateD
assign wsiS_operateD_D_IN = 1'b1 ;
assign wsiS_operateD_EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount_D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq_wget[57] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady_D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady_EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg_D_IN =
WILL_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq !=
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid_D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ||
WILL_FIRE_RL_wsiS_reqFifo_enq ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR_D_IN =
{ wsiS_isReset_isInReset,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR_EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount_D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount_EN =
wsiS_operateD && wsiS_peerIsReady &&
(!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget) ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky_D_IN = 1'd1 ;
assign wsiS_trafficSticky_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wsiS_wordCount
assign wsiS_wordCount_D_IN =
wsiS_wsiReq_wget[57] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo_D_IN = wsiS_wsiReq_wget ;
assign wsiS_reqFifo_ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_DEQ = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_CLR = 1'b0 ;
// remaining internal signals
assign _dfoo1 =
wsiM_reqFifo_cntr_r != 2'd2 ||
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ;
assign _dfoo3 =
wsiM_reqFifo_cntr_r != 2'd1 ||
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ;
assign be__h8502 = { 28'd0, stage_0[11:8] } ;
assign be__h8521 = { 24'd0, x__h8525 } ;
assign be__h8562 = { 20'd0, x__h8566 } ;
assign be__h8618 = { 16'd0, x__h8622 } ;
assign be__h8689 = { 12'd0, x__h8693 } ;
assign be__h8775 = { 8'd0, x__h8779 } ;
assign be__h8876 = { 4'd0, x__h8880 } ;
assign be__h8992 = { stage_7[11:8], x__h8880 } ;
assign x__h8525 = { stage_1[11:8], stage_0[11:8] } ;
assign x__h8566 = { stage_2[11:8], x__h8525 } ;
assign x__h8622 = { stage_3[11:8], x__h8566 } ;
assign x__h8693 = { stage_4[11:8], x__h8622 } ;
assign x__h8779 = { stage_5[11:8], x__h8693 } ;
assign x__h8880 = { stage_6[11:8], x__h8779 } ;
assign x_burstLength__h6987 = stage_0[55:44] >> 3 ;
assign x_data__h6988 =
{ stage_7[43:12],
stage_6[43:12],
stage_5[43:12],
stage_4[43:12],
stage_3[43:12],
stage_2[43:12],
stage_1[43:12],
stage_0[43:12] } ;
always@(pos or
stage_7 or
stage_6 or
stage_5 or
stage_4 or
stage_3 or
stage_2 or
stage_1 or
stage_0 or
be__h8502 or
be__h8521 or
be__h8562 or
be__h8618 or be__h8689 or be__h8775 or be__h8876 or be__h8992)
begin
case (pos)
3'd0: x_byteEn__h6989 = be__h8502;
3'd1: x_byteEn__h6989 = be__h8521;
3'd2: x_byteEn__h6989 = be__h8562;
3'd3: x_byteEn__h6989 = be__h8618;
3'd4: x_byteEn__h6989 = be__h8689;
3'd5: x_byteEn__h6989 = be__h8775;
3'd6: x_byteEn__h6989 = be__h8876;
3'd7: x_byteEn__h6989 = be__h8992;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
isFull <= `BSV_ASSIGNMENT_DELAY 1'd0;
isLast <= `BSV_ASSIGNMENT_DELAY 1'd0;
pos <= `BSV_ASSIGNMENT_DELAY 3'd0;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (isFull_EN) isFull <= `BSV_ASSIGNMENT_DELAY isFull_D_IN;
if (isLast_EN) isLast <= `BSV_ASSIGNMENT_DELAY isLast_D_IN;
if (pos_EN) pos <= `BSV_ASSIGNMENT_DELAY pos_D_IN;
if (wsiM_burstKind_EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind_D_IN;
if (wsiM_errorSticky_EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky_D_IN;
if (wsiM_iMesgCount_EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount_D_IN;
if (wsiM_operateD_EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD_D_IN;
if (wsiM_pMesgCount_EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount_D_IN;
if (wsiM_peerIsReady_EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady_D_IN;
if (wsiM_reqFifo_cntr_r_EN)
wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY
wsiM_reqFifo_cntr_r_D_IN;
if (wsiM_reqFifo_q_0_EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0_D_IN;
if (wsiM_reqFifo_q_1_EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1_D_IN;
if (wsiM_sThreadBusy_d_EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d_D_IN;
if (wsiM_tBusyCount_EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount_D_IN;
if (wsiM_trafficSticky_EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky_D_IN;
if (wsiS_burstKind_EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind_D_IN;
if (wsiS_errorSticky_EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky_D_IN;
if (wsiS_iMesgCount_EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount_D_IN;
if (wsiS_operateD_EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD_D_IN;
if (wsiS_pMesgCount_EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount_D_IN;
if (wsiS_peerIsReady_EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady_D_IN;
if (wsiS_reqFifo_countReg_EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg_D_IN;
if (wsiS_reqFifo_levelsValid_EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid_D_IN;
if (wsiS_tBusyCount_EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount_D_IN;
if (wsiS_trafficSticky_EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky_D_IN;
if (wsiS_wordCount_EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount_D_IN;
end
if (stage_0_EN) stage_0 <= `BSV_ASSIGNMENT_DELAY stage_0_D_IN;
if (stage_1_EN) stage_1 <= `BSV_ASSIGNMENT_DELAY stage_1_D_IN;
if (stage_2_EN) stage_2 <= `BSV_ASSIGNMENT_DELAY stage_2_D_IN;
if (stage_3_EN) stage_3 <= `BSV_ASSIGNMENT_DELAY stage_3_D_IN;
if (stage_4_EN) stage_4 <= `BSV_ASSIGNMENT_DELAY stage_4_D_IN;
if (stage_5_EN) stage_5 <= `BSV_ASSIGNMENT_DELAY stage_5_D_IN;
if (stage_6_EN) stage_6 <= `BSV_ASSIGNMENT_DELAY stage_6_D_IN;
if (stage_7_EN) stage_7 <= `BSV_ASSIGNMENT_DELAY stage_7_D_IN;
if (wsiM_statusR_EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR_D_IN;
if (wsiS_mesgWordLength_EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength_D_IN;
if (wsiS_statusR_EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR_D_IN;
end
always@(posedge CLK or `BSV_RESET_EDGE RST_N)
if (RST_N == `BSV_RESET_VALUE)
begin
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wsiM_isReset_isInReset_EN)
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiM_isReset_isInReset_D_IN;
if (wsiS_isReset_isInReset_EN)
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiS_isReset_isInReset_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
isFull = 1'h0;
isLast = 1'h0;
pos = 3'h2;
stage_0 = 61'h0AAAAAAAAAAAAAAA;
stage_1 = 61'h0AAAAAAAAAAAAAAA;
stage_2 = 61'h0AAAAAAAAAAAAAAA;
stage_3 = 61'h0AAAAAAAAAAAAAAA;
stage_4 = 61'h0AAAAAAAAAAAAAAA;
stage_5 = 61'h0AAAAAAAAAAAAAAA;
stage_6 = 61'h0AAAAAAAAAAAAAAA;
stage_7 = 61'h0AAAAAAAAAAAAAAA;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_isReset_isInReset = 1'h0;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_cntr_r = 2'h2;
wsiM_reqFifo_q_0 =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_isReset_isInReset = 1'h0;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkWsiAdapter4B32B
|
`include "DC_define.v"
`include "logfunc.h"
`include "scmemc.vh"
module DC_1_tagcheck #(parameter Width = 15, Size =256, Forward=0, REQ_BITS=7)
//tag 10+counter 2+states 3 =15//29 bits virtual adress
(
input clk
,input reset
,input req_valid
,input write
,input ack_retry
,input [14:0] req_tag
,input[4:0] index
//Search Only for 10 bit tags
,output ack_valid
,output req_retry_to_1_tagcheck
,output [14:0] ack_data_to_1_tagcheck
//****************************************,output [2:0] ack_req_to_L2 //3 bit ack req to L2
,output miss
,output hit
,output[2:0] way
,input coretodc_ld_valid
,output coretodc_ld_retry
,input [4:0] coretodc_ld_req
//---------------------------
// 7 bit store Req,atomic,checkpoint
,input coretodc_std_valid
,output coretodc_std_retry
,input [6:0] coretodc_std
//3 bit DC->L2 Req
,output l1tol2_req_valid
,input l1tol2_req_retry
,output [2:0] l1tol2_req
//5 bit L2 -> DC ACK
,input l2tol1_snack_valid
,input [4:0] l2tol1_snack
// 3 bit Displacement
,output l1tol2_disp_valid
,output [2:0] l1tol2_disp //command out displacement
);
logic[2:0] state_line;
logic [7:0] req_pos,req_pos_in_tag;
reg [1:0] counter,counter_;
//,counter_RRIP;
logic [9:0] req_tag_search;
logic [4:0] set_index;
logic write_1_tagcheck;
logic [14:0] req_data_1_tagbank=req_tag;//req tag = 10 bit tag
assign set_index=index;
assign counter=req_tag[11:10];
assign req_tag_search=req_tag[9:0];
assign req_pos = (set_index*8);
assign write_1_tagcheck=write;
always@(req_tag_search)
begin// all works at time=0 counter-- for RRIP
write_1_tagcheck=1'b1;
counter_=counter-1'b1;
req_data_1_tagbank[11:10]=counter_;
end
DC_1_tagbank
#(.Width(Width), .Size(Size))
tagbank (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.write_1_tagbank (write_1_tagcheck)//we=0 for read
,.req_data (req_data_1_tagbank)
,.ack_retry (ack_retry)
,.req_pos_tag (req_pos_in_tag )//search the set index position
,.req_retry (req_retry_to_1_tagcheck)
,.ack_valid (ack_valid)
,.ack_data (ack_data_to_1_tagcheck)
,.coretodc_ld_valid (coretodc_ld_valid)
,.coretodc_ld_retry (coretodc_ld_retry)
,.coretodc_ld_req (coretodc_ld_req)
,.coretodc_std_valid (coretodc_std_valid)
,.coretodc_std_retry (coretodc_std_retry)
,.coretodc_std (coretodc_std)
,.l2tol1_snack_valid (l2tol1_snack_valid)
,.l2tol1_snack (l2tol1_snack)
,.l1tol2_disp_valid (l1tol2_disp_valid)
,.l1tol2_disp (l1tol2_disp)
,.state_cache(state_line)
);
logic [2:0] way_no;
logic [7:0] way_no_ext;//8 bits needed
//logic NO_TAG_PRESENT=0;
assign hit=1'b0;
assign miss=1'b1;//miss is auto select but if hit then miss=0
always @ (posedge clk) begin
if(reset) begin
way_no <= 0;
end else begin
if(way_no <= 7) begin
way_no <= way_no + 1;
end else begin
way_no <= 0;
end
end
end
assign way_no_ext={{5{1'b0}},way_no};
assign req_pos_in_tag = (req_pos+way_no_ext);
always_comb begin
if (ack_data_to_1_tagcheck[9:0]== req_tag_search) begin
if(state_line!=`I) begin//what happens if cacheline is hit but in I state?
hit=1'b1;
miss=1'b0;
end
way = way_no;
end else begin//if (ack_data_to_1_tagcheck[9:0]!= req_tag_search)
hit=1'b0;
miss=1'b1;
end
end
/*
always@(req_tag_search or set_index) begin
//if(tag_sel_a_b)begin
for(way_no=0;way_no<=7;way_no++) begin
way_no_ext={{5{1'b0}},way_no};
req_pos_in_tag = (req_pos+way_no_ext);
if (ack_data_to_1_tagcheck[9:0]== req_tag_search) begin
way=way_no;
if(state_line!=`I) begin//what happens if cacheline is hit but in I state?
hit=1'b1;
miss=1'b0;
end
end // req_tag_search
else begin//if (ack_data_to_1_tagcheck[9:0]!= req_tag_search)
hit=1'b0;
miss=1'b1;
end
end//for
end//always
*/
always_comb
begin
if (miss|l1tol2_req_retry)
begin
if(coretodc_ld_valid) begin l1tol2_req_valid=1;l1tol2_req=`SC_CMD_REQ_S; end
else if(coretodc_std_valid) begin l1tol2_req_valid=1;l1tol2_req=`SC_CMD_REQ_M; end
end//if miss
end//always_comb
/*
always_comb begin
if (l2tol1_snack_valid) begin
if((l2tol1_snack==`SC_SCMD_ACK_S)||(l2tol1_snack==`SC_SCMD_ACK_M)||(l2tol1_snack==`SC_SCMD_ACK_S)) begin
for(way_no=0;way_no<=7;way_no++) begin
way_no_ext={{5{1'b0}},way_no};
req_pos_in_tag = (req_pos+way_no_ext);
if (ack_data_to_1_tagcheck[9:0]== req_tag_search) begin //data comming from ram : ack_data_to_1_tagcheck
way=way_no;
if(state_line==`I) begin//what happens if cacheline in I state?
req_data_1_tagbank=req_tag;
write_1_tagcheck=1;//write enable to ram the req data in this tag way
end
end//]== req_tag_search
NO_TAG_PRESENT=1;
end //for
end
end
end*/
//if(state_line!=I) //no cache tag present
/*
always_comb begin
if (l2tol1_snack_valid && NO_TAG_PRESENT) begin
if((l2tol1_snack==`SC_SCMD_ACK_S)||(l2tol1_snack==`SC_SCMD_ACK_M)||(l2tol1_snack==`SC_SCMD_ACK_S))begin
for(way_no=0;way_no<=7;way_no++) begin
way_no_ext={{5{1'b0}},way_no};
req_pos_in_tag = (req_pos+way_no_ext);
if(ack_data_to_1_tagcheck[11:10]==3)begin
req_data_1_tagbank=req_tag;
write_1_tagcheck=1;//write enable to ram the req data in this tag way
end
else begin
counter_RRIP=counter+1;
//req_data_1_tagbank[=ack_data_to_1_tagcheck;// increase the RRIP counters
req_data_1_tagbank[11:10]=counter_RRIP;
write_1_tagcheck=1;
end
end//for
end //if (l2tol1_snack==`SC_SCMD_ACK_S)
end//if valid
end//always_comb
//end//sel
*/
endmodule
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* DHRYSTONE FOR MCU */
/*---------------------------------------------------------------------------*/
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
`define NO_TIMEOUT
time mclk_start_time, mclk_end_time;
real mclk_period, mclk_frequency;
time dhry_start_time, dhry_end_time;
real dhry_per_sec, dhry_mips, dhry_mips_per_mhz;
integer Number_Of_Runs;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
// Disable automatic DMA verification
#10;
dma_verif_on = 0;
repeat(5) @(posedge mclk);
stimulus_done = 0;
//---------------------------------------
// Check CPU configuration
//---------------------------------------
if ((`PMEM_SIZE !== 49152) || (`DMEM_SIZE !== 10240))
begin
$display(" ===============================================");
$display("| SIMULATION ERROR |");
$display("| |");
$display("| Core must be configured for: |");
$display("| - 48kB program memory |");
$display("| - 10kB data memory |");
$display(" ===============================================");
$finish;
end
// Disable watchdog
// (only required because RedHat/TI GCC toolchain doesn't disable watchdog properly at startup)
`ifdef WATCHDOG
force dut.watchdog_0.wdtcnt = 16'h0000;
`endif
//---------------------------------------
// Number of benchmark iteration
// (Must match the C-code value)
//---------------------------------------
Number_Of_Runs = 100;
//---------------------------------------
// Measure clock period
//---------------------------------------
repeat(100) @(posedge mclk);
$timeformat(-9, 3, " ns", 10);
@(posedge mclk);
mclk_start_time = $time;
@(posedge mclk);
mclk_end_time = $time;
@(posedge mclk);
mclk_period = mclk_end_time-mclk_start_time;
mclk_frequency = 1000/mclk_period;
$display("\nINFO-VERILOG: openMSP430 System clock frequency %f MHz\n", mclk_frequency);
//---------------------------------------
// Measure Dhrystone run time
//---------------------------------------
// Detect beginning of run
@(posedge p3_dout[0]);
dhry_start_time = $time;
$timeformat(-3, 3, " ms", 10);
$display("\nINFO-VERILOG: Dhrystone loop started at %t ", dhry_start_time);
$display("");
$display("INFO-VERILOG: Be patient... there could be up to 13ms to simulate");
$display("");
// Detect end of run
@(negedge p3_dout[0]);
dhry_end_time = $time;
$timeformat(-3, 3, " ms", 10);
$display("INFO-VERILOG: Dhrystone loop ended at %t ", dhry_end_time);
// Compute results
$timeformat(-9, 3, " ns", 10);
dhry_per_sec = (Number_Of_Runs*1000000000)/(dhry_end_time - dhry_start_time);
dhry_mips = dhry_per_sec / 1757;
dhry_mips_per_mhz = dhry_mips / mclk_frequency;
// Report results
$display("\INFO-VERILOG: Dhrystone per second : %f", dhry_per_sec);
$display("\INFO-VERILOG: DMIPS : %f", dhry_mips);
$display("\INFO-VERILOG: DMIPS/MHz : %f\n", dhry_mips_per_mhz);
//---------------------------------------
// Wait for the end of C-code execution
//---------------------------------------
@(posedge p4_dout[0]);
stimulus_done = 1;
$display(" ===============================================");
$display("| SIMULATION DONE |");
$display("| (stopped through verilog stimulus) |");
$display(" ===============================================");
$finish;
end
// Display stuff from the C-program
always @(p2_dout[0])
begin
$write("%s", p1_dout);
$fflush();
end
// Display some info to show simulation progress
initial
begin
@(posedge p3_dout[0]);
#1000000;
while (p3_dout[0])
begin
$display("INFO-VERILOG: Simulated time %t ", $time);
#1000000;
end
end
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// counters
int cnt;
int cnt_bit ;
int cnt_byte;
int cnt_int ;
int cnt_ar1d;
int cnt_ar2d;
// sizes
int siz_bit ;
int siz_byte;
int siz_int ;
int siz_ar1d;
int siz_ar2d;
// add all counters
assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d;
// finish report
always @ (posedge clk)
if (cnt == 5) begin
if (siz_bit != 1) $stop();
if (siz_byte != 8) $stop();
if (siz_int != 32) $stop();
if (siz_ar1d != 24) $stop();
if (siz_ar2d != 16) $stop();
end else if (cnt > 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
// instances with various types
mod_typ #(.TYP (bit )) mod_bit (clk, cnt_bit [ 1-1:0], siz_bit );
mod_typ #(.TYP (byte )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte);
mod_typ #(.TYP (int )) mod_int (clk, cnt_int [32-1:0], siz_int );
mod_typ #(.TYP (bit [23:0] )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d);
mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d);
endmodule : t
module mod_typ #(
parameter type TYP = byte
)(
input logic clk,
output TYP cnt = 0,
output int siz
);
always @ (posedge clk)
cnt <= cnt + 1;
assign siz = $bits (cnt);
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(*i $Id: NStrongRec.v 13323 2010-07-24 15:57:30Z herbelin $ i*)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Module NStrongRecPropFunct (Import N : NAxiomsSig').
Include NSubPropFunct N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows to define a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
(** We need a result similar to [f_equal], but for setoid equalities. *)
Lemma f_equiv : forall f g x y,
(N.eq==>Aeq)%signature f g -> N.eq x y -> Aeq (f x) (g y).
Proof.
auto.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0.
repeat red; intros.
apply f_equiv; auto.
apply recursion_wd; try red; auto.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt.
apply strong_rec0_wd; auto.
now rewrite Enn'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
apply f_equiv; auto with *.
rewrite recursion_succ; try (repeat red; auto with *; fail).
apply f_wd.
apply recursion_wd; try red; auto with *.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ.
apply f_wd; auto with *.
red; intros; rewrite strong_rec0_0; auto with *.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
apply f_wd; auto with *.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Implicit Arguments strong_rec [A].
End NStrongRecPropFunct.
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_brams_v6.v
// Version : 2.3
//--
//-- Description: BlockRAM module for Virtex6 PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_brams_v6
#(
// the number of BRAMs to use
// supported values are:
// 1,2,4,8,18
parameter NUM_BRAMS = 0,
// BRAM read address latency
//
// value meaning
// ====================================================
// 0 BRAM read address port sample
// 1 BRAM read address port sample and a pipeline stage on the address port
parameter RAM_RADDR_LATENCY = 1,
// BRAM read data latency
//
// value meaning
// ====================================================
// 1 no BRAM OREG
// 2 use BRAM OREG
// 3 use BRAM OREG and a pipeline stage on the data port
parameter RAM_RDATA_LATENCY = 1,
// BRAM write latency
// The BRAM write port is synchronous
//
// value meaning
// ====================================================
// 0 BRAM write port sample
// 1 BRAM write port sample plus pipeline stage
parameter RAM_WRITE_LATENCY = 1,
parameter TCQ = 1
)
(
input user_clk_i,
input reset_i,
input wen,
input [12:0] waddr,
input [71:0] wdata,
input ren,
input rce,
input [12:0] raddr,
output [71:0] rdata
);
// turn on the bram output register
localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;
// calculate the data width of the individual brams
localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 72 :
(NUM_BRAMS == 2) ? 36 :
(NUM_BRAMS == 4) ? 18 :
(NUM_BRAMS == 8) ? 9 :
4
);
//synthesis translate_off
initial begin
$display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d",
$time, NUM_BRAMS, DOB_REG, WIDTH, RAM_WRITE_LATENCY, RAM_RADDR_LATENCY, RAM_RDATA_LATENCY);
case (NUM_BRAMS)
1,2,4,8,18:;
default:
begin
$display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS);
$finish;
end
endcase // case(NUM_BRAMS)
case (RAM_RADDR_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY);
$finish;
end
endcase // case (RAM_RADDR_LATENCY)
case (RAM_RDATA_LATENCY)
1,2,3:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY);
$finish;
end
endcase // case (RAM_RDATA_LATENCY)
case (RAM_WRITE_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY);
$finish;
end
endcase // case(RAM_WRITE_LATENCY)
end
//synthesis translate_on
// model the delays for ram write latency
wire wen_int;
wire [12:0] waddr_int;
wire [71:0] wdata_int;
generate if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2
reg wen_dly;
reg [12:0] waddr_dly;
reg [71:0] wdata_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
wen_dly <= #TCQ 1'b0;
waddr_dly <= #TCQ 13'b0;
wdata_dly <= #TCQ 72'b0;
end else begin
wen_dly <= #TCQ wen;
waddr_dly <= #TCQ waddr;
wdata_dly <= #TCQ wdata;
end
end
assign wen_int = wen_dly;
assign waddr_int = waddr_dly;
assign wdata_int = wdata_dly;
end // if (RAM_WRITE_LATENCY == 1)
else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1
assign wen_int = wen;
assign waddr_int = waddr;
assign wdata_int = wdata;
end
endgenerate
// model the delays for ram read latency
wire ren_int;
wire [12:0] raddr_int;
wire [71:0] rdata_int;
generate if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2
reg ren_dly;
reg [12:0] raddr_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
ren_dly <= #TCQ 1'b0;
raddr_dly <= #TCQ 13'b0;
end else begin
ren_dly <= #TCQ ren;
raddr_dly <= #TCQ raddr;
end // else: !if(reset_i)
end
assign ren_int = ren_dly;
assign raddr_int = raddr_dly;
end // block: rd_lat_addr_2
else begin : raddr_lat_1
assign ren_int = ren;
assign raddr_int = raddr;
end
endgenerate
generate if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3
reg [71:0] rdata_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
rdata_dly <= #TCQ 72'b0;
end else begin
rdata_dly <= #TCQ rdata_int;
end // else: !if(reset_i)
end
assign rdata = rdata_dly;
end // block: rd_lat_data_3
else begin : rdata_lat_1_2
assign #TCQ rdata = rdata_int;
end
endgenerate
// instantiate the brams
generate
genvar i;
for (i = 0; i < NUM_BRAMS; i = i + 1) begin : brams
pcie_bram_v6 #(.DOB_REG(DOB_REG), .WIDTH(WIDTH))
ram (.user_clk_i(user_clk_i), .reset_i(reset_i),
.wen_i(wen_int), .waddr_i(waddr_int), .wdata_i(wdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]),
.ren_i(ren_int), .raddr_i(raddr_int), .rdata_o(rdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]), .rce_i(rce));
end
endgenerate
endmodule // pcie_brams_v6
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O32AI_TB_V
`define SKY130_FD_SC_HDLL__O32AI_TB_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o32ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hdll__o32ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O32AI_TB_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
function integer get_baz(input integer bar);
get_baz = bar;
$fatal(2, "boom");
endfunction
module foo #(parameter BAR = 0);
localparam integer BAZ = get_baz(BAR);
endmodule
module foo2 #(parameter QUX = 0);
genvar x;
generate
for (x = 0; x < 2; x++) begin: foo2_loop
foo #(.BAR (QUX + x)) foo_in_foo2_inst();
end
endgenerate
endmodule
module t;
genvar i, j;
generate
for (i = 0; i < 2; i++) begin: genloop
foo #(.BAR (i)) foo_inst();
end
for (i = 2; i < 4; i++) begin: gen_l1
for (j = 0; j < 2; j++) begin: gen_l2
foo #(.BAR (i + j*2)) foo_inst2();
end
end
if (1 == 1) begin: cond_true
foo #(.BAR (6)) foo_inst3();
end
if (1 == 1) begin // unnamed
foo #(.BAR (7)) foo_inst4();
end
for (i = 8; i < 12; i = i + 2) begin: nested_loop
foo2 #(.QUX (i)) foo2_inst();
end
endgenerate
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ns / 1ps
module mmc3_top(
// FX 3 interface
input wire fx3_pclk_100MHz,
(* IOB = "FORCE" *) input wire fx3_wr, // force IOB register
(* IOB = "FORCE" *) input wire fx3_cs, // async. signal
(* IOB = "FORCE" *) input wire fx3_oe, // async. signal
input wire fx3_rst, // async. signal from FX3, active high
(* IOB = "FORCE" *) output wire fx3_ack, // force IOB register
(* IOB = "FORCE" *) output wire fx3_rdy, // force IOB register
output wire reset_fx3,
inout wire [31:0] fx3_bus, // 32 bit databus
// 200 MHz oscillator
input wire sys_clk_p,
input wire sys_clk_n,
// 100 Mhz oscillator
input wire Clk100,
// GPIO
output wire [8:1] led,
output wire [3:0] PWR_EN,
(* IOB = "FORCE" *) output wire fx3_rd_finish,
input wire Reset_button2,// async. signal
input wire FLAG1, // was DMA Flag; currently connected to TEST signal from FX3
(* IOB = "FORCE" *) input wire FLAG2, // DMA watermark flag for thread 2 of FX3
// Power supply regulators EN signals
output wire EN_VD1,
output wire EN_VD2,
output wire EN_VA1,
output wire EN_VA2,
// Command sequencer signals
output wire CMD_CLK_OUT,
(* IOB = "FORCE" *) output wire CMD_DATA,
// FE-I4_rx signals
(* IOB = "FORCE" *) input wire DOBOUT
);
assign reset_fx3 = 1; // not to reset fx3 while loading fpga
assign EN_VD1 = 1;
assign EN_VD2 = 1;
assign EN_VA1 = 1;
assign EN_VA2 = 1;
wire [31:0] BUS_ADD;
wire [31:0] BUS_DATA;
wire BUS_RD, BUS_WR, BUS_RST, BUS_CLK;
//assign BUS_RST = (BUS_RST | (!LOCKED));
wire BUS_BYTE_ACCESS;
assign BUS_BYTE_ACCESS = (BUS_ADD < 32'h8000_0000) ? 1'b1 : 1'b0;
wire PLL_RST;
assign PLL_RST = ((fx3_rst)|(!LOCKED));
FX3_IF FX3_IF_inst (
.fx3_bus(fx3_bus),
.fx3_wr(fx3_wr),
.fx3_oe(fx3_oe),
.fx3_cs(fx3_cs),
.fx3_clk(fx3_pclk_100MHz),
.fx3_rdy(fx3_rdy),
.fx3_ack(fx3_ack),
.fx3_rd_finish(fx3_rd_finish),
.fx3_rst(PLL_RST), // PLL is reset first
// .fx3_rst(fx3_rst), // Comment before synthesis and uncomment previous line
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_BYTE_ACCESS(BUS_BYTE_ACCESS),
.FLAG1(FLAG1),
.FLAG2(FLAG2)
);
wire clk40mhz_pll, clk320mhz_pll, clk160mhz_pll, clk16mhz_pll;
wire pll_feedback, LOCKED;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(64), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(10.000), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKOUT0_DIVIDE(32), // Divide amount for CLKOUT0 (1-128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT1_DIVIDE(4), // Divide amount for CLKOUT0 (1-128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT2_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT3_DIVIDE(80), // Divide amount for CLKOUT0 (1-128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT3_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.DIVCLK_DIVIDE(5), // Master division value, (1-56)
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) PLLE2_BASE_inst (
// Generated 40 MHz clock
.CLKOUT0(clk40mhz_pll),
.CLKOUT1(clk320mhz_pll),
.CLKOUT2(clk160mhz_pll),
.CLKOUT3(clk16mhz_pll),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(pll_feedback),
.LOCKED(LOCKED), // 1-bit output: LOCK
// Input 100 MHz clock
.CLKIN1(BUS_CLK),
// Control Ports
.PWRDWN(0),
.RST(fx3_rst), // Button is active low
// Feedback
.CLKFBIN(pll_feedback)
);
wire clk40mhz, clk320mhz, clk160mhz, clk16mhz;
BUFG BUFG_inst_40 (
.O(clk40mhz), // Clock buffer output
.I(clk40mhz_pll) // Clock buffer input
);
BUFG BUFG_inst_320 (
.O(clk320mhz), // Clock buffer output
.I(clk320mhz_pll) // Clock buffer input
);
BUFG BUFG_inst_160 (
.O(clk160mhz), // Clock buffer output
.I(clk160mhz_pll) // Clock buffer input
);
BUFG BUFG_inst_16 (
.O(clk16mhz), // Clock buffer output
.I(clk16mhz_pll) // Clock buffer input
);
// ------- MODULE ADREESSES ------- //
localparam CMD_BASEADDR = 32'h0000;
localparam CMD_HIGHADDR = 32'h1000-1;
localparam GPIO1_BASEADDR = 32'h1000;
localparam GPIO1_HIGHADDR = 32'h1003;
localparam GPIO2_BASEADDR = 32'h1004;
localparam GPIO2_HIGHADDR = 32'h1007;
localparam FIFO_BASEADDR = 32'h8100;
localparam FIFO_HIGHADDR = 32'h8200-1;
localparam RX4_BASEADDR = 32'h8300;
localparam RX4_HIGHADDR = 32'h8400-1;
localparam RX3_BASEADDR = 32'h8400;
localparam RX3_HIGHADDR = 32'h8500-1;
localparam RX2_BASEADDR = 32'h8500;
localparam RX2_HIGHADDR = 32'h8600-1;
localparam RX1_BASEADDR = 32'h8600;
localparam RX1_HIGHADDR = 32'h8700-1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
wire CMD_EXT_START_FLAG;
assign CMD_EXT_START_FLAG = 0;
gpio #(
.BASEADDR(GPIO1_BASEADDR),
.HIGHADDR(GPIO1_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff),
.IO_TRI(0)
) gpio1 (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(led)
);
gpio #(
.BASEADDR(GPIO2_BASEADDR),
.HIGHADDR(GPIO2_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff),
.IO_TRI(0)
) gpio2 (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(PWR_EN[3:0])
);
cmd_seq #(
.BASEADDR(CMD_BASEADDR),
.HIGHADDR(CMD_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) icmd (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CMD_CLK_OUT(CMD_CLK_OUT),
.CMD_CLK_IN(clk40mhz),
.CMD_EXT_START_FLAG(CMD_EXT_START_FLAG),
.CMD_EXT_START_ENABLE(),
.CMD_DATA(CMD_DATA),
.CMD_READY(),
.CMD_START_FLAG()
);
parameter DSIZE = 10;
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
//assign FIFO_READ = 0;
genvar i;
generate
for (i = 3; i < 4; i = i + 1) begin: rx_gen
fei4_rx #(
.BASEADDR(RX1_BASEADDR-32'h0100*i),
.HIGHADDR(RX1_HIGHADDR-32'h0100*i),
.DSIZE(DSIZE),
.DATA_IDENTIFIER(i+1),
.ABUSWIDTH(ABUSWIDTH)
) i_fei4_rx (
.RX_CLK(clk160mhz),
.RX_CLK2X(clk320mhz),
.DATA_CLK(clk16mhz),
.RX_DATA(DOBOUT),
.RX_READY(),
.RX_8B10B_DECODER_ERR(),
.RX_FIFO_OVERFLOW_ERR(),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.RX_FIFO_FULL(),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR)
);
end
endgenerate
wire FIFO_NOT_EMPTY, FIFO_FULL, FIFO_NEAR_FULL, FIFO_READ_ERROR;
bram_fifo #(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(FIFO_NOT_EMPTY),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(FIFO_NEAR_FULL),
.FIFO_READ_ERROR(FIFO_READ_ERROR)
);
//assign led[5] = FIFO_NOT_EMPTY;
//assign led[6] = FIFO_FULL;
//assign led[7] = FIFO_NEAR_FULL;
//assign led[8] = FIFO_READ_ERROR;
/*always @(posedge BUS_CLK)
begin
if (BUS_RST)
begin
led[5] <= 0;
led[6] <= 0;
led[7] <= 0;
led[8] <= 0;
end
else
begin
if (FIFO_NOT_EMPTY)
led[5] <= 1;
else if (FIFO_FULL)
led[6] <= 1;
else if (FIFO_NEAR_FULL)
led[7] <= 1;
else if (FIFO_READ_ERROR)
led[8] <= 1;
end
end*/
/*
gpio
#(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(32),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(led[8:1])
);
*/
/*Register #(
.REG_SIZE(32),
.ADDRESS(1))
Reg1_inst (
.D(DataIn),
.WR(WR),
.RD(RD),
.Addr(Addr),
.CLK(CLK_100MHz),
.Q(Reg1),
.RB(DataOut),
.RDYB(RDYB),
.RD_VALID_N(ACKB),
.RST(RST)
);
Register #(
.REG_SIZE(32),
.ADDRESS(2))
Reg2_inst (
.D(DataIn),
.WR(WR),
.RD(RD),
.Addr(Addr),
.CLK(CLK_100MHz),
.Q(Reg2),
.RB(DataOut),
.RDYB(RDYB),
.RD_VALID_N(ACKB),
.RST(RST)
);
BRAM_Test #(
.ADDRESS( 32'h10_00_00_00),
.MEM_SIZE(32'h00_00_40_00))
BRAM_Test_inst (
.DataIn(DataIn),
.WR(WR),
.RD(RD),
.CLK(CLK_100MHz),
.DataOut(DataOut),
.Addr(Addr[31:0]),
.RDYB(RDYB),
.RD_VALID_N(ACKB),
// .DMA_RDY(DMA_RDY),
.RST(RST)
);
DDR3_256_8 #(
.ADDRESS( 32'h20_00_00_00),
.MEM_SIZE(32'h10_00_00_00))
DDR3_256_8_inst (
.DataIn(DataIn[31:0]),
.WR(WR),
.RD(RD),
.Addr(Addr[31:0]),
.DataOut(DataOut[31:0]),
.RDY_N(RDYB),
.RD_VALID_N(ACKB),
.CLK_OUT(CLK_100MHz),
.RST(RST),
.Reset_button2(Reset_button2),
.INIT_COMPLETE(INIT_COMPLETE),
.ddr3_dq(ddr3_dq),
.ddr3_addr(ddr3_addr),
// .ddr3_dm(ddr3_dm),
.ddr3_dqs_p(ddr3_dqs_p),
.ddr3_dqs_n(ddr3_dqs_n),
.ddr3_ba(ddr3_ba),
.ddr3_ck_p(ddr3_ck_p),
.ddr3_ck_n(ddr3_ck_n),
.ddr3_ras_n(ddr3_ras_n),
.ddr3_cas_n(ddr3_cas_n),
.ddr3_we_n(ddr3_we_n),
.ddr3_reset_n(ddr3_reset_n),
.ddr3_cke(ddr3_cke),
.ddr3_odt(ddr3_odt),
// .ddr3_cs_n(ddr3_cs_n),
.sys_clk_p(sys_clk_p),
.sys_clk_n(sys_clk_n),
.Clk100(Clk100),
.full_fifo(full_fifo),
// .DMA_RDY(DMA_RDY),
.CS_FX3(CS_FX3),
.FLAG2_reg(FLAG2_reg)
);*/
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.06.2015 14:58:39
// Design Name:
// Module Name: harness
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "system.vh"
module harness();
parameter X_LOCAL = 2,
Y_LOCAL = 2,
CYCLE = 100,
Tsetup = 15,
Thold = 5;
// -- Señales de interconexion ----------------------------------- >>>>>
reg clk;
reg reset;
// -- puertos de entradas ------------------------------------ >>>>>
wire credit_out_xpos_dout;
wire [`CHANNEL_WIDTH-1:0] channel_xpos_din;
wire credit_out_ypos_dout;
wire [`CHANNEL_WIDTH-1:0] channel_ypos_din;
wire credit_out_xneg_dout;
wire[`CHANNEL_WIDTH-1:0] channel_xneg_din;
wire credit_out_yneg_dout;
wire [`CHANNEL_WIDTH-1:0] channel_yneg_din;
wire credit_out_pe_dout;
wire [`CHANNEL_WIDTH-1:0] channel_pe_din;
// -- puertos de salida -------------------------------------- >>>>>
wire credit_in_xpos_din;
wire [`CHANNEL_WIDTH-1:0] channel_xpos_dout;
wire credit_in_ypos_din;
wire [`CHANNEL_WIDTH-1:0] channel_ypos_dout;
wire credit_in_xneg_din;
wire [`CHANNEL_WIDTH-1:0] channel_xneg_dout;
wire credit_in_yneg_din;
wire [`CHANNEL_WIDTH-1:0] channel_yneg_dout;
wire credit_in_pe_din;
wire [`CHANNEL_WIDTH-1:0] channel_pe_dout;
// -- DUT -------------------------------------------------------- >>>>>
router
#(
.X_LOCAL(X_LOCAL),
.Y_LOCAL(Y_LOCAL)
)
lancetfish_router
(
.clk (clk),
.reset (reset),
// -- puertos de entrada ------------------------------------- >>>>>
.credit_out_xpos_dout (credit_out_xpos_dout),
.channel_xpos_din (channel_xpos_din),
.credit_out_ypos_dout (credit_out_ypos_dout),
.channel_ypos_din (channel_ypos_din),
.credit_out_xneg_dout (credit_out_xneg_dout),
.channel_xneg_din (channel_xneg_din),
.credit_out_yneg_dout (credit_out_yneg_dout),
.channel_yneg_din (channel_yneg_din),
.credit_out_pe_dout (credit_out_pe_dout), // PE
.channel_pe_din (channel_pe_din),
// -- puertos de salida -------------------------------------- >>>>>
.credit_in_xpos_din (credit_in_xpos_din),
.channel_xpos_dout (channel_xpos_dout),
.credit_in_ypos_din (credit_in_ypos_din),
.channel_ypos_dout (channel_ypos_dout),
.credit_in_xneg_din (credit_in_xneg_din),
.channel_xneg_dout (channel_xneg_dout),
.credit_in_yneg_din (credit_in_yneg_din),
.channel_yneg_dout (channel_yneg_dout),
.credit_in_pe_din (credit_in_pe_din), // PE
.channel_pe_dout (channel_pe_dout)
);
// -- Bus Behaivoral Model --------------------------------------- >>>>>
// -- Canal x+ ----------------------------------------------- >>>>>
source
#(
.Thold(Thold)
)
xpos_in_channel
(
.clk (clk),
.credit_in (credit_out_xpos_dout),
.channel_out(channel_xpos_din)
);
sink
#(
.Thold(Thold)
)
xpos_out_channel
(
.clk (clk),
.channel_in (channel_xpos_dout),
.credit_out (credit_in_xpos_din)
);
// -- Canal y+ ----------------------------------------------- >>>>>
source
#(
.Thold(Thold)
)
ypos_in_channel
(
.clk (clk),
.credit_in (credit_out_ypos_dout),
.channel_out(channel_ypos_din)
);
sink
#(
.Thold(Thold)
)
ypos_out_channel
(
.clk (clk),
.channel_in (channel_ypos_dout),
.credit_out (credit_in_ypos_din)
);
// -- Canal x- ----------------------------------------------- >>>>>
source
#(
.Thold(Thold)
)
xneg_in_channel
(
.clk (clk),
.credit_in (credit_out_xneg_dout),
.channel_out(channel_xneg_din)
);
sink
#(
.Thold(Thold)
)
xneg_out_channel
(
.clk (clk),
.channel_in (channel_xneg_dout),
.credit_out (credit_in_xneg_din)
);
// -- Canal x- ----------------------------------------------- >>>>>
source
#(
.Thold(Thold)
)
yneg_in_channel
(
.clk (clk),
.credit_in (credit_out_yneg_dout),
.channel_out(channel_yneg_din)
);
sink
#(
.Thold(Thold)
)
yneg_out_channel
(
.clk (clk),
.channel_in (channel_yneg_dout),
.credit_out (credit_in_yneg_din)
);
// -- Canal pe ------------------------------------------- >>>>>
source
#(
.Thold(Thold)
)
pe_in_channel
(
.clk (clk),
.credit_in (credit_out_pe_dout),
.channel_out(channel_pe_din)
);
sink
#(
.Thold(Thold)
)
pe_out_channel
(
.clk (clk),
.channel_in (channel_pe_dout),
.credit_out (credit_in_pe_din)
);
// -- Clock Generator -------------------------------------------- >>>>>
always
begin
#(CYCLE/2) clk = 1'b0;
#(CYCLE/2) clk = 1'b1;
end
// -- Sync Reset Generator --------------------------------------- >>>>>
task sync_reset;
begin
reset <= 1'b1;
repeat(4)
begin
@(posedge clk);
#(Thold);
end
reset <= 1'b0;
end
endtask : sync_reset
endmodule
|
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module SoCKitTest(
//////////// CLOCK //////////
OSC_50_B3B,
OSC_50_B4A,
OSC_50_B5B,
OSC_50_B8A,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
RESET_n,
//////////// SW //////////
SW,
//////////// Si5338 //////////
SI5338_SCL,
SI5338_SDA,
//////////// Temperature //////////
TEMP_CS_n,
TEMP_DIN,
TEMP_DOUT,
TEMP_SCLK,
//////////// VGA //////////
VGA_B,
VGA_BLANK_n,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_n,
VGA_VS,
//////////// Audio //////////
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_MUTE,
AUD_XCK,
//////////// I2C for Audio //////////
AUD_I2C_SCLK,
AUD_I2C_SDAT,
//////////// IR Receiver //////////
IRDA_RXD,
//////////// SDRAM //////////
DDR3_A,
DDR3_BA,
DDR3_CAS_n,
DDR3_CK_n,
DDR3_CK_p,
DDR3_CKE,
DDR3_CS_n,
DDR3_DM,
DDR3_DQ,
DDR3_DQS_n,
DDR3_DQS_p,
DDR3_ODT,
DDR3_RAS_n,
DDR3_RESET_n,
DDR3_RZQ,
DDR3_WE_n,
//////////// HSMC, HSMC connect to HTG - HSMC to PIO Adaptor //////////
GPIO0_0,
GPIO0_1,
GPIO0_10,
GPIO0_11,
GPIO0_12,
GPIO0_13,
GPIO0_14,
GPIO0_15,
GPIO0_16,
GPIO0_17,
GPIO0_18,
GPIO0_19,
GPIO0_2,
GPIO0_20,
GPIO0_21,
GPIO0_22,
GPIO0_23,
GPIO0_24,
GPIO0_25,
GPIO0_26,
GPIO0_27,
GPIO0_28,
GPIO0_29,
GPIO0_3,
GPIO0_30,
GPIO0_31,
GPIO0_32,
GPIO0_33,
GPIO0_34,
GPIO0_35,
GPIO0_4,
GPIO0_5,
GPIO0_6,
GPIO0_7,
GPIO0_8,
GPIO0_9,
GPIO1_0,
GPIO1_1,
GPIO1_10,
GPIO1_11,
GPIO1_12,
GPIO1_13,
GPIO1_14,
GPIO1_15,
GPIO1_16,
GPIO1_17,
GPIO1_18,
GPIO1_19,
GPIO1_2,
GPIO1_20,
GPIO1_21,
GPIO1_22,
GPIO1_23,
GPIO1_24,
GPIO1_25,
GPIO1_26,
GPIO1_27,
GPIO1_28,
GPIO1_29,
GPIO1_3,
GPIO1_30,
GPIO1_31,
GPIO1_32,
GPIO1_33,
GPIO1_34,
GPIO1_35,
GPIO1_4,
GPIO1_5,
GPIO1_6,
GPIO1_7,
GPIO1_8,
GPIO1_9
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input OSC_50_B3B;
input OSC_50_B4A;
input OSC_50_B5B;
input OSC_50_B8A;
//////////// LED //////////
output [3:0] LED;
//////////// KEY //////////
input [3:0] KEY;
input RESET_n;
//////////// SW //////////
input [3:0] SW;
//////////// Si5338 //////////
output SI5338_SCL;
inout SI5338_SDA;
//////////// Temperature //////////
output TEMP_CS_n;
output TEMP_DIN;
input TEMP_DOUT;
output TEMP_SCLK;
//////////// VGA //////////
output [7:0] VGA_B;
output VGA_BLANK_n;
output VGA_CLK;
output [7:0] VGA_G;
output VGA_HS;
output [7:0] VGA_R;
output VGA_SYNC_n;
output VGA_VS;
//////////// Audio //////////
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_MUTE;
output AUD_XCK;
//////////// I2C for Audio //////////
output AUD_I2C_SCLK;
inout AUD_I2C_SDAT;
//////////// IR Receiver //////////
input IRDA_RXD;
//////////// SDRAM //////////
output [14:0] DDR3_A;
output [2:0] DDR3_BA;
output DDR3_CAS_n;
output DDR3_CK_n;
output DDR3_CK_p;
output DDR3_CKE;
output DDR3_CS_n;
output [3:0] DDR3_DM;
inout [31:0] DDR3_DQ;
inout [3:0] DDR3_DQS_n;
inout [3:0] DDR3_DQS_p;
output DDR3_ODT;
output DDR3_RAS_n;
output DDR3_RESET_n;
input DDR3_RZQ;
output DDR3_WE_n;
//////////// HSMC, HSMC connect to HTG - HSMC to PIO Adaptor //////////
inout GPIO0_0;
inout GPIO0_1;
inout GPIO0_10;
inout GPIO0_11;
inout GPIO0_12;
inout GPIO0_13;
inout GPIO0_14;
inout GPIO0_15;
inout GPIO0_16;
inout GPIO0_17;
inout GPIO0_18;
inout GPIO0_19;
inout GPIO0_2;
inout GPIO0_20;
inout GPIO0_21;
inout GPIO0_22;
inout GPIO0_23;
inout GPIO0_24;
inout GPIO0_25;
inout GPIO0_26;
inout GPIO0_27;
inout GPIO0_28;
inout GPIO0_29;
inout GPIO0_3;
inout GPIO0_30;
inout GPIO0_31;
inout GPIO0_32;
inout GPIO0_33;
inout GPIO0_34;
inout GPIO0_35;
inout GPIO0_4;
inout GPIO0_5;
inout GPIO0_6;
inout GPIO0_7;
inout GPIO0_8;
inout GPIO0_9;
inout GPIO1_0;
inout GPIO1_1;
inout GPIO1_10;
inout GPIO1_11;
inout GPIO1_12;
inout GPIO1_13;
inout GPIO1_14;
inout GPIO1_15;
inout GPIO1_16;
inout GPIO1_17;
inout GPIO1_18;
inout GPIO1_19;
inout GPIO1_2;
inout GPIO1_20;
inout GPIO1_21;
inout GPIO1_22;
inout GPIO1_23;
inout GPIO1_24;
inout GPIO1_25;
inout GPIO1_26;
inout GPIO1_27;
inout GPIO1_28;
inout GPIO1_29;
inout GPIO1_3;
inout GPIO1_30;
inout GPIO1_31;
inout GPIO1_32;
inout GPIO1_33;
inout GPIO1_34;
inout GPIO1_35;
inout GPIO1_4;
inout GPIO1_5;
inout GPIO1_6;
inout GPIO1_7;
inout GPIO1_8;
inout GPIO1_9;
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_PP_SYMBOL_V
`define SKY130_FD_SC_LP__AND3B_PP_SYMBOL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_PP_SYMBOL_V
|
/*Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module top (clk, reset, start, din, params, dout, ready,iir_start,iir_done);
input clk, reset, start;
input [7:0] din;
input [15:0] params;
output [7:0] dout;
reg [7:0] dout;
output ready;
reg ready;
reg temp_ready;
reg [6:0] finite_counter;
wire count0;
input iir_start;
output iir_done;
wire iir_done;
reg del_count0;
reg [15:0] a1, a2, b0, b1, b2, yk1, yk2;
reg [7:0] uk, uk1, uk2 ;
reg [28:0] ysum ;
reg [26:0] yk ;
reg [22:0] utmp;
reg [3:0] wait_counter ;
// temporary variable
wire [31:0] yo1, yo2;
//wire [23:0] b0t, b1t, b2t;
wire [22:0] b0t, b1t, b2t;
wire [22:0] b0tpaj, b1tpaj, b2tpaj;
reg [3:0] obf_state, obf_next_state ;
reg [7:0] temp_uk, temp_uk1, temp_uk2 ;
reg [15:0] temp_a1, temp_a2, temp_b0, temp_b1, temp_b2, temp_yk1, temp_yk2;
reg [28:0] temp_ysum ;
reg [26:0] temp_yk ;
reg [22:0] temp_utmp;
reg [7:0] temp_dout;
reg [3:0] temp_wait_counter ;
parameter
idle = 4'b0001 ,
load_a2 = 4'b0010 ,
load_b0 = 4'b0011 ,
load_b1 = 4'b0100 ,
load_b2 = 4'b0101 ,
wait4_start = 4'b0110 ,
latch_din = 4'b0111 ,
compute_a = 4'b1000 ,
compute_b = 4'b1001 ,
compute_yk = 4'b1010 ,
wait4_count = 4'b1011 ,
latch_dout = 4'b1100 ;
always @(obf_state or start or din or wait_counter or iir_start or count0)
begin
case (obf_state )
idle :
begin
if (iir_start)
obf_next_state = load_a2 ;
else
obf_next_state = idle;
temp_a1 = params ;
end
load_a2 :
begin
obf_next_state = load_b0 ;
temp_a2 = params ;
end
load_b0 :
begin
obf_next_state = load_b1 ;
temp_b0 = params ;
end
load_b1 :
begin
obf_next_state = load_b2 ;
temp_b1 = params ;
end
load_b2 :
begin
obf_next_state = wait4_start ;
temp_b2 = params ;
end
wait4_start :
begin
if (start)
begin
obf_next_state = latch_din ;
temp_uk = din ;
end
else
begin
obf_next_state = wait4_start ;
temp_uk = uk;
end
temp_ready = wait4_start;
end
latch_din :
begin
obf_next_state = compute_a ;
end
compute_a :
begin
obf_next_state = compute_b ;
temp_ysum = yo1[31:3] + yo2[31:3];
end
compute_b :
begin
obf_next_state = compute_yk ;
// temp_utmp = b0t[23:0] + b1t[23:0] + b2t[23:0];
temp_utmp = b0t + b1t + b2t;
end
compute_yk :
begin
obf_next_state = wait4_count ;
temp_uk1 = uk ;
temp_uk2 = uk1 ;
temp_yk = ysum[26:0] + {utmp[22], utmp[22], utmp[22], utmp[22], utmp};
temp_wait_counter = 4 ;
end
wait4_count :
begin
if (wait_counter==0 )
begin
obf_next_state = latch_dout ;
temp_dout = yk[26:19];
temp_yk1 = yk[26:11] ;
temp_yk2 = yk1 ;
end
else
begin
obf_next_state = wait4_count ;
temp_dout = dout;
temp_yk1 = yk1;
//temp_yk2 = yk2;
end
temp_wait_counter = wait_counter - 1;
end
latch_dout :
if (count0)
obf_next_state = idle;
else
obf_next_state = wait4_start ;
endcase
end
//assign yo1 = mul_tc_16_16(yk1, a1, clk);
assign yo1 = yk1 + a1;
//assign yo2 = mul_tc_16_16(yk2, a2, clk);
assign yo2 = yk2 + a2;
//assign b0t = mul_tc_8_16(uk, b0, clk);
//assign b1t = mul_tc_8_16(uk1, b1, clk);
//assign b2t = mul_tc_8_16(uk2, b2, clk);
assign b0t = uk*b0;
assign b1t = uk1*b1;
assign b2t = uk2*b2;
// paj added to solve unused high order bit
assign b0tpaj = b0t;
assign b1tpaj = b1t;
assign b2tpaj = b2t;
// A COEFFICENTS
always @(posedge clk or posedge reset) begin
if (reset ) begin
uk <= 0 ;
uk1 <= 0 ;
uk2 <= 0 ;
yk1 <= 0 ;
yk2 <= 0 ;
yk <= 0 ;
ysum <= 0 ;
utmp <= 0 ;
a1 <= 0 ;
a2 <= 0 ;
b0 <= 0 ;
b1 <= 0 ;
b2 <= 0 ;
dout <= 0 ;
obf_state <= idle ;
ready <= 0;
end
else begin
obf_state <= obf_next_state ;
uk1 <= temp_uk1;
uk2 <= temp_uk2;
yk <= temp_yk;
uk <= temp_uk ;
a1 <= temp_a1 ;
a2 <= temp_a2 ;
b0 <= temp_b0 ;
b1 <= temp_b1 ;
b2 <= temp_b2 ;
ysum <= temp_ysum;
utmp <= temp_utmp;
dout <= temp_dout;
yk1 <= temp_yk1;
yk2 <= temp_yk2;
ready <= temp_ready;
end
end
// wait counter, count 4 clock after sum is calculated, to
// time outputs are ready, and filter is ready to accept next
// input
always @(posedge clk or posedge reset ) begin
if (reset )
wait_counter <= 0 ;
else begin
wait_counter <= temp_wait_counter ;
end
end
always @(posedge clk) begin
if (reset)
finite_counter<=100;
else
if (iir_start)
finite_counter<=finite_counter -1;
else
finite_counter<=finite_counter;
end
assign count0=finite_counter==7'b0;
always @(posedge clk) begin
del_count0 <= count0;
end
assign iir_done = (count0 && ~del_count0);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32O_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A32O_PP_BLACKBOX_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a32o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32O_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DLXBN_BEHAVIORAL_PP_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_no_pg/sky130_fd_sc_hs__u_dl_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxbn (
VPWR ,
VGND ,
Q ,
Q_N ,
D ,
GATE_N
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
wire 1 ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_hs__u_dl_p_no_pg u_dl_p_no_pg0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
assign awake = ( VPWR === 1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBN_BEHAVIORAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iobdg_dbg_porta.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg_dbg_porta (IO Bridge debug/visibility)
// Description:
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module iobdg_dbg_porta (/*AUTOARG*/
// Outputs
iob_io_dbg_data, iob_io_dbg_en, iob_io_dbg_ck_p, iob_io_dbg_ck_n,
l2_vis_armin, iob_clk_tr,
// Inputs
rst_l, clk, src0_data, src1_data, src2_data, src3_data, src4_data,
src0_vld, src1_vld, src2_vld, src3_vld, src4_vld,
creg_dbg_enet_ctrl, creg_dbg_enet_idleval, io_trigin
);
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
// Global interface
input rst_l;
input clk;
// Debug input buses
input [39:0] src0_data;
input [39:0] src1_data;
input [39:0] src2_data;
input [39:0] src3_data;
input [39:0] src4_data;
input src0_vld;
input src1_vld;
input src2_vld;
input src3_vld;
input src4_vld;
// Debug output bus
output [39:0] iob_io_dbg_data;
output iob_io_dbg_en;
output [2:0] iob_io_dbg_ck_p;
output [2:0] iob_io_dbg_ck_n;
// Control interface
input [63:0] creg_dbg_enet_ctrl;
input [63:0] creg_dbg_enet_idleval;
// Misc interface
input io_trigin;
output l2_vis_armin;
output iob_clk_tr;
// Internal signals
wire dbg_en;
wire dbg_armin_en;
wire dbg_trigin_en;
wire [3:0] dbg_sel;
wire [39:0] dbg_idleval;
reg [39:0] mux_data;
reg mux_vld;
wire [39:0] dbg_data;
wire iob_io_dbg_ck_p_next;
wire io_trigin_d1;
wire io_trigin_d2;
wire io_trigin_d3;
wire io_trigin_detected;
wire iob_clk_tr_a1;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
assign dbg_en = creg_dbg_enet_ctrl[8];
assign dbg_armin_en = creg_dbg_enet_ctrl[6];
assign dbg_trigin_en = creg_dbg_enet_ctrl[5];
assign dbg_sel = creg_dbg_enet_ctrl[3:0];
assign dbg_idleval = creg_dbg_enet_idleval[39:0];
always @(/*AUTOSENSE*/dbg_sel or src0_data or src0_vld or src1_data
or src1_vld or src2_data or src2_vld or src3_data
or src3_vld or src4_data or src4_vld)
case (dbg_sel)
4'b0000: {mux_vld,mux_data} = {src0_vld,src0_data};
4'b0001: {mux_vld,mux_data} = {src1_vld,src1_data};
4'b0010: {mux_vld,mux_data} = {src2_vld,src2_data};
4'b0011: {mux_vld,mux_data} = {src3_vld,src3_data};
4'b0100: {mux_vld,mux_data} = {src4_vld,src4_data};
default: {mux_vld,mux_data} = {1'b0,40'b0};
endcase // case(dbg_sel)
assign dbg_data = mux_vld ? mux_data : dbg_idleval;
dff_ns #(40) iob_io_dbg_data_ff (.din(dbg_data),
.clk(clk),
.q(iob_io_dbg_data));
dff_ns #(1) iob_io_dbg_en_ff (.din(dbg_en),
.clk(clk),
.q(iob_io_dbg_en));
// Generate clocks for the debug pad
assign iob_io_dbg_ck_p_next = ~iob_io_dbg_ck_p[0] & dbg_en;
dff_ns #(1) iob_io_dbg_ck_p_ff (.din(iob_io_dbg_ck_p_next),
.clk(clk),
.q(iob_io_dbg_ck_p[0]));
assign iob_io_dbg_ck_p[1] = iob_io_dbg_ck_p[0];
assign iob_io_dbg_ck_p[2] = iob_io_dbg_ck_p[0];
assign iob_io_dbg_ck_n = ~iob_io_dbg_ck_p;
// Flop TRIGIN pin and detect edge
dffrl_ns #(1) io_trigin_d1_ff (.din(io_trigin),
.clk(clk),
.rst_l(rst_l),
.q(io_trigin_d1));
dffrl_ns #(1) io_trigin_d2_ff (.din(io_trigin_d1),
.clk(clk),
.rst_l(rst_l),
.q(io_trigin_d2));
dffrl_ns #(1) io_trigin_d3_ff (.din(io_trigin_d2),
.clk(clk),
.rst_l(rst_l),
.q(io_trigin_d3));
assign io_trigin_detected = io_trigin_d2 & ~io_trigin_d3;
// Route TRIGIN pin to L2 Visibility port as ARM_IN
assign l2_vis_armin = dbg_armin_en & io_trigin_detected;
// Route TRIGIN pin to clock block for stop_and_scan
assign iob_clk_tr_a1 = dbg_trigin_en & io_trigin_detected;
dffrl_ns #(1) iob_clk_tr_ff (.din(iob_clk_tr_a1),
.clk(clk),
.rst_l(rst_l),
.q(iob_clk_tr));
endmodule // iobdg_dbg_porta
// Local Variables:
// verilog-auto-sense-defines-constant:t
// End:
|
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.2 (win64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
//Date : Sun Mar 06 21:30:27 2016
//Host : raw-PC running 64-bit Service Pack 1 (build 7601)
//Command : generate_target system_wrapper.bd
//Design : system_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
btns_5bit_tri_i,
sw_8bit_tri_i);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input [4:0]btns_5bit_tri_i;
input [7:0]sw_8bit_tri_i;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [4:0]btns_5bit_tri_i;
wire [7:0]sw_8bit_tri_i;
system system_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.btns_5bit_tri_i(btns_5bit_tri_i),
.sw_8bit_tri_i(sw_8bit_tri_i));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_LP_V
`define SKY130_FD_SC_LP__A221O_LP_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221o_lp (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221o_lp (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_LP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:30:27 03/03/2015
// Design Name:
// Module Name: vga
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_driver(clk, color, hsync, vsync, red, green, blue, x, y);
// VGA signal explanation and timing values for specific modes:
// http://www-mtl.mit.edu/Courses/6.111/labkit/vga.shtml
// 640x480 @ 60Hz, 25MHz pixel clock
parameter H_ACTIVE = 640;
parameter H_FRONT = 16;
parameter H_PULSE = 96;
parameter H_BACK = 48;
parameter V_ACTIVE = 480;
parameter V_FRONT = 11;
parameter V_PULSE = 2;
parameter V_BACK = 31;
input clk;
input [7:0] color;
output hsync, vsync;
output [9:0] x, y;
output [2:0] red, green;
output [1:0] blue;
reg [9:0] h_count;
reg [9:0] v_count;
reg [6:0] bar_count;
reg [2:0] column_count;
always @(posedge clk)
begin
if (h_count < H_ACTIVE + H_FRONT + H_PULSE + H_BACK - 1)
begin
// Increment horizontal count for each tick of the pixel clock
h_count <= h_count + 1;
if (bar_count>91)
begin
bar_count <= 0;
column_count <= column_count+1;
end
else
begin
bar_count <= bar_count + 1;
end
end
else
begin
bar_count <= 0;
column_count <= 0;
// At the end of the line, reset horizontal count and increment vertical
h_count <= 0;
if (v_count < V_ACTIVE + V_FRONT + V_PULSE + V_BACK - 1)
v_count <= v_count + 1;
else
// At the end of the frame, reset vertical count
v_count <= 0;
end
end
// Generate horizontal and vertical sync pulses at the appropriate time
assign hsync = h_count > H_ACTIVE + H_FRONT && h_count < H_ACTIVE + H_FRONT + H_PULSE;
assign vsync = v_count > V_ACTIVE + V_FRONT && v_count < V_ACTIVE + V_FRONT + V_PULSE;
// Output x and y coordinates
assign x = h_count < H_ACTIVE ? h_count : 0;
assign y = v_count < V_ACTIVE ? v_count : 0;
// Generate separate RGB signals from different parts of color byte
// Output black during horizontal and vertical blanking intervals
assign red = h_count < H_ACTIVE && v_count < V_ACTIVE ? color[7:5] : 3'b0;
assign green = h_count < H_ACTIVE && v_count < V_ACTIVE ? color[4:2] : 3'b0;
assign blue = h_count < H_ACTIVE && v_count < V_ACTIVE ? color[1:0] : 2'b0;
assign colour_count = column_count;
endmodule
|
`include "memory.v"
module Memory(input[15:0] in, input clock, load, input[14:0] address, output[15:0] out);
wire[15:0] outM, outS, outK, outSK;
Not g1(address[14], N14);
And g2(N14, load, Mload);
And g3(address[14], load, Sload);
RAM16K ram16k(in, clock, Mload, address[13:0], outM);
RAM8K screen(in, clock, Sload, address[12:0], outS);
Register keyboard(16'h0F0F, clock, 1'b0, outK);
Mux16 g4(outM, outSK, address[14], out);
Mux16 g5(outS, outK, address[13], outSK);
endmodule
module CPU(input[15:0] inM, I, input clock, reset, output[15:0] outM, output writeM, output[14:0] addressM, pc);
wire[15:0] Ain, Aout, AorM, ALUout, Dout, pcOut, addressMOut;
Or g1(ng, zr, ngzr); // ngzr = (ng|zr)
Not g2(ngzr, g); // g = out > 0 = !(ng|zr); ng = out < 0; zr = out = 0
And g3(ng, I[2], passLT); // ngLT = (ng<)
And g4(zr, I[1], passEQ); // zrEQ = (zr&EQ)
And g5(g, I[0], passGT); // gGT = (g>)
Or g6(passLT, passEQ, passLE);
Or g7(passLE, passGT, pass);
And g8(I[15], pass, PCload); // PCload = I15&J
// ALU
Mux16 g9(Aout, inM, I[12], AorM); // Mux ALU in : cAorM = I[12]
ALU alu(Dout, AorM, I[11], I[10], I[9], I[8], I[7], I[6], ALUout, zr, ng);
PC pc1(Aout, clock, PCload, 1'b1, reset, pcOut);
assign pc = pcOut[14:0];
// A register
Not g10(I[15], Atype);
And g11(I[15], I[5], AluToA); // AluToA = I[15]&d1
Or g12(Atype, AluToA, Aload);
Mux16 g13(I, ALUout, AluToA, Ain); // sel=I[15]
Register A(Ain, clock, Aload, Aout);
// D register
And g14(I[15], I[4], Dload); // Aload = I[15]&d2
Register D(ALUout, clock, Dload, Dout);
// output
assign addressM = Aout[14:0];
And g16(I[15], I[3], writeM); // writeM = I[15] & d3
And16 g17(ALUout, ALUout, outM);
endmodule
module Computer(input clock, reset);
wire[15:0] inM, outM, I;
wire[14:0] addressM, pc;
Memory ram(inM, !clock, loadM, addressM, outM);
ROM32K rom(pc, I);
CPU cpu(outM, I, clock, reset, inM, loadM, addressM, pc);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLRBP_PP_BLACKBOX_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBP_PP_BLACKBOX_V
|
// Code generated by Icestudio 0.8.1w202112300112
`default_nettype none
//---- Top entity
module main #(
parameter v98ea37 = 240000,
parameter v4b43d0 = 2,
parameter v315560 = 25,
parameter v0f02ae = -2
) (
input vclk,
output [7:0] vb5f8d6
);
localparam p2 = v98ea37;
localparam p6 = v0f02ae;
localparam p9 = v315560;
localparam p18 = v4b43d0;
wire [0:7] w0;
wire w1;
wire [0:2] w3;
wire [0:7] w4;
wire [0:7] w5;
wire [0:7] w7;
wire w8;
wire [0:7] w10;
wire [0:7] w11;
wire [0:7] w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w19;
wire w20;
wire w21;
wire w22;
wire w23;
wire w24;
wire w25;
wire w26;
wire w27;
wire w28;
wire w29;
wire [0:7] w30;
wire w31;
wire w32;
wire [0:7] w33;
wire [0:7] w34;
wire w35;
wire w36;
wire w37;
wire w38;
wire w39;
wire w40;
wire [0:7] w41;
wire [0:7] w42;
wire [0:7] w43;
wire [0:7] w44;
assign vb5f8d6 = w0;
assign w23 = vclk;
assign w24 = vclk;
assign w25 = vclk;
assign w26 = vclk;
assign w27 = vclk;
assign w28 = vclk;
assign w29 = vclk;
assign w22 = w21;
assign w24 = w23;
assign w25 = w23;
assign w25 = w24;
assign w26 = w23;
assign w26 = w24;
assign w26 = w25;
assign w27 = w23;
assign w27 = w24;
assign w27 = w25;
assign w27 = w26;
assign w28 = w23;
assign w28 = w24;
assign w28 = w25;
assign w28 = w26;
assign w28 = w27;
assign w29 = w23;
assign w29 = w24;
assign w29 = w25;
assign w29 = w26;
assign w29 = w27;
assign w29 = w28;
assign w32 = w31;
assign w33 = w4;
assign w34 = w4;
assign w34 = w33;
assign w35 = w16;
assign w37 = w36;
assign w38 = w36;
assign w38 = w37;
assign w39 = w36;
assign w39 = w37;
assign w39 = w38;
assign w42 = w5;
assign w43 = w5;
assign w43 = w42;
v75c864 v645c43 (
.va8064a(w0),
.v5a2634(w1),
.v1336f1(w3)
);
vfebcfe vd146ce (
.v9fb85f(w1)
);
vbce541 #(
.va04f5d(p2)
) v47bd3e (
.v4642b6(w15),
.v6dda25(w23)
);
v857d2e v449769 (
.v19a59f(w4),
.v6dda25(w24),
.vccca56(w32),
.vec26ff(w44)
);
v9c1f69 v71f96f (
.v1045ee(w3),
.vcc8c7c(w33)
);
vcb23aa ve224a5 (
.veb2f59(w4),
.v39966a(w43),
.v62bf25(w44)
);
v89d234 v55be45 (
.vb1c024(w5),
.v39f831(w7),
.vf892a0(w8),
.v41eb95(w25)
);
vcb23aa vec74fb (
.veb2f59(w5),
.v39966a(w30),
.v62bf25(w41)
);
vffc517 #(
.vc5c8ea(p6)
) v30a629 (
.va0aeac(w11)
);
v1bbb5b v64a91b (
.v9d2a6a(w7),
.v2a1cbe(w10),
.v2d3366(w38),
.v9d7ae8(w41)
);
v873425 v8ee855 (
.vcbab45(w8),
.v0e28cb(w31),
.v3ca442(w39)
);
vffc517 #(
.vc5c8ea(p9)
) v76838a (
.va0aeac(w10)
);
v89d234 v7825c7 (
.v39f831(w11),
.v41eb95(w26),
.vb1c024(w30),
.vf892a0(w36)
);
v78be07 va08ca8 (
.v2ce16c(w14),
.vcc8c7c(w42)
);
vb2762a vecb412 (
.v715730(w12),
.v4642b6(w13),
.vf191e6(w34)
);
vba518e vc58236 (
.v0e28cb(w13),
.v3ca442(w14),
.vcbab45(w40)
);
vba518e v50132d (
.v0e28cb(w15),
.vcbab45(w31),
.v3ca442(w35)
);
v4c1570 vf52c7c (
.v4642b6(w16),
.v6dda25(w27),
.v27dec4(w37),
.v92a149(w40)
);
v3676a0 v91794b (
.v0e28cb(w16),
.vcbab45(w17)
);
vba518e v496601 (
.v0e28cb(w17),
.v3ca442(w22),
.vcbab45(w36)
);
vda0861 vf481a4 (
.vffb58f(w12)
);
v876875 v59e5e1 (
.v4642b6(w20),
.vd6bebe(w28)
);
v56885a #(
.v187a47(p18)
) v9413db (
.v6e1dd1(w19),
.va9e2af(w21),
.v5688a8(w29)
);
v873425 vd0afc2 (
.vcbab45(w19),
.v0e28cb(w20),
.v3ca442(w21)
);
endmodule
//---- Top entity
module v75c864 (
input v5a2634,
input [2:0] v1336f1,
output [7:0] va8064a
);
wire w0;
wire [0:7] w1;
wire [0:2] w2;
assign w0 = v5a2634;
assign va8064a = w1;
assign w2 = v1336f1;
v75c864_v45bd49 v45bd49 (
.i(w0),
.o(w1),
.sel(w2)
);
endmodule
//---------------------------------------------------
//-- Demux-3-8
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Demultiplexor de 1 bit, de 3 a 8 (salida de bus)
//---------------------------------------------------
module v75c864_v45bd49 (
input i,
input [2:0] sel,
output [7:0] o
);
assign o = i << sel;
endmodule
//---- Top entity
module vfebcfe (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vfebcfe_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 1
//---------------------------------------------------
module vfebcfe_vb2eccd (
output q
);
//-- Constant bit-1
assign q = 1'b1;
endmodule
//---- Top entity
module vbce541 #(
parameter va04f5d = 16777216
) (
input v6dda25,
output v4642b6
);
localparam p1 = va04f5d;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
wire w4;
wire w5;
assign v4642b6 = w0;
assign w5 = v6dda25;
assign w4 = w0;
vef98b5 #(
.vc5c8ea(p1)
) v4016e8 (
.ve70c2d(w3)
);
vd84ae0 v45b714 (
.v4642b6(w0),
.va89056(w2),
.v06bdfb(w3)
);
v97d607 v2299cf (
.v9e1c43(w2),
.ve556f1(w4),
.v6dda25(w5)
);
endmodule
//---------------------------------------------------
//-- sysclk_divN_24
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- sysclk_divN_24bits: Generate a signal from the division of the system clock by N. (24-bits precision) (N = 2,3,4,..,0x1000000))
//---------------------------------------------------
//---- Top entity
module vef98b5 #(
parameter vc5c8ea = 1
) (
output [23:0] ve70c2d
);
localparam p0 = vc5c8ea;
wire [0:23] w1;
assign ve70c2d = w1;
vef98b5_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 24-bits-k-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 24-bits k-1 constant (Input values: 1,2,...,h1000000). It returns the value input by the user minus 1. Outputs: 0,1,2,...,FFFFFF
//---------------------------------------------------
module vef98b5_v465065 #(
parameter VALUE = 0
) (
output [23:0] k
);
assign k = VALUE-1;
endmodule
//---- Top entity
module vd84ae0 (
input [23:0] v06bdfb,
input [23:0] va89056,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:23] w4;
wire [0:23] w5;
wire [0:7] w6;
wire [0:7] w7;
wire [0:7] w8;
wire [0:7] w9;
wire [0:7] w10;
wire [0:7] w11;
assign v4642b6 = w0;
assign w4 = v06bdfb;
assign w5 = va89056;
vb2762a vb6832a (
.v4642b6(w1),
.v715730(w8),
.vf191e6(w11)
);
vb2762a v302658 (
.v4642b6(w2),
.v715730(w7),
.vf191e6(w10)
);
vae245c v9196c7 (
.vcbab45(w0),
.v3ca442(w1),
.v0e28cb(w2),
.v033bf6(w3)
);
v6fef69 vb1e577 (
.v9804b7(w5),
.vd83cb2(w9),
.v243fb2(w10),
.va2a3a1(w11)
);
v6fef69 v62b64f (
.v9804b7(w4),
.vd83cb2(w6),
.v243fb2(w7),
.va2a3a1(w8)
);
vb2762a v9a65c6 (
.v4642b6(w3),
.v715730(w6),
.vf191e6(w9)
);
endmodule
//---------------------------------------------------
//-- comp2-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-24bit: Comparator of two 24-bit numbers
//---------------------------------------------------
//---- Top entity
module vb2762a (
input [7:0] v715730,
input [7:0] vf191e6,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire [0:3] w8;
assign v4642b6 = w0;
assign w3 = v715730;
assign w4 = vf191e6;
v438230 v577a36 (
.v4642b6(w2),
.v693354(w6),
.v5369cd(w8)
);
vba518e v707c6e (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w2)
);
v6bdcd9 v921a9f (
.vcc8c7c(w4),
.v651522(w7),
.v2cc41f(w8)
);
v6bdcd9 v8cfa4d (
.vcc8c7c(w3),
.v651522(w5),
.v2cc41f(w6)
);
v438230 vfc1765 (
.v4642b6(w1),
.v693354(w5),
.v5369cd(w7)
);
endmodule
//---------------------------------------------------
//-- comp2-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-8bit: Comparator of two 8-bit numbers
//---------------------------------------------------
//---- Top entity
module v438230 (
input [3:0] v693354,
input [3:0] v5369cd,
output v4642b6
);
wire w0;
wire [0:3] w1;
wire [0:3] w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
assign v4642b6 = w0;
assign w1 = v693354;
assign w2 = v5369cd;
v23b15b v09a5a5 (
.v4642b6(w3),
.v27dec4(w12),
.v6848e9(w14)
);
v23b15b vc1b29d (
.v4642b6(w4),
.v27dec4(w11),
.v6848e9(w13)
);
v23b15b vcd27ce (
.v4642b6(w5),
.v27dec4(w9),
.v6848e9(w10)
);
vc4f23a vea9c80 (
.v985fcb(w1),
.v4f1fd3(w7),
.vda577d(w9),
.v3f8943(w11),
.v64d863(w12)
);
vc4f23a va7dcdc (
.v985fcb(w2),
.v4f1fd3(w8),
.vda577d(w10),
.v3f8943(w13),
.v64d863(w14)
);
v23b15b va0849c (
.v4642b6(w6),
.v27dec4(w7),
.v6848e9(w8)
);
veffd42 v6e3e65 (
.vcbab45(w0),
.v3ca442(w3),
.v0e28cb(w4),
.v033bf6(w5),
.v9eb652(w6)
);
endmodule
//---------------------------------------------------
//-- comp2-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-4bit: Comparator of two 4-bit numbers
//---------------------------------------------------
//---- Top entity
module v23b15b (
input v27dec4,
input v6848e9,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire w3;
assign w1 = v27dec4;
assign v4642b6 = w2;
assign w3 = v6848e9;
vd12401 v955b2b (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v3676a0 vf92936 (
.v0e28cb(w0),
.vcbab45(w2)
);
endmodule
//---------------------------------------------------
//-- comp2-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-1bit: Comparator of two 1-bit numbers
//---------------------------------------------------
//---- Top entity
module vd12401 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vd12401_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- XOR2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- XOR gate: two bits input xor gate
//---------------------------------------------------
module vd12401_vf4938a (
input a,
input b,
output c
);
//-- XOR gate
//-- Verilog implementation
assign c = a ^ b;
endmodule
//---- Top entity
module v3676a0 (
input v0e28cb,
output vcbab45
);
wire w0;
wire w1;
assign w0 = v0e28cb;
assign vcbab45 = w1;
v3676a0_vd54ca1 vd54ca1 (
.a(w0),
.q(w1)
);
endmodule
//---------------------------------------------------
//-- NOT
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- NOT gate (Verilog implementation)
//---------------------------------------------------
module v3676a0_vd54ca1 (
input a,
output q
);
//-- NOT Gate
assign q = ~a;
endmodule
//---- Top entity
module vc4f23a (
input [3:0] v985fcb,
output v4f1fd3,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign v3f8943 = w0;
assign v64d863 = w1;
assign vda577d = w2;
assign v4f1fd3 = w3;
assign w4 = v985fcb;
vc4f23a_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.o2(w2),
.o3(w3),
.i(w4)
);
endmodule
//---------------------------------------------------
//-- Bus4-Split-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus4-Split-all: Split the 4-bits bus into its wires
//---------------------------------------------------
module vc4f23a_v9a2a06 (
input [3:0] i,
output o3,
output o2,
output o1,
output o0
);
assign o3 = i[3];
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module veffd42 (
input v9eb652,
input v033bf6,
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w0 = v3ca442;
assign w1 = v9eb652;
assign w2 = v033bf6;
assign w3 = v0e28cb;
assign vcbab45 = w4;
vba518e vf3ef0f (
.v3ca442(w0),
.v0e28cb(w3),
.vcbab45(w6)
);
vba518e vdcc53d (
.v0e28cb(w1),
.v3ca442(w2),
.vcbab45(w5)
);
vba518e v17ac22 (
.vcbab45(w4),
.v0e28cb(w5),
.v3ca442(w6)
);
endmodule
//---------------------------------------------------
//-- AND4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Three bits input And gate
//---------------------------------------------------
//---- Top entity
module vba518e (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vba518e_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- AND2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Two bits input And gate
//---------------------------------------------------
module vba518e_vf4938a (
input a,
input b,
output c
);
//-- AND gate
//-- Verilog implementation
assign c = a & b;
endmodule
//---- Top entity
module v6bdcd9 (
input [7:0] vcc8c7c,
output [3:0] v651522,
output [3:0] v2cc41f
);
wire [0:3] w0;
wire [0:3] w1;
wire [0:7] w2;
assign v651522 = w0;
assign v2cc41f = w1;
assign w2 = vcc8c7c;
v6bdcd9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Split-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Split-half: Split the 8-bits bus into two buses of the same size
//---------------------------------------------------
module v6bdcd9_v9a2a06 (
input [7:0] i,
output [3:0] o1,
output [3:0] o0
);
assign o1 = i[7:4];
assign o0 = i[3:0];
endmodule
//---- Top entity
module vae245c (
input v033bf6,
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = v033bf6;
assign w1 = v0e28cb;
assign w2 = v3ca442;
assign vcbab45 = w4;
vba518e v19b5b0 (
.v0e28cb(w0),
.v3ca442(w1),
.vcbab45(w3)
);
vba518e vf3ef0f (
.v3ca442(w2),
.v0e28cb(w3),
.vcbab45(w4)
);
endmodule
//---------------------------------------------------
//-- AND3
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Three bits input And gate
//---------------------------------------------------
//---- Top entity
module v6fef69 (
input [23:0] v9804b7,
output [7:0] vd83cb2,
output [7:0] v243fb2,
output [7:0] va2a3a1
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:23] w3;
assign v243fb2 = w0;
assign vd83cb2 = w1;
assign va2a3a1 = w2;
assign w3 = v9804b7;
v6fef69_v9a2a06 v9a2a06 (
.o1(w0),
.o2(w1),
.o0(w2),
.i(w3)
);
endmodule
//---------------------------------------------------
//-- Bus24-Split-one-third
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Split-one-third: Split the 24-bits bus into three buses of the same size
//---------------------------------------------------
module v6fef69_v9a2a06 (
input [23:0] i,
output [7:0] o2,
output [7:0] o1,
output [7:0] o0
);
assign o2 = i[23:16];
assign o1 = i[15:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module v97d607 (
input v6dda25,
input ve556f1,
output [23:0] v9e1c43,
output ve37344
);
wire w0;
wire [0:23] w1;
wire [0:23] w2;
wire w3;
wire [0:23] w4;
wire w5;
assign w0 = ve556f1;
assign w3 = v6dda25;
assign v9e1c43 = w4;
assign ve37344 = w5;
assign w4 = w1;
v5495b5 v5e4c9c (
.v782748(w0),
.vb02eea(w1),
.v15c6e6(w2),
.v6dda25(w3)
);
v9c4559 v62e821 (
.v005b83(w1),
.v53d485(w2),
.v4642b6(w5)
);
endmodule
//---------------------------------------------------
//-- syscounter-rst-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 24-bits Syscounter with reset
//---------------------------------------------------
//---- Top entity
module v5495b5 (
input v6dda25,
input v782748,
input [23:0] v15c6e6,
output [23:0] vb02eea
);
wire [0:23] w0;
wire [0:23] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:7] w5;
wire [0:7] w6;
wire [0:7] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
assign vb02eea = w0;
assign w1 = v15c6e6;
assign w8 = v6dda25;
assign w9 = v6dda25;
assign w10 = v6dda25;
assign w11 = v782748;
assign w12 = v782748;
assign w13 = v782748;
assign w9 = w8;
assign w10 = w8;
assign w10 = w9;
assign w12 = w11;
assign w13 = w11;
assign w13 = w12;
v6fef69 vad6f1d (
.v9804b7(w1),
.va2a3a1(w5),
.v243fb2(w6),
.vd83cb2(w7)
);
v33e50d vba7365 (
.v6d326e(w0),
.v77c6e9(w2),
.vf7d213(w3),
.vba04ee(w4)
);
vcf4344 v13ddeb (
.vc1f0d2(w2),
.vd85d4e(w5),
.v6dda25(w10),
.v782748(w13)
);
vcf4344 v08e1bd (
.vc1f0d2(w3),
.vd85d4e(w6),
.v6dda25(w9),
.v782748(w12)
);
vcf4344 v5c3b0f (
.vc1f0d2(w4),
.vd85d4e(w7),
.v6dda25(w8),
.v782748(w11)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x24
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x24: 24 D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v33e50d (
input [7:0] vba04ee,
input [7:0] vf7d213,
input [7:0] v77c6e9,
output [23:0] v6d326e
);
wire [0:23] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
assign v6d326e = w0;
assign w1 = vf7d213;
assign w2 = v77c6e9;
assign w3 = vba04ee;
v33e50d_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2),
.i2(w3)
);
endmodule
//---------------------------------------------------
//-- Bus24-Join-one-third
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Join-one-third: Join the three buses into an 24-bits Bus
//---------------------------------------------------
module v33e50d_v9a2a06 (
input [7:0] i2,
input [7:0] i1,
input [7:0] i0,
output [23:0] o
);
assign o = {i2, i1, i0};
endmodule
//---- Top entity
module vcf4344 (
input v6dda25,
input v782748,
input [7:0] vd85d4e,
output [7:0] vc1f0d2
);
wire [0:3] w0;
wire [0:3] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:3] w4;
wire [0:3] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w2 = vd85d4e;
assign vc1f0d2 = w3;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 = v782748;
assign w9 = v782748;
assign w7 = w6;
assign w9 = w8;
v5c75f6 vbdef88 (
.v50034e(w0),
.v4de61b(w1),
.v6dda25(w7),
.v782748(w9)
);
v6bdcd9 vc95779 (
.v2cc41f(w1),
.vcc8c7c(w2),
.v651522(w4)
);
vafb28f v618315 (
.v3c88fc(w0),
.va9ac17(w3),
.v515fe7(w5)
);
v5c75f6 v6188f9 (
.v4de61b(w4),
.v50034e(w5),
.v6dda25(w6),
.v782748(w8)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x08
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x08: Eight D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v5c75f6 (
input v6dda25,
input v782748,
input [3:0] v4de61b,
output [3:0] v50034e
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v4de61b;
assign v50034e = w7;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = v782748;
assign w15 = v782748;
assign w16 = v782748;
assign w17 = v782748;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
vc4f23a v4b1225 (
.v3f8943(w2),
.v64d863(w3),
.vda577d(w4),
.v985fcb(w6),
.v4f1fd3(w8)
);
v84f0a1 v6491fd (
.v03aaf0(w0),
.vee8a83(w1),
.vf8041d(w5),
.v11bca5(w7),
.vd84a57(w9)
);
v2be0f8 v10a04f (
.v4642b6(w0),
.vf354ee(w3),
.vd53b77(w13),
.v27dec4(w17)
);
v2be0f8 v7d9648 (
.v4642b6(w1),
.vf354ee(w2),
.vd53b77(w12),
.v27dec4(w16)
);
v2be0f8 v004b14 (
.vf354ee(w4),
.v4642b6(w5),
.vd53b77(w11),
.v27dec4(w15)
);
v2be0f8 v8aa818 (
.vf354ee(w8),
.v4642b6(w9),
.vd53b77(w10),
.v27dec4(w14)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x04
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x04: Three D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v84f0a1 (
input vd84a57,
input vf8041d,
input vee8a83,
input v03aaf0,
output [3:0] v11bca5
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign w2 = vf8041d;
assign w3 = vd84a57;
assign v11bca5 = w4;
v84f0a1_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.i2(w2),
.i3(w3),
.o(w4)
);
endmodule
//---------------------------------------------------
//-- Bus4-Join-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus4-Join-all: Join all the wires into a 4-bits Bus
//---------------------------------------------------
module v84f0a1_v9a2a06 (
input i3,
input i2,
input i1,
input i0,
output [3:0] o
);
assign o = {i3, i2, i1, i0};
endmodule
//---- Top entity
module v2be0f8 #(
parameter vbd3217 = 0
) (
input vd53b77,
input v27dec4,
input vf354ee,
output v4642b6
);
localparam p5 = vbd3217;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w6;
assign w2 = v27dec4;
assign w3 = vf354ee;
assign v4642b6 = w4;
assign w6 = vd53b77;
v3676a0 v7539bf (
.vcbab45(w1),
.v0e28cb(w2)
);
vba518e vfe8158 (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v053dc2 #(
.v71e305(p5)
) vd104a4 (
.vf54559(w0),
.ve8318d(w4),
.va4102a(w6)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x01: D Flip flop with reset input. When rst=1, the DFF is 0
//---------------------------------------------------
//---- Top entity
module v053dc2 #(
parameter v71e305 = 0
) (
input va4102a,
input vf54559,
output ve8318d
);
localparam p2 = v71e305;
wire w0;
wire w1;
wire w3;
assign w0 = va4102a;
assign ve8318d = w1;
assign w3 = vf54559;
v053dc2_vb8adf8 #(
.INI(p2)
) vb8adf8 (
.clk(w0),
.q(w1),
.d(w3)
);
endmodule
//---------------------------------------------------
//-- DFF
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- D Flip-flop (verilog implementation)
//---------------------------------------------------
module v053dc2_vb8adf8 #(
parameter INI = 0
) (
input clk,
input d,
output q
);
//-- Initial value
reg q = INI;
//-- Capture the input data
//-- on the rising edge of
//-- the system clock
always @(posedge clk)
q <= d;
endmodule
//---- Top entity
module vafb28f (
input [3:0] v515fe7,
input [3:0] v3c88fc,
output [7:0] va9ac17
);
wire [0:7] w0;
wire [0:3] w1;
wire [0:3] w2;
assign va9ac17 = w0;
assign w1 = v515fe7;
assign w2 = v3c88fc;
vafb28f_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Join-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Join-half: Join the two same halves into an 8-bits Bus
//---------------------------------------------------
module vafb28f_v9a2a06 (
input [3:0] i1,
input [3:0] i0,
output [7:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v9c4559 #(
parameter v6c5139 = 1
) (
input [23:0] v005b83,
output v4642b6,
output [23:0] v53d485
);
localparam p1 = v6c5139;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
assign v4642b6 = w0;
assign w2 = v005b83;
assign v53d485 = w3;
v44c099 #(
.vd73390(p1)
) v8c0045 (
.v4642b6(w0),
.vd90f46(w2),
.v8826c0(w3)
);
endmodule
//---------------------------------------------------
//-- Inc1-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Inc1-24bit: Increment a 24-bits number by one
//---------------------------------------------------
//---- Top entity
module v44c099 #(
parameter vd73390 = 0
) (
input [23:0] vd90f46,
output v4642b6,
output [23:0] v8826c0
);
localparam p1 = vd73390;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
wire [0:23] w4;
assign v4642b6 = w0;
assign v8826c0 = w2;
assign w3 = vd90f46;
v4c802f #(
.vc5c8ea(p1)
) ve78914 (
.v8513f7(w4)
);
v91404d v19ed8b (
.v4642b6(w0),
.vb5c06c(w2),
.v7959e8(w3),
.vb5a2f2(w4)
);
endmodule
//---------------------------------------------------
//-- AdderK-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderK-24bit: Adder of 24-bit operand and 24-bit constant
//---------------------------------------------------
//---- Top entity
module v4c802f #(
parameter vc5c8ea = 0
) (
output [23:0] v8513f7
);
localparam p0 = vc5c8ea;
wire [0:23] w1;
assign v8513f7 = w1;
v4c802f_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 24-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 24-bits generic constant
//---------------------------------------------------
module v4c802f_v465065 #(
parameter VALUE = 0
) (
output [23:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v91404d (
input [23:0] vb5a2f2,
input [23:0] v7959e8,
output v4642b6,
output [23:0] vb5c06c
);
wire w0;
wire [0:7] w1;
wire [0:7] w2;
wire w3;
wire w4;
wire [0:15] w5;
wire [0:23] w6;
wire [0:15] w7;
wire [0:23] w8;
wire [0:15] w9;
wire [0:7] w10;
wire [0:23] w11;
wire [0:7] w12;
wire [0:7] w13;
wire [0:7] w14;
wire [0:7] w15;
wire [0:7] w16;
wire [0:7] w17;
assign v4642b6 = w4;
assign w6 = v7959e8;
assign w8 = vb5a2f2;
assign vb5c06c = w11;
vcb23aa v8e0bba (
.v4642b6(w0),
.v62bf25(w2),
.v39966a(w16),
.veb2f59(w17)
);
vc3c498 v917bbf (
.vb9cfc3(w0),
.veeaa8e(w1),
.v4642b6(w3),
.v45c6ee(w14),
.v20212e(w15)
);
v8cc49c v03c3e3 (
.vb334ae(w1),
.v2b8a97(w2),
.v14a530(w5)
);
vab13f0 v43653c (
.vb18564(w6),
.vf0a06e(w7),
.v5246f6(w17)
);
v306ca3 v177126 (
.v91b9c1(w7),
.vef5eee(w13),
.vd3ef3b(w15)
);
vab13f0 vf15711 (
.vb18564(w8),
.vf0a06e(w9),
.v5246f6(w16)
);
v306ca3 vf9ed57 (
.v91b9c1(w9),
.vef5eee(w12),
.vd3ef3b(w14)
);
vc3c498 vf0db78 (
.vb9cfc3(w3),
.v4642b6(w4),
.veeaa8e(w10),
.v45c6ee(w12),
.v20212e(w13)
);
va52e3b v67022b (
.vbf8961(w5),
.vf7d213(w10),
.v6d326e(w11)
);
endmodule
//---------------------------------------------------
//-- Adder-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-24bits: Adder of two operands of 24 bits
//---------------------------------------------------
//---- Top entity
module vcb23aa (
input [7:0] v39966a,
input [7:0] veb2f59,
output v4642b6,
output [7:0] v62bf25
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:7] w4;
wire w5;
wire w6;
wire [0:3] w7;
wire [0:3] w8;
wire [0:3] w9;
wire [0:3] w10;
assign w0 = veb2f59;
assign w1 = v39966a;
assign v62bf25 = w4;
assign v4642b6 = w5;
v6bdcd9 vd88c66 (
.vcc8c7c(w0),
.v651522(w9),
.v2cc41f(w10)
);
v6bdcd9 v26a0bb (
.vcc8c7c(w1),
.v651522(w7),
.v2cc41f(w8)
);
v25966b v9ea427 (
.v817794(w3),
.v4642b6(w6),
.v0550b6(w8),
.v24708e(w10)
);
vafb28f vc75346 (
.v515fe7(w2),
.v3c88fc(w3),
.va9ac17(w4)
);
va1ce30 v40c17f (
.v817794(w2),
.v4642b6(w5),
.vb9cfc3(w6),
.v0550b6(w7),
.v24708e(w9)
);
endmodule
//---------------------------------------------------
//-- Adder-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-8bits: Adder of two operands of 8 bits
//---------------------------------------------------
//---- Top entity
module v25966b (
input [3:0] v0550b6,
input [3:0] v24708e,
output v4642b6,
output [3:0] v817794
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign w5 = v24708e;
assign w6 = v0550b6;
assign v817794 = w7;
assign v4642b6 = w9;
v1ea21d vdbe125 (
.v4642b6(w0),
.v8e8a67(w2),
.v27dec4(w15),
.v82de4f(w18)
);
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w3),
.v27dec4(w14),
.v82de4f(w17)
);
vad119b v5d29b2 (
.v0ef266(w3),
.v8e8a67(w4),
.v4642b6(w8),
.v27dec4(w12),
.v82de4f(w16)
);
vc4f23a vf4a6ff (
.v985fcb(w5),
.v4f1fd3(w13),
.vda577d(w16),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a v9d4632 (
.v985fcb(w6),
.v4f1fd3(w11),
.vda577d(w12),
.v3f8943(w14),
.v64d863(w15)
);
v84f0a1 v140dbf (
.vee8a83(w1),
.v03aaf0(w2),
.vf8041d(w4),
.v11bca5(w7),
.vd84a57(w10)
);
vad119b v5c5937 (
.v0ef266(w8),
.v4642b6(w9),
.v8e8a67(w10),
.v27dec4(w11),
.v82de4f(w13)
);
endmodule
//---------------------------------------------------
//-- Adder-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-4bits: Adder of two operands of 4 bits
//---------------------------------------------------
//---- Top entity
module v1ea21d (
input v27dec4,
input v82de4f,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = v82de4f;
assign w1 = v27dec4;
assign v4642b6 = w3;
assign v8e8a67 = w4;
vad119b vb820a1 (
.v82de4f(w0),
.v27dec4(w1),
.v0ef266(w2),
.v4642b6(w3),
.v8e8a67(w4)
);
vd30ca9 v23ebb6 (
.v9fb85f(w2)
);
endmodule
//---------------------------------------------------
//-- Adder-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-1bit: Adder of two operands of 1 bit
//---------------------------------------------------
//---- Top entity
module vad119b (
input v27dec4,
input v82de4f,
input v0ef266,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
assign v8e8a67 = w1;
assign v4642b6 = w5;
assign w6 = v27dec4;
assign w7 = v27dec4;
assign w8 = v82de4f;
assign w9 = v82de4f;
assign w10 = v0ef266;
assign w11 = v0ef266;
assign w2 = w0;
assign w7 = w6;
assign w9 = w8;
assign w11 = w10;
vd12401 v2e3d9f (
.vcbab45(w0),
.v0e28cb(w7),
.v3ca442(w9)
);
vd12401 vb50462 (
.v0e28cb(w0),
.vcbab45(w1),
.v3ca442(w11)
);
vba518e v4882f4 (
.v3ca442(w2),
.vcbab45(w3),
.v0e28cb(w10)
);
vba518e v8fcf41 (
.vcbab45(w4),
.v0e28cb(w6),
.v3ca442(w8)
);
v873425 vc5b8b9 (
.v3ca442(w3),
.v0e28cb(w4),
.vcbab45(w5)
);
endmodule
//---------------------------------------------------
//-- AdderC-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-1bit: Adder of two operands of 1 bit plus the carry in
//---------------------------------------------------
//---- Top entity
module v873425 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
v873425_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- OR2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- OR2: Two bits input OR gate
//---------------------------------------------------
module v873425_vf4938a (
input a,
input b,
output c
);
//-- OR Gate
//-- Verilog implementation
assign c = a | b;
endmodule
//---- Top entity
module vd30ca9 (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vd30ca9_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 0
//---------------------------------------------------
module vd30ca9_vb2eccd (
output q
);
//-- Constant bit-0
assign q = 1'b0;
endmodule
//---- Top entity
module va1ce30 (
input [3:0] v0550b6,
input [3:0] v24708e,
input vb9cfc3,
output v4642b6,
output [3:0] v817794
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
wire w19;
assign w5 = v24708e;
assign w6 = v0550b6;
assign v817794 = w7;
assign v4642b6 = w9;
assign w11 = vb9cfc3;
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w3),
.v27dec4(w15),
.v82de4f(w18)
);
vad119b v5d29b2 (
.v0ef266(w3),
.v8e8a67(w4),
.v4642b6(w8),
.v27dec4(w13),
.v82de4f(w17)
);
vc4f23a vf4a6ff (
.v985fcb(w5),
.v4f1fd3(w14),
.vda577d(w17),
.v3f8943(w18),
.v64d863(w19)
);
vc4f23a v9d4632 (
.v985fcb(w6),
.v4f1fd3(w12),
.vda577d(w13),
.v3f8943(w15),
.v64d863(w16)
);
v84f0a1 v140dbf (
.vee8a83(w1),
.v03aaf0(w2),
.vf8041d(w4),
.v11bca5(w7),
.vd84a57(w10)
);
vad119b v5c5937 (
.v0ef266(w8),
.v4642b6(w9),
.v8e8a67(w10),
.v27dec4(w12),
.v82de4f(w14)
);
vad119b v3599be (
.v4642b6(w0),
.v8e8a67(w2),
.v0ef266(w11),
.v27dec4(w16),
.v82de4f(w19)
);
endmodule
//---------------------------------------------------
//-- AdderC-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-4bits: Adder of two operands of 4 bits and Carry in
//---------------------------------------------------
//---- Top entity
module vc3c498 (
input [7:0] v45c6ee,
input [7:0] v20212e,
input vb9cfc3,
output v4642b6,
output [7:0] veeaa8e
);
wire w0;
wire w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:3] w5;
wire [0:3] w6;
wire w7;
wire [0:3] w8;
wire [0:3] w9;
wire [0:3] w10;
wire [0:3] w11;
assign w1 = vb9cfc3;
assign w2 = v45c6ee;
assign w3 = v20212e;
assign veeaa8e = w4;
assign v4642b6 = w7;
v6bdcd9 v8d795a (
.vcc8c7c(w3),
.v651522(w10),
.v2cc41f(w11)
);
v6bdcd9 v23dbc5 (
.vcc8c7c(w2),
.v651522(w8),
.v2cc41f(w9)
);
vafb28f vef3a58 (
.va9ac17(w4),
.v3c88fc(w5),
.v515fe7(w6)
);
va1ce30 v0ff71a (
.v4642b6(w0),
.vb9cfc3(w1),
.v817794(w5),
.v0550b6(w9),
.v24708e(w11)
);
va1ce30 v12f94f (
.vb9cfc3(w0),
.v817794(w6),
.v4642b6(w7),
.v0550b6(w8),
.v24708e(w10)
);
endmodule
//---------------------------------------------------
//-- AdderC-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-8bits: Adder of two operands of 8 bits and Carry in
//---------------------------------------------------
//---- Top entity
module v8cc49c (
input [7:0] vb334ae,
input [7:0] v2b8a97,
output [15:0] v14a530
);
wire [0:15] w0;
wire [0:7] w1;
wire [0:7] w2;
assign v14a530 = w0;
assign w1 = v2b8a97;
assign w2 = vb334ae;
v8cc49c_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus16-Join-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus16-Join-half: Join the two same halves into an 16-bits Bus
//---------------------------------------------------
module v8cc49c_v9a2a06 (
input [7:0] i1,
input [7:0] i0,
output [15:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module vab13f0 (
input [23:0] vb18564,
output [15:0] vf0a06e,
output [7:0] v5246f6
);
wire [0:23] w0;
wire [0:15] w1;
wire [0:7] w2;
assign w0 = vb18564;
assign vf0a06e = w1;
assign v5246f6 = w2;
vab13f0_v9a2a06 v9a2a06 (
.i(w0),
.o1(w1),
.o0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus24-Split-16-8
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Split-16-8: Split the 24-bits bus into two buses of 16 and 8 wires
//---------------------------------------------------
module vab13f0_v9a2a06 (
input [23:0] i,
output [15:0] o1,
output [7:0] o0
);
assign o1 = i[23:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module v306ca3 (
input [15:0] v91b9c1,
output [7:0] vef5eee,
output [7:0] vd3ef3b
);
wire [0:15] w0;
wire [0:7] w1;
wire [0:7] w2;
assign w0 = v91b9c1;
assign vef5eee = w1;
assign vd3ef3b = w2;
v306ca3_v9a2a06 v9a2a06 (
.i(w0),
.o1(w1),
.o0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus16-Split-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus16-Split-half: Split the 16-bits bus into two buses of the same size
//---------------------------------------------------
module v306ca3_v9a2a06 (
input [15:0] i,
output [7:0] o1,
output [7:0] o0
);
assign o1 = i[15:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module va52e3b (
input [7:0] vf7d213,
input [15:0] vbf8961,
output [23:0] v6d326e
);
wire [0:15] w0;
wire [0:23] w1;
wire [0:7] w2;
assign w0 = vbf8961;
assign v6d326e = w1;
assign w2 = vf7d213;
va52e3b_v9a2a06 v9a2a06 (
.i0(w0),
.o(w1),
.i1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus24-Join-8-16 CLONE
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Join-8-16: Join the two buses into an 24-bits Bus
//---------------------------------------------------
module va52e3b_v9a2a06 (
input [7:0] i1,
input [15:0] i0,
output [23:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v857d2e (
input v6dda25,
input [7:0] vec26ff,
input vccca56,
output [7:0] v19a59f
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:3] w4;
wire [0:3] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w0 = vec26ff;
assign v19a59f = w1;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 = vccca56;
assign w9 = vccca56;
assign w7 = w6;
assign w9 = w8;
v6bdcd9 v8e04d7 (
.vcc8c7c(w0),
.v651522(w2),
.v2cc41f(w4)
);
vafb28f vdbcc53 (
.va9ac17(w1),
.v515fe7(w3),
.v3c88fc(w5)
);
v370cd6 v732df5 (
.v2856c0(w2),
.v7891f9(w3),
.v6dda25(w6),
.vccca56(w8)
);
v370cd6 v21c6af (
.v2856c0(w4),
.v7891f9(w5),
.v6dda25(w7),
.vccca56(w9)
);
endmodule
//---------------------------------------------------
//-- Reg-x08
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg-x08: 8-bits register
//---------------------------------------------------
//---- Top entity
module v370cd6 (
input v6dda25,
input [3:0] v2856c0,
input vccca56,
output [3:0] v7891f9
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v2856c0;
assign v7891f9 = w7;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = vccca56;
assign w15 = vccca56;
assign w16 = vccca56;
assign w17 = vccca56;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
v22cb98 v1ba30c (
.v27dec4(w0),
.v4642b6(w2),
.ve4a668(w12),
.vd793aa(w16)
);
v22cb98 v38f79d (
.v27dec4(w1),
.v4642b6(w3),
.ve4a668(w13),
.vd793aa(w17)
);
v22cb98 v009467 (
.v27dec4(w4),
.v4642b6(w5),
.ve4a668(w11),
.vd793aa(w15)
);
vc4f23a vf2e2c0 (
.v3f8943(w0),
.v64d863(w1),
.vda577d(w4),
.v985fcb(w6),
.v4f1fd3(w8)
);
v84f0a1 v947047 (
.vee8a83(w2),
.v03aaf0(w3),
.vf8041d(w5),
.v11bca5(w7),
.vd84a57(w9)
);
v22cb98 v3a0f4c (
.v27dec4(w8),
.v4642b6(w9),
.ve4a668(w10),
.vd793aa(w14)
);
endmodule
//---------------------------------------------------
//-- Reg-x04
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg-x04: 4-bits register
//---------------------------------------------------
//---- Top entity
module v22cb98 #(
parameter v5462c0 = 0
) (
input ve4a668,
input v27dec4,
input vd793aa,
output v4642b6
);
localparam p1 = v5462c0;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w2 = ve4a668;
assign w3 = v27dec4;
assign v4642b6 = w5;
assign w6 = vd793aa;
assign w5 = w4;
va40d2f v9ff767 (
.v030ad0(w0),
.vb192d0(w3),
.v27dec4(w4),
.v2d3366(w6)
);
v053dc2 #(
.v71e305(p1)
) v89c757 (
.vf54559(w0),
.va4102a(w2),
.ve8318d(w4)
);
endmodule
//---------------------------------------------------
//-- 1-bit-reg
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg: 1-Bit register
//---------------------------------------------------
//---- Top entity
module va40d2f (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
assign v030ad0 = w0;
assign w1 = v2d3366;
assign w2 = v27dec4;
assign w3 = vb192d0;
vd0c4e5 v0f3fef (
.v030ad0(w0),
.v2d3366(w1),
.vb192d0(w2),
.v27dec4(w3)
);
endmodule
//---------------------------------------------------
//-- MuxF-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (1-bit channels). Fippled version
//---------------------------------------------------
//---- Top entity
module vd0c4e5 (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
assign v030ad0 = w0;
assign w2 = v2d3366;
assign w3 = v2d3366;
assign w6 = v27dec4;
assign w7 = vb192d0;
assign w3 = w2;
v873425 vaaee1f (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w4)
);
vba518e v569873 (
.vcbab45(w1),
.v3ca442(w2),
.v0e28cb(w6)
);
v3676a0 v1f00ae (
.v0e28cb(w3),
.vcbab45(w5)
);
vba518e vc8527f (
.vcbab45(w4),
.v3ca442(w5),
.v0e28cb(w7)
);
endmodule
//---------------------------------------------------
//-- Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (1-bit channels)
//---------------------------------------------------
//---- Top entity
module v9c1f69 (
input [7:0] vcc8c7c,
output [2:0] v1045ee,
output [4:0] v52d10b
);
wire [0:7] w0;
wire [0:4] w1;
wire [0:2] w2;
assign w0 = vcc8c7c;
assign v52d10b = w1;
assign v1045ee = w2;
v9c1f69_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Split-3-5
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Split-3-5: Split the 8-bits bus into two buses of 3 and 5 wires
//---------------------------------------------------
module v9c1f69_v9a2a06 (
input [7:0] i,
output [2:0] o1,
output [4:0] o0
);
assign o1 = i[7:5];
assign o0 = i[4:0];
endmodule
//---- Top entity
module v89d234 #(
parameter v422d28 = 0
) (
input v41eb95,
input [7:0] v39f831,
input vf892a0,
output [7:0] vb1c024
);
localparam p0 = v422d28;
wire [0:7] w1;
wire [0:7] w2;
wire w3;
wire w4;
assign vb1c024 = w1;
assign w2 = v39f831;
assign w3 = vf892a0;
assign w4 = v41eb95;
v89d234_v9148cb #(
.INI(p0)
) v9148cb (
.q(w1),
.d(w2),
.load(w3),
.clk(w4)
);
endmodule
//---------------------------------------------------
//-- Registro
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Registro de 8 bits
//---------------------------------------------------
module v89d234_v9148cb #(
parameter INI = 0
) (
input clk,
input [7:0] d,
input load,
output [7:0] q
);
localparam N = 8;
reg [N-1:0] q = INI;
always @(posedge clk)
if (load)
q <= d;
endmodule
//---- Top entity
module vffc517 #(
parameter vc5c8ea = 0
) (
output [7:0] va0aeac
);
localparam p0 = vc5c8ea;
wire [0:7] w1;
assign va0aeac = w1;
vffc517_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 8-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 8-bits generic constant (0-255)
//---------------------------------------------------
module vffc517_v465065 #(
parameter VALUE = 0
) (
output [7:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v1bbb5b (
input [7:0] v2a1cbe,
input [7:0] v9d7ae8,
input v2d3366,
output [7:0] v9d2a6a
);
wire [0:3] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:3] w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire [0:3] w10;
assign v9d2a6a = w1;
assign w2 = v2a1cbe;
assign w3 = v9d7ae8;
assign w8 = v2d3366;
assign w9 = v2d3366;
assign w9 = w8;
v952eda v54aed2 (
.v6833fd(w0),
.v54ac99(w7),
.v2d3366(w9),
.ve2616d(w10)
);
vafb28f v117a88 (
.v3c88fc(w0),
.va9ac17(w1),
.v515fe7(w4)
);
v6bdcd9 v9f32ae (
.vcc8c7c(w2),
.v651522(w5),
.v2cc41f(w7)
);
v6bdcd9 v9881c7 (
.vcc8c7c(w3),
.v651522(w6),
.v2cc41f(w10)
);
v952eda v34a43a (
.v6833fd(w4),
.v54ac99(w5),
.ve2616d(w6),
.v2d3366(w8)
);
endmodule
//---------------------------------------------------
//-- 8-bits-Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (8-bit channels)
//---------------------------------------------------
//---- Top entity
module v952eda (
input [3:0] v54ac99,
input [3:0] ve2616d,
input v2d3366,
output [3:0] v6833fd
);
wire w0;
wire w1;
wire w2;
wire [0:3] w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign v6833fd = w3;
assign w5 = ve2616d;
assign w6 = v54ac99;
assign w9 = v2d3366;
assign w10 = v2d3366;
assign w11 = v2d3366;
assign w12 = v2d3366;
assign w10 = w9;
assign w11 = w9;
assign w11 = w10;
assign w12 = w9;
assign w12 = w10;
assign w12 = w11;
vd0c4e5 v6d94c9 (
.v030ad0(w0),
.v2d3366(w11),
.v27dec4(w15),
.vb192d0(w17)
);
vd0c4e5 vebe465 (
.v030ad0(w1),
.v2d3366(w12),
.v27dec4(w16),
.vb192d0(w18)
);
vd0c4e5 ve1c21f (
.v030ad0(w2),
.v2d3366(w10),
.v27dec4(w13),
.vb192d0(w14)
);
v84f0a1 va44bdf (
.vee8a83(w0),
.v03aaf0(w1),
.vf8041d(w2),
.v11bca5(w3),
.vd84a57(w4)
);
vd0c4e5 v2ebff3 (
.v030ad0(w4),
.v27dec4(w7),
.vb192d0(w8),
.v2d3366(w9)
);
vc4f23a v3c3a57 (
.v985fcb(w5),
.v4f1fd3(w8),
.vda577d(w14),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a vd6d480 (
.v985fcb(w6),
.v4f1fd3(w7),
.vda577d(w13),
.v3f8943(w15),
.v64d863(w16)
);
endmodule
//---------------------------------------------------
//-- 4-bits-Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (4-bit channels)
//---------------------------------------------------
//---- Top entity
module v78be07 (
input [7:0] vcc8c7c,
output v2ce16c,
output [6:0] vdb77b6
);
wire [0:7] w0;
wire [0:6] w1;
wire w2;
assign w0 = vcc8c7c;
assign vdb77b6 = w1;
assign v2ce16c = w2;
v78be07_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Split-1-7
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Split-half: Split the 8-bits bus into two buses of 1 and 7 wires
//---------------------------------------------------
module v78be07_v9a2a06 (
input [7:0] i,
output o1,
output [6:0] o0
);
assign o1 = i[7];
assign o0 = i[6:0];
endmodule
//---- Top entity
module v4c1570 #(
parameter v573b2a = 0
) (
input v6dda25,
input v27dec4,
input v92a149,
output v4642b6
);
localparam p0 = v573b2a;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w5 = v6dda25;
assign v4642b6 = w6;
assign w8 = v27dec4;
assign w9 = v92a149;
assign w7 = w6;
v053dc2 #(
.v71e305(p0)
) v24b497 (
.vf54559(w1),
.va4102a(w5),
.ve8318d(w6)
);
vd0c4e5 vda4b54 (
.v030ad0(w1),
.v27dec4(w2),
.vb192d0(w3),
.v2d3366(w8)
);
vfebcfe v2141a0 (
.v9fb85f(w2)
);
vd0c4e5 v75d8ff (
.v030ad0(w3),
.v27dec4(w4),
.vb192d0(w7),
.v2d3366(w9)
);
vd30ca9 va595cf (
.v9fb85f(w4)
);
endmodule
//---------------------------------------------------
//-- RS-FF-set
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- RS-FF-set. RS Flip-flop with priority set
//---------------------------------------------------
//---- Top entity
module vda0861 #(
parameter vfffc23 = 0
) (
output [7:0] vffb58f
);
localparam p0 = vfffc23;
wire [0:7] w1;
assign vffb58f = w1;
vffc517 #(
.vc5c8ea(p0)
) v778577 (
.va0aeac(w1)
);
endmodule
//---------------------------------------------------
//-- 8bits-Value_0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 8bits constant value: 0
//---------------------------------------------------
//---- Top entity
module v876875 #(
parameter v001ed5 = 1
) (
input vd6bebe,
output v4642b6
);
localparam p1 = v001ed5;
wire w0;
wire w2;
wire w3;
assign v4642b6 = w2;
assign w3 = vd6bebe;
vd30ca9 v0ad98b (
.v9fb85f(w0)
);
v053dc2 #(
.v71e305(p1)
) v9c5dc5 (
.vf54559(w0),
.ve8318d(w2),
.va4102a(w3)
);
endmodule
//---------------------------------------------------
//-- start
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- start: Start signal: It goes from 1 to 0 when the system clock starts. 1 cycle pulse witch
//---------------------------------------------------
//---- Top entity
module v56885a #(
parameter v187a47 = 1
) (
input v5688a8,
input v6e1dd1,
output veabfb2,
output va9e2af
);
localparam p0 = v187a47;
wire w1;
wire w2;
wire w3;
wire w4;
assign w1 = v6e1dd1;
assign veabfb2 = w2;
assign va9e2af = w3;
assign w4 = v5688a8;
v56885a_v3140f5 #(
.SEG(p0)
) v3140f5 (
.start(w1),
.p(w2),
.tic(w3),
.clk(w4)
);
endmodule
//---------------------------------------------------
//-- timer-sec
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Temporizador en segundos. La señal p está activa durante el tiempo indicado. Por tic se emite un tic al finalizar
//---------------------------------------------------
module v56885a_v3140f5 #(
parameter SEG = 0
) (
input clk,
input start,
output p,
output tic
);
//localparam SEC;
//-- Constante para dividir y obtener una frecuencia de 1Hz
localparam M = 12000000;
//-- Calcular el numero de bits para almacenar M
localparam N = $clog2(M);
//-- Cable de reset para el corazon
wire rst_heart;
//-- Overflow del temporizador del corazon
wire ov_heart;
//-- Habilitacion del corazon
wire ena;
//-- Tics del corazon
wire tic_heart;
//-- Contador del corazon
reg [N-1:0] heart=0;
always @(posedge clk)
if (rst_heart)
heart <= 0;
else
heart <= heart + 1;
//-- Overflow del contador
assign ov_heart = (heart == M-1);
//-- La salida del corazon es la señal de overflow
assign tic_heart = ov_heart;
//-- Reset del corazon
assign rst_heart =~ena | ov_heart;
//--------------------------------------------
//-- Contador de tics
//--------------------------------------------
reg [7:0] counter = 0;
//-- Overflow del contador
wire ov;
//-- Señal de reset del contador
wire rst;
always @(posedge clk)
if (rst)
counter <= 0;
else
if (tic_heart)
counter <= counter + 1;
//-- Evento: cuenta máxima de tics alcanzada
assign ov = (counter == SEG);
//---------------------------------------
//-- Biestable de estado del timer
//-- 0: Apagado
//-- 1: Funcionando
reg q = 0;
always @(posedge clk)
if (start)
q <= 1'b1;
else if (rst)
q<=1'b0;
//-- Lógica de reset
//En función de la entrada, el estado y
// el overflow se inicializa el contador y
// se habilita el corazón de tics
assign rst = ~q | ov | start;
assign ena = ~rst;
//-- Salida de pulso
assign p = q;
//-- Salida de tic
//-- Saca un tic cuando ha finalizado la cuenta
assign tic = ov;
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll200M.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll200M (
inclk0,
c0);
input inclk0;
output c0;
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll200M",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll200M.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll200M.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll200M.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll200M.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll200M.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll200M.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll200M_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll200M_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Module: WB_SPI_Flash.v
// Description: Wishbone SPI Master core.
// --------------------------------------------------------------------
// --------------------------------------------------------------------
module WB_SPI_Flash(
input wb_clk_i, // Wishbone slave interface
input wb_rst_i,
input [15:0] wb_dat_i,
output reg [7:0] wb_dat_o,
input wb_we_i,
input [1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
output reg sclk, // Serial pad signal
input miso,
output reg mosi,
output reg sels, // Flash Select
output reg mcus // MCU select
);
wire op; // Operator
wire start; // Start indication
wire send; // End indication
reg st;
reg [7:0] tr;
reg [7:0] sft;
reg [1:0] clk_div;
assign op = wb_stb_i & wb_cyc_i;
assign start = !st & op;
assign send = start & wb_we_i & wb_sel_i[0];
always @(posedge wb_clk_i) clk_div <= clk_div - 2'd1;
always @(posedge wb_clk_i) sclk <= wb_rst_i ? 1'b1 : (clk_div[0] ? sclk : !(op & clk_div[1]));
always @(posedge wb_clk_i) wb_ack_o <= wb_rst_i ? 1'b0 : (wb_ack_o ? 1'b0 : (sft[0] && clk_div == 2'b00));
always @(negedge wb_clk_i) sels <= wb_rst_i ? 1'b1 : ((op & wb_we_i & wb_sel_i[1]) ? wb_dat_i[8] : sels);
always @(negedge wb_clk_i) mcus <= wb_rst_i ? 1'b1 : ((op & wb_we_i & wb_sel_i[1]) ? wb_dat_i[9] : mcus);
always @(posedge wb_clk_i) mosi <= wb_rst_i ? 1'b1 : (clk_div == 2'b10 ? (send ? wb_dat_i[7] : tr[7]) : mosi);
always @(posedge wb_clk_i) tr <= wb_rst_i ? 8'hff : (clk_div == 2'b10 ? { (send ? wb_dat_i[6:0] : tr[6:0]), 1'b1 } : tr);
always @(posedge wb_clk_i) wb_dat_o <= wb_rst_i ? 8'h0 : ((op && clk_div == 2'b0) ? { wb_dat_o[6:0], miso } : wb_dat_o);
always @(posedge wb_clk_i) st <= wb_rst_i ? 1'b0 : (st ? !sft[0] : op && clk_div == 2'b10);
always @(posedge wb_clk_i) sft <= wb_rst_i ? 8'h0 : (clk_div == 2'b10 ? { start, sft[7:1] } : sft);
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
//----------------------------------------------------------------------------
//-- Memoria RAM genérica
//------------------------------------------
//-- (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Memoria con los siguientes parametros:
//-- * AW: Numero de bits de las direcciones
//-- * DW: Numero de bits de los datos
//-- * ROMFILE: Fichero a usar para cargar la memoria
//--
//-- Con este componente podemos hacer memorias ram de cualquier tamano
//----------------------------------------------------------------------------
module genram #( //-- Parametros
parameter AW = 9, //-- Bits de las direcciones (Adress width)
parameter DW = 12) //-- Bits de los datos (Data witdh)
( //-- Puertos
input clk, //-- Señal de reloj global
input cs, //-- Chip select
input wire [AW-1: 0] addr, //-- Direcciones
input wire rw, //-- Modo lectura (1) o escritura (0)
input wire [DW-1: 0] data_in, //-- Dato de entrada
output reg [DW-1: 0] data_out); //-- Dato a escribir
//-- Parametro: Nombre del fichero con el contenido de la RAM
parameter ROMFILE = "";
//-- Calcular el numero de posiciones totales de memoria
localparam NPOS = 2 ** AW;
//-- Memoria
reg [DW-1: 0] ram [0: NPOS-1];
//-- Lectura de la memoria
//-- Solo si el chip select esta activado!
always @(posedge clk) begin
if (cs & rw == 1)
data_out <= ram[addr];
end
//-- Escritura en la memoria
//-- Solo si el chip select esta activado
always @(posedge clk) begin
if (cs & rw == 0)
ram[addr] <= data_in;
end
//-- Cargar en la memoria el fichero ROMFILE
//-- Los valores deben estan dados en hexadecimal
initial begin
if (ROMFILE) $readmemh(ROMFILE, ram);
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ccx_arbc.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
// Code start here
//
module ccx_arbc(/*AUTOARG*/
// Outputs
scan_out, ccx_dest_data_rdy_x, arb_src5_grant_a, arb_src4_grant_a,
arb_src3_grant_a, arb_src2_grant_a, arb_src1_grant_a,
arb_src0_grant_a, arb_dp_grant_a, arb_dp_q0_hold_a,
arb_dp_qsel0_a, arb_dp_qsel1_a, arb_dp_shift_x,
// Inputs
src5_arb_req_q, src5_arb_atom_q, src4_arb_req_q, src4_arb_atom_q,
src3_arb_req_q, src3_arb_atom_q, src2_arb_req_q, src2_arb_atom_q,
src1_arb_req_q, src1_arb_atom_q, src0_arb_req_q, src0_arb_atom_q,
se, scan_in, reset_l, rclk, adbginit_l
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output arb_src0_grant_a; // From ccx_arb of ccx_arb.v
output arb_src1_grant_a; // From ccx_arb of ccx_arb.v
output arb_src2_grant_a; // From ccx_arb of ccx_arb.v
output arb_src3_grant_a; // From ccx_arb of ccx_arb.v
output arb_src4_grant_a; // From ccx_arb of ccx_arb.v
output arb_src5_grant_a; // From ccx_arb of ccx_arb.v
output ccx_dest_data_rdy_x; // From ccx_arb of ccx_arb.v
output scan_out; // From ccx_arb of ccx_arb.v
// End of automatics
output [5:0] arb_dp_grant_a;
output [5:0] arb_dp_q0_hold_a;
output [5:0] arb_dp_qsel0_a;
output [5:0] arb_dp_qsel1_a;
output [5:0] arb_dp_shift_x;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To ccx_arb of ccx_arb.v
input rclk; // To ccx_arb of ccx_arb.v
input reset_l; // To ccx_arb of ccx_arb.v
input scan_in; // To ccx_arb of ccx_arb.v
input se; // To ccx_arb of ccx_arb.v
input src0_arb_atom_q; // To ccx_arb of ccx_arb.v
input src0_arb_req_q; // To ccx_arb of ccx_arb.v
input src1_arb_atom_q; // To ccx_arb of ccx_arb.v
input src1_arb_req_q; // To ccx_arb of ccx_arb.v
input src2_arb_atom_q; // To ccx_arb of ccx_arb.v
input src2_arb_req_q; // To ccx_arb of ccx_arb.v
input src3_arb_atom_q; // To ccx_arb of ccx_arb.v
input src3_arb_req_q; // To ccx_arb of ccx_arb.v
input src4_arb_atom_q; // To ccx_arb of ccx_arb.v
input src4_arb_req_q; // To ccx_arb of ccx_arb.v
input src5_arb_atom_q; // To ccx_arb of ccx_arb.v
input src5_arb_req_q; // To ccx_arb of ccx_arb.v
// End of automatics
wire src6_arb_atom_q ;
wire src6_arb_req_q ;
wire src7_arb_atom_q ;
wire src7_arb_req_q ;
wire stall1_q ;
wire stall2_q ;
wire [1:0] sinka;
wire [1:0] sinkb;
wire [1:0] sinkc;
wire [1:0] sinkd;
wire [1:0] sinke;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
assign src6_arb_atom_q = 1'b0;
assign src6_arb_req_q = 1'b0;
assign src7_arb_atom_q = 1'b0;
assign src7_arb_req_q = 1'b0;
assign stall1_q = 1'b0;
assign stall2_q = 1'b0;
// commented out - backend does not like this
// sink #(2) sink1(.in (sinka[1:0]));
// sink #(2) sink2(.in (sinkb[1:0]));
// sink #(2) sink3(.in (sinkc[1:0]));
// sink #(2) sink4(.in (sinkd[1:0]));
// sink #(2) sink5(.in (sinke[1:0]));
/*
ccx_arb AUTO_TEMPLATE(
.ccx_dest_atom_x (),
.arb_dp_grant_a ({sinka[0], sinka[1],arb_dp_grant_a[5:0]}),
.arb_dp_q0_hold_a ({sinkb[0], sinkb[1],arb_dp_q0_hold_a[5:0]}),
.arb_dp_qsel0_a ({sinkc[0], sinkc[1],arb_dp_qsel0_a[5:0]}),
.arb_dp_qsel1_a ({sinkd[0], sinkd[1],arb_dp_qsel1_a[5:0]}),
.arb_dp_shift_x ({sinke[0], sinke[1],arb_dp_shift_x[5:0]}),
.arb_src6_grant_a (),
.arb_src7_grant_a ());
*/
ccx_arb ccx_arb(/*AUTOINST*/
// Outputs
.arb_dp_grant_a ({sinka[0], sinka[1],arb_dp_grant_a[5:0]}), // Templated
.arb_dp_q0_hold_a ({sinkb[0], sinkb[1],arb_dp_q0_hold_a[5:0]}), // Templated
.arb_dp_qsel0_a ({sinkc[0], sinkc[1],arb_dp_qsel0_a[5:0]}), // Templated
.arb_dp_qsel1_a ({sinkd[0], sinkd[1],arb_dp_qsel1_a[5:0]}), // Templated
.arb_dp_shift_x ({sinke[0], sinke[1],arb_dp_shift_x[5:0]}), // Templated
.arb_src0_grant_a (arb_src0_grant_a),
.arb_src1_grant_a (arb_src1_grant_a),
.arb_src2_grant_a (arb_src2_grant_a),
.arb_src3_grant_a (arb_src3_grant_a),
.arb_src4_grant_a (arb_src4_grant_a),
.arb_src5_grant_a (arb_src5_grant_a),
.arb_src6_grant_a (), // Templated
.arb_src7_grant_a (), // Templated
.ccx_dest_atom_x (), // Templated
.ccx_dest_data_rdy_x (ccx_dest_data_rdy_x),
.scan_out (scan_out),
// Inputs
.adbginit_l (adbginit_l),
.rclk (rclk),
.reset_l (reset_l),
.src0_arb_atom_q (src0_arb_atom_q),
.src0_arb_req_q (src0_arb_req_q),
.src1_arb_atom_q (src1_arb_atom_q),
.src1_arb_req_q (src1_arb_req_q),
.src2_arb_atom_q (src2_arb_atom_q),
.src2_arb_req_q (src2_arb_req_q),
.src3_arb_atom_q (src3_arb_atom_q),
.src3_arb_req_q (src3_arb_req_q),
.src4_arb_atom_q (src4_arb_atom_q),
.src4_arb_req_q (src4_arb_req_q),
.src5_arb_atom_q (src5_arb_atom_q),
.src5_arb_req_q (src5_arb_req_q),
.src6_arb_atom_q (src6_arb_atom_q),
.src6_arb_req_q (src6_arb_req_q),
.src7_arb_atom_q (src7_arb_atom_q),
.src7_arb_req_q (src7_arb_req_q),
.stall1_q (stall1_q),
.stall2_q (stall2_q),
.scan_in (scan_in),
.se (se));
endmodule // ccx_arb
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.in (in[31:0]));
Test2 test2 (/*AUTOINST*/
// Inputs
.clk (clk),
.in (in[31:0]));
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Inputs
clk, in
);
input clk;
input [31:0] in;
reg [31:0] dly0;
reg [31:0] dly1;
reg [31:0] dly2;
reg [31:0] dly3;
// If called in an assertion, sequence, or property, the appropriate clocking event.
// Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit.
// Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used.
// Otherwise, if called in a procedure, the inferred clock
// Otherwise, default clocking
always @(posedge clk) begin
dly0 <= in;
dly1 <= dly0;
dly2 <= dly1;
dly3 <= dly2;
// $past(expression, ticks, expression, clocking)
// In clock expression
if (dly0 != $past(in)) $stop;
if (dly0 != $past(in,1)) $stop;
if (dly1 != $past(in,2)) $stop;
end
assert property (@(posedge clk) dly0 == $past(in));
endmodule
module Test2 (/*AUTOARG*/
// Inputs
clk, in
);
input clk;
input [31:0] in;
reg [31:0] dly0;
reg [31:0] dly1;
default clocking @(posedge clk); endclocking
assert property (@(posedge clk) dly1 == $past(in, 2));
endmodule
|
// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.1.0.96
// Netlist written on Mon Jun 02 21:58:34 2014
//
// Verilog Description of module Sec6_Top
//
module Sec6_Top (ADCData, reset_n, sel, segments) /* synthesis syn_module_defined=1 */ ; // c:/lscc/diamond/3.1_x64/bin/nt64/lab6_finaldesign/section6_top.v(1[8:16])
input [7:0]ADCData; // c:/lscc/diamond/3.1_x64/bin/nt64/lab6_finaldesign/section6_top.v(2[14:21])
input reset_n; // c:/lscc/diamond/3.1_x64/bin/nt64/lab6_finaldesign/section6_top.v(3[8:15])
output [2:0]sel; // c:/lscc/diamond/3.1_x64/bin/nt64/lab6_finaldesign/section6_top.v(4[15:18])
output [6:0]segments; // c:/lscc/diamond/3.1_x64/bin/nt64/lab6_finaldesign/section6_top.v(5[15:23])
wire GND_net; // c:/lscc/diamond/3.1_x64/bin/nt64/lab6_finaldesign/section6_top.v(11[13:20])
wire reset_n_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab6_finaldesign/section6_top.v(3[8:15])
wire [2:0]sel_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab6_finaldesign/section6_top.v(4[15:18])
wire clk; // c:/lscc/diamond/3.1_x64/bin/nt64/lab6_finaldesign/section6_top.v(9[7:10])
wire clk_slow; // c:/lscc/diamond/3.1_x64/bin/nt64/lab6_finaldesign/section6_top.v(10[7:15])
wire VCC_net; // c:/lscc/diamond/3.1_x64/bin/nt64/lab6_finaldesign/section6_top.v(11[13:20])
VHI i5 (.Z(VCC_net));
OB sel_pad_1 (.I(sel_c[1]), .O(sel[1]));
OSCH osc_int (.STDBY(GND_net), .OSC(clk)) /* synthesis syn_instantiated=1 */ ;
defparam osc_int.NOM_FREQ = "2.08";
VLO i1 (.Z(GND_net));
PUR PUR_INST (.PUR(VCC_net));
defparam PUR_INST.RST_PULSE = 1;
OB sel_pad_2 (.I(sel_c[2]), .O(sel[2]));
GSR GSR_INST (.GSR(reset_n_c));
clock_counter counter_1 (.clk_slow(clk_slow), .clk(clk), .GND_net(GND_net)) /* synthesis syn_module_defined=1 */ ;
Sec6_SM FSM_1 (.sel({sel_c}), .clk_slow(clk_slow)) /* synthesis syn_module_defined=1 */ ;
OB sel_pad_0 (.I(sel_c[0]), .O(sel[0]));
OB segments_pad_6 (.I(GND_net), .O(segments[6]));
OB segments_pad_5 (.I(GND_net), .O(segments[5]));
OB segments_pad_4 (.I(GND_net), .O(segments[4]));
OB segments_pad_3 (.I(VCC_net), .O(segments[3]));
OB segments_pad_2 (.I(VCC_net), .O(segments[2]));
OB segments_pad_1 (.I(VCC_net), .O(segments[1]));
OB segments_pad_0 (.I(VCC_net), .O(segments[0]));
IB reset_n_pad (.I(reset_n), .O(reset_n_c));
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box.
//
//
// Verilog Description of module clock_counter
//
module clock_counter (clk_slow, clk, GND_net) /* synthesis syn_module_defined=1 */ ;
output clk_slow;
input clk;
input GND_net;
wire [15:0]count; // c:/lscc/diamond/3.1_x64/bin/nt64/lab6_finaldesign/section6_finaldesign/source/clock_counter.v(8[14:19])
wire n24, n26;
wire [14:0]n66;
wire n104, n8, n14, n112, n8_adj_1, n110, n109, n108, n107,
n106, n105;
LUT4 i15_2_lut (.A(clk_slow), .B(n24), .Z(n26)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
defparam i15_2_lut.init = 16'h6666;
FD1S3IX dff_11_31_32__i1 (.D(n66[0]), .CK(clk), .CD(n24), .Q(count[0]));
defparam dff_11_31_32__i1.GSR = "ENABLED";
FD1S3IX dff_11_31_32__i15 (.D(n66[14]), .CK(clk), .CD(n24), .Q(count[14]));
defparam dff_11_31_32__i15.GSR = "ENABLED";
FD1S3AX clk_o_13 (.D(n26), .CK(clk), .Q(clk_slow));
defparam clk_o_13.GSR = "ENABLED";
FD1S3IX dff_11_31_32__i14 (.D(n66[13]), .CK(clk), .CD(n24), .Q(count[13]));
defparam dff_11_31_32__i14.GSR = "ENABLED";
FD1S3IX dff_11_31_32__i13 (.D(n66[12]), .CK(clk), .CD(n24), .Q(count[12]));
defparam dff_11_31_32__i13.GSR = "ENABLED";
FD1S3IX dff_11_31_32__i12 (.D(n66[11]), .CK(clk), .CD(n24), .Q(count[11]));
defparam dff_11_31_32__i12.GSR = "ENABLED";
FD1S3IX dff_11_31_32__i11 (.D(n66[10]), .CK(clk), .CD(n24), .Q(count[10]));
defparam dff_11_31_32__i11.GSR = "ENABLED";
FD1S3IX dff_11_31_32__i10 (.D(n66[9]), .CK(clk), .CD(n24), .Q(count[9]));
defparam dff_11_31_32__i10.GSR = "ENABLED";
FD1S3IX dff_11_31_32__i9 (.D(n66[8]), .CK(clk), .CD(n24), .Q(count[8]));
defparam dff_11_31_32__i9.GSR = "ENABLED";
FD1S3IX dff_11_31_32__i8 (.D(n66[7]), .CK(clk), .CD(n24), .Q(count[7]));
defparam dff_11_31_32__i8.GSR = "ENABLED";
FD1S3IX dff_11_31_32__i7 (.D(n66[6]), .CK(clk), .CD(n24), .Q(count[6]));
defparam dff_11_31_32__i7.GSR = "ENABLED";
FD1S3IX dff_11_31_32__i6 (.D(n66[5]), .CK(clk), .CD(n24), .Q(count[5]));
defparam dff_11_31_32__i6.GSR = "ENABLED";
FD1S3IX dff_11_31_32__i5 (.D(n66[4]), .CK(clk), .CD(n24), .Q(count[4]));
defparam dff_11_31_32__i5.GSR = "ENABLED";
FD1S3IX dff_11_31_32__i4 (.D(n66[3]), .CK(clk), .CD(n24), .Q(count[3]));
defparam dff_11_31_32__i4.GSR = "ENABLED";
FD1S3IX dff_11_31_32__i3 (.D(n66[2]), .CK(clk), .CD(n24), .Q(count[2]));
defparam dff_11_31_32__i3.GSR = "ENABLED";
FD1S3IX dff_11_31_32__i2 (.D(n66[1]), .CK(clk), .CD(n24), .Q(count[1]));
defparam dff_11_31_32__i2.GSR = "ENABLED";
CCU2D dff_11_31_32_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net),
.D0(GND_net), .A1(count[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net),
.COUT(n104), .S1(n66[0]));
defparam dff_11_31_32_add_4_1.INIT0 = 16'hF000;
defparam dff_11_31_32_add_4_1.INIT1 = 16'h0555;
defparam dff_11_31_32_add_4_1.INJECT1_0 = "NO";
defparam dff_11_31_32_add_4_1.INJECT1_1 = "NO";
LUT4 i50_4_lut (.A(count[0]), .B(count[3]), .C(count[2]), .D(count[1]),
.Z(n8)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
defparam i50_4_lut.init = 16'hfcec;
LUT4 i49_4_lut (.A(count[5]), .B(count[6]), .C(count[4]), .D(n8),
.Z(n14)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;
defparam i49_4_lut.init = 16'heccc;
LUT4 i3_4_lut (.A(n14), .B(count[9]), .C(count[8]), .D(count[7]),
.Z(n112)) /* synthesis lut_function=(A (B (C (D)))) */ ;
defparam i3_4_lut.init = 16'h8000;
LUT4 i3_3_lut (.A(count[13]), .B(count[12]), .C(count[10]), .Z(n8_adj_1)) /* synthesis lut_function=(A+(B+(C))) */ ;
defparam i3_3_lut.init = 16'hfefe;
LUT4 i48_4_lut (.A(count[11]), .B(count[14]), .C(n8_adj_1), .D(n112),
.Z(n24)) /* synthesis lut_function=(A (B)+!A (B (C+(D)))) */ ;
defparam i48_4_lut.init = 16'hccc8;
CCU2D dff_11_31_32_add_4_15 (.A0(count[13]), .B0(GND_net), .C0(GND_net),
.D0(GND_net), .A1(count[14]), .B1(GND_net), .C1(GND_net),
.D1(GND_net), .CIN(n110), .S0(n66[13]), .S1(n66[14]));
defparam dff_11_31_32_add_4_15.INIT0 = 16'hfaaa;
defparam dff_11_31_32_add_4_15.INIT1 = 16'hfaaa;
defparam dff_11_31_32_add_4_15.INJECT1_0 = "NO";
defparam dff_11_31_32_add_4_15.INJECT1_1 = "NO";
CCU2D dff_11_31_32_add_4_13 (.A0(count[11]), .B0(GND_net), .C0(GND_net),
.D0(GND_net), .A1(count[12]), .B1(GND_net), .C1(GND_net),
.D1(GND_net), .CIN(n109), .COUT(n110), .S0(n66[11]), .S1(n66[12]));
defparam dff_11_31_32_add_4_13.INIT0 = 16'hfaaa;
defparam dff_11_31_32_add_4_13.INIT1 = 16'hfaaa;
defparam dff_11_31_32_add_4_13.INJECT1_0 = "NO";
defparam dff_11_31_32_add_4_13.INJECT1_1 = "NO";
CCU2D dff_11_31_32_add_4_11 (.A0(count[9]), .B0(GND_net), .C0(GND_net),
.D0(GND_net), .A1(count[10]), .B1(GND_net), .C1(GND_net),
.D1(GND_net), .CIN(n108), .COUT(n109), .S0(n66[9]), .S1(n66[10]));
defparam dff_11_31_32_add_4_11.INIT0 = 16'hfaaa;
defparam dff_11_31_32_add_4_11.INIT1 = 16'hfaaa;
defparam dff_11_31_32_add_4_11.INJECT1_0 = "NO";
defparam dff_11_31_32_add_4_11.INJECT1_1 = "NO";
CCU2D dff_11_31_32_add_4_9 (.A0(count[7]), .B0(GND_net), .C0(GND_net),
.D0(GND_net), .A1(count[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net),
.CIN(n107), .COUT(n108), .S0(n66[7]), .S1(n66[8]));
defparam dff_11_31_32_add_4_9.INIT0 = 16'hfaaa;
defparam dff_11_31_32_add_4_9.INIT1 = 16'hfaaa;
defparam dff_11_31_32_add_4_9.INJECT1_0 = "NO";
defparam dff_11_31_32_add_4_9.INJECT1_1 = "NO";
CCU2D dff_11_31_32_add_4_7 (.A0(count[5]), .B0(GND_net), .C0(GND_net),
.D0(GND_net), .A1(count[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net),
.CIN(n106), .COUT(n107), .S0(n66[5]), .S1(n66[6]));
defparam dff_11_31_32_add_4_7.INIT0 = 16'hfaaa;
defparam dff_11_31_32_add_4_7.INIT1 = 16'hfaaa;
defparam dff_11_31_32_add_4_7.INJECT1_0 = "NO";
defparam dff_11_31_32_add_4_7.INJECT1_1 = "NO";
CCU2D dff_11_31_32_add_4_5 (.A0(count[3]), .B0(GND_net), .C0(GND_net),
.D0(GND_net), .A1(count[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net),
.CIN(n105), .COUT(n106), .S0(n66[3]), .S1(n66[4]));
defparam dff_11_31_32_add_4_5.INIT0 = 16'hfaaa;
defparam dff_11_31_32_add_4_5.INIT1 = 16'hfaaa;
defparam dff_11_31_32_add_4_5.INJECT1_0 = "NO";
defparam dff_11_31_32_add_4_5.INJECT1_1 = "NO";
CCU2D dff_11_31_32_add_4_3 (.A0(count[1]), .B0(GND_net), .C0(GND_net),
.D0(GND_net), .A1(count[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net),
.CIN(n104), .COUT(n105), .S0(n66[1]), .S1(n66[2]));
defparam dff_11_31_32_add_4_3.INIT0 = 16'hfaaa;
defparam dff_11_31_32_add_4_3.INIT1 = 16'hfaaa;
defparam dff_11_31_32_add_4_3.INJECT1_0 = "NO";
defparam dff_11_31_32_add_4_3.INJECT1_1 = "NO";
endmodule
//
// Verilog Description of module Sec6_SM
//
module Sec6_SM (sel, clk_slow) /* synthesis syn_module_defined=1 */ ;
output [2:0]sel;
input clk_slow;
wire [3:0]n27;
LUT4 i1_3_lut (.A(sel[2]), .B(n27[1]), .C(n27[2]), .Z(sel[0])) /* synthesis lut_function=(!(A+!(B+(C)))) */ ;
defparam i1_3_lut.init = 16'h5454;
FD1S3AX state_FSM_i3 (.D(n27[2]), .CK(clk_slow), .Q(sel[2]));
defparam state_FSM_i3.GSR = "ENABLED";
LUT4 i64_2_lut (.A(sel[2]), .B(n27[2]), .Z(sel[1])) /* synthesis lut_function=(!(A+!(B))) */ ;
defparam i64_2_lut.init = 16'h4444;
FD1S3AX state_FSM_i2 (.D(n27[1]), .CK(clk_slow), .Q(n27[2]));
defparam state_FSM_i2.GSR = "ENABLED";
FD1S3AX state_FSM_i1 (.D(n27[0]), .CK(clk_slow), .Q(n27[1]));
defparam state_FSM_i1.GSR = "ENABLED";
FD1S3AY state_FSM_i0 (.D(sel[2]), .CK(clk_slow), .Q(n27[0]));
defparam state_FSM_i0.GSR = "ENABLED";
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__HA_0_V
`define SKY130_FD_SC_LP__HA_0_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ha_0 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ha_0 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__HA_0_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_k7_vivado_pipe_clock.v
// Version : 3.3
//------------------------------------------------------------------------------
// Filename : pipe_clock.v
// Description : PIPE Clock Module for 7 Series Transceiver
// Version : 15.3
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Clock Module -------------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_k7_vivado_pipe_clock #
(
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_CLK_SHARING_EN= "FALSE", // Enable Clock Sharing
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency
parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency
parameter PCIE_OOBCLK_MODE = 1, // PCIe oob clock mode
parameter PCIE_DEBUG_MODE = 0 // PCIe Debug mode
)
(
//---------- Input -------------------------------------
input CLK_CLK,
input CLK_TXOUTCLK,
input [PCIE_LANE-1:0] CLK_RXOUTCLK_IN,
input CLK_RST_N,
input [PCIE_LANE-1:0] CLK_PCLK_SEL,
input [PCIE_LANE-1:0] CLK_PCLK_SEL_SLAVE,
input CLK_GEN3,
//---------- Output ------------------------------------
output CLK_PCLK,
output CLK_PCLK_SLAVE,
output CLK_RXUSRCLK,
output [PCIE_LANE-1:0] CLK_RXOUTCLK_OUT,
output CLK_DCLK,
output CLK_OOBCLK,
output CLK_USERCLK1,
output CLK_USERCLK2,
output CLK_MMCM_LOCK
);
//---------- Select Clock Divider ----------------------
localparam DIVCLK_DIVIDE = (PCIE_REFCLK_FREQ == 2) ? 1 :
(PCIE_REFCLK_FREQ == 1) ? 1 : 1;
localparam CLKFBOUT_MULT_F = (PCIE_REFCLK_FREQ == 2) ? 4 :
(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
localparam CLKIN1_PERIOD = (PCIE_REFCLK_FREQ == 2) ? 4 :
(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
localparam CLKOUT0_DIVIDE_F = 8;
localparam CLKOUT1_DIVIDE = 4;
localparam CLKOUT2_DIVIDE = (PCIE_USERCLK1_FREQ == 5) ? 2 :
(PCIE_USERCLK1_FREQ == 4) ? 4 :
(PCIE_USERCLK1_FREQ == 3) ? 8 :
(PCIE_USERCLK1_FREQ == 1) ? 32 : 16;
localparam CLKOUT3_DIVIDE = (PCIE_USERCLK2_FREQ == 5) ? 2 :
(PCIE_USERCLK2_FREQ == 4) ? 4 :
(PCIE_USERCLK2_FREQ == 3) ? 8 :
(PCIE_USERCLK2_FREQ == 1) ? 32 : 16;
localparam CLKOUT4_DIVIDE = 20;
localparam PCIE_GEN1_MODE = 1'b1; // PCIe link speed is GEN1 only
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_slave_reg1 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1 = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_slave_reg2 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2 = 1'd0;
//---------- Internal Signals --------------------------
wire refclk;
wire mmcm_fb;
wire clk_125mhz;
wire clk_125mhz_buf;
wire clk_250mhz;
wire userclk1;
wire userclk2;
wire oobclk;
(* dont_touch = "true" *)reg pclk_sel = 1'd0;
reg pclk_sel_slave = 1'd0;
//---------- Output Registers --------------------------
wire pclk_1;
wire pclk;
wire userclk1_1;
wire userclk2_1;
wire mmcm_lock;
//---------- Generate Per-Lane Signals -----------------
genvar i; // Index for per-lane signals
//---------- Input FF ----------------------------------------------------------
always @ (posedge pclk)
begin
if (!CLK_RST_N)
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= {PCIE_LANE{1'd0}};
pclk_sel_slave_reg1 <= {PCIE_LANE{1'd0}};
gen3_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= {PCIE_LANE{1'd0}};
pclk_sel_slave_reg2 <= {PCIE_LANE{1'd0}};
gen3_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= CLK_PCLK_SEL;
pclk_sel_slave_reg1 <= CLK_PCLK_SEL_SLAVE;
gen3_reg1 <= CLK_GEN3;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= pclk_sel_reg1;
pclk_sel_slave_reg2 <= pclk_sel_slave_reg1;
gen3_reg2 <= gen3_reg1;
end
end
//---------- Select Reference clock or TXOUTCLK --------------------------------
generate if ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3))
begin : refclk_i
//---------- Select Reference Clock ----------------------------------------
BUFG refclk_i
(
//---------- Input -------------------------------------
.I (CLK_CLK),
//---------- Output ------------------------------------
.O (refclk)
);
end
else
begin : txoutclk_i
//---------- Select TXOUTCLK -----------------------------------------------
BUFG txoutclk_i
(
//---------- Input -------------------------------------
.I (CLK_TXOUTCLK),
//---------- Output ------------------------------------
.O (refclk)
);
end
endgenerate
//---------- MMCM --------------------------------------------------------------
MMCME2_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (CLKOUT0_DIVIDE_F),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
.CLKOUT4_PHASE (0.000),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT4_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (CLKIN1_PERIOD),
.REF_JITTER1 (0.010)
)
mmcm_i
(
//---------- Input ------------------------------------
.CLKIN1 (refclk),
.CLKIN2 (1'd0), // not used, comment out CLKIN2 if it cause implementation issues
//.CLKIN2 (refclk), // not used, comment out CLKIN2 if it cause implementation issues
.CLKINSEL (1'd1),
.CLKFBIN (mmcm_fb),
.RST (!CLK_RST_N),
.PWRDWN (1'd0),
//---------- Output ------------------------------------
.CLKFBOUT (mmcm_fb),
.CLKFBOUTB (),
.CLKOUT0 (clk_125mhz),
.CLKOUT0B (),
.CLKOUT1 (clk_250mhz),
.CLKOUT1B (),
.CLKOUT2 (userclk1),
.CLKOUT2B (),
.CLKOUT3 (userclk2),
.CLKOUT3B (),
.CLKOUT4 (oobclk),
.CLKOUT5 (),
.CLKOUT6 (),
.LOCKED (mmcm_lock),
//---------- Dynamic Reconfiguration -------------------
.DCLK ( 1'd0),
.DADDR ( 7'd0),
.DEN ( 1'd0),
.DWE ( 1'd0),
.DI (16'd0),
.DO (),
.DRDY (),
//---------- Dynamic Phase Shift -----------------------
.PSCLK (1'd0),
.PSEN (1'd0),
.PSINCDEC (1'd0),
.PSDONE (),
//---------- Status ------------------------------------
.CLKINSTOPPED (),
.CLKFBSTOPPED ()
);
//---------- Select PCLK MUX ---------------------------------------------------
generate if (PCIE_LINK_SPEED != 1)
begin : pclk_i1_bufgctrl
//---------- PCLK Mux ----------------------------------
BUFGCTRL pclk_i1
(
//---------- Input ---------------------------------
.CE0 (1'd1),
.CE1 (1'd1),
.I0 (clk_125mhz),
.I1 (clk_250mhz),
.IGNORE0 (1'd0),
.IGNORE1 (1'd0),
.S0 (~pclk_sel),
.S1 ( pclk_sel),
//---------- Output --------------------------------
.O (pclk_1)
);
end
else
//---------- Select PCLK Buffer ------------------------
begin : pclk_i1_bufg
//---------- PCLK Buffer -------------------------------
BUFG pclk_i1
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (clk_125mhz_buf)
);
assign pclk_1 = clk_125mhz_buf;
end
endgenerate
//---------- Select PCLK MUX for Slave---------------------------------------------------
generate if(PCIE_CLK_SHARING_EN == "FALSE")
//---------- PCLK MUX for Slave------------------//
begin : pclk_slave_disable
assign CLK_PCLK_SLAVE = 1'b0;
end
else if (PCIE_LINK_SPEED != 1)
begin : pclk_slave_bufgctrl
//---------- PCLK Mux ----------------------------------
BUFGCTRL pclk_slave
(
//---------- Input ---------------------------------
.CE0 (1'd1),
.CE1 (1'd1),
.I0 (clk_125mhz),
.I1 (clk_250mhz),
.IGNORE0 (1'd0),
.IGNORE1 (1'd0),
.S0 (~pclk_sel_slave),
.S1 ( pclk_sel_slave),
//---------- Output --------------------------------
.O (CLK_PCLK_SLAVE)
);
end
else
//---------- Select PCLK Buffer ------------------------
begin : pclk_slave_bufg
//---------- PCLK Buffer -------------------------------
BUFG pclk_slave
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (CLK_PCLK_SLAVE)
);
end
endgenerate
//---------- Generate RXOUTCLK Buffer for Debug --------------------------------
generate if ((PCIE_DEBUG_MODE == 1) || (PCIE_ASYNC_EN == "TRUE"))
begin : rxoutclk_per_lane
//---------- Generate per Lane -------------------------
for (i=0; i<PCIE_LANE; i=i+1)
begin : rxoutclk_i
//---------- RXOUTCLK Buffer -----------------------
BUFG rxoutclk_i
(
//---------- Input -----------------------------
.I (CLK_RXOUTCLK_IN[i]),
//---------- Output ----------------------------
.O (CLK_RXOUTCLK_OUT[i])
);
end
end
else
//---------- Disable RXOUTCLK Buffer for Normal Operation
begin : rxoutclk_i_disable
assign CLK_RXOUTCLK_OUT = {PCIE_LANE{1'd0}};
end
endgenerate
//---------- Generate DCLK Buffer ----------------------------------------------
//generate if (PCIE_USERCLK2_FREQ <= 3)
//---------- Disable DCLK Buffer -----------------------
// begin : dclk_i
// assign CLK_DCLK = userclk2_1; // always less than 125Mhz
// end
//else
// begin : dclk_i_bufg
//---------- DCLK Buffer -------------------------------
// BUFG dclk_i
// (
//---------- Input ---------------------------------
// .I (clk_125mhz),
//---------- Output --------------------------------
// .O (CLK_DCLK)
// );
// end
//endgenerate
generate if (PCIE_LINK_SPEED != 1)
begin : dclk_i_bufg
//---------- DCLK Buffer -------------------------------
BUFG dclk_i
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (CLK_DCLK)
);
end
else
//---------- Disable DCLK Buffer -----------------------
begin : dclk_i
assign CLK_DCLK = clk_125mhz_buf; // always 125 MHz in Gen1
end
endgenerate
//---------- Generate USERCLK1 Buffer ------------------------------------------
generate if (PCIE_GEN1_MODE == 1'b1 && PCIE_USERCLK1_FREQ == 3)
//---------- USERCLK1 same as PCLK -------------------
begin :userclk1_i1_no_bufg
assign userclk1_1 = pclk_1;
end
else
begin : userclk1_i1
//---------- USERCLK1 Buffer ---------------------------
BUFG usrclk1_i1
(
//---------- Input ---------------------------------
.I (userclk1),
//---------- Output --------------------------------
.O (userclk1_1)
);
end
endgenerate
//---------- Generate USERCLK2 Buffer ------------------------------------------
generate if (PCIE_GEN1_MODE == 1'b1 && PCIE_USERCLK2_FREQ == 3 )
//---------- USERCLK2 same as PCLK -------------------
begin : userclk2_i1_no_bufg0
assign userclk2_1 = pclk_1;
end
else if (PCIE_USERCLK2_FREQ == PCIE_USERCLK1_FREQ )
//---------- USERCLK2 same as USERCLK1 -------------------
begin : userclk2_i1_no_bufg1
assign userclk2_1 = userclk1_1;
end
else
begin : userclk2_i1
//---------- USERCLK2 Buffer ---------------------------
BUFG usrclk2_i1
(
//---------- Input ---------------------------------
.I (userclk2),
//---------- Output --------------------------------
.O (userclk2_1)
);
end
endgenerate
//---------- Generate OOBCLK Buffer --------------------------------------------
generate if (PCIE_OOBCLK_MODE == 2)
begin : oobclk_i1
//---------- OOBCLK Buffer -----------------------------
BUFG oobclk_i1
(
//---------- Input ---------------------------------
.I (oobclk),
//---------- Output --------------------------------
.O (CLK_OOBCLK)
);
end
else
//---------- Disable OOBCLK Buffer ---------------------
begin : oobclk_i1_disable
assign CLK_OOBCLK = pclk;
end
endgenerate
// Disabled Second Stage Buffers
assign pclk = pclk_1;
assign CLK_RXUSRCLK = pclk_1;
assign CLK_USERCLK1 = userclk1_1;
assign CLK_USERCLK2 = userclk2_1;
//---------- Select PCLK -------------------------------------------------------
always @ (posedge pclk)
begin
if (!CLK_RST_N)
pclk_sel <= 1'd0;
else
begin
//---------- Select 250 MHz ------------------------
if (&pclk_sel_reg2)
pclk_sel <= 1'd1;
//---------- Select 125 MHz ------------------------
else if (&(~pclk_sel_reg2))
pclk_sel <= 1'd0;
//---------- Hold PCLK -----------------------------
else
pclk_sel <= pclk_sel;
end
end
always @ (posedge pclk)
begin
if (!CLK_RST_N)
pclk_sel_slave<= 1'd0;
else
begin
//---------- Select 250 MHz ------------------------
if (&pclk_sel_slave_reg2)
pclk_sel_slave <= 1'd1;
//---------- Select 125 MHz ------------------------
else if (&(~pclk_sel_slave_reg2))
pclk_sel_slave <= 1'd0;
//---------- Hold PCLK -----------------------------
else
pclk_sel_slave <= pclk_sel_slave;
end
end
//---------- PIPE Clock Output -------------------------------------------------
assign CLK_PCLK = pclk;
assign CLK_MMCM_LOCK = mmcm_lock;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////
//
// GLOBAL_LOGIC
//
// Description: The GLOBAL_LOGIC module handles channel bonding, channel error manangement
// and channel bond block code generation.
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_GLOBAL_LOGIC #
(
parameter INTER_CB_GAP = 5'd9
)
(
// GTX Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
CHAN_BOND_RESET,
// Aurora Lane Interface
LANE_UP,
HARD_ERR,
GEN_NA_IDLES,
GEN_CH_BOND,
RESET_LANES,
GOT_NA_IDLES,
GOT_CCS,
REMOTE_READY,
GOT_CBS,
GOT_IDLES,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP_RX_IF,
CHANNEL_UP_TX_IF,
CHANNEL_HARD_ERR,
TXDATAVALID_IN
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTX Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
output CHAN_BOND_RESET;
// Aurora Lane Interface
input LANE_UP;
input HARD_ERR;
input GOT_NA_IDLES;
input GOT_CCS;
input REMOTE_READY;
input GOT_CBS;
input GOT_IDLES;
output GEN_NA_IDLES;
output GEN_CH_BOND;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input TXDATAVALID_IN;
output CHANNEL_UP_RX_IF;
output CHANNEL_UP_TX_IF;
output CHANNEL_HARD_ERR;
//*********************************Wire Declarations**********************************
wire reset_channel_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_64b66b_25p4G_CHANNEL_INIT_SM channel_init_sm_i
(
// GTX Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
.CHAN_BOND_RESET(CHAN_BOND_RESET),
// Aurora Lane Interface
.GEN_NA_IDLES(GEN_NA_IDLES),
.RX_NA_IDLES(GOT_NA_IDLES),
.RX_CC(GOT_CCS),
.REMOTE_READY(REMOTE_READY),
.RX_CB(GOT_CBS),
.RX_IDLES(GOT_IDLES),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.LANE_UP(LANE_UP),
.CHANNEL_UP_TX_IF(CHANNEL_UP_TX_IF),
.CHANNEL_UP_RX_IF(CHANNEL_UP_RX_IF)
);
// Idle and verification sequence generator module.
aurora_64b66b_25p4G_CHANNEL_BOND_GEN #
(
.INTER_CB_GAP (INTER_CB_GAP)
)channel_bond_gen_i
(
// Channel Init SM Interface
.CHANNEL_UP(CHANNEL_UP_TX_IF),
// Aurora Lane Interface
.GEN_CH_BOND(GEN_CH_BOND),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.TXDATAVALID_IN(TXDATAVALID_IN)
);
// Channel Error Management module.
aurora_64b66b_25p4G_CHANNEL_ERR_DETECT channel_err_detect_i
(
// Aurora Lane Interface
.HARD_ERR(HARD_ERR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.CHANNEL_HARD_ERR(CHANNEL_HARD_ERR)
);
endmodule
|
// $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
//====================================================================
module CmpEng (/*AUTOARG*/
// Inputs
clk, reset_l
);
input clk;
input reset_l;
// ****************************************************************
/*AUTOREG*/
/*AUTOWIRE*/
// ********* Prefetch FSM definitions ****************************
reg [3:0] m_cac_state_r;
reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
reg m_wid1_r;
reg [2:0] m_wid3_r;
reg [5:2] m_wid4_r_l;
logic [4:1] logic_four;
logic [PARAM-1:0] paramed;
`define M 2
`define L 1
parameter MS = 2;
parameter LS = 1;
reg [MS:LS] m_param_r;
reg [`M:`L] m_def2_r;
always @ (posedge clk) begin
if (~reset_l) begin
m_cac_state_r <= CAC_IDLE;
m_cac_sel_r <= CSEL_PF;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
logic_four <= '0;
m_def2_r <= '0;
m_param_r <= '0;
m_wid1_r <= '0;
m_wid3_r <= '0;
m_wid4_r_l <= ~'0;
paramed <= '0;
// End of automatics
end
else begin
m_wid1_r <= 0;
m_wid3_r <= 0;
m_wid4_r_l <= 0;
m_param_r <= 0;
m_def2_r <= 0;
logic_four <= 4;
paramed <= 1;
end
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// verilog-auto-sense-defines-constant: t
// verilog-auto-reset-widths: unbased
// verilog-active-low-regexp: "_l$"
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21AI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O21AI_FUNCTIONAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o21ai (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21AI_FUNCTIONAL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_top(
clk,
// gpio
dac_gpio_input,
dac_gpio_output,
adc_gpio_input,
adc_gpio_output,
// TX side
dma_dac_en,
dma_dac_dunf,
dma_dac_ddata,
dma_dac_dvalid,
core_dac_en,
core_dac_dunf,
core_dac_ddata,
core_dac_dvalid,
// RX side
core_adc_dwr,
core_adc_dsync,
core_adc_ddata,
core_adc_ovf,
dma_adc_dwr,
dma_adc_dsync,
dma_adc_ddata,
dma_adc_ovf
);
localparam ENABELED = 1;
localparam DATA_WIDTH = 32;
parameter NUM_CHANNEL = 2;
parameter ADC_EN = 1;
parameter DAC_EN = 1;
localparam DBUS_WIDTH = DATA_WIDTH * NUM_CHANNEL;
input clk;
input [31:0] dac_gpio_input;
output [31:0] dac_gpio_output;
input [31:0] adc_gpio_input;
output [31:0] adc_gpio_output;
output dma_dac_en;
input dma_dac_dunf;
input [(DBUS_WIDTH - 1):0] dma_dac_ddata;
input dma_dac_dvalid;
input core_dac_en;
output core_dac_dunf;
output [(DBUS_WIDTH - 1):0] core_dac_ddata;
output core_dac_dvalid;
input core_adc_dwr;
input core_adc_dsync;
input [(DBUS_WIDTH - 1):0] core_adc_ddata;
output core_adc_ovf;
output dma_adc_dwr;
output dma_adc_dsync;
output [(DBUS_WIDTH - 1):0] dma_adc_ddata;
input dma_adc_ovf;
wire [31:0] adc_gpio_out_s[(NUM_CHANNEL - 1):0];
wire [(NUM_CHANNEL - 1):0] adc_gpio_out_s_inv[31:0];
wire [31:0] dac_gpio_out_s[(NUM_CHANNEL - 1):0];
wire [(NUM_CHANNEL - 1):0] dac_gpio_out_s_inv[31:0];
genvar l_inst;
generate
for(l_inst = 0; l_inst < NUM_CHANNEL; l_inst = l_inst + 1) begin: tx_rx_data_path
if(ADC_EN == ENABELED) begin
if(l_inst == 0) begin
prcfg_adc #(
.CHANNEL_ID(l_inst)
) i_prcfg_adc_1 (
.clk(clk),
.control(adc_gpio_input),
.status(adc_gpio_out_s[l_inst]),
.src_adc_dwr(core_adc_dwr),
.src_adc_dsync(core_adc_dsync),
.src_adc_ddata(core_adc_ddata[(DATA_WIDTH - 1):0]),
.src_adc_dovf(core_adc_ovf),
.dst_adc_dwr(dma_adc_dwr),
.dst_adc_dsync(dma_adc_dsync),
.dst_adc_ddata(dma_adc_ddata[(DATA_WIDTH - 1):0]),
.dst_adc_dovf(dma_adc_ovf)
);
end else begin
prcfg_adc #(
.CHANNEL_ID(l_inst)
) i_prcfg_adc_i (
.clk(clk),
.control(adc_gpio_input),
.status(adc_gpio_out_s[l_inst]),
.src_adc_dwr(core_adc_dwr),
.src_adc_dsync(core_adc_dsync),
.src_adc_ddata(core_adc_ddata[((DATA_WIDTH * (l_inst + 1)) - 1):(DATA_WIDTH * l_inst)]),
.src_adc_dovf(),
.dst_adc_dwr(),
.dst_adc_dsync(),
.dst_adc_ddata(dma_adc_ddata[((DATA_WIDTH * (l_inst + 1)) - 1):(DATA_WIDTH * l_inst)]),
.dst_adc_dovf(dma_adc_ovf)
);
end
end
if(DAC_EN == ENABELED) begin
if(l_inst == 0) begin
prcfg_dac #(
.CHANNEL_ID(l_inst)
) i_prcfg_dac_1 (
.clk(clk),
.control(dac_gpio_input),
.status(dac_gpio_out_s[l_inst]),
.src_dac_en(dma_dac_en),
.src_dac_ddata(dma_dac_ddata[(DATA_WIDTH - 1):0]),
.src_dac_dunf(dma_dac_dunf),
.src_dac_dvalid(dma_dac_dvalid),
.dst_dac_en(core_dac_en),
.dst_dac_ddata(core_dac_ddata[(DATA_WIDTH - 1):0]),
.dst_dac_dunf(core_dac_dunf),
.dst_dac_dvalid(core_dac_dvalid)
);
end else begin
prcfg_dac #(
.CHANNEL_ID(l_inst)
) i_prcfg_dac_i (
.clk(clk),
.control(dac_gpio_input),
.status(dac_gpio_out_s[l_inst]),
.src_dac_en(),
.src_dac_ddata(dma_dac_ddata[((DATA_WIDTH * (l_inst + 1)) - 1):(DATA_WIDTH * l_inst)]),
.src_dac_dunf(dma_dac_dunf),
.src_dac_dvalid(dma_dac_dvalid),
.dst_dac_en(core_dac_en),
.dst_dac_ddata(core_dac_ddata[((DATA_WIDTH * (l_inst + 1)) - 1):(DATA_WIDTH * l_inst)]),
.dst_dac_dunf(),
.dst_dac_dvalid()
);
end
end
end
endgenerate
genvar i;
genvar j;
generate
for(i = 0; i < 32; i = i + 1) begin
for(j = 0; j < NUM_CHANNEL; j = j + 1) begin
assign adc_gpio_out_s_inv[i][j] = adc_gpio_out_s[j][i];
assign dac_gpio_out_s_inv[i][j] = dac_gpio_out_s[j][i];
end
end
endgenerate
// generate gpio_outputs
generate
for(i = 0; i < 32; i = i + 1) begin
assign adc_gpio_output[i] = |adc_gpio_out_s_inv[i];
assign dac_gpio_output[i] = |dac_gpio_out_s_inv[i];
end
endgenerate
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA DMA Engine Core ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_de.v,v 1.3 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/15 05:40:30 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.3 2001/06/13 02:26:48 rudi
//
//
// Small changes after running lint.
//
// Revision 1.2 2001/06/05 10:22:36 rudi
//
//
// - Added Support of up to 31 channels
// - Added support for 2,4 and 8 priority levels
// - Now can have up to 31 channels
// - Added many configuration items
// - Changed reset to async
//
// Revision 1.1.1.1 2001/03/19 13:10:44 rudi
// Initial Release
//
//
//
`include "wb_dma_defines.v"
module wb_dma_de(clk, rst,
// WISHBONE MASTER INTERFACE 0
mast0_go, mast0_we, mast0_adr, mast0_din,
mast0_dout, mast0_err, mast0_drdy, mast0_wait,
// WISHBONE MASTER INTERFACE 1
mast1_go, mast1_we, mast1_adr, mast1_din,
mast1_dout, mast1_err, mast1_drdy, mast1_wait,
// DMA Engine Init & Setup
de_start, nd, csr, pointer, pointer_s, txsz,
adr0, adr1, am0, am1,
// DMA Engine Register File Update Outputs
de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set,
de_csr, de_txsz, de_adr0, de_adr1, de_fetch_descr,
// DMA Engine Control Outputs
next_ch, de_ack,
// DMA Engine Status
pause_req, paused,
dma_abort, dma_busy, dma_err, dma_done, dma_done_all
);
input clk, rst;
// --------------------------------------
// WISHBONE MASTER INTERFACE 0
output mast0_go; // Perform a Master Cycle
output mast0_we; // Read/Write
output [31:0] mast0_adr; // Address for the transfer
input [31:0] mast0_din; // Internal Input Data
output [31:0] mast0_dout; // Internal Output Data
input mast0_err; // Indicates an error has occurred
input mast0_drdy; // Indicated that either data is available
// during a read, or that the master can accept
// the next data during a write
output mast0_wait; // Tells the master to insert wait cycles
// because data can not be accepted/provided
// --------------------------------------
// WISHBONE MASTER INTERFACE 1
output mast1_go; // Perform a Master Cycle
output mast1_we; // Read/Write
output [31:0] mast1_adr; // Address for the transfer
input [31:0] mast1_din; // Internal Input Data
output [31:0] mast1_dout; // Internal Output Data
input mast1_err; // Indicates an error has occurred
input mast1_drdy; // Indicated that either data is available
// during a read, or that the master can accept
// the next data during a write
output mast1_wait; // Tells the master to insert wait cycles
// because data can not be accepted/provided
// --------------------------------------
// DMA Engine Signals
// DMA Engine Init & Setup
input de_start; // Start DMA Engine Indicator
input nd; // Next Descriptor Indicator
input [31:0] csr; // Selected Channel CSR
input [31:0] pointer; // Linked List Descriptor pointer
input [31:0] pointer_s; // Previous Pointer
input [31:0] txsz; // Selected Channel Transfer Size
input [31:0] adr0, adr1; // Selected Channel Addresses
input [31:0] am0, am1; // Selected Channel Address Masks
// DMA Engine Register File Update Outputs
output de_csr_we; // Write enable for csr register
output de_txsz_we; // Write enable for txsz register
output de_adr0_we; // Write enable for adr0 register
output de_adr1_we; // Write enable for adr1 register
output ptr_set; // Set Pointer as Valid
output [31:0] de_csr; // Write Data for CSR when loading External Desc.
output [11:0] de_txsz; // Write back data for txsz register
output [31:0] de_adr0; // Write back data for adr0 register
output [31:0] de_adr1; // Write back data for adr1 register
output de_fetch_descr; // Indicates that we are fetching a descriptor
// DMA Engine Control Outputs
output next_ch; // Indicates the DMA Engine is done
output de_ack;
// DMA Abort from RF (software forced abort)
input dma_abort;
// DMA Engine Status
input pause_req;
output paused;
output dma_busy, dma_err, dma_done, dma_done_all;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
parameter [10:0] // synopsys enum state
IDLE = 11'b000_0000_0001,
READ = 11'b000_0000_0010,
WRITE = 11'b000_0000_0100,
UPDATE = 11'b000_0000_1000,
LD_DESC1 = 11'b000_0001_0000,
LD_DESC2 = 11'b000_0010_0000,
LD_DESC3 = 11'b000_0100_0000,
LD_DESC4 = 11'b000_1000_0000,
LD_DESC5 = 11'b001_0000_0000,
WB = 11'b010_0000_0000,
PAUSE = 11'b100_0000_0000;
reg [10:0] /* synopsys enum state */ state, next_state;
// synopsys state_vector state
reg [31:0] mast0_adr, mast1_adr;
reg [29:0] adr0_cnt, adr1_cnt;
wire [29:0] adr0_cnt_next, adr1_cnt_next;
wire [29:0] adr0_cnt_next1, adr1_cnt_next1;
reg adr0_inc, adr1_inc;
reg [8:0] chunk_cnt;
reg chunk_dec;
reg [11:0] tsz_cnt;
reg tsz_dec;
reg de_txsz_we;
reg de_csr_we;
reg de_adr0_we;
reg de_adr1_we;
reg ld_desc_sel;
wire chunk_cnt_is_0_d;
reg chunk_cnt_is_0_r;
wire tsz_cnt_is_0_d;
reg tsz_cnt_is_0_r;
reg read, write;
reg read_r, write_r;
wire rd_ack, wr_ack;
reg rd_ack_r;
reg chunk_0;
wire done;
reg dma_done_d;
reg dma_done_r;
reg dma_abort_r;
reg next_ch;
wire read_hold, write_hold;
reg write_hold_r;
reg [1:0] ptr_adr_low;
reg m0_go;
reg m0_we;
reg ptr_set;
// Aliases
wire a0_inc_en = csr[4]; // Source Address (Adr 0) increment enable
wire a1_inc_en = csr[3]; // Dest. Address (Adr 1) increment enable
wire ptr_valid = pointer[0];
wire use_ed = csr[`WDMA_USE_ED];
reg mast0_drdy_r;
reg paused;
reg de_fetch_descr; // Indicates that we are fetching a descriptor
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
dma_done_r <= #1 dma_done;
// Address Counter 0 (Source Address)
always @(posedge clk)
if(de_start | ptr_set) adr0_cnt <= #1 adr0[31:2];
else
if(adr0_inc & a0_inc_en) adr0_cnt <= #1 adr0_cnt_next;
// 30 Bit Incrementor (registered)
wb_dma_inc30r u0( .clk( clk ),
.in( adr0_cnt ),
.out( adr0_cnt_next1 ) );
assign adr0_cnt_next[1:0] = adr0_cnt_next1[1:0];
assign adr0_cnt_next[2] = am0[4] ? adr0_cnt_next1[2] : adr0_cnt[2];
assign adr0_cnt_next[3] = am0[5] ? adr0_cnt_next1[3] : adr0_cnt[3];
assign adr0_cnt_next[4] = am0[6] ? adr0_cnt_next1[4] : adr0_cnt[4];
assign adr0_cnt_next[5] = am0[7] ? adr0_cnt_next1[5] : adr0_cnt[5];
assign adr0_cnt_next[6] = am0[8] ? adr0_cnt_next1[6] : adr0_cnt[6];
assign adr0_cnt_next[7] = am0[9] ? adr0_cnt_next1[7] : adr0_cnt[7];
assign adr0_cnt_next[8] = am0[10] ? adr0_cnt_next1[8] : adr0_cnt[8];
assign adr0_cnt_next[9] = am0[11] ? adr0_cnt_next1[9] : adr0_cnt[9];
assign adr0_cnt_next[10] = am0[12] ? adr0_cnt_next1[10] : adr0_cnt[10];
assign adr0_cnt_next[11] = am0[13] ? adr0_cnt_next1[11] : adr0_cnt[11];
assign adr0_cnt_next[12] = am0[14] ? adr0_cnt_next1[12] : adr0_cnt[12];
assign adr0_cnt_next[13] = am0[15] ? adr0_cnt_next1[13] : adr0_cnt[13];
assign adr0_cnt_next[14] = am0[16] ? adr0_cnt_next1[14] : adr0_cnt[14];
assign adr0_cnt_next[15] = am0[17] ? adr0_cnt_next1[15] : adr0_cnt[15];
assign adr0_cnt_next[16] = am0[18] ? adr0_cnt_next1[16] : adr0_cnt[16];
assign adr0_cnt_next[17] = am0[19] ? adr0_cnt_next1[17] : adr0_cnt[17];
assign adr0_cnt_next[18] = am0[20] ? adr0_cnt_next1[18] : adr0_cnt[18];
assign adr0_cnt_next[19] = am0[21] ? adr0_cnt_next1[19] : adr0_cnt[19];
assign adr0_cnt_next[20] = am0[22] ? adr0_cnt_next1[20] : adr0_cnt[20];
assign adr0_cnt_next[21] = am0[23] ? adr0_cnt_next1[21] : adr0_cnt[21];
assign adr0_cnt_next[22] = am0[24] ? adr0_cnt_next1[22] : adr0_cnt[22];
assign adr0_cnt_next[23] = am0[25] ? adr0_cnt_next1[23] : adr0_cnt[23];
assign adr0_cnt_next[24] = am0[26] ? adr0_cnt_next1[24] : adr0_cnt[24];
assign adr0_cnt_next[25] = am0[27] ? adr0_cnt_next1[25] : adr0_cnt[25];
assign adr0_cnt_next[26] = am0[28] ? adr0_cnt_next1[26] : adr0_cnt[26];
assign adr0_cnt_next[27] = am0[29] ? adr0_cnt_next1[27] : adr0_cnt[27];
assign adr0_cnt_next[28] = am0[30] ? adr0_cnt_next1[28] : adr0_cnt[28];
assign adr0_cnt_next[29] = am0[31] ? adr0_cnt_next1[29] : adr0_cnt[29];
// Address Counter 1 (Destination Address)
always @(posedge clk)
if(de_start | ptr_set) adr1_cnt <= #1 adr1[31:2];
else
if(adr1_inc & a1_inc_en) adr1_cnt <= #1 adr1_cnt_next;
// 30 Bit Incrementor (registered)
wb_dma_inc30r u1( .clk( clk ),
.in( adr1_cnt ),
.out( adr1_cnt_next1 ) );
assign adr1_cnt_next[1:0] = adr1_cnt_next1[1:0];
assign adr1_cnt_next[2] = am1[4] ? adr1_cnt_next1[2] : adr1_cnt[2];
assign adr1_cnt_next[3] = am1[5] ? adr1_cnt_next1[3] : adr1_cnt[3];
assign adr1_cnt_next[4] = am1[6] ? adr1_cnt_next1[4] : adr1_cnt[4];
assign adr1_cnt_next[5] = am1[7] ? adr1_cnt_next1[5] : adr1_cnt[5];
assign adr1_cnt_next[6] = am1[8] ? adr1_cnt_next1[6] : adr1_cnt[6];
assign adr1_cnt_next[7] = am1[9] ? adr1_cnt_next1[7] : adr1_cnt[7];
assign adr1_cnt_next[8] = am1[10] ? adr1_cnt_next1[8] : adr1_cnt[8];
assign adr1_cnt_next[9] = am1[11] ? adr1_cnt_next1[9] : adr1_cnt[9];
assign adr1_cnt_next[10] = am1[12] ? adr1_cnt_next1[10] : adr1_cnt[10];
assign adr1_cnt_next[11] = am1[13] ? adr1_cnt_next1[11] : adr1_cnt[11];
assign adr1_cnt_next[12] = am1[14] ? adr1_cnt_next1[12] : adr1_cnt[12];
assign adr1_cnt_next[13] = am1[15] ? adr1_cnt_next1[13] : adr1_cnt[13];
assign adr1_cnt_next[14] = am1[16] ? adr1_cnt_next1[14] : adr1_cnt[14];
assign adr1_cnt_next[15] = am1[17] ? adr1_cnt_next1[15] : adr1_cnt[15];
assign adr1_cnt_next[16] = am1[18] ? adr1_cnt_next1[16] : adr1_cnt[16];
assign adr1_cnt_next[17] = am1[19] ? adr1_cnt_next1[17] : adr1_cnt[17];
assign adr1_cnt_next[18] = am1[20] ? adr1_cnt_next1[18] : adr1_cnt[18];
assign adr1_cnt_next[19] = am1[21] ? adr1_cnt_next1[19] : adr1_cnt[19];
assign adr1_cnt_next[20] = am1[22] ? adr1_cnt_next1[20] : adr1_cnt[20];
assign adr1_cnt_next[21] = am1[23] ? adr1_cnt_next1[21] : adr1_cnt[21];
assign adr1_cnt_next[22] = am1[24] ? adr1_cnt_next1[22] : adr1_cnt[22];
assign adr1_cnt_next[23] = am1[25] ? adr1_cnt_next1[23] : adr1_cnt[23];
assign adr1_cnt_next[24] = am1[26] ? adr1_cnt_next1[24] : adr1_cnt[24];
assign adr1_cnt_next[25] = am1[27] ? adr1_cnt_next1[25] : adr1_cnt[25];
assign adr1_cnt_next[26] = am1[28] ? adr1_cnt_next1[26] : adr1_cnt[26];
assign adr1_cnt_next[27] = am1[29] ? adr1_cnt_next1[27] : adr1_cnt[27];
assign adr1_cnt_next[28] = am1[30] ? adr1_cnt_next1[28] : adr1_cnt[28];
assign adr1_cnt_next[29] = am1[31] ? adr1_cnt_next1[29] : adr1_cnt[29];
// Chunk Counter
always @(posedge clk)
if(de_start) chunk_cnt <= #1 txsz[24:16];
else
if(chunk_dec & !chunk_cnt_is_0_r) chunk_cnt <= #1 chunk_cnt - 9'h1;
assign chunk_cnt_is_0_d = (chunk_cnt == 9'h0);
always @(posedge clk)
chunk_cnt_is_0_r <= #1 chunk_cnt_is_0_d;
// Total Size Counter
always @(posedge clk)
if(de_start | ptr_set) tsz_cnt <= #1 txsz[11:0];
else
if(tsz_dec & !tsz_cnt_is_0_r) tsz_cnt <= #1 tsz_cnt - 12'h1;
assign tsz_cnt_is_0_d = (tsz_cnt == 12'h0) & !txsz[15];
always @(posedge clk)
tsz_cnt_is_0_r <= #1 tsz_cnt_is_0_d;
// Counter Control Logic
always @(posedge clk)
chunk_dec <= #1 read & !read_r;
always @(posedge clk)
tsz_dec <= #1 read & !read_r;
//always @(posedge clk)
always @(rd_ack or read_r)
adr0_inc = rd_ack & read_r;
//always @(posedge clk)
always @(wr_ack or write_r)
adr1_inc = wr_ack & write_r;
// Done logic
always @(posedge clk)
chunk_0 <= #1 (txsz[24:16] == 9'h0);
assign done = chunk_0 ? tsz_cnt_is_0_d : (tsz_cnt_is_0_d | chunk_cnt_is_0_d);
assign dma_done = dma_done_d & done;
assign dma_done_all = dma_done_d & (tsz_cnt_is_0_r | (nd & chunk_cnt_is_0_d));
always @(posedge clk)
next_ch <= #1 dma_done;
// Register Update Outputs
assign de_txsz = ld_desc_sel ? mast0_din[11:0] : tsz_cnt;
assign de_adr0 = ld_desc_sel ? mast0_din : {adr0_cnt, 2'b00};
assign de_adr1 = ld_desc_sel ? mast0_din : {adr1_cnt, 2'b00};
assign de_csr = mast0_din;
// Abort logic
always @(posedge clk)
dma_abort_r <= #1 dma_abort | mast0_err | mast1_err;
assign dma_err = dma_abort_r;
assign dma_busy = (state != IDLE);
////////////////////////////////////////////////////////////////////
//
// WISHBONE Interface Logic
//
always @(posedge clk)
read_r <= #1 read;
always @(posedge clk)
write_r <= #1 write;
always @(posedge clk)
rd_ack_r <= #1 read_r;
// Data Path
assign mast0_dout = m0_we ? {20'h0, tsz_cnt} : csr[2] ? mast1_din : mast0_din;
assign mast1_dout = csr[2] ? mast1_din : mast0_din;
// Address Path
always @(posedge clk)
`ifdef DR_0002
mast0_adr <= #1 m0_go ?
(m0_we ? pointer_s : {pointer[31:4], ptr_adr_low, 2'b00}) :
read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00};
`else
mast0_adr <= #1 m0_go ?
(m0_we ? pointer_s : {pointer[31:2] + ptr_adr_low, 2'b00}) :
read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00};
`endif
always @(posedge clk)
mast1_adr <= #1 read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00};
// CTRL
assign write_hold = (read | write) & write_hold_r;
always @(posedge clk)
write_hold_r <= #1 read | write;
assign read_hold = done ? read : (read | write);
assign mast0_go = (!csr[2] & read_hold) | (!csr[1] & write_hold) | m0_go;
assign mast1_go = ( csr[2] & read_hold) | ( csr[1] & write_hold);
assign mast0_we = m0_go ? m0_we : (!csr[1] & write);
assign mast1_we = csr[1] & write;
assign rd_ack = (csr[2] ? mast1_drdy : mast0_drdy);
assign wr_ack = (csr[1] ? mast1_drdy : mast0_drdy);
assign mast0_wait = !((!csr[2] & read) | (!csr[1] & write)) & !m0_go;
assign mast1_wait = !(( csr[2] & read) | ( csr[1] & write));
always @(posedge clk)
mast0_drdy_r <= #1 mast0_drdy;
assign de_ack = dma_done;
////////////////////////////////////////////////////////////////////
//
// State Machine
//
always @(posedge clk or negedge rst)
if(!rst) state <= #1 IDLE;
else state <= #1 next_state;
always @(state or pause_req or dma_abort_r or de_start or rd_ack or wr_ack or
done or ptr_valid or use_ed or mast0_drdy or mast0_drdy_r or csr or nd)
begin
next_state = state; // Default keep state
read = 1'b0;
write = 1'b0;
dma_done_d = 1'b0;
de_csr_we = 1'b0;
de_txsz_we = 1'b0;
de_adr0_we = 1'b0;
de_adr1_we = 1'b0;
de_fetch_descr = 1'b0;
m0_go = 1'b0;
m0_we = 1'b0;
ptr_adr_low = 2'h0;
ptr_set = 1'b0;
ld_desc_sel = 1'b0;
paused = 1'b0;
case(state) // synopsys parallel_case full_case
IDLE:
begin
if(pause_req) next_state = PAUSE;
else
if(de_start & !csr[`WDMA_ERR])
begin
if(use_ed & !ptr_valid) next_state = LD_DESC1;
else next_state = READ;
end
end
PAUSE:
begin
paused = 1'b1;
if(!pause_req) next_state = IDLE;
end
READ: // Read From Source
begin
if(dma_abort_r) next_state = UPDATE;
else
if(!rd_ack) read = 1'b1;
else
begin
write = 1'b1;
next_state = WRITE;
end
end
WRITE: // Write To Destination
begin
if(dma_abort_r) next_state = UPDATE;
else
if(!wr_ack) write = 1'b1;
else
begin
if(done) next_state = UPDATE;
else
begin
read = 1'b1;
next_state = READ;
end
end
end
UPDATE: // Update Registers
begin
dma_done_d = 1'b1;
de_txsz_we = 1'b1;
de_adr0_we = 1'b1;
de_adr1_we = 1'b1;
if(use_ed & csr[`WDMA_WRB] & nd)
begin
m0_we = 1'b1;
m0_go = 1'b1;
next_state = WB;
end
else next_state = IDLE;
end
WB:
begin
m0_we = 1'b1;
if(mast0_drdy)
begin
next_state = IDLE;
end
else m0_go = 1'b1;
end
LD_DESC1: // Load Descriptor from memory to registers
begin
ptr_adr_low = 2'h0;
ld_desc_sel = 1'b1;
m0_go = 1'b1;
de_csr_we = 1'b1;
de_txsz_we = 1'b1;
de_fetch_descr = 1'b1;
if(mast0_drdy)
begin
ptr_adr_low = 2'h1;
next_state = LD_DESC2;
end
end
LD_DESC2:
begin
de_fetch_descr = 1'b1;
if(mast0_drdy_r) de_csr_we = 1'b1;
if(mast0_drdy_r) de_txsz_we = 1'b1;
ptr_adr_low = 2'h1;
ld_desc_sel = 1'b1;
m0_go = 1'b1;
if(mast0_drdy)
begin
ptr_adr_low = 2'h2;
next_state = LD_DESC3;
end
end
LD_DESC3:
begin
de_fetch_descr = 1'b1;
if(mast0_drdy_r) de_adr0_we = 1'b1;
ptr_adr_low = 2'h2;
ld_desc_sel = 1'b1;
m0_go = 1'b1;
if(mast0_drdy)
begin
ptr_adr_low = 2'h3;
next_state = LD_DESC4;
end
end
LD_DESC4:
begin
de_fetch_descr = 1'b1;
if(mast0_drdy_r) de_adr1_we = 1'b1;
ptr_adr_low = 2'h3;
ld_desc_sel = 1'b1;
if(mast0_drdy)
begin
next_state = LD_DESC5;
end
else m0_go = 1'b1;
end
LD_DESC5:
begin
de_fetch_descr = 1'b1;
ptr_set = 1'b1;
next_state = READ;
end
endcase
end
endmodule
|
// -*- Mode: Verilog -*-
// Filename : simple_slave_00.v
// Description : Wishbone DSP Simple Slave interface testing
// Author : Philip Tracton
// Created On : Wed Dec 2 14:02:57 2015
// Last Modified By: Philip Tracton
// Last Modified On: Wed Dec 2 14:02:57 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`include "wb_dsp_includes.vh"
module test_case ();
//
// Test Configuration
// These parameters need to be set for each test case
//
parameter simulation_name = "simple_slave_00";
parameter ram_image = "simple_slave_00.mem";
parameter channel0_adc_image = "simple_slave_00_adc.mem";
parameter channel1_adc_image = "simple_slave_00_adc.mem";
parameter channel2_adc_image = "simple_slave_00_adc.mem";
parameter channel3_adc_image = "simple_slave_00_adc.mem";
parameter number_of_tests = 1035;
reg err;
reg [31:0] data_out;
integer i;
initial begin
$display("Simple Slave Test Case");
`TB.master_bfm.reset;
@(posedge `WB_RST);
@(negedge `WB_RST);
@(posedge `WB_CLK);
`TB.master_bfm.write(`WB_DSP_EQUATION0_ADDRESS_REG, 32'h1122_3344, 4'hF, err);
`TB.master_bfm.write(`WB_DSP_EQUATION1_ADDRESS_REG, 32'h5566_7788, 4'hF, err);
`TB.master_bfm.write(`WB_DSP_EQUATION2_ADDRESS_REG, 32'h99aa_bbcc, 4'hF, err);
`TB.master_bfm.write(`WB_DSP_EQUATION3_ADDRESS_REG, 32'hddee_ff00, 4'hF, err);
`TB.master_bfm.write(`WB_DSP_CONTROL_REG, 32'h5566_7788, 4'hF, err);
`TB.master_bfm.write(`WB_DAQ_CONTROL_REG, 32'h99AA_BBCC, 4'hF, err);
`TB.master_bfm.write(`WB_DAQ_CHANNEL0_CONTROL_REG, 32'h1234_5678, 4'hF, err);
`TB.master_bfm.write(`WB_DAQ_CHANNEL1_CONTROL_REG, 32'h9ABC_DEF0, 4'hF, err);
`TB.master_bfm.write(`WB_DAQ_CHANNEL2_CONTROL_REG, 32'hA5B6_C7D8, 4'hF, err);
`TB.master_bfm.write(`WB_DAQ_CHANNEL3_CONTROL_REG, 32'hE9FA_DEAD, 4'hF, err);
@(posedge `WB_CLK);
`TB.master_bfm.read_burst(`WB_DSP_EQUATION0_ADDRESS_REG, data_out, 4'hF, 1, 0, err);
`TEST_COMPARE("DSP Equation0 Read", 32'h1122_3344, data_out);
@(posedge `WB_CLK);
`TB.master_bfm.read_burst(`WB_DSP_EQUATION1_ADDRESS_REG, data_out, 4'hF, 1, 0, err);
`TEST_COMPARE("DSP Equation1 Read", 32'h5566_7788, data_out);
@(posedge `WB_CLK);
`TB.master_bfm.read_burst(`WB_DSP_EQUATION2_ADDRESS_REG, data_out, 4'hF, 1, 0, err);
`TEST_COMPARE("DSP Equation2 Read", 32'h99aa_bbcc, data_out);
@(posedge `WB_CLK);
`TB.master_bfm.read_burst(`WB_DSP_EQUATION3_ADDRESS_REG, data_out, 4'hF, 1, 0, err);
`TEST_COMPARE("DSP Equation3 Read", 32'hddee_ff00, data_out);
@(posedge `WB_CLK);
`TB.master_bfm.read_burst(`WB_DSP_CONTROL_REG, data_out, 4'hF, 1, 0, err);
`TEST_COMPARE("DSP Control Read", 32'h5566_7788, data_out);
@(posedge `WB_CLK);
`TB.master_bfm.read_burst(`WB_DSP_STATUS_REG, data_out, 4'hF, 1, 0, err);
`TEST_COMPARE("DSP Status Read", 32'h1, data_out);
@(posedge `WB_CLK);
`TB.master_bfm.read_burst(`WB_DAQ_CONTROL_REG, data_out, 4'hF, 1, 0, err);
#3 `TEST_COMPARE("DAQ Control Read", 32'h99AA_BBCC, data_out);
@(posedge `WB_CLK);
`TB.master_bfm.read_burst(`WB_DAQ_CHANNEL0_CONTROL_REG, data_out, 4'hF, 1, 0, err);
`TEST_COMPARE("DAQ CH0 Control Read", 32'h1234_5678, data_out);
@(posedge `WB_CLK);
`TB.master_bfm.read_burst(`WB_DAQ_CHANNEL1_CONTROL_REG, data_out, 4'hF, 1, 0, err);
`TEST_COMPARE("DAQ CH1 Control Read", 32'h9ABC_DEF0, data_out);
@(posedge `WB_CLK);
`TB.master_bfm.read_burst(`WB_DAQ_CHANNEL2_CONTROL_REG, data_out, 4'hF, 1, 0, err);
`TEST_COMPARE("DAQ CH2 Control Read", 32'hA5B6_C7D8, data_out);
@(posedge `WB_CLK);
`TB.master_bfm.read_burst(`WB_DAQ_CHANNEL3_CONTROL_REG, data_out, 4'hF, 1, 0, err);
`TEST_COMPARE("DAQ CH3 Control Read", 32'hE9FA_DEAD, data_out);
repeat(10) @(posedge `WB_CLK);
for (i=0; i<4096; i=i+4)begin
`TB.master_bfm.write(`WB_DSP_RAM_BASE_ADDRESS + i, {i[7:0],i[7:0],i[7:0],i[7:0]}, 4'hF, err);
end
for (i=0; i<4096; i=i+4)begin
`TB.master_bfm.read_burst(`WB_DSP_RAM_BASE_ADDRESS+i, data_out, 4'hF, 1, 0, err);
`TEST_COMPARE("RAM0 Read", {i[7:0],i[7:0],i[7:0],i[7:0]}, data_out);
end
for (i=0; i<4096; i=i+4)begin
`TB.master_bfm.write(`WB_DSP_RAM_BASE_ADDRESS + i, {24'h0,i[7:0]*4'd2}, 4'h1, err);
`TB.master_bfm.write(`WB_DSP_RAM_BASE_ADDRESS + i, {16'h0,i[7:0]*4'd3,8'h00}, 4'h2, err);
`TB.master_bfm.write(`WB_DSP_RAM_BASE_ADDRESS + i, {8'h0,i[7:0]*4'd4,16'h0}, 4'h4, err);
`TB.master_bfm.write(`WB_DSP_RAM_BASE_ADDRESS + i, {i[7:0]*4'd5,24'h0}, 4'h8, err);
end
#1000;
`TEST_COMPLETE;
end
endmodule // test_case
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_M_V
`define SKY130_FD_SC_LP__O31A_M_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_m (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_m (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_M_V
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module pixelq_op_Mat2AXIvideo (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
img_rows_V_read,
img_cols_V_read,
img_data_stream_0_V_dout,
img_data_stream_0_V_empty_n,
img_data_stream_0_V_read,
img_data_stream_1_V_dout,
img_data_stream_1_V_empty_n,
img_data_stream_1_V_read,
img_data_stream_2_V_dout,
img_data_stream_2_V_empty_n,
img_data_stream_2_V_read,
AXI_video_strm_V_data_V_din,
AXI_video_strm_V_data_V_full_n,
AXI_video_strm_V_data_V_write,
AXI_video_strm_V_keep_V_din,
AXI_video_strm_V_keep_V_full_n,
AXI_video_strm_V_keep_V_write,
AXI_video_strm_V_strb_V_din,
AXI_video_strm_V_strb_V_full_n,
AXI_video_strm_V_strb_V_write,
AXI_video_strm_V_user_V_din,
AXI_video_strm_V_user_V_full_n,
AXI_video_strm_V_user_V_write,
AXI_video_strm_V_last_V_din,
AXI_video_strm_V_last_V_full_n,
AXI_video_strm_V_last_V_write,
AXI_video_strm_V_id_V_din,
AXI_video_strm_V_id_V_full_n,
AXI_video_strm_V_id_V_write,
AXI_video_strm_V_dest_V_din,
AXI_video_strm_V_dest_V_full_n,
AXI_video_strm_V_dest_V_write
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 4'b1;
parameter ap_ST_st2_fsm_1 = 4'b10;
parameter ap_ST_pp0_stg0_fsm_2 = 4'b100;
parameter ap_ST_st5_fsm_3 = 4'b1000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv12_0 = 12'b000000000000;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv3_7 = 3'b111;
parameter ap_const_lv3_0 = 3'b000;
parameter ap_const_lv13_1FFF = 13'b1111111111111;
parameter ap_const_lv12_1 = 12'b1;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [11:0] img_rows_V_read;
input [11:0] img_cols_V_read;
input [7:0] img_data_stream_0_V_dout;
input img_data_stream_0_V_empty_n;
output img_data_stream_0_V_read;
input [7:0] img_data_stream_1_V_dout;
input img_data_stream_1_V_empty_n;
output img_data_stream_1_V_read;
input [7:0] img_data_stream_2_V_dout;
input img_data_stream_2_V_empty_n;
output img_data_stream_2_V_read;
output [23:0] AXI_video_strm_V_data_V_din;
input AXI_video_strm_V_data_V_full_n;
output AXI_video_strm_V_data_V_write;
output [2:0] AXI_video_strm_V_keep_V_din;
input AXI_video_strm_V_keep_V_full_n;
output AXI_video_strm_V_keep_V_write;
output [2:0] AXI_video_strm_V_strb_V_din;
input AXI_video_strm_V_strb_V_full_n;
output AXI_video_strm_V_strb_V_write;
output [0:0] AXI_video_strm_V_user_V_din;
input AXI_video_strm_V_user_V_full_n;
output AXI_video_strm_V_user_V_write;
output [0:0] AXI_video_strm_V_last_V_din;
input AXI_video_strm_V_last_V_full_n;
output AXI_video_strm_V_last_V_write;
output [0:0] AXI_video_strm_V_id_V_din;
input AXI_video_strm_V_id_V_full_n;
output AXI_video_strm_V_id_V_write;
output [0:0] AXI_video_strm_V_dest_V_din;
input AXI_video_strm_V_dest_V_full_n;
output AXI_video_strm_V_dest_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg img_data_stream_0_V_read;
reg img_data_stream_1_V_read;
reg img_data_stream_2_V_read;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm = 4'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_23;
reg [11:0] p_3_reg_202;
reg ap_sig_bdd_79;
wire [12:0] op2_assign_fu_218_p2;
reg [12:0] op2_assign_reg_297;
wire [0:0] exitcond3_fu_229_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_93;
wire [11:0] i_V_fu_234_p2;
reg [11:0] i_V_reg_306;
wire [0:0] exitcond4_fu_240_p2;
reg [0:0] exitcond4_reg_311;
reg ap_sig_cseq_ST_pp0_stg0_fsm_2;
reg ap_sig_bdd_104;
reg ap_reg_ppiten_pp0_it0 = 1'b0;
wire AXI_video_strm_V_id_V1_status;
reg ap_sig_bdd_122;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
wire [11:0] j_V_fu_245_p2;
wire [0:0] axi_last_V_fu_255_p2;
reg [0:0] axi_last_V_reg_320;
reg [11:0] p_s_reg_191;
reg ap_sig_cseq_ST_st5_fsm_3;
reg ap_sig_bdd_149;
reg AXI_video_strm_V_id_V1_update;
reg [0:0] tmp_user_V_fu_128;
wire [12:0] tmp_cast_fu_214_p1;
wire [12:0] tmp_cast_62_fu_251_p1;
reg [3:0] ap_NS_fsm;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond3_fu_229_p2 == ap_const_lv1_0))) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_122 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_240_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond3_fu_229_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_122 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond4_fu_240_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond3_fu_229_p2 == ap_const_lv1_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_122 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_240_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_122 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond4_fu_240_p2 == ap_const_lv1_0))) begin
p_3_reg_202 <= j_V_fu_245_p2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond3_fu_229_p2 == ap_const_lv1_0))) begin
p_3_reg_202 <= ap_const_lv12_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_3)) begin
p_s_reg_191 <= i_V_reg_306;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_79)) begin
p_s_reg_191 <= ap_const_lv12_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_311 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_122 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
tmp_user_V_fu_128 <= ap_const_lv1_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_79)) begin
tmp_user_V_fu_128 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_122 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond4_fu_240_p2 == ap_const_lv1_0))) begin
axi_last_V_reg_320 <= axi_last_V_fu_255_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_122 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
exitcond4_reg_311 <= exitcond4_fu_240_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
i_V_reg_306 <= i_V_fu_234_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_79)) begin
op2_assign_reg_297 <= op2_assign_fu_218_p2;
end
end
/// AXI_video_strm_V_id_V1_update assign process. ///
always @ (exitcond4_reg_311 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_122 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_311 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_122 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
AXI_video_strm_V_id_V1_update = ap_const_logic_1;
end else begin
AXI_video_strm_V_id_V1_update = ap_const_logic_0;
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or exitcond3_fu_229_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond3_fu_229_p2 == ap_const_lv1_0)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (exitcond3_fu_229_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond3_fu_229_p2 == ap_const_lv1_0))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. ///
always @ (ap_sig_bdd_104)
begin
if (ap_sig_bdd_104) begin
ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_23)
begin
if (ap_sig_bdd_23) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_93)
begin
if (ap_sig_bdd_93) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st5_fsm_3 assign process. ///
always @ (ap_sig_bdd_149)
begin
if (ap_sig_bdd_149) begin
ap_sig_cseq_ST_st5_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st5_fsm_3 = ap_const_logic_0;
end
end
/// img_data_stream_0_V_read assign process. ///
always @ (exitcond4_reg_311 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_122 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_311 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_122 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_data_stream_0_V_read = ap_const_logic_1;
end else begin
img_data_stream_0_V_read = ap_const_logic_0;
end
end
/// img_data_stream_1_V_read assign process. ///
always @ (exitcond4_reg_311 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_122 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_311 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_122 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_data_stream_1_V_read = ap_const_logic_1;
end else begin
img_data_stream_1_V_read = ap_const_logic_0;
end
end
/// img_data_stream_2_V_read assign process. ///
always @ (exitcond4_reg_311 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_122 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_311 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_122 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_data_stream_2_V_read = ap_const_logic_1;
end else begin
img_data_stream_2_V_read = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_79 or exitcond3_fu_229_p2 or exitcond4_fu_240_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_122 or ap_reg_ppiten_pp0_it1)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~ap_sig_bdd_79) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (~(exitcond3_fu_229_p2 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
end
ap_ST_pp0_stg0_fsm_2 :
begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_122 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_240_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_122 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_240_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st5_fsm_3;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
end
ap_ST_st5_fsm_3 :
begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign AXI_video_strm_V_data_V_din = {{{{img_data_stream_2_V_dout}, {img_data_stream_1_V_dout}}}, {img_data_stream_0_V_dout}};
assign AXI_video_strm_V_data_V_write = AXI_video_strm_V_id_V1_update;
assign AXI_video_strm_V_dest_V_din = ap_const_lv1_0;
assign AXI_video_strm_V_dest_V_write = AXI_video_strm_V_id_V1_update;
assign AXI_video_strm_V_id_V1_status = (AXI_video_strm_V_data_V_full_n & AXI_video_strm_V_keep_V_full_n & AXI_video_strm_V_strb_V_full_n & AXI_video_strm_V_user_V_full_n & AXI_video_strm_V_last_V_full_n & AXI_video_strm_V_id_V_full_n & AXI_video_strm_V_dest_V_full_n);
assign AXI_video_strm_V_id_V_din = ap_const_lv1_0;
assign AXI_video_strm_V_id_V_write = AXI_video_strm_V_id_V1_update;
assign AXI_video_strm_V_keep_V_din = ap_const_lv3_7;
assign AXI_video_strm_V_keep_V_write = AXI_video_strm_V_id_V1_update;
assign AXI_video_strm_V_last_V_din = axi_last_V_reg_320;
assign AXI_video_strm_V_last_V_write = AXI_video_strm_V_id_V1_update;
assign AXI_video_strm_V_strb_V_din = ap_const_lv3_0;
assign AXI_video_strm_V_strb_V_write = AXI_video_strm_V_id_V1_update;
assign AXI_video_strm_V_user_V_din = tmp_user_V_fu_128;
assign AXI_video_strm_V_user_V_write = AXI_video_strm_V_id_V1_update;
/// ap_sig_bdd_104 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_104 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
/// ap_sig_bdd_122 assign process. ///
always @ (img_data_stream_0_V_empty_n or img_data_stream_1_V_empty_n or img_data_stream_2_V_empty_n or exitcond4_reg_311 or AXI_video_strm_V_id_V1_status)
begin
ap_sig_bdd_122 = (((img_data_stream_0_V_empty_n == ap_const_logic_0) & (exitcond4_reg_311 == ap_const_lv1_0)) | ((exitcond4_reg_311 == ap_const_lv1_0) & (img_data_stream_1_V_empty_n == ap_const_logic_0)) | ((exitcond4_reg_311 == ap_const_lv1_0) & (img_data_stream_2_V_empty_n == ap_const_logic_0)) | ((exitcond4_reg_311 == ap_const_lv1_0) & (AXI_video_strm_V_id_V1_status == ap_const_logic_0)));
end
/// ap_sig_bdd_149 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_149 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_23 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_23 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_79 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_79 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
/// ap_sig_bdd_93 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_93 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
assign axi_last_V_fu_255_p2 = (tmp_cast_62_fu_251_p1 == op2_assign_reg_297? 1'b1: 1'b0);
assign exitcond3_fu_229_p2 = (p_s_reg_191 == img_rows_V_read? 1'b1: 1'b0);
assign exitcond4_fu_240_p2 = (p_3_reg_202 == img_cols_V_read? 1'b1: 1'b0);
assign i_V_fu_234_p2 = (p_s_reg_191 + ap_const_lv12_1);
assign j_V_fu_245_p2 = (p_3_reg_202 + ap_const_lv12_1);
assign op2_assign_fu_218_p2 = ($signed(tmp_cast_fu_214_p1) + $signed(ap_const_lv13_1FFF));
assign tmp_cast_62_fu_251_p1 = p_3_reg_202;
assign tmp_cast_fu_214_p1 = img_cols_V_read;
endmodule //pixelq_op_Mat2AXIvideo
|
//
// Paul Gao 02/2021
//
//
module bsg_link_sdr_test_node
#(parameter `BSG_INV_PARAM(num_channels_p )
,parameter `BSG_INV_PARAM(channel_width_p )
,parameter is_downstream_node_p = 0
,parameter lg_fifo_depth_lp = 3
,parameter width_lp = num_channels_p * channel_width_p
)
(// Node side
input node_clk_i
,input node_reset_i
,input node_en_i
,output logic error_o
,output [31:0] sent_o
,output [31:0] received_o
// Link side
,input clk_i
,input reset_i
,input v_i
,input [width_lp-1:0] data_i
,output ready_o
,output v_o
,output [width_lp-1:0] data_o
,input yumi_i
);
// Async fifo signals
logic node_async_fifo_valid_li, node_async_fifo_ready_lo;
logic node_async_fifo_valid_lo, node_async_fifo_yumi_li;
logic [width_lp-1:0] node_async_fifo_data_li;
logic [width_lp-1:0] node_async_fifo_data_lo;
if (is_downstream_node_p == 0)
begin: upstream
// Generate data packets
test_bsg_data_gen
#(.channel_width_p(channel_width_p)
,.num_channels_p (num_channels_p)
) gen_out
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.yumi_i (node_async_fifo_valid_li & node_async_fifo_ready_lo)
,.o (node_async_fifo_data_li)
);
// Send when node is enabled
assign node_async_fifo_valid_li = node_en_i;
// Count sent packets
bsg_counter_clear_up
#(.max_val_p (1<<32-1)
,.init_val_p(0)
) sent_count
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.clear_i(1'b0)
,.up_i (node_async_fifo_valid_li & node_async_fifo_ready_lo)
,.count_o(sent_o)
);
end
else
begin: downstream
// Generate checking packets
logic [width_lp-1:0] data_check;
test_bsg_data_gen
#(.channel_width_p(channel_width_p)
,.num_channels_p (num_channels_p)
) gen_in
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.yumi_i (node_async_fifo_yumi_li)
,.o (data_check)
);
// Always ready
assign node_async_fifo_yumi_li = node_async_fifo_valid_lo;
// Count received packets
bsg_counter_clear_up
#(.max_val_p (1<<32-1)
,.init_val_p(0)
) received_count
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.clear_i(1'b0)
,.up_i (node_async_fifo_yumi_li)
,.count_o(received_o)
);
// Check errors
always_ff @(posedge node_clk_i)
if (node_reset_i)
error_o <= 0;
else
if (node_async_fifo_yumi_li && data_check != node_async_fifo_data_lo)
begin
// synopsys translate_off
$error("%m mismatched resp data %x %x",data_check, node_async_fifo_data_lo);
// synopsys translate_on
error_o <= 1;
end
end
/********************* Async fifo to link *********************/
// Node side async fifo input
logic node_async_fifo_full_lo;
assign node_async_fifo_ready_lo = ~node_async_fifo_full_lo;
// Link side async fifo input
logic link_async_fifo_full_lo;
assign ready_o = ~link_async_fifo_full_lo;
bsg_async_fifo
#(.lg_size_p(lg_fifo_depth_lp)
,.width_p (width_lp)
) wh_to_mc
(.w_clk_i (clk_i)
,.w_reset_i(reset_i)
,.w_enq_i (v_i & ready_o)
,.w_data_i (data_i)
,.w_full_o (link_async_fifo_full_lo)
,.r_clk_i (node_clk_i)
,.r_reset_i(node_reset_i)
,.r_deq_i (node_async_fifo_yumi_li)
,.r_data_o (node_async_fifo_data_lo)
,.r_valid_o(node_async_fifo_valid_lo)
);
bsg_async_fifo
#(.lg_size_p(lg_fifo_depth_lp)
,.width_p (width_lp)
) mc_to_wh
(.w_clk_i (node_clk_i)
,.w_reset_i(node_reset_i)
,.w_enq_i (node_async_fifo_valid_li & node_async_fifo_ready_lo)
,.w_data_i (node_async_fifo_data_li)
,.w_full_o (node_async_fifo_full_lo)
,.r_clk_i (clk_i)
,.r_reset_i(reset_i)
,.r_deq_i (yumi_i)
,.r_data_o (data_o)
,.r_valid_o(v_o)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_link_sdr_test_node)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_8_V
`define SKY130_FD_SC_LP__EINVP_8_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvp_8 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvp_8 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_8_V
|
`ifndef _alu
`define _alu
module alu(
input [3:0] ctl,
input [31:0] a, b,
output reg [31:0] out,
output zero);
wire [31:0] sub_ab;
wire [31:0] add_ab;
wire oflow_add;
wire oflow_sub;
wire oflow;
wire slt;
assign zero = (0 == out);
assign sub_ab = a - b;
assign add_ab = a + b;
// overflow occurs (with 2's complement numbers) when
// the operands have the same sign, but the sign of the result is
// different. The actual sign is the opposite of the result.
// It is also dependent on wheter addition or subtraction is performed.
assign oflow_add = (a[31] == b[31] && add_ab[31] != a[31]) ? 1 : 0;
assign oflow_sub = (a[31] == b[31] && sub_ab[31] != a[31]) ? 1 : 0;
assign oflow = (ctl == 4'b0010) ? oflow_add : oflow_sub;
// set if less than, 2s compliment 32-bit numbers
assign slt = oflow_sub ? ~(a[31]) : a[31];
always @(*) begin
case (ctl)
4'b0010: out <= add_ab; // a + b
4'b0000: out <= a & b; // and
4'b1100: out <= ~(a | b); // nor
4'b0001: out <= a | b; // or
4'b0111: out <= {{31{1'b0}}, slt}; // set if less than
4'b0110: out <= sub_ab; // a - b
4'b1101: out <= a ^ b; // xor
default: out <= 0;
endcase
end
endmodule
`endif
|
/*
*
* Clock, reset generation unit for Atlys board
*
* Implements clock generation according to design defines
*
` */
`include "orpsoc-defines.v"
module clkgen
(
// Main clocks in, depending on board
input sys_clk_pad_i,
// Asynchronous, active low reset in
input rst_n_pad_i,
// Input reset - through a buffer, asynchronous
output async_rst_o,
// Wishbone clock and reset out
output wb_clk_o,
output wb_rst_o,
// JTAG clock
// input tck_pad_i,
// output dbg_tck_o,
// VGA CLK
// output dvi_clk_o,
// Main memory clocks
output ddr2_if_clk_o,
output ddr2_if_rst_o
// output clk100_o
);
// First, deal with the asychronous reset
wire async_rst_n;
assign async_rst_n = ~rst_n_pad_i;//rst_n_pad_i;
// Everyone likes active-high reset signals...
//assign async_rst_o = ~async_rst_n;
reg rst_r;
reg wb_rst_r;
//assign dbg_tck_o = tck_pad_i;
//
// Declare synchronous reset wires here
//
// An active-low synchronous reset signal (usually a PLL lock signal)
//wire sync_wb_rst_n;
wire sync_ddr2_rst_n;
// An active-low synchronous reset from ethernet PLL
//wire sync_eth_rst_n;
wire sys_clk_pad_ibufg;
/* DCM0 wires */
wire dcm0_clk0_prebufg, dcm0_clk0;
wire dcm0_clk90_prebufg, dcm0_clk90;
wire dcm0_clkfx_prebufg, dcm0_clkfx;
wire dcm0_clkdv_prebufg, dcm0_clkdv;
//wire dcm0_clk2x_prebufg, dcm0_clk2x;
wire dcm0_locked;
//wire pll0_clkfb;
//wire pll0_locked;
//wire pll0_clk1_prebufg, pll0_clk1;
IBUFG sys_clk_in_ibufg (
.I (sys_clk_pad_i),
.O (sys_clk_pad_ibufg)
);
// DCM providing main system/Wishbone clock
DCM_SP #(
// Generate 200 MHz from CLKFX
.CLKFX_MULTIPLY (4),
.CLKFX_DIVIDE (1),
.CLKIN_PERIOD (20.0),
// Generate 25 MHz from CLKDV
.CLKDV_DIVIDE (2.0)
) dcm0 (
// Outputs
.CLK0 (dcm0_clk0_prebufg),
.CLK180 (),
.CLK270 (),
.CLK2X180 (),
.CLK2X (),//dcm0_clk2x_prebufg),
.CLK90 (),//dcm0_clk90_prebufg),
.CLKDV (dcm0_clkdv_prebufg),
.CLKFX180 (),//dcm0_clkfx_prebufg),
.CLKFX (dcm0_clkfx_prebufg),
.LOCKED (dcm0_locked),
// Inputs
.CLKFB (dcm0_clk0),
.CLKIN (sys_clk_pad_ibufg),
.PSEN (1'b0),
.RST (1'b0)//async_rst_o)
);
/*
// Daisy chain DCM-PLL to reduce jitter
PLL_BASE #(
.BANDWIDTH("OPTIMIZED"),
// .CLKFBOUT_MULT(8), // 80 MHz
.CLKFBOUT_MULT(8), // 50 MHz
.CLKFBOUT_PHASE(0.0),
.CLKIN_PERIOD(20),
.CLKOUT1_DIVIDE(16),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLK_FEEDBACK("CLKFBOUT"),
.COMPENSATION("DCM2PLL"),
.DIVCLK_DIVIDE(1),
.REF_JITTER(0.1),
.RESET_ON_LOSS_OF_LOCK("FALSE")
) pll0 (
.CLKFBOUT (pll0_clkfb),
.CLKOUT1 (pll0_clk1_prebufg),
.CLKOUT2 (),
.CLKOUT3 (CLKOUT3),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.LOCKED (pll0_locked),
.CLKFBIN (pll0_clkfb),
.CLKIN (sys_clk_pad_ibufg),////dcm0_clk90_prebufg),
.RST (async_rst_o)
);
*/
BUFG dcm0_clk0_bufg
(// Outputs
.O (dcm0_clk0),
// Inputs
.I (dcm0_clk0_prebufg)
);
/*
BUFG dcm0_clk2x_bufg
(// Outputs
.O (dcm0_clk2x),
// Inputs
.I (dcm0_clk2x_prebufg)
);
*/
BUFG dcm0_clkfx_bufg
(// Outputs
.O (dcm0_clkfx),
// Inputs
.I (dcm0_clkfx_prebufg)
);
/* This is buffered in dvi_gen*/
BUFG dcm0_clkdv_bufg
(// Outputs
.O (dcm0_clkdv),
// Inputs
.I (dcm0_clkdv_prebufg)
);
/*
BUFG pll0_clk1_bufg
(// Outputs
.O (pll0_clk1),
// Inputs
.I (pll0_clk1_prebufg));
*/
assign wb_clk_o = dcm0_clkdv; //pll0_clk1;
//assign sync_wb_rst_n = pll0_locked;
assign sync_ddr2_rst_n = dcm0_locked;
assign ddr2_if_clk_o = dcm0_clkfx; // 200MHz
//assign clk100_o = dcm0_clk0; // 100MHz
//assign dvi_clk_o = dcm0_clkdv_prebufg;
//
// Reset generation
//
//
always @(posedge wb_clk_o or negedge async_rst_n)
if (~async_rst_n)
rst_r <= 1'b1;
else
rst_r <= #1 1'b0;
assign async_rst_o = rst_r;
always @(posedge wb_clk_o)
wb_rst_r <= #1 async_rst_o;
assign wb_rst_o = wb_rst_r;
// Reset generation for wishbone
/*reg [15:0] wb_rst_shr;
always @(posedge wb_clk_o or posedge async_rst_o)
if (async_rst_o)
wb_rst_shr <= 16'hffff;
else
wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_wb_rst_n)};
assign wb_rst_o = wb_rst_shr[15];
*/
assign ddr2_if_rst_o = async_rst_o;
endmodule // clkgen
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2AI_SYMBOL_V
`define SKY130_FD_SC_LS__O2BB2AI_SYMBOL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2AI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221OI_BLACKBOX_V
`define SKY130_FD_SC_MS__A221OI_BLACKBOX_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221OI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4BB_TB_V
`define SKY130_FD_SC_HDLL__NOR4BB_TB_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4bb.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C_N = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C_N = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C_N = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C_N = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hdll__nor4bb dut (.A(A), .B(B), .C_N(C_N), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4BB_TB_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file gc_command_fifo.v when simulating
// the core, gc_command_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module gc_command_fifo(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
data_count,
prog_full
);
input clk;
input rst;
input [28 : 0] din;
input wr_en;
input rd_en;
output [28 : 0] dout;
output full;
output empty;
output [4 : 0] data_count;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(29),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(29),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(1),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(5),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(4),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(5),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(16),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.RST(rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.DATA_COUNT(data_count),
.PROG_FULL(prog_full),
.BACKUP(),
.BACKUP_MARKER(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
///////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Simulation Library Component
// / / 7SERIES PHASER REF
// /__/ /\ Filename : PHASER_REF.v
// \ \ / \
// \__\/\__ \
//
// Revision: Comment:
// 23APR2010 Initial UNI/UNP/SIM from yml
// 02JUL2010 add functionality
// 29SEP2010 update functionality based on rtl
// add width checks
// 28OCT2010 CR580289 ref_clock_input_freq_MHz_min/max < vs <=
// 09NOV2010 CR581863 blocking statements, clock counts to lock.
// 11NOV2010 CR582599 warning in place of LOCK
// 01DEC2010 clean up display of real numbers
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 15AUG2011 621681 remove SIM_SPEEDUP make default
// 16APR2012 655365 else missing from delay_LOCKED always block
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PHASER_REF (
LOCKED,
CLKIN,
PWRDWN,
RST
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
parameter [0:0] IS_RST_INVERTED = 1'b0;
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam INCLK_DELAY = 0;
localparam out_delay = 0;
`else
localparam in_delay = 1;
localparam INCLK_DELAY = 0;
localparam out_delay = 10;
`endif
localparam MODULE_NAME = "PHASER_REF";
localparam real REF_CLK_JITTER_MAX = 100.000;
output LOCKED;
input CLKIN;
input PWRDWN;
input RST;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
wire delay_CLKIN;
wire delay_PWRDWN;
wire delay_RST;
wire delay_GSR;
reg delay_LOCKED = 1'b1;
real ref_clock_input_period = 11.0;
real ref_clock_input_freq_MHz = 1.68;
real time_last_rising_edge = 1.0;
real last_ref_clock_input_period = 13.0;
real last_ref_clock_input_freq_MHz = 1.69;
integer same_period_count = 0;
integer different_period_count = 0;
integer same_period_count_last = 0;
integer count_clks = 0;
real ref_clock_input_freq_MHz_min = 400.000; // valid min freq in MHz
real ref_clock_input_freq_MHz_max = 1066.000; // valid max freq in MHz
reg IS_PWRDWN_INVERTED_BIN = IS_PWRDWN_INVERTED;
reg IS_RST_INVERTED_BIN = IS_RST_INVERTED;
assign #(out_delay) LOCKED = delay_LOCKED;
assign #(INCLK_DELAY) delay_CLKIN = CLKIN;
assign #(in_delay) delay_PWRDWN = PWRDWN ^ IS_PWRDWN_INVERTED_BIN;
assign #(in_delay) delay_RST = RST ^ IS_RST_INVERTED_BIN;
assign delay_GSR = GSR;
always @(posedge delay_CLKIN)
begin
last_ref_clock_input_period <= ref_clock_input_period;
last_ref_clock_input_freq_MHz <= ref_clock_input_freq_MHz;
same_period_count_last <= same_period_count;
ref_clock_input_period <= $time - time_last_rising_edge;
ref_clock_input_freq_MHz <= 1e6/($time - time_last_rising_edge);
time_last_rising_edge <= $time/1.0;
if ( (delay_RST==0) && (delay_PWRDWN ==0) &&
(ref_clock_input_period - last_ref_clock_input_period <= REF_CLK_JITTER_MAX) &&
(last_ref_clock_input_period - ref_clock_input_period <= REF_CLK_JITTER_MAX) )
begin
if (same_period_count < 6) same_period_count <= same_period_count + 1;
if ( same_period_count >= 3 && same_period_count != same_period_count_last && different_period_count != 0)
begin
different_period_count <= 0; //reset different_period_count
end
end
else // detecting different clock-preiod
begin
different_period_count = different_period_count + 1;
if ( different_period_count >= 1 && same_period_count != 0 )
begin
same_period_count <= 0 ; //reset same_period_count
end
end
end
always @(posedge delay_CLKIN or posedge delay_RST or posedge delay_PWRDWN) begin
if ( delay_RST||delay_PWRDWN)
begin
delay_LOCKED <= 1'b0;
count_clks <= 0;
end
else if ((same_period_count >= 1) && (count_clks < 6))
begin
count_clks <= count_clks + 1;
end
else if (different_period_count >= 1)
begin
delay_LOCKED <= 1'b0;
count_clks <= 0;
end
else if ( (count_clks >= 5) &&
((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 >= ref_clock_input_freq_MHz_min ) &&
((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 <= ref_clock_input_freq_MHz_max ) )
begin
delay_LOCKED <= 1'b1;
end
end
always @(posedge delay_CLKIN)
if ( (count_clks == 5) &&
( ((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 < ref_clock_input_freq_MHz_min) ||
((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 > ref_clock_input_freq_MHz_max) ) ) begin
$display("Warning: Invalid average CLKIN frequency detected = %4.3f MHz", (ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000);
$display(" on %s instance %m at time %t ps.", MODULE_NAME, $time);
$display(" The valid CLKIN frequency range is:");
$display(" Minimum = %4.3f MHz", ref_clock_input_freq_MHz_min );
$display(" Maximum = %4.3f MHz", ref_clock_input_freq_MHz_max );
end
`ifdef XIL_TIMING
specify
$period (negedge CLKIN, 0:0:0, notifier);
$period (posedge CLKIN, 0:0:0, notifier);
$width (negedge CLKIN, 0:0:0, 0, notifier);
$width (posedge CLKIN, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // PHASER_REF
`endcelldefine
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17.03.2016 10:17:01
// Design Name:
// Module Name: memory
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MEMORY(
input [9:0] ADDR,
input CLK,
input RE,
input INIT,
output reg [10:0] DATAOUT = 0
);
reg[11:0] storage[0:1023];
always @(posedge CLK)
begin
DATAOUT <= (RE) ? storage[ADDR] : DATAOUT;
// Pythom help us
storage[0] <= (INIT) ? 12'd2048 : storage[0];
storage[1] <= (INIT) ? 12'd2060 : storage[1];
storage[2] <= (INIT) ? 12'd2073 : storage[2];
storage[3] <= (INIT) ? 12'd2086 : storage[3];
storage[4] <= (INIT) ? 12'd2099 : storage[4];
storage[5] <= (INIT) ? 12'd2112 : storage[5];
storage[6] <= (INIT) ? 12'd2125 : storage[6];
storage[7] <= (INIT) ? 12'd2138 : storage[7];
storage[8] <= (INIT) ? 12'd2150 : storage[8];
storage[9] <= (INIT) ? 12'd2163 : storage[9];
storage[10] <= (INIT) ? 12'd2176 : storage[10];
storage[11] <= (INIT) ? 12'd2189 : storage[11];
storage[12] <= (INIT) ? 12'd2202 : storage[12];
storage[13] <= (INIT) ? 12'd2215 : storage[13];
storage[14] <= (INIT) ? 12'd2227 : storage[14];
storage[15] <= (INIT) ? 12'd2240 : storage[15];
storage[16] <= (INIT) ? 12'd2253 : storage[16];
storage[17] <= (INIT) ? 12'd2266 : storage[17];
storage[18] <= (INIT) ? 12'd2279 : storage[18];
storage[19] <= (INIT) ? 12'd2291 : storage[19];
storage[20] <= (INIT) ? 12'd2304 : storage[20];
storage[21] <= (INIT) ? 12'd2317 : storage[21];
storage[22] <= (INIT) ? 12'd2330 : storage[22];
storage[23] <= (INIT) ? 12'd2342 : storage[23];
storage[24] <= (INIT) ? 12'd2355 : storage[24];
storage[25] <= (INIT) ? 12'd2368 : storage[25];
storage[26] <= (INIT) ? 12'd2380 : storage[26];
storage[27] <= (INIT) ? 12'd2393 : storage[27];
storage[28] <= (INIT) ? 12'd2406 : storage[28];
storage[29] <= (INIT) ? 12'd2418 : storage[29];
storage[30] <= (INIT) ? 12'd2431 : storage[30];
storage[31] <= (INIT) ? 12'd2444 : storage[31];
storage[32] <= (INIT) ? 12'd2456 : storage[32];
storage[33] <= (INIT) ? 12'd2469 : storage[33];
storage[34] <= (INIT) ? 12'd2481 : storage[34];
storage[35] <= (INIT) ? 12'd2494 : storage[35];
storage[36] <= (INIT) ? 12'd2507 : storage[36];
storage[37] <= (INIT) ? 12'd2519 : storage[37];
storage[38] <= (INIT) ? 12'd2532 : storage[38];
storage[39] <= (INIT) ? 12'd2544 : storage[39];
storage[40] <= (INIT) ? 12'd2557 : storage[40];
storage[41] <= (INIT) ? 12'd2569 : storage[41];
storage[42] <= (INIT) ? 12'd2581 : storage[42];
storage[43] <= (INIT) ? 12'd2594 : storage[43];
storage[44] <= (INIT) ? 12'd2606 : storage[44];
storage[45] <= (INIT) ? 12'd2619 : storage[45];
storage[46] <= (INIT) ? 12'd2631 : storage[46];
storage[47] <= (INIT) ? 12'd2643 : storage[47];
storage[48] <= (INIT) ? 12'd2656 : storage[48];
storage[49] <= (INIT) ? 12'd2668 : storage[49];
storage[50] <= (INIT) ? 12'd2680 : storage[50];
storage[51] <= (INIT) ? 12'd2692 : storage[51];
storage[52] <= (INIT) ? 12'd2704 : storage[52];
storage[53] <= (INIT) ? 12'd2717 : storage[53];
storage[54] <= (INIT) ? 12'd2729 : storage[54];
storage[55] <= (INIT) ? 12'd2741 : storage[55];
storage[56] <= (INIT) ? 12'd2753 : storage[56];
storage[57] <= (INIT) ? 12'd2765 : storage[57];
storage[58] <= (INIT) ? 12'd2777 : storage[58];
storage[59] <= (INIT) ? 12'd2789 : storage[59];
storage[60] <= (INIT) ? 12'd2801 : storage[60];
storage[61] <= (INIT) ? 12'd2813 : storage[61];
storage[62] <= (INIT) ? 12'd2825 : storage[62];
storage[63] <= (INIT) ? 12'd2837 : storage[63];
storage[64] <= (INIT) ? 12'd2849 : storage[64];
storage[65] <= (INIT) ? 12'd2860 : storage[65];
storage[66] <= (INIT) ? 12'd2872 : storage[66];
storage[67] <= (INIT) ? 12'd2884 : storage[67];
storage[68] <= (INIT) ? 12'd2896 : storage[68];
storage[69] <= (INIT) ? 12'd2907 : storage[69];
storage[70] <= (INIT) ? 12'd2919 : storage[70];
storage[71] <= (INIT) ? 12'd2931 : storage[71];
storage[72] <= (INIT) ? 12'd2942 : storage[72];
storage[73] <= (INIT) ? 12'd2954 : storage[73];
storage[74] <= (INIT) ? 12'd2965 : storage[74];
storage[75] <= (INIT) ? 12'd2977 : storage[75];
storage[76] <= (INIT) ? 12'd2988 : storage[76];
storage[77] <= (INIT) ? 12'd3000 : storage[77];
storage[78] <= (INIT) ? 12'd3011 : storage[78];
storage[79] <= (INIT) ? 12'd3022 : storage[79];
storage[80] <= (INIT) ? 12'd3034 : storage[80];
storage[81] <= (INIT) ? 12'd3045 : storage[81];
storage[82] <= (INIT) ? 12'd3056 : storage[82];
storage[83] <= (INIT) ? 12'd3067 : storage[83];
storage[84] <= (INIT) ? 12'd3078 : storage[84];
storage[85] <= (INIT) ? 12'd3090 : storage[85];
storage[86] <= (INIT) ? 12'd3101 : storage[86];
storage[87] <= (INIT) ? 12'd3112 : storage[87];
storage[88] <= (INIT) ? 12'd3123 : storage[88];
storage[89] <= (INIT) ? 12'd3133 : storage[89];
storage[90] <= (INIT) ? 12'd3144 : storage[90];
storage[91] <= (INIT) ? 12'd3155 : storage[91];
storage[92] <= (INIT) ? 12'd3166 : storage[92];
storage[93] <= (INIT) ? 12'd3177 : storage[93];
storage[94] <= (INIT) ? 12'd3187 : storage[94];
storage[95] <= (INIT) ? 12'd3198 : storage[95];
storage[96] <= (INIT) ? 12'd3209 : storage[96];
storage[97] <= (INIT) ? 12'd3219 : storage[97];
storage[98] <= (INIT) ? 12'd3230 : storage[98];
storage[99] <= (INIT) ? 12'd3240 : storage[99];
storage[100] <= (INIT) ? 12'd3251 : storage[100];
storage[101] <= (INIT) ? 12'd3261 : storage[101];
storage[102] <= (INIT) ? 12'd3271 : storage[102];
storage[103] <= (INIT) ? 12'd3282 : storage[103];
storage[104] <= (INIT) ? 12'd3292 : storage[104];
storage[105] <= (INIT) ? 12'd3302 : storage[105];
storage[106] <= (INIT) ? 12'd3312 : storage[106];
storage[107] <= (INIT) ? 12'd3322 : storage[107];
storage[108] <= (INIT) ? 12'd3332 : storage[108];
storage[109] <= (INIT) ? 12'd3342 : storage[109];
storage[110] <= (INIT) ? 12'd3352 : storage[110];
storage[111] <= (INIT) ? 12'd3362 : storage[111];
storage[112] <= (INIT) ? 12'd3372 : storage[112];
storage[113] <= (INIT) ? 12'd3382 : storage[113];
storage[114] <= (INIT) ? 12'd3392 : storage[114];
storage[115] <= (INIT) ? 12'd3401 : storage[115];
storage[116] <= (INIT) ? 12'd3411 : storage[116];
storage[117] <= (INIT) ? 12'd3420 : storage[117];
storage[118] <= (INIT) ? 12'd3430 : storage[118];
storage[119] <= (INIT) ? 12'd3439 : storage[119];
storage[120] <= (INIT) ? 12'd3449 : storage[120];
storage[121] <= (INIT) ? 12'd3458 : storage[121];
storage[122] <= (INIT) ? 12'd3468 : storage[122];
storage[123] <= (INIT) ? 12'd3477 : storage[123];
storage[124] <= (INIT) ? 12'd3486 : storage[124];
storage[125] <= (INIT) ? 12'd3495 : storage[125];
storage[126] <= (INIT) ? 12'd3504 : storage[126];
storage[127] <= (INIT) ? 12'd3513 : storage[127];
storage[128] <= (INIT) ? 12'd3522 : storage[128];
storage[129] <= (INIT) ? 12'd3531 : storage[129];
storage[130] <= (INIT) ? 12'd3540 : storage[130];
storage[131] <= (INIT) ? 12'd3549 : storage[131];
storage[132] <= (INIT) ? 12'd3557 : storage[132];
storage[133] <= (INIT) ? 12'd3566 : storage[133];
storage[134] <= (INIT) ? 12'd3575 : storage[134];
storage[135] <= (INIT) ? 12'd3583 : storage[135];
storage[136] <= (INIT) ? 12'd3592 : storage[136];
storage[137] <= (INIT) ? 12'd3600 : storage[137];
storage[138] <= (INIT) ? 12'd3608 : storage[138];
storage[139] <= (INIT) ? 12'd3617 : storage[139];
storage[140] <= (INIT) ? 12'd3625 : storage[140];
storage[141] <= (INIT) ? 12'd3633 : storage[141];
storage[142] <= (INIT) ? 12'd3641 : storage[142];
storage[143] <= (INIT) ? 12'd3649 : storage[143];
storage[144] <= (INIT) ? 12'd3657 : storage[144];
storage[145] <= (INIT) ? 12'd3665 : storage[145];
storage[146] <= (INIT) ? 12'd3673 : storage[146];
storage[147] <= (INIT) ? 12'd3681 : storage[147];
storage[148] <= (INIT) ? 12'd3689 : storage[148];
storage[149] <= (INIT) ? 12'd3696 : storage[149];
storage[150] <= (INIT) ? 12'd3704 : storage[150];
storage[151] <= (INIT) ? 12'd3711 : storage[151];
storage[152] <= (INIT) ? 12'd3719 : storage[152];
storage[153] <= (INIT) ? 12'd3726 : storage[153];
storage[154] <= (INIT) ? 12'd3734 : storage[154];
storage[155] <= (INIT) ? 12'd3741 : storage[155];
storage[156] <= (INIT) ? 12'd3748 : storage[156];
storage[157] <= (INIT) ? 12'd3755 : storage[157];
storage[158] <= (INIT) ? 12'd3762 : storage[158];
storage[159] <= (INIT) ? 12'd3769 : storage[159];
storage[160] <= (INIT) ? 12'd3776 : storage[160];
storage[161] <= (INIT) ? 12'd3783 : storage[161];
storage[162] <= (INIT) ? 12'd3790 : storage[162];
storage[163] <= (INIT) ? 12'd3797 : storage[163];
storage[164] <= (INIT) ? 12'd3803 : storage[164];
storage[165] <= (INIT) ? 12'd3810 : storage[165];
storage[166] <= (INIT) ? 12'd3816 : storage[166];
storage[167] <= (INIT) ? 12'd3823 : storage[167];
storage[168] <= (INIT) ? 12'd3829 : storage[168];
storage[169] <= (INIT) ? 12'd3835 : storage[169];
storage[170] <= (INIT) ? 12'd3842 : storage[170];
storage[171] <= (INIT) ? 12'd3848 : storage[171];
storage[172] <= (INIT) ? 12'd3854 : storage[172];
storage[173] <= (INIT) ? 12'd3860 : storage[173];
storage[174] <= (INIT) ? 12'd3866 : storage[174];
storage[175] <= (INIT) ? 12'd3872 : storage[175];
storage[176] <= (INIT) ? 12'd3878 : storage[176];
storage[177] <= (INIT) ? 12'd3883 : storage[177];
storage[178] <= (INIT) ? 12'd3889 : storage[178];
storage[179] <= (INIT) ? 12'd3895 : storage[179];
storage[180] <= (INIT) ? 12'd3900 : storage[180];
storage[181] <= (INIT) ? 12'd3906 : storage[181];
storage[182] <= (INIT) ? 12'd3911 : storage[182];
storage[183] <= (INIT) ? 12'd3916 : storage[183];
storage[184] <= (INIT) ? 12'd3921 : storage[184];
storage[185] <= (INIT) ? 12'd3927 : storage[185];
storage[186] <= (INIT) ? 12'd3932 : storage[186];
storage[187] <= (INIT) ? 12'd3937 : storage[187];
storage[188] <= (INIT) ? 12'd3942 : storage[188];
storage[189] <= (INIT) ? 12'd3946 : storage[189];
storage[190] <= (INIT) ? 12'd3951 : storage[190];
storage[191] <= (INIT) ? 12'd3956 : storage[191];
storage[192] <= (INIT) ? 12'd3961 : storage[192];
storage[193] <= (INIT) ? 12'd3965 : storage[193];
storage[194] <= (INIT) ? 12'd3970 : storage[194];
storage[195] <= (INIT) ? 12'd3974 : storage[195];
storage[196] <= (INIT) ? 12'd3978 : storage[196];
storage[197] <= (INIT) ? 12'd3983 : storage[197];
storage[198] <= (INIT) ? 12'd3987 : storage[198];
storage[199] <= (INIT) ? 12'd3991 : storage[199];
storage[200] <= (INIT) ? 12'd3995 : storage[200];
storage[201] <= (INIT) ? 12'd3999 : storage[201];
storage[202] <= (INIT) ? 12'd4003 : storage[202];
storage[203] <= (INIT) ? 12'd4006 : storage[203];
storage[204] <= (INIT) ? 12'd4010 : storage[204];
storage[205] <= (INIT) ? 12'd4014 : storage[205];
storage[206] <= (INIT) ? 12'd4017 : storage[206];
storage[207] <= (INIT) ? 12'd4021 : storage[207];
storage[208] <= (INIT) ? 12'd4024 : storage[208];
storage[209] <= (INIT) ? 12'd4028 : storage[209];
storage[210] <= (INIT) ? 12'd4031 : storage[210];
storage[211] <= (INIT) ? 12'd4034 : storage[211];
storage[212] <= (INIT) ? 12'd4037 : storage[212];
storage[213] <= (INIT) ? 12'd4040 : storage[213];
storage[214] <= (INIT) ? 12'd4043 : storage[214];
storage[215] <= (INIT) ? 12'd4046 : storage[215];
storage[216] <= (INIT) ? 12'd4049 : storage[216];
storage[217] <= (INIT) ? 12'd4051 : storage[217];
storage[218] <= (INIT) ? 12'd4054 : storage[218];
storage[219] <= (INIT) ? 12'd4056 : storage[219];
storage[220] <= (INIT) ? 12'd4059 : storage[220];
storage[221] <= (INIT) ? 12'd4061 : storage[221];
storage[222] <= (INIT) ? 12'd4064 : storage[222];
storage[223] <= (INIT) ? 12'd4066 : storage[223];
storage[224] <= (INIT) ? 12'd4068 : storage[224];
storage[225] <= (INIT) ? 12'd4070 : storage[225];
storage[226] <= (INIT) ? 12'd4072 : storage[226];
storage[227] <= (INIT) ? 12'd4074 : storage[227];
storage[228] <= (INIT) ? 12'd4076 : storage[228];
storage[229] <= (INIT) ? 12'd4078 : storage[229];
storage[230] <= (INIT) ? 12'd4079 : storage[230];
storage[231] <= (INIT) ? 12'd4081 : storage[231];
storage[232] <= (INIT) ? 12'd4082 : storage[232];
storage[233] <= (INIT) ? 12'd4084 : storage[233];
storage[234] <= (INIT) ? 12'd4085 : storage[234];
storage[235] <= (INIT) ? 12'd4086 : storage[235];
storage[236] <= (INIT) ? 12'd4087 : storage[236];
storage[237] <= (INIT) ? 12'd4089 : storage[237];
storage[238] <= (INIT) ? 12'd4090 : storage[238];
storage[239] <= (INIT) ? 12'd4091 : storage[239];
storage[240] <= (INIT) ? 12'd4091 : storage[240];
storage[241] <= (INIT) ? 12'd4092 : storage[241];
storage[242] <= (INIT) ? 12'd4093 : storage[242];
storage[243] <= (INIT) ? 12'd4093 : storage[243];
storage[244] <= (INIT) ? 12'd4094 : storage[244];
storage[245] <= (INIT) ? 12'd4094 : storage[245];
storage[246] <= (INIT) ? 12'd4095 : storage[246];
storage[247] <= (INIT) ? 12'd4095 : storage[247];
storage[248] <= (INIT) ? 12'd4095 : storage[248];
storage[249] <= (INIT) ? 12'd4095 : storage[249];
storage[250] <= (INIT) ? 12'd4095 : storage[250];
storage[251] <= (INIT) ? 12'd4095 : storage[251];
storage[252] <= (INIT) ? 12'd4095 : storage[252];
storage[253] <= (INIT) ? 12'd4095 : storage[253];
storage[254] <= (INIT) ? 12'd4095 : storage[254];
storage[255] <= (INIT) ? 12'd4095 : storage[255];
storage[256] <= (INIT) ? 12'd4094 : storage[256];
storage[257] <= (INIT) ? 12'd4094 : storage[257];
storage[258] <= (INIT) ? 12'd4093 : storage[258];
storage[259] <= (INIT) ? 12'd4092 : storage[259];
storage[260] <= (INIT) ? 12'd4092 : storage[260];
storage[261] <= (INIT) ? 12'd4091 : storage[261];
storage[262] <= (INIT) ? 12'd4090 : storage[262];
storage[263] <= (INIT) ? 12'd4089 : storage[263];
storage[264] <= (INIT) ? 12'd4088 : storage[264];
storage[265] <= (INIT) ? 12'd4087 : storage[265];
storage[266] <= (INIT) ? 12'd4085 : storage[266];
storage[267] <= (INIT) ? 12'd4084 : storage[267];
storage[268] <= (INIT) ? 12'd4083 : storage[268];
storage[269] <= (INIT) ? 12'd4081 : storage[269];
storage[270] <= (INIT) ? 12'd4080 : storage[270];
storage[271] <= (INIT) ? 12'd4078 : storage[271];
storage[272] <= (INIT) ? 12'd4076 : storage[272];
storage[273] <= (INIT) ? 12'd4074 : storage[273];
storage[274] <= (INIT) ? 12'd4073 : storage[274];
storage[275] <= (INIT) ? 12'd4071 : storage[275];
storage[276] <= (INIT) ? 12'd4069 : storage[276];
storage[277] <= (INIT) ? 12'd4066 : storage[277];
storage[278] <= (INIT) ? 12'd4064 : storage[278];
storage[279] <= (INIT) ? 12'd4062 : storage[279];
storage[280] <= (INIT) ? 12'd4060 : storage[280];
storage[281] <= (INIT) ? 12'd4057 : storage[281];
storage[282] <= (INIT) ? 12'd4055 : storage[282];
storage[283] <= (INIT) ? 12'd4052 : storage[283];
storage[284] <= (INIT) ? 12'd4049 : storage[284];
storage[285] <= (INIT) ? 12'd4047 : storage[285];
storage[286] <= (INIT) ? 12'd4044 : storage[286];
storage[287] <= (INIT) ? 12'd4041 : storage[287];
storage[288] <= (INIT) ? 12'd4038 : storage[288];
storage[289] <= (INIT) ? 12'd4035 : storage[289];
storage[290] <= (INIT) ? 12'd4032 : storage[290];
storage[291] <= (INIT) ? 12'd4028 : storage[291];
storage[292] <= (INIT) ? 12'd4025 : storage[292];
storage[293] <= (INIT) ? 12'd4022 : storage[293];
storage[294] <= (INIT) ? 12'd4018 : storage[294];
storage[295] <= (INIT) ? 12'd4015 : storage[295];
storage[296] <= (INIT) ? 12'd4011 : storage[296];
storage[297] <= (INIT) ? 12'd4007 : storage[297];
storage[298] <= (INIT) ? 12'd4004 : storage[298];
storage[299] <= (INIT) ? 12'd4000 : storage[299];
storage[300] <= (INIT) ? 12'd3996 : storage[300];
storage[301] <= (INIT) ? 12'd3992 : storage[301];
storage[302] <= (INIT) ? 12'd3988 : storage[302];
storage[303] <= (INIT) ? 12'd3984 : storage[303];
storage[304] <= (INIT) ? 12'd3979 : storage[304];
storage[305] <= (INIT) ? 12'd3975 : storage[305];
storage[306] <= (INIT) ? 12'd3971 : storage[306];
storage[307] <= (INIT) ? 12'd3966 : storage[307];
storage[308] <= (INIT) ? 12'd3962 : storage[308];
storage[309] <= (INIT) ? 12'd3957 : storage[309];
storage[310] <= (INIT) ? 12'd3952 : storage[310];
storage[311] <= (INIT) ? 12'd3948 : storage[311];
storage[312] <= (INIT) ? 12'd3943 : storage[312];
storage[313] <= (INIT) ? 12'd3938 : storage[313];
storage[314] <= (INIT) ? 12'd3933 : storage[314];
storage[315] <= (INIT) ? 12'd3928 : storage[315];
storage[316] <= (INIT) ? 12'd3923 : storage[316];
storage[317] <= (INIT) ? 12'd3918 : storage[317];
storage[318] <= (INIT) ? 12'd3912 : storage[318];
storage[319] <= (INIT) ? 12'd3907 : storage[319];
storage[320] <= (INIT) ? 12'd3901 : storage[320];
storage[321] <= (INIT) ? 12'd3896 : storage[321];
storage[322] <= (INIT) ? 12'd3890 : storage[322];
storage[323] <= (INIT) ? 12'd3885 : storage[323];
storage[324] <= (INIT) ? 12'd3879 : storage[324];
storage[325] <= (INIT) ? 12'd3873 : storage[325];
storage[326] <= (INIT) ? 12'd3867 : storage[326];
storage[327] <= (INIT) ? 12'd3861 : storage[327];
storage[328] <= (INIT) ? 12'd3855 : storage[328];
storage[329] <= (INIT) ? 12'd3849 : storage[329];
storage[330] <= (INIT) ? 12'd3843 : storage[330];
storage[331] <= (INIT) ? 12'd3837 : storage[331];
storage[332] <= (INIT) ? 12'd3831 : storage[332];
storage[333] <= (INIT) ? 12'd3824 : storage[333];
storage[334] <= (INIT) ? 12'd3818 : storage[334];
storage[335] <= (INIT) ? 12'd3811 : storage[335];
storage[336] <= (INIT) ? 12'd3805 : storage[336];
storage[337] <= (INIT) ? 12'd3798 : storage[337];
storage[338] <= (INIT) ? 12'd3791 : storage[338];
storage[339] <= (INIT) ? 12'd3785 : storage[339];
storage[340] <= (INIT) ? 12'd3778 : storage[340];
storage[341] <= (INIT) ? 12'd3771 : storage[341];
storage[342] <= (INIT) ? 12'd3764 : storage[342];
storage[343] <= (INIT) ? 12'd3757 : storage[343];
storage[344] <= (INIT) ? 12'd3750 : storage[344];
storage[345] <= (INIT) ? 12'd3743 : storage[345];
storage[346] <= (INIT) ? 12'd3735 : storage[346];
storage[347] <= (INIT) ? 12'd3728 : storage[347];
storage[348] <= (INIT) ? 12'd3721 : storage[348];
storage[349] <= (INIT) ? 12'd3713 : storage[349];
storage[350] <= (INIT) ? 12'd3706 : storage[350];
storage[351] <= (INIT) ? 12'd3698 : storage[351];
storage[352] <= (INIT) ? 12'd3690 : storage[352];
storage[353] <= (INIT) ? 12'd3683 : storage[353];
storage[354] <= (INIT) ? 12'd3675 : storage[354];
storage[355] <= (INIT) ? 12'd3667 : storage[355];
storage[356] <= (INIT) ? 12'd3659 : storage[356];
storage[357] <= (INIT) ? 12'd3651 : storage[357];
storage[358] <= (INIT) ? 12'd3643 : storage[358];
storage[359] <= (INIT) ? 12'd3635 : storage[359];
storage[360] <= (INIT) ? 12'd3627 : storage[360];
storage[361] <= (INIT) ? 12'd3619 : storage[361];
storage[362] <= (INIT) ? 12'd3611 : storage[362];
storage[363] <= (INIT) ? 12'd3602 : storage[363];
storage[364] <= (INIT) ? 12'd3594 : storage[364];
storage[365] <= (INIT) ? 12'd3585 : storage[365];
storage[366] <= (INIT) ? 12'd3577 : storage[366];
storage[367] <= (INIT) ? 12'd3568 : storage[367];
storage[368] <= (INIT) ? 12'd3560 : storage[368];
storage[369] <= (INIT) ? 12'd3551 : storage[369];
storage[370] <= (INIT) ? 12'd3542 : storage[370];
storage[371] <= (INIT) ? 12'd3533 : storage[371];
storage[372] <= (INIT) ? 12'd3524 : storage[372];
storage[373] <= (INIT) ? 12'd3515 : storage[373];
storage[374] <= (INIT) ? 12'd3506 : storage[374];
storage[375] <= (INIT) ? 12'd3497 : storage[375];
storage[376] <= (INIT) ? 12'd3488 : storage[376];
storage[377] <= (INIT) ? 12'd3479 : storage[377];
storage[378] <= (INIT) ? 12'd3470 : storage[378];
storage[379] <= (INIT) ? 12'd3461 : storage[379];
storage[380] <= (INIT) ? 12'd3451 : storage[380];
storage[381] <= (INIT) ? 12'd3442 : storage[381];
storage[382] <= (INIT) ? 12'd3432 : storage[382];
storage[383] <= (INIT) ? 12'd3423 : storage[383];
storage[384] <= (INIT) ? 12'd3413 : storage[384];
storage[385] <= (INIT) ? 12'd3404 : storage[385];
storage[386] <= (INIT) ? 12'd3394 : storage[386];
storage[387] <= (INIT) ? 12'd3384 : storage[387];
storage[388] <= (INIT) ? 12'd3375 : storage[388];
storage[389] <= (INIT) ? 12'd3365 : storage[389];
storage[390] <= (INIT) ? 12'd3355 : storage[390];
storage[391] <= (INIT) ? 12'd3345 : storage[391];
storage[392] <= (INIT) ? 12'd3335 : storage[392];
storage[393] <= (INIT) ? 12'd3325 : storage[393];
storage[394] <= (INIT) ? 12'd3315 : storage[394];
storage[395] <= (INIT) ? 12'd3305 : storage[395];
storage[396] <= (INIT) ? 12'd3295 : storage[396];
storage[397] <= (INIT) ? 12'd3284 : storage[397];
storage[398] <= (INIT) ? 12'd3274 : storage[398];
storage[399] <= (INIT) ? 12'd3264 : storage[399];
storage[400] <= (INIT) ? 12'd3253 : storage[400];
storage[401] <= (INIT) ? 12'd3243 : storage[401];
storage[402] <= (INIT) ? 12'd3233 : storage[402];
storage[403] <= (INIT) ? 12'd3222 : storage[403];
storage[404] <= (INIT) ? 12'd3211 : storage[404];
storage[405] <= (INIT) ? 12'd3201 : storage[405];
storage[406] <= (INIT) ? 12'd3190 : storage[406];
storage[407] <= (INIT) ? 12'd3179 : storage[407];
storage[408] <= (INIT) ? 12'd3169 : storage[408];
storage[409] <= (INIT) ? 12'd3158 : storage[409];
storage[410] <= (INIT) ? 12'd3147 : storage[410];
storage[411] <= (INIT) ? 12'd3136 : storage[411];
storage[412] <= (INIT) ? 12'd3125 : storage[412];
storage[413] <= (INIT) ? 12'd3114 : storage[413];
storage[414] <= (INIT) ? 12'd3103 : storage[414];
storage[415] <= (INIT) ? 12'd3092 : storage[415];
storage[416] <= (INIT) ? 12'd3081 : storage[416];
storage[417] <= (INIT) ? 12'd3070 : storage[417];
storage[418] <= (INIT) ? 12'd3059 : storage[418];
storage[419] <= (INIT) ? 12'd3048 : storage[419];
storage[420] <= (INIT) ? 12'd3037 : storage[420];
storage[421] <= (INIT) ? 12'd3025 : storage[421];
storage[422] <= (INIT) ? 12'd3014 : storage[422];
storage[423] <= (INIT) ? 12'd3003 : storage[423];
storage[424] <= (INIT) ? 12'd2991 : storage[424];
storage[425] <= (INIT) ? 12'd2980 : storage[425];
storage[426] <= (INIT) ? 12'd2968 : storage[426];
storage[427] <= (INIT) ? 12'd2957 : storage[427];
storage[428] <= (INIT) ? 12'd2945 : storage[428];
storage[429] <= (INIT) ? 12'd2934 : storage[429];
storage[430] <= (INIT) ? 12'd2922 : storage[430];
storage[431] <= (INIT) ? 12'd2910 : storage[431];
storage[432] <= (INIT) ? 12'd2899 : storage[432];
storage[433] <= (INIT) ? 12'd2887 : storage[433];
storage[434] <= (INIT) ? 12'd2875 : storage[434];
storage[435] <= (INIT) ? 12'd2863 : storage[435];
storage[436] <= (INIT) ? 12'd2852 : storage[436];
storage[437] <= (INIT) ? 12'd2840 : storage[437];
storage[438] <= (INIT) ? 12'd2828 : storage[438];
storage[439] <= (INIT) ? 12'd2816 : storage[439];
storage[440] <= (INIT) ? 12'd2804 : storage[440];
storage[441] <= (INIT) ? 12'd2792 : storage[441];
storage[442] <= (INIT) ? 12'd2780 : storage[442];
storage[443] <= (INIT) ? 12'd2768 : storage[443];
storage[444] <= (INIT) ? 12'd2756 : storage[444];
storage[445] <= (INIT) ? 12'd2744 : storage[445];
storage[446] <= (INIT) ? 12'd2732 : storage[446];
storage[447] <= (INIT) ? 12'd2720 : storage[447];
storage[448] <= (INIT) ? 12'd2708 : storage[448];
storage[449] <= (INIT) ? 12'd2695 : storage[449];
storage[450] <= (INIT) ? 12'd2683 : storage[450];
storage[451] <= (INIT) ? 12'd2671 : storage[451];
storage[452] <= (INIT) ? 12'd2659 : storage[452];
storage[453] <= (INIT) ? 12'd2646 : storage[453];
storage[454] <= (INIT) ? 12'd2634 : storage[454];
storage[455] <= (INIT) ? 12'd2622 : storage[455];
storage[456] <= (INIT) ? 12'd2609 : storage[456];
storage[457] <= (INIT) ? 12'd2597 : storage[457];
storage[458] <= (INIT) ? 12'd2585 : storage[458];
storage[459] <= (INIT) ? 12'd2572 : storage[459];
storage[460] <= (INIT) ? 12'd2560 : storage[460];
storage[461] <= (INIT) ? 12'd2547 : storage[461];
storage[462] <= (INIT) ? 12'd2535 : storage[462];
storage[463] <= (INIT) ? 12'd2522 : storage[463];
storage[464] <= (INIT) ? 12'd2510 : storage[464];
storage[465] <= (INIT) ? 12'd2497 : storage[465];
storage[466] <= (INIT) ? 12'd2485 : storage[466];
storage[467] <= (INIT) ? 12'd2472 : storage[467];
storage[468] <= (INIT) ? 12'd2459 : storage[468];
storage[469] <= (INIT) ? 12'd2447 : storage[469];
storage[470] <= (INIT) ? 12'd2434 : storage[470];
storage[471] <= (INIT) ? 12'd2422 : storage[471];
storage[472] <= (INIT) ? 12'd2409 : storage[472];
storage[473] <= (INIT) ? 12'd2396 : storage[473];
storage[474] <= (INIT) ? 12'd2384 : storage[474];
storage[475] <= (INIT) ? 12'd2371 : storage[475];
storage[476] <= (INIT) ? 12'd2358 : storage[476];
storage[477] <= (INIT) ? 12'd2346 : storage[477];
storage[478] <= (INIT) ? 12'd2333 : storage[478];
storage[479] <= (INIT) ? 12'd2320 : storage[479];
storage[480] <= (INIT) ? 12'd2307 : storage[480];
storage[481] <= (INIT) ? 12'd2295 : storage[481];
storage[482] <= (INIT) ? 12'd2282 : storage[482];
storage[483] <= (INIT) ? 12'd2269 : storage[483];
storage[484] <= (INIT) ? 12'd2256 : storage[484];
storage[485] <= (INIT) ? 12'd2243 : storage[485];
storage[486] <= (INIT) ? 12'd2231 : storage[486];
storage[487] <= (INIT) ? 12'd2218 : storage[487];
storage[488] <= (INIT) ? 12'd2205 : storage[488];
storage[489] <= (INIT) ? 12'd2192 : storage[489];
storage[490] <= (INIT) ? 12'd2179 : storage[490];
storage[491] <= (INIT) ? 12'd2166 : storage[491];
storage[492] <= (INIT) ? 12'd2154 : storage[492];
storage[493] <= (INIT) ? 12'd2141 : storage[493];
storage[494] <= (INIT) ? 12'd2128 : storage[494];
storage[495] <= (INIT) ? 12'd2115 : storage[495];
storage[496] <= (INIT) ? 12'd2102 : storage[496];
storage[497] <= (INIT) ? 12'd2089 : storage[497];
storage[498] <= (INIT) ? 12'd2076 : storage[498];
storage[499] <= (INIT) ? 12'd2064 : storage[499];
storage[500] <= (INIT) ? 12'd2051 : storage[500];
storage[501] <= (INIT) ? 12'd2038 : storage[501];
storage[502] <= (INIT) ? 12'd2025 : storage[502];
storage[503] <= (INIT) ? 12'd2012 : storage[503];
storage[504] <= (INIT) ? 12'd1999 : storage[504];
storage[505] <= (INIT) ? 12'd1986 : storage[505];
storage[506] <= (INIT) ? 12'd1974 : storage[506];
storage[507] <= (INIT) ? 12'd1961 : storage[507];
storage[508] <= (INIT) ? 12'd1948 : storage[508];
storage[509] <= (INIT) ? 12'd1935 : storage[509];
storage[510] <= (INIT) ? 12'd1922 : storage[510];
storage[511] <= (INIT) ? 12'd1909 : storage[511];
storage[512] <= (INIT) ? 12'd1897 : storage[512];
storage[513] <= (INIT) ? 12'd1884 : storage[513];
storage[514] <= (INIT) ? 12'd1871 : storage[514];
storage[515] <= (INIT) ? 12'd1858 : storage[515];
storage[516] <= (INIT) ? 12'd1845 : storage[516];
storage[517] <= (INIT) ? 12'd1833 : storage[517];
storage[518] <= (INIT) ? 12'd1820 : storage[518];
storage[519] <= (INIT) ? 12'd1807 : storage[519];
storage[520] <= (INIT) ? 12'd1794 : storage[520];
storage[521] <= (INIT) ? 12'd1781 : storage[521];
storage[522] <= (INIT) ? 12'd1769 : storage[522];
storage[523] <= (INIT) ? 12'd1756 : storage[523];
storage[524] <= (INIT) ? 12'd1743 : storage[524];
storage[525] <= (INIT) ? 12'd1731 : storage[525];
storage[526] <= (INIT) ? 12'd1718 : storage[526];
storage[527] <= (INIT) ? 12'd1705 : storage[527];
storage[528] <= (INIT) ? 12'd1692 : storage[528];
storage[529] <= (INIT) ? 12'd1680 : storage[529];
storage[530] <= (INIT) ? 12'd1667 : storage[530];
storage[531] <= (INIT) ? 12'd1655 : storage[531];
storage[532] <= (INIT) ? 12'd1642 : storage[532];
storage[533] <= (INIT) ? 12'd1629 : storage[533];
storage[534] <= (INIT) ? 12'd1617 : storage[534];
storage[535] <= (INIT) ? 12'd1604 : storage[535];
storage[536] <= (INIT) ? 12'd1592 : storage[536];
storage[537] <= (INIT) ? 12'd1579 : storage[537];
storage[538] <= (INIT) ? 12'd1567 : storage[538];
storage[539] <= (INIT) ? 12'd1554 : storage[539];
storage[540] <= (INIT) ? 12'd1542 : storage[540];
storage[541] <= (INIT) ? 12'd1529 : storage[541];
storage[542] <= (INIT) ? 12'd1517 : storage[542];
storage[543] <= (INIT) ? 12'd1504 : storage[543];
storage[544] <= (INIT) ? 12'd1492 : storage[544];
storage[545] <= (INIT) ? 12'd1480 : storage[545];
storage[546] <= (INIT) ? 12'd1467 : storage[546];
storage[547] <= (INIT) ? 12'd1455 : storage[547];
storage[548] <= (INIT) ? 12'd1443 : storage[548];
storage[549] <= (INIT) ? 12'd1430 : storage[549];
storage[550] <= (INIT) ? 12'd1418 : storage[550];
storage[551] <= (INIT) ? 12'd1406 : storage[551];
storage[552] <= (INIT) ? 12'd1394 : storage[552];
storage[553] <= (INIT) ? 12'd1381 : storage[553];
storage[554] <= (INIT) ? 12'd1369 : storage[554];
storage[555] <= (INIT) ? 12'd1357 : storage[555];
storage[556] <= (INIT) ? 12'd1345 : storage[556];
storage[557] <= (INIT) ? 12'd1333 : storage[557];
storage[558] <= (INIT) ? 12'd1321 : storage[558];
storage[559] <= (INIT) ? 12'd1309 : storage[559];
storage[560] <= (INIT) ? 12'd1297 : storage[560];
storage[561] <= (INIT) ? 12'd1285 : storage[561];
storage[562] <= (INIT) ? 12'd1273 : storage[562];
storage[563] <= (INIT) ? 12'd1261 : storage[563];
storage[564] <= (INIT) ? 12'd1249 : storage[564];
storage[565] <= (INIT) ? 12'd1238 : storage[565];
storage[566] <= (INIT) ? 12'd1226 : storage[566];
storage[567] <= (INIT) ? 12'd1214 : storage[567];
storage[568] <= (INIT) ? 12'd1202 : storage[568];
storage[569] <= (INIT) ? 12'd1191 : storage[569];
storage[570] <= (INIT) ? 12'd1179 : storage[570];
storage[571] <= (INIT) ? 12'd1167 : storage[571];
storage[572] <= (INIT) ? 12'd1156 : storage[572];
storage[573] <= (INIT) ? 12'd1144 : storage[573];
storage[574] <= (INIT) ? 12'd1133 : storage[574];
storage[575] <= (INIT) ? 12'd1121 : storage[575];
storage[576] <= (INIT) ? 12'd1110 : storage[576];
storage[577] <= (INIT) ? 12'd1098 : storage[577];
storage[578] <= (INIT) ? 12'd1087 : storage[578];
storage[579] <= (INIT) ? 12'd1075 : storage[579];
storage[580] <= (INIT) ? 12'd1064 : storage[580];
storage[581] <= (INIT) ? 12'd1053 : storage[581];
storage[582] <= (INIT) ? 12'd1042 : storage[582];
storage[583] <= (INIT) ? 12'd1031 : storage[583];
storage[584] <= (INIT) ? 12'd1019 : storage[584];
storage[585] <= (INIT) ? 12'd1008 : storage[585];
storage[586] <= (INIT) ? 12'd997 : storage[586];
storage[587] <= (INIT) ? 12'd986 : storage[587];
storage[588] <= (INIT) ? 12'd975 : storage[588];
storage[589] <= (INIT) ? 12'd964 : storage[589];
storage[590] <= (INIT) ? 12'd953 : storage[590];
storage[591] <= (INIT) ? 12'd943 : storage[591];
storage[592] <= (INIT) ? 12'd932 : storage[592];
storage[593] <= (INIT) ? 12'd921 : storage[593];
storage[594] <= (INIT) ? 12'd910 : storage[594];
storage[595] <= (INIT) ? 12'd900 : storage[595];
storage[596] <= (INIT) ? 12'd889 : storage[596];
storage[597] <= (INIT) ? 12'd878 : storage[597];
storage[598] <= (INIT) ? 12'd868 : storage[598];
storage[599] <= (INIT) ? 12'd857 : storage[599];
storage[600] <= (INIT) ? 12'd847 : storage[600];
storage[601] <= (INIT) ? 12'd836 : storage[601];
storage[602] <= (INIT) ? 12'd826 : storage[602];
storage[603] <= (INIT) ? 12'd816 : storage[603];
storage[604] <= (INIT) ? 12'd806 : storage[604];
storage[605] <= (INIT) ? 12'd795 : storage[605];
storage[606] <= (INIT) ? 12'd785 : storage[606];
storage[607] <= (INIT) ? 12'd775 : storage[607];
storage[608] <= (INIT) ? 12'd765 : storage[608];
storage[609] <= (INIT) ? 12'd755 : storage[609];
storage[610] <= (INIT) ? 12'd745 : storage[610];
storage[611] <= (INIT) ? 12'd735 : storage[611];
storage[612] <= (INIT) ? 12'd725 : storage[612];
storage[613] <= (INIT) ? 12'd716 : storage[613];
storage[614] <= (INIT) ? 12'd706 : storage[614];
storage[615] <= (INIT) ? 12'd696 : storage[615];
storage[616] <= (INIT) ? 12'd687 : storage[616];
storage[617] <= (INIT) ? 12'd677 : storage[617];
storage[618] <= (INIT) ? 12'd667 : storage[618];
storage[619] <= (INIT) ? 12'd658 : storage[619];
storage[620] <= (INIT) ? 12'd648 : storage[620];
storage[621] <= (INIT) ? 12'd639 : storage[621];
storage[622] <= (INIT) ? 12'd630 : storage[622];
storage[623] <= (INIT) ? 12'd621 : storage[623];
storage[624] <= (INIT) ? 12'd611 : storage[624];
storage[625] <= (INIT) ? 12'd602 : storage[625];
storage[626] <= (INIT) ? 12'd593 : storage[626];
storage[627] <= (INIT) ? 12'd584 : storage[627];
storage[628] <= (INIT) ? 12'd575 : storage[628];
storage[629] <= (INIT) ? 12'd566 : storage[629];
storage[630] <= (INIT) ? 12'd557 : storage[630];
storage[631] <= (INIT) ? 12'd549 : storage[631];
storage[632] <= (INIT) ? 12'd540 : storage[632];
storage[633] <= (INIT) ? 12'd531 : storage[633];
storage[634] <= (INIT) ? 12'd523 : storage[634];
storage[635] <= (INIT) ? 12'd514 : storage[635];
storage[636] <= (INIT) ? 12'd506 : storage[636];
storage[637] <= (INIT) ? 12'd497 : storage[637];
storage[638] <= (INIT) ? 12'd489 : storage[638];
storage[639] <= (INIT) ? 12'd480 : storage[639];
storage[640] <= (INIT) ? 12'd472 : storage[640];
storage[641] <= (INIT) ? 12'd464 : storage[641];
storage[642] <= (INIT) ? 12'd456 : storage[642];
storage[643] <= (INIT) ? 12'd448 : storage[643];
storage[644] <= (INIT) ? 12'd440 : storage[644];
storage[645] <= (INIT) ? 12'd432 : storage[645];
storage[646] <= (INIT) ? 12'd424 : storage[646];
storage[647] <= (INIT) ? 12'd416 : storage[647];
storage[648] <= (INIT) ? 12'd408 : storage[648];
storage[649] <= (INIT) ? 12'd401 : storage[649];
storage[650] <= (INIT) ? 12'd393 : storage[650];
storage[651] <= (INIT) ? 12'd386 : storage[651];
storage[652] <= (INIT) ? 12'd378 : storage[652];
storage[653] <= (INIT) ? 12'd371 : storage[653];
storage[654] <= (INIT) ? 12'd363 : storage[654];
storage[655] <= (INIT) ? 12'd356 : storage[655];
storage[656] <= (INIT) ? 12'd349 : storage[656];
storage[657] <= (INIT) ? 12'd342 : storage[657];
storage[658] <= (INIT) ? 12'd335 : storage[658];
storage[659] <= (INIT) ? 12'd328 : storage[659];
storage[660] <= (INIT) ? 12'd321 : storage[660];
storage[661] <= (INIT) ? 12'd314 : storage[661];
storage[662] <= (INIT) ? 12'd307 : storage[662];
storage[663] <= (INIT) ? 12'd300 : storage[663];
storage[664] <= (INIT) ? 12'd294 : storage[664];
storage[665] <= (INIT) ? 12'd287 : storage[665];
storage[666] <= (INIT) ? 12'd280 : storage[666];
storage[667] <= (INIT) ? 12'd274 : storage[667];
storage[668] <= (INIT) ? 12'd268 : storage[668];
storage[669] <= (INIT) ? 12'd261 : storage[669];
storage[670] <= (INIT) ? 12'd255 : storage[670];
storage[671] <= (INIT) ? 12'd249 : storage[671];
storage[672] <= (INIT) ? 12'd243 : storage[672];
storage[673] <= (INIT) ? 12'd237 : storage[673];
storage[674] <= (INIT) ? 12'd231 : storage[674];
storage[675] <= (INIT) ? 12'd225 : storage[675];
storage[676] <= (INIT) ? 12'd219 : storage[676];
storage[677] <= (INIT) ? 12'd213 : storage[677];
storage[678] <= (INIT) ? 12'd207 : storage[678];
storage[679] <= (INIT) ? 12'd202 : storage[679];
storage[680] <= (INIT) ? 12'd196 : storage[680];
storage[681] <= (INIT) ? 12'd191 : storage[681];
storage[682] <= (INIT) ? 12'd185 : storage[682];
storage[683] <= (INIT) ? 12'd180 : storage[683];
storage[684] <= (INIT) ? 12'd175 : storage[684];
storage[685] <= (INIT) ? 12'd170 : storage[685];
storage[686] <= (INIT) ? 12'd165 : storage[686];
storage[687] <= (INIT) ? 12'd160 : storage[687];
storage[688] <= (INIT) ? 12'd155 : storage[688];
storage[689] <= (INIT) ? 12'd150 : storage[689];
storage[690] <= (INIT) ? 12'd145 : storage[690];
storage[691] <= (INIT) ? 12'd140 : storage[691];
storage[692] <= (INIT) ? 12'd136 : storage[692];
storage[693] <= (INIT) ? 12'd131 : storage[693];
storage[694] <= (INIT) ? 12'd127 : storage[694];
storage[695] <= (INIT) ? 12'd122 : storage[695];
storage[696] <= (INIT) ? 12'd118 : storage[696];
storage[697] <= (INIT) ? 12'd114 : storage[697];
storage[698] <= (INIT) ? 12'd109 : storage[698];
storage[699] <= (INIT) ? 12'd105 : storage[699];
storage[700] <= (INIT) ? 12'd101 : storage[700];
storage[701] <= (INIT) ? 12'd97 : storage[701];
storage[702] <= (INIT) ? 12'd93 : storage[702];
storage[703] <= (INIT) ? 12'd89 : storage[703];
storage[704] <= (INIT) ? 12'd86 : storage[704];
storage[705] <= (INIT) ? 12'd82 : storage[705];
storage[706] <= (INIT) ? 12'd79 : storage[706];
storage[707] <= (INIT) ? 12'd75 : storage[707];
storage[708] <= (INIT) ? 12'd72 : storage[708];
storage[709] <= (INIT) ? 12'd68 : storage[709];
storage[710] <= (INIT) ? 12'd65 : storage[710];
storage[711] <= (INIT) ? 12'd62 : storage[711];
storage[712] <= (INIT) ? 12'd59 : storage[712];
storage[713] <= (INIT) ? 12'd56 : storage[713];
storage[714] <= (INIT) ? 12'd53 : storage[714];
storage[715] <= (INIT) ? 12'd50 : storage[715];
storage[716] <= (INIT) ? 12'd47 : storage[716];
storage[717] <= (INIT) ? 12'd44 : storage[717];
storage[718] <= (INIT) ? 12'd42 : storage[718];
storage[719] <= (INIT) ? 12'd39 : storage[719];
storage[720] <= (INIT) ? 12'd37 : storage[720];
storage[721] <= (INIT) ? 12'd34 : storage[721];
storage[722] <= (INIT) ? 12'd32 : storage[722];
storage[723] <= (INIT) ? 12'd30 : storage[723];
storage[724] <= (INIT) ? 12'd28 : storage[724];
storage[725] <= (INIT) ? 12'd25 : storage[725];
storage[726] <= (INIT) ? 12'd23 : storage[726];
storage[727] <= (INIT) ? 12'd22 : storage[727];
storage[728] <= (INIT) ? 12'd20 : storage[728];
storage[729] <= (INIT) ? 12'd18 : storage[729];
storage[730] <= (INIT) ? 12'd16 : storage[730];
storage[731] <= (INIT) ? 12'd15 : storage[731];
storage[732] <= (INIT) ? 12'd13 : storage[732];
storage[733] <= (INIT) ? 12'd12 : storage[733];
storage[734] <= (INIT) ? 12'd10 : storage[734];
storage[735] <= (INIT) ? 12'd9 : storage[735];
storage[736] <= (INIT) ? 12'd8 : storage[736];
storage[737] <= (INIT) ? 12'd7 : storage[737];
storage[738] <= (INIT) ? 12'd6 : storage[738];
storage[739] <= (INIT) ? 12'd5 : storage[739];
storage[740] <= (INIT) ? 12'd4 : storage[740];
storage[741] <= (INIT) ? 12'd3 : storage[741];
storage[742] <= (INIT) ? 12'd2 : storage[742];
storage[743] <= (INIT) ? 12'd2 : storage[743];
storage[744] <= (INIT) ? 12'd1 : storage[744];
storage[745] <= (INIT) ? 12'd1 : storage[745];
storage[746] <= (INIT) ? 12'd0 : storage[746];
storage[747] <= (INIT) ? 12'd0 : storage[747];
storage[748] <= (INIT) ? 12'd0 : storage[748];
storage[749] <= (INIT) ? 12'd0 : storage[749];
storage[750] <= (INIT) ? 12'd0 : storage[750];
storage[751] <= (INIT) ? 12'd0 : storage[751];
storage[752] <= (INIT) ? 12'd0 : storage[752];
storage[753] <= (INIT) ? 12'd0 : storage[753];
storage[754] <= (INIT) ? 12'd0 : storage[754];
storage[755] <= (INIT) ? 12'd0 : storage[755];
storage[756] <= (INIT) ? 12'd1 : storage[756];
storage[757] <= (INIT) ? 12'd1 : storage[757];
storage[758] <= (INIT) ? 12'd2 : storage[758];
storage[759] <= (INIT) ? 12'd2 : storage[759];
storage[760] <= (INIT) ? 12'd3 : storage[760];
storage[761] <= (INIT) ? 12'd4 : storage[761];
storage[762] <= (INIT) ? 12'd5 : storage[762];
storage[763] <= (INIT) ? 12'd6 : storage[763];
storage[764] <= (INIT) ? 12'd7 : storage[764];
storage[765] <= (INIT) ? 12'd8 : storage[765];
storage[766] <= (INIT) ? 12'd9 : storage[766];
storage[767] <= (INIT) ? 12'd11 : storage[767];
storage[768] <= (INIT) ? 12'd12 : storage[768];
storage[769] <= (INIT) ? 12'd13 : storage[769];
storage[770] <= (INIT) ? 12'd15 : storage[770];
storage[771] <= (INIT) ? 12'd17 : storage[771];
storage[772] <= (INIT) ? 12'd18 : storage[772];
storage[773] <= (INIT) ? 12'd20 : storage[773];
storage[774] <= (INIT) ? 12'd22 : storage[774];
storage[775] <= (INIT) ? 12'd24 : storage[775];
storage[776] <= (INIT) ? 12'd26 : storage[776];
storage[777] <= (INIT) ? 12'd28 : storage[777];
storage[778] <= (INIT) ? 12'd30 : storage[778];
storage[779] <= (INIT) ? 12'd32 : storage[779];
storage[780] <= (INIT) ? 12'd35 : storage[780];
storage[781] <= (INIT) ? 12'd37 : storage[781];
storage[782] <= (INIT) ? 12'd40 : storage[782];
storage[783] <= (INIT) ? 12'd42 : storage[783];
storage[784] <= (INIT) ? 12'd45 : storage[784];
storage[785] <= (INIT) ? 12'd48 : storage[785];
storage[786] <= (INIT) ? 12'd51 : storage[786];
storage[787] <= (INIT) ? 12'd53 : storage[787];
storage[788] <= (INIT) ? 12'd56 : storage[788];
storage[789] <= (INIT) ? 12'd59 : storage[789];
storage[790] <= (INIT) ? 12'd63 : storage[790];
storage[791] <= (INIT) ? 12'd66 : storage[791];
storage[792] <= (INIT) ? 12'd69 : storage[792];
storage[793] <= (INIT) ? 12'd72 : storage[793];
storage[794] <= (INIT) ? 12'd76 : storage[794];
storage[795] <= (INIT) ? 12'd79 : storage[795];
storage[796] <= (INIT) ? 12'd83 : storage[796];
storage[797] <= (INIT) ? 12'd87 : storage[797];
storage[798] <= (INIT) ? 12'd90 : storage[798];
storage[799] <= (INIT) ? 12'd94 : storage[799];
storage[800] <= (INIT) ? 12'd98 : storage[800];
storage[801] <= (INIT) ? 12'd102 : storage[801];
storage[802] <= (INIT) ? 12'd106 : storage[802];
storage[803] <= (INIT) ? 12'd110 : storage[803];
storage[804] <= (INIT) ? 12'd115 : storage[804];
storage[805] <= (INIT) ? 12'd119 : storage[805];
storage[806] <= (INIT) ? 12'd123 : storage[806];
storage[807] <= (INIT) ? 12'd128 : storage[807];
storage[808] <= (INIT) ? 12'd132 : storage[808];
storage[809] <= (INIT) ? 12'd137 : storage[809];
storage[810] <= (INIT) ? 12'd141 : storage[810];
storage[811] <= (INIT) ? 12'd146 : storage[811];
storage[812] <= (INIT) ? 12'd151 : storage[812];
storage[813] <= (INIT) ? 12'd156 : storage[813];
storage[814] <= (INIT) ? 12'd161 : storage[814];
storage[815] <= (INIT) ? 12'd166 : storage[815];
storage[816] <= (INIT) ? 12'd171 : storage[816];
storage[817] <= (INIT) ? 12'd176 : storage[817];
storage[818] <= (INIT) ? 12'd181 : storage[818];
storage[819] <= (INIT) ? 12'd187 : storage[819];
storage[820] <= (INIT) ? 12'd192 : storage[820];
storage[821] <= (INIT) ? 12'd198 : storage[821];
storage[822] <= (INIT) ? 12'd203 : storage[822];
storage[823] <= (INIT) ? 12'd209 : storage[823];
storage[824] <= (INIT) ? 12'd215 : storage[824];
storage[825] <= (INIT) ? 12'd220 : storage[825];
storage[826] <= (INIT) ? 12'd226 : storage[826];
storage[827] <= (INIT) ? 12'd232 : storage[827];
storage[828] <= (INIT) ? 12'd238 : storage[828];
storage[829] <= (INIT) ? 12'd244 : storage[829];
storage[830] <= (INIT) ? 12'd250 : storage[830];
storage[831] <= (INIT) ? 12'd256 : storage[831];
storage[832] <= (INIT) ? 12'd263 : storage[832];
storage[833] <= (INIT) ? 12'd269 : storage[833];
storage[834] <= (INIT) ? 12'd275 : storage[834];
storage[835] <= (INIT) ? 12'd282 : storage[835];
storage[836] <= (INIT) ? 12'd288 : storage[836];
storage[837] <= (INIT) ? 12'd295 : storage[837];
storage[838] <= (INIT) ? 12'd302 : storage[838];
storage[839] <= (INIT) ? 12'd309 : storage[839];
storage[840] <= (INIT) ? 12'd315 : storage[840];
storage[841] <= (INIT) ? 12'd322 : storage[841];
storage[842] <= (INIT) ? 12'd329 : storage[842];
storage[843] <= (INIT) ? 12'd336 : storage[843];
storage[844] <= (INIT) ? 12'd343 : storage[844];
storage[845] <= (INIT) ? 12'd351 : storage[845];
storage[846] <= (INIT) ? 12'd358 : storage[846];
storage[847] <= (INIT) ? 12'd365 : storage[847];
storage[848] <= (INIT) ? 12'd372 : storage[848];
storage[849] <= (INIT) ? 12'd380 : storage[849];
storage[850] <= (INIT) ? 12'd387 : storage[850];
storage[851] <= (INIT) ? 12'd395 : storage[851];
storage[852] <= (INIT) ? 12'd403 : storage[852];
storage[853] <= (INIT) ? 12'd410 : storage[853];
storage[854] <= (INIT) ? 12'd418 : storage[854];
storage[855] <= (INIT) ? 12'd426 : storage[855];
storage[856] <= (INIT) ? 12'd434 : storage[856];
storage[857] <= (INIT) ? 12'd442 : storage[857];
storage[858] <= (INIT) ? 12'd450 : storage[858];
storage[859] <= (INIT) ? 12'd458 : storage[859];
storage[860] <= (INIT) ? 12'd466 : storage[860];
storage[861] <= (INIT) ? 12'd474 : storage[861];
storage[862] <= (INIT) ? 12'd482 : storage[862];
storage[863] <= (INIT) ? 12'd491 : storage[863];
storage[864] <= (INIT) ? 12'd499 : storage[864];
storage[865] <= (INIT) ? 12'd508 : storage[865];
storage[866] <= (INIT) ? 12'd516 : storage[866];
storage[867] <= (INIT) ? 12'd525 : storage[867];
storage[868] <= (INIT) ? 12'd533 : storage[868];
storage[869] <= (INIT) ? 12'd542 : storage[869];
storage[870] <= (INIT) ? 12'd551 : storage[870];
storage[871] <= (INIT) ? 12'd560 : storage[871];
storage[872] <= (INIT) ? 12'd568 : storage[872];
storage[873] <= (INIT) ? 12'd577 : storage[873];
storage[874] <= (INIT) ? 12'd586 : storage[874];
storage[875] <= (INIT) ? 12'd595 : storage[875];
storage[876] <= (INIT) ? 12'd604 : storage[876];
storage[877] <= (INIT) ? 12'd614 : storage[877];
storage[878] <= (INIT) ? 12'd623 : storage[878];
storage[879] <= (INIT) ? 12'd632 : storage[879];
storage[880] <= (INIT) ? 12'd641 : storage[880];
storage[881] <= (INIT) ? 12'd651 : storage[881];
storage[882] <= (INIT) ? 12'd660 : storage[882];
storage[883] <= (INIT) ? 12'd670 : storage[883];
storage[884] <= (INIT) ? 12'd679 : storage[884];
storage[885] <= (INIT) ? 12'd689 : storage[885];
storage[886] <= (INIT) ? 12'd698 : storage[886];
storage[887] <= (INIT) ? 12'd708 : storage[887];
storage[888] <= (INIT) ? 12'd718 : storage[888];
storage[889] <= (INIT) ? 12'd728 : storage[889];
storage[890] <= (INIT) ? 12'd738 : storage[890];
storage[891] <= (INIT) ? 12'd747 : storage[891];
storage[892] <= (INIT) ? 12'd757 : storage[892];
storage[893] <= (INIT) ? 12'd767 : storage[893];
storage[894] <= (INIT) ? 12'd778 : storage[894];
storage[895] <= (INIT) ? 12'd788 : storage[895];
storage[896] <= (INIT) ? 12'd798 : storage[896];
storage[897] <= (INIT) ? 12'd808 : storage[897];
storage[898] <= (INIT) ? 12'd818 : storage[898];
storage[899] <= (INIT) ? 12'd829 : storage[899];
storage[900] <= (INIT) ? 12'd839 : storage[900];
storage[901] <= (INIT) ? 12'd849 : storage[901];
storage[902] <= (INIT) ? 12'd860 : storage[902];
storage[903] <= (INIT) ? 12'd870 : storage[903];
storage[904] <= (INIT) ? 12'd881 : storage[904];
storage[905] <= (INIT) ? 12'd891 : storage[905];
storage[906] <= (INIT) ? 12'd902 : storage[906];
storage[907] <= (INIT) ? 12'd913 : storage[907];
storage[908] <= (INIT) ? 12'd924 : storage[908];
storage[909] <= (INIT) ? 12'd934 : storage[909];
storage[910] <= (INIT) ? 12'd945 : storage[910];
storage[911] <= (INIT) ? 12'd956 : storage[911];
storage[912] <= (INIT) ? 12'd967 : storage[912];
storage[913] <= (INIT) ? 12'd978 : storage[913];
storage[914] <= (INIT) ? 12'd989 : storage[914];
storage[915] <= (INIT) ? 12'd1000 : storage[915];
storage[916] <= (INIT) ? 12'd1011 : storage[916];
storage[917] <= (INIT) ? 12'd1022 : storage[917];
storage[918] <= (INIT) ? 12'd1033 : storage[918];
storage[919] <= (INIT) ? 12'd1044 : storage[919];
storage[920] <= (INIT) ? 12'd1056 : storage[920];
storage[921] <= (INIT) ? 12'd1067 : storage[921];
storage[922] <= (INIT) ? 12'd1078 : storage[922];
storage[923] <= (INIT) ? 12'd1090 : storage[923];
storage[924] <= (INIT) ? 12'd1101 : storage[924];
storage[925] <= (INIT) ? 12'd1112 : storage[925];
storage[926] <= (INIT) ? 12'd1124 : storage[926];
storage[927] <= (INIT) ? 12'd1135 : storage[927];
storage[928] <= (INIT) ? 12'd1147 : storage[928];
storage[929] <= (INIT) ? 12'd1158 : storage[929];
storage[930] <= (INIT) ? 12'd1170 : storage[930];
storage[931] <= (INIT) ? 12'd1182 : storage[931];
storage[932] <= (INIT) ? 12'd1193 : storage[932];
storage[933] <= (INIT) ? 12'd1205 : storage[933];
storage[934] <= (INIT) ? 12'd1217 : storage[934];
storage[935] <= (INIT) ? 12'd1229 : storage[935];
storage[936] <= (INIT) ? 12'd1240 : storage[936];
storage[937] <= (INIT) ? 12'd1252 : storage[937];
storage[938] <= (INIT) ? 12'd1264 : storage[938];
storage[939] <= (INIT) ? 12'd1276 : storage[939];
storage[940] <= (INIT) ? 12'd1288 : storage[940];
storage[941] <= (INIT) ? 12'd1300 : storage[941];
storage[942] <= (INIT) ? 12'd1312 : storage[942];
storage[943] <= (INIT) ? 12'd1324 : storage[943];
storage[944] <= (INIT) ? 12'd1336 : storage[944];
storage[945] <= (INIT) ? 12'd1348 : storage[945];
storage[946] <= (INIT) ? 12'd1360 : storage[946];
storage[947] <= (INIT) ? 12'd1372 : storage[947];
storage[948] <= (INIT) ? 12'd1384 : storage[948];
storage[949] <= (INIT) ? 12'd1397 : storage[949];
storage[950] <= (INIT) ? 12'd1409 : storage[950];
storage[951] <= (INIT) ? 12'd1421 : storage[951];
storage[952] <= (INIT) ? 12'd1433 : storage[952];
storage[953] <= (INIT) ? 12'd1446 : storage[953];
storage[954] <= (INIT) ? 12'd1458 : storage[954];
storage[955] <= (INIT) ? 12'd1470 : storage[955];
storage[956] <= (INIT) ? 12'd1482 : storage[956];
storage[957] <= (INIT) ? 12'd1495 : storage[957];
storage[958] <= (INIT) ? 12'd1507 : storage[958];
storage[959] <= (INIT) ? 12'd1520 : storage[959];
storage[960] <= (INIT) ? 12'd1532 : storage[960];
storage[961] <= (INIT) ? 12'd1545 : storage[961];
storage[962] <= (INIT) ? 12'd1557 : storage[962];
storage[963] <= (INIT) ? 12'd1570 : storage[963];
storage[964] <= (INIT) ? 12'd1582 : storage[964];
storage[965] <= (INIT) ? 12'd1595 : storage[965];
storage[966] <= (INIT) ? 12'd1607 : storage[966];
storage[967] <= (INIT) ? 12'd1620 : storage[967];
storage[968] <= (INIT) ? 12'd1632 : storage[968];
storage[969] <= (INIT) ? 12'd1645 : storage[969];
storage[970] <= (INIT) ? 12'd1658 : storage[970];
storage[971] <= (INIT) ? 12'd1670 : storage[971];
storage[972] <= (INIT) ? 12'd1683 : storage[972];
storage[973] <= (INIT) ? 12'd1695 : storage[973];
storage[974] <= (INIT) ? 12'd1708 : storage[974];
storage[975] <= (INIT) ? 12'd1721 : storage[975];
storage[976] <= (INIT) ? 12'd1734 : storage[976];
storage[977] <= (INIT) ? 12'd1746 : storage[977];
storage[978] <= (INIT) ? 12'd1759 : storage[978];
storage[979] <= (INIT) ? 12'd1772 : storage[979];
storage[980] <= (INIT) ? 12'd1784 : storage[980];
storage[981] <= (INIT) ? 12'd1797 : storage[981];
storage[982] <= (INIT) ? 12'd1810 : storage[982];
storage[983] <= (INIT) ? 12'd1823 : storage[983];
storage[984] <= (INIT) ? 12'd1836 : storage[984];
storage[985] <= (INIT) ? 12'd1848 : storage[985];
storage[986] <= (INIT) ? 12'd1861 : storage[986];
storage[987] <= (INIT) ? 12'd1874 : storage[987];
storage[988] <= (INIT) ? 12'd1887 : storage[988];
storage[989] <= (INIT) ? 12'd1900 : storage[989];
storage[990] <= (INIT) ? 12'd1912 : storage[990];
storage[991] <= (INIT) ? 12'd1925 : storage[991];
storage[992] <= (INIT) ? 12'd1938 : storage[992];
storage[993] <= (INIT) ? 12'd1951 : storage[993];
storage[994] <= (INIT) ? 12'd1964 : storage[994];
storage[995] <= (INIT) ? 12'd1977 : storage[995];
storage[996] <= (INIT) ? 12'd1990 : storage[996];
storage[997] <= (INIT) ? 12'd2002 : storage[997];
storage[998] <= (INIT) ? 12'd2015 : storage[998];
storage[999] <= (INIT) ? 12'd2028 : storage[999];
storage[1000] <= (INIT) ? 12'd0 : storage[1000];
storage[1001] <= (INIT) ? 12'd0 : storage[1001];
storage[1002] <= (INIT) ? 12'd0 : storage[1002];
storage[1003] <= (INIT) ? 12'd0 : storage[1003];
storage[1004] <= (INIT) ? 12'd0 : storage[1004];
storage[1005] <= (INIT) ? 12'd0 : storage[1005];
storage[1006] <= (INIT) ? 12'd0 : storage[1006];
storage[1007] <= (INIT) ? 12'd0 : storage[1007];
storage[1008] <= (INIT) ? 12'd0 : storage[1008];
storage[1009] <= (INIT) ? 12'd0 : storage[1009];
storage[1010] <= (INIT) ? 12'd0 : storage[1010];
storage[1011] <= (INIT) ? 12'd0 : storage[1011];
storage[1012] <= (INIT) ? 12'd0 : storage[1012];
storage[1013] <= (INIT) ? 12'd0 : storage[1013];
storage[1014] <= (INIT) ? 12'd0 : storage[1014];
storage[1015] <= (INIT) ? 12'd0 : storage[1015];
storage[1016] <= (INIT) ? 12'd0 : storage[1016];
storage[1017] <= (INIT) ? 12'd0 : storage[1017];
storage[1018] <= (INIT) ? 12'd0 : storage[1018];
storage[1019] <= (INIT) ? 12'd0 : storage[1019];
storage[1020] <= (INIT) ? 12'd0 : storage[1020];
storage[1021] <= (INIT) ? 12'd0 : storage[1021];
storage[1022] <= (INIT) ? 12'd0 : storage[1022];
storage[1023] <= (INIT) ? 12'd0 : storage[1023];
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module RAMB16_S1_S2 (
CLKA, CLKB, ENB, WEA, WEB, ENA, SSRA, SSRB, DIPB, ADDRA, ADDRB, DIA, DIB, DOA, DOB, DOPB
);
input wire CLKA;
input wire CLKB;
output reg [1 : 0] DOB;
output reg [0 : 0] DOA;
input wire [0 : 0] WEA;
input wire [0 : 0] WEB;
input wire [12 : 0] ADDRB;
input wire [13 : 0] ADDRA;
input wire [1 : 0] DIB;
input wire [0 : 0] DIA;
input wire ENB;
input wire ENA;
input wire SSRA;
input wire SSRB;
input wire DIPB;
output wire DOPB;
parameter WIDTHA = 1;
parameter SIZEA = 16384;
parameter ADDRWIDTHA = 14;
parameter WIDTHB = 2;
parameter SIZEB = SIZEA/2;
parameter ADDRWIDTHB = 13;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
`include "../includes/log2func.v"
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = `CLOG2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
always @(posedge CLKA)
if (WEA)
RAM[ADDRA] <= DIA;
else
DOA <= RAM[ADDRA];
genvar i;
generate for (i = 0; i < RATIO; i = i+1)
begin: portA
localparam [log2RATIO-1:0] lsbaddr = i;
always @(posedge CLKB)
if (WEB)
RAM[{ADDRB, lsbaddr}] <= DIB[(i+1)*minWIDTH-1:i*minWIDTH];
else
DOB[(i+1)*minWIDTH-1:i*minWIDTH] <= RAM[{ADDRB, lsbaddr}];
end
endgenerate
endmodule
|
`timescale 1 ps / 1 ps
module onetswitch_top(
inout [14:0] DDR_addr,
inout [2:0] DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0] DDR_dm,
inout [31:0] DDR_dq,
inout [3:0] DDR_dqs_n,
inout [3:0] DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0] FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
input sgmii_refclk_p,
input sgmii_refclk_n,
output gtx_pcie_txp ,
output gtx_pcie_txn ,
input gtx_pcie_rxp ,
input gtx_pcie_rxn ,
input gtx_pcie_clk_100m_p ,
input gtx_pcie_clk_100m_n ,
input pcie_wake_b ,
input pcie_clkreq_b ,
output pcie_perst_b ,
output pcie_w_disable_b ,
output [1:0] pl_led,
output [1:0] pl_pmod,
input pl_btn
);
wire bd_fclk0_125m ;
wire bd_fclk1_75m ;
wire bd_fclk2_200m ;
wire bd_aresetn ;
wire sgmii_refclk_se;
wire pcie_dbg_clk ;
wire pcie_dbg_mmcm_lock ;
wire gtx_pcie_refclk;
reg [23:0] cnt_0;
reg [23:0] cnt_1;
reg [23:0] cnt_2;
reg [23:0] cnt_3;
always @(posedge bd_fclk0_125m) begin
cnt_0 <= cnt_0 + 1'b1;
end
always @(posedge bd_fclk1_75m) begin
cnt_1 <= cnt_1 + 1'b1;
end
always @(posedge sgmii_refclk_se) begin
cnt_2 <= cnt_2 + 1'b1;
end
always @(posedge pcie_dbg_clk) begin
cnt_3 <= cnt_3 + 1'b1;
end
assign pl_led[0] = pcie_dbg_mmcm_lock;
assign pl_led[1] = bd_aresetn;
assign pl_pmod[0] = cnt_2[23];
assign pl_pmod[1] = cnt_3[23];
// sgmii ref clk
IBUFDS #(
.DIFF_TERM("FALSE"), // Differential Termination
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFDS_i_sgmii_refclk (
.O (sgmii_refclk_se), // Buffer output
.I (sgmii_refclk_p), // Diff_p buffer input (connect directly to top-level port)
.IB (sgmii_refclk_n) // Diff_n buffer input (connect directly to top-level port)
);
assign pcie_perst_b = bd_aresetn ;
assign pcie_w_disable_b = bd_aresetn ;
IBUFDS_GTE2 refclk_ibuf_pcie (.O(gtx_pcie_refclk), .ODIV2(), .I(gtx_pcie_clk_100m_p), .CEB(1'b0), .IB(gtx_pcie_clk_100m_n));
onets_bd_wrapper i_onets_bd_wrapper(
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.pcie_7x_mgt_rxn ( gtx_pcie_rxn ),
.pcie_7x_mgt_rxp ( gtx_pcie_rxp ),
.pcie_7x_mgt_txn ( gtx_pcie_txn ),
.pcie_7x_mgt_txp ( gtx_pcie_txp ),
.pcie_msi_en ( 'b0),
.pcie_msi_gnt ( ),
.pcie_msi_req ( 'b0 ),
.pcie_msi_vec_num ( 'b0),
.pcie_msi_vec_width ( ),
.pcie_refclk ( gtx_pcie_refclk ),
.pcie_dbg_clk ( pcie_dbg_clk ),
.pcie_dbg_mmcm_lock ( pcie_dbg_mmcm_lock ),
.bd_fclk0_125m ( bd_fclk0_125m ),
.bd_fclk1_75m ( bd_fclk1_75m ),
.bd_fclk2_200m ( bd_fclk2_200m ),
.bd_aresetn ( bd_aresetn ),
.ext_rst ( pl_btn )
);
endmodule
|
module simple(/*AUTOARG*/
// Outputs
o,
// Inputs
clk, rst_n, a, b
); //line
parameter IN_SIZE = 4; // Line comment applied to IN_SIZE
localparam IN_MSB = IN_SIZE - 1, // applied to IN_MSB, as first identifier on line
OUT_SIZE = IN_SIZE + 1,
OUT_MSB = OUT_SIZE - 1;
input clk, rst_n;
input [IN_MSB:0] a, b;
output [OUT_MSB:0] o;
reg [OUT_MSB:0] d;
wire rst = !rst_n;
assign o = 2*a + -b ? fortyten : d;
always @(posedge clk or negedge rst_n)
if (!rst_n)
d <= {OUT_SIZE{1'b0}};
else
d <= o;
always @* begin
hello = world;
all = work + and | no * play == makes ^ !jack & a % dull / boy;
end
/*metav
"Docstring goes here. Note the indentation."
x = "hello world"
print(x.capitalize())
print("portstyle: "+ module.portstyle)
module.add_item(ast.Input(ast.Id("generated_input")))
for i in module.items:
if isinstance(i, ast.ContAssigns):
i.delete()
print(module)
for id in module.ids:
print(id+":\t"+repr(module.ids[id]))
*/
/*metav_generated:*/
assign ignored = "This code is ignored by the lexer";
syntax errors are ignored;
Lexer errors are also ignored: ¤;
/*:metav_generated*/
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_device.v ////
//// ////
//// This file is part of the "uart16550" project ////
//// http://www.opencores.org/projects/uart16550/ ////
//// ////
//// Author(s): ////
//// - [email protected] (Tadej Markovic) ////
//// - [email protected] (Igor Mohor) ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
`include "uart_testbench_defines.v"
module uart_device
(
// UART signals
stx_i,
srx_o,
// Modem signals
rts_i,
cts_o,
dtr_i,
dsr_o,
ri_o,
dcd_o
);
// IN/OUT signals
//###############
// UART signals
input stx_i;
output srx_o;
// Modem signals
input rts_i;
output cts_o;
input dtr_i;
output dsr_o;
output ri_o;
output dcd_o;
// INTERNAL signals
//#################
// Clock generation signals
//#########################
// Operational and transmission clock signals
reg rx_clk; // RX device clock with period T_clk_period (should be equal to wb_clk_period)
reg tx_clk; // TX device clock with period (T_clk_period + T_clk_delay)
reg tx_clk_divided; // divided TX device clock with period ((T_clk_period + T_clk_delay) * T_divisor * 16)
// Clock enable signals
reg rx_clk_en = 1'b1;
reg tx_clk_en = 1'b1;
reg tx_clk_divided_en = 1'b1;
// Clock period variables
real T_clk_period = 20;
real T_clk_delay = 0;
integer T_divisor = 5;
// IN/OUT assignment signals
//##########################
// Modem signals
wire rts;
wire dtr;
// UART receiver signals
//######################
// RX packet control signals
wire rx;
reg [3:0] rx_length;
reg rx_odd_parity;
reg rx_even_parity;
reg rx_stick1_parity;
reg rx_stick0_parity;
reg rx_parity_enabled;
reg rx_stop_bit_1;
reg rx_stop_bit_1_5;
reg rx_stop_bit_2;
// RX logic signals
wire [3:0] rx_total_length;
wire [5:0] rx_break_detection_length;
reg rx_packet_end;
reg rx_packet_end_q;
reg rx_clk_cnt_en;
reg [31:0] rx_clk_cnt;
reg rx_sample_clock;
integer rx_bit_index;
integer rx_stop_bit_index;
reg [7:0] rx_data;
reg [1:0] rx_stop;
reg rx_framing_error;
reg rx_parity;
reg rx_parity_error;
reg rx_break_detected;
reg rx_break_detected_q;
reg [31:0] rx_break_cnt;
// RX events
event device_received_packet;
event device_received_last_bit;
event device_received_stop_bit;
event device_detected_rx_break;
// UART transmitter signals
//#########################
// TX packet control signals
reg tx;
reg [3:0] tx_length;
reg tx_odd_parity;
reg tx_even_parity;
reg tx_stick1_parity;
reg tx_stick0_parity;
reg tx_parity_enabled;
reg tx_parity_wrong;
reg tx_framing_wrong;
// TX logic signals
reg [23:0] tx_glitch_num;
reg start_tx_glitch_cnt;
reg [31:0] tx_glitch_cnt;
reg tx_glitch;
reg tx_break_enable;
reg [15:0] tx_break_num;
reg start_tx_break_cnt;
reg [31:0] tx_break_cnt;
reg tx_break;
// TX test signals
reg [7:0] sent_data;
reg tx_accept_next_framing_err;
reg tx_framing_err;
reg tx_framing_glitch_err;
// TX events
event device_sent_packet;
event sent_packet_received;
// Clock generation
//#################
// Example of TESTBENCH's task for setting UART clock period:
// ----------------
// task set_uart_clk_period;
// input [31:0] clk_period;
// begin
// //@(posedge testbench.uart_device.clk);
// testbench.uart_device.T_clk_period = clk_period;
// end
// endtask // set_uart_clk_period
// ----------------
// Example of TESTBENCH's task for setting UART clock rising edge
// delayed for time_delay_i after WB clock rising edge:
// ----------------
// task uart_clk_follows_wb_clk;
// input [31:0] time_delay_i;
// integer time_delay;
// begin
// time_delay = time_delay_i;
// @(posedge testbench.uart_device.clk);
// testbench.uart_device.clk_en = 1'b0;
// @(posedge wb_clk);
// #time_delay testbench.uart_device.clk = 1'b1;
// testbench.uart_device.clk_en = 1'b1;
// end
// endtask // uart_clk_follows_wb_clk
// ----------------
// rx_clk rising edge
always@(posedge rx_clk)
if (rx_clk_en)
#(T_clk_period / 2) rx_clk = 1'b0;
// rx_clk falling edge
always@(negedge rx_clk)
if (rx_clk_en)
#(T_clk_period / 2) rx_clk = 1'b1;
// tx_clk rising edge
always@(posedge tx_clk)
if (tx_clk_en)
#((T_clk_period + T_clk_delay) / 2) tx_clk = 1'b0;
// tx_clk falling edge
always@(negedge tx_clk)
if (tx_clk_en)
#((T_clk_period + T_clk_delay) / 2) tx_clk = 1'b1;
// tx_clk_divided rising edge
always@(posedge tx_clk_divided)
if (tx_clk_divided_en)
#(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) tx_clk_divided = 1'b0;
// tx_clk_divided falling edge
always@(negedge tx_clk_divided)
if (tx_clk_divided_en)
#(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) tx_clk_divided = 1'b1;
// Inital CLK values
initial
begin:device
rx_clk = 1'b0;
tx_clk = 1'b0;
tx_clk_divided = 1'b0;
end
// IN/OUT assignments
//###################
// UART output
assign srx_o = (tx ^ tx_glitch) & ~tx_break;
// Modem output
assign cts_o = 0;
assign dsr_o = 0;
assign ri_o = 0;
assign dcd_o = 0;
// UART input
assign rx = stx_i;
// Modem input
assign rts = rts_i;
assign dtr = dtr_i;
// UART receiver
//##############
// Initial values for RX
initial
begin
// Default LENGTH
rx_length = 8;
// Default PARITY
rx_odd_parity = 1'b0;
rx_even_parity = 1'b0;
rx_stick1_parity = 1'b0;
rx_stick0_parity = 1'b0;
rx_parity_enabled = 1'b0;
// Default STOP
rx_stop_bit_1 = 1'b1;
rx_stop_bit_1_5 = 1'b0;
rx_stop_bit_2 = 1'b0;
end
// Total length of RX packet (for proper generation of the rx_packet_end signal):
// data length + parity + 1 stop bit + second stop bit (when enabled)
assign rx_total_length = rx_length + rx_parity_enabled + 1 + rx_stop_bit_2;
// +1 is used because start bit was not included in rx_total_length.
assign rx_break_detection_length = rx_total_length + 1;
// Generating rx_clk_cnt_en signal.
always@(posedge rx_clk)
begin
if (~rx_clk_cnt_en)
begin
wait (~rx);
end
rx_clk_cnt_en = 1;
rx_packet_end = 0;
wait (rx_packet_end);
rx_clk_cnt_en = 0;
wait (rx); // Must be high to continue, because of break condition
end
// Counter used in data reception
always@(posedge rx_clk)
begin
if (rx_clk_cnt_en)
begin
if (rx_clk_cnt == (8 * T_divisor - 1) & rx) // False start bit detection
rx_packet_end = 1;
if (rx_clk_cnt_en) // Checking is still enabled after devisor clocks
rx_clk_cnt <= #1 rx_clk_cnt + 1;
else
rx_clk_cnt <= #1 0;
end
else
rx_clk_cnt <= #1 0;
end
// Delayed rx_packet_end signal
always@(posedge rx_clk)
rx_packet_end_q = rx_packet_end;
// Generating sample clock and end of the frame (Received data is sampled with this clock)
always@(posedge rx_clk)
begin
if (rx_clk_cnt == 8 * T_divisor - 1)
rx_bit_index = 0;
else if (rx_clk_cnt == (8 * T_divisor + 16 * T_divisor * (rx_bit_index + 1) - 1))
begin
rx_sample_clock = 1;
rx_bit_index = rx_bit_index + 1;
if (rx_bit_index == rx_total_length)
rx_packet_end = 1;
end
else
rx_sample_clock = 0;
end
// Sampling data (received data)
always@(posedge rx_clk)
begin
if (rx_sample_clock)
begin
if (rx_bit_index <= rx_length) // Sampling data
begin
rx_stop_bit_index <= 0; // Stop bit index reset at the beginning of the data stage
// $display("\t\t\t\t\t\t\t(rx_bit_index = %0d) Reading data bits = %0x", rx_bit_index, rx);
rx_data[rx_bit_index - 1] = rx;
if (rx_bit_index == rx_length)
-> device_received_last_bit;
end
else
begin
if (rx_bit_index == (rx_length + 1))
begin
if (rx_parity_enabled)
begin
// $display("\t\t\t\t\t\t\t(rx_bit_index = %0d) Reading parity bits = %0x", rx_bit_index, rx);
end
else
begin
-> device_received_stop_bit;
rx_stop[rx_stop_bit_index] = rx;
rx_stop_bit_index <= rx_stop_bit_index + 1;
end
rx_parity = rx & rx_parity_enabled;
end
if (rx_bit_index >= (rx_length + 1 + rx_parity_enabled))
begin
// $display("\t\t\t\t\t\t\t(rx_bit_index = %0d) Reading stop bits = %0x", rx_bit_index, rx);
rx_stop[rx_stop_bit_index] = rx;
rx_stop_bit_index <= rx_stop_bit_index + 1;
end
end
end
// Filling the rest of the data with 0
if (rx_length == 5)
rx_data[7:5] = 0;
if (rx_length == 6)
rx_data[7:6] = 0;
if (rx_length == 7)
rx_data[7] = 0;
// Framing error generation
// When 1 or 1.5 stop bits are used, only first stop bit is checked
rx_framing_error = (rx_stop_bit_1 | rx_stop_bit_1_5) ? ~rx_stop[0] : ~(&rx_stop[1:0]);
// Parity error generation
if (rx_odd_parity)
rx_parity_error = ~(^{rx_data, rx_parity});
else if (rx_even_parity)
rx_parity_error = ^{rx_data, rx_parity};
else if (rx_stick0_parity)
rx_parity_error = rx_parity;
else if (rx_stick1_parity)
rx_parity_error = ~rx_parity;
else
rx_parity_error = 0;
end
// Break detection
always@(posedge rx_clk)
begin
rx_break_detected_q <= rx_break_detected;
if (rx)
begin
rx_break_cnt = 0; // Reseting counter
rx_break_detected = 0; // Clearing break detected signal
end
else
rx_break_cnt = rx_break_cnt + 1;
if (rx_break_cnt == rx_break_detection_length * 16 * T_divisor)
begin
// $display("\n(%0t) Break_detected.", $time);
rx_break_detected <= 1;
-> device_detected_rx_break;
end
end
// Writing received data
always@(posedge rx_clk)
begin
if ((rx_packet_end & ~rx_packet_end_q) | (rx_break_detected & ~rx_break_detected_q))
begin
wait (rx | rx_break_detected); // Waiting for "end of cycle detected" or "break to be activated"
// rx_break_detected
// rx_length
// rx_parity_enabled
// rx_odd_parity | rx_even_parity | rx_stick1_parity | rx_stick0_parity
// rx_stop_bit_1 | rx_stop_bit_1_5 | rx_stop_bit_2
-> device_received_packet;
end
end
// UART transmitter
//#################
// Initial values for TX
initial
begin
// Default LENGTH
tx_length = 8;
// Default PARITY
tx_odd_parity = 1'b0;
tx_even_parity = 1'b0;
tx_stick1_parity = 1'b0;
tx_stick0_parity = 1'b0;
tx_parity_enabled = 1'b0;
// Default CORRECT PARITY
tx_parity_wrong = 1'b0;
// Default CORRECT FRAME
tx_framing_wrong = 1'b0;
tx_framing_err = 0;
tx_framing_glitch_err = 0;
// Default NO GLITCH
tx_glitch_num = 24'h0;
// Default NO BREAK
tx_break_enable = 1'b0;
tx_break_num = 16'h0;
end
// Counter for TX glitch generation
always@(posedge tx_clk or posedge start_tx_glitch_cnt)
begin
if (start_tx_glitch_cnt)
begin
tx_glitch_cnt <= tx_glitch_cnt + 1;
if (tx_glitch_cnt == ((tx_glitch_num - 1) * T_divisor))
tx_glitch = 1'b1;
else if (tx_glitch_cnt == (tx_glitch_num * T_divisor))
begin
tx_glitch = 1'b0;
start_tx_glitch_cnt = 1'b0;
end
end
else
tx_glitch_cnt <= 0;
end
// Break setting & break counter
always@(posedge tx_clk)
begin
if (tx_break_enable && (tx_break_cnt == (tx_break_num * T_divisor)))
begin
start_tx_break_cnt = 0;
end
else if (start_tx_break_cnt)
begin
tx_break_cnt = tx_break_cnt + 1;
tx_break = 1;
end
else
begin
tx_break_cnt = 0;
tx_break = 0;
end
end
// Sending packets
task send_packet;
input tx_random_i;
input [7:0] tx_data_i;
input num_of_tx_data_i;
reg [7:0] tx_data;
reg tx_parity_xor;
integer tx_bit_index;
integer num_of_tx_data;
reg last_tx_data;
begin
// SEVERE ERROR
if (// WRONG combinations of parameters for testing
((T_clk_delay != 0) && (tx_parity_wrong || tx_framing_wrong)) ||
((T_clk_delay != 0) && (tx_glitch_num != 0)) ||
((T_clk_delay != 0) && (tx_break_enable)) ||
((tx_parity_wrong || tx_framing_wrong) && (tx_glitch_num != 0)) ||
((tx_parity_wrong || tx_framing_wrong) && (tx_break_enable)) ||
((tx_glitch_num != 0) && (tx_break_enable)) ||
(tx_glitch_num > ((tx_length + 2'h2 + tx_parity_enabled) * 16 * T_divisor)) || // with STOP bit
// (tx_glitch_num > ((tx_length + 2'h1 + tx_parity_enabled) * 16 * T_divisor)) || // without STOP bit
// WRONG input parameters
(num_of_tx_data_i == 0) ||
((num_of_tx_data_i > 1) && tx_break_enable)
)
begin
`SEVERE_ERROR("WRONG combination of parameters for testing UART receiver");
end
for (num_of_tx_data = 0;
num_of_tx_data < num_of_tx_data_i;
num_of_tx_data = (num_of_tx_data + 1'b1))
begin
if (num_of_tx_data == (num_of_tx_data_i - 1'b1))
last_tx_data = 1'b1;
else
last_tx_data = 0;
// TX data
if (~tx_random_i)
tx_data = tx_data_i;
else
tx_data = {$random}%256; // 0..255
// Sending start bit
@(posedge tx_clk_divided);
tx = 0;
if (tx_glitch_num > 0)
start_tx_glitch_cnt = 1; // enabling tx_glitch generation
if (tx_break_enable)
start_tx_break_cnt = 1; // Start counter that counts break tx_length
// Wait for almost 1 bit
#(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor); // wait half period
#((((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) - 2); // wait 2 less than half period
// Sending tx_data bits
for (tx_bit_index = 0; tx_bit_index < tx_length; tx_bit_index = tx_bit_index + 1)
begin
@(posedge tx_clk_divided);
tx = tx_data[tx_bit_index];
end
// Wait for almost 1 bit
#(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor); // wait half period
#((((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) - 2); // wait 2 less than half period
sent_data = tx_data;
// Calculating parity
if(tx_length == 5)
begin
tx_parity_xor = ^tx_data[4:0];
end
else if(tx_length == 6)
begin
tx_parity_xor = ^tx_data[5:0];
end
else if(tx_length == 7)
begin
tx_parity_xor = ^tx_data[6:0];
end
else if(tx_length == 8)
begin
tx_parity_xor = ^tx_data[7:0];
end
else
$display("WRONG length of TX data packet");
// Sending parity bit
if (tx_parity_enabled)
begin
@(posedge tx_clk_divided);
if (tx_odd_parity)
tx = tx_parity_wrong ^ (~tx_parity_xor);
else if (tx_even_parity)
tx = tx_parity_wrong ^ tx_parity_xor;
else if (tx_stick1_parity)
tx = tx_parity_wrong ^ 1;
else if (tx_stick0_parity)
tx = tx_parity_wrong ^ 0;
// Wait for almost 1 bit
#(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor); // wait half period
#((((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) - 2); // wait 2 less than half period
end
// Sending stop bit
if (~tx_framing_wrong ||
(tx_glitch_num != ((((tx_length + 2'h2 + tx_parity_enabled) * 2) - 1'b1) * 8 * T_divisor)))
begin
@(posedge tx_clk_divided);
tx = 1;
// Wait for almost 1 bit
#(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor); // wait half period
#((((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) - 2); // wait 2 less than half period
-> device_sent_packet;
@(sent_packet_received);
end
else if (~tx_framing_wrong ||
(tx_glitch_num == ((((tx_length + 2'h2 + tx_parity_enabled) * 2) - 1'b1) * 8 * T_divisor)))
begin
@(posedge tx_clk_divided);
tx = 1;
// Wait for 1 bit
@(posedge tx_clk_divided); // this will be like 2. stop bit
-> device_sent_packet;
@(sent_packet_received);
end
else if (tx_framing_wrong && last_tx_data)
begin
@(posedge tx_clk_divided);
// Wrong stop | start bit
tx = 0;
@(posedge tx_clk_divided);
-> device_sent_packet;
@(sent_packet_received);
tx_framing_wrong = 0;
// TX data
tx = 1;
tx_data = 8'hFF;
// Sending tx_data bits
for (tx_bit_index = 0; tx_bit_index < tx_length; tx_bit_index = tx_bit_index + 1)
begin
@(posedge tx_clk_divided);
tx = tx_data[tx_bit_index];
end
// Wait for almost 1 bit
#(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor); // wait half period
#((((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) - 2); // wait 2 less than half period
sent_data = tx_data;
// Calculating parity
if(tx_length == 5)
begin
tx_parity_xor = ^tx_data[4:0];
end
else if(tx_length == 6)
begin
tx_parity_xor = ^tx_data[5:0];
end
else if(tx_length == 7)
begin
tx_parity_xor = ^tx_data[6:0];
end
else if(tx_length == 8)
begin
tx_parity_xor = ^tx_data[7:0];
end
else
$display("WRONG length of TX data packet");
// Sending parity bit
if (tx_parity_enabled)
begin
@(posedge tx_clk_divided);
if (tx_odd_parity)
tx = tx_parity_wrong ^ (~tx_parity_xor);
else if (tx_even_parity)
tx = tx_parity_wrong ^ tx_parity_xor;
else if (tx_stick1_parity)
tx = tx_parity_wrong ^ 1;
else if (tx_stick0_parity)
tx = tx_parity_wrong ^ 0;
// Wait for almost 1 bit
#(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor); // wait half period
#((((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) - 2); // wait 2 less than half period
end
// Stop bit
@(posedge tx_clk_divided);
tx = 1;
// Wait for almost 1 bit
#(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor); // wait half period
#((((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) - 2); // wait 2 less than half period
-> device_sent_packet;
@(sent_packet_received);
tx_framing_wrong = 1'b1;
end
else if (last_tx_data)
begin
@(posedge tx_clk_divided);
-> device_sent_packet;
@(sent_packet_received);
end
end
end
endtask // send_packet
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__XOR2_PP_BLACKBOX_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR2_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVKAPWR_PP_SYMBOL_V
`define SKY130_FD_SC_LP__INVKAPWR_PP_SYMBOL_V
/**
* invkapwr: Inverter on keep-alive power rail.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__invkapwr (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input KAPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVKAPWR_PP_SYMBOL_V
|
// -*- Mode: Verilog -*-
// Filename : test_tasks.v
// Description : Tasks to help test the code
// Author : Philip Tracton
// Created On : Fri Dec 4 12:34:28 2015
// Last Modified By: Philip Tracton
// Last Modified On: Fri Dec 4 12:34:28 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`include "wb_dsp_includes.vh"
module test_tasks (/*AUTOARG*/ ) ;
reg test_case_fail = 1;
reg test_passed = 1'b0;
reg test_failed = 1'b0;
integer test_count = 0;
always @(posedge test_passed) begin
$display("--------------------------------------------------------------------------------------------");
$display("\n\n\033[1;32mTEST PASSED\033[0m @ %d", $time);
#10 $finish;
end
always @(posedge test_failed) begin
$display("--------------------------------------------------------------------------------------------");
$display("\n\033[1;31m***** TEST FAILED *****\033[0m @ %d\n", $time);
#100 $finish;
end
//
// Do not let a test bench just run forever.
//
initial begin
#50000000;
$display("TEST CASE TIMEOUT @ %d", $time);
test_failed <= 1'b1;
end
/****************************************************************************
TASK: all_tests_completed
PARAMETERS:
OPERATION:
This task is called at the end of a test case to indicate it is done.
If the correct number of test cases were executed we indicate this test
has passed. Otherwise we indicate failure.
***************************************************************************/
task all_tests_completed;
begin
if (`NUMBER_OF_TESTS == test_count) begin
`TEST_PASSED <= 1;
end else begin
$display("INCORRECT NUMBER OF TESTS! Exp: %d Ran: %d", `NUMBER_OF_TESTS, test_count);
`TEST_FAILED <= 1;
end
end
endtask // if
/****************************************************************************
TASK: compare_values
PARAMETERS:
input [8*80:1] display_string; -- Test to indicate which test this is
input [31:0] expected; -- Expected correct value
input [31:0] measured; -- Actual measured value
OPERATION:
This task is the one called from the test cases. It checks for bad data (X)
and compares the expected and measured values. Sets the pass/fail flag
and calls the display_results task.
***************************************************************************/
task compare_values;
input [8*80:1] display_string;
input [31:0] expected;
input [31:0] measured;
begin
if (|measured == 1'bX) begin
display_results("Data is X", expected, measured);
`TEST_FAILED <= 1'b1;
end else begin
if (expected !== measured) begin
test_case_fail <= 1;
//$display("EXP: 0x%h\tMeasure:0x%h", expected, measured);
#1 display_results(display_string, expected, measured);
end else begin
test_case_fail <= 0;
#1 display_results(display_string, expected, measured);
end
end
end
endtask
/****************************************************************************
TASK: display_results
PARAMETERS:
input [8*80:1] display_string; -- Test to indicate which test this is
input [31:0] expected; -- Expected correct value
input [31:0] measured; -- Actual measured value
OPERATION:
This task will display the table of tests with their time stamp,
test number, string, expected, measured and results.
***************************************************************************/
task display_results;
input [8*80:1] display_string;
input [31:0] expected;
input [31:0] measured;
reg [17*8-1:0] pass_fail;
begin
if (test_case_fail) begin
pass_fail = "\033[1;31mFAIL\033[0m";
`TEST_FAILED <= 1;
end else begin
pass_fail = "\033[1;32mPASS\033[0m";
end
// left justify string
while (display_string[8*35:8*35-7] == 8'h00)begin
display_string = {display_string," "};
end
if (test_count == 0) begin
$display("--------------------------------------------------------------------------------------------");
$display("|TIME |Test| \tTest Case \t\t\t\t|Expected |\tMeasured | State |");
$display("--------------------------------------------------------------------------------------------");
end
test_count <= test_count + 1;
$display("|%4d |%4d|\t%0s \t|0x%8h |\t0x%8h |%s |", $time-1, test_count, display_string, expected, measured, pass_fail);
if (((test_count %10) == 0) && test_count >0) begin
$display("--------------------------------------------------------------------------------------------");
end
end
endtask //
endmodule // test_tasks
|
//*******************************************************************************************************************************************************/
// Module Name: smr_reg
// Module Type: Synchronous Register
// Author: Shreyas Vinod
// Purpose: Memory Address Register (MAR) and Program Counter (PC) for Neptune I v3.0
// Description: A synchronous register specifically designed for Neptune I's Memory Address Register (MAR) and Program Counter (PC) with memory reset
// support.
//*******************************************************************************************************************************************************/
module smr_reg(clk, rst, we, incr, wr, rd);
// Parameter Definitions
parameter width = 'd16; // Register Width
parameter add_width = 'd13; // Addressing Width, cannot be larger than the Data Width
// Inputs
input wire clk /* System Clock Input */, rst /* System Reset. Resets memory contents. */; // Management Interfaces
input wire we /* Register Write Enable */, incr /* Increment contents */; // Control Interfaces
input wire [width-1:0] wr /* Write Port */;
// Outputs
output wire [add_width-1:0] rd /* Read Port to A Bus */;
// Internal
reg [width-1:0] mem /* Register Memory */;
// Read Logic
assign rd [add_width-1:0] = mem [add_width-1:0];
// Memory Write Block
always@(posedge clk) begin
if(rst) mem [width-1:0] <= {width{1'b0}}; // Resets the contents of memory if rst is true.
else if(we) mem [width-1:0] <= wr [width-1:0]; // Writes the value at wr to memory if we is true.
else if(incr) mem [width-1:0] <= mem [width-1:0] + 1'b1; // Increment Memory contents.
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32OI_SYMBOL_V
`define SKY130_FD_SC_LS__A32OI_SYMBOL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a32oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32OI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311O_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A311O_PP_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a311o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311O_PP_SYMBOL_V
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:22:53 06/15/2015
// Design Name:
// Module Name: scratch_register
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module scratch_register(
input wire clk,
input wire poweron_rst_n,
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire zxuno_regwr,
input wire [7:0] din,
output reg [7:0] dout,
output wire oe_n
);
parameter SCRATCH = 8'hFE;
assign oe_n = ~(zxuno_addr == SCRATCH && zxuno_regrd == 1'b1);
reg [7:0] scratch = 8'h00; // initial value
always @(posedge clk) begin
if (poweron_rst_n == 1'b0)
scratch <= 8'h00; // or after a hardware reset (not implemented yet)
else if (zxuno_addr == SCRATCH && zxuno_regwr == 1'b1)
scratch <= din;
dout <= scratch;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
|
//wb_nysa_artemis_platform.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x00000000
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:artemis_platform
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x022
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x02
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/05/23
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:3
*/
`unconnected_drive pull0
module wb_nysa_artemis_platform #(
parameter DDR3_W0_CH = 1,
parameter DDR3_R0_CH = 1,
parameter DDR3_W1_CH = 0,
parameter DDR3_R1_CH = 0,
parameter DDR3_RW0_CH = 0
)(
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int,
//output o_wbs_int
output calibration_done,
output ddr3_rst,
//output ddr3_clk_out,
//input ddr3_clk_in,
inout [7:0] ddr3_dram_dq,
output [13:0] ddr3_dram_a,
output [2:0] ddr3_dram_ba,
output ddr3_dram_ras_n,
output ddr3_dram_cas_n,
output ddr3_dram_we_n,
output ddr3_dram_odt,
output ddr3_dram_reset_n,
output ddr3_dram_cke,
output ddr3_dram_dm,
inout ddr3_dram_rzq,
inout ddr3_dram_zio,
inout ddr3_dram_dqs,
inout ddr3_dram_dqs_n,
output ddr3_dram_ck,
output ddr3_dram_ck_n,
//Write Channel 0
input w0_write_enable,
input [63:0] w0_write_addr,
input w0_write_addr_inc,
input w0_write_addr_dec,
output w0_write_finished,
input [31:0] w0_write_count,
input w0_write_flush,
output [1:0] w0_write_ready,
input [1:0] w0_write_activate,
output [23:0] w0_write_size,
input w0_write_strobe,
input [31:0] w0_write_data,
//Write Channel 1
input w1_write_enable,
input [63:0] w1_write_addr,
input w1_write_addr_inc,
input w1_write_addr_dec,
output w1_write_finished,
input [31:0] w1_write_count,
input w1_write_flush,
output [1:0] w1_write_ready,
input [1:0] w1_write_activate,
output [23:0] w1_write_size,
input w1_write_strobe,
input [31:0] w1_write_data,
//Read Channel 0
input r0_read_enable,
input [63:0] r0_read_addr,
input r0_read_addr_inc,
input r0_read_addr_dec,
output r0_read_busy,
output r0_read_error,
input [23:0] r0_read_count,
input r0_read_flush,
output r0_read_ready,
input r0_read_activate,
output [23:0] r0_read_size,
output [31:0] r0_read_data,
input r0_read_strobe,
//Read Channel 1
input r1_read_enable,
input [63:0] r1_read_addr,
input r1_read_addr_inc,
input r1_read_addr_dec,
output r1_read_busy,
output r1_read_error,
input [23:0] r1_read_count,
input r1_read_flush,
output r1_read_ready,
input r1_read_activate,
output [23:0] r1_read_size,
output [31:0] r1_read_data,
input r1_read_strobe,
//Read/Write Channel 0
input rw0_read_enable,
input [63:0] rw0_read_addr,
input rw0_read_addr_inc,
input rw0_read_addr_dec,
output rw0_read_busy,
output rw0_read_error,
input [23:0] rw0_read_count,
input rw0_read_flush,
output rw0_read_ready,
input rw0_read_activate,
output [23:0] rw0_read_size,
output [31:0] rw0_read_data,
input rw0_read_strobe,
input rw0_write_enable,
input [63:0] rw0_write_addr,
input rw0_write_addr_inc,
input rw0_write_addr_dec,
output rw0_write_finished,
input [31:0] rw0_write_count,
input rw0_write_flush,
output [1:0] rw0_write_ready,
input [1:0] rw0_write_activate,
output [23:0] rw0_write_size,
input rw0_write_strobe,
input [31:0] rw0_write_data,
input p0_cmd_clk,
input p0_cmd_en,
input [2:0] p0_cmd_instr,
input [5:0] p0_cmd_bl,
input [29:0] p0_cmd_byte_addr,
output p0_cmd_empty,
output p0_cmd_full,
input p0_wr_clk,
input p0_wr_en,
input [3:0] p0_wr_mask,
input [31:0] p0_wr_data,
output p0_wr_full,
output p0_wr_empty,
output [6:0] p0_wr_count,
output p0_wr_underrun,
output p0_wr_error,
input p0_rd_clk,
input p0_rd_en,
output [31:0] p0_rd_data,
output p0_rd_full,
output p0_rd_empty,
output [6:0] p0_rd_count,
output p0_rd_overflow,
output p0_rd_error
);
//Local Parameters
localparam CONTROL = 32'h00000000;
localparam BIT_CALIBRATION_DONE = 0;
localparam BIT_DDR3_RST = 1;
localparam BIT_P0_ENABLE = 2;
localparam BIT_P1_ENABLE = 3;
localparam BIT_P2_ENABLE = 4;
localparam BIT_P3_ENABLE = 5;
localparam BIT_P4_ENABLE = 6;
localparam BIT_P5_ENABLE = 7;
localparam BIT_PLL_LOCKED = 8;
localparam DDR3_STATUS0 = 32'h00000001;
localparam BIT_P0_RD_FULL = 0;
localparam BIT_P0_RD_EMPTY = 1;
localparam BIT_P0_RD_OVERFLOW = 2;
localparam BIT_P0_RD_ERROR = 3;
localparam BIT_P0_WR_EMPTY = 4;
localparam BIT_P0_WR_FULL = 5;
localparam BIT_P0_WR_UNDERRUN = 6;
localparam BIT_P1_RD_FULL = 0 + 8;
localparam BIT_P1_RD_EMPTY = 1 + 8;
localparam BIT_P1_RD_OVERFLOW = 2 + 8;
localparam BIT_P1_RD_ERROR = 3 + 8;
localparam BIT_P1_WR_EMPTY = 4 + 8;
localparam BIT_P1_WR_FULL = 5 + 8;
localparam BIT_P1_WR_UNDERRUN = 6 + 8;
localparam BIT_P2_RD_FULL = 0 + 16;
localparam BIT_P2_RD_EMPTY = 1 + 16;
localparam BIT_P2_RD_OVERFLOW = 2 + 16;
localparam BIT_P2_RD_ERROR = 3 + 16;
localparam BIT_P2_WR_EMPTY = 4 + 16;
localparam BIT_P2_WR_FULL = 5 + 16;
localparam BIT_P2_WR_UNDERRUN = 6 + 16;
localparam BIT_P3_RD_FULL = 0 + 24;
localparam BIT_P3_RD_EMPTY = 1 + 24;
localparam BIT_P3_RD_OVERFLOW = 2 + 24;
localparam BIT_P3_RD_ERROR = 3 + 24;
localparam BIT_P3_WR_EMPTY = 4 + 24;
localparam BIT_P3_WR_FULL = 5 + 24;
localparam BIT_P3_WR_UNDERRUN = 6 + 24;
localparam DDR3_STATUS1 = 32'h00000002;
localparam BIT_P4_RD_FULL = 0;
localparam BIT_P4_RD_EMPTY = 1;
localparam BIT_P4_RD_OVERFLOW = 2;
localparam BIT_P4_RD_ERROR = 3;
localparam BIT_P4_WR_EMPTY = 4;
localparam BIT_P4_WR_FULL = 5;
localparam BIT_P4_WR_UNDERRUN = 6;
localparam BIT_P5_RD_FULL = 0 + 8;
localparam BIT_P5_RD_EMPTY = 1 + 8;
localparam BIT_P5_RD_OVERFLOW = 2 + 8;
localparam BIT_P5_RD_ERROR = 3 + 8;
localparam BIT_P5_WR_EMPTY = 4 + 8;
localparam BIT_P5_WR_FULL = 5 + 8;
localparam BIT_P5_WR_UNDERRUN = 6 + 8;
//Local Registers/Wires
wire pll_locked;
wire p1_cmd_clk;
wire p1_cmd_en;
wire [2:0] p1_cmd_instr;
wire [5:0] p1_cmd_bl;
wire [29:0] p1_cmd_byte_addr;
wire p1_cmd_empty;
wire p1_cmd_full;
wire p1_wr_clk;
wire p1_wr_en;
wire [3:0] p1_wr_mask;
wire [31:0] p1_wr_data;
wire p1_wr_full;
wire p1_wr_empty;
wire [6:0] p1_wr_count;
wire p1_wr_underrun;
wire p1_wr_error;
wire p1_rd_clk;
wire p1_rd_en;
wire [31:0] p1_rd_data;
wire p1_rd_full;
wire p1_rd_empty;
wire [6:0] p1_rd_count;
wire p1_rd_overflow;
wire p1_rd_error;
wire p2_cmd_clk;
wire p2_cmd_en;
wire [2:0] p2_cmd_instr;
wire [5:0] p2_cmd_bl;
wire [29:0] p2_cmd_byte_addr;
wire p2_cmd_empty;
wire p2_cmd_full;
wire p2_wr_clk;
wire p2_wr_en;
wire [3:0] p2_wr_mask;
wire [31:0] p2_wr_data;
wire p2_wr_full;
wire p2_wr_empty;
wire [6:0] p2_wr_count;
wire p2_wr_underrun;
wire p2_wr_error;
wire p3_cmd_clk;
wire p3_cmd_en;
wire [2:0] p3_cmd_instr;
wire [5:0] p3_cmd_bl;
wire [29:0] p3_cmd_byte_addr;
wire p3_cmd_empty;
wire p3_cmd_full;
wire p3_wr_clk;
wire p3_wr_en;
wire [3:0] p3_wr_mask;
wire [31:0] p3_wr_data;
wire p3_wr_full;
wire p3_wr_empty;
wire [6:0] p3_wr_count;
wire p3_wr_underrun;
wire p3_wr_error;
wire p4_cmd_clk;
wire p4_cmd_en;
wire [2:0] p4_cmd_instr;
wire [5:0] p4_cmd_bl;
wire [29:0] p4_cmd_byte_addr;
wire p4_cmd_empty;
wire p4_cmd_full;
wire p4_rd_clk;
wire p4_rd_en;
wire [31:0] p4_rd_data;
wire p4_rd_full;
wire p4_rd_empty;
wire [6:0] p4_rd_count;
wire p4_rd_overflow;
wire p4_rd_error;
wire p5_cmd_clk;
wire p5_cmd_en;
wire [2:0] p5_cmd_instr;
wire [5:0] p5_cmd_bl;
wire [29:0] p5_cmd_byte_addr;
wire p5_cmd_empty;
wire p5_cmd_full;
wire p5_rd_clk;
wire p5_rd_en;
wire [31:0] p5_rd_data;
wire p5_rd_full;
wire p5_rd_empty;
wire [6:0] p5_rd_count;
wire p5_rd_overflow;
wire p5_rd_error;
wire usr_clk;
reg ddr3_rst_in;
reg [15:0] ddr3_rst_in_count;
(* KEEP = "TRUE" *) wire ddr3_clk;
//wire startup_rst;
//Submodules
/*
STARTUP_SPARTAN6 strtup (
.GSR (startup_rst )
);
*/
artemis_clkgen clkgen(
.clk (clk ),
.rst (rst ),
.locked (pll_locked ),
.ddr3_clk (ddr3_clk )
);
artemis_ddr3 artemis_ddr3_cntrl(
.clk_333mhz (ddr3_clk ),
//.board_rst (rst || !pll_locked ),
.board_rst (ddr3_rst_in ),
.calibration_done (calibration_done ),
.usr_clk (usr_clk ),
.rst (ddr3_rst ),
.ddr3_dram_dq (ddr3_dram_dq ),
.ddr3_dram_a (ddr3_dram_a ),
.ddr3_dram_ba (ddr3_dram_ba ),
.ddr3_dram_ras_n (ddr3_dram_ras_n ),
.ddr3_dram_cas_n (ddr3_dram_cas_n ),
.ddr3_dram_we_n (ddr3_dram_we_n ),
.ddr3_dram_odt (ddr3_dram_odt ),
.ddr3_dram_reset_n (ddr3_dram_reset_n ),
.ddr3_dram_cke (ddr3_dram_cke ),
.ddr3_dram_dm (ddr3_dram_dm ),
.ddr3_rzq (ddr3_dram_rzq ),
.ddr3_zio (ddr3_dram_zio ),
.ddr3_dram_dqs (ddr3_dram_dqs ),
.ddr3_dram_dqs_n (ddr3_dram_dqs_n ),
.ddr3_dram_ck (ddr3_dram_ck ),
.ddr3_dram_ck_n (ddr3_dram_ck_n ),
.p0_cmd_clk (p0_cmd_clk ),
.p0_cmd_en (p0_cmd_en ),
.p0_cmd_instr (p0_cmd_instr ),
.p0_cmd_bl (p0_cmd_bl ),
.p0_cmd_byte_addr (p0_cmd_byte_addr ),
.p0_cmd_empty (p0_cmd_empty ),
.p0_cmd_full (p0_cmd_full ),
.p0_wr_clk (p0_wr_clk ),
.p0_wr_en (p0_wr_en ),
.p0_wr_mask (p0_wr_mask ),
.p0_wr_data (p0_wr_data ),
.p0_wr_full (p0_wr_full ),
.p0_wr_empty (p0_wr_empty ),
.p0_wr_count (p0_wr_count ),
.p0_wr_underrun (p0_wr_underrun ),
.p0_wr_error (p0_wr_error ),
.p0_rd_clk (p0_rd_clk ),
.p0_rd_en (p0_rd_en ),
.p0_rd_data (p0_rd_data ),
.p0_rd_full (p0_rd_full ),
.p0_rd_empty (p0_rd_empty ),
.p0_rd_count (p0_rd_count ),
.p0_rd_overflow (p0_rd_overflow ),
.p0_rd_error (p0_rd_error ),
.p1_cmd_clk (p1_cmd_clk ),
.p1_cmd_en (p1_cmd_en ),
.p1_cmd_instr (p1_cmd_instr ),
.p1_cmd_bl (p1_cmd_bl ),
.p1_cmd_byte_addr (p1_cmd_byte_addr ),
.p1_cmd_empty (p1_cmd_empty ),
.p1_cmd_full (p1_cmd_full ),
.p1_wr_clk (p1_wr_clk ),
.p1_wr_en (p1_wr_en ),
.p1_wr_mask (p1_wr_mask ),
.p1_wr_data (p1_wr_data ),
.p1_wr_full (p1_wr_full ),
.p1_wr_empty (p1_wr_empty ),
.p1_wr_count (p1_wr_count ),
.p1_wr_underrun (p1_wr_underrun ),
.p1_wr_error (p1_wr_error ),
.p1_rd_clk (p1_rd_clk ),
.p1_rd_en (p1_rd_en ),
.p1_rd_data (p1_rd_data ),
.p1_rd_full (p1_rd_full ),
.p1_rd_empty (p1_rd_empty ),
.p1_rd_count (p1_rd_count ),
.p1_rd_overflow (p1_rd_overflow ),
.p1_rd_error (p1_rd_error ),
.p2_cmd_clk (p2_cmd_clk ),
.p2_cmd_en (p2_cmd_en ),
.p2_cmd_instr (p2_cmd_instr ),
.p2_cmd_bl (p2_cmd_bl ),
.p2_cmd_byte_addr (p2_cmd_byte_addr ),
.p2_cmd_empty (p2_cmd_empty ),
.p2_cmd_full (p2_cmd_full ),
.p2_wr_clk (p2_wr_clk ),
.p2_wr_en (p2_wr_en ),
.p2_wr_mask (p2_wr_mask ),
.p2_wr_data (p2_wr_data ),
.p2_wr_full (p2_wr_full ),
.p2_wr_empty (p2_wr_empty ),
.p2_wr_count (p2_wr_count ),
.p2_wr_underrun (p2_wr_underrun ),
.p2_wr_error (p2_wr_error ),
.p3_cmd_clk (p3_cmd_clk ),
.p3_cmd_en (p3_cmd_en ),
.p3_cmd_instr (p3_cmd_instr ),
.p3_cmd_bl (p3_cmd_bl ),
.p3_cmd_byte_addr (p3_cmd_byte_addr ),
.p3_cmd_empty (p3_cmd_empty ),
.p3_cmd_full (p3_cmd_full ),
.p3_wr_clk (p3_wr_clk ),
.p3_wr_en (p3_wr_en ),
.p3_wr_mask (p3_wr_mask ),
.p3_wr_data (p3_wr_data ),
.p3_wr_full (p3_wr_full ),
.p3_wr_empty (p3_wr_empty ),
.p3_wr_count (p3_wr_count ),
.p3_wr_underrun (p3_wr_underrun ),
.p3_wr_error (p3_wr_error ),
.p4_cmd_clk (p4_cmd_clk ),
.p4_cmd_en (p4_cmd_en ),
.p4_cmd_instr (p4_cmd_instr ),
.p4_cmd_bl (p4_cmd_bl ),
.p4_cmd_byte_addr (p4_cmd_byte_addr ),
.p4_cmd_empty (p4_cmd_empty ),
.p4_cmd_full (p4_cmd_full ),
.p4_rd_clk (p4_rd_clk ),
.p4_rd_en (p4_rd_en ),
.p4_rd_data (p4_rd_data ),
.p4_rd_full (p4_rd_full ),
.p4_rd_empty (p4_rd_empty ),
.p4_rd_count (p4_rd_count ),
.p4_rd_overflow (p4_rd_overflow ),
.p4_rd_error (p4_rd_error ),
.p5_cmd_clk (p5_cmd_clk ),
.p5_cmd_en (p5_cmd_en ),
.p5_cmd_instr (p5_cmd_instr ),
.p5_cmd_bl (p5_cmd_bl ),
.p5_cmd_byte_addr (p5_cmd_byte_addr ),
.p5_cmd_empty (p5_cmd_empty ),
.p5_cmd_full (p5_cmd_full ),
.p5_rd_clk (p5_rd_clk ),
.p5_rd_en (p5_rd_en ),
.p5_rd_data (p5_rd_data ),
.p5_rd_full (p5_rd_full ),
.p5_rd_empty (p5_rd_empty ),
.p5_rd_count (p5_rd_count ),
.p5_rd_overflow (p5_rd_overflow ),
.p5_rd_error (p5_rd_error )
);
generate
if (DDR3_W0_CH) begin
assign p2_cmd_clk = clk;
assign p2_wr_clk = clk;
ddr3_dma w0(
.clk (clk ),
.rst (rst ),
//Write Side
.write_enable (w0_write_enable ),
.write_addr (w0_write_addr ),
.write_addr_inc (w0_write_addr_inc ),
.write_addr_dec (w0_write_addr_dec ),
.write_finished (w0_write_finished ),
.write_count (w0_write_count ),
.write_flush (w0_write_flush ),
.write_ready (w0_write_ready ),
.write_activate (w0_write_activate ),
.write_size (w0_write_size ),
.write_strobe (w0_write_strobe ),
.write_data (w0_write_data ),
//Read Side
.read_enable (1'b0 ),
.read_addr (64'b0 ),
.read_addr_inc (1'b0 ),
.read_addr_dec (1'b0 ),
.read_count (24'b0 ),
.read_flush (1'b0 ),
.read_busy ( ),
.read_activate (1'b0 ),
.read_strobe (1'b0 ),
//Local Registers/Wires
.cmd_en (p2_cmd_en ),
.cmd_instr (p2_cmd_instr ),
.cmd_bl (p2_cmd_bl ),
.cmd_byte_addr (p2_cmd_byte_addr ),
.cmd_empty (p2_cmd_empty ),
.cmd_full (p2_cmd_full ),
.wr_en (p2_wr_en ),
.wr_mask (p2_wr_mask ),
.wr_data (p2_wr_data ),
.wr_full (p2_wr_full ),
.wr_empty (p2_wr_empty ),
.wr_count (p2_wr_count ),
.wr_underrun (p2_wr_underrun ),
.wr_error (p2_wr_error ),
.rd_data (32'b0 ),
.rd_full (1'b0 ),
.rd_empty (1'b1 ),
.rd_count (24'b0 ),
.rd_overflow (1'b0 ),
.rd_error (1'b0 )
);
end
else begin
assign p2_cmd_clk = 0;
assign p2_cmd_instr = 0;
assign p2_cmd_en = 0;
assign p2_cmd_bl = 0;
assign p2_cmd_byte_addr = 0;
assign p2_wr_clk = 0;
assign p2_wr_en = 0;
assign p2_wr_mask = 0;
assign p2_wr_data = 0;
assign w0_write_finished = 0;
assign w0_write_ready = 0;
assign w0_write_size = 0;
end
endgenerate
generate
if (DDR3_W1_CH) begin
assign p3_cmd_clk = clk;
assign p3_wr_clk = clk;
ddr3_dma w1(
.clk (clk ),
.rst (rst ),
//Write Side
.write_enable (w1_write_enable ),
.write_addr (w1_write_addr ),
.write_addr_inc (w1_write_addr_inc ),
.write_addr_dec (w1_write_addr_dec ),
.write_finished (w1_write_finished ),
.write_count (w1_write_count ),
.write_flush (w1_write_flush ),
.write_ready (w1_write_ready ),
.write_activate (w1_write_activate ),
.write_size (w1_write_size ),
.write_strobe (w1_write_strobe ),
.write_data (w1_write_data ),
//Read Side
.read_enable (1'b0 ),
.read_addr (64'b0 ),
.read_addr_inc (1'b0 ),
.read_addr_dec (1'b0 ),
.read_count (24'b0 ),
.read_flush (1'b0 ),
.read_busy ( ),
.read_activate (1'b0 ),
.read_strobe (1'b0 ),
//Local Registers/Wires
.cmd_en (p3_cmd_en ),
.cmd_instr (p3_cmd_instr ),
.cmd_bl (p3_cmd_bl ),
.cmd_byte_addr (p3_cmd_byte_addr ),
.cmd_empty (p3_cmd_empty ),
.cmd_full (p3_cmd_full ),
.wr_en (p3_wr_en ),
.wr_mask (p3_wr_mask ),
.wr_data (p3_wr_data ),
.wr_full (p3_wr_full ),
.wr_empty (p3_wr_empty ),
.wr_count (p3_wr_count ),
.wr_underrun (p3_wr_underrun ),
.wr_error (p3_wr_error ),
.rd_data (32'b0 ),
.rd_full (1'b0 ),
.rd_empty (1'b1 ),
.rd_count (24'b0 ),
.rd_overflow (1'b0 ),
.rd_error (1'b0 )
);
end
else begin
assign p3_cmd_clk = 0;
assign p3_cmd_instr = 0;
assign p3_cmd_en = 0;
assign p3_cmd_bl = 0;
assign p3_cmd_byte_addr = 0;
assign p3_wr_clk = 0;
assign p3_wr_en = 0;
assign p3_wr_mask = 0;
assign p3_wr_data = 0;
assign w1_write_finished = 0;
assign w1_write_ready = 0;
assign w1_write_size = 0;
end
endgenerate
generate
if (DDR3_R0_CH) begin
assign p4_cmd_clk = clk;
assign p4_rd_clk = clk;
ddr3_dma r0(
.clk (clk ),
.rst (rst ),
//Write Side
.write_enable (1'b0 ),
.write_addr (64'b0 ),
.write_addr_inc (1'b0 ),
.write_addr_dec (1'b0 ),
.write_count (24'b0 ),
.write_activate (1'b0 ),
.write_strobe (1'b0 ),
.write_data (32'b0 ),
//Read Side
.read_enable (r0_read_enable ),
.read_addr (r0_read_addr ),
.read_addr_inc (r0_read_addr_inc ),
.read_addr_dec (r0_read_addr_dec ),
.read_busy (r0_read_busy ),
.read_error (r0_read_error ),
.read_count (r0_read_count ),
.read_flush (r0_read_flush ),
.read_ready (r0_read_ready ),
.read_activate (r0_read_activate ),
.read_size (r0_read_size ),
.read_data (r0_read_data ),
.read_strobe (r0_read_strobe ),
//Local Registers/Wires
.cmd_en (p4_cmd_en ),
.cmd_instr (p4_cmd_instr ),
.cmd_bl (p4_cmd_bl ),
.cmd_byte_addr (p4_cmd_byte_addr ),
.cmd_empty (p4_cmd_empty ),
.cmd_full (p4_cmd_full ),
.wr_full (1'b0 ),
.wr_empty (1'b1 ),
.wr_count (7'b0 ),
.wr_underrun (1'b0 ),
.wr_error (1'b0 ),
.rd_en (p4_rd_en ),
.rd_data (p4_rd_data ),
.rd_full (p4_rd_full ),
.rd_empty (p4_rd_empty ),
.rd_count (p4_rd_count ),
.rd_overflow (p4_rd_overflow ),
.rd_error (p4_rd_error )
);
end
else begin
assign p4_cmd_clk = 0;
assign p4_cmd_en = 0;
assign p4_cmd_instr = 0;
assign p4_cmd_bl = 0;
assign p4_cmd_byte_addr = 0;
assign p4_rd_clk = 0;
assign p4_rd_en = 0;
assign r0_read_busy = 0;
assign r0_read_error = 0;
assign r0_read_ready = 0;
assign r0_read_size = 0;
assign r0_read_data = 0;
end
endgenerate
generate
if (DDR3_R1_CH) begin
assign p5_cmd_clk = clk;
assign p5_rd_clk = clk;
ddr3_dma r1(
.clk (clk ),
.rst (rst ),
//Write Side
.write_enable (1'b0 ),
.write_addr (64'b0 ),
.write_addr_inc (1'b0 ),
.write_addr_dec (1'b0 ),
.write_count (24'b0 ),
.write_activate (1'b0 ),
.write_strobe (1'b0 ),
.write_data (32'b0 ),
//Read Side
.read_enable (r1_read_enable ),
.read_addr (r1_read_addr ),
.read_addr_inc (r1_read_addr_inc ),
.read_addr_dec (r1_read_addr_dec ),
.read_busy (r1_read_busy ),
.read_error (r1_read_error ),
.read_count (r1_read_count ),
.read_flush (r1_read_flush ),
.read_ready (r1_read_ready ),
.read_activate (r1_read_activate ),
.read_size (r1_read_size ),
.read_data (r1_read_data ),
.read_strobe (r1_read_strobe ),
.cmd_en (p5_cmd_en ),
.cmd_instr (p5_cmd_instr ),
.cmd_bl (p5_cmd_bl ),
.cmd_byte_addr (p5_cmd_byte_addr ),
.cmd_empty (p5_cmd_empty ),
.cmd_full (p5_cmd_full ),
.wr_full (1'b0 ),
.wr_empty (1'b1 ),
.wr_count (7'b0 ),
.wr_underrun (1'b0 ),
.wr_error (1'b0 ),
.rd_en (p5_rd_en ),
.rd_data (p5_rd_data ),
.rd_full (p5_rd_full ),
.rd_empty (p5_rd_empty ),
.rd_count (p5_rd_count ),
.rd_overflow (p5_rd_overflow ),
.rd_error (p5_rd_error )
);
end
else begin
assign p5_cmd_clk = 0;
assign p5_cmd_en = 0;
assign p5_cmd_instr = 0;
assign p5_cmd_bl = 0;
assign p5_cmd_byte_addr = 0;
assign p5_rd_clk = 0;
assign p5_rd_en = 0;
assign r1_read_busy = 0;
assign r1_read_error = 0;
assign r1_read_ready = 0;
assign r1_read_size = 0;
assign r1_read_data = 0;
end
endgenerate
generate
if (DDR3_RW0_CH) begin
assign p1_cmd_clk = clk;
assign p1_wr_clk = clk;
assign p1_rd_clk = clk;
ddr3_dma rw0(
.clk (clk ),
.rst (rst ),
//Write Side
.write_enable (rw0_write_enable ),
.write_addr (rw0_write_addr ),
.write_addr_inc (rw0_write_addr_inc ),
.write_addr_dec (rw0_write_addr_dec ),
.write_finished (rw0_write_finished ),
.write_count (rw0_write_count ),
.write_flush (rw0_write_flush ),
.write_ready (rw0_write_ready ),
.write_activate (rw0_write_activate ),
.write_size (rw0_write_size ),
.write_strobe (rw0_write_strobe ),
.write_data (rw0_write_data ),
//Read Side
.read_enable (rw0_read_enable ),
.read_addr (rw0_read_addr ),
.read_addr_inc (rw0_read_addr_inc ),
.read_addr_dec (rw0_read_addr_dec ),
.read_busy (rw0_read_busy ),
.read_error (rw0_read_error ),
.read_count (rw0_read_count ),
.read_flush (rw0_read_flush ),
.read_ready (rw0_read_ready ),
.read_activate (rw0_read_activate ),
.read_size (rw0_read_size ),
.read_data (rw0_read_data ),
.read_strobe (rw0_read_strobe ),
//Memory Interfaces
.cmd_en (p1_cmd_en ),
.cmd_instr (p1_cmd_instr ),
.cmd_bl (p1_cmd_bl ),
.cmd_byte_addr (p1_cmd_byte_addr ),
.cmd_empty (p1_cmd_empty ),
.cmd_full (p1_cmd_full ),
.wr_en (p1_wr_en ),
.wr_mask (p1_wr_mask ),
.wr_data (p1_wr_data ),
.wr_full (p1_wr_full ),
.wr_empty (p1_wr_empty ),
.wr_count (p1_wr_count ),
.wr_underrun (p1_wr_underrun ),
.wr_error (p1_wr_error ),
.rd_en (p1_rd_en ),
.rd_data (p1_rd_data ),
.rd_full (p1_rd_full ),
.rd_empty (p1_rd_empty ),
.rd_count (p1_rd_count ),
.rd_overflow (p1_rd_overflow ),
.rd_error (p1_rd_error )
);
end
else begin
assign p1_cmd_clk = 0;
assign p1_cmd_en = 0;
assign p1_cmd_instr = 0;
assign p1_cmd_bl = 0;
assign p1_cmd_byte_addr = 0;
assign p1_wr_data = 0;
assign p1_wr_en = 0;
assign p1_wr_clk = 0;
assign p1_wr_mask = 0;
assign p1_rd_clk = 0;
assign p1_rd_en = 0;
assign rw0_read_busy = 0;
assign rw0_read_error = 0;
assign rw0_read_ready = 0;
assign rw0_read_size = 0;
assign rw0_read_data = 0;
assign rw0_write_finished = 0;
assign rw0_write_ready = 0;
assign rw0_write_size = 0;
end
endgenerate
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
CONTROL: begin
end
default: begin
end
endcase
end
else begin
//read request
case (i_wbs_adr)
CONTROL: begin
o_wbs_dat <= 32'h00;
o_wbs_dat[BIT_CALIBRATION_DONE] <= calibration_done;
o_wbs_dat[BIT_PLL_LOCKED] <= pll_locked;
o_wbs_dat[BIT_DDR3_RST] <= ddr3_rst;
o_wbs_dat[BIT_P0_ENABLE] <= 1;
o_wbs_dat[BIT_P1_ENABLE] <= DDR3_RW0_CH;
o_wbs_dat[BIT_P2_ENABLE] <= DDR3_W0_CH;
o_wbs_dat[BIT_P3_ENABLE] <= DDR3_W1_CH;
o_wbs_dat[BIT_P4_ENABLE] <= DDR3_R0_CH;
o_wbs_dat[BIT_P5_ENABLE] <= DDR3_R1_CH;
end
DDR3_STATUS0: begin
o_wbs_dat <= 0;
o_wbs_dat[BIT_P0_RD_FULL] <= p0_rd_full;
o_wbs_dat[BIT_P0_RD_EMPTY] <= p0_rd_empty;
o_wbs_dat[BIT_P0_RD_OVERFLOW] <= p0_rd_overflow;
o_wbs_dat[BIT_P0_RD_ERROR] <= p0_rd_error;
o_wbs_dat[BIT_P0_WR_EMPTY] <= p0_wr_empty;
o_wbs_dat[BIT_P0_WR_FULL] <= p0_wr_full;
o_wbs_dat[BIT_P0_WR_UNDERRUN] <= p0_wr_underrun;
o_wbs_dat[BIT_P1_RD_FULL] <= p1_rd_full;
o_wbs_dat[BIT_P1_RD_EMPTY] <= p1_rd_empty;
o_wbs_dat[BIT_P1_RD_OVERFLOW] <= p1_rd_overflow;
o_wbs_dat[BIT_P1_RD_ERROR] <= p1_rd_error;
o_wbs_dat[BIT_P1_WR_EMPTY] <= p1_wr_empty;
o_wbs_dat[BIT_P1_WR_FULL] <= p1_wr_full;
o_wbs_dat[BIT_P1_WR_UNDERRUN] <= p1_wr_underrun;
o_wbs_dat[BIT_P2_RD_FULL] <= 1'b0;
o_wbs_dat[BIT_P2_RD_EMPTY] <= 1'b0;
o_wbs_dat[BIT_P2_RD_OVERFLOW] <= 1'b0;
o_wbs_dat[BIT_P2_RD_ERROR] <= 1'b0;
o_wbs_dat[BIT_P2_WR_EMPTY] <= p2_wr_empty;
o_wbs_dat[BIT_P2_WR_FULL] <= p2_wr_full;
o_wbs_dat[BIT_P2_WR_UNDERRUN] <= p2_wr_underrun;
o_wbs_dat[BIT_P3_RD_FULL] <= 1'b0;
o_wbs_dat[BIT_P3_RD_EMPTY] <= 1'b0;
o_wbs_dat[BIT_P3_RD_OVERFLOW] <= 1'b0;
o_wbs_dat[BIT_P3_RD_ERROR] <= 1'b0;
o_wbs_dat[BIT_P3_WR_EMPTY] <= p3_wr_empty;
o_wbs_dat[BIT_P3_WR_FULL] <= p3_wr_full;
o_wbs_dat[BIT_P3_WR_UNDERRUN] <= p3_wr_underrun;
end
DDR3_STATUS1: begin
o_wbs_dat <= 0;
o_wbs_dat[BIT_P4_RD_FULL] <= p4_rd_full;
o_wbs_dat[BIT_P4_RD_EMPTY] <= p4_rd_empty;
o_wbs_dat[BIT_P4_RD_OVERFLOW] <= p4_rd_overflow;
o_wbs_dat[BIT_P4_RD_ERROR] <= p4_rd_error;
o_wbs_dat[BIT_P4_WR_EMPTY] <= 1'b0;
o_wbs_dat[BIT_P4_WR_FULL] <= 1'b0;
o_wbs_dat[BIT_P4_WR_UNDERRUN] <= 1'b0;
o_wbs_dat[BIT_P5_RD_FULL] <= p5_rd_full;
o_wbs_dat[BIT_P5_RD_EMPTY] <= p5_rd_empty;
o_wbs_dat[BIT_P5_RD_OVERFLOW] <= p5_rd_overflow;
o_wbs_dat[BIT_P5_RD_ERROR] <= p5_rd_error;
o_wbs_dat[BIT_P5_WR_EMPTY] <= 1'b0;
o_wbs_dat[BIT_P5_WR_FULL] <= 1'b0;
o_wbs_dat[BIT_P5_WR_UNDERRUN] <= 1'b0;
end
default: begin
end
endcase
end
o_wbs_ack <= 1;
end
end
end
end
always @ (posedge clk) begin
if (rst || !pll_locked) begin
ddr3_rst_in_count <= 0;
ddr3_rst_in <= 1;
end
else begin
if (ddr3_rst_in_count < 16'hFFFF) begin
ddr3_rst_in <= 1;
ddr3_rst_in_count <= ddr3_rst_in_count + 16'h0001;
end
else begin
ddr3_rst_in <= 0;
end
end
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
// Date : Mon Dec 01 03:09:56 2014
// Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim
// c:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_funcsim.v
// Design : clk_wiz_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "clk_wiz_1,clk_wiz_v5_1,{component_name=clk_wiz_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_wiz_1
(clk_in1,
clk_out1,
reset,
locked);
input clk_in1;
output clk_out1;
input reset;
output locked;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
wire reset;
clk_wiz_1_clk_wiz_1_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked),
.reset(reset));
endmodule
(* ORIG_REF_NAME = "clk_wiz_1_clk_wiz" *)
module clk_wiz_1_clk_wiz_1_clk_wiz
(clk_in1,
clk_out1,
reset,
locked);
input clk_in1;
output clk_out1;
input reset;
output locked;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_in1_clk_wiz_1;
wire clk_out1;
wire clk_out1_clk_wiz_1;
wire clkfbout_buf_clk_wiz_1;
wire clkfbout_clk_wiz_1;
wire locked;
wire reset;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_wiz_1),
.O(clkfbout_buf_clk_wiz_1));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_clk_wiz_1));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_clk_wiz_1),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(36.375000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(36.375000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(4),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_wiz_1),
.CLKFBOUT(clkfbout_clk_wiz_1),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_clk_wiz_1),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_clk_wiz_1),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:01:48 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_21 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_23 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_26 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_27 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_29 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_32 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module CORDIC_Arch3v1_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, add_subt_dataA, add_subt_dataB,
result_add_subt, op_add_subt, ready_add_subt, enab_cont_iter );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
output [31:0] add_subt_dataA;
output [31:0] add_subt_dataB;
input [31:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, op_add_subt, enab_cont_iter;
wire enab_d_ff4_Zn, enab_d_ff_RB1, enab_RB3, enab_d_ff5_data_out,
d_ff1_operation_out, d_ff3_sign_out, enab_d_ff4_Yn, enab_d_ff4_Xn,
fmtted_Result_31_, ITER_CONT_net3604909, ITER_CONT_N5, ITER_CONT_N4,
ITER_CONT_N3, d_ff5_data_out_net3604886, reg_Z0_net3604886,
reg_val_muxZ_2stage_net3604886, reg_shift_y_net3604886,
d_ff4_Xn_net3604886, d_ff4_Yn_net3604886, d_ff4_Zn_net3604886, n154,
n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528,
n529, n531, n532, n533, n534, n535, n536, n537, intadd_419_CI,
intadd_419_n3, intadd_419_n2, intadd_419_n1, intadd_420_CI,
intadd_420_n3, intadd_420_n2, intadd_420_n1, n605, n606, n607, n608,
n609, n610, n611, n612, n613, n614, n615, n616, n617, n618, n619,
n620, n621, n622, n623, n624, n625, n626, n627, n628, n629, n630,
n631, n632, n633, n634, n635, n636, n637, n638, n639, n640, n641,
n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, n652,
n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663,
n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674,
n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685,
n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696,
n697, n698, n699, n700, n701, n702, n703, n704, n705, n706, n707,
n708, n709, n710, n711, n712, n713, n714, n715, n716, n717, n718,
n719, n720, n721, n722, n723, n724, n725, n726, n727, n728, n729,
n730, n731, n732, n733, n734, n735, n736, n737, n738, n739, n740,
n741, n742, n743, n744, n745, n746, n747, n748, n749, n750, n751,
n752, n753, n754, n755, n756, n757, n758, n759, n760, n761, n762,
n763, n764, n765, n766, n767, n768, n769, n770, n771, n772, n773,
n774, n775, n776, n777, n778, n779, n780, n781, n782, n783, n784,
n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, n795,
n796, n797, n798, n799, n800, n801, n802, n803, n804, n805, n806,
n807, n808, n809, n810, n811, n812, n813, n814, n815, n816, n817,
n818;
wire [3:0] cont_iter_out;
wire [1:0] cont_var_out;
wire [1:0] d_ff1_shift_region_flag_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] first_mux_X;
wire [31:0] d_ff_Yn;
wire [31:0] first_mux_Y;
wire [31:0] d_ff_Zn;
wire [31:0] first_mux_Z;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [7:0] sh_exp_x;
wire [7:0] sh_exp_y;
wire [25:4] data_out_LUT;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [30:0] mux_sal;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(enab_cont_iter), .ENCLK(ITER_CONT_net3604909), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_21 d_ff5_data_out_clk_gate_Q_reg ( .CLK(
clk), .EN(enab_d_ff5_data_out), .ENCLK(d_ff5_data_out_net3604886),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_32 reg_Z0_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff_RB1), .ENCLK(reg_Z0_net3604886), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_29 reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
reg_val_muxZ_2stage_net3604886), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_27 reg_shift_y_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_RB3), .ENCLK(reg_shift_y_net3604886), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_26 d_ff4_Xn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Xn), .ENCLK(d_ff4_Xn_net3604886), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_24 d_ff4_Yn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Yn), .ENCLK(d_ff4_Yn_net3604886), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_23 d_ff4_Zn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Zn), .ENCLK(d_ff4_Zn_net3604886), .TE(1'b0) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n816), .Q(
inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRXLTS reg_region_flag_Q_reg_0_ ( .D(shift_region_flag[0]), .CK(
reg_Z0_net3604886), .RN(n816), .Q(d_ff1_shift_region_flag_out[0]),
.QN(n608) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n524), .CK(reg_shift_y_net3604886), .RN(n816),
.Q(d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n534), .CK(reg_shift_y_net3604886), .RN(n816),
.Q(d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n528), .CK(reg_shift_y_net3604886), .RN(n815),
.Q(d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n536), .CK(reg_shift_y_net3604886), .RN(n815),
.Q(d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(data_out_LUT[4]), .CK(reg_shift_y_net3604886),
.RN(n815), .Q(d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n525), .CK(reg_shift_y_net3604886), .RN(n815),
.Q(d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n527), .CK(reg_shift_y_net3604886), .RN(n815),
.Q(d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n531), .CK(reg_shift_y_net3604886), .RN(n815),
.Q(d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n773), .CK(reg_shift_y_net3604886), .RN(n815),
.Q(d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n533), .CK(reg_shift_y_net3604886), .RN(n815),
.Q(d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n526), .CK(reg_shift_y_net3604886), .RN(n815), .Q(d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n532), .CK(reg_shift_y_net3604886), .RN(n815), .Q(d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n523), .CK(reg_shift_y_net3604886), .RN(n818), .Q(d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n535), .CK(reg_shift_y_net3604886), .RN(n817), .Q(d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n537), .CK(reg_shift_y_net3604886), .RN(n818), .Q(d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n522), .CK(reg_shift_y_net3604886), .RN(n817), .Q(d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n521), .CK(reg_shift_y_net3604886), .RN(n618), .Q(d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n520), .CK(reg_shift_y_net3604886), .RN(n154), .Q(d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(data_out_LUT[25]), .CK(
reg_shift_y_net3604886), .RN(n154), .Q(d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n529), .CK(reg_shift_y_net3604886), .RN(n154), .Q(d_ff3_LUT_out[26]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(data_in[0]), .CK(reg_Z0_net3604886), .RN(n154),
.Q(d_ff1_Z[0]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(data_in[1]), .CK(reg_Z0_net3604886), .RN(n154),
.Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(data_in[2]), .CK(reg_Z0_net3604886), .RN(n814),
.Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(data_in[3]), .CK(reg_Z0_net3604886), .RN(n814),
.Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(data_in[4]), .CK(reg_Z0_net3604886), .RN(n814),
.Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(data_in[5]), .CK(reg_Z0_net3604886), .RN(n814),
.Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(data_in[6]), .CK(reg_Z0_net3604886), .RN(n814),
.Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(data_in[7]), .CK(reg_Z0_net3604886), .RN(n814),
.Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(data_in[8]), .CK(reg_Z0_net3604886), .RN(n814),
.Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(data_in[9]), .CK(reg_Z0_net3604886), .RN(n814),
.Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(data_in[10]), .CK(reg_Z0_net3604886), .RN(
n814), .Q(d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(data_in[11]), .CK(reg_Z0_net3604886), .RN(
n814), .Q(d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(data_in[12]), .CK(reg_Z0_net3604886), .RN(
n813), .Q(d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(data_in[13]), .CK(reg_Z0_net3604886), .RN(
n813), .Q(d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(data_in[14]), .CK(reg_Z0_net3604886), .RN(
n813), .Q(d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(data_in[15]), .CK(reg_Z0_net3604886), .RN(
n813), .Q(d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(data_in[16]), .CK(reg_Z0_net3604886), .RN(
n813), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(data_in[17]), .CK(reg_Z0_net3604886), .RN(
n813), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(data_in[18]), .CK(reg_Z0_net3604886), .RN(
n813), .Q(d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(data_in[19]), .CK(reg_Z0_net3604886), .RN(
n813), .Q(d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(data_in[20]), .CK(reg_Z0_net3604886), .RN(
n813), .Q(d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(data_in[21]), .CK(reg_Z0_net3604886), .RN(
n813), .Q(d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(data_in[22]), .CK(reg_Z0_net3604886), .RN(
n812), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(data_in[23]), .CK(reg_Z0_net3604886), .RN(
n812), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(data_in[24]), .CK(reg_Z0_net3604886), .RN(
n812), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(data_in[25]), .CK(reg_Z0_net3604886), .RN(
n812), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(data_in[26]), .CK(reg_Z0_net3604886), .RN(
n812), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(data_in[27]), .CK(reg_Z0_net3604886), .RN(
n812), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(data_in[28]), .CK(reg_Z0_net3604886), .RN(
n812), .Q(d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(data_in[29]), .CK(reg_Z0_net3604886), .RN(
n812), .Q(d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(data_in[30]), .CK(reg_Z0_net3604886), .RN(
n812), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(data_in[31]), .CK(reg_Z0_net3604886), .RN(
n812), .Q(d_ff1_Z[31]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(sh_exp_x[0]), .CK(reg_shift_y_net3604886), .RN(n811), .Q(d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(sh_exp_x[1]), .CK(reg_shift_y_net3604886), .RN(n811), .Q(d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(sh_exp_x[2]), .CK(reg_shift_y_net3604886), .RN(n811), .Q(d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(sh_exp_x[3]), .CK(reg_shift_y_net3604886), .RN(n811), .Q(d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(sh_exp_x[4]), .CK(reg_shift_y_net3604886), .RN(n811), .Q(d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(sh_exp_x[5]), .CK(reg_shift_y_net3604886), .RN(n811), .Q(d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(sh_exp_x[6]), .CK(reg_shift_y_net3604886), .RN(n811), .Q(d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(sh_exp_x[7]), .CK(reg_shift_y_net3604886), .RN(n811), .Q(d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(sh_exp_y[0]), .CK(reg_shift_y_net3604886), .RN(n811), .Q(d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(sh_exp_y[1]), .CK(reg_shift_y_net3604886), .RN(n811), .Q(d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(sh_exp_y[2]), .CK(reg_shift_y_net3604886), .RN(n810), .Q(d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(sh_exp_y[3]), .CK(reg_shift_y_net3604886), .RN(n810), .Q(d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(sh_exp_y[4]), .CK(reg_shift_y_net3604886), .RN(n810), .Q(d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(sh_exp_y[5]), .CK(reg_shift_y_net3604886), .RN(n810), .Q(d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(sh_exp_y[6]), .CK(reg_shift_y_net3604886), .RN(n810), .Q(d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(sh_exp_y[7]), .CK(reg_shift_y_net3604886), .RN(n810), .Q(d_ff3_sh_y_out[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Xn_net3604886), .RN(n810), .Q(d_ff_Xn[0]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_0_ ( .D(first_mux_X[0]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n810), .Q(d_ff2_X[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(d_ff2_X[0]), .CK(reg_shift_y_net3604886),
.RN(n810), .Q(d_ff3_sh_x_out[0]) );
DFFRXLTS d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Xn_net3604886), .RN(n810), .Q(d_ff_Xn[1]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_1_ ( .D(first_mux_X[1]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n809), .Q(d_ff2_X[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(d_ff2_X[1]), .CK(reg_shift_y_net3604886),
.RN(n809), .Q(d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Xn_net3604886), .RN(n809), .Q(d_ff_Xn[2]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_2_ ( .D(first_mux_X[2]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n809), .Q(d_ff2_X[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(d_ff2_X[2]), .CK(reg_shift_y_net3604886),
.RN(n809), .Q(d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Xn_net3604886), .RN(n809), .Q(d_ff_Xn[3]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_3_ ( .D(first_mux_X[3]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n809), .Q(d_ff2_X[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(d_ff2_X[3]), .CK(reg_shift_y_net3604886),
.RN(n809), .Q(d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Xn_net3604886), .RN(n809), .Q(d_ff_Xn[4]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(first_mux_X[4]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n809), .Q(d_ff2_X[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(d_ff2_X[4]), .CK(reg_shift_y_net3604886),
.RN(n808), .Q(d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Xn_net3604886), .RN(n808), .Q(d_ff_Xn[5]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(first_mux_X[5]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n808), .Q(d_ff2_X[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(d_ff2_X[5]), .CK(reg_shift_y_net3604886),
.RN(n808), .Q(d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Xn_net3604886), .RN(n808), .Q(d_ff_Xn[6]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(first_mux_X[6]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n808), .Q(d_ff2_X[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(d_ff2_X[6]), .CK(reg_shift_y_net3604886),
.RN(n808), .Q(d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Xn_net3604886), .RN(n808), .Q(d_ff_Xn[7]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(first_mux_X[7]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n808), .Q(d_ff2_X[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(d_ff2_X[7]), .CK(reg_shift_y_net3604886),
.RN(n808), .Q(d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Xn_net3604886), .RN(n807), .Q(d_ff_Xn[8]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(first_mux_X[8]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n807), .Q(d_ff2_X[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(d_ff2_X[8]), .CK(reg_shift_y_net3604886),
.RN(n807), .Q(d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Xn_net3604886), .RN(n807), .Q(d_ff_Xn[9]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(first_mux_X[9]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n807), .Q(d_ff2_X[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(d_ff2_X[9]), .CK(reg_shift_y_net3604886),
.RN(n807), .Q(d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Xn_net3604886), .RN(n807), .Q(d_ff_Xn[10]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_10_ ( .D(first_mux_X[10]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n807), .Q(d_ff2_X[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(d_ff2_X[10]), .CK(reg_shift_y_net3604886), .RN(n807), .Q(d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Xn_net3604886), .RN(n807), .Q(d_ff_Xn[11]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_11_ ( .D(first_mux_X[11]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n806), .Q(d_ff2_X[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(d_ff2_X[11]), .CK(reg_shift_y_net3604886), .RN(n806), .Q(d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Xn_net3604886), .RN(n806), .Q(d_ff_Xn[12]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_12_ ( .D(first_mux_X[12]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n806), .Q(d_ff2_X[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(d_ff2_X[12]), .CK(reg_shift_y_net3604886), .RN(n806), .Q(d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Xn_net3604886), .RN(n806), .Q(d_ff_Xn[13]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_13_ ( .D(first_mux_X[13]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n806), .Q(d_ff2_X[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(d_ff2_X[13]), .CK(reg_shift_y_net3604886), .RN(n806), .Q(d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Xn_net3604886), .RN(n806), .Q(d_ff_Xn[14]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_14_ ( .D(first_mux_X[14]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n806), .Q(d_ff2_X[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(d_ff2_X[14]), .CK(reg_shift_y_net3604886), .RN(n805), .Q(d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Xn_net3604886), .RN(n805), .Q(d_ff_Xn[15]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_15_ ( .D(first_mux_X[15]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n805), .Q(d_ff2_X[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(d_ff2_X[15]), .CK(reg_shift_y_net3604886), .RN(n805), .Q(d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Xn_net3604886), .RN(n805), .Q(d_ff_Xn[16]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_16_ ( .D(first_mux_X[16]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n805), .Q(d_ff2_X[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(d_ff2_X[16]), .CK(reg_shift_y_net3604886), .RN(n805), .Q(d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Xn_net3604886), .RN(n805), .Q(d_ff_Xn[17]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_17_ ( .D(first_mux_X[17]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n805), .Q(d_ff2_X[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(d_ff2_X[17]), .CK(reg_shift_y_net3604886), .RN(n805), .Q(d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Xn_net3604886), .RN(n804), .Q(d_ff_Xn[18]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_18_ ( .D(first_mux_X[18]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n804), .Q(d_ff2_X[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(d_ff2_X[18]), .CK(reg_shift_y_net3604886), .RN(n804), .Q(d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Xn_net3604886), .RN(n804), .Q(d_ff_Xn[19]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_19_ ( .D(first_mux_X[19]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n804), .Q(d_ff2_X[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(d_ff2_X[19]), .CK(reg_shift_y_net3604886), .RN(n804), .Q(d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Xn_net3604886), .RN(n804), .Q(d_ff_Xn[20]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_20_ ( .D(first_mux_X[20]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n804), .Q(d_ff2_X[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(d_ff2_X[20]), .CK(reg_shift_y_net3604886), .RN(n804), .Q(d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Xn_net3604886), .RN(n804), .Q(d_ff_Xn[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_21_ ( .D(first_mux_X[21]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n803), .Q(d_ff2_X[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(d_ff2_X[21]), .CK(reg_shift_y_net3604886), .RN(n803), .Q(d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Xn_net3604886), .RN(n803), .Q(d_ff_Xn[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(first_mux_X[22]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n803), .Q(d_ff2_X[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(d_ff2_X[22]), .CK(reg_shift_y_net3604886), .RN(n803), .Q(d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Xn_net3604886), .RN(n803), .Q(d_ff_Xn[23]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(first_mux_X[23]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n803), .Q(d_ff2_X[23]), .QN(n777)
);
DFFRXLTS d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Xn_net3604886), .RN(n803), .Q(d_ff_Xn[24]) );
DFFRXLTS d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Xn_net3604886), .RN(n803), .Q(d_ff_Xn[25]) );
DFFRXLTS d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Xn_net3604886), .RN(n802), .Q(d_ff_Xn[26]) );
DFFRXLTS d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Xn_net3604886), .RN(n802), .Q(d_ff_Xn[27]) );
DFFRXLTS d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Xn_net3604886), .RN(n802), .Q(d_ff_Xn[28]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(first_mux_X[28]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n802), .Q(d_ff2_X[28]), .QN(n781)
);
DFFRXLTS d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Xn_net3604886), .RN(n802), .Q(d_ff_Xn[29]) );
DFFRXLTS d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Xn_net3604886), .RN(n802), .Q(d_ff_Xn[30]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(first_mux_X[30]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n801), .Q(d_ff2_X[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Xn_net3604886), .RN(n801), .Q(d_ff_Xn[31]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(first_mux_X[31]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n801), .Q(d_ff2_X[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(d_ff2_X[31]), .CK(reg_shift_y_net3604886), .RN(n801), .Q(d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Yn_net3604886), .RN(n801), .Q(d_ff_Yn[0]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(first_mux_Y[0]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n801), .Q(d_ff2_Y[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(d_ff2_Y[0]), .CK(reg_shift_y_net3604886),
.RN(n801), .Q(d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Yn_net3604886), .RN(n801), .Q(d_ff_Yn[1]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_1_ ( .D(first_mux_Y[1]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n801), .Q(d_ff2_Y[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(d_ff2_Y[1]), .CK(reg_shift_y_net3604886),
.RN(n800), .Q(d_ff3_sh_y_out[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Yn_net3604886), .RN(n800), .Q(d_ff_Yn[2]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_2_ ( .D(first_mux_Y[2]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n800), .Q(d_ff2_Y[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(d_ff2_Y[2]), .CK(reg_shift_y_net3604886),
.RN(n800), .Q(d_ff3_sh_y_out[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Yn_net3604886), .RN(n800), .Q(d_ff_Yn[3]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_3_ ( .D(first_mux_Y[3]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n800), .Q(d_ff2_Y[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(d_ff2_Y[3]), .CK(reg_shift_y_net3604886),
.RN(n800), .Q(d_ff3_sh_y_out[3]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Yn_net3604886), .RN(n799), .Q(d_ff_Yn[4]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_4_ ( .D(first_mux_Y[4]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n799), .Q(d_ff2_Y[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(d_ff2_Y[4]), .CK(reg_shift_y_net3604886),
.RN(n799), .Q(d_ff3_sh_y_out[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Yn_net3604886), .RN(n799), .Q(d_ff_Yn[5]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_5_ ( .D(first_mux_Y[5]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n799), .Q(d_ff2_Y[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(d_ff2_Y[5]), .CK(reg_shift_y_net3604886),
.RN(n799), .Q(d_ff3_sh_y_out[5]) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Yn_net3604886), .RN(n799), .Q(d_ff_Yn[6]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(first_mux_Y[6]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n799), .Q(d_ff2_Y[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(d_ff2_Y[6]), .CK(reg_shift_y_net3604886),
.RN(n798), .Q(d_ff3_sh_y_out[6]) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Yn_net3604886), .RN(n798), .Q(d_ff_Yn[7]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_7_ ( .D(first_mux_Y[7]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n798), .Q(d_ff2_Y[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(d_ff2_Y[7]), .CK(reg_shift_y_net3604886),
.RN(n798), .Q(d_ff3_sh_y_out[7]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Yn_net3604886), .RN(n798), .Q(d_ff_Yn[8]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(first_mux_Y[8]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n798), .Q(d_ff2_Y[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(d_ff2_Y[8]), .CK(reg_shift_y_net3604886),
.RN(n798), .Q(d_ff3_sh_y_out[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Yn_net3604886), .RN(n797), .Q(d_ff_Yn[9]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_9_ ( .D(first_mux_Y[9]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n797), .Q(d_ff2_Y[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(d_ff2_Y[9]), .CK(reg_shift_y_net3604886),
.RN(n797), .Q(d_ff3_sh_y_out[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Yn_net3604886), .RN(n797), .Q(d_ff_Yn[10]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_10_ ( .D(first_mux_Y[10]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n797), .Q(d_ff2_Y[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(d_ff2_Y[10]), .CK(reg_shift_y_net3604886), .RN(n797), .Q(d_ff3_sh_y_out[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Yn_net3604886), .RN(n797), .Q(d_ff_Yn[11]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_11_ ( .D(first_mux_Y[11]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n797), .Q(d_ff2_Y[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(d_ff2_Y[11]), .CK(reg_shift_y_net3604886), .RN(n796), .Q(d_ff3_sh_y_out[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Yn_net3604886), .RN(n796), .Q(d_ff_Yn[12]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_12_ ( .D(first_mux_Y[12]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n796), .Q(d_ff2_Y[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(d_ff2_Y[12]), .CK(reg_shift_y_net3604886), .RN(n796), .Q(d_ff3_sh_y_out[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Yn_net3604886), .RN(n796), .Q(d_ff_Yn[13]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_13_ ( .D(first_mux_Y[13]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n796), .Q(d_ff2_Y[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(d_ff2_Y[13]), .CK(reg_shift_y_net3604886), .RN(n796), .Q(d_ff3_sh_y_out[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Yn_net3604886), .RN(n795), .Q(d_ff_Yn[14]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_14_ ( .D(first_mux_Y[14]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n795), .Q(d_ff2_Y[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(d_ff2_Y[14]), .CK(reg_shift_y_net3604886), .RN(n795), .Q(d_ff3_sh_y_out[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Yn_net3604886), .RN(n795), .Q(d_ff_Yn[15]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_15_ ( .D(first_mux_Y[15]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n795), .Q(d_ff2_Y[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(d_ff2_Y[15]), .CK(reg_shift_y_net3604886), .RN(n795), .Q(d_ff3_sh_y_out[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Yn_net3604886), .RN(n795), .Q(d_ff_Yn[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_16_ ( .D(first_mux_Y[16]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n795), .Q(d_ff2_Y[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(d_ff2_Y[16]), .CK(reg_shift_y_net3604886), .RN(n794), .Q(d_ff3_sh_y_out[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Yn_net3604886), .RN(n794), .Q(d_ff_Yn[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(first_mux_Y[17]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n794), .Q(d_ff2_Y[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(d_ff2_Y[17]), .CK(reg_shift_y_net3604886), .RN(n794), .Q(d_ff3_sh_y_out[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Yn_net3604886), .RN(n794), .Q(d_ff_Yn[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(first_mux_Y[18]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n794), .Q(d_ff2_Y[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(d_ff2_Y[18]), .CK(reg_shift_y_net3604886), .RN(n794), .Q(d_ff3_sh_y_out[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Yn_net3604886), .RN(n793), .Q(d_ff_Yn[19]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(first_mux_Y[19]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n793), .Q(d_ff2_Y[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(d_ff2_Y[19]), .CK(reg_shift_y_net3604886), .RN(n793), .Q(d_ff3_sh_y_out[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Yn_net3604886), .RN(n793), .Q(d_ff_Yn[20]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_20_ ( .D(first_mux_Y[20]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n793), .Q(d_ff2_Y[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(d_ff2_Y[20]), .CK(reg_shift_y_net3604886), .RN(n793), .Q(d_ff3_sh_y_out[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Yn_net3604886), .RN(n793), .Q(d_ff_Yn[21]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_21_ ( .D(first_mux_Y[21]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n793), .Q(d_ff2_Y[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(d_ff2_Y[21]), .CK(reg_shift_y_net3604886), .RN(n792), .Q(d_ff3_sh_y_out[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Yn_net3604886), .RN(n792), .Q(d_ff_Yn[22]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_22_ ( .D(first_mux_Y[22]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n792), .Q(d_ff2_Y[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(d_ff2_Y[22]), .CK(reg_shift_y_net3604886), .RN(n792), .Q(d_ff3_sh_y_out[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Yn_net3604886), .RN(n792), .Q(d_ff_Yn[23]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_23_ ( .D(first_mux_Y[23]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n792), .Q(d_ff2_Y[23]), .QN(n778)
);
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Yn_net3604886), .RN(n792), .Q(d_ff_Yn[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Yn_net3604886), .RN(n791), .Q(d_ff_Yn[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Yn_net3604886), .RN(n791), .Q(d_ff_Yn[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Yn_net3604886), .RN(n791), .Q(d_ff_Yn[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Yn_net3604886), .RN(n790), .Q(d_ff_Yn[28]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_28_ ( .D(first_mux_Y[28]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n790), .Q(d_ff2_Y[28]), .QN(n782)
);
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Yn_net3604886), .RN(n790), .Q(d_ff_Yn[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Yn_net3604886), .RN(n790), .Q(d_ff_Yn[30]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_30_ ( .D(first_mux_Y[30]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n790), .Q(d_ff2_Y[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Yn_net3604886), .RN(n789), .Q(d_ff_Yn[31]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_31_ ( .D(first_mux_Y[31]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n789), .Q(d_ff2_Y[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(d_ff2_Y[31]), .CK(reg_shift_y_net3604886), .RN(n789), .Q(d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Zn_net3604886), .RN(n789), .Q(d_ff_Zn[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(first_mux_Z[0]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n789), .Q(d_ff2_Z[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Zn_net3604886), .RN(n789), .Q(d_ff_Zn[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(first_mux_Z[1]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n789), .Q(d_ff2_Z[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Zn_net3604886), .RN(n789), .Q(d_ff_Zn[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(first_mux_Z[2]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n789), .Q(d_ff2_Z[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Zn_net3604886), .RN(n788), .Q(d_ff_Zn[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(first_mux_Z[3]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n788), .Q(d_ff2_Z[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Zn_net3604886), .RN(n788), .Q(d_ff_Zn[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(first_mux_Z[4]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n788), .Q(d_ff2_Z[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Zn_net3604886), .RN(n788), .Q(d_ff_Zn[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(first_mux_Z[5]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n788), .Q(d_ff2_Z[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Zn_net3604886), .RN(n788), .Q(d_ff_Zn[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(first_mux_Z[6]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n788), .Q(d_ff2_Z[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Zn_net3604886), .RN(n788), .Q(d_ff_Zn[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(first_mux_Z[7]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n788), .Q(d_ff2_Z[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Zn_net3604886), .RN(n787), .Q(d_ff_Zn[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(first_mux_Z[8]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n787), .Q(d_ff2_Z[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Zn_net3604886), .RN(n787), .Q(d_ff_Zn[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(first_mux_Z[9]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n787), .Q(d_ff2_Z[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Zn_net3604886), .RN(n787), .Q(d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(first_mux_Z[10]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n787), .Q(d_ff2_Z[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Zn_net3604886), .RN(n787), .Q(d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(first_mux_Z[11]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n787), .Q(d_ff2_Z[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Zn_net3604886), .RN(n787), .Q(d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(first_mux_Z[12]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n787), .Q(d_ff2_Z[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Zn_net3604886), .RN(n786), .Q(d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(first_mux_Z[13]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n786), .Q(d_ff2_Z[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Zn_net3604886), .RN(n786), .Q(d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(first_mux_Z[14]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n786), .Q(d_ff2_Z[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Zn_net3604886), .RN(n786), .Q(d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(first_mux_Z[15]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n786), .Q(d_ff2_Z[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Zn_net3604886), .RN(n786), .Q(d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(first_mux_Z[16]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n786), .Q(d_ff2_Z[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Zn_net3604886), .RN(n786), .Q(d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(first_mux_Z[17]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n786), .Q(d_ff2_Z[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Zn_net3604886), .RN(n785), .Q(d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(first_mux_Z[18]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n785), .Q(d_ff2_Z[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Zn_net3604886), .RN(n785), .Q(d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(first_mux_Z[19]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n785), .Q(d_ff2_Z[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Zn_net3604886), .RN(n785), .Q(d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(first_mux_Z[20]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n785), .Q(d_ff2_Z[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Zn_net3604886), .RN(n785), .Q(d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(first_mux_Z[21]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n785), .Q(d_ff2_Z[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Zn_net3604886), .RN(n785), .Q(d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(first_mux_Z[22]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n785), .Q(d_ff2_Z[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Zn_net3604886), .RN(n784), .Q(d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(first_mux_Z[23]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n784), .Q(d_ff2_Z[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Zn_net3604886), .RN(n784), .Q(d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(first_mux_Z[24]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n784), .Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Zn_net3604886), .RN(n784), .Q(d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(first_mux_Z[25]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n784), .Q(d_ff2_Z[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Zn_net3604886), .RN(n784), .Q(d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(first_mux_Z[26]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n784), .Q(d_ff2_Z[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Zn_net3604886), .RN(n784), .Q(d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(first_mux_Z[27]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n784), .Q(d_ff2_Z[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Zn_net3604886), .RN(n783), .Q(d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(first_mux_Z[28]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n783), .Q(d_ff2_Z[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Zn_net3604886), .RN(n783), .Q(d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(first_mux_Z[29]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n783), .Q(d_ff2_Z[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Zn_net3604886), .RN(n783), .Q(d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(first_mux_Z[30]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n783), .Q(d_ff2_Z[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Zn_net3604886), .RN(n783), .Q(d_ff_Zn[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(first_mux_Z[31]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n783), .Q(d_ff2_Z[31]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(reg_shift_y_net3604886), .RN(n783), .Q(d_ff3_LUT_out[27]) );
DFFRX1TS VAR_CONT_temp_reg_1_ ( .D(n519), .CK(clk), .RN(n817), .Q(
cont_var_out[1]), .QN(n780) );
DFFRX2TS VAR_CONT_temp_reg_0_ ( .D(n518), .CK(clk), .RN(n818), .Q(
cont_var_out[0]), .QN(n779) );
DFFRX2TS ITER_CONT_temp_reg_0_ ( .D(n775), .CK(ITER_CONT_net3604909), .RN(
n818), .Q(cont_iter_out[0]), .QN(n775) );
DFFRX2TS ITER_CONT_temp_reg_3_ ( .D(ITER_CONT_N5), .CK(ITER_CONT_net3604909),
.RN(n817), .Q(cont_iter_out[3]), .QN(n774) );
DFFRX2TS ITER_CONT_temp_reg_2_ ( .D(ITER_CONT_N4), .CK(ITER_CONT_net3604909),
.RN(n818), .Q(cont_iter_out[2]), .QN(n773) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(mux_sal[0]), .CK(
d_ff5_data_out_net3604886), .RN(n801), .Q(data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(mux_sal[1]), .CK(
d_ff5_data_out_net3604886), .RN(n800), .Q(data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(mux_sal[2]), .CK(
d_ff5_data_out_net3604886), .RN(n800), .Q(data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(mux_sal[3]), .CK(
d_ff5_data_out_net3604886), .RN(n800), .Q(data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(mux_sal[4]), .CK(
d_ff5_data_out_net3604886), .RN(n799), .Q(data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(mux_sal[5]), .CK(
d_ff5_data_out_net3604886), .RN(n799), .Q(data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(mux_sal[6]), .CK(
d_ff5_data_out_net3604886), .RN(n798), .Q(data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(mux_sal[7]), .CK(
d_ff5_data_out_net3604886), .RN(n798), .Q(data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(mux_sal[8]), .CK(
d_ff5_data_out_net3604886), .RN(n798), .Q(data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(mux_sal[9]), .CK(
d_ff5_data_out_net3604886), .RN(n797), .Q(data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(mux_sal[10]), .CK(
d_ff5_data_out_net3604886), .RN(n797), .Q(data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(mux_sal[11]), .CK(
d_ff5_data_out_net3604886), .RN(n796), .Q(data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(mux_sal[12]), .CK(
d_ff5_data_out_net3604886), .RN(n796), .Q(data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(mux_sal[13]), .CK(
d_ff5_data_out_net3604886), .RN(n796), .Q(data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(mux_sal[14]), .CK(
d_ff5_data_out_net3604886), .RN(n795), .Q(data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(mux_sal[15]), .CK(
d_ff5_data_out_net3604886), .RN(n795), .Q(data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(mux_sal[16]), .CK(
d_ff5_data_out_net3604886), .RN(n794), .Q(data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(mux_sal[17]), .CK(
d_ff5_data_out_net3604886), .RN(n794), .Q(data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(mux_sal[18]), .CK(
d_ff5_data_out_net3604886), .RN(n794), .Q(data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(mux_sal[19]), .CK(
d_ff5_data_out_net3604886), .RN(n793), .Q(data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(mux_sal[20]), .CK(
d_ff5_data_out_net3604886), .RN(n793), .Q(data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(mux_sal[21]), .CK(
d_ff5_data_out_net3604886), .RN(n792), .Q(data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(mux_sal[22]), .CK(
d_ff5_data_out_net3604886), .RN(n792), .Q(data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(mux_sal[23]), .CK(
d_ff5_data_out_net3604886), .RN(n792), .Q(data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(mux_sal[24]), .CK(
d_ff5_data_out_net3604886), .RN(n791), .Q(data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(mux_sal[25]), .CK(
d_ff5_data_out_net3604886), .RN(n791), .Q(data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(mux_sal[26]), .CK(
d_ff5_data_out_net3604886), .RN(n791), .Q(data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(mux_sal[27]), .CK(
d_ff5_data_out_net3604886), .RN(n790), .Q(data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(mux_sal[28]), .CK(
d_ff5_data_out_net3604886), .RN(n790), .Q(data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(mux_sal[29]), .CK(
d_ff5_data_out_net3604886), .RN(n790), .Q(data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(mux_sal[30]), .CK(
d_ff5_data_out_net3604886), .RN(n790), .Q(data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(fmtted_Result_31_), .CK(
d_ff5_data_out_net3604886), .RN(n789), .Q(data_output[31]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n816), .Q(
inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n617), .Q(
inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n154), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n816), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n816), .Q(
inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(d_ff2_Z[31]), .CK(reg_shift_y_net3604886),
.RN(n783), .Q(d_ff3_sign_out) );
DFFSX1TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n818), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(first_mux_X[27]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n802), .Q(d_ff2_X[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(first_mux_Y[27]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n791), .Q(d_ff2_Y[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(first_mux_X[29]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n802), .Q(d_ff2_X[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(first_mux_Y[29]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n790), .Q(d_ff2_Y[29]) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(operation), .CK(reg_Z0_net3604886),
.RN(n816), .Q(d_ff1_operation_out) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(first_mux_X[24]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n803), .Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(first_mux_X[26]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n802), .Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(first_mux_X[25]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n802), .Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(first_mux_Y[26]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n791), .Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(first_mux_Y[25]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n791), .Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(first_mux_Y[24]), .CK(
reg_val_muxZ_2stage_net3604886), .RN(n791), .Q(d_ff2_Y[24]) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(shift_region_flag[1]), .CK(
reg_Z0_net3604886), .RN(n816), .Q(d_ff1_shift_region_flag_out[1]) );
DFFRX2TS ITER_CONT_temp_reg_1_ ( .D(ITER_CONT_N3), .CK(ITER_CONT_net3604909),
.RN(n817), .Q(cont_iter_out[1]), .QN(n776) );
ADDFX1TS intadd_420_U4 ( .A(d_ff2_Y[24]), .B(n606), .CI(intadd_420_CI), .CO(
intadd_420_n3), .S(sh_exp_y[1]) );
ADDFX1TS intadd_419_U4 ( .A(n606), .B(d_ff2_X[24]), .CI(intadd_419_CI), .CO(
intadd_419_n3), .S(sh_exp_x[1]) );
ADDFX1TS intadd_419_U3 ( .A(d_ff2_X[25]), .B(n773), .CI(intadd_419_n3), .CO(
intadd_419_n2), .S(sh_exp_x[2]) );
ADDFX1TS intadd_420_U3 ( .A(d_ff2_Y[25]), .B(n773), .CI(intadd_420_n3), .CO(
intadd_420_n2), .S(sh_exp_y[2]) );
ADDFX1TS intadd_420_U2 ( .A(d_ff2_Y[26]), .B(n774), .CI(intadd_420_n2), .CO(
intadd_420_n1), .S(sh_exp_y[3]) );
ADDFX1TS intadd_419_U2 ( .A(d_ff2_X[26]), .B(n774), .CI(intadd_419_n2), .CO(
intadd_419_n1), .S(sh_exp_x[3]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n816), .Q(
inst_CORDIC_FSM_v3_state_reg[2]) );
AOI222X1TS U407 ( .A0(n689), .A1(d_ff3_sh_y_out[12]), .B0(n666), .B1(
d_ff3_sh_x_out[12]), .C0(n758), .C1(d_ff3_LUT_out[12]), .Y(n668) );
AOI222X1TS U408 ( .A0(n667), .A1(d_ff3_sh_y_out[23]), .B0(n666), .B1(
d_ff3_sh_x_out[23]), .C0(n758), .C1(d_ff3_LUT_out[23]), .Y(n665) );
AOI222X1TS U409 ( .A0(n732), .A1(d_ff3_sh_y_out[10]), .B0(n666), .B1(
d_ff3_sh_x_out[10]), .C0(n758), .C1(d_ff3_LUT_out[10]), .Y(n664) );
AOI222X1TS U410 ( .A0(n693), .A1(d_ff3_sh_y_out[9]), .B0(n666), .B1(
d_ff3_sh_x_out[9]), .C0(n758), .C1(d_ff3_LUT_out[9]), .Y(n663) );
AOI222X1TS U411 ( .A0(n689), .A1(d_ff3_sh_y_out[8]), .B0(n666), .B1(
d_ff3_sh_x_out[8]), .C0(n758), .C1(d_ff3_LUT_out[8]), .Y(n662) );
AOI222X1TS U412 ( .A0(n667), .A1(d_ff3_sh_y_out[6]), .B0(n666), .B1(
d_ff3_sh_x_out[6]), .C0(n758), .C1(d_ff3_LUT_out[6]), .Y(n660) );
AOI222X1TS U413 ( .A0(n732), .A1(d_ff3_sh_y_out[21]), .B0(n666), .B1(
d_ff3_sh_x_out[21]), .C0(n758), .C1(d_ff3_LUT_out[21]), .Y(n659) );
AOI222X1TS U414 ( .A0(n667), .A1(d_ff3_sh_y_out[24]), .B0(n666), .B1(
d_ff3_sh_x_out[24]), .C0(n758), .C1(d_ff3_LUT_out[24]), .Y(n655) );
AOI222X1TS U415 ( .A0(n693), .A1(d_ff2_X[30]), .B0(n688), .B1(d_ff2_Y[30]),
.C0(n691), .C1(d_ff2_Z[30]), .Y(n687) );
AOI222X1TS U416 ( .A0(n693), .A1(d_ff3_sh_y_out[4]), .B0(n666), .B1(
d_ff3_sh_x_out[4]), .C0(n691), .C1(d_ff3_LUT_out[4]), .Y(n658) );
AOI222X1TS U417 ( .A0(n689), .A1(d_ff3_sh_y_out[2]), .B0(n666), .B1(
d_ff3_sh_x_out[2]), .C0(n691), .C1(d_ff3_LUT_out[2]), .Y(n656) );
OAI21XLTS U418 ( .A0(d_ff1_operation_out), .A1(
d_ff1_shift_region_flag_out[1]), .B0(n702), .Y(n700) );
INVX2TS U419 ( .A(n714), .Y(n712) );
INVX2TS U420 ( .A(n714), .Y(n724) );
INVX3TS U421 ( .A(n709), .Y(n707) );
INVX2TS U422 ( .A(n714), .Y(n710) );
CLKBUFX3TS U423 ( .A(n714), .Y(n711) );
CLKBUFX3TS U424 ( .A(n714), .Y(n713) );
INVX2TS U425 ( .A(n714), .Y(n706) );
INVX3TS U426 ( .A(n709), .Y(n705) );
CLKBUFX3TS U427 ( .A(n721), .Y(n719) );
CLKBUFX3TS U428 ( .A(n721), .Y(n718) );
CLKBUFX3TS U429 ( .A(n721), .Y(n716) );
NAND3X1TS U430 ( .A(enab_cont_iter), .B(n759), .C(n730), .Y(n646) );
CLKBUFX3TS U431 ( .A(n626), .Y(n709) );
AOI222X1TS U432 ( .A0(n689), .A1(d_ff2_X[27]), .B0(n731), .B1(d_ff2_Y[27]),
.C0(n691), .C1(d_ff2_Z[27]), .Y(n686) );
AOI222X1TS U433 ( .A0(n667), .A1(d_ff2_X[29]), .B0(n688), .B1(d_ff2_Y[29]),
.C0(n691), .C1(d_ff2_Z[29]), .Y(n657) );
AOI222X1TS U434 ( .A0(n667), .A1(d_ff2_X[25]), .B0(n731), .B1(d_ff2_Y[25]),
.C0(n683), .C1(d_ff2_Z[25]), .Y(n684) );
CLKBUFX3TS U435 ( .A(n739), .Y(n672) );
CLKBUFX3TS U436 ( .A(n754), .Y(n758) );
OR2X2TS U437 ( .A(cont_iter_out[2]), .B(n699), .Y(n626) );
CLKBUFX3TS U438 ( .A(n676), .Y(n691) );
NAND3BX1TS U439 ( .AN(inst_CORDIC_FSM_v3_state_reg[6]), .B(n620), .C(
inst_CORDIC_FSM_v3_state_reg[4]), .Y(n727) );
NAND2BX1TS U440 ( .AN(inst_CORDIC_FSM_v3_state_reg[3]), .B(n624), .Y(n613)
);
NAND4BXLTS U441 ( .AN(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[3]), .C(n625), .D(n624), .Y(n647) );
CLKBUFX3TS U442 ( .A(n683), .Y(n754) );
CLKBUFX3TS U443 ( .A(n683), .Y(n739) );
INVX3TS U444 ( .A(n733), .Y(n644) );
INVX3TS U445 ( .A(n726), .Y(n683) );
OR2X2TS U446 ( .A(n779), .B(cont_var_out[1]), .Y(n733) );
OR2X4TS U447 ( .A(n780), .B(cont_var_out[0]), .Y(n697) );
NAND3XLTS U448 ( .A(n727), .B(n695), .C(n698), .Y(n765) );
NAND3BXLTS U449 ( .AN(n613), .B(inst_CORDIC_FSM_v3_state_reg[1]), .C(n625),
.Y(n622) );
AOI222X1TS U450 ( .A0(n732), .A1(d_ff2_X[24]), .B0(n755), .B1(d_ff2_Y[24]),
.C0(n683), .C1(d_ff2_Z[24]), .Y(n682) );
AOI222X1TS U451 ( .A0(n693), .A1(d_ff2_X[26]), .B0(n750), .B1(d_ff2_Y[26]),
.C0(n683), .C1(d_ff2_Z[26]), .Y(n678) );
NOR2XLTS U452 ( .A(n698), .B(n733), .Y(enab_d_ff4_Yn) );
NOR2XLTS U453 ( .A(n730), .B(n621), .Y(ITER_CONT_N3) );
OR2X1TS U454 ( .A(d_ff_Xn[25]), .B(n627), .Y(first_mux_X[25]) );
OR2X1TS U455 ( .A(d_ff_Xn[26]), .B(n628), .Y(first_mux_X[26]) );
OR2X1TS U456 ( .A(d_ff_Xn[24]), .B(n628), .Y(first_mux_X[24]) );
OR2X1TS U457 ( .A(d_ff_Xn[29]), .B(n628), .Y(first_mux_X[29]) );
OR2X1TS U458 ( .A(d_ff_Xn[27]), .B(n708), .Y(first_mux_X[27]) );
AO22XLTS U459 ( .A0(n722), .A1(d_ff_Yn[30]), .B0(n721), .B1(d_ff_Xn[30]),
.Y(mux_sal[30]) );
AO22XLTS U460 ( .A0(n722), .A1(d_ff_Yn[29]), .B0(n721), .B1(d_ff_Xn[29]),
.Y(mux_sal[29]) );
AO22XLTS U461 ( .A0(n720), .A1(d_ff_Yn[28]), .B0(n721), .B1(d_ff_Xn[28]),
.Y(mux_sal[28]) );
AO22XLTS U462 ( .A0(n720), .A1(d_ff_Yn[27]), .B0(n721), .B1(d_ff_Xn[27]),
.Y(mux_sal[27]) );
AO22XLTS U463 ( .A0(n720), .A1(d_ff_Yn[26]), .B0(n721), .B1(d_ff_Xn[26]),
.Y(mux_sal[26]) );
AO22XLTS U464 ( .A0(n720), .A1(d_ff_Yn[25]), .B0(n721), .B1(d_ff_Xn[25]),
.Y(mux_sal[25]) );
AO22XLTS U465 ( .A0(n720), .A1(d_ff_Yn[24]), .B0(n719), .B1(d_ff_Xn[24]),
.Y(mux_sal[24]) );
AO22XLTS U466 ( .A0(n720), .A1(d_ff_Yn[23]), .B0(n718), .B1(d_ff_Xn[23]),
.Y(mux_sal[23]) );
AO22XLTS U467 ( .A0(n720), .A1(d_ff_Yn[22]), .B0(n718), .B1(d_ff_Xn[22]),
.Y(mux_sal[22]) );
AO22XLTS U468 ( .A0(n720), .A1(d_ff_Yn[21]), .B0(n719), .B1(d_ff_Xn[21]),
.Y(mux_sal[21]) );
AO22XLTS U469 ( .A0(n720), .A1(d_ff_Yn[20]), .B0(n721), .B1(d_ff_Xn[20]),
.Y(mux_sal[20]) );
AO22XLTS U470 ( .A0(n720), .A1(d_ff_Yn[19]), .B0(n718), .B1(d_ff_Xn[19]),
.Y(mux_sal[19]) );
AO22XLTS U471 ( .A0(n717), .A1(d_ff_Yn[18]), .B0(n718), .B1(d_ff_Xn[18]),
.Y(mux_sal[18]) );
AO22XLTS U472 ( .A0(n717), .A1(d_ff_Yn[17]), .B0(n718), .B1(d_ff_Xn[17]),
.Y(mux_sal[17]) );
AO22XLTS U473 ( .A0(n717), .A1(d_ff_Yn[16]), .B0(n716), .B1(d_ff_Xn[16]),
.Y(mux_sal[16]) );
AO22XLTS U474 ( .A0(n717), .A1(d_ff_Yn[15]), .B0(n716), .B1(d_ff_Xn[15]),
.Y(mux_sal[15]) );
AO22XLTS U475 ( .A0(n717), .A1(d_ff_Yn[14]), .B0(n716), .B1(d_ff_Xn[14]),
.Y(mux_sal[14]) );
AO22XLTS U476 ( .A0(n717), .A1(d_ff_Yn[13]), .B0(n716), .B1(d_ff_Xn[13]),
.Y(mux_sal[13]) );
AO22XLTS U477 ( .A0(n717), .A1(d_ff_Yn[12]), .B0(n716), .B1(d_ff_Xn[12]),
.Y(mux_sal[12]) );
AO22XLTS U478 ( .A0(n717), .A1(d_ff_Yn[11]), .B0(n716), .B1(d_ff_Xn[11]),
.Y(mux_sal[11]) );
AO22XLTS U479 ( .A0(n717), .A1(d_ff_Yn[10]), .B0(n716), .B1(d_ff_Xn[10]),
.Y(mux_sal[10]) );
AO22XLTS U480 ( .A0(n717), .A1(d_ff_Yn[9]), .B0(n716), .B1(d_ff_Xn[9]), .Y(
mux_sal[9]) );
AO22XLTS U481 ( .A0(n715), .A1(d_ff_Yn[8]), .B0(n716), .B1(d_ff_Xn[8]), .Y(
mux_sal[8]) );
AO22XLTS U482 ( .A0(n715), .A1(d_ff_Yn[7]), .B0(n716), .B1(d_ff_Xn[7]), .Y(
mux_sal[7]) );
AO22XLTS U483 ( .A0(n715), .A1(d_ff_Yn[6]), .B0(n719), .B1(d_ff_Xn[6]), .Y(
mux_sal[6]) );
AO22XLTS U484 ( .A0(n715), .A1(d_ff_Yn[5]), .B0(n719), .B1(d_ff_Xn[5]), .Y(
mux_sal[5]) );
AO22XLTS U485 ( .A0(n715), .A1(d_ff_Yn[4]), .B0(n719), .B1(d_ff_Xn[4]), .Y(
mux_sal[4]) );
AO22XLTS U486 ( .A0(n715), .A1(d_ff_Yn[3]), .B0(n719), .B1(d_ff_Xn[3]), .Y(
mux_sal[3]) );
AO22XLTS U487 ( .A0(n715), .A1(d_ff_Yn[2]), .B0(n719), .B1(d_ff_Xn[2]), .Y(
mux_sal[2]) );
AO22XLTS U488 ( .A0(n715), .A1(d_ff_Yn[1]), .B0(n719), .B1(d_ff_Xn[1]), .Y(
mux_sal[1]) );
AO22XLTS U489 ( .A0(n715), .A1(d_ff_Yn[0]), .B0(n718), .B1(d_ff_Xn[0]), .Y(
mux_sal[0]) );
NOR2XLTS U490 ( .A(n623), .B(n529), .Y(ITER_CONT_N5) );
OAI211XLTS U491 ( .A0(n766), .A1(n733), .B0(n697), .C0(n696), .Y(n519) );
AO22XLTS U492 ( .A0(n723), .A1(d_ff1_Z[31]), .B0(n714), .B1(d_ff_Zn[31]),
.Y(first_mux_Z[31]) );
AO22XLTS U493 ( .A0(n723), .A1(d_ff1_Z[30]), .B0(n714), .B1(d_ff_Zn[30]),
.Y(first_mux_Z[30]) );
AO22XLTS U494 ( .A0(n723), .A1(d_ff1_Z[29]), .B0(n713), .B1(d_ff_Zn[29]),
.Y(first_mux_Z[29]) );
AO22XLTS U495 ( .A0(n723), .A1(d_ff1_Z[28]), .B0(n713), .B1(d_ff_Zn[28]),
.Y(first_mux_Z[28]) );
AO22XLTS U496 ( .A0(n723), .A1(d_ff1_Z[27]), .B0(n713), .B1(d_ff_Zn[27]),
.Y(first_mux_Z[27]) );
AO22XLTS U497 ( .A0(n710), .A1(d_ff1_Z[26]), .B0(n713), .B1(d_ff_Zn[26]),
.Y(first_mux_Z[26]) );
AO22XLTS U498 ( .A0(n712), .A1(d_ff1_Z[25]), .B0(n713), .B1(d_ff_Zn[25]),
.Y(first_mux_Z[25]) );
AO22XLTS U499 ( .A0(n724), .A1(d_ff1_Z[24]), .B0(n713), .B1(d_ff_Zn[24]),
.Y(first_mux_Z[24]) );
AO22XLTS U500 ( .A0(n710), .A1(d_ff1_Z[23]), .B0(n713), .B1(d_ff_Zn[23]),
.Y(first_mux_Z[23]) );
AO22XLTS U501 ( .A0(n712), .A1(d_ff1_Z[22]), .B0(n713), .B1(d_ff_Zn[22]),
.Y(first_mux_Z[22]) );
AO22XLTS U502 ( .A0(n706), .A1(d_ff1_Z[21]), .B0(n713), .B1(d_ff_Zn[21]),
.Y(first_mux_Z[21]) );
AO22XLTS U503 ( .A0(n723), .A1(d_ff1_Z[20]), .B0(n713), .B1(d_ff_Zn[20]),
.Y(first_mux_Z[20]) );
AO22XLTS U504 ( .A0(n723), .A1(d_ff1_Z[19]), .B0(n711), .B1(d_ff_Zn[19]),
.Y(first_mux_Z[19]) );
AO22XLTS U505 ( .A0(n723), .A1(d_ff1_Z[18]), .B0(n711), .B1(d_ff_Zn[18]),
.Y(first_mux_Z[18]) );
AO22XLTS U506 ( .A0(n724), .A1(d_ff1_Z[17]), .B0(n711), .B1(d_ff_Zn[17]),
.Y(first_mux_Z[17]) );
AO22XLTS U507 ( .A0(n710), .A1(d_ff1_Z[16]), .B0(n711), .B1(d_ff_Zn[16]),
.Y(first_mux_Z[16]) );
AO22XLTS U508 ( .A0(n723), .A1(d_ff1_Z[15]), .B0(n711), .B1(d_ff_Zn[15]),
.Y(first_mux_Z[15]) );
AO22XLTS U509 ( .A0(n712), .A1(d_ff1_Z[14]), .B0(n711), .B1(d_ff_Zn[14]),
.Y(first_mux_Z[14]) );
AO22XLTS U510 ( .A0(n706), .A1(d_ff1_Z[13]), .B0(n711), .B1(d_ff_Zn[13]),
.Y(first_mux_Z[13]) );
AO22XLTS U511 ( .A0(n724), .A1(d_ff1_Z[12]), .B0(n711), .B1(d_ff_Zn[12]),
.Y(first_mux_Z[12]) );
AO22XLTS U512 ( .A0(n706), .A1(d_ff1_Z[11]), .B0(n711), .B1(d_ff_Zn[11]),
.Y(first_mux_Z[11]) );
AO22XLTS U513 ( .A0(n710), .A1(d_ff1_Z[10]), .B0(n711), .B1(d_ff_Zn[10]),
.Y(first_mux_Z[10]) );
AO22XLTS U514 ( .A0(n712), .A1(d_ff1_Z[9]), .B0(n709), .B1(d_ff_Zn[9]), .Y(
first_mux_Z[9]) );
AO22XLTS U515 ( .A0(n627), .A1(d_ff1_Z[8]), .B0(n709), .B1(d_ff_Zn[8]), .Y(
first_mux_Z[8]) );
AO22XLTS U516 ( .A0(n724), .A1(d_ff1_Z[7]), .B0(n709), .B1(d_ff_Zn[7]), .Y(
first_mux_Z[7]) );
AO22XLTS U517 ( .A0(n708), .A1(d_ff1_Z[6]), .B0(n709), .B1(d_ff_Zn[6]), .Y(
first_mux_Z[6]) );
AO22XLTS U518 ( .A0(n628), .A1(d_ff1_Z[5]), .B0(n709), .B1(d_ff_Zn[5]), .Y(
first_mux_Z[5]) );
AO22XLTS U519 ( .A0(n627), .A1(d_ff1_Z[4]), .B0(n709), .B1(d_ff_Zn[4]), .Y(
first_mux_Z[4]) );
AO22XLTS U520 ( .A0(n708), .A1(d_ff1_Z[3]), .B0(n709), .B1(d_ff_Zn[3]), .Y(
first_mux_Z[3]) );
AO22XLTS U521 ( .A0(n628), .A1(d_ff1_Z[2]), .B0(n626), .B1(d_ff_Zn[2]), .Y(
first_mux_Z[2]) );
AO22XLTS U522 ( .A0(n706), .A1(d_ff1_Z[1]), .B0(n714), .B1(d_ff_Zn[1]), .Y(
first_mux_Z[1]) );
AO22XLTS U523 ( .A0(n723), .A1(d_ff1_Z[0]), .B0(n626), .B1(d_ff_Zn[0]), .Y(
first_mux_Z[0]) );
OR2X1TS U524 ( .A(d_ff_Xn[20]), .B(n628), .Y(first_mux_X[20]) );
OR2X1TS U525 ( .A(d_ff_Xn[19]), .B(n628), .Y(first_mux_X[19]) );
OR2X1TS U526 ( .A(d_ff_Xn[17]), .B(n708), .Y(first_mux_X[17]) );
OR2X1TS U527 ( .A(d_ff_Xn[16]), .B(n627), .Y(first_mux_X[16]) );
OR2X1TS U528 ( .A(d_ff_Xn[14]), .B(n627), .Y(first_mux_X[14]) );
OR2X1TS U529 ( .A(d_ff_Xn[13]), .B(n708), .Y(first_mux_X[13]) );
OR2X1TS U530 ( .A(d_ff_Xn[12]), .B(n628), .Y(first_mux_X[12]) );
OR2X1TS U531 ( .A(d_ff_Xn[10]), .B(n708), .Y(first_mux_X[10]) );
OR2X1TS U532 ( .A(d_ff_Xn[7]), .B(n627), .Y(first_mux_X[7]) );
OR2X1TS U533 ( .A(d_ff_Xn[6]), .B(n628), .Y(first_mux_X[6]) );
OR2X1TS U534 ( .A(d_ff_Xn[5]), .B(n627), .Y(first_mux_X[5]) );
OR2X1TS U535 ( .A(d_ff_Xn[3]), .B(n708), .Y(first_mux_X[3]) );
OR2X1TS U536 ( .A(d_ff_Xn[2]), .B(n708), .Y(first_mux_X[2]) );
OR2X1TS U537 ( .A(d_ff_Xn[1]), .B(n708), .Y(first_mux_X[1]) );
XOR2XLTS U538 ( .A(d_ff2_Y[30]), .B(n767), .Y(sh_exp_y[7]) );
OAI21XLTS U539 ( .A0(n769), .A1(n782), .B0(n768), .Y(sh_exp_y[5]) );
AO21XLTS U540 ( .A0(intadd_420_n1), .A1(d_ff2_Y[27]), .B0(n769), .Y(
sh_exp_y[4]) );
OAI21XLTS U541 ( .A0(cont_iter_out[0]), .A1(n778), .B0(intadd_420_CI), .Y(
sh_exp_y[0]) );
XOR2XLTS U542 ( .A(d_ff2_X[30]), .B(n770), .Y(sh_exp_x[7]) );
OAI21XLTS U543 ( .A0(n772), .A1(n781), .B0(n771), .Y(sh_exp_x[5]) );
AO21XLTS U544 ( .A0(intadd_419_n1), .A1(d_ff2_X[27]), .B0(n772), .Y(
sh_exp_x[4]) );
OAI21XLTS U545 ( .A0(cont_iter_out[0]), .A1(n777), .B0(intadd_419_CI), .Y(
sh_exp_x[0]) );
CLKAND2X2TS U546 ( .A(n729), .B(n774), .Y(n529) );
OR2X1TS U547 ( .A(n535), .B(n763), .Y(n522) );
OAI31X1TS U548 ( .A0(cont_iter_out[3]), .A1(cont_iter_out[1]), .A2(n773),
.B0(n610), .Y(n528) );
OAI21XLTS U549 ( .A0(n623), .A1(n695), .B0(n622), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
OAI21XLTS U550 ( .A0(ack_cordic), .A1(n649), .B0(n646), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
OR4X2TS U551 ( .A(inst_CORDIC_FSM_v3_state_reg[3]), .B(
inst_CORDIC_FSM_v3_state_reg[1]), .C(inst_CORDIC_FSM_v3_state_reg[0]),
.D(inst_CORDIC_FSM_v3_state_reg[5]), .Y(n605) );
INVX2TS U552 ( .A(cont_iter_out[1]), .Y(n606) );
INVX2TS U553 ( .A(n605), .Y(n607) );
CLKBUFX3TS U554 ( .A(n615), .Y(n618) );
OAI21XLTS U555 ( .A0(n683), .A1(n727), .B0(n647), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
NAND3X2TS U556 ( .A(n774), .B(n775), .C(n606), .Y(n699) );
NOR2X4TS U557 ( .A(n773), .B(n774), .Y(n759) );
CLKINVX3TS U558 ( .A(n733), .Y(n756) );
INVX2TS U559 ( .A(n697), .Y(n643) );
CLKINVX3TS U560 ( .A(n733), .Y(n751) );
NOR3BX2TS U561 ( .AN(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[7]), .C(n609), .Y(
inst_CORDIC_FSM_v3_state_next[3]) );
CLKBUFX3TS U562 ( .A(n616), .Y(n617) );
NOR2X2TS U563 ( .A(n698), .B(n697), .Y(enab_d_ff4_Zn) );
NOR2X4TS U564 ( .A(n775), .B(n776), .Y(n730) );
NOR3BX2TS U565 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n609), .Y(ready_cordic) );
OAI32X4TS U566 ( .A0(n608), .A1(d_ff1_operation_out), .A2(
d_ff1_shift_region_flag_out[1]), .B0(d_ff1_shift_region_flag_out[0]),
.B1(n702), .Y(n703) );
OAI21XLTS U567 ( .A0(cont_iter_out[1]), .A1(n761), .B0(n635), .Y(n534) );
OAI21XLTS U568 ( .A0(n759), .A1(cont_iter_out[1]), .B0(n635), .Y(n536) );
AOI21X2TS U569 ( .A0(cont_iter_out[2]), .A1(n774), .B0(n619), .Y(n635) );
OAI21XLTS U570 ( .A0(beg_fsm_cordic), .A1(n725), .B0(n651), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
OR2X1TS U571 ( .A(d_ff_Xn[28]), .B(n627), .Y(first_mux_X[28]) );
OAI21XLTS U572 ( .A0(cont_iter_out[0]), .A1(n537), .B0(n764), .Y(n521) );
OAI211XLTS U573 ( .A0(n621), .A1(n611), .B0(n610), .C0(n699), .Y(n527) );
NOR2X1TS U574 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[6]), .Y(n612) );
NAND2X1TS U575 ( .A(n607), .B(n612), .Y(n609) );
NOR2X1TS U576 ( .A(cont_iter_out[0]), .B(cont_iter_out[1]), .Y(n621) );
NAND2X1TS U577 ( .A(n773), .B(cont_iter_out[3]), .Y(n611) );
NAND2X1TS U578 ( .A(n730), .B(n773), .Y(n610) );
INVX2TS U579 ( .A(n759), .Y(n537) );
INVX2TS U580 ( .A(n611), .Y(n619) );
NAND2X1TS U581 ( .A(n537), .B(cont_iter_out[0]), .Y(n764) );
INVX2TS U582 ( .A(n764), .Y(n763) );
NOR2X1TS U583 ( .A(n619), .B(n763), .Y(n760) );
OAI211X1TS U584 ( .A0(cont_iter_out[3]), .A1(n775), .B0(n773), .C0(n776),
.Y(n762) );
OAI21XLTS U585 ( .A0(n760), .A1(n776), .B0(n762), .Y(n526) );
OAI31X4TS U586 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[3]), .A2(n775),
.B0(n537), .Y(n761) );
OAI21XLTS U587 ( .A0(n776), .A1(n761), .B0(n611), .Y(n532) );
NOR3BX1TS U588 ( .AN(n612), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[2]), .Y(n624) );
NOR2X1TS U589 ( .A(inst_CORDIC_FSM_v3_state_reg[0]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .Y(n625) );
NOR2X1TS U590 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(n613), .Y(n614) );
NAND3BX1TS U591 ( .AN(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(n614), .Y(n725) );
NAND2X1TS U592 ( .A(n622), .B(n725), .Y(enab_d_ff_RB1) );
INVX2TS U593 ( .A(ready_add_subt), .Y(n698) );
OAI21XLTS U594 ( .A0(n759), .A1(n776), .B0(n761), .Y(n531) );
NOR3BX1TS U595 ( .AN(n607), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[2]), .Y(n620) );
NAND3BX1TS U596 ( .AN(inst_CORDIC_FSM_v3_state_reg[0]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(n614), .Y(n728) );
NAND2X1TS U597 ( .A(n727), .B(n728), .Y(beg_add_subt) );
INVX2TS U598 ( .A(rst), .Y(n154) );
BUFX3TS U599 ( .A(n618), .Y(n817) );
BUFX3TS U600 ( .A(n817), .Y(n809) );
BUFX3TS U601 ( .A(n817), .Y(n808) );
BUFX3TS U602 ( .A(n617), .Y(n807) );
CLKBUFX2TS U603 ( .A(n154), .Y(n615) );
BUFX3TS U604 ( .A(n618), .Y(n802) );
BUFX3TS U605 ( .A(n615), .Y(n806) );
BUFX3TS U606 ( .A(n615), .Y(n803) );
BUFX3TS U607 ( .A(n618), .Y(n804) );
BUFX3TS U608 ( .A(n618), .Y(n818) );
BUFX3TS U609 ( .A(n818), .Y(n816) );
CLKBUFX2TS U610 ( .A(n154), .Y(n616) );
BUFX3TS U611 ( .A(n617), .Y(n789) );
BUFX3TS U612 ( .A(n617), .Y(n790) );
BUFX3TS U613 ( .A(n818), .Y(n815) );
BUFX3TS U614 ( .A(n616), .Y(n791) );
BUFX3TS U615 ( .A(n617), .Y(n792) );
BUFX3TS U616 ( .A(n617), .Y(n793) );
BUFX3TS U617 ( .A(n616), .Y(n794) );
BUFX3TS U618 ( .A(n615), .Y(n795) );
BUFX3TS U619 ( .A(n615), .Y(n796) );
BUFX3TS U620 ( .A(n618), .Y(n797) );
BUFX3TS U621 ( .A(n818), .Y(n814) );
BUFX3TS U622 ( .A(n615), .Y(n798) );
BUFX3TS U623 ( .A(n618), .Y(n799) );
BUFX3TS U624 ( .A(n618), .Y(n800) );
BUFX3TS U625 ( .A(n618), .Y(n801) );
BUFX3TS U626 ( .A(n818), .Y(n813) );
BUFX3TS U627 ( .A(n616), .Y(n783) );
BUFX3TS U628 ( .A(n817), .Y(n812) );
BUFX3TS U629 ( .A(n616), .Y(n784) );
BUFX3TS U630 ( .A(n617), .Y(n785) );
BUFX3TS U631 ( .A(n616), .Y(n786) );
BUFX3TS U632 ( .A(n817), .Y(n811) );
BUFX3TS U633 ( .A(n617), .Y(n787) );
BUFX3TS U634 ( .A(n817), .Y(n810) );
BUFX3TS U635 ( .A(n617), .Y(n788) );
BUFX3TS U636 ( .A(n618), .Y(n805) );
NAND2X1TS U637 ( .A(n635), .B(n764), .Y(n523) );
NAND3BX1TS U638 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[6]), .C(n620), .Y(n695) );
INVX2TS U639 ( .A(n695), .Y(enab_cont_iter) );
INVX2TS U640 ( .A(ready_cordic), .Y(n649) );
NAND2X1TS U641 ( .A(n649), .B(n646), .Y(enab_d_ff5_data_out) );
NAND2X1TS U642 ( .A(n777), .B(cont_iter_out[0]), .Y(intadd_419_CI) );
NAND2X1TS U643 ( .A(n778), .B(cont_iter_out[0]), .Y(intadd_420_CI) );
NOR2X1TS U644 ( .A(d_ff2_X[27]), .B(intadd_419_n1), .Y(n772) );
OR3X1TS U645 ( .A(d_ff2_X[28]), .B(d_ff2_X[27]), .C(intadd_419_n1), .Y(n771)
);
NOR2X1TS U646 ( .A(d_ff2_Y[27]), .B(intadd_420_n1), .Y(n769) );
OR3X1TS U647 ( .A(d_ff2_Y[28]), .B(d_ff2_Y[27]), .C(intadd_420_n1), .Y(n768)
);
NAND2X1TS U648 ( .A(cont_iter_out[2]), .B(n730), .Y(n729) );
NOR2X1TS U649 ( .A(n774), .B(n729), .Y(n623) );
NAND2X1TS U650 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .Y(n726) );
INVX2TS U651 ( .A(n626), .Y(n627) );
INVX2TS U652 ( .A(n626), .Y(n628) );
INVX2TS U653 ( .A(n626), .Y(n708) );
AOI222X1TS U654 ( .A0(n644), .A1(d_ff2_X[6]), .B0(n692), .B1(d_ff2_Y[6]),
.C0(n739), .C1(d_ff2_Z[6]), .Y(n629) );
INVX2TS U655 ( .A(n629), .Y(add_subt_dataA[6]) );
AOI222X1TS U656 ( .A0(n644), .A1(d_ff2_X[3]), .B0(n692), .B1(d_ff2_Y[3]),
.C0(n739), .C1(d_ff2_Z[3]), .Y(n630) );
INVX2TS U657 ( .A(n630), .Y(add_subt_dataA[3]) );
INVX2TS U658 ( .A(n697), .Y(n755) );
AOI222X1TS U659 ( .A0(n756), .A1(d_ff2_X[1]), .B0(n643), .B1(d_ff2_Y[1]),
.C0(n739), .C1(d_ff2_Z[1]), .Y(n631) );
INVX2TS U660 ( .A(n631), .Y(add_subt_dataA[1]) );
AOI222X1TS U661 ( .A0(n756), .A1(d_ff2_X[4]), .B0(n750), .B1(d_ff2_Y[4]),
.C0(n739), .C1(d_ff2_Z[4]), .Y(n632) );
INVX2TS U662 ( .A(n632), .Y(add_subt_dataA[4]) );
AOI222X1TS U663 ( .A0(n756), .A1(d_ff2_X[2]), .B0(n755), .B1(d_ff2_Y[2]),
.C0(n739), .C1(d_ff2_Z[2]), .Y(n633) );
INVX2TS U664 ( .A(n633), .Y(add_subt_dataA[2]) );
AOI222X1TS U665 ( .A0(n756), .A1(d_ff2_X[5]), .B0(n731), .B1(d_ff2_Y[5]),
.C0(n739), .C1(d_ff2_Z[5]), .Y(n634) );
INVX2TS U666 ( .A(n634), .Y(add_subt_dataA[5]) );
OAI21X1TS U667 ( .A0(n759), .A1(n776), .B0(n635), .Y(n535) );
AOI222X1TS U668 ( .A0(n644), .A1(d_ff2_X[7]), .B0(n692), .B1(d_ff2_Y[7]),
.C0(n672), .C1(d_ff2_Z[7]), .Y(n636) );
INVX2TS U669 ( .A(n636), .Y(add_subt_dataA[7]) );
AOI222X1TS U670 ( .A0(n644), .A1(d_ff2_X[10]), .B0(n692), .B1(d_ff2_Y[10]),
.C0(n672), .C1(d_ff2_Z[10]), .Y(n637) );
INVX2TS U671 ( .A(n637), .Y(add_subt_dataA[10]) );
AOI222X1TS U672 ( .A0(n644), .A1(d_ff2_X[13]), .B0(n692), .B1(d_ff2_Y[13]),
.C0(n672), .C1(d_ff2_Z[13]), .Y(n638) );
INVX2TS U673 ( .A(n638), .Y(add_subt_dataA[13]) );
AOI222X1TS U674 ( .A0(n644), .A1(d_ff2_X[11]), .B0(n692), .B1(d_ff2_Y[11]),
.C0(n672), .C1(d_ff2_Z[11]), .Y(n639) );
INVX2TS U675 ( .A(n639), .Y(add_subt_dataA[11]) );
AOI222X1TS U676 ( .A0(n644), .A1(d_ff2_X[12]), .B0(n692), .B1(d_ff2_Y[12]),
.C0(n672), .C1(d_ff2_Z[12]), .Y(n640) );
INVX2TS U677 ( .A(n640), .Y(add_subt_dataA[12]) );
AOI222X1TS U678 ( .A0(n644), .A1(d_ff2_X[9]), .B0(n692), .B1(d_ff2_Y[9]),
.C0(n672), .C1(d_ff2_Z[9]), .Y(n641) );
INVX2TS U679 ( .A(n641), .Y(add_subt_dataA[9]) );
AOI222X1TS U680 ( .A0(n644), .A1(d_ff2_X[8]), .B0(n692), .B1(d_ff2_Y[8]),
.C0(n672), .C1(d_ff2_Z[8]), .Y(n642) );
INVX2TS U681 ( .A(n642), .Y(add_subt_dataA[8]) );
AOI222X1TS U682 ( .A0(n644), .A1(d_ff2_X[14]), .B0(n643), .B1(d_ff2_Y[14]),
.C0(n672), .C1(d_ff2_Z[14]), .Y(n645) );
INVX2TS U683 ( .A(n645), .Y(add_subt_dataA[14]) );
INVX2TS U684 ( .A(n647), .Y(enab_RB3) );
NOR4X1TS U685 ( .A(enab_cont_iter), .B(enab_RB3), .C(enab_d_ff_RB1), .D(
beg_add_subt), .Y(n650) );
INVX2TS U686 ( .A(inst_CORDIC_FSM_v3_state_next[3]), .Y(n648) );
AOI32X1TS U687 ( .A0(n650), .A1(n649), .A2(n648), .B0(ready_cordic), .B1(
ack_cordic), .Y(n651) );
CLKBUFX2TS U688 ( .A(n733), .Y(n669) );
INVX2TS U689 ( .A(n669), .Y(n732) );
INVX2TS U690 ( .A(n697), .Y(n731) );
AOI222X1TS U691 ( .A0(n667), .A1(d_ff3_sh_y_out[25]), .B0(n750), .B1(
d_ff3_sh_x_out[25]), .C0(n758), .C1(d_ff3_LUT_out[25]), .Y(n652) );
INVX2TS U692 ( .A(n652), .Y(add_subt_dataB[25]) );
AOI222X1TS U693 ( .A0(n689), .A1(d_ff3_sh_y_out[26]), .B0(n755), .B1(
d_ff3_sh_x_out[26]), .C0(n739), .C1(d_ff3_LUT_out[26]), .Y(n653) );
INVX2TS U694 ( .A(n653), .Y(add_subt_dataB[26]) );
INVX2TS U695 ( .A(n669), .Y(n689) );
INVX2TS U696 ( .A(n697), .Y(n688) );
CLKBUFX2TS U697 ( .A(n683), .Y(n676) );
AOI222X1TS U698 ( .A0(n667), .A1(d_ff3_sh_y_out[0]), .B0(n688), .B1(
d_ff3_sh_x_out[0]), .C0(n691), .C1(d_ff3_LUT_out[0]), .Y(n654) );
INVX2TS U699 ( .A(n654), .Y(add_subt_dataB[0]) );
INVX2TS U700 ( .A(n669), .Y(n667) );
INVX2TS U701 ( .A(n697), .Y(n666) );
INVX2TS U702 ( .A(n655), .Y(add_subt_dataB[24]) );
INVX2TS U703 ( .A(n656), .Y(add_subt_dataB[2]) );
INVX2TS U704 ( .A(n657), .Y(add_subt_dataA[29]) );
INVX2TS U705 ( .A(n658), .Y(add_subt_dataB[4]) );
INVX2TS U706 ( .A(n659), .Y(add_subt_dataB[21]) );
INVX2TS U707 ( .A(n660), .Y(add_subt_dataB[6]) );
AOI222X1TS U708 ( .A0(n689), .A1(d_ff3_sh_y_out[1]), .B0(n750), .B1(
d_ff3_sh_x_out[1]), .C0(n691), .C1(d_ff3_LUT_out[1]), .Y(n661) );
INVX2TS U709 ( .A(n661), .Y(add_subt_dataB[1]) );
INVX2TS U710 ( .A(n662), .Y(add_subt_dataB[8]) );
INVX2TS U711 ( .A(n663), .Y(add_subt_dataB[9]) );
INVX2TS U712 ( .A(n664), .Y(add_subt_dataB[10]) );
INVX2TS U713 ( .A(n665), .Y(add_subt_dataB[23]) );
INVX2TS U714 ( .A(n668), .Y(add_subt_dataB[12]) );
INVX2TS U715 ( .A(n669), .Y(n693) );
INVX2TS U716 ( .A(n697), .Y(n692) );
AOI222X1TS U717 ( .A0(n693), .A1(d_ff2_X[20]), .B0(n643), .B1(d_ff2_Y[20]),
.C0(n676), .C1(d_ff2_Z[20]), .Y(n670) );
INVX2TS U718 ( .A(n670), .Y(add_subt_dataA[20]) );
AOI222X1TS U719 ( .A0(n732), .A1(d_ff2_X[15]), .B0(n750), .B1(d_ff2_Y[15]),
.C0(n672), .C1(d_ff2_Z[15]), .Y(n671) );
INVX2TS U720 ( .A(n671), .Y(add_subt_dataA[15]) );
AOI222X1TS U721 ( .A0(n667), .A1(d_ff2_X[16]), .B0(n755), .B1(d_ff2_Y[16]),
.C0(n672), .C1(d_ff2_Z[16]), .Y(n673) );
INVX2TS U722 ( .A(n673), .Y(add_subt_dataA[16]) );
AOI222X1TS U723 ( .A0(n689), .A1(d_ff2_X[17]), .B0(n688), .B1(d_ff2_Y[17]),
.C0(n676), .C1(d_ff2_Z[17]), .Y(n674) );
INVX2TS U724 ( .A(n674), .Y(add_subt_dataA[17]) );
AOI222X1TS U725 ( .A0(n693), .A1(d_ff2_X[18]), .B0(n731), .B1(d_ff2_Y[18]),
.C0(n676), .C1(d_ff2_Z[18]), .Y(n675) );
INVX2TS U726 ( .A(n675), .Y(add_subt_dataA[18]) );
AOI222X1TS U727 ( .A0(n732), .A1(d_ff2_X[19]), .B0(n643), .B1(d_ff2_Y[19]),
.C0(n676), .C1(d_ff2_Z[19]), .Y(n677) );
INVX2TS U728 ( .A(n677), .Y(add_subt_dataA[19]) );
INVX2TS U729 ( .A(n678), .Y(add_subt_dataA[26]) );
AOI222X1TS U730 ( .A0(n667), .A1(d_ff2_X[21]), .B0(n750), .B1(d_ff2_Y[21]),
.C0(n683), .C1(d_ff2_Z[21]), .Y(n679) );
INVX2TS U731 ( .A(n679), .Y(add_subt_dataA[21]) );
AOI222X1TS U732 ( .A0(n689), .A1(d_ff2_X[22]), .B0(n755), .B1(d_ff2_Y[22]),
.C0(n683), .C1(d_ff2_Z[22]), .Y(n680) );
INVX2TS U733 ( .A(n680), .Y(add_subt_dataA[22]) );
AOI222X1TS U734 ( .A0(n693), .A1(d_ff2_X[23]), .B0(n688), .B1(d_ff2_Y[23]),
.C0(n683), .C1(d_ff2_Z[23]), .Y(n681) );
INVX2TS U735 ( .A(n681), .Y(add_subt_dataA[23]) );
INVX2TS U736 ( .A(n682), .Y(add_subt_dataA[24]) );
INVX2TS U737 ( .A(n684), .Y(add_subt_dataA[25]) );
AOI222X1TS U738 ( .A0(n689), .A1(d_ff2_X[28]), .B0(n755), .B1(d_ff2_Y[28]),
.C0(n691), .C1(d_ff2_Z[28]), .Y(n685) );
INVX2TS U739 ( .A(n685), .Y(add_subt_dataA[28]) );
INVX2TS U740 ( .A(n686), .Y(add_subt_dataA[27]) );
INVX2TS U741 ( .A(n687), .Y(add_subt_dataA[30]) );
AOI222X1TS U742 ( .A0(n732), .A1(d_ff2_X[31]), .B0(n643), .B1(d_ff2_Y[31]),
.C0(n691), .C1(d_ff2_Z[31]), .Y(n690) );
INVX2TS U743 ( .A(n690), .Y(add_subt_dataA[31]) );
AOI222X1TS U744 ( .A0(n732), .A1(d_ff2_X[0]), .B0(n731), .B1(d_ff2_Y[0]),
.C0(n691), .C1(d_ff2_Z[0]), .Y(n694) );
INVX2TS U745 ( .A(n694), .Y(add_subt_dataA[0]) );
INVX2TS U746 ( .A(n765), .Y(n766) );
NAND2X1TS U747 ( .A(n766), .B(cont_var_out[1]), .Y(n696) );
NOR3XLTS U748 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .C(n698), .Y(
enab_d_ff4_Xn) );
AOI32X1TS U750 ( .A0(cont_iter_out[3]), .A1(n699), .A2(n776), .B0(
cont_iter_out[2]), .B1(n699), .Y(data_out_LUT[4]) );
OAI22X1TS U751 ( .A0(cont_iter_out[3]), .A1(n729), .B0(cont_iter_out[2]),
.B1(n730), .Y(data_out_LUT[25]) );
NAND2X1TS U752 ( .A(d_ff1_operation_out), .B(d_ff1_shift_region_flag_out[1]),
.Y(n702) );
XOR2X1TS U753 ( .A(n608), .B(n700), .Y(n701) );
INVX2TS U754 ( .A(n701), .Y(n721) );
INVX2TS U755 ( .A(n719), .Y(n715) );
AOI22X1TS U756 ( .A0(n715), .A1(d_ff_Yn[31]), .B0(d_ff_Xn[31]), .B1(n719),
.Y(n704) );
XNOR2X1TS U757 ( .A(n704), .B(n703), .Y(fmtted_Result_31_) );
NOR2BX1TS U758 ( .AN(d_ff_Yn[0]), .B(n705), .Y(first_mux_Y[0]) );
NOR2BX1TS U759 ( .AN(d_ff_Yn[1]), .B(n705), .Y(first_mux_Y[1]) );
NOR2BX1TS U760 ( .AN(d_ff_Yn[2]), .B(n705), .Y(first_mux_Y[2]) );
NOR2BX1TS U761 ( .AN(d_ff_Yn[3]), .B(n705), .Y(first_mux_Y[3]) );
NOR2BX1TS U762 ( .AN(d_ff_Yn[4]), .B(n705), .Y(first_mux_Y[4]) );
NOR2BX1TS U763 ( .AN(d_ff_Yn[5]), .B(n705), .Y(first_mux_Y[5]) );
NOR2BX1TS U764 ( .AN(d_ff_Yn[6]), .B(n705), .Y(first_mux_Y[6]) );
NOR2BX1TS U765 ( .AN(d_ff_Yn[7]), .B(n705), .Y(first_mux_Y[7]) );
NOR2BX1TS U766 ( .AN(d_ff_Yn[8]), .B(n705), .Y(first_mux_Y[8]) );
NOR2BX1TS U767 ( .AN(d_ff_Yn[9]), .B(n705), .Y(first_mux_Y[9]) );
BUFX3TS U768 ( .A(n626), .Y(n714) );
NOR2BX1TS U769 ( .AN(d_ff_Yn[10]), .B(n706), .Y(first_mux_Y[10]) );
NOR2BX1TS U770 ( .AN(d_ff_Yn[11]), .B(n724), .Y(first_mux_Y[11]) );
NOR2BX1TS U771 ( .AN(d_ff_Yn[12]), .B(n712), .Y(first_mux_Y[12]) );
NOR2BX1TS U772 ( .AN(d_ff_Yn[13]), .B(n710), .Y(first_mux_Y[13]) );
NOR2BX1TS U773 ( .AN(d_ff_Yn[14]), .B(n706), .Y(first_mux_Y[14]) );
NOR2BX1TS U774 ( .AN(d_ff_Yn[15]), .B(n724), .Y(first_mux_Y[15]) );
NOR2BX1TS U775 ( .AN(d_ff_Yn[16]), .B(n712), .Y(first_mux_Y[16]) );
NOR2BX1TS U776 ( .AN(d_ff_Yn[17]), .B(n710), .Y(first_mux_Y[17]) );
NOR2BX1TS U777 ( .AN(d_ff_Yn[18]), .B(n706), .Y(first_mux_Y[18]) );
NOR2BX1TS U778 ( .AN(d_ff_Yn[19]), .B(n724), .Y(first_mux_Y[19]) );
NOR2BX1TS U779 ( .AN(d_ff_Yn[20]), .B(n707), .Y(first_mux_Y[20]) );
NOR2BX1TS U780 ( .AN(d_ff_Yn[21]), .B(n707), .Y(first_mux_Y[21]) );
NOR2BX1TS U781 ( .AN(d_ff_Yn[22]), .B(n707), .Y(first_mux_Y[22]) );
NOR2BX1TS U782 ( .AN(d_ff_Yn[23]), .B(n707), .Y(first_mux_Y[23]) );
NOR2BX1TS U783 ( .AN(d_ff_Yn[24]), .B(n707), .Y(first_mux_Y[24]) );
NOR2BX1TS U784 ( .AN(d_ff_Yn[25]), .B(n707), .Y(first_mux_Y[25]) );
NOR2BX1TS U785 ( .AN(d_ff_Yn[26]), .B(n707), .Y(first_mux_Y[26]) );
NOR2BX1TS U786 ( .AN(d_ff_Yn[27]), .B(n707), .Y(first_mux_Y[27]) );
NOR2BX1TS U787 ( .AN(d_ff_Yn[28]), .B(n707), .Y(first_mux_Y[28]) );
NOR2BX1TS U788 ( .AN(d_ff_Yn[29]), .B(n707), .Y(first_mux_Y[29]) );
INVX2TS U789 ( .A(n714), .Y(n723) );
NOR2BX1TS U790 ( .AN(d_ff_Yn[30]), .B(n706), .Y(first_mux_Y[30]) );
NOR2BX1TS U791 ( .AN(d_ff_Yn[31]), .B(n712), .Y(first_mux_Y[31]) );
INVX2TS U792 ( .A(n718), .Y(n717) );
INVX2TS U793 ( .A(n718), .Y(n720) );
INVX2TS U794 ( .A(n718), .Y(n722) );
NOR2BX1TS U795 ( .AN(d_ff_Xn[0]), .B(n712), .Y(first_mux_X[0]) );
NOR2BX1TS U796 ( .AN(d_ff_Xn[4]), .B(n710), .Y(first_mux_X[4]) );
NOR2BX1TS U797 ( .AN(d_ff_Xn[8]), .B(n706), .Y(first_mux_X[8]) );
NOR2BX1TS U798 ( .AN(d_ff_Xn[9]), .B(n710), .Y(first_mux_X[9]) );
NOR2BX1TS U799 ( .AN(d_ff_Xn[11]), .B(n724), .Y(first_mux_X[11]) );
NOR2BX1TS U800 ( .AN(d_ff_Xn[15]), .B(n706), .Y(first_mux_X[15]) );
NOR2BX1TS U801 ( .AN(d_ff_Xn[18]), .B(n712), .Y(first_mux_X[18]) );
NOR2BX1TS U802 ( .AN(d_ff_Xn[21]), .B(n710), .Y(first_mux_X[21]) );
NOR2BX1TS U803 ( .AN(d_ff_Xn[22]), .B(n724), .Y(first_mux_X[22]) );
NOR2BX1TS U804 ( .AN(d_ff_Xn[23]), .B(n712), .Y(first_mux_X[23]) );
NOR2BX1TS U805 ( .AN(d_ff_Xn[30]), .B(n710), .Y(first_mux_X[30]) );
NOR2BX1TS U806 ( .AN(d_ff_Xn[31]), .B(n724), .Y(first_mux_X[31]) );
NOR2BX1TS U807 ( .AN(beg_fsm_cordic), .B(n725), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U808 ( .A0(enab_d_ff4_Zn), .A1(n728), .B0(n727), .B1(n726), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U809 ( .AN(enab_d_ff4_Zn), .B(n728), .Y(
inst_CORDIC_FSM_v3_state_next[6]) );
OA21XLTS U810 ( .A0(cont_iter_out[2]), .A1(n730), .B0(n729), .Y(ITER_CONT_N4) );
XOR2XLTS U811 ( .A(d_ff3_sign_out), .B(cont_var_out[0]), .Y(op_add_subt) );
AO22XLTS U812 ( .A0(n693), .A1(d_ff3_sh_y_out[31]), .B0(n688), .B1(
d_ff3_sh_x_out[31]), .Y(add_subt_dataB[31]) );
AO22XLTS U813 ( .A0(n732), .A1(d_ff3_sh_y_out[30]), .B0(n731), .B1(
d_ff3_sh_x_out[30]), .Y(add_subt_dataB[30]) );
INVX2TS U814 ( .A(n697), .Y(n750) );
AOI22X1TS U815 ( .A0(n751), .A1(d_ff3_sh_y_out[29]), .B0(n643), .B1(
d_ff3_sh_x_out[29]), .Y(n734) );
NAND2X1TS U816 ( .A(n739), .B(d_ff3_LUT_out[27]), .Y(n736) );
NAND2X1TS U817 ( .A(n734), .B(n736), .Y(add_subt_dataB[29]) );
AOI22X1TS U818 ( .A0(n751), .A1(d_ff3_sh_y_out[28]), .B0(n750), .B1(
d_ff3_sh_x_out[28]), .Y(n735) );
NAND2X1TS U819 ( .A(n735), .B(n736), .Y(add_subt_dataB[28]) );
AOI22X1TS U820 ( .A0(n751), .A1(d_ff3_sh_y_out[27]), .B0(n755), .B1(
d_ff3_sh_x_out[27]), .Y(n737) );
NAND2X1TS U821 ( .A(n737), .B(n736), .Y(add_subt_dataB[27]) );
AOI22X1TS U822 ( .A0(n751), .A1(d_ff3_sh_y_out[22]), .B0(n750), .B1(
d_ff3_sh_x_out[22]), .Y(n738) );
OAI2BB1X1TS U823 ( .A0N(n754), .A1N(d_ff3_LUT_out[19]), .B0(n738), .Y(
add_subt_dataB[22]) );
AOI22X1TS U824 ( .A0(n751), .A1(d_ff3_sh_y_out[20]), .B0(n688), .B1(
d_ff3_sh_x_out[20]), .Y(n740) );
NAND2X1TS U825 ( .A(n739), .B(d_ff3_LUT_out[15]), .Y(n745) );
NAND2X1TS U826 ( .A(n740), .B(n745), .Y(add_subt_dataB[20]) );
AOI22X1TS U827 ( .A0(n751), .A1(d_ff3_sh_y_out[19]), .B0(n755), .B1(
d_ff3_sh_x_out[19]), .Y(n741) );
OAI2BB1X1TS U828 ( .A0N(n754), .A1N(d_ff3_LUT_out[19]), .B0(n741), .Y(
add_subt_dataB[19]) );
AOI22X1TS U829 ( .A0(n751), .A1(d_ff3_sh_y_out[18]), .B0(n688), .B1(
d_ff3_sh_x_out[18]), .Y(n742) );
OAI2BB1X1TS U830 ( .A0N(n754), .A1N(d_ff3_LUT_out[13]), .B0(n742), .Y(
add_subt_dataB[18]) );
AOI22X1TS U831 ( .A0(n751), .A1(d_ff3_sh_y_out[17]), .B0(n731), .B1(
d_ff3_sh_x_out[17]), .Y(n743) );
NAND2X1TS U832 ( .A(n743), .B(n745), .Y(add_subt_dataB[17]) );
AOI22X1TS U833 ( .A0(n756), .A1(d_ff3_sh_y_out[16]), .B0(n750), .B1(
d_ff3_sh_x_out[16]), .Y(n744) );
OAI2BB1X1TS U834 ( .A0N(n754), .A1N(d_ff3_LUT_out[3]), .B0(n744), .Y(
add_subt_dataB[16]) );
AOI22X1TS U835 ( .A0(n756), .A1(d_ff3_sh_y_out[15]), .B0(n643), .B1(
d_ff3_sh_x_out[15]), .Y(n746) );
NAND2X1TS U836 ( .A(n746), .B(n745), .Y(add_subt_dataB[15]) );
AOI22X1TS U837 ( .A0(n751), .A1(d_ff3_sh_y_out[14]), .B0(n731), .B1(
d_ff3_sh_x_out[14]), .Y(n747) );
OAI2BB1X1TS U838 ( .A0N(n754), .A1N(d_ff3_LUT_out[5]), .B0(n747), .Y(
add_subt_dataB[14]) );
AOI22X1TS U839 ( .A0(n756), .A1(d_ff3_sh_y_out[13]), .B0(n755), .B1(
d_ff3_sh_x_out[13]), .Y(n748) );
OAI2BB1X1TS U840 ( .A0N(n754), .A1N(d_ff3_LUT_out[13]), .B0(n748), .Y(
add_subt_dataB[13]) );
AOI22X1TS U841 ( .A0(n756), .A1(d_ff3_sh_y_out[11]), .B0(n688), .B1(
d_ff3_sh_x_out[11]), .Y(n749) );
OAI2BB1X1TS U842 ( .A0N(n754), .A1N(d_ff3_LUT_out[7]), .B0(n749), .Y(
add_subt_dataB[11]) );
AOI22X1TS U843 ( .A0(n751), .A1(d_ff3_sh_y_out[7]), .B0(n643), .B1(
d_ff3_sh_x_out[7]), .Y(n752) );
OAI2BB1X1TS U844 ( .A0N(n754), .A1N(d_ff3_LUT_out[7]), .B0(n752), .Y(
add_subt_dataB[7]) );
AOI22X1TS U845 ( .A0(n756), .A1(d_ff3_sh_y_out[5]), .B0(n731), .B1(
d_ff3_sh_x_out[5]), .Y(n753) );
OAI2BB1X1TS U846 ( .A0N(n754), .A1N(d_ff3_LUT_out[5]), .B0(n753), .Y(
add_subt_dataB[5]) );
AOI22X1TS U847 ( .A0(n756), .A1(d_ff3_sh_y_out[3]), .B0(n643), .B1(
d_ff3_sh_x_out[3]), .Y(n757) );
OAI2BB1X1TS U848 ( .A0N(n758), .A1N(d_ff3_LUT_out[3]), .B0(n757), .Y(
add_subt_dataB[3]) );
AOI22X1TS U849 ( .A0(cont_iter_out[1]), .A1(n761), .B0(n759), .B1(n606), .Y(
n533) );
AOI22X1TS U850 ( .A0(cont_iter_out[1]), .A1(n761), .B0(n760), .B1(n776), .Y(
n525) );
OAI2BB1X1TS U851 ( .A0N(cont_iter_out[1]), .A1N(n523), .B0(n762), .Y(n524)
);
AOI22X1TS U852 ( .A0(cont_iter_out[1]), .A1(n764), .B0(n763), .B1(n776), .Y(
n520) );
AOI22X1TS U853 ( .A0(n766), .A1(n779), .B0(cont_var_out[0]), .B1(n765), .Y(
n518) );
NOR2XLTS U855 ( .A(d_ff2_Y[29]), .B(n768), .Y(n767) );
XNOR2X1TS U856 ( .A(d_ff2_Y[29]), .B(n768), .Y(sh_exp_y[6]) );
NOR2XLTS U857 ( .A(d_ff2_X[29]), .B(n771), .Y(n770) );
XNOR2X1TS U858 ( .A(d_ff2_X[29]), .B(n771), .Y(sh_exp_x[6]) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
|
module mojo_top(
// 50MHz clock input
input wire clk,
// Input from reset button (active low)
input wire rst_n,
// cclk input from AVR, high when AVR is ready
input wire cclk,
// Outputs to the 8 onboard LEDs
output wire [7:0]led,
// AVR SPI connections
output wire spi_miso,
input wire spi_ss,
input wire spi_mosi,
input wire spi_sck,
// AVR ADC channel select
output wire [3:0] spi_channel,
// Serial connections
input wire avr_tx, // AVR Tx => FPGA Rx
output wire avr_rx, // AVR Rx => FPGA Tx
input wire avr_rx_busy, // AVR Rx buffer full
output wire i2c_scl,
inout wire i2c_sda,
output wire i2c_clk_in
);
wire reset = ~rst_n; // make reset active high
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
assign led[5:0] = led_buffer;
assign led[7] = tick_1s;
assign led[6] = i2c_clk_in;
wire tick_1s;
//Generate a 1s timer
//timer #(.CTR_LEN(26)) second_timer (
timer #(.CTR_LEN(16)) second_timer (
.clk(clk),
.reset(reset),
.tick(tick_1s)
);
clk_divider #(.DIVIDER(500)) i2c_clk_divider (
.reset(reset),
.clk_in(clk),
.clk_out(i2c_clk_in)
);
wire i2c_start;
reg i2c_reset = 1'b1;
wire [7:0] i2c_nbytes;
wire [6:0] i2c_slave_addr;
wire i2c_rw;
wire [7:0] i2c_write_data;
wire [7:0] i2c_read_data;
wire i2c_tx_data_req;
wire i2c_rx_data_ready;
wire ready;
wire busy;
i2c_master i2c (
.clk(i2c_clk_in),
.reset(i2c_reset),
.start(i2c_start),
.nbytes_in(i2c_nbytes),
.addr_in(i2c_slave_addr),
.rw_in(i2c_rw),
.write_data(i2c_write_data),
.read_data(i2c_read_data),
.tx_data_req(i2c_tx_data_req),
.rx_data_ready(i2c_rx_data_ready),
.sda_w(i2c_sda),
.scl(i2c_scl)
);
wire [6:0] slave_addr = 7'b1010000;
reg [15:0] mem_addr;
wire [7:0] read_n_bytes = 8'd1;
wire [7:0] read_nbytes = 1;
reg start = 0;
wire [7:0] data_out;
wire byte_ready;
wire eeprom_busy;
read_eeprom instance_name (
.clk(clk),
.reset(reset),
.slave_addr_w(slave_addr),
.mem_addr_w(mem_addr),
.read_nbytes_w(read_nbytes),
.start(start),
.data_out(data_out),
.byte_ready(byte_ready),
.i2c_slave_addr(i2c_slave_addr),
.i2c_rw(i2c_rw),
.i2c_write_data(i2c_write_data),
.i2c_nbytes(i2c_nbytes),
.i2c_read_data(i2c_read_data),
.i2c_tx_data_req(i2c_tx_data_req),
.i2c_rx_data_ready(i2c_rx_data_ready),
.i2c_start(i2c_start),
.busy(eeprom_busy)
);
reg [5:0] led_buffer;
//every time a new byte is ready, write it to the LEDs
always @(posedge byte_ready) begin
led_buffer <= data_out[5:0];
end
reg measured_this_pulse;
always @(posedge clk) begin
if (reset == 1) begin
mem_addr <= 16'h0000;
measured_this_pulse <= 0;
end else begin
if ((tick_1s == 1) && (measured_this_pulse == 0)) begin
measured_this_pulse <= 1;
mem_addr <= mem_addr + 1'b1;
if (mem_addr > 8) begin
mem_addr <= 0;
end
start <= 1;
end //tick_1s==1
if ((start == 1) && (eeprom_busy == 1)) begin
start <= 0;
end //eeprom_busy and start
if (tick_1s == 0) begin
measured_this_pulse <= 0;
end //tick_1s==0
end //reset
end
//we need to make sure the i2c module is reset *after*
//it's clock has begun
always @(negedge i2c_clk_in) begin
if (reset == 1) begin
i2c_reset <= 1;
end else begin
i2c_reset <= 0;
end
end //posedge clk_i2c_in
endmodule
|
`timescale 1 ns / 1 ps
module sample_generator_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S_AXIS
parameter integer C_S_AXIS_TDATA_WIDTH = 32,
// Parameters of Axi Master Bus Interface M_AXIS
parameter integer C_M_AXIS_TDATA_WIDTH = 32,
parameter integer C_M_AXIS_START_COUNT = 32
)
(
// Users to add ports here
input [7:0] FrameSize,
input En,
input AXI_En,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S_AXIS
input wire s_axis_aclk,
input wire s_axis_aresetn,
output wire s_axis_tready,
input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] s_axis_tdata,
input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] s_axis_tstrb,
input wire s_axis_tlast,
input wire s_axis_tvalid,
// Ports of Axi Master Bus Interface M_AXIS
input wire m_axis_aclk,
input wire m_axis_aresetn,
output wire m_axis_tvalid,
output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] m_axis_tdata,
output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] m_axis_tstrb,
output wire m_axis_tlast,
input wire m_axis_tready
);
// Instantiation of Axi Bus Interface S_AXIS
sample_generator_v1_0_S_AXIS # (
.C_S_AXIS_TDATA_WIDTH(C_S_AXIS_TDATA_WIDTH)
) sample_generator_v1_0_S_AXIS_inst (
.En(En),
.S_AXIS_ACLK(s_axis_aclk),
.S_AXIS_ARESETN(s_axis_aresetn),
.S_AXIS_TREADY(s_axis_tready),
.S_AXIS_TDATA(s_axis_tdata),
.S_AXIS_TSTRB(s_axis_tstrb),
.S_AXIS_TLAST(s_axis_tlast),
.S_AXIS_TVALID(s_axis_tvalid)
);
// Instantiation of Axi Bus Interface M_AXIS
sample_generator_v1_0_M_AXIS # (
.C_M_AXIS_TDATA_WIDTH(C_M_AXIS_TDATA_WIDTH),
.C_M_START_COUNT(C_M_AXIS_START_COUNT)
) sample_generator_v1_0_M_AXIS_inst (
.FrameSize(FrameSize),
.AXI_En(AXI_En),
.M_AXIS_ACLK(m_axis_aclk),
.M_AXIS_ARESETN(m_axis_aresetn),
.M_AXIS_TVALID(m_axis_tvalid),
.M_AXIS_TDATA(m_axis_tdata),
.M_AXIS_TSTRB(m_axis_tstrb),
.M_AXIS_TLAST(m_axis_tlast),
.M_AXIS_TREADY(m_axis_tready)
);
// Add user logic here
// User logic ends
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22AI_TB_V
`define SKY130_FD_SC_LP__O22AI_TB_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o22ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_lp__o22ai dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22AI_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3_BEHAVIORAL_V
`define SKY130_FD_SC_LS__OR3_BEHAVIORAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3_BEHAVIORAL_V
|
module sine (
phase,
sine_out
);
input wire [20:0] phase;
output wire [15:0] sine_out;
wire [8:0] rom_adrs;
wire [9:0] leap_coeff;
wire [15:0] sin_rom_out;
wire [15:0] diff_rom_out;
wire [25:0] leap_add_p;
wire [15:0] leap_add;
wire [15:0] signed_sine;
function [8:0] adrs_conv;
input [8:0] adrs_p;
input sel;
begin
case(sel)
0 : adrs_conv = adrs_p;
1 : adrs_conv = 9'H1FF - adrs_p;
default : adrs_conv = 9'bxxxxxxxxx;
endcase
end
endfunction
function [9:0] leap_conv;
input [9:0] leap_p;
input sel;
begin
case(sel)
0 : leap_conv = leap_p;
1 : leap_conv = 10'H2FF - leap_p;
default : leap_conv = 10'bxxxxxxxxxx;
endcase
end
endfunction
function [15:0] quad3_4;
input [15:0] signed_sine;
input sel;
begin
case(sel)
0 : quad3_4 = signed_sine >> 1;
1 : quad3_4 = ~(signed_sine >> 1) + 1'b1;
default : quad3_4 = 16'bxxxxxxxxxxxxxxxx;
endcase
end
endfunction
assign leap_add_p = diff_rom_out * leap_coeff;
assign leap_add = leap_add_p[25:9];
assign signed_sine = sin_rom_out[15:0] + leap_add[15:0];
assign rom_adrs = adrs_conv(phase[18:10], phase[19]);
assign leap_coeff = leap_conv(phase[9:0], phase[19]);
assign sine_out = quad3_4(signed_sine, phase[20]);
sin_rom sin_rom_i(
.inadrs(rom_adrs),
.outsine(sin_rom_out)
);
diff_rom diff_rom_i(
.inadrs(rom_adrs),
.outdiff(diff_rom_out)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
//
// Title : Drawing Engine Color Selector
// File : ded_colsel.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Select Outgoing color value
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module ded_colsel
#(parameter BYTES = 4)
(
input mclock, // Memory Controller Clock
input ps8_4, // Pixel size equals 8 bits
input ps16_4, // Pixel size equals 16 bits.
input ps32_4, // Pixel size equals 32 bits.
input [1:0] stpl_4, // Stipple bit 01=planar, 10 = packed.
input lt_actv_4, // Line active bit.
input [31:0] fore_4, // foreground data.
input [31:0] back_4, // background data.
input [(BYTES<<3)-1:0] fs_dat, // Data from funnel shifter.
input [BYTES-1:0] cx_sel, // Color Expand selector.
input [(BYTES<<3)-1:0] pc_col, // Pixel Cache Data.
input solid_4, // Solid bit level two.
output reg [(BYTES<<3)-1:0] col_dat, // color data output.
output [BYTES-1:0] trns_msk // transparentcy mask.
);
reg [(BYTES<<3)-1:0] pipe_col, pipe_col_0;
reg [BYTES-1:0] fg_bg; // color selector signal
reg [BYTES-1:0] cx_reg; // Color Expand selector
reg [(BYTES<<3)-1:0] pc_col_d;
wire [(BYTES<<3)-1:0] cx_color_dat; // color expanded data
wire [(BYTES<<3)-1:0] wide_fore_4; // expanded foreground color
wire [(BYTES<<3)-1:0] wide_back_4; // expanded background color
// Pipe stage from funnel shifter
always @(posedge mclock) pc_col_d <= pc_col;
always @(posedge mclock) begin
cx_reg <= cx_sel; // pipe stage insterted in the funshf
// addd one stage to increase clock speed of MC
pipe_col_0 <= (lt_actv_4) ? pc_col_d : fs_dat;
pipe_col <= pipe_col_0;
end
/************************************************************************/
/* EXPAND THE COLOR REGISTERS */
/* if in stipple mode or line draw use color expanded data. */
assign wide_fore_4[(BYTES<<3)-1:0] = (lt_actv_4 && |stpl_4) ? pc_col : {(BYTES/4){fore_4}} ;
assign wide_back_4[(BYTES<<3)-1:0] = {(BYTES/4){back_4}} ;
/************************************************************************/
/************************************************************************/
/* OUTPUT SELECTOR */
/* if in stipple mode or line draw use color expanded data. */
/************************************************************************/
always @(posedge mclock)begin
if(lt_actv_4) col_dat <= pipe_col; // else use funnel shifter color
else if(solid_4) col_dat <= wide_fore_4; // solid is set force foreground col
else if(stpl_4 == 2'b00) col_dat <= pipe_col; // use pixel cache data
else col_dat <= cx_color_dat;// stipple color expanded color
end
assign trns_msk = fg_bg;
/************************************************************************/
/* Replicate color data and selectors. */
/************************************************************************/
always @*
begin
if(BYTES == 4)
begin
case({ps8_4,ps16_4,ps32_4}) /* synopsys parallel_case */
3'b001: fg_bg = { cx_reg[0],cx_reg[0],cx_reg[0],cx_reg[0]};
3'b010: fg_bg = { cx_reg[1],cx_reg[1],cx_reg[0],cx_reg[0]};
default: fg_bg = cx_reg;
endcase
end
else if(BYTES == 8)
begin
case({ps8_4,ps16_4,ps32_4}) /* synopsys parallel_case */
3'b001:fg_bg = { cx_reg[1],cx_reg[1],cx_reg[1],cx_reg[1],
cx_reg[0],cx_reg[0],cx_reg[0],cx_reg[0]};
3'b010:fg_bg = { cx_reg[3],cx_reg[3],cx_reg[2],cx_reg[2],
cx_reg[1],cx_reg[1],cx_reg[0],cx_reg[0]};
// 3'b1xx:fg_bg = cx_reg;
default:fg_bg = cx_reg;
endcase
end
else begin
case({ps8_4,ps16_4,ps32_4}) /* synopsys parallel_case */
3'b001:fg_bg = {cx_reg[3],cx_reg[3],cx_reg[3],cx_reg[3],
cx_reg[2],cx_reg[2],cx_reg[2],cx_reg[2],
cx_reg[1],cx_reg[1],cx_reg[1],cx_reg[1],
cx_reg[0],cx_reg[0],cx_reg[0],cx_reg[0]};
3'b010:fg_bg = {cx_reg[7],cx_reg[7],cx_reg[6],cx_reg[6],
cx_reg[5],cx_reg[5],cx_reg[4],cx_reg[4],
cx_reg[3],cx_reg[3],cx_reg[2],cx_reg[2],
cx_reg[1],cx_reg[1],cx_reg[0],cx_reg[0]};
// 3'b1xx:fg_bg = cx_reg;
default:fg_bg = cx_reg;
endcase
end
end
/************************************************************************/
assign cx_color_dat[007:000] = (fg_bg[00]) ? wide_fore_4[007:000] : wide_back_4[007:000];
assign cx_color_dat[015:008] = (fg_bg[01]) ? wide_fore_4[015:008] : wide_back_4[015:008];
assign cx_color_dat[023:016] = (fg_bg[02]) ? wide_fore_4[023:016] : wide_back_4[023:016];
assign cx_color_dat[031:024] = (fg_bg[03]) ? wide_fore_4[031:024] : wide_back_4[031:024];
`ifdef BYTE8
assign cx_color_dat[039:032] = (fg_bg[04]) ? wide_fore_4[039:032] : wide_back_4[039:032];
assign cx_color_dat[047:040] = (fg_bg[05]) ? wide_fore_4[047:040] : wide_back_4[047:040];
assign cx_color_dat[055:048] = (fg_bg[06]) ? wide_fore_4[055:048] : wide_back_4[055:048];
assign cx_color_dat[063:056] = (fg_bg[07]) ? wide_fore_4[063:056] : wide_back_4[063:056];
`endif
`ifdef BYTE16
assign cx_color_dat[039:032] = (fg_bg[04]) ? wide_fore_4[039:032] : wide_back_4[039:032];
assign cx_color_dat[047:040] = (fg_bg[05]) ? wide_fore_4[047:040] : wide_back_4[047:040];
assign cx_color_dat[055:048] = (fg_bg[06]) ? wide_fore_4[055:048] : wide_back_4[055:048];
assign cx_color_dat[063:056] = (fg_bg[07]) ? wide_fore_4[063:056] : wide_back_4[063:056];
assign cx_color_dat[071:064] = (fg_bg[08]) ? wide_fore_4[071:064] : wide_back_4[071:064];
assign cx_color_dat[079:072] = (fg_bg[09]) ? wide_fore_4[079:072] : wide_back_4[079:072];
assign cx_color_dat[087:080] = (fg_bg[10]) ? wide_fore_4[087:080] : wide_back_4[087:080];
assign cx_color_dat[095:088] = (fg_bg[11]) ? wide_fore_4[095:088] : wide_back_4[095:088];
assign cx_color_dat[103:096] = (fg_bg[12]) ? wide_fore_4[103:096] : wide_back_4[103:096];
assign cx_color_dat[111:104] = (fg_bg[13]) ? wide_fore_4[111:104] : wide_back_4[111:104];
assign cx_color_dat[119:112] = (fg_bg[14]) ? wide_fore_4[119:112] : wide_back_4[119:112];
assign cx_color_dat[127:120] = (fg_bg[15]) ? wide_fore_4[127:120] : wide_back_4[127:120];
`endif
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Thomas Kappenman
//
// Create Date: 03/03/2015 09:33:36 PM
// Design Name:
// Module Name: PS2Receiver
// Project Name: Nexys4DDR Keyboard Demo
// Target Devices: Nexys4DDR
// Tool Versions:
// Description: PS2 Receiver module used to shift in keycodes from a keyboard plugged into the PS2 port
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PS2Receiver(
input clk,
input kclk,
input kdata,
output [31:0] keycodeout
);
wire kclkf, kdataf;
reg [7:0]datacur;
reg [7:0]dataprev;
reg [3:0]cnt;
reg [31:0]keycode;
reg flag;
initial begin
keycode[31:0]<=0'h00000000;
cnt<=4'b0000;
flag<=1'b0;
end
debouncer debounce(
.clk(clk),
.I0(kclk),
.I1(kdata),
.O0(kclkf),
.O1(kdataf)
);
always@(negedge(kclkf))begin
case(cnt)
0:;//Start bit
1:datacur[0]<=kdataf;
2:datacur[1]<=kdataf;
3:datacur[2]<=kdataf;
4:datacur[3]<=kdataf;
5:datacur[4]<=kdataf;
6:datacur[5]<=kdataf;
7:datacur[6]<=kdataf;
8:datacur[7]<=kdataf;
9:flag<=1'b1;
10:flag<=1'b0;
endcase
if(cnt<=9) cnt<=cnt+1;
else if(cnt==10) cnt<=0;
end
always @(posedge flag)begin
if (dataprev!=datacur)begin
keycode[31:24]<=keycode[23:16];
keycode[23:16]<=keycode[15:8];
keycode[15:8]<=dataprev;
keycode[7:0]<=datacur;
dataprev<=datacur;
end
end
assign keycodeout=keycode;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module flt_fx1616_mult
(
input clk,
input rstn,
input [31:0] fx,
input [31:0] bfl,
output reg [31:0] fl
);
reg sfx; // Sign of fixed
reg [31:0] afx; // Absolute fixed
reg [5:0] nom_shft_1; // Normalize shift.
reg [55:0] mfl_1; // Multiply Result.
reg [55:0] nmfl_1; // Mantisa of the Float
reg sfx_1;
reg sbfl_1;
reg [7:0] efl_1; // Exponent of the Float
reg [7:0] ebfl_1; // Exponent of the Float
reg sfl_1; // Sign of float
reg result0;
reg result0_1;
always @* // Take the absolute value of AFX.
begin
if(fx[31]) begin
sfx = 1;
afx = ~fx + 1;
end else begin
sfx = 0;
afx = fx;
end
if((fx==0) || (bfl[30:0]==0))result0 = 1;
else result0 = 0;
end
// Calculate the Mantissa.
always @(posedge clk, negedge rstn) begin
if(!rstn) begin
mfl_1 <= 56'h0;
sfx_1 <= 1'b0;
sbfl_1 <= 1'b0;
ebfl_1 <= 8'h0;
result0_1 <= 1'b0;
end else begin
mfl_1 <= afx * {1'b1,bfl[22:0]};
sfx_1 <= sfx;
sbfl_1 <= bfl[31];
ebfl_1 <= bfl[30:23];
result0_1 <= result0;
end
end
always @* begin
casex(mfl_1[55:23]) /* synopsys parallel_case */
33'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd0;
33'b01xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd1;
33'b001xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd2;
33'b0001xxxxxxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd3;
33'b00001xxxxxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd4;
33'b000001xxxxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd5;
33'b0000001xxxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd6;
33'b00000001xxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd7;
33'b000000001xxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd8;
33'b0000000001xxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd9;
33'b00000000001xxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd10;
33'b000000000001xxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd11;
33'b0000000000001xxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd12;
33'b00000000000001xxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd13;
33'b000000000000001xxxxxxxxxxxxxxxxxx: nom_shft_1=6'd14;
33'b0000000000000001xxxxxxxxxxxxxxxxx: nom_shft_1=6'd15;
33'b00000000000000001xxxxxxxxxxxxxxxx: nom_shft_1=6'd16;
33'b000000000000000001xxxxxxxxxxxxxxx: nom_shft_1=6'd17;
33'b0000000000000000001xxxxxxxxxxxxxx: nom_shft_1=6'd18;
33'b00000000000000000001xxxxxxxxxxxxx: nom_shft_1=6'd19;
33'b000000000000000000001xxxxxxxxxxxx: nom_shft_1=6'd20;
33'b0000000000000000000001xxxxxxxxxxx: nom_shft_1=6'd21;
33'b00000000000000000000001xxxxxxxxxx: nom_shft_1=6'd22;
33'b000000000000000000000001xxxxxxxxx: nom_shft_1=6'd23;
33'b0000000000000000000000001xxxxxxxx: nom_shft_1=6'd24;
33'b00000000000000000000000001xxxxxxx: nom_shft_1=6'd25;
33'b000000000000000000000000001xxxxxx: nom_shft_1=6'd26;
33'b0000000000000000000000000001xxxxx: nom_shft_1=6'd27;
33'b00000000000000000000000000001xxxx: nom_shft_1=6'd28;
33'b000000000000000000000000000001xxx: nom_shft_1=6'd29;
33'b0000000000000000000000000000001xx: nom_shft_1=6'd30;
33'b00000000000000000000000000000001x: nom_shft_1=6'd31;
33'b000000000000000000000000000000001: nom_shft_1=6'd32;
default: nom_shft_1=0;
endcase
end
// Calculate the sign bit.
always @* sfl_1 = sfx_1 ^ sbfl_1;
// Calculate the Exponant.
// always @* efl_1 = ebfl_1 + (8'h10 - nom_shft_1);
always @* efl_1 = ebfl_1 + (8'h10 - nom_shft_1);
always @* nmfl_1 = mfl_1 << nom_shft_1;
always @(posedge clk, negedge rstn) //(SFL or EFL or MFL or FX or BFL)
begin
if(!rstn) fl <= 32'h0;
else if(result0_1) fl <= 32'h0;
else fl <= {sfl_1,efl_1,nmfl_1[54:32]};
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_test_expr;
assign valid_test_expr = ~((^test_expr) ^ (^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_ASSERT_ON
reg [width-1:0] last_test_expr;
reg [width:0] temp_expr;
reg r_reset_n;
`ifdef OVL_SYNTHESIS
`else
initial begin
r_reset_n = 1'b0;
end
`endif
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
r_reset_n <= `OVL_RESET_SIGNAL;
last_test_expr <= test_expr;
// check second clock after reset
if (r_reset_n && (last_test_expr != test_expr)) begin
temp_expr = {1'b0,last_test_expr} - {1'b0,test_expr};
// 2's complement result
if (temp_expr[width-1:0] != value) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is decreased by a value other than specified");
end
end
end
else begin
r_reset_n <= 0;
`ifdef OVL_INIT_REG
last_test_expr <= {width{1'b0}};
temp_expr = {(width+1){1'b0}};
`endif
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
always @(posedge clk)
begin
if (`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
reg [width-1:0] prev_test_expr;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
if (test_expr != prev_test_expr) begin
ovl_cover_t("test_expr_change covered");
end
prev_test_expr <= test_expr;
end //basic coverage
end // OVL_COVER_NONE
end
else begin
`ifdef OVL_INIT_REG
prev_test_expr <= {width{1'b0}};
`endif
end
end //always
`endif // OVL_COVER_ON
|
module spi_ctrl_kl(
clk,rst_n,sck,mosi,miso,cs_n,spi_tx_en,spi_rx_en,mode_select,receive_status
);
input clk,rst_n,miso;
input mode_select;
output sck,mosi,cs_n;
output receive_status;
input spi_tx_en;
input spi_rx_en;
wire spi_over;
wire receive_status;
wire tran_cs;
reg spi_clk;
reg cs_n;
reg[7:0] clk_count;
reg[7:0] rst_count;
reg rst_flag;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
clk_count <= 8'h0;
spi_clk <= 1'b0;
end
else begin
if(clk_count < 8'd250)
clk_count <= clk_count + 1'b1;
else begin
clk_count <= 8'h0;
spi_clk <= ~spi_clk;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cs_n <= 1'b1;
else begin
if(spi_over || ((spi_tx_en == 1'b0) && (spi_rx_en == 1'b0)))
cs_n <= 1'b1;
else
cs_n <= tran_cs;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
rst_flag <= 1'b0;
rst_count <= 'h0;
end
else begin
if(rst_count<8'd20)
rst_count <= rst_count + 1'b1;
else
rst_flag <= 1'b1;
end
end
spi_master_kl spi_master_kl_instance(
.clk(spi_clk),
.rst_n(rst_flag),
.spi_miso(miso),
.spi_mosi(mosi),
.spi_clk(sck),
.spi_tx_en(spi_tx_en),
.spi_over(spi_over),
.spi_rx_en(spi_rx_en),
.mode_select(mode_select),
.receive_status(receive_status),
.cs(tran_cs)
);
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_pwm16_core(
input clock,
input reset,
input io_regs_cfg_write_valid,
input [31:0] io_regs_cfg_write_bits,
output [31:0] io_regs_cfg_read,
input io_regs_countLo_write_valid,
input [31:0] io_regs_countLo_write_bits,
output [31:0] io_regs_countLo_read,
input io_regs_countHi_write_valid,
input [31:0] io_regs_countHi_write_bits,
output [31:0] io_regs_countHi_read,
input io_regs_s_write_valid,
input [15:0] io_regs_s_write_bits,
output [15:0] io_regs_s_read,
input io_regs_cmp_0_write_valid,
input [15:0] io_regs_cmp_0_write_bits,
output [15:0] io_regs_cmp_0_read,
input io_regs_cmp_1_write_valid,
input [15:0] io_regs_cmp_1_write_bits,
output [15:0] io_regs_cmp_1_read,
input io_regs_cmp_2_write_valid,
input [15:0] io_regs_cmp_2_write_bits,
output [15:0] io_regs_cmp_2_read,
input io_regs_cmp_3_write_valid,
input [15:0] io_regs_cmp_3_write_bits,
output [15:0] io_regs_cmp_3_read,
input io_regs_feed_write_valid,
input [31:0] io_regs_feed_write_bits,
output [31:0] io_regs_feed_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
output io_ip_0,
output io_ip_1,
output io_ip_2,
output io_ip_3,
output io_gpio_0,
output io_gpio_1,
output io_gpio_2,
output io_gpio_3
);
wire [3:0] T_178;
reg [3:0] scale;
reg [31:0] GEN_22;
wire [3:0] GEN_0;
reg [15:0] cmp_0;
reg [31:0] GEN_23;
wire [15:0] GEN_1;
reg [15:0] cmp_1;
reg [31:0] GEN_24;
wire [15:0] GEN_2;
reg [15:0] cmp_2;
reg [31:0] GEN_25;
wire [15:0] GEN_3;
reg [15:0] cmp_3;
reg [31:0] GEN_26;
wire [15:0] GEN_4;
wire countEn;
reg [4:0] T_196;
reg [31:0] GEN_27;
wire [4:0] GEN_18;
wire [5:0] T_197;
reg [25:0] T_199;
reg [31:0] GEN_28;
wire T_200;
wire [26:0] T_202;
wire [26:0] GEN_5;
wire [30:0] T_203;
wire [32:0] T_207;
wire [27:0] T_208;
wire [32:0] GEN_6;
wire [27:0] GEN_7;
wire [30:0] T_209;
wire [15:0] s;
wire T_210;
wire [3:0] T_211;
reg [3:0] center;
reg [31:0] GEN_29;
wire [3:0] GEN_8;
wire T_215;
wire T_216;
wire [15:0] T_217;
wire [15:0] T_218;
wire elapsed_0;
wire T_220;
wire T_221;
wire [15:0] T_223;
wire elapsed_1;
wire T_225;
wire T_226;
wire [15:0] T_228;
wire elapsed_2;
wire T_230;
wire T_231;
wire [15:0] T_233;
wire elapsed_3;
wire [5:0] GEN_19;
wire [5:0] T_234;
wire [4:0] T_235;
wire [26:0] GEN_20;
wire [26:0] T_239;
wire [26:0] T_241;
wire [25:0] T_242;
wire [30:0] T_243;
wire [4:0] GEN_21;
wire [5:0] T_245;
wire [4:0] T_246;
wire [30:0] T_247;
wire feed;
wire T_248;
reg zerocmp;
reg [31:0] GEN_30;
wire GEN_9;
wire T_252;
wire countReset;
wire [32:0] GEN_10;
wire [27:0] GEN_11;
wire T_255;
reg T_259;
reg [31:0] GEN_31;
wire GEN_12;
wire T_261;
wire T_262;
wire T_263;
reg T_267;
reg [31:0] GEN_32;
wire GEN_13;
wire T_268;
reg T_269;
reg [31:0] GEN_33;
wire [1:0] T_282;
wire [1:0] T_283;
wire [3:0] T_284;
reg [3:0] ip;
reg [31:0] GEN_34;
wire [1:0] T_286;
wire [1:0] T_287;
wire [3:0] T_288;
wire [3:0] T_289;
wire [3:0] T_290;
wire [3:0] T_297;
wire [3:0] T_298;
wire [3:0] T_299;
wire [3:0] T_300;
wire [3:0] T_301;
wire [3:0] T_304;
wire [3:0] GEN_14;
wire [3:0] T_305;
reg [3:0] gang;
reg [31:0] GEN_35;
wire [3:0] GEN_15;
wire T_316;
wire T_319;
wire T_323;
reg oneShot;
reg [31:0] GEN_36;
wire GEN_16;
wire T_325;
reg countAlways;
reg [31:0] GEN_37;
wire GEN_17;
wire [4:0] T_333;
wire [8:0] T_334;
wire [1:0] T_335;
wire [2:0] T_336;
wire [11:0] T_337;
wire [2:0] T_338;
wire [3:0] T_339;
wire [7:0] T_340;
wire [7:0] T_341;
wire [15:0] T_342;
wire [19:0] T_343;
wire [31:0] T_344;
wire T_350_0;
wire T_350_1;
wire T_350_2;
wire T_350_3;
wire T_352;
wire T_353;
wire T_354;
wire T_355;
wire [2:0] T_357;
wire [3:0] T_358;
wire [3:0] T_359;
wire [3:0] T_360;
wire [3:0] T_361;
wire T_364_0;
wire T_364_1;
wire T_364_2;
wire T_364_3;
wire T_366;
wire T_367;
wire T_368;
wire T_369;
wire T_370;
assign io_regs_cfg_read = T_344;
assign io_regs_countLo_read = {{1'd0}, T_203};
assign io_regs_countHi_read = 32'h0;
assign io_regs_s_read = s;
assign io_regs_cmp_0_read = cmp_0;
assign io_regs_cmp_1_read = cmp_1;
assign io_regs_cmp_2_read = cmp_2;
assign io_regs_cmp_3_read = cmp_3;
assign io_regs_feed_read = 32'h0;
assign io_regs_key_read = 32'h1;
assign io_ip_0 = T_350_0;
assign io_ip_1 = T_350_1;
assign io_ip_2 = T_350_2;
assign io_ip_3 = T_350_3;
assign io_gpio_0 = T_364_0;
assign io_gpio_1 = T_364_1;
assign io_gpio_2 = T_364_2;
assign io_gpio_3 = T_364_3;
assign T_178 = io_regs_cfg_write_bits[3:0];
assign GEN_0 = io_regs_cfg_write_valid ? T_178 : scale;
assign GEN_1 = io_regs_cmp_0_write_valid ? io_regs_cmp_0_write_bits : cmp_0;
assign GEN_2 = io_regs_cmp_1_write_valid ? io_regs_cmp_1_write_bits : cmp_1;
assign GEN_3 = io_regs_cmp_2_write_valid ? io_regs_cmp_2_write_bits : cmp_2;
assign GEN_4 = io_regs_cmp_3_write_valid ? io_regs_cmp_3_write_bits : cmp_3;
assign countEn = T_370;
assign GEN_18 = {{4'd0}, countEn};
assign T_197 = T_196 + GEN_18;
assign T_200 = T_197[5];
assign T_202 = T_199 + 26'h1;
assign GEN_5 = T_200 ? T_202 : {{1'd0}, T_199};
assign T_203 = {T_199,T_196};
assign T_207 = {1'h0,io_regs_countLo_write_bits};
assign T_208 = T_207[32:5];
assign GEN_6 = io_regs_countLo_write_valid ? T_207 : {{27'd0}, T_197};
assign GEN_7 = io_regs_countLo_write_valid ? T_208 : {{1'd0}, GEN_5};
assign T_209 = T_203 >> scale;
assign s = T_209[15:0];
assign T_210 = s[15];
assign T_211 = io_regs_cfg_write_bits[19:16];
assign GEN_8 = io_regs_cfg_write_valid ? T_211 : center;
assign T_215 = center[0];
assign T_216 = T_210 & T_215;
assign T_217 = ~ s;
assign T_218 = T_216 ? T_217 : s;
assign elapsed_0 = T_218 >= cmp_0;
assign T_220 = center[1];
assign T_221 = T_210 & T_220;
assign T_223 = T_221 ? T_217 : s;
assign elapsed_1 = T_223 >= cmp_1;
assign T_225 = center[2];
assign T_226 = T_210 & T_225;
assign T_228 = T_226 ? T_217 : s;
assign elapsed_2 = T_228 >= cmp_2;
assign T_230 = center[3];
assign T_231 = T_210 & T_230;
assign T_233 = T_231 ? T_217 : s;
assign elapsed_3 = T_233 >= cmp_3;
assign GEN_19 = {{1'd0}, T_196};
assign T_234 = GEN_19 ^ T_197;
assign T_235 = T_234[5:1];
assign GEN_20 = {{1'd0}, T_199};
assign T_239 = GEN_20 ^ T_202;
assign T_241 = T_200 ? T_239 : 27'h0;
assign T_242 = T_241[26:1];
assign T_243 = {T_242,T_235};
assign GEN_21 = {{1'd0}, scale};
assign T_245 = GEN_21 + 5'h10;
assign T_246 = T_245[4:0];
assign T_247 = T_243 >> T_246;
assign feed = T_247[0];
assign T_248 = io_regs_cfg_write_bits[9];
assign GEN_9 = io_regs_cfg_write_valid ? T_248 : zerocmp;
assign T_252 = zerocmp & elapsed_0;
assign countReset = feed | T_252;
assign GEN_10 = countReset ? 33'h0 : GEN_6;
assign GEN_11 = countReset ? 28'h0 : GEN_7;
assign T_255 = io_regs_cfg_write_bits[10];
assign GEN_12 = io_regs_cfg_write_valid ? T_255 : T_259;
assign T_261 = countReset == 1'h0;
assign T_262 = T_259 & T_261;
assign T_263 = io_regs_cfg_write_bits[8];
assign GEN_13 = io_regs_cfg_write_valid ? T_263 : T_267;
assign T_268 = T_262 | T_267;
assign T_282 = {T_221,T_216};
assign T_283 = {T_231,T_226};
assign T_284 = {T_283,T_282};
assign T_286 = {elapsed_1,elapsed_0};
assign T_287 = {elapsed_3,elapsed_2};
assign T_288 = {T_287,T_286};
assign T_289 = T_284 & T_288;
assign T_290 = ~ T_284;
assign T_297 = T_269 ? 4'hf : 4'h0;
assign T_298 = T_297 & ip;
assign T_299 = T_288 | T_298;
assign T_300 = T_290 & T_299;
assign T_301 = T_289 | T_300;
assign T_304 = io_regs_cfg_write_bits[31:28];
assign GEN_14 = io_regs_cfg_write_valid ? T_304 : T_301;
assign T_305 = io_regs_cfg_write_bits[27:24];
assign GEN_15 = io_regs_cfg_write_valid ? T_305 : gang;
assign T_316 = io_regs_cfg_write_bits[13];
assign T_319 = T_316 & T_261;
assign T_323 = io_regs_cfg_write_valid | countReset;
assign GEN_16 = T_323 ? T_319 : oneShot;
assign T_325 = io_regs_cfg_write_bits[12];
assign GEN_17 = io_regs_cfg_write_valid ? T_325 : countAlways;
assign T_333 = {T_267,4'h0};
assign T_334 = {T_333,scale};
assign T_335 = {1'h0,T_259};
assign T_336 = {T_335,zerocmp};
assign T_337 = {T_336,T_334};
assign T_338 = {2'h0,oneShot};
assign T_339 = {T_338,countAlways};
assign T_340 = {4'h0,center};
assign T_341 = {ip,gang};
assign T_342 = {T_341,T_340};
assign T_343 = {T_342,T_339};
assign T_344 = {T_343,T_337};
assign T_350_0 = T_352;
assign T_350_1 = T_353;
assign T_350_2 = T_354;
assign T_350_3 = T_355;
assign T_352 = ip[0];
assign T_353 = ip[1];
assign T_354 = ip[2];
assign T_355 = ip[3];
assign T_357 = ip[3:1];
assign T_358 = {T_352,T_357};
assign T_359 = gang & T_358;
assign T_360 = ~ T_359;
assign T_361 = ip & T_360;
assign T_364_0 = T_366;
assign T_364_1 = T_367;
assign T_364_2 = T_368;
assign T_364_3 = T_369;
assign T_366 = T_361[0];
assign T_367 = T_361[1];
assign T_368 = T_361[2];
assign T_369 = T_361[3];
assign T_370 = countAlways | oneShot;
always @(posedge clock or posedge reset)
if(reset) begin
scale <= 4'b0;
cmp_0 <= 16'b0;
cmp_1 <= 16'b0;
cmp_2 <= 16'b0;
cmp_3 <= 16'b0;
T_196 <= 5'b0;
T_199 <= 26'b0;
center <= 4'b0;
zerocmp <= 1'b0;
T_259 <= 1'b0;
T_267 <= 1'b0;
T_269 <= 1'b0;
ip <= 4'b0;
gang <= 4'b0;
end
else begin
if (io_regs_cfg_write_valid) begin
scale <= T_178;
end
if (io_regs_cmp_0_write_valid) begin
cmp_0 <= io_regs_cmp_0_write_bits;
end
if (io_regs_cmp_1_write_valid) begin
cmp_1 <= io_regs_cmp_1_write_bits;
end
if (io_regs_cmp_2_write_valid) begin
cmp_2 <= io_regs_cmp_2_write_bits;
end
if (io_regs_cmp_3_write_valid) begin
cmp_3 <= io_regs_cmp_3_write_bits;
end
T_196 <= GEN_10[4:0];
T_199 <= GEN_11[25:0];
if (io_regs_cfg_write_valid) begin
center <= T_211;
end
if (io_regs_cfg_write_valid) begin
zerocmp <= T_248;
end
if (io_regs_cfg_write_valid) begin
T_259 <= T_255;
end
if (io_regs_cfg_write_valid) begin
T_267 <= T_263;
end
T_269 <= T_268;
if (io_regs_cfg_write_valid) begin
ip <= T_304;
end else begin
ip <= T_301;
end
if (io_regs_cfg_write_valid) begin
gang <= T_305;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
oneShot <= 1'h0;
end else begin
if (T_323) begin
oneShot <= T_319;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
countAlways <= 1'h0;
end else begin
if (io_regs_cfg_write_valid) begin
countAlways <= T_325;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O221A_FUNCTIONAL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311A_TB_V
`define SKY130_FD_SC_HS__O311A_TB_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o311a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 A3 = 1'b0;
#360 B1 = 1'b0;
#380 C1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 C1 = 1'b1;
#500 B1 = 1'b1;
#520 A3 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 C1 = 1'bx;
#640 B1 = 1'bx;
#660 A3 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__o311a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311A_TB_V
|
module PHYctrl_Slave_MAX10 (
input CLOCK_50_MAX10,
input CLOCK_25_MAX10,
input [3: 0] USER_PB,
output [4: 0] USER_LED,
output [1:0] PMODA_IO,
output ENET_MDC,
inout ENET_MDIO,
// Ethernet A
output ENET0_RESET_N,
output ENET0_GTX_CLK,
input ENET0_TX_CLK,
input ENET0_RX_CLK,
input [3: 0] ENET0_RX_DATA,
input ENET0_RX_DV,
input ENET0_LED_LINK100,
output [3: 0] ENET0_TX_DATA,
output ENET0_TX_EN,
output ENET0_TX_ER,
// Ethernet 1
output ENET1_GTX_CLK,
output ENET1_RESET_N,
input ENET1_TX_CLK,
input ENET1_RX_CLK,
input [3: 0] ENET1_RX_DATA,
input ENET1_RX_DV,
input ENET1_LED_LINK100,
output [3: 0] ENET1_TX_DATA,
output ENET1_TX_EN
);
wire rst;
assign rst = ~USER_PB[3];
assign ENET0_RESET_N = USER_PB[3];
assign ENET1_RESET_N = USER_PB[3];
wire clk_tx0_25;
wire clk_tx1_25;
wire clk_rx0_25;
wire clk_rx1_25;
assign clk_tx0_25 = ENET0_TX_CLK;
assign clk_tx1_25 = ENET1_TX_CLK;
assign clk_rx0_25 = ENET0_RX_CLK;
assign clk_rx1_25 = ENET1_RX_CLK;
/////////////////////////////////////// transmitter mac /////////////////////////////
wire [7:0] TxRamAddr;
wire [7:0] TxData;
//dual port ram for tx, a port for write from higher level, b port for read from txmac
tx_dual_port_ram_8bit tx_dual_port_ram_8bit_ins(
//.data_a,
.data_b(TxData),
//.addr_a,
.addr_b(TxRamAddr),
//.we_a,
.we_b(1'b0),
.clk(clk_rx1_25),
//.q_a,
.q_b(TxData)
);
//////////////////////////////////// receiver mac /////////////////////////////
wire [7:0]RxRamAddr;
wire [7:0]RxData;
wire RxValid;
wire [7:0]readFromRxRam8bit;
//dual port ram for rx, a port for write from rxmac, b port for read from higher level
rx_dual_port_ram_8bit rx_dual_port_ram_8bit_ins(
.data_a(RxData),
//.data_b,
.addr_a(RxRamAddr),
//.addr_b(SW[7:2]),
.we_a(RxValid),
.we_b(1'b0),
.clk(clk_rx1_25),
//.q_a,
.q_b(readFromRxRam8bit)
);
reg [5:0]rx_ram_addr1;
always @ (posedge clk_rx1_25 )
begin
if (rst) begin
rx_ram_addr1 <= 6'b0;
end else if (ENET1_RX_DV)begin
if (rx_ram_addr1 < 6'b111110 )
rx_ram_addr1 <= rx_ram_addr1 + 1'b1;
end
end
wire [3:0]readFromRxRam;
rx_data_ram rx_data_ram_ins(
.data_a(ENET1_RX_DATA),
//.data_b,
.addr_a(rx_ram_addr1),
// .addr_b(SW[7:2]),
.we_a(ENET1_RX_DV),
.we_b(1'b0),
.clk(clk_rx1_25),
//.q_a,
.q_b(readFromRxRam)
);
// generatioon of 100MHz clock
wire Clk_100MHz;
pll_25to100MHz delay_measure_clock
(
.inclk0(CLOCK_25_MAX10),
.areset(rst),
.c0(Clk_100MHz)
);
wire [7:0]LastSlaveIDPlus1;
wire [7:0]SlaveID;
wire [3:0]readSlaveID;
wire [7:0]LogicDelay;
wire [7:0]AveSlaveDelay;
fb_slave_mac fb_slave_mac_ins
(
.MRxClk(clk_rx1_25),
.MTxClk(clk_tx0_25),
.Clk_100MHz(Clk_100MHz),
.MRxDV(ENET1_RX_DV),
.MRxD(ENET1_RX_DATA),
.Reset(rst),
.TxData(TxData),
.inSlaveID(8'd1),
.inLastSlaveIDPlus1(8'd2),
.MTxD_sync2(ENET0_TX_DATA),
.MTxEn_sync2(ENET0_TX_EN),
.RxData(RxData),
.RxValid(RxValid),
.RxRamAddr(RxRamAddr),
.TxRamAddr(TxRamAddr),
.SynchSignal(PMODA_IO[0]),
.SlaveID(SlaveID),
.LastSlaveIDPlus1(LastSlaveIDPlus1),
.LogicDelay(LogicDelay),
.AveSlaveDelay(AveSlaveDelay)
/*.FrmCrcError
.CrcError,
.StateIdle,
.StateFFS,
.StatePreamble,
.StateNumb,
.StateSlaveID,
.StateDist,
.StateDelay,
.StateDelayMeas,
.StateDelayDist,
.StateData,
.StateSlaveData,
.StateSlaveCrc,
.StateFrmCrc*/
);
assign readSlaveID = USER_PB[1]?LastSlaveIDPlus1[1:0]:SlaveID[1:0];
assign USER_LED[1:0] = readSlaveID[1:0];
////////////////////////////////// MI INTERFACE FOR PORT 0 ///////////////////////////////
wire [31:0] command0;
wire [15:0] command_and0;
wire [3: 0] comm_addr0;
wire [15:0] readData0;
wire [15:0] readDataRam0;
phyInital phyInital_ins0 (
.clk(CLOCK_50_MAX10),
.reset(~USER_PB[0]),
.mdc(ENET_MDC),
.md_inout(ENET_MDIO),
.command(command0),
.command_and(command_and0),
.comm_addr(comm_addr0),
//.ram_read_addr(USER_PB[3:0]),
.iniStart(1'b1),
//.iniEnd(USER_LED[0]),
//.stateout(LEDR[12:0]),
.readDataoutRam(readDataRam0)
//.busy(USER_LED[1]),
//.WCtrlDataStartout(USER_LED[2])
);
phyIniCommand0 pyhIniCommands (
.clk(CLOCK_50_MAX10),
.q(command0),
.addr(comm_addr0)
);
phyIniCommand0_and pyhIniCommands_and (
.clk(CLOCK_50_MAX10),
.q(command_and0),
.addr(comm_addr0)
);
assign USER_LED[3] = ENET0_LED_LINK100;
assign USER_LED[4] = ENET1_LED_LINK100;
///////////////////////////////////////////////////end of MI INTERFACE FOR PORT 1 ///////////////////////////////
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2B_1_V
`define SKY130_FD_SC_HDLL__AND2B_1_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2b_1 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2b_1 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2B_1_V
|
(*
Copyright © 2006-2008 Russell O’Connor
Permission is hereby granted, free of charge, to any person obtaining a copy of
this proof and associated documentation files (the "Proof"), to deal in
the Proof without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
the Proof, and to permit persons to whom the Proof is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Proof.
THE PROOF IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE PROOF OR THE USE OR OTHER DEALINGS IN THE PROOF.
*)
Require Export RSetoid.
Require Import Relation_Definitions.
Require Export Qpossec.
Require Import COrdFields2.
Require Import Qordfield.
Require Import QMinMax.
Require Import List.
Require Import CornTac.
Require Import stdlib_omissions.Q.
Require QnnInf.
Import QnnInf.notations.
Open Local Scope Q_scope.
Set Implicit Arguments.
(**
* Metric Space
In this version, a metric space over a setoid X is characterized by a
ball relation B where B e x y is intended to mean that the two points
x and y are within e of each other ( d(x,y)<=e ). This is characterized
by the axioms given in the record structure below.
*)
Record is_MetricSpace (X : RSetoid) (B: Qpos -> relation X) : Prop :=
{ msp_refl: forall e, Reflexive (B e)
; msp_sym: forall e, Symmetric (B e)
; msp_triangle: forall e1 e2 a b c, B e1 a b -> B e2 b c -> B (e1 + e2)%Qpos a c
; msp_closed: forall e a b, (forall d, B (e+d)%Qpos a b) -> B e a b
; msp_eq: forall a b, (forall e, B e a b) -> st_eq a b
}.
Record MetricSpace : Type :=
{ msp_is_setoid :> RSetoid
; ball : Qpos -> msp_is_setoid -> msp_is_setoid -> Prop
; ball_wd : forall (e1 e2:Qpos), (QposEq e1 e2) ->
forall x1 x2, (st_eq x1 x2) ->
forall y1 y2, (st_eq y1 y2) ->
(ball e1 x1 y1 <-> ball e2 x2 y2)
; msp : is_MetricSpace msp_is_setoid ball
}.
(* begin hide *)
Implicit Arguments ball [m].
(*This is intended to be used as a ``type cast'' that Coq won't randomly make disappear.
It is useful when defining setoid rewrite lemmas for st_eq.*)
Definition ms_id (m:MetricSpace) (x:m) : m := x.
Implicit Arguments ms_id [m].
Add Parametric Morphism (m:MetricSpace) : (@ball m) with signature QposEq ==> (@st_eq m) ==> (@st_eq m) ==> iff as ball_compat.
Proof.
exact (@ball_wd m).
Qed.
(* end hide *)
Section Metric_Space.
(*
** Ball lemmas
*)
Variable X : MetricSpace.
(** These lemmas give direct access to the ball axioms of a metric space
*)
Lemma ball_refl : forall e (a:X), ball e a a.
Proof.
apply (msp_refl (msp X)).
Qed.
Lemma ball_sym : forall e (a b:X), ball e a b -> ball e b a.
Proof.
apply (msp_sym (msp X)).
Qed.
Lemma ball_triangle : forall e1 e2 (a b c:X), ball e1 a b -> ball e2 b c -> ball (e1+e2) a c.
Proof.
apply (msp_triangle (msp X)).
Qed.
Lemma ball_closed : forall e (a b:X), (forall d, ball (e+d) a b) -> ball e a b.
Proof.
apply (msp_closed (msp X)).
Qed.
Lemma ball_eq : forall (a b:X), (forall e, ball e a b) -> st_eq a b.
Proof.
apply (msp_eq (msp X)).
Qed.
Lemma ball_eq_iff : forall (a b:X), (forall e, ball e a b) <-> st_eq a b.
Proof.
split.
apply ball_eq.
intros H e.
rewrite -> H.
apply ball_refl.
Qed.
(** The ball constraint on a and b can always be weakened. Here are
two forms of the weakening lemma.
*)
Lemma ball_weak : forall e d (a b:X), ball e a b -> ball (e+d) a b.
Proof.
intros e d a b B1.
eapply ball_triangle.
apply B1.
apply ball_refl.
Qed.
Hint Resolve ball_refl ball_triangle ball_weak : metric.
Lemma ball_weak_le : forall (e d:Qpos) (a b:X), e<=d -> ball e a b -> ball d a b.
Proof.
intros e d a b Hed B1.
destruct (Qle_lt_or_eq _ _ Hed).
destruct (Qpos_lt_plus H) as [c Hc].
rewrite <- Q_Qpos_plus in Hc.
change (QposEq d (e+c)) in Hc.
rewrite -> Hc; clear - B1.
auto with *.
change (QposEq e d) in H.
rewrite <- H.
assumption.
Qed.
End Metric_Space.
(* begin hide *)
Hint Resolve ball_refl ball_sym ball_triangle ball_weak : metric.
(* end hide *)
(** We can easily generalize ball to take the ratio from Q or QnnInf: *)
Section gball.
Context {m: MetricSpace}.
Definition gball (q: Q) (x y: m): Prop :=
match Qdec_sign q with
| inl (inl _) => False (* q < 0, silly *)
| inl (inr p) => ball (exist (Qlt 0) q p) x y (* 0 < q, normal *)
| inr _ => x[=]y (* q == 0 *)
end.
(* Program can make this definition slightly cleaner, but the resulting term is much nastier... *)
Definition gball_ex (e: QnnInf): relation m :=
match e with
| QnnInf.Finite e' => gball (proj1_sig e')
| QnnInf.Infinite => fun _ _ => True
end.
Lemma ball_gball (q: Qpos) (x y: m): gball q x y <-> ball q x y.
Proof with auto.
unfold gball.
revert q x y.
intros [q p] ??. simpl.
destruct Qdec_sign as [[A | A] | A].
exfalso.
apply (Qlt_is_antisymmetric_unfolded q 0)...
apply ball_wd; reflexivity.
exfalso.
apply (Qlt_irrefl 0).
rewrite <- A at 2...
Qed.
Global Instance gball_Proper: Proper (Qeq ==> @st_eq m ==> @st_eq m ==> iff) gball.
Proof with auto.
intros x y E a b F v w G.
unfold gball.
destruct Qdec_sign as [[A | B] | C];
destruct Qdec_sign as [[P | Q] | R].
reflexivity.
exfalso. apply (Qlt_irrefl 0). apply Qlt_trans with x... rewrite E...
exfalso. apply (Qlt_irrefl 0). rewrite <- R at 1. rewrite <- E...
exfalso. apply (Qlt_irrefl 0). apply Qlt_trans with x... rewrite E...
apply ball_wd...
exfalso. apply (Qlt_irrefl 0). rewrite <- R at 2. rewrite <- E...
exfalso. apply (Qlt_irrefl 0). rewrite <- C at 1. rewrite E...
exfalso. apply (Qlt_irrefl 0). rewrite <- C at 2. rewrite E...
rewrite F, G. reflexivity.
Qed.
Global Instance gball_ex_Proper: Proper (QnnInf.eq ==> @st_eq m ==> @st_eq m ==> iff) gball_ex.
Proof.
repeat intro.
destruct x, y. intuition. intuition. intuition.
apply gball_Proper; assumption.
Qed.
Global Instance gball_refl (e: Q): 0 <= e -> Reflexive (gball e).
Proof with auto.
repeat intro.
unfold gball.
destruct Qdec_sign as [[?|?]|?].
apply (Qlt_not_le e 0)...
apply ball_refl.
reflexivity.
Qed.
Global Instance gball_ex_refl (e: QnnInf): Reflexive (gball_ex e).
Proof.
destruct e. intuition.
apply gball_refl, proj2_sig.
Qed.
Global Instance gball_sym (e: Q): Symmetric (gball e).
Proof with auto.
unfold gball. repeat intro.
destruct Qdec_sign as [[?|?]|?]...
apply ball_sym...
symmetry...
Qed.
Lemma gball_ex_sym (e: QnnInf): Symmetric (gball_ex e).
Proof. destruct e. auto. simpl. apply gball_sym. Qed.
Lemma gball_triangle (e1 e2: Q) (a b c: m):
gball e1 a b -> gball e2 b c -> gball (e1 + e2) a c.
Proof with auto with *.
unfold gball.
intros.
destruct (Qdec_sign e1) as [[A|B]|C].
exfalso...
destruct (Qdec_sign e2) as [[?|?]|?].
intuition.
destruct (Qdec_sign (e1 + e2)) as [[?|?]|?].
assert (0 < e1 + e2).
apply Qplus_lt_le_0_compat...
revert H1. apply Qle_not_lt...
simpl.
setoid_replace (exist (Qlt 0) (e1 + e2) q0) with (exist (Qlt 0) e1 B + exist (Qlt 0) e2 q)%Qpos by reflexivity.
apply ball_triangle with b...
exfalso.
assert (0 < e1 + e2).
apply Qplus_lt_le_0_compat...
revert H1. rewrite q0.
apply Qlt_irrefl.
destruct (Qdec_sign (e1 + e2)) as [[?|?]|?].
revert q0. rewrite q. rewrite Qplus_0_r. apply Qle_not_lt...
apply ball_gball. simpl. rewrite q, Qplus_0_r. rewrite <- H0. apply ball_gball in H. assumption.
exfalso.
revert q0. rewrite q. rewrite Qplus_0_r. intro. clear H. revert B. rewrite H1. apply Qlt_irrefl.
destruct (Qdec_sign e2) as [[?|?]|?].
intuition.
apply ball_gball in H0.
simpl in H0.
destruct (Qdec_sign (e1 + e2)) as [[?|?]|?].
revert q0. rewrite C. rewrite Qplus_0_l. apply Qle_not_lt...
apply ball_gball. simpl.
rewrite C, Qplus_0_l, H...
exfalso. revert q0. rewrite C, Qplus_0_l. intro. clear H0. revert q. rewrite H1. apply Qlt_irrefl.
destruct (Qdec_sign (e1 + e2)) as [[?|?]|?].
revert q0. rewrite C, q, Qplus_0_l. apply Qlt_irrefl.
exfalso. revert q0. rewrite C, q, Qplus_0_l. apply Qlt_irrefl.
transitivity b...
Qed. (* TODO: THE HORROR!! *)
Lemma gball_ex_triangle (e1 e2: QnnInf) (a b c: m):
gball_ex e1 a b -> gball_ex e2 b c -> gball_ex (e1 + e2)%QnnInf a c.
Proof. destruct e1, e2; auto. simpl. apply gball_triangle. Qed.
Lemma gball_0 (x y: m): gball 0 x y <-> x [=] y.
Proof. reflexivity. Qed.
Lemma gball_weak_le (q q': Q): q <= q' -> forall x y, gball q x y -> gball q' x y.
Proof with auto.
revert q q'.
intros ?? E ?? F.
unfold gball in F.
destruct Qdec_sign as [[A | B] | C].
intuition.
assert (0 < q') as q'p. apply Qlt_le_trans with q...
apply (ball_gball (exist _ q' q'p)).
apply ball_weak_le with (exist _ q B)...
rewrite F.
apply gball_refl.
rewrite <- C...
Qed.
End gball.
|
`timescale 1ns / 1ps
//AND Gate
module andgate(a, b, out);
input a, b;
output out;
assign out = a & b;
endmodule
//Testbench definition for AND Gate
module andgate_tb;
wire t_out;
reg t_a, t_b;
andgate my_gate( .a(t_a), .b(t_b), .out(t_out) );
initial
begin
$monitor(t_a, t_b, t_out);
t_a = 1'b0;
t_b = 1'b0;
#5
t_a = 1'b0;
t_b = 1'b1;
#5
t_a = 1'b1;
t_b = 1'b0;
#5
t_a = 1'b1;
t_b = 1'b1;
end
endmodule
// AND Gate 16
module andgate16(a, b, out);
input [15:0] a, b;
output [15:0] out;
assign out = a & b;
endmodule
//Testbench definition for AND Gate
module andgate16_tb;
wire [15:0] t_out;
reg [15:0] t_a, t_b;
andgate16 my_gate( .a(t_a), .b(t_b), .out(t_out) );
initial
begin
$monitor(t_a, t_b, t_out);
t_a = 16'b0;
t_b = 16'b0;
#5
t_a = 16'b0;
t_b = 16'b1111111111111111;
#5
t_a = 16'b1111111111111111;
t_b = 16'b0;
#5
t_a = 16'b1111111111111111;
t_b = 16'b1111111111111111;
end
endmodule
// Mux8Way16
module mux8way16(a, b, c, d, e ,f, g, h, sel, out);
input [15:0] a, b, c, d, e, f, g, h;
input [2:0] sel;
output reg [15:0] out;
always @(sel)
begin
case (sel)
3'b000 : out = a;
3'b001 : out = b;
3'b010 : out = c;
3'b011 : out = d;
3'b100 : out = e;
3'b101 : out = f;
3'b110 : out = g;
3'b111 : out = h;
default out = 3'b000;
endcase
end
endmodule
//Testbench definition for Mux8Way16
module mux8way16_tb;
wire [15:0] t_out;
reg [15:0] t_a, t_b, t_c, t_d, t_e, t_f, t_g, t_h;
reg [2:0] t_sel;
mux8way16 my_gate( .a(t_a), .b(t_b), .c(t_c), .d(t_d), .e(t_e), .f(t_f), .g(t_g), .h(t_h), .sel(t_sel), .out(t_out) );
initial
begin
$monitor(t_a, t_b, t_c, t_d, t_e, t_f, t_g, t_h, t_out);
t_a = 16'b0000000000000000;
t_b = 16'b0000000000000011;
t_c = 16'b0000000000001100;
t_d = 16'b0000000000110000;
t_e = 16'b0000000011000000;
t_f = 16'b0000001100000000;
t_g = 16'b0000110000000000;
t_h = 16'b0011000000000000;
t_sel = 3'b000;
#5
t_sel = 3'b000;
#5
t_sel = 3'b001;
#5
t_sel = 3'b010;
#5
t_sel = 3'b011;
#5
t_sel = 3'b010;
#5
t_sel = 3'b011;
#5
t_sel = 3'b100;
#5
t_sel = 3'b101;
#5
t_sel = 3'b111;
end
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.